3a4bcfca2f
1. add cvitek folders to u-boot-2021.10 2. add cv183x/cv182x part 3. add cv181x/cv180x part Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
187 lines
5.1 KiB
C
187 lines
5.1 KiB
C
#ifndef __CV180X_REG_H__
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#define __CV180X_REG_H__
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#define TOP_BASE 0x03000000
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#define PINMUX_BASE (TOP_BASE + 0x1000)
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#define WATCHDOG_BASE (TOP_BASE + 0x00010000)
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#define RTC_BASE 0x05026000
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/*
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* RTC info registers
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*/
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#define RTC_INFO0 (RTC_BASE + 0x1C)
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/*
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* General purpose registers
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*/
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#define GP_REG0 (TOP_BASE + 0x80)
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#define GP_REG1 (TOP_BASE + 0x84)
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#define GP_REG2 (TOP_BASE + 0x88
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#define GP_REG3 (TOP_BASE + 0x8C)
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#define GP_REG4 (TOP_BASE + 0x90)
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#define GP_REG5 (TOP_BASE + 0x94)
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#define GP_REG6 (TOP_BASE + 0x98)
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#define GP_REG7 (TOP_BASE + 0x9C)
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#define GP_REG8 (TOP_BASE + 0xA0)
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#define GP_REG9 (TOP_BASE + 0xA4)
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#define GP_REG10 (TOP_BASE + 0xA8)
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/*
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* Pinmux definitions
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*/
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#define PINMUX_UART0 0
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#define PINMUX_UART1 1
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#define PINMUX_UART2 2
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#define PINMUX_UART3 3
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#define PINMUX_UART3_2 4
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#define PINMUX_I2C0 5
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#define PINMUX_I2C1 6
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#define PINMUX_I2C2 7
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#define PINMUX_I2C3 8
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#define PINMUX_I2C4 9
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#define PINMUX_I2C4_2 10
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#define PINMUX_SPI0 11
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#define PINMUX_SPI1 12
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#define PINMUX_SPI2 13
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#define PINMUX_SPI2_2 14
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#define PINMUX_SPI3 15
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#define PINMUX_SPI3_2 16
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#define PINMUX_I2S0 17
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#define PINMUX_I2S1 18
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#define PINMUX_I2S2 19
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#define PINMUX_I2S3 20
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#define PINMUX_USBID 21
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#define PINMUX_SDIO0 22
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#define PINMUX_SDIO1 23
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#define PINMUX_ND 24
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#define PINMUX_EMMC 25
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#define PINMUX_SPI_NOR 26
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#define PINMUX_SPI_NAND 27
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#define PINMUX_CAM0 28
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#define PINMUX_CAM1 29
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#define PINMUX_PCM0 30
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#define PINMUX_PCM1 31
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#define PINMUX_CSI0 32
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#define PINMUX_CSI1 33
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#define PINMUX_CSI2 34
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#define PINMUX_DSI 35
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#define PINMUX_VI0 36
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#define PINMUX_VO 37
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#define PINMUX_RMII1 38
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#define PINMUX_EPHY_LED 39
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#define PINMUX_I80 40
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#define PINMUX_LVDS 41
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#define PINMUX_USB 42
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#define PINMUX_USB_VBUS_DET (PINMUX_BASE + 0x108)
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#define REG_TOP_USB_ECO (TOP_BASE + 0xB4)
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#define BIT_TOP_USB_ECO_RX_FLUSH 0x80
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/* rst */
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#define REG_TOP_SOFT_RST 0x3000
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#define BIT_TOP_SOFT_RST_USB BIT(11)
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#define BIT_TOP_SOFT_RST_SDIO BIT(14)
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#define BIT_TOP_SOFT_RST_NAND BIT(12)
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#define REG_TOP_USB_CTRSTS (TOP_BASE + 0x38)
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#define REG_TOP_CONF_INFO (TOP_BASE + 0x4)
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#define BIT_TOP_CONF_INFO_VBUS BIT(9)
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#define REG_TOP_USB_PHY_CTRL (TOP_BASE + 0x48)
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#define BIT_TOP_USB_PHY_CTRL_EXTVBUS BIT(0)
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#define USB_PHY_ID_OVERRIDE_ENABLE BIT(6)
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#define USB_PHY_ID_VALUE BIT(7)
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#define REG_TOP_DDR_ADDR_MODE (TOP_BASE + 0x64)
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/* irq */
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#define IRQ_LEVEL 0
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#define IRQ_EDGE 3
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/* usb */
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#define USB_BASE 0x04340000
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/* ethernet phy */
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#define ETH_PHY_BASE 0x03009000
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#define ETH_PHY_INIT_MASK 0xFFFFFFF9
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#define ETH_PHY_SHUTDOWN BIT(1)
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#define ETH_PHY_POWERUP 0xFFFFFFFD
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#define ETH_PHY_RESET 0xFFFFFFFB
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#define ETH_PHY_RESET_N BIT(2)
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#define ETH_PHY_LED_LOW_ACTIVE BIT(3)
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/* watchdog */
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#define CONFIG_DW_WDT_BASE WATCHDOG_BASE
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#define CONFIG_DW_WDT_CLOCK_KHZ 25000
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#define DW_WDT_CR 0x00
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#define DW_WDT_TORR 0x04
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#define DW_WDT_CRR 0x0C
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#define DW_WDT_CR_EN_OFFSET 0x00
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#define DW_WDT_CR_RMOD_OFFSET 0x01
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#define DW_WDT_CR_RMOD_VAL 0x00
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#define DW_WDT_CRR_RESTART_VAL 0x76
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/* SDIO Wifi */
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#define WIFI_CHIP_EN_BGA BIT(18)
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#define WIFI_CHIP_EN_QFN BIT(2)
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/* RTC */
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#define RTC_SYS_BASE 0x05000000
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#define RTC_MACRO_BASE (RTC_SYS_BASE + 0x00026400)
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#define RTC_MACRO_DA_SOC_READY 0x8C
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#define RTC_MACRO_RO_T 0xA8
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#define RTC_CORE_SRAM_BASE (RTC_SYS_BASE + 0x00026800)
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#define RTC_CORE_SRAM_SIZE 0x0800 // 2KB
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#define REG_RTC_CTRL_BASE (RTC_SYS_BASE + 0x00025000)
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#define RTC_CTRL0_UNLOCKKEY 0x4
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#define RTC_CTRL0 0x8
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#define RTC_CTRL0_STATUS0 0xC
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#define RTCSYS_RST_CTRL 0x18
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#define REG_RTC_BASE (RTC_SYS_BASE + 0x00026000)
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#define RTC_EN_PWR_WAKEUP 0xBC
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#define RTC_EN_SHDN_REQ 0xC0
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#define RTC_EN_PWR_CYC_REQ 0xC8
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#define RTC_EN_WARM_RST_REQ 0xCC
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#define RTC_EN_WDT_RST_REQ 0xE0
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#define RTC_EN_SUSPEND_REQ 0xE4
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#define RTC_PG_REG 0xF0
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#define RTC_ST_ON_REASON 0xF8
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#define REG_RTC_ST_ON_REASON (REG_RTC_BASE + RTC_ST_ON_REASON)
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#define RTCSYS_F32KLESS_BASE (RTC_SYS_BASE + 0x0002A000)
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#define RTC_INTERNAL_32K 0
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#define RTC_EXTERNAL_32K 1
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/* eFuse */
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#define EFUSE_BASE (TOP_BASE + 0x00050000)
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/* AXI SRAM */
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#define AXI_SRAM_BASE 0x0E000000
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#define AXI_SRAM_SIZE 0x40
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#define EFUSE_SW_INFO_ADDR (AXI_SRAM_BASE)
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#define EFUSE_SW_INFO_SIZE 4
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#define BOOT_SOURCE_FLAG_ADDR (EFUSE_SW_INFO_ADDR + EFUSE_SW_INFO_SIZE)
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#define BOOT_SOURCE_FLAG_SIZE 4
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#define MAGIC_NUM_USB_DL 0x4D474E31 // MGN1
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#define MAGIC_NUM_SD_DL 0x4D474E32 // MGN2
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#define BOOT_LOG_LEN_ADDR (BOOT_SOURCE_FLAG_ADDR + BOOT_SOURCE_FLAG_SIZE) // 0x0E000008
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#define BOOT_LOG_LEN_SIZE 4
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#define TIME_RECORDS_ADDR (AXI_SRAM_BASE + 0x10) // 0x0E000010
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/* from fsbl/plat/cv180x/include/platform_def.h struct _time_records { ... } */
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#define TIME_RECORDS_FIELD_UBOOT_START (TIME_RECORDS_ADDR + 0x10)
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#define TIME_RECORDS_FIELD_BOOTCMD_START (TIME_RECORDS_ADDR + 0x12)
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#define TIME_RECORDS_FIELD_DECOMPRESS_KERNEL_START (TIME_RECORDS_ADDR + 0x14)
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#define TIME_RECORDS_FIELD_KERNEL_START (TIME_RECORDS_ADDR + 0x16)
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#endif /* __CV180X_REG_H__ */
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