3a4bcfca2f
1. add cvitek folders to u-boot-2021.10 2. add cv183x/cv182x part 3. add cv181x/cv180x part Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
123 lines
4.1 KiB
C
123 lines
4.1 KiB
C
#ifndef _SDHCI_REG_H
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#define _SDHCI_REG_H
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#include "cv1835_reg.h"
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#define REG_TOP_SD_PWRSW_CTRL (0x1F4)
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#define REG_SDIO0_PAD_MASK (0xFFFFFFF3)
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#define REG_SDIO0_PAD_SHIFT (2)
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#define REG_SDIO0_PAD_CLR_MASK (0xC)
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#define REG_SDIO0_CD_PAD_REG (PINMUX_BASE + 0xC04)
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#define REG_SDIO0_CD_PAD_VALUE (1)
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#define REG_SDIO0_CD_PAD_RESET (1)
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#define REG_SDIO0_CLK_PAD_REG (PINMUX_BASE + 0xB04)
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#define REG_SDIO0_CLK_PAD_VALUE (2)
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#define REG_SDIO0_CLK_PAD_RESET (2)
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#define REG_SDIO0_CMD_PAD_REG (PINMUX_BASE + 0xB00)
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#define REG_SDIO0_CMD_PAD_VALUE (1)
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#define REG_SDIO0_CMD_PAD_RESET (2)
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#define REG_SDIO0_DAT0_PAD_REG (PINMUX_BASE + 0xB08)
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#define REG_SDIO0_DAT0_PAD_VALUE (1)
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#define REG_SDIO0_DAT0_PAD_RESET (2)
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#define REG_SDIO0_DAT1_PAD_REG (PINMUX_BASE + 0xB0C)
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#define REG_SDIO0_DAT1_PAD_VALUE (1)
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#define REG_SDIO0_DAT1_PAD_RESET (2)
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#define REG_SDIO0_DAT2_PAD_REG (PINMUX_BASE + 0xB10)
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#define REG_SDIO0_DAT2_PAD_VALUE (1)
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#define REG_SDIO0_DAT2_PAD_RESET (2)
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#define REG_SDIO0_DAT3_PAD_REG (PINMUX_BASE + 0xB14)
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#define REG_SDIO0_DAT3_PAD_VALUE (1)
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#define REG_SDIO0_DAT3_PAD_RESET (2)
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#define PAD_SDIO0_CD_REG (PINMUX_BASE + 0x04)
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#define PAD_SDIO0_PWR_EN_REG (PINMUX_BASE + 0x14)
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#define PAD_SDIO0_CLK_REG (PINMUX_BASE + 0x40)
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#define PAD_SDIO0_CMD_REG (PINMUX_BASE + 0x3C)
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#define PAD_SDIO0_D0_REG (PINMUX_BASE + 0x44)
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#define PAD_SDIO0_D1_REG (PINMUX_BASE + 0x48)
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#define PAD_SDIO0_D2_REG (PINMUX_BASE + 0x4C)
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#define PAD_SDIO0_D3_REG (PINMUX_BASE + 0x50)
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#define REG_SDIO1_PAD_MASK (0xFFFFFFF3)
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#define REG_SDIO1_PAD_SHIFT (2)
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#define REG_SDIO1_PAD_CLR_MASK (0xC)
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#define REG_SDIO1_CLK_PAD_REG (PINMUX_BASE + 0xA14)
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#define REG_SDIO1_CLK_PAD_VALUE (2)
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#define REG_SDIO1_CMD_PAD_REG (PINMUX_BASE + 0xA10)
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#define REG_SDIO1_CMD_PAD_VALUE (1)
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#define REG_SDIO1_DAT0_PAD_REG (PINMUX_BASE + 0xA0C)
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#define REG_SDIO1_DAT0_PAD_VALUE (1)
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#define REG_SDIO1_DAT2_PAD_REG (PINMUX_BASE + 0xA1C)
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#define REG_SDIO1_DAT2_PAD_VALUE (1)
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#define REG_SDIO1_DAT1_PAD_REG (PINMUX_BASE + 0xA20)
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#define REG_SDIO1_DAT1_PAD_VALUE (1)
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#define REG_SDIO1_DAT3_PAD_REG (PINMUX_BASE + 0xA24)
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#define REG_SDIO1_DAT3_PAD_VALUE (1)
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#define REG_EMMC_PAD_CLR_MASK (0xC)
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#define REG_EMMC_PAD_SHIFT (2)
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#define REG_EMMC_RSTN_PAD_REG (PINMUX_BASE + 0xC24)
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#define REG_EMMC_RSTN_PAD_VALUE (1)
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#define REG_EMMC_CLK_PAD_REG (PINMUX_BASE + 0xC20)
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#define REG_EMMC_CLK_PAD_VALUE (2)
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#define REG_EMMC_CMD_PAD_REG (PINMUX_BASE + 0xC28)
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#define REG_EMMC_CMD_PAD_VALUE (1)
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#define REG_EMMC_DAT0_PAD_REG (PINMUX_BASE + 0xC30)
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#define REG_EMMC_DAT0_PAD_VALUE (1)
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#define REG_EMMC_DAT1_PAD_REG (PINMUX_BASE + 0xC2C)
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#define REG_EMMC_DAT1_PAD_VALUE (1)
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#define REG_EMMC_DAT2_PAD_REG (PINMUX_BASE + 0xC34)
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#define REG_EMMC_DAT2_PAD_VALUE (1)
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#define REG_EMMC_DAT3_PAD_REG (PINMUX_BASE + 0xC38)
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#define REG_EMMC_DAT3_PAD_VALUE (1)
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#define SDHCI_RX_DELAY_LINE (SDHCI_PHY_R_OFFSET + 0x0C)
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#define REG_RX_SRC_SEL_MASK (0xFFCFFFFF) // 0x30c reg_rx_src_sel [21:20]
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#define REG_RX_SRC_SEL_CLK_TX_INV (0) // clk_tx_inv
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#define REG_RX_SRC_SEL_PAD_CLK (1) // pad_clk
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#define REG_RX_SRC_SEL_RES (2) // resvd
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#define REG_RX_SRC_SEL_CLK_TX (3) // clk_tx
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#define REG_RX_SRC_SEL_SHIFT (20) // 0x30c reg_rx_src_sel [21:20]
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#define SDHCI_TX_DELAY_LINE (SDHCI_PHY_R_OFFSET + 0x1C)
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#define REG_TX_SRC_SEL_MASK (0xFFFFF3FF) // 0x31c reg_tx_src_sel [11:10]
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#define REG_TX_SRC_SEL_CLK_TX_INV (0) // clk_tx_inv
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#define REG_TX_SRC_SEL_PAD_CLK (1) // pad_clk
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#define REG_TX_SRC_SEL_RES (2) // resvd
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#define REG_TX_SRC_SEL_CLK_TX (3) // clk_tx
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#define REG_TX_SRC_SEL_SHIFT (10) // 0x31c reg_tx_src_sel [11:10]
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#define MMC_MAX_CLOCK (375000000)
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#define MMC_MAX_CLOCK_DIV_VALUE (0x40009)
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#define CLOCK_BYPASS_SELECT_REGISTER (0x3002030)
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#define CVI_SDHCI_VENDOR_OFFSET 0x500
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#define CVI_SDHCI_VENDOR_MSHC_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x8)
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#define CVI_SDHCI_VENDOR_EMMC_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x2C)
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#define CVI_SDHCI_VENDOR_A_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x40)
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#define CVI_SDHCI_VENDOR_A_STAT_R (CVI_SDHCI_VENDOR_OFFSET + 0x44)
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#define MAX_TUNING_CMD_RETRY_COUNT 50
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#define TUNE_MAX_PHCODE 128
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#define TAP_WINDOW_THLD 20
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#endif
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