4f810186ab
1. update cv182x/cv183x configuration file 2. update cv181x/cv180x configuration file 3. update clk driver for cvitek 4. update dma driver for cvitek 5. update soc driver for cvitek 6. porting cvitek ion driver from kernel-4.19 7. compatible with riscv Change-Id: Icff9fafe0ebe7d6bab824bbadb952e08bdc66c19
60 lines
1.2 KiB
YAML
60 lines
1.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/cvitek,cv180x-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cvitek CV180X SoC Clock Controller
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maintainers:
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- Fisher Cheng <fisher.cheng@cvitek.com>
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description: |
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The Cvitek CV180X SoC clock controller generates and supplies clock to
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various peripherals within the SoC.
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This binding uses common clock bindings
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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properties:
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compatible:
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const: cvitek,cv180x-clk
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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# Clock controller node:
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- |
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clk: clock-controller {
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compatible = "cvitek,cv180x-clk";
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reg = <0x0 0x03002000 0x0 0x1000>;
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clocks = <&osc>;
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#clock-cells = <1>;
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};
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# Example PWM controller node that consumes clock generated by the clock controller:
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- |
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pwm0: pwm@3060000 {
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compatible = "cvitek,cvi-pwm";
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reg = <0x0 0x3060000 0x0 0x1000>;
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clocks = <&clk CV180X_CLK_PWM>;
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#pwm-cells = <1>;
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};
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...
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