3a4bcfca2f
1. add cvitek folders to u-boot-2021.10 2. add cv183x/cv182x part 3. add cv181x/cv180x part Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
131 lines
4.3 KiB
C
131 lines
4.3 KiB
C
#ifndef _SDHCI_REG_H
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#define _SDHCI_REG_H
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#include "cv180x_reg.h"
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#define REG_TOP_SD_PWRSW_CTRL (0x1F4)
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#define REG_SDIO0_PAD_MASK (0xFFFFFFF3)
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#define REG_SDIO0_PAD_SHIFT (2)
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#define REG_SDIO0_PAD_CLR_MASK (0xC)
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#define REG_SDIO0_CD_PAD_REG (PINMUX_BASE + 0x900)
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#define REG_SDIO0_CD_PAD_VALUE (1)
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#define REG_SDIO0_CD_PAD_RESET (1)
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#define REG_SDIO0_PWR_EN_PAD_REG (PINMUX_BASE + 0x904)
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#define REG_SDIO0_PWR_EN_PAD_VALUE (2)
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#define REG_SDIO0_PWR_EN_PAD_RESET (2)
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#define REG_SDIO0_CLK_PAD_REG (PINMUX_BASE + 0xA00)
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#define REG_SDIO0_CLK_PAD_VALUE (2)
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#define REG_SDIO0_CLK_PAD_RESET (2)
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#define REG_SDIO0_CMD_PAD_REG (PINMUX_BASE + 0xA04)
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#define REG_SDIO0_CMD_PAD_VALUE (1)
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#define REG_SDIO0_CMD_PAD_RESET (2)
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#define REG_SDIO0_DAT0_PAD_REG (PINMUX_BASE + 0xA08)
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#define REG_SDIO0_DAT0_PAD_VALUE (1)
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#define REG_SDIO0_DAT0_PAD_RESET (2)
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#define REG_SDIO0_DAT1_PAD_REG (PINMUX_BASE + 0xA0C)
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#define REG_SDIO0_DAT1_PAD_VALUE (1)
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#define REG_SDIO0_DAT1_PAD_RESET (2)
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#define REG_SDIO0_DAT2_PAD_REG (PINMUX_BASE + 0xA10)
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#define REG_SDIO0_DAT2_PAD_VALUE (1)
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#define REG_SDIO0_DAT2_PAD_RESET (2)
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#define REG_SDIO0_DAT3_PAD_REG (PINMUX_BASE + 0xA14)
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#define REG_SDIO0_DAT3_PAD_VALUE (1)
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#define REG_SDIO0_DAT3_PAD_RESET (2)
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#define PAD_SDIO0_CD_REG (PINMUX_BASE + 0x18)
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#define PAD_SDIO0_PWR_EN_REG (PINMUX_BASE + 0x1C)
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#define PAD_SDIO0_CLK_REG (PINMUX_BASE + 0x0)
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#define PAD_SDIO0_CMD_REG (PINMUX_BASE + 0x4)
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#define PAD_SDIO0_D0_REG (PINMUX_BASE + 0x8)
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#define PAD_SDIO0_D1_REG (PINMUX_BASE + 0xC)
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#define PAD_SDIO0_D2_REG (PINMUX_BASE + 0x10)
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#define PAD_SDIO0_D3_REG (PINMUX_BASE + 0x14)
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#define REG_SDIO1_PAD_MASK (0xFFFFFFF3)
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#define REG_SDIO1_PAD_SHIFT (2)
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#define SDIO1_PAD_BASE 0x05027000
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#define REG_SDIO1_PAD_CLR_MASK (0xC)
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#define REG_SDIO1_CLK_PAD_REG (SDIO1_PAD_BASE + 0x06C)
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#define REG_SDIO1_CLK_PAD_VALUE (2)
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#define REG_SDIO1_CMD_PAD_REG (SDIO1_PAD_BASE + 0x068)
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#define REG_SDIO1_CMD_PAD_VALUE (1)
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#define REG_SDIO1_DAT0_PAD_REG (SDIO1_PAD_BASE + 0x064)
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#define REG_SDIO1_DAT0_PAD_VALUE (1)
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#define REG_SDIO1_DAT2_PAD_REG (SDIO1_PAD_BASE + 0x05C)
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#define REG_SDIO1_DAT2_PAD_VALUE (1)
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#define REG_SDIO1_DAT1_PAD_REG (SDIO1_PAD_BASE + 0x060)
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#define REG_SDIO1_DAT1_PAD_VALUE (1)
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#define REG_SDIO1_DAT3_PAD_REG (SDIO1_PAD_BASE + 0x058)
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#define REG_SDIO1_DAT3_PAD_VALUE (1)
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#define REG_EMMC_PAD_CLR_MASK (0xC)
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#define REG_EMMC_PAD_SHIFT (2)
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#define REG_EMMC_RSTN_PAD_REG (PINMUX_BASE + 0x914)
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#define REG_EMMC_RSTN_PAD_VALUE (1)
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#define REG_EMMC_CLK_PAD_REG (PINMUX_BASE + 0x91c)
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#define REG_EMMC_CLK_PAD_VALUE (2)
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#define REG_EMMC_CMD_PAD_REG (PINMUX_BASE + 0x928)
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#define REG_EMMC_CMD_PAD_VALUE (1)
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#define REG_EMMC_DAT0_PAD_REG (PINMUX_BASE + 0x920)
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#define REG_EMMC_DAT0_PAD_VALUE (1)
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#define REG_EMMC_DAT1_PAD_REG (PINMUX_BASE + 0x92C)
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#define REG_EMMC_DAT1_PAD_VALUE (1)
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#define REG_EMMC_DAT2_PAD_REG (PINMUX_BASE + 0x918)
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#define REG_EMMC_DAT2_PAD_VALUE (1)
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#define REG_EMMC_DAT3_PAD_REG (PINMUX_BASE + 0x924)
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#define REG_EMMC_DAT3_PAD_VALUE (1)
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#define CVI_SDHCI_VENDOR_OFFSET 0x200
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#define CVI_SDHCI_PHY_TX_RX_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x40)
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#define CVI_SDHCI_PHY_DS_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x44)
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#define CVI_SDHCI_PHY_DLY_STS (CVI_SDHCI_VENDOR_OFFSET + 0x48)
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#define CVI_SDHCI_PHY_CONFIG (CVI_SDHCI_VENDOR_OFFSET + 0x4C)
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#define CVI_SDHCI_BIT_CLK_FREE_EN 2
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#define CVI_SDHCI_CLK_FREE_EN_VALUE 0
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#define CVI_SDHCI_CLK_FREE_EN_MASK 0xFFFFFFFB
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#define CVI_SDHCI_VENDOR_MSHC_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x0)
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#define CVI_SDHCI_PHY_RX_DLY_SHIFT 16
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// Bit 16~22
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#define CVI_SDHCI_PHY_RX_DLY_MASK 0x7F0000
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#define CVI_SDHCI_PHY_TX_RX_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x40)
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#define CVI_SDHCI_PHY_RX_SRC_BIT_1 24
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#define CVI_SDHCI_PHY_RX_SRC_BIT_2 25
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#define SDHCI_PHY_CONFIG \
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(CVI_SDHCI_VENDOR_OFFSET + \
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0x4C) // P_VERDOR_SPECIFIC_AREA + 0x4c0x24c( PHY_TX_BPS )
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#define REG_TX_BPS_SEL_MASK 0xFFFFFFFE
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#define REG_TX_BPS_SEL_CLR_MASK (0x1) // 0x24c PHY_TX_BPS
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#define REG_TX_BPS_SEL_SHIFT (0) // 0x24c PHY_TX_BPS
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#define REG_TX_BPS_SEL_BYPASS (1) // 0x24c PHY_TX_BPS inv
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#define MMC_MAX_CLOCK (375000000)
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#define MMC_MAX_CLOCK_DIV_VALUE (0x40009)
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#define CLOCK_BYPASS_SELECT_REGISTER (0x3002030)
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#define MAX_TUNING_CMD_RETRY_COUNT 50
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#define TUNE_MAX_PHCODE 128
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#define TAP_WINDOW_THLD 20
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#endif
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