607778300c
1. add cv181x functions 2. Delete some useless files and add .gitignore Change-Id: Iea2b2fa43b5a1152e5e99fb32b88f8d2c249251a
256 lines
6.8 KiB
C
256 lines
6.8 KiB
C
#include <common.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <linux/delay.h>
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#include "vip_common.h"
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#include "scaler_reg.h"
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#include "reg.h"
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#include "dsi_phy.h"
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/****************************************************************************
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* Global parameters
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****************************************************************************/
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static uintptr_t reg_base;
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static u8 data_0_lane;
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static bool data_0_pn_swap;
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/****************************************************************************
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* Interfaces
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****************************************************************************/
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void dphy_set_base_addr(void *base)
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{
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reg_base = (uintptr_t)base;
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}
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/**
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* dphy_dsi_lane_en - set dsi-lanes enable control.
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* setup before dphy_dsi_init().
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*
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* @param clk_en: clk lane enable
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* @param data_en: data lane[0-3] enable
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* @param preamble_en: preeamble enable
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*/
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void dphy_dsi_lane_en(bool clk_en, bool *data_en, bool preamble_en)
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{
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u8 val = 0, i = 0;
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val |= clk_en;
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for (i = 0; i < 4; ++i)
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val |= (data_en[i] << (i + 1));
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if (preamble_en)
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val |= 0x20;
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_reg_write_mask(reg_base + REG_DSI_PHY_EN, 0x3f, val);
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}
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/**
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* dphy_dsi_set_lane - dsi-lanes control.
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* setup before dphy_dsi_lane_en().
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*
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* @param lane_num: lane[0-4].
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* @param lane: the role of this lane.
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* @param pn_swap: if this lane positive/negative swap.
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* @param clk_phase_shift: if this clk lane phase shift 90 degree.
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* @return: 0 for success.
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*/
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int dphy_dsi_set_lane(u8 lane_num, enum lane_id lane, bool pn_swap, bool clk_phase_shift)
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{
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if ((lane_num > 4) || (lane > DSI_LANE_MAX))
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return -1;
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_reg_write_mask(reg_base + REG_DSI_PHY_LANE_SEL, 0x7 << (4 * lane_num), lane << (4 * lane_num));
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_reg_write_mask(reg_base + REG_DSI_PHY_LANE_PN_SWAP, BIT(lane_num), pn_swap << lane_num);
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if (lane == DSI_LANE_CLK)
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_reg_write_mask(reg_base + REG_DSI_PHY_LANE_SEL, 0x1f << 24,
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clk_phase_shift ? ((1 << 24) << lane_num) : 0);
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if (lane == DSI_LANE_0) {
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data_0_lane = lane_num;
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data_0_pn_swap = pn_swap;
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}
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return 0;
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}
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void dphy_lvds_enable(bool en)
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{
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_reg_write(reg_base + REG_DSI_PHY_LVDS_EN, en);
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}
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/**
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* dphy_dsi_init - dphy init.
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* Invoked after dphy_dsi_set_lane() and dphy_dsi_lane_en().
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*
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*/
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void dphy_init(enum sclr_vo_intf intf)
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{
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_reg_write(reg_base + REG_DSI_PHY_PD, (intf == SCLR_VO_INTF_MIPI || intf == SCLR_VO_INTF_LVDS
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) ? 0x0 : 0x1f1f);
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_reg_write(reg_base + REG_DSI_PHY_ESC_INIT, 0x100);
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_reg_write(reg_base + REG_DSI_PHY_ESC_WAKE, 0x100);
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if ((intf == SCLR_VO_INTF_BT656) || (intf == SCLR_VO_INTF_BT1120) || (intf == SCLR_VO_INTF_I80))
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_reg_write(reg_base + REG_DSI_PHY_EXT_GPIO, 0x000fffff);
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else
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_reg_write(reg_base + REG_DSI_PHY_EXT_GPIO, 0x0);
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_reg_write(reg_base + REG_DSI_PHY_LVDS_EN, (intf == SCLR_VO_INTF_LVDS));
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}
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int ilog2(int x)
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{
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/*
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* Find the leftmost 1. Use a method that is similar to
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* binary search.
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*/
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int result = 0;
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result = (!!(x >> 16)) << 4; // if > 16?
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// based on previous result, if > (result + 8)
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result = result + ((!!(x >> (result + 8))) << 3);
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result = result + ((!!(x >> (result + 4))) << 2);
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result = result + ((!!(x >> (result + 2))) << 1);
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result = result + (!!(x >> (result + 1)));
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return result;
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}
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void _cal_pll_reg(u32 clkkHz, u32 VCOR_10000, u32 *reg_txpll, u32 *reg_set)
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{
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u8 gain = 1 << ilog2(max((u32)1, (u32)(25000000UL / VCOR_10000)));
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u32 VCOC_1000 = VCOR_10000 * gain / 10;
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u8 reg_disp_div_sel = VCOC_1000 / clkkHz;
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u8 dig_dig = ilog2(gain);
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u8 reg_divout_sel = min((u8)3, dig_dig);
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u8 reg_div_sel = dig_dig - reg_divout_sel;
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u8 loop_gain = (((VCOC_1000 / 266000) + 7) >> 3) << 3;
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*reg_set = ((u64)(1200000 * loop_gain) << 26) / VCOC_1000;
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*reg_txpll = (reg_div_sel << 10) | (reg_divout_sel << 8) | reg_disp_div_sel;
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#if 0
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pr_info("clkkHz(%d) VCORx10000(%d) gain(%d)\n", clkkHz, VCOR_10000, gain);
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pr_info("VCOCx1000(%d) dig_dig(%d) loop_gain(%d)\n", VCOC_1000, dig_dig, loop_gain);
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pr_info("regs: disp_div_sel(%d), divout_sel(%d), set(%#x)\n", reg_disp_div_sel, reg_divout_sel, *reg_set);
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#endif
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}
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void dphy_lvds_set_pll(u32 clkkHz, u8 link)
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{
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u32 VCOR_10000 = clkkHz * 70 / link;
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u32 reg_txpll, reg_set;
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_cal_pll_reg(clkkHz, VCOR_10000, ®_txpll, ®_set);
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_reg_write_mask(reg_base + REG_DSI_PHY_TXPLL, 0x7ff, reg_txpll);
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_reg_write(reg_base + REG_DSI_PHY_REG_SET, reg_set);
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}
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void dphy_dsi_set_pll(u32 clkkHz, u8 lane, u8 bits)
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{
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u32 VCOR_10000 = clkkHz * bits * 10 / lane;
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u32 reg_txpll, reg_set;
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_cal_pll_reg(clkkHz, VCOR_10000, ®_txpll, ®_set);
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_reg_write_mask(reg_base + REG_DSI_PHY_TXPLL, 0x7ff, reg_txpll);
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_reg_write(reg_base + REG_DSI_PHY_REG_SET, reg_set);
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// update
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_reg_write_mask(reg_base + REG_DSI_PHY_REG_8C, BIT(0), 0);
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_reg_write_mask(reg_base + REG_DSI_PHY_REG_8C, BIT(0), 1);
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}
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void dphy_dsi_analog_setting(bool is_lvds)
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{
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//mercury needs this analog setting while lvds tx mode
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if (is_lvds)
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_reg_write_mask(reg_base + REG_DSI_PHY_REG_74, 0x3ff, 0x2AA);
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else
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_reg_write_mask(reg_base + REG_DSI_PHY_REG_74, 0x3ff, 0x0);
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}
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#define dcs_delay 1
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enum LP_DATA {
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LP_DATA_00 = 0x00010001,
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LP_DATA_01 = 0x00010101,
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LP_DATA_10 = 0x01010001,
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LP_DATA_11 = 0x01010101,
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LP_DATA_MAX
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};
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static inline void _data_0_manual_data(enum LP_DATA data)
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{
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if (data_0_pn_swap) {
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switch (data) {
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case LP_DATA_01:
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_reg_write(reg_base + REG_DSI_PHY_DATA_OV, LP_DATA_10 << data_0_lane);
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break;
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case LP_DATA_10:
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_reg_write(reg_base + REG_DSI_PHY_DATA_OV, LP_DATA_01 << data_0_lane);
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break;
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default:
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_reg_write(reg_base + REG_DSI_PHY_DATA_OV, data << data_0_lane);
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break;
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}
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} else {
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_reg_write(reg_base + REG_DSI_PHY_DATA_OV, data << data_0_lane);
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}
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udelay(dcs_delay);
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}
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// LP-11, LP-10, LP-00, LP-01, LP-00
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static void _esc_entry(void)
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{
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_data_0_manual_data(LP_DATA_11);
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_data_0_manual_data(LP_DATA_10);
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_data_0_manual_data(LP_DATA_00);
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_data_0_manual_data(LP_DATA_01);
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_data_0_manual_data(LP_DATA_00);
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}
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// LP-00, LP-10, LP-11
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static void _esc_exit(void)
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{
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_data_0_manual_data(LP_DATA_00);
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_data_0_manual_data(LP_DATA_10);
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_data_0_manual_data(LP_DATA_11);
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}
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static void _esc_data(u8 data)
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{
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u8 i = 0;
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for (i = 0; i < 8; ++i) {
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_data_0_manual_data(((data & (1 << i)) ? LP_DATA_10 : LP_DATA_01));
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_data_0_manual_data(LP_DATA_00);
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}
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}
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void dpyh_mipi_tx_manual_packet(const u8 *data, u8 count)
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{
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u8 i = 0;
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_esc_entry();
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_esc_data(0x87); // LPDT
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for (i = 0; i < count; ++i)
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_esc_data(data[i]);
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_esc_exit();
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_reg_write(reg_base + REG_DSI_PHY_DATA_OV, 0x0);
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}
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void dphy_set_hs_settle(u8 prepare, u8 zero, u8 trail)
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{
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_reg_write_mask(reg_base + REG_DSI_PHY_HS_CFG1, 0xffffff00, (trail << 24) | (zero << 16) | (prepare << 8));
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}
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void dphy_get_hs_settle(u8 *prepare, u8 *zero, u8 *trail)
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{
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u32 value = _reg_read(reg_base + REG_DSI_PHY_HS_CFG1);
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if (prepare)
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*prepare = (value >> 8) & 0xff;
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if (zero)
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*zero = (value >> 16) & 0xff;
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if (trail)
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*trail = (value >> 24) & 0xff;
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}
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