607778300c
1. add cv181x functions 2. Delete some useless files and add .gitignore Change-Id: Iea2b2fa43b5a1152e5e99fb32b88f8d2c249251a
148 lines
7.4 KiB
C
148 lines
7.4 KiB
C
#ifndef _CVI_SCL_REG_H_
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#define _CVI_SCL_REG_H_
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#if defined(ENV_CVITEST) || defined(ENV_EMU)
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#define REG_SCL_TOP_BASE 0x0A080000
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#define REG_DSI_WRAP_BASE 0x0300C000
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#else
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#define REG_SCL_TOP_BASE 0
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#define REG_DSI_WRAP_BASE 0
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#endif
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#define REG_GOP_OFFSET 0x800
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#define REG_SCL_DISP_BASE (REG_SCL_TOP_BASE + 0x8000)
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#define REG_SCL_BT_BASE (REG_SCL_TOP_BASE + 0x9000)
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#define REG_SCL_DSI_BASE (REG_SCL_TOP_BASE + 0xA000)
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// ============== TOP ============== //
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#define REG_SCL_TOP_CFG0 (REG_SCL_TOP_BASE + 0x00)
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#define REG_SCL_TOP_CFG1 (REG_SCL_TOP_BASE + 0x04)
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#define REG_SCL_TOP_AXI (REG_SCL_TOP_BASE + 0x08)
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#define REG_SCL_TOP_BT_CFG (REG_SCL_TOP_BASE + 0x0C)
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#define REG_SCL_TOP_SHD (REG_SCL_TOP_BASE + 0x10)
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#define REG_SCL_TOP_INTR_MASK (REG_SCL_TOP_BASE + 0x30)
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#define REG_SCL_TOP_INTR_STATUS (REG_SCL_TOP_BASE + 0x34)
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#define REG_SCL_TOP_INTR_ENABLE (REG_SCL_TOP_BASE + 0x38)
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#define REG_SCL_TOP_IMG_CTRL (REG_SCL_TOP_BASE + 0x40)
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#define REG_SCL_TOP_CMDQ_START (REG_SCL_TOP_BASE + 0x44)
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#define REG_SCL_TOP_CMDQ_STOP (REG_SCL_TOP_BASE + 0x48)
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#define REG_SCL_TOP_PG (REG_SCL_TOP_BASE + 0x4C)
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#define REG_SCL_TOP_LVDSTX (REG_SCL_TOP_BASE + 0x50)
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#define REG_SCL_TOP_BT_ENC (REG_SCL_TOP_BASE + 0x60)
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#define REG_SCL_TOP_BT_SYNC_CODE (REG_SCL_TOP_BASE + 0x64)
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#define REG_SCL_TOP_BT_BLK_DATA (REG_SCL_TOP_BASE + 0x68)
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#define REG_SCL_TOP_VO_MUX (REG_SCL_TOP_BASE + 0x70)
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// ============== DISP ============== //
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#define REG_SCL_DISP_CFG (REG_SCL_DISP_BASE + 0x00)
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#define REG_SCL_DISP_TOTAL (REG_SCL_DISP_BASE + 0x04)
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#define REG_SCL_DISP_VSYNC (REG_SCL_DISP_BASE + 0x08)
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#define REG_SCL_DISP_VFDE (REG_SCL_DISP_BASE + 0x0C)
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#define REG_SCL_DISP_VMDE (REG_SCL_DISP_BASE + 0x10)
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#define REG_SCL_DISP_HSYNC (REG_SCL_DISP_BASE + 0x14)
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#define REG_SCL_DISP_HFDE (REG_SCL_DISP_BASE + 0x18)
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#define REG_SCL_DISP_HMDE (REG_SCL_DISP_BASE + 0x1C)
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#define REG_SCL_DISP_ADDR0_L (REG_SCL_DISP_BASE + 0x34)
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#define REG_SCL_DISP_ADDR0_H (REG_SCL_DISP_BASE + 0x38)
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#define REG_SCL_DISP_ADDR1_L (REG_SCL_DISP_BASE + 0x3C)
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#define REG_SCL_DISP_ADDR1_H (REG_SCL_DISP_BASE + 0x40)
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#define REG_SCL_DISP_ADDR2_L (REG_SCL_DISP_BASE + 0x44)
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#define REG_SCL_DISP_ADDR2_H (REG_SCL_DISP_BASE + 0x48)
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#define REG_SCL_DISP_PITCH_Y (REG_SCL_DISP_BASE + 0x4C)
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#define REG_SCL_DISP_PITCH_C (REG_SCL_DISP_BASE + 0x50)
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#define REG_SCL_DISP_OFFSET (REG_SCL_DISP_BASE + 0x50)
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#define REG_SCL_DISP_SIZE (REG_SCL_DISP_BASE + 0x58)
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#define REG_SCL_DISP_OUT_CSC0 (REG_SCL_DISP_BASE + 0x5C)
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#define REG_SCL_DISP_OUT_CSC1 (REG_SCL_DISP_BASE + 0x60)
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#define REG_SCL_DISP_OUT_CSC2 (REG_SCL_DISP_BASE + 0x64)
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#define REG_SCL_DISP_OUT_CSC3 (REG_SCL_DISP_BASE + 0x68)
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#define REG_SCL_DISP_OUT_CSC4 (REG_SCL_DISP_BASE + 0x6C)
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#define REG_SCL_DISP_OUT_CSC_SUB (REG_SCL_DISP_BASE + 0x70)
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#define REG_SCL_DISP_OUT_CSC_ADD (REG_SCL_DISP_BASE + 0x74)
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#define REG_SCL_DISP_IN_CSC0 (REG_SCL_DISP_BASE + 0x78)
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#define REG_SCL_DISP_IN_CSC1 (REG_SCL_DISP_BASE + 0x7C)
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#define REG_SCL_DISP_IN_CSC2 (REG_SCL_DISP_BASE + 0x80)
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#define REG_SCL_DISP_IN_CSC3 (REG_SCL_DISP_BASE + 0x84)
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#define REG_SCL_DISP_IN_CSC4 (REG_SCL_DISP_BASE + 0x88)
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#define REG_SCL_DISP_IN_CSC_SUB (REG_SCL_DISP_BASE + 0x8C)
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#define REG_SCL_DISP_IN_CSC_ADD (REG_SCL_DISP_BASE + 0x90)
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#define REG_SCL_DISP_PAT_CFG (REG_SCL_DISP_BASE + 0x94)
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#define REG_SCL_DISP_PAT_COLOR0 (REG_SCL_DISP_BASE + 0x98)
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#define REG_SCL_DISP_PAT_COLOR1 (REG_SCL_DISP_BASE + 0x9C)
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#define REG_SCL_DISP_PAT_COLOR2 (REG_SCL_DISP_BASE + 0xA0)
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#define REG_SCL_DISP_PAT_COLOR3 (REG_SCL_DISP_BASE + 0xA4)
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#define REG_SCL_DISP_PAT_COLOR4 (REG_SCL_DISP_BASE + 0xA8)
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#define REG_SCL_DISP_DBG (REG_SCL_DISP_BASE + 0xAC)
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#define REG_SCL_DISP_AXI_ST (REG_SCL_DISP_BASE + 0xB0)
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#define REG_SCL_DISP_CACHE (REG_SCL_DISP_BASE + 0xC0)
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#define REG_SCL_DISP_DUMMY (REG_SCL_DISP_BASE + 0xF8)
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// GAMMA
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#define REG_SCL_DISP_GAMMA_CTRL (REG_SCL_DISP_BASE + 0x180)
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#define REG_SCL_DISP_GAMMA_WR_LUT (REG_SCL_DISP_BASE + 0x184)
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#define REG_SCL_DISP_GAMMA_RD_LUT (REG_SCL_DISP_BASE + 0x188)
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// i80
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#define REG_SCL_DISP_MCU_IF_CTRL (REG_SCL_DISP_BASE + 0x200)
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#define REG_SCL_DISP_MCU_SW_CTRL (REG_SCL_DISP_BASE + 0x204)
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#define REG_SCL_DISP_MCU_STATUS (REG_SCL_DISP_BASE + 0x208)
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// GOP
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#define REG_SCL_DISP_GOP_FMT(y) (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x20 * (y) + 0x00)
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#define REG_SCL_DISP_GOP_H_RANGE(y) (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x20 * (y) + 0x04)
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#define REG_SCL_DISP_GOP_V_RANGE(y) (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x20 * (y) + 0x08)
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#define REG_SCL_DISP_GOP_ADDR_L(y) (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x20 * (y) + 0x0c)
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#define REG_SCL_DISP_GOP_ADDR_H(y) (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x20 * (y) + 0x10)
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#define REG_SCL_DISP_GOP_PITCH(y) (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x20 * (y) + 0x14)
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#define REG_SCL_DISP_GOP_SIZE(y) (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x20 * (y) + 0x18)
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#define REG_SCL_DISP_GOP_CFG (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x100)
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#define REG_SCL_DISP_GOP_LUT0 (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x104)
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#define REG_SCL_DISP_GOP_LUT1 (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x108)
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#define REG_SCL_DISP_GOP_COLORKEY (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x10c)
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#define REG_SCL_DISP_GOP_FONTCOLOR (REG_SCL_DISP_BASE + REG_GOP_OFFSET + 0x110)
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// ============== DSI ============== //
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#define REG_SCL_DSI_MAC_EN (REG_SCL_DSI_BASE + 0x00)
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#define REG_SCL_DSI_HS_0 (REG_SCL_DSI_BASE + 0x04)
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#define REG_SCL_DSI_HS_1 (REG_SCL_DSI_BASE + 0x08)
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#define REG_SCL_DSI_ESC (REG_SCL_DSI_BASE + 0x0C)
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#define REG_SCL_DSI_ESC_TX0 (REG_SCL_DSI_BASE + 0x10)
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#define REG_SCL_DSI_ESC_TX1 (REG_SCL_DSI_BASE + 0x14)
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#define REG_SCL_DSI_ESC_TX2 (REG_SCL_DSI_BASE + 0x18)
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#define REG_SCL_DSI_ESC_TX3 (REG_SCL_DSI_BASE + 0x1C)
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#define REG_SCL_DSI_ESC_RX0 (REG_SCL_DSI_BASE + 0x20)
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#define REG_SCL_DSI_ESC_RX1 (REG_SCL_DSI_BASE + 0x24)
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// ============== DSI PHY ============== //
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#define REG_DSI_PHY_EN (REG_DSI_WRAP_BASE + 0x00)
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#define REG_DSI_PHY_CLK_CFG1 (REG_DSI_WRAP_BASE + 0x04)
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#define REG_DSI_PHY_CLK_CFG2 (REG_DSI_WRAP_BASE + 0x08)
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#define REG_DSI_PHY_ESC_INIT (REG_DSI_WRAP_BASE + 0x0C)
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#define REG_DSI_PHY_ESC_WAKE (REG_DSI_WRAP_BASE + 0x10)
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#define REG_DSI_PHY_HS_CFG1 (REG_DSI_WRAP_BASE + 0x14)
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#define REG_DSI_PHY_HS_CFG2 (REG_DSI_WRAP_BASE + 0x18)
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#define REG_DSI_PHY_CAL_CFG (REG_DSI_WRAP_BASE + 0x1C)
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#define REG_DSI_PHY_CAL_NUM (REG_DSI_WRAP_BASE + 0x20)
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#define REG_DSI_PHY_CLK_STATE (REG_DSI_WRAP_BASE + 0x24)
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#define REG_DSI_PHY_DATA0_STATE (REG_DSI_WRAP_BASE + 0x28)
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#define REG_DSI_PHY_DATA12_STATE (REG_DSI_WRAP_BASE + 0x2C)
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#define REG_DSI_PHY_DATA3_STATE (REG_DSI_WRAP_BASE + 0x30)
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#define REG_DSI_PHY_HS_OV (REG_DSI_WRAP_BASE + 0x38)
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#define REG_DSI_PHY_HS_SW1 (REG_DSI_WRAP_BASE + 0x3C)
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#define REG_DSI_PHY_HS_SW2 (REG_DSI_WRAP_BASE + 0x40)
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#define REG_DSI_PHY_DATA_OV (REG_DSI_WRAP_BASE + 0x44)
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#define REG_DSI_PHY_LPTX_OV (REG_DSI_WRAP_BASE + 0x4C)
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#define REG_DSI_PHY_LPRX_OV (REG_DSI_WRAP_BASE + 0x4C)
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#define REG_DSI_PHY_PD (REG_DSI_WRAP_BASE + 0x64)
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#define REG_DSI_PHY_TXPLL (REG_DSI_WRAP_BASE + 0x6C)
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#define REG_DSI_PHY_REG_74 (REG_DSI_WRAP_BASE + 0x74)
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#define REG_DSI_PHY_REG_8C (REG_DSI_WRAP_BASE + 0x8C)
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#define REG_DSI_PHY_REG_SET (REG_DSI_WRAP_BASE + 0x90)
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#define REG_DSI_PHY_LANE_SEL (REG_DSI_WRAP_BASE + 0x9C)
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#define REG_DSI_PHY_LANE_PN_SWAP (REG_DSI_WRAP_BASE + 0xA0)
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#define REG_DSI_PHY_LVDS_EN (REG_DSI_WRAP_BASE + 0xB4)
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#define REG_DSI_PHY_EXT_GPIO (REG_DSI_WRAP_BASE + 0xC0)
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#endif // _CVI_SCL_REG_H_
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