7e1529d0dc
0debf7abc [dma] When using DMA, if the DMA addr spans 128MB boundary we have to split the DMA transfer into two so that each one doesn't exceed the boundary. 4f7ed7449 Merge "[eth] change rxterm and vcm to link DianXin router" into v4.1.0 feb60bba5 Merge "[audio][lt9611]add drivers" into v4.1.0 a3dde371c [eth] change rxterm and vcm to link DianXin router e615d3a43 [audio][lt9611]add drivers Change-Id: If4fdcbc32df6aeaed04da0efbd23455376e2a53c
375 lines
11 KiB
C
375 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/* Driver for CVITEK PHYs */
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/cv180x_efuse.h>
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#define REG_EPHY_TOP_WRAP 0x03009800
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#define REG_EPHY_BASE 0x03009000
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#define EPHY_EFUSE_TXECHORC_FLAG 0x00000100 // bit 8
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#define EPHY_EFUSE_TXITUNE_FLAG 0x00000200 // bit 9
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#define EPHY_EFUSE_TXRXTERM_FLAG 0x00000800 // bit 11
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#define CVI_INT_EVENTS \
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(CVI_LNK_STS_CHG_INT_MSK | CVI_MGC_PKT_DET_INT_MSK)
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static int cv182xa_phy_config_intr(struct phy_device *phydev)
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{
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return 0;
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}
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static int cv182xa_phy_ack_interrupt(struct phy_device *phydev)
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{
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return 0;
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}
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static int cv182xa_read_status(struct phy_device *phydev)
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{
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int err = genphy_read_status(phydev);
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pr_debug("%s, speed=%d, duplex=%d, ", __func__, phydev->speed, phydev->duplex);
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pr_debug("pasue=%d, asym_pause=%d, autoneg=%d ", phydev->pause, phydev->asym_pause, phydev->autoneg);
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return err;
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}
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#if defined(CONFIG_CVITEK_PHY_UAPS)
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/* Ultra Auto Power Saving mode */
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static int cv182xa_phy_aps_enable(struct phy_device *phydev)
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{
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return 0;
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}
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#endif
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static int cv182xa_phy_config_aneg(struct phy_device *phydev)
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{
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int ret;
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#if defined(CONFIG_CVITEK_PHY_UAPS)
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cv182xa_phy_aps_enable(phydev); /* if phy not work, disable this function for try */
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#endif
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ret = genphy_config_aneg(phydev);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int cv182xa_phy_config_init(struct phy_device *phydev)
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{
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int ret = 0;
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u32 val = 0;
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void __iomem *reg_ephy_top_wrap = NULL;
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void __iomem *reg_ephy_base = NULL;
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reg_ephy_top_wrap = ioremap(REG_EPHY_TOP_WRAP, 0x8);
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if (!reg_ephy_top_wrap) {
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ret = -EBUSY;
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goto err_ephy_mem_1;
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}
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reg_ephy_base = ioremap(REG_EPHY_BASE, 0x80);
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if (!reg_ephy_base) {
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ret = -EBUSY;
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goto err_ephy_mem_2;
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}
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// set rg_ephy_apb_rw_sel 0x0804@[0]=1/APB by using APB interface
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writel(0x0001, reg_ephy_top_wrap + 4);
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writel(0x0, reg_ephy_base + 0x7c);
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/* do this in board.c */
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// Release 0x0800[0]=0/shutdown
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// writel(0x0900, reg_ephy_top_wrap);
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// // Release 0x0800[2]=1/dig_rst_n, Let mii_reg can be accessabile
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// writel(0x0904, reg_ephy_top_wrap);
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// //mdelay(10);
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// // ANA INIT (PD/EN), switch to MII-page5
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// writel(0x0500, reg_ephy_base + 0x7c);
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// // Release ANA_PD p5.0x10@[13:8] = 6'b001100
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// writel(0x0c00, reg_ephy_base + 0x40);
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// // Release ANA_EN p5.0x10@[7:0] = 8'b01111110
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// writel(0x0c7e, reg_ephy_base + 0x40);
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// // Wait PLL_Lock, Lock_Status p5.0x12@[15] = 1
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// //mdelay(1);
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// // Release 0x0800[1] = 1/ana_rst_n
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// writel(0x0906, reg_ephy_top_wrap);
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// // ANA INIT
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// // @Switch to MII-page5
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// writel(0x0500, reg_ephy_base + 0x7c);
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// Efuse register
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// Set Double Bias Current
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//Set rg_eth_txitune1 reg_ephy_base + 0x64 [15:8]
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//Set rg_eth_txitune0 reg_ephy_base + 0x64 [7:0]
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if ((cvi_efuse_read_from_shadow(0x20) & EPHY_EFUSE_TXITUNE_FLAG) ==
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EPHY_EFUSE_TXITUNE_FLAG) {
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val = ((cvi_efuse_read_from_shadow(0x24) >> 24) & 0xFF) |
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(((cvi_efuse_read_from_shadow(0x24) >> 16) & 0xFF) << 8);
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writel((readl(reg_ephy_base + 0x64) & ~0xFFFF) | val, reg_ephy_base + 0x64);
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} else
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writel(0x5a5a, reg_ephy_base + 0x64);
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// Set Echo_I
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// Set rg_eth_txechoiadj reg_ephy_base + 0x54 [15:8]
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if ((cvi_efuse_read_from_shadow(0x20) & EPHY_EFUSE_TXECHORC_FLAG) ==
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EPHY_EFUSE_TXECHORC_FLAG) {
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writel((readl(reg_ephy_base + 0x54) & ~0xFF00) |
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(((cvi_efuse_read_from_shadow(0x24) >> 8) & 0xFF) << 8), reg_ephy_base + 0x54);
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} else
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writel(0x0000, reg_ephy_base + 0x54);
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//Set TX_Rterm & Echo_RC_Delay
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// Set rg_eth_txrterm_p1 reg_ephy_base + 0x58 [11:8]
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// Set rg_eth_txrterm reg_ephy_base + 0x58 [7:4]
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// Set rg_eth_txechorcadj reg_ephy_base + 0x58 [3:0]
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if ((cvi_efuse_read_from_shadow(0x20) & EPHY_EFUSE_TXRXTERM_FLAG) ==
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EPHY_EFUSE_TXRXTERM_FLAG) {
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val = (((cvi_efuse_read_from_shadow(0x20) >> 28) & 0xF) << 4) |
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(((cvi_efuse_read_from_shadow(0x20) >> 24) & 0xF) << 8);
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writel((readl(reg_ephy_base + 0x58) & ~0xFF0) | val, reg_ephy_base + 0x58);
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} else
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writel(0x0bb0, reg_ephy_base + 0x58);
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// ETH_100BaseT
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// Set Rise update
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writel(0x0c10, reg_ephy_base + 0x5c);
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// Set Falling phase
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writel(0x0003, reg_ephy_base + 0x68);
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// Set Double TX Bias Current
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writel(0x0000, reg_ephy_base + 0x54);
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// Switch to MII-page16
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writel(0x1000, reg_ephy_base + 0x7c);
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// Set MLT3 Positive phase code, Set MLT3 +0
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writel(0x1000, reg_ephy_base + 0x68);
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writel(0x3020, reg_ephy_base + 0x6c);
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writel(0x5040, reg_ephy_base + 0x70);
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writel(0x7060, reg_ephy_base + 0x74);
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// Set MLT3 +I
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writel(0x1708, reg_ephy_base + 0x58);
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writel(0x3827, reg_ephy_base + 0x5c);
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writel(0x5748, reg_ephy_base + 0x60);
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writel(0x7867, reg_ephy_base + 0x64);
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// Switch to MII-page17
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writel(0x1100, reg_ephy_base + 0x7c);
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// Set MLT3 Negative phase code, Set MLT3 -0
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writel(0x9080, reg_ephy_base + 0x40);
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writel(0xb0a0, reg_ephy_base + 0x44);
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writel(0xd0c0, reg_ephy_base + 0x48);
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writel(0xf0e0, reg_ephy_base + 0x4c);
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// Set MLT3 -I
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writel(0x9788, reg_ephy_base + 0x50);
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writel(0xb8a7, reg_ephy_base + 0x54);
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writel(0xd7c8, reg_ephy_base + 0x58);
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writel(0xf8e7, reg_ephy_base + 0x5c);
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// @Switch to MII-page5
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writel(0x0500, reg_ephy_base + 0x7c);
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// En TX_Rterm
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writel((0x0001 | readl(reg_ephy_base + 0x40)), reg_ephy_base + 0x40);
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//Change rx vcm
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writel((0x820 |readl(reg_ephy_base + 0x4c)), reg_ephy_base + 0x4c);
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// Link Pulse
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// Switch to MII-page10
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writel(0x0a00, reg_ephy_base + 0x7c);
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#if 1
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// Set Link Pulse
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writel(0x3e00, reg_ephy_base + 0x40);
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writel(0x7864, reg_ephy_base + 0x44);
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writel(0x6470, reg_ephy_base + 0x48);
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writel(0x5f62, reg_ephy_base + 0x4c);
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writel(0x5a5a, reg_ephy_base + 0x50);
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writel(0x5458, reg_ephy_base + 0x54);
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writel(0xb23a, reg_ephy_base + 0x58);
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writel(0x94a0, reg_ephy_base + 0x5c);
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writel(0x9092, reg_ephy_base + 0x60);
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writel(0x8a8e, reg_ephy_base + 0x64);
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writel(0x8688, reg_ephy_base + 0x68);
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writel(0x8484, reg_ephy_base + 0x6c);
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writel(0x0082, reg_ephy_base + 0x70);
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#else
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// from sean
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// Fix err: the status is still linkup when removed the network cable.
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writel(0x2000, reg_ephy_base + 0x40);
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writel(0x3832, reg_ephy_base + 0x44);
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writel(0x3132, reg_ephy_base + 0x48);
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writel(0x2d2f, reg_ephy_base + 0x4c);
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writel(0x2c2d, reg_ephy_base + 0x50);
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writel(0x1b2b, reg_ephy_base + 0x54);
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writel(0x94a0, reg_ephy_base + 0x58);
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writel(0x8990, reg_ephy_base + 0x5c);
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writel(0x8788, reg_ephy_base + 0x60);
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writel(0x8485, reg_ephy_base + 0x64);
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writel(0x8283, reg_ephy_base + 0x68);
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writel(0x8182, reg_ephy_base + 0x6c);
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writel(0x0081, reg_ephy_base + 0x70);
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#endif
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// TP_IDLE
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// Switch to MII-page11
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writel(0x0b00, reg_ephy_base + 0x7c);
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// Set TP_IDLE
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writel(0x5252, reg_ephy_base + 0x40);
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writel(0x5252, reg_ephy_base + 0x44);
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writel(0x4B52, reg_ephy_base + 0x48);
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writel(0x3D47, reg_ephy_base + 0x4c);
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writel(0xAA99, reg_ephy_base + 0x50);
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writel(0x989E, reg_ephy_base + 0x54);
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writel(0x9395, reg_ephy_base + 0x58);
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writel(0x9091, reg_ephy_base + 0x5c);
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writel(0x8E8F, reg_ephy_base + 0x60);
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writel(0x8D8E, reg_ephy_base + 0x64);
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writel(0x8C8C, reg_ephy_base + 0x68);
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writel(0x8B8B, reg_ephy_base + 0x6c);
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writel(0x008A, reg_ephy_base + 0x70);
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// ETH 10BaseT Data
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// Switch to MII-page13
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writel(0x0d00, reg_ephy_base + 0x7c);
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writel(0x1E0A, reg_ephy_base + 0x40);
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writel(0x3862, reg_ephy_base + 0x44);
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writel(0x1E62, reg_ephy_base + 0x48);
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writel(0x2A08, reg_ephy_base + 0x4c);
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writel(0x244C, reg_ephy_base + 0x50);
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writel(0x1A44, reg_ephy_base + 0x54);
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writel(0x061C, reg_ephy_base + 0x58);
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// Switch to MII-page14
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writel(0x0e00, reg_ephy_base + 0x7c);
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writel(0x2D30, reg_ephy_base + 0x40);
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writel(0x3470, reg_ephy_base + 0x44);
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writel(0x0648, reg_ephy_base + 0x48);
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writel(0x261C, reg_ephy_base + 0x4c);
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writel(0x3160, reg_ephy_base + 0x50);
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writel(0x2D5E, reg_ephy_base + 0x54);
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// Switch to MII-page15
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writel(0x0f00, reg_ephy_base + 0x7c);
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writel(0x2922, reg_ephy_base + 0x40);
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writel(0x366E, reg_ephy_base + 0x44);
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writel(0x0752, reg_ephy_base + 0x48);
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writel(0x2556, reg_ephy_base + 0x4c);
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writel(0x2348, reg_ephy_base + 0x50);
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writel(0x0C30, reg_ephy_base + 0x54);
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// Switch to MII-page16
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writel(0x1000, reg_ephy_base + 0x7c);
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writel(0x1E08, reg_ephy_base + 0x40);
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writel(0x3868, reg_ephy_base + 0x44);
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writel(0x1462, reg_ephy_base + 0x48);
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writel(0x1A0E, reg_ephy_base + 0x4c);
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writel(0x305E, reg_ephy_base + 0x50);
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writel(0x2F62, reg_ephy_base + 0x54);
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// LED
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// Switch to MII-page1
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writel(0x0100, reg_ephy_base + 0x7c);
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// select LED_LNK/SPD/DPX out to LED_PAD
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writel((readl(reg_ephy_base + 0x68) & ~0x0f00), reg_ephy_base + 0x68);
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// Switch to MII-page19
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writel(0x1300, reg_ephy_base + 0x7c);
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writel(0x0012, reg_ephy_base + 0x58);
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// set agc max/min swing
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writel(0x6848, reg_ephy_base + 0x5c);
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// Switch to MII-page18
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writel(0x1200, reg_ephy_base + 0x7c);
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#if IS_ENABLED(CONFIG_ARCH_CV181X)
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/* mars LPF(8, 8, 8, 8) HPF(-8, 50(+32), -36, -8) */
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// lpf
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writel(0x0808, reg_ephy_base + 0x48);
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writel(0x0808, reg_ephy_base + 0x4c);
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// hpf
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writel(0x32f8, reg_ephy_base + 0x50);
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writel(0xf8dc, reg_ephy_base + 0x54);
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#elif IS_ENABLED(CONFIG_ARCH_CV180X)
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/* phobos LPF:(1 8 23 23 8 1) HPF:(-4,58,-45,8,-5, 0) from sean PPT */
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// lpf
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writel(0x0801, reg_ephy_base + 0x48);
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writel(0x1717, reg_ephy_base + 0x4C);
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writel(0x0108, reg_ephy_base + 0x5C);
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// hpf
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writel(0x3afc, reg_ephy_base + 0x50);
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writel(0x08d3, reg_ephy_base + 0x54);
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writel(0x00fb, reg_ephy_base + 0x60);
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#endif
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// Switch to MII-page0
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writel(0x0000, reg_ephy_base + 0x7c);
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// EPHY start auto-neg procedure
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writel(0x090e, reg_ephy_top_wrap);
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// from jinyu.zhao
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/* EPHY is configured as half-duplex after reset, but we need force full-duplex */
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writel((readl(reg_ephy_base) | 0x100), reg_ephy_base);
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// switch to MDIO control by ETH_MAC
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writel(0x0000, reg_ephy_top_wrap + 4);
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iounmap(reg_ephy_base);
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err_ephy_mem_2:
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iounmap(reg_ephy_top_wrap);
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err_ephy_mem_1:
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return ret;
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}
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static struct phy_driver cv182xa_phy_driver[] = {
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{
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.phy_id = 0x00435649,
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.phy_id_mask = 0xffffffff,
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.name = "CVITEK CV182XA",
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.config_init = cv182xa_phy_config_init,
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.config_aneg = cv182xa_phy_config_aneg,
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.read_status = cv182xa_read_status,
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/* IRQ related */
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.ack_interrupt = cv182xa_phy_ack_interrupt,
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.config_intr = cv182xa_phy_config_intr,
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.aneg_done = genphy_aneg_done,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.set_loopback = genphy_loopback,
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} };
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module_phy_driver(cv182xa_phy_driver);
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MODULE_DESCRIPTION("CV182XA EPHY driver");
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MODULE_AUTHOR("Ethan Chen");
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MODULE_LICENSE("GPL");
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static struct mdio_device_id __maybe_unused cv182xa_tbl[] = {
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{ 0x00435649, 0xffffffff },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, cv182xa_tbl);
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