e6f4602bfc
support u-boot-spl [panel]add st7785m panel in uboot, sync clk with kernel [fix](sbi size): get sbi size from memmap.h [ion] support get ion total size Change-Id: I108fdbd39646db2b70e8ef118622737806ce46d7
36 lines
899 B
C
36 lines
899 B
C
/*
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* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
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*
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*/
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#ifndef _CVI_DSI_PHY_H_
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#define _CVI_DSI_PHY_H_
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#include "scaler.h"
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enum lane_id {
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DSI_LANE_CLK = 0,
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DSI_LANE_0,
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DSI_LANE_1,
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DSI_LANE_2,
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DSI_LANE_3,
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DSI_LANE_MAX,
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};
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void dphy_set_base_addr(void *base);
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void dphy_dsi_lane_en(bool clk_en, bool *data_en, bool preamble_en);
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int dphy_dsi_set_lane(u8 lane_num, enum lane_id lane, bool pn_swap, bool clk_phase_shift);
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int dphy_dsi_disable_lanes(void);
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void dphy_init(enum sclr_vo_intf intf);
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void dphy_dsi_set_pll(u32 clkkHz, u8 lane, u8 bits);
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void dphy_lvds_enable(bool en);
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void dphy_lvds_set_pll(u32 clkkHz, u8 link);
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void dphy_dsi_analog_setting(bool is_lvds);
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void dpyh_mipi_tx_manual_packet(const u8 *data, u8 count);
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void dphy_set_hs_settle(u8 prepare, u8 zero, u8 trail);
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void dphy_get_hs_settle(u8 *prepare, u8 *zero, u8 *trail);
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#endif // _CVI_DSI_PHY_H
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