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menu "Target options"
config BR2_ARCH_IS_64
bool
config BR2_KERNEL_64_USERLAND_32
bool
config BR2_SOFT_FLOAT
bool
config BR2_USE_MMU
bool
choice
prompt "Target Architecture"
default BR2_i386
help
Select the target architecture family to build for.
config BR2_arcle
bool "ARC (little endian)"
select BR2_USE_MMU
help
Synopsys' DesignWare ARC Processor Cores are a family of
32-bit CPUs that can be used from deeply embedded to high
performance host applications. Little endian.
config BR2_arceb
bool "ARC (big endian)"
select BR2_USE_MMU
help
Synopsys' DesignWare ARC Processor Cores are a family of
32-bit CPUs that can be used from deeply embedded to high
performance host applications. Big endian.
config BR2_arm
bool "ARM (little endian)"
# MMU support is set by the subarchitecture file, arch/Config.in.arm
help
ARM is a 32-bit reduced instruction set computer (RISC)
instruction set architecture (ISA) developed by ARM Holdings.
Little endian.
http://www.arm.com/
http://en.wikipedia.org/wiki/ARM
config BR2_armeb
bool "ARM (big endian)"
select BR2_USE_MMU
help
ARM is a 32-bit reduced instruction set computer (RISC)
instruction set architecture (ISA) developed by ARM Holdings.
Big endian.
http://www.arm.com/
http://en.wikipedia.org/wiki/ARM
config BR2_aarch64
bool "AArch64 (little endian)"
select BR2_ARCH_IS_64
help
Aarch64 is a 64-bit architecture developed by ARM Holdings.
http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
http://en.wikipedia.org/wiki/ARM
config BR2_aarch64_be
bool "AArch64 (big endian)"
select BR2_ARCH_IS_64
help
Aarch64 is a 64-bit architecture developed by ARM Holdings.
http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
http://en.wikipedia.org/wiki/ARM
config BR2_i386
bool "i386"
select BR2_USE_MMU
help
Intel i386 architecture compatible microprocessor
http://en.wikipedia.org/wiki/I386
config BR2_m68k
bool "m68k"
# MMU support is set by the subarchitecture file, arch/Config.in.m68k
help
Motorola 68000 family microprocessor
http://en.wikipedia.org/wiki/M68k
config BR2_microblazeel
bool "Microblaze AXI (little endian)"
select BR2_USE_MMU
help
Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
bus based architecture (little endian)
http://www.xilinx.com
http://en.wikipedia.org/wiki/Microblaze
config BR2_microblazebe
bool "Microblaze non-AXI (big endian)"
select BR2_USE_MMU
help
Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
bus based architecture (non-AXI, big endian)
http://www.xilinx.com
http://en.wikipedia.org/wiki/Microblaze
config BR2_mips
bool "MIPS (big endian)"
select BR2_USE_MMU
help
MIPS is a RISC microprocessor from MIPS Technologies. Big
endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
config BR2_mipsel
bool "MIPS (little endian)"
select BR2_USE_MMU
help
MIPS is a RISC microprocessor from MIPS Technologies. Little
endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
config BR2_mips64
bool "MIPS64 (big endian)"
select BR2_ARCH_IS_64
select BR2_USE_MMU
help
MIPS is a RISC microprocessor from MIPS Technologies. Big
endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
config BR2_mips64el
bool "MIPS64 (little endian)"
select BR2_ARCH_IS_64
select BR2_USE_MMU
help
MIPS is a RISC microprocessor from MIPS Technologies. Little
endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
config BR2_nios2
bool "Nios II"
select BR2_USE_MMU
help
Nios II is a soft core processor from Altera Corporation.
http://www.altera.com/
http://en.wikipedia.org/wiki/Nios_II
config BR2_or1k
bool "OpenRISC"
select BR2_USE_MMU
help
OpenRISC is a free and open processor for embedded system.
http://openrisc.io
config BR2_powerpc
bool "PowerPC"
select BR2_USE_MMU
help
PowerPC is a RISC architecture created by Apple-IBM-Motorola
alliance. Big endian.
http://www.power.org/
http://en.wikipedia.org/wiki/Powerpc
config BR2_powerpc64
bool "PowerPC64 (big endian)"
select BR2_ARCH_IS_64
select BR2_USE_MMU
help
PowerPC is a RISC architecture created by Apple-IBM-Motorola
alliance. Big endian.
http://www.power.org/
http://en.wikipedia.org/wiki/Powerpc
config BR2_powerpc64le
bool "PowerPC64 (little endian)"
select BR2_ARCH_IS_64
select BR2_USE_MMU
help
PowerPC is a RISC architecture created by Apple-IBM-Motorola
alliance. Little endian.
http://www.power.org/
http://en.wikipedia.org/wiki/Powerpc
config BR2_riscv
bool "RISCV"
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
help
RISC-V is an open, free Instruction Set Architecture created
by the UC Berkeley Architecture Research group and supported
and promoted by RISC-V Foundation.
https://riscv.org/
https://en.wikipedia.org/wiki/RISC-V
config BR2_s390x
bool "s390x"
select BR2_ARCH_IS_64
select BR2_USE_MMU
help
s390x is a big-endian architecture made by IBM.
http://www.ibm.com/
http://en.wikipedia.org/wiki/IBM_System/390
config BR2_sh
bool "SuperH"
select BR2_USE_MMU
help
SuperH (or SH) is a 32-bit reduced instruction set computer
(RISC) instruction set architecture (ISA) developed by
Hitachi.
http://www.hitachi.com/
http://en.wikipedia.org/wiki/SuperH
config BR2_sparc
bool "SPARC"
select BR2_USE_MMU
help
SPARC (from Scalable Processor Architecture) is a RISC
instruction set architecture (ISA) developed by Sun
Microsystems.
http://www.oracle.com/sun
http://en.wikipedia.org/wiki/Sparc
config BR2_sparc64
bool "SPARC64"
select BR2_ARCH_IS_64
select BR2_USE_MMU
help
SPARC (from Scalable Processor Architecture) is a RISC
instruction set architecture (ISA) developed by Sun
Microsystems.
http://www.oracle.com/sun
http://en.wikipedia.org/wiki/Sparc
config BR2_x86_64
bool "x86_64"
select BR2_ARCH_IS_64
select BR2_USE_MMU
help
x86-64 is an extension of the x86 instruction set (Intel i386
architecture compatible microprocessor).
http://en.wikipedia.org/wiki/X86_64
config BR2_xtensa
bool "Xtensa"
# MMU support is set by the subarchitecture file, arch/Config.in.xtensa
help
Xtensa is a Tensilica processor IP architecture.
http://en.wikipedia.org/wiki/Xtensa
http://www.tensilica.com/
endchoice
# For some architectures or specific cores, our internal toolchain
# backend is not suitable (like, missing support in upstream gcc, or
# no ChipCo fork exists...)
config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
bool
config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
bool
default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
# The following symbols are selected by the individual
# Config.in.$ARCH files
config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
bool
config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_ARCH_NEEDS_GCC_AT_LEAST_9
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
config BR2_ARCH_NEEDS_GCC_AT_LEAST_10
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_ARCH_NEEDS_GCC_AT_LEAST_11
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_10
config BR2_ARCH_NEEDS_GCC_AT_LEAST_12
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
# The following string values are defined by the individual
# Config.in.$ARCH files
config BR2_ARCH
string
config BR2_NORMALIZED_ARCH
string
config BR2_ENDIAN
string
config BR2_GCC_TARGET_ARCH
string
config BR2_GCC_TARGET_ABI
string
config BR2_GCC_TARGET_NAN
string
config BR2_GCC_TARGET_FP32_MODE
string
config BR2_GCC_TARGET_CPU
string
# The value of this option will be passed as --with-fpu=<value> when
# building gcc (internal backend) or -mfpu=<value> in the toolchain
# wrapper (external toolchain)
config BR2_GCC_TARGET_FPU
string
# The value of this option will be passed as --with-float=<value> when
# building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
# wrapper (external toolchain)
config BR2_GCC_TARGET_FLOAT_ABI
string
# The value of this option will be passed as --with-mode=<value> when
# building gcc (internal backend) or -m<value> in the toolchain
# wrapper (external toolchain)
config BR2_GCC_TARGET_MODE
string
# Must be selected by binary formats that support shared libraries.
config BR2_BINFMT_SUPPORTS_SHARED
bool
# Must match the name of the architecture from readelf point of view,
# i.e the "Machine:" field of readelf output. See get_machine_name()
# in binutils/readelf.c for the list of possible values.
config BR2_READELF_ARCH_NAME
string
if BR2_arcle || BR2_arceb
source "arch/Config.in.arc"
endif
if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
source "arch/Config.in.arm"
endif
if BR2_m68k
source "arch/Config.in.m68k"
endif
if BR2_microblazeel || BR2_microblazebe
source "arch/Config.in.microblaze"
endif
if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
source "arch/Config.in.mips"
endif
if BR2_nios2
source "arch/Config.in.nios2"
endif
if BR2_or1k
source "arch/Config.in.or1k"
endif
if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
source "arch/Config.in.powerpc"
endif
if BR2_riscv
source "arch/Config.in.riscv"
endif
if BR2_s390x
source "arch/Config.in.s390x"
endif
if BR2_sh
source "arch/Config.in.sh"
endif
if BR2_sparc || BR2_sparc64
source "arch/Config.in.sparc"
endif
if BR2_i386 || BR2_x86_64
source "arch/Config.in.x86"
endif
if BR2_xtensa
source "arch/Config.in.xtensa"
endif
# Set up target binary format
choice
prompt "Target Binary Format"
default BR2_BINFMT_ELF if BR2_USE_MMU
default BR2_BINFMT_FLAT
config BR2_BINFMT_ELF
bool "ELF"
depends on BR2_USE_MMU
select BR2_BINFMT_SUPPORTS_SHARED
help
ELF (Executable and Linkable Format) is a format for libraries
and executables used across different architectures and
operating systems.
config BR2_BINFMT_FLAT
bool "FLAT"
depends on !BR2_USE_MMU
help
FLAT binary is a relatively simple and lightweight executable
format based on the original a.out format. It is widely used
in environment where no MMU is available.
endchoice
# Set up flat binary type
choice
prompt "FLAT Binary type"
default BR2_BINFMT_FLAT_ONE
depends on BR2_BINFMT_FLAT
config BR2_BINFMT_FLAT_ONE
bool "One memory region"
help
All segments are linked into one memory region.
config BR2_BINFMT_FLAT_SHARED
bool "Shared binary"
depends on BR2_m68k
# Even though this really generates shared binaries, there is no libdl
# and dlopen() cannot be used. So packages that require shared
# libraries cannot be built. Therefore, we don't select
# BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
# Although this adds -static to the compilation, that's not a problem
# because the -mid-shared-library option overrides it.
help
Allow to load and link indiviual FLAT binaries at run time.
endchoice
endmenu # Target options

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choice
prompt "Target CPU"
default BR2_arc770d
depends on BR2_arc
help
Specific CPU to use
config BR2_arc750d
bool "ARC 750D"
config BR2_arc770d
bool "ARC 770D"
config BR2_archs38
bool "ARC HS38"
help
Generic ARC HS capable of running Linux, i.e. with MMU,
caches and 32-bit multiplier. Also it corresponds to the
default configuration in older GNU toolchain versions.
config BR2_archs38_64mpy
bool "ARC HS38 with 64-bit mpy"
help
Fully featured ARC HS capable of running Linux, i.e. with
MMU, caches and 64-bit multiplier.
If you're not sure which version of ARC HS core you build
for use this one.
config BR2_archs38_full
bool "ARC HS38 with Quad MAC & FPU"
help
Fully featured ARC HS with additional support for
- Dual- and quad multiply and MC oprations
- Double-precision FPU
It corresponds to "hs38_slc_full" ARC HS template in
ARChitect.
config BR2_archs4x_rel31
bool "ARC HS48 rel 31"
help
Build for HS48 release 3.1
config BR2_archs4x
bool "ARC HS48"
help
Latest release of HS48 processor
- Dual and Quad multiply and MAC operations
- Double-precision FPU
endchoice
# Choice of atomic instructions presence
config BR2_ARC_ATOMIC_EXT
bool "Atomic extension (LLOCK/SCOND instructions)"
default y if BR2_arc770d
default y if BR2_archs38 || BR2_archs38_64mpy || BR2_archs38_full
default y if BR2_archs4x_rel31 || BR2_archs4x
config BR2_ARCH
default "arc" if BR2_arcle
default "arceb" if BR2_arceb
config BR2_NORMALIZED_ARCH
default "arc"
config BR2_arc
bool
default y if BR2_arcle || BR2_arceb
config BR2_ENDIAN
default "LITTLE" if BR2_arcle
default "BIG" if BR2_arceb
config BR2_GCC_TARGET_CPU
default "arc700" if BR2_arc750d
default "arc700" if BR2_arc770d
default "archs" if BR2_archs38
default "hs38" if BR2_archs38_64mpy
default "hs38_linux" if BR2_archs38_full
default "hs4x_rel31" if BR2_archs4x_rel31
default "hs4x" if BR2_archs4x
config BR2_READELF_ARCH_NAME
default "ARCompact" if BR2_arc750d || BR2_arc770d
default "ARCv2" if BR2_archs38 || BR2_archs38_64mpy || BR2_archs38_full
default "ARCv2" if BR2_archs4x_rel31 || BR2_archs4x
choice
prompt "MMU Page Size"
default BR2_ARC_PAGE_SIZE_8K
help
MMU starting from version 3 (found in ARC 770) and now
version 4 (found in ARC HS38) allows the selection of the
page size during ASIC design creation.
The following options are available for MMU v3 and v4: 4kB,
8kB and 16 kB.
The default is 8 kB (that really matches the only page size
in MMU v2). It is important to build a toolchain with page
size matching the hardware configuration. Otherwise
user-space applications will fail at runtime.
config BR2_ARC_PAGE_SIZE_4K
bool "4KB"
depends on !BR2_arc750d
config BR2_ARC_PAGE_SIZE_8K
bool "8KB"
help
This is the one and only option available for MMUv2 and
default value for MMU v3 and v4.
config BR2_ARC_PAGE_SIZE_16K
bool "16KB"
depends on !BR2_arc750d
endchoice
config BR2_ARC_PAGE_SIZE
string
default "4K" if BR2_ARC_PAGE_SIZE_4K
default "8K" if BR2_ARC_PAGE_SIZE_8K
default "16K" if BR2_ARC_PAGE_SIZE_16K
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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# arm cpu features
config BR2_ARM_CPU_HAS_NEON
bool
# for some cores, NEON support is optional
config BR2_ARM_CPU_MAYBE_HAS_NEON
bool
# For some cores, the FPU is optional
config BR2_ARM_CPU_MAYBE_HAS_FPU
bool
config BR2_ARM_CPU_HAS_FPU
bool
# for some cores, VFPv2 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV2
bool
select BR2_ARM_CPU_MAYBE_HAS_FPU
config BR2_ARM_CPU_HAS_VFPV2
bool
select BR2_ARM_CPU_HAS_FPU
# for some cores, VFPv3 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV3
bool
select BR2_ARM_CPU_MAYBE_HAS_VFPV2
config BR2_ARM_CPU_HAS_VFPV3
bool
select BR2_ARM_CPU_HAS_VFPV2
# for some cores, VFPv4 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV4
bool
select BR2_ARM_CPU_MAYBE_HAS_VFPV3
config BR2_ARM_CPU_HAS_VFPV4
bool
select BR2_ARM_CPU_HAS_VFPV3
# FPv4 is always optional
config BR2_ARM_CPU_MAYBE_HAS_FPV4
bool
select BR2_ARM_CPU_MAYBE_HAS_FPU
config BR2_ARM_CPU_HAS_FPV4
bool
select BR2_ARM_CPU_HAS_FPU
# FPv5 is always optional
config BR2_ARM_CPU_MAYBE_HAS_FPV5
bool
select BR2_ARM_CPU_MAYBE_HAS_FPV4
config BR2_ARM_CPU_HAS_FPV5
bool
select BR2_ARM_CPU_HAS_FPV4
config BR2_ARM_CPU_HAS_FP_ARMV8
bool
select BR2_ARM_CPU_HAS_VFPV4
config BR2_ARM_CPU_HAS_ARM
bool
config BR2_ARM_CPU_HAS_THUMB
bool
config BR2_ARM_CPU_HAS_THUMB2
bool
config BR2_ARM_CPU_ARMV4
bool
select BR2_USE_MMU
config BR2_ARM_CPU_ARMV5
bool
select BR2_USE_MMU
config BR2_ARM_CPU_ARMV6
bool
select BR2_USE_MMU
config BR2_ARM_CPU_ARMV7A
bool
select BR2_USE_MMU
config BR2_ARM_CPU_ARMV7M
bool
config BR2_ARM_CPU_ARMV8A
bool
select BR2_USE_MMU
choice
prompt "Target Architecture Variant"
default BR2_cortex_a53 if BR2_ARCH_IS_64
default BR2_arm926t
help
Specific CPU variant to use
if !BR2_ARCH_IS_64
comment "armv4 cores"
config BR2_arm920t
bool "arm920t"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV4
config BR2_arm922t
bool "arm922t"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV4
config BR2_fa526
bool "fa526/626"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV4
config BR2_strongarm
bool "strongarm sa110/sa1100"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV4
comment "armv5 cores"
config BR2_arm926t
bool "arm926t"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_MAYBE_HAS_VFPV2
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV5
config BR2_iwmmxt
bool "iwmmxt"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV5
config BR2_xscale
bool "xscale"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV5
comment "armv6 cores"
config BR2_arm1136j_s
bool "arm1136j-s"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
config BR2_arm1136jf_s
bool "arm1136jf-s"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_VFPV2
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
config BR2_arm1176jz_s
bool "arm1176jz-s"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
config BR2_arm1176jzf_s
bool "arm1176jzf-s"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_VFPV2
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
config BR2_arm11mpcore
bool "mpcore"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_MAYBE_HAS_VFPV2
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
comment "armv7a cores"
config BR2_cortex_a5
bool "cortex-A5"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_MAYBE_HAS_NEON
select BR2_ARM_CPU_MAYBE_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
config BR2_cortex_a7
bool "cortex-A7"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
config BR2_cortex_a8
bool "cortex-A8"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV3
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
config BR2_cortex_a9
bool "cortex-A9"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_MAYBE_HAS_NEON
select BR2_ARM_CPU_MAYBE_HAS_VFPV3
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
config BR2_cortex_a12
bool "cortex-A12"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
config BR2_cortex_a15
bool "cortex-A15"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
config BR2_cortex_a15_a7
bool "cortex-A15/A7 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_cortex_a17
bool "cortex-A17"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_cortex_a17_a7
bool "cortex-A17/A7 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_pj4
bool "pj4"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_VFPV3
select BR2_ARM_CPU_ARMV7A
# Cortex-M cores are only supported for little endian configurations
if BR2_arm
comment "armv7m cores"
config BR2_cortex_m3
bool "cortex-M3"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7M
config BR2_cortex_m4
bool "cortex-M4"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_MAYBE_HAS_FPV4
select BR2_ARM_CPU_ARMV7M
config BR2_cortex_m7
bool "cortex-M7"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_MAYBE_HAS_FPV5
select BR2_ARM_CPU_ARMV7M
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
endif # BR2_arm
endif # !BR2_ARCH_IS_64
comment "armv8 cores"
config BR2_cortex_a32
bool "cortex-A32"
depends on !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_cortex_a35
bool "cortex-A35"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_cortex_a53
bool "cortex-A53"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
config BR2_cortex_a57
bool "cortex-A57"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
config BR2_cortex_a57_a53
bool "cortex-A57/A53 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_cortex_a72
bool "cortex-A72"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_cortex_a72_a53
bool "cortex-A72/A53 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_cortex_a73
bool "cortex-A73"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_cortex_a73_a35
bool "cortex-A73/A35 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_cortex_a73_a53
bool "cortex-A73/A53 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_emag
bool "emag"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_exynos_m1
bool "exynos-m1"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_falkor
bool "falkor"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_phecda
bool "phecda"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_qdf24xx
bool "qdf24xx"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_thunderx
bool "thunderx (aka octeontx)"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_thunderxt81
bool "thunderxt81 (aka octeontx81)"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_thunderxt83
bool "thunderxt83 (aka octeontx83)"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_thunderxt88
bool "thunderxt88"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_thunderxt88p1
bool "thunderxt88p1"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_xgene1
bool "xgene1"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
comment "armv8.1a cores"
config BR2_thunderx2t99
bool "thunderx2t99"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_thunderx2t99p1
bool "thunderx2t99p1"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_vulcan
bool "vulcan"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
comment "armv8.2a cores"
config BR2_cortex_a55
bool "cortex-A55"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
config BR2_cortex_a75
bool "cortex-A75"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
config BR2_cortex_a75_a55
bool "cortex-A75/A55 big.LITTLE"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
config BR2_cortex_a76
bool "cortex-A76"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_cortex_a76_a55
bool "cortex-A76/A55 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_neoverse_n1
bool "neoverse-N1 (aka ares)"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_tsv110
bool "tsv110"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
comment "armv8.4a cores"
config BR2_saphira
bool "saphira"
depends on BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
endchoice
config BR2_ARM_ENABLE_NEON
bool "Enable NEON SIMD extension support"
depends on BR2_ARM_CPU_MAYBE_HAS_NEON
select BR2_ARM_CPU_HAS_NEON
help
For some CPU cores, the NEON SIMD extension is optional.
Select this option if you are certain your particular
implementation has NEON support and you want to use it.
config BR2_ARM_ENABLE_VFP
bool "Enable VFP extension support"
depends on BR2_ARM_CPU_MAYBE_HAS_FPU
select BR2_ARM_CPU_HAS_FPV5 if BR2_ARM_CPU_MAYBE_HAS_FPV5
select BR2_ARM_CPU_HAS_FPV4 if BR2_ARM_CPU_MAYBE_HAS_FPV4
select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
help
For some CPU cores, the VFP extension is optional. Select
this option if you are certain your particular
implementation has VFP support and you want to use it.
choice
prompt "Target ABI"
default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_FPU
default BR2_ARM_EABI
depends on BR2_arm || BR2_armeb
help
Application Binary Interface to use. The Application Binary
Interface describes the calling conventions (how arguments
are passed to functions, how the return value is passed, how
system calls are made, etc.).
config BR2_ARM_EABI
bool "EABI"
help
The EABI is currently the standard ARM ABI, which is used in
most projects. It supports both the 'soft' floating point
model (in which floating point instructions are emulated in
software) and the 'softfp' floating point model (in which
floating point instructions are executed using an hardware
floating point unit, but floating point arguments to
functions are passed in integer registers).
The 'softfp' floating point model is link-compatible with
the 'soft' floating point model, i.e you can link a library
built 'soft' with some other code built 'softfp'.
However, passing the floating point arguments in integer
registers is a bit inefficient, so if your ARM processor has
a floating point unit, and you don't have pre-compiled
'soft' or 'softfp' code, using the EABIhf ABI will provide
better floating point performances.
If your processor does not have a floating point unit, then
you must use this ABI.
config BR2_ARM_EABIHF
bool "EABIhf"
depends on BR2_ARM_CPU_HAS_FPU
help
The EABIhf is an extension of EABI which supports the 'hard'
floating point model. This model uses the floating point
unit to execute floating point instructions, and passes
floating point arguments in floating point registers.
It is more efficient than EABI for floating point related
workload. However, it does not allow to link against code
that has been pre-built for the 'soft' or 'softfp' floating
point models.
If your processor has a floating point unit, and you don't
depend on existing pre-compiled code, this option is most
likely the best choice.
endchoice
choice
prompt "Floating point strategy"
default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8
default BR2_ARM_FPU_FPV5D16 if BR2_ARM_CPU_HAS_FPV5
default BR2_ARM_FPU_FPV4D16 if BR2_ARM_CPU_HAS_FPV4
default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_FPU
config BR2_ARM_SOFT_FLOAT
bool "Soft float"
depends on BR2_ARM_EABI
select BR2_SOFT_FLOAT
help
This option allows to use software emulated floating
point. It should be used for ARM cores that do not include a
Vector Floating Point unit, such as ARMv5 cores (ARM926 for
example) or certain ARMv6 cores.
config BR2_ARM_FPU_VFPV2
bool "VFPv2"
depends on BR2_ARM_CPU_HAS_VFPV2
help
This option allows to use the VFPv2 floating point unit, as
available in some ARMv5 processors (ARM926EJ-S) and some
ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
MPCore).
Note that this option is also safe to use for newer cores
such as Cortex-A, because the VFPv3 and VFPv4 units are
backward compatible with VFPv2.
config BR2_ARM_FPU_VFPV3
bool "VFPv3"
depends on BR2_ARM_CPU_HAS_VFPV3
help
This option allows to use the VFPv3 floating point unit, as
available in some ARMv7 processors (Cortex-A{8, 9}). This
option requires a VFPv3 unit that has 32 double-precision
registers, which is not necessarily the case in all SOCs
based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
instead, which is guaranteed to work on all Cortex-A{8, 9}.
Note that this option is also safe to use for newer cores
that have a VFPv4 unit, because VFPv4 is backward compatible
with VFPv3. They must of course also have 32
double-precision registers.
config BR2_ARM_FPU_VFPV3D16
bool "VFPv3-D16"
depends on BR2_ARM_CPU_HAS_VFPV3
help
This option allows to use the VFPv3 floating point unit, as
available in some ARMv7 processors (Cortex-A{8, 9}). This
option requires a VFPv3 unit that has 16 double-precision
registers, which is generally the case in all SOCs based on
Cortex-A{8, 9}, even though VFPv3 is technically optional on
Cortex-A9. This is the safest option for those cores.
Note that this option is also safe to use for newer cores
such that have a VFPv4 unit, because the VFPv4 is backward
compatible with VFPv3.
config BR2_ARM_FPU_VFPV4
bool "VFPv4"
depends on BR2_ARM_CPU_HAS_VFPV4
help
This option allows to use the VFPv4 floating point unit, as
available in some ARMv7 processors (Cortex-A{5, 7, 12,
15}). This option requires a VFPv4 unit that has 32
double-precision registers, which is not necessarily the
case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
unsure, you should probably use VFPv4-D16 instead.
Note that if you want binary code that works on all ARMv7
cores, including the earlier Cortex-A{8, 9}, you should
instead select VFPv3.
config BR2_ARM_FPU_VFPV4D16
bool "VFPv4-D16"
depends on BR2_ARM_CPU_HAS_VFPV4
help
This option allows to use the VFPv4 floating point unit, as
available in some ARMv7 processors (Cortex-A{5, 7, 12,
15}). This option requires a VFPv4 unit that has 16
double-precision registers, which is always available on
Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
Cortex-A7.
Note that if you want binary code that works on all ARMv7
cores, including the earlier Cortex-A{8, 9}, you should
instead select VFPv3-D16.
config BR2_ARM_FPU_NEON
bool "NEON"
depends on BR2_ARM_CPU_HAS_NEON
help
This option allows to use the NEON SIMD unit, as available
in some ARMv7 processors, as a floating-point unit. It
should however be noted that using NEON for floating point
operations doesn't provide a complete compatibility with the
IEEE 754.
config BR2_ARM_FPU_NEON_VFPV4
bool "NEON/VFPv4"
depends on BR2_ARM_CPU_HAS_VFPV4
depends on BR2_ARM_CPU_HAS_NEON
help
This option allows to use both the VFPv4 and the NEON SIMD
units for floating point operations. Note that some ARMv7
cores do not necessarily have VFPv4 and/or NEON support, for
example on Cortex-A5 and Cortex-A7, support for VFPv4 and
NEON is optional.
config BR2_ARM_FPU_FPV4D16
bool "FPv4-D16"
depends on BR2_ARM_CPU_HAS_FPV4
help
This option allows to use the FPv4-SP (single precision)
floating point unit, as available in some ARMv7m processors
(Cortex-M4).
config BR2_ARM_FPU_FPV5D16
bool "FPv5-D16"
depends on BR2_ARM_CPU_HAS_FPV5
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
help
This option allows to use the FPv5-SP (single precision)
floating point unit, as available in some ARMv7m processors
(Cortex-M7).
Note that if you want binary code that works on the earlier
Cortex-M4, you should instead select FPv4-D16.
config BR2_ARM_FPU_FPV5DPD16
bool "FPv5-DP-D16"
depends on BR2_ARM_CPU_HAS_FPV5
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
help
This option allows to use the FPv5-DP (double precision)
floating point unit, as available in some ARMv7m processors
(Cortex-M7).
Note that if you want binary code that works on the earlier
Cortex-M4, you should instead select FPv4-D16.
config BR2_ARM_FPU_FP_ARMV8
bool "FP-ARMv8"
depends on BR2_ARM_CPU_HAS_FP_ARMV8
help
This option allows to use the ARMv8 floating point unit.
config BR2_ARM_FPU_NEON_FP_ARMV8
bool "NEON/FP-ARMv8"
depends on BR2_ARM_CPU_HAS_FP_ARMV8
depends on BR2_ARM_CPU_HAS_NEON
help
This option allows to use both the ARMv8 floating point unit
and the NEON SIMD unit for floating point operations.
endchoice
choice
prompt "ARM instruction set"
depends on BR2_arm || BR2_armeb
config BR2_ARM_INSTRUCTIONS_ARM
bool "ARM"
depends on BR2_ARM_CPU_HAS_ARM
help
This option instructs the compiler to generate regular ARM
instructions, that are all 32 bits wide.
config BR2_ARM_INSTRUCTIONS_THUMB
bool "Thumb"
depends on BR2_ARM_CPU_HAS_THUMB
# Thumb-1 and VFP are not compatible
depends on BR2_ARM_SOFT_FLOAT
help
This option instructions the compiler to generate Thumb
instructions, which allows to mix 16 bits instructions and
32 bits instructions. This generally provides a much smaller
compiled binary size.
comment "Thumb1 is not compatible with VFP"
depends on BR2_ARM_CPU_HAS_THUMB
depends on !BR2_ARM_SOFT_FLOAT
config BR2_ARM_INSTRUCTIONS_THUMB2
bool "Thumb2"
depends on BR2_ARM_CPU_HAS_THUMB2
help
This option instructions the compiler to generate Thumb2
instructions, which allows to mix 16 bits instructions and
32 bits instructions. This generally provides a much smaller
compiled binary size.
endchoice
choice
prompt "MMU Page Size"
default BR2_ARM64_PAGE_SIZE_4K
depends on BR2_aarch64 || BR2_aarch64_be
help
The default is 4KB, and you should probably keep this unless
you know what you are doing. In particular, the kernel
configuration must match this choice. If your kernel is
built by Buildroot, the kernel configuration is
automatically adjusted, but not if you built your kernel
outside of Buildroot.
config BR2_ARM64_PAGE_SIZE_4K
bool "4KB"
config BR2_ARM64_PAGE_SIZE_64K
bool "64KB"
endchoice
config BR2_ARM64_PAGE_SIZE
string
default "4K" if BR2_ARM64_PAGE_SIZE_4K
default "64K" if BR2_ARM64_PAGE_SIZE_64K
config BR2_ARCH
default "arm" if BR2_arm
default "armeb" if BR2_armeb
default "aarch64" if BR2_aarch64
default "aarch64_be" if BR2_aarch64_be
config BR2_NORMALIZED_ARCH
default "arm" if BR2_arm || BR2_armeb
default "arm64" if BR2_aarch64 || BR2_aarch64_be
config BR2_ENDIAN
default "LITTLE" if (BR2_arm || BR2_aarch64)
default "BIG" if (BR2_armeb || BR2_aarch64_be)
config BR2_GCC_TARGET_CPU
# armv4
default "arm920t" if BR2_arm920t
default "arm922t" if BR2_arm922t
default "fa526" if BR2_fa526
default "strongarm" if BR2_strongarm
# armv5
default "arm926ej-s" if BR2_arm926t
default "iwmmxt" if BR2_iwmmxt
default "xscale" if BR2_xscale
# armv6
default "arm1136j-s" if BR2_arm1136j_s
default "arm1136jf-s" if BR2_arm1136jf_s
default "arm1176jz-s" if BR2_arm1176jz_s
default "arm1176jzf-s" if BR2_arm1176jzf_s
default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
default "mpcorenovfp" if BR2_arm11mpcore
# armv7a
default "cortex-a5" if BR2_cortex_a5
default "cortex-a7" if BR2_cortex_a7
default "cortex-a8" if BR2_cortex_a8
default "cortex-a9" if BR2_cortex_a9
default "cortex-a12" if BR2_cortex_a12
default "cortex-a15" if BR2_cortex_a15
default "cortex-a15.cortex-a7" if BR2_cortex_a15_a7
default "cortex-a17" if BR2_cortex_a17
default "cortex-a17.cortex-a7" if BR2_cortex_a17_a7
default "marvell-pj4" if BR2_pj4
# armv7m
default "cortex-m3" if BR2_cortex_m3
default "cortex-m4" if BR2_cortex_m4
default "cortex-m7" if BR2_cortex_m7
# armv8a
default "cortex-a32" if BR2_cortex_a32
default "cortex-a35" if BR2_cortex_a35
default "cortex-a53" if BR2_cortex_a53
default "cortex-a57" if BR2_cortex_a57
default "cortex-a57.cortex-a53" if BR2_cortex_a57_a53
default "cortex-a72" if BR2_cortex_a72
default "cortex-a72.cortex-a53" if BR2_cortex_a72_a53
default "cortex-a73" if BR2_cortex_a73
default "cortex-a73.cortex-a35" if BR2_cortex_a73_a35
default "cortex-a73.cortex-a53" if BR2_cortex_a73_a53
default "emag" if BR2_emag
default "exynos-m1" if BR2_exynos_m1
default "falkor" if BR2_falkor
default "phecda" if BR2_phecda
default "qdf24xx" if BR2_qdf24xx
default "thunderx" if BR2_thunderx && !BR2_TOOLCHAIN_GCC_AT_LEAST_9
default "octeontx" if BR2_thunderx && BR2_TOOLCHAIN_GCC_AT_LEAST_9
default "thunderxt81" if BR2_thunderxt81 && !BR2_TOOLCHAIN_GCC_AT_LEAST_9
default "octeontx81" if BR2_thunderxt81 && BR2_TOOLCHAIN_GCC_AT_LEAST_9
default "thunderxt83" if BR2_thunderxt83 && !BR2_TOOLCHAIN_GCC_AT_LEAST_9
default "octeontx83" if BR2_thunderxt83 && BR2_TOOLCHAIN_GCC_AT_LEAST_9
default "thunderxt88" if BR2_thunderxt88
default "thunderxt88p1" if BR2_thunderxt88p1
default "xgene1" if BR2_xgene1
# armv8.1a
default "thunderx2t99" if BR2_thunderx2t99
default "thunderx2t99p1" if BR2_thunderx2t99p1
default "vulcan" if BR2_vulcan
# armv8.2a
default "cortex-a55" if BR2_cortex_a55
default "cortex-a75" if BR2_cortex_a75
default "cortex-a75.cortex-a55" if BR2_cortex_a75_a55
default "cortex-a76" if BR2_cortex_a76
default "cortex-a76.cortex-a55" if BR2_cortex_a76_a55
default "neoverse-n1" if BR2_neoverse_n1
default "tsv110" if BR2_tsv110
# armv8.4a
default "saphira" if BR2_saphira
config BR2_GCC_TARGET_ABI
default "aapcs-linux" if BR2_arm || BR2_armeb
default "lp64" if BR2_aarch64 || BR2_aarch64_be
config BR2_GCC_TARGET_FPU
default "vfp" if BR2_ARM_FPU_VFPV2
default "vfpv3" if BR2_ARM_FPU_VFPV3
default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
default "vfpv4" if BR2_ARM_FPU_VFPV4
default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
default "neon" if BR2_ARM_FPU_NEON
default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
default "fpv4-sp-d16" if BR2_ARM_FPU_FPV4D16
default "fpv5-sp-d16" if BR2_ARM_FPU_FPV5D16
default "fpv5-d16" if BR2_ARM_FPU_FPV5DPD16
default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8
default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8
depends on BR2_arm || BR2_armeb
config BR2_GCC_TARGET_FLOAT_ABI
default "soft" if BR2_ARM_SOFT_FLOAT
default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
config BR2_GCC_TARGET_MODE
default "arm" if BR2_ARM_INSTRUCTIONS_ARM
default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2
config BR2_READELF_ARCH_NAME
default "ARM" if BR2_arm || BR2_armeb
default "AArch64" if BR2_aarch64 || BR2_aarch64_be
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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config BR2_ARCH
default "m68k" if BR2_m68k
config BR2_NORMALIZED_ARCH
default "m68k"
config BR2_ENDIAN
default "BIG"
# symbols used to distinguish between m68k and coldfire
# for gcc multilib
config BR2_m68k_m68k
bool
config BR2_m68k_cf
bool
# coldfire variants will be added later
choice
prompt "Target CPU"
default BR2_m68k_68040
depends on BR2_m68k
help
Specific CPU variant to use
config BR2_m68k_68040
bool "68040"
select BR2_m68k_m68k
select BR2_USE_MMU
config BR2_m68k_cf5208
bool "5208"
select BR2_m68k_cf
select BR2_SOFT_FLOAT
endchoice
config BR2_GCC_TARGET_CPU
default "68040" if BR2_m68k_68040
default "5208" if BR2_m68k_cf5208
config BR2_READELF_ARCH_NAME
default "MC68000"
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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config BR2_ARCH
default "microblazeel" if BR2_microblazeel
default "microblaze" if BR2_microblazebe
config BR2_NORMALIZED_ARCH
default "microblaze"
config BR2_ENDIAN
default "LITTLE" if BR2_microblazeel
default "BIG" if BR2_microblazebe
config BR2_READELF_ARCH_NAME
default "Xilinx MicroBlaze"
config BR2_microblaze
bool
default y if BR2_microblazeel || BR2_microblazebe
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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# mips default CPU ISAs
config BR2_MIPS_CPU_MIPS32
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS32R2
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS32R3
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS32R5
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_MIPS_CPU_MIPS32R6
bool
select BR2_MIPS_NAN_2008
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_MIPS_CPU_MIPS64
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS64R2
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS64R3
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS64R5
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_MIPS_CPU_MIPS64R6
bool
select BR2_MIPS_NAN_2008
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
choice
prompt "Target Architecture Variant"
default BR2_mips_32 if BR2_mips || BR2_mipsel
default BR2_mips_64 if BR2_mips64 || BR2_mips64el
depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el
help
Specific CPU variant to use
64bit capable: 64, 64r2, 64r3, 64r5, 64r6
non-64bit capable: 32, 32r2, 32r3, 32r5, 32r6
config BR2_mips_32
bool "Generic MIPS32"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32
config BR2_mips_32r2
bool "Generic MIPS32R2"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R2
config BR2_mips_32r3
bool "Generic MIPS32R3"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R3
config BR2_mips_32r5
bool "Generic MIPS32R5"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R5
config BR2_mips_32r6
bool "Generic MIPS32R6"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R6
config BR2_mips_interaptiv
bool "interAptiv"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R2
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_mips_m5150
bool "M5150"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R5
select BR2_MIPS_NAN_2008
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_mips_m6250
bool "M6250"
depends on !BR2_ARCH_IS_64
select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
select BR2_MIPS_CPU_MIPS32R6
config BR2_mips_p5600
bool "P5600"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R5
select BR2_MIPS_NAN_2008
config BR2_mips_xburst
bool "XBurst"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R2
help
The Ingenic XBurst is a MIPS32R2 microprocessor. It has a
bug in the FPU that can generate incorrect results in
certain cases. The problem shows up when you have several
fused madd instructions in sequence with dependant
operands. This requires the -mno-fused-madd compiler option
to be used in order to prevent emitting these instructions.
See http://www.ingenic.com/en/?xburst.html
config BR2_mips_64
bool "Generic MIPS64"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64
config BR2_mips_64r2
bool "Generic MIPS64R2"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R2
config BR2_mips_64r3
bool "Generic MIPS64R3"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R3
config BR2_mips_64r5
bool "Generic MIPS64R5"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R5
config BR2_mips_64r6
bool "Generic MIPS64R6"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R6
config BR2_mips_i6400
bool "I6400"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R6
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_mips_octeon2
bool "Octeon II"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R2
help
Marvell (formerly Cavium Networks) Octeon II CN60XX
processors.
config BR2_mips_octeon3
bool "Octeon III"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R3
help
Marvell (formerly Cavium Networks) Octeon III CN7XXX
processors.
config BR2_mips_p6600
bool "P6600"
depends on BR2_ARCH_IS_64
select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
select BR2_MIPS_CPU_MIPS64R6
endchoice
choice
prompt "Target ABI"
default BR2_MIPS_NABI32
depends on BR2_mips64 || BR2_mips64el
help
Application Binary Interface to use
config BR2_MIPS_NABI32
bool "n32"
depends on BR2_ARCH_IS_64
select BR2_KERNEL_64_USERLAND_32
config BR2_MIPS_NABI64
bool "n64"
depends on BR2_ARCH_IS_64
endchoice
config BR2_MIPS_SOFT_FLOAT
bool "Use soft-float"
default y
depends on !BR2_mips_octeon3 # hard-float only
select BR2_SOFT_FLOAT
help
If your target CPU does not have a Floating Point Unit (FPU)
or a kernel FPU emulator, but you still wish to support
floating point functions, then everything will need to be
compiled with soft floating point support (-msoft-float).
choice
prompt "FP mode"
default BR2_MIPS_FP32_MODE_XX
depends on !BR2_ARCH_IS_64 && !BR2_MIPS_SOFT_FLOAT
help
MIPS32 supports different FP modes (32,xx,64). Information
about FP modes can be found here:
https://sourceware.org/binutils/docs/as/MIPS-Options.html
https://dmz-portal.imgtec.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#5._Generating_modeless_code
config BR2_MIPS_FP32_MODE_32
bool "32"
depends on !BR2_MIPS_CPU_MIPS32R6
config BR2_MIPS_FP32_MODE_XX
bool "xx"
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_MIPS_FP32_MODE_64
bool "64"
depends on !BR2_MIPS_CPU_MIPS32
endchoice
config BR2_GCC_TARGET_FP32_MODE
default "32" if BR2_MIPS_FP32_MODE_32
default "xx" if BR2_MIPS_FP32_MODE_XX
default "64" if BR2_MIPS_FP32_MODE_64
config BR2_MIPS_NAN_LEGACY
bool
config BR2_MIPS_NAN_2008
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
choice
prompt "Target NaN"
default BR2_MIPS_ENABLE_NAN_2008
depends on BR2_mips_32r5 || BR2_mips_64r5
help
MIPS supports two different NaN encodings, legacy and 2008.
Information about MIPS NaN encodings can be found here:
https://sourceware.org/binutils/docs/as/MIPS-NaN-Encodings.html
config BR2_MIPS_ENABLE_NAN_LEGACY
bool "legacy"
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_ENABLE_NAN_2008
bool "2008"
depends on !BR2_MIPS_SOFT_FLOAT
select BR2_MIPS_NAN_2008
endchoice
config BR2_GCC_TARGET_NAN
default "legacy" if BR2_MIPS_NAN_LEGACY
default "2008" if BR2_MIPS_NAN_2008
config BR2_ARCH
default "mips" if BR2_mips
default "mipsel" if BR2_mipsel
default "mips64" if BR2_mips64
default "mips64el" if BR2_mips64el
config BR2_NORMALIZED_ARCH
default "mips"
config BR2_ENDIAN
default "LITTLE" if BR2_mipsel || BR2_mips64el
default "BIG" if BR2_mips || BR2_mips64
config BR2_GCC_TARGET_ARCH
default "mips32" if BR2_mips_32
default "mips32r2" if BR2_mips_32r2
default "mips32r3" if BR2_mips_32r3
default "mips32r5" if BR2_mips_32r5
default "mips32r6" if BR2_mips_32r6
default "interaptiv" if BR2_mips_interaptiv
default "m5101" if BR2_mips_m5150
default "m6201" if BR2_mips_m6250
default "p5600" if BR2_mips_p5600
default "mips32r2" if BR2_mips_xburst
default "mips64" if BR2_mips_64
default "mips64r2" if BR2_mips_64r2
default "mips64r3" if BR2_mips_64r3
default "mips64r5" if BR2_mips_64r5
default "mips64r6" if BR2_mips_64r6
default "i6400" if BR2_mips_i6400
default "octeon2" if BR2_mips_octeon2
default "octeon3" if BR2_mips_octeon3
default "p6600" if BR2_mips_p6600
config BR2_MIPS_OABI32
bool
default y if BR2_mips || BR2_mipsel
config BR2_GCC_TARGET_ABI
default "32" if BR2_MIPS_OABI32
default "n32" if BR2_MIPS_NABI32
default "64" if BR2_MIPS_NABI64
config BR2_READELF_ARCH_NAME
default "MIPS R3000"
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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config BR2_ARCH
default "nios2"
config BR2_NORMALIZED_ARCH
default "nios2"
config BR2_ENDIAN
default "LITTLE"
config BR2_READELF_ARCH_NAME
default "Altera Nios II"
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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config BR2_ARCH
default "or1k"
config BR2_NORMALIZED_ARCH
default "openrisc"
config BR2_ENDIAN
default "BIG"
config BR2_READELF_ARCH_NAME
default "OpenRISC 1000"
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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config BR2_POWERPC_CPU_HAS_ALTIVEC
bool
config BR2_POWERPC_CPU_HAS_VSX
bool
config BR2_POWERPC_CPU_HAS_SPE
bool
choice
prompt "Target Architecture Variant"
default BR2_generic_powerpc
help
Specific CPU variant to use
config BR2_generic_powerpc
bool "generic"
# No C library supports this variant on ppc64le
depends on !BR2_powerpc64le
config BR2_powerpc_401
bool "401"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_403
bool "403"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_405
bool "405"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_405fp
bool "405 with FPU"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_440
bool "440"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_440fp
bool "440 with FPU"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_464
bool "464"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_464fp
bool "464 with FPU"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_476
bool "476"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_476fp
bool "476 with FPU"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_505
bool "505"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_602
bool "602"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_603
bool "603"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_603e
bool "603e"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_604
bool "604"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_604e
bool "604e"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_620
bool "620"
# No C library supports this variant on ppc64le
depends on !BR2_powerpc64le
config BR2_powerpc_630
bool "630"
# No C library supports this variant on ppc64le
depends on !BR2_powerpc64le
config BR2_powerpc_740
bool "740"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_7400
bool "7400"
depends on !BR2_ARCH_IS_64
select BR2_POWERPC_CPU_HAS_ALTIVEC
config BR2_powerpc_7450
bool "7450"
depends on !BR2_ARCH_IS_64
select BR2_POWERPC_CPU_HAS_ALTIVEC
config BR2_powerpc_750
bool "750"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_821
bool "821"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_823
bool "823"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_860
bool "860"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_970
bool "970"
select BR2_POWERPC_CPU_HAS_ALTIVEC
config BR2_powerpc_8540
bool "8540 / e500v1"
depends on !BR2_ARCH_IS_64
select BR2_POWERPC_CPU_HAS_SPE
config BR2_powerpc_8548
bool "8548 / e500v2"
depends on !BR2_ARCH_IS_64
select BR2_POWERPC_CPU_HAS_SPE
config BR2_powerpc_e300c2
bool "e300c2"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_e300c3
bool "e300c3"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_e500mc
bool "e500mc"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_e5500
bool "e5500"
depends on !BR2_powerpc64le
config BR2_powerpc_e6500
bool "e6500"
depends on !BR2_powerpc64le
select BR2_POWERPC_CPU_HAS_ALTIVEC
config BR2_powerpc_power4
bool "power4"
# No C library supports this variant on ppc64le
depends on !BR2_powerpc64le
config BR2_powerpc_power5
bool "power5"
# No C library supports this variant on ppc64le
depends on !BR2_powerpc64le
config BR2_powerpc_power6
bool "power6"
select BR2_POWERPC_CPU_HAS_ALTIVEC
config BR2_powerpc_power7
bool "power7"
select BR2_POWERPC_CPU_HAS_ALTIVEC
select BR2_POWERPC_CPU_HAS_VSX
config BR2_powerpc_power8
bool "power8"
select BR2_POWERPC_CPU_HAS_ALTIVEC
select BR2_POWERPC_CPU_HAS_VSX
endchoice
choice
prompt "Target ABI"
default BR2_powerpc_SPE if BR2_POWERPC_CPU_HAS_SPE
default BR2_powerpc_CLASSIC
help
Application Binary Interface to use
config BR2_powerpc_CLASSIC
bool "Classic"
depends on !BR2_POWERPC_CPU_HAS_SPE
config BR2_powerpc_SPE
bool "SPE"
depends on BR2_POWERPC_CPU_HAS_SPE
endchoice
config BR2_POWERPC_SOFT_FLOAT
bool "Use soft-float"
select BR2_SOFT_FLOAT
help
If your target CPU does not have a Floating Point Unit (FPU)
or a kernel FPU emulator, but you still wish to support
floating point functions, then everything will need to be
compiled with soft floating point support (-msoft-float).
config BR2_ARCH
default "powerpc" if BR2_powerpc
default "powerpc64" if BR2_powerpc64
default "powerpc64le" if BR2_powerpc64le
config BR2_NORMALIZED_ARCH
default "powerpc"
config BR2_ENDIAN
default "BIG" if BR2_powerpc || BR2_powerpc64
default "LITTLE" if BR2_powerpc64le
config BR2_GCC_TARGET_CPU
default "401" if BR2_powerpc_401
default "403" if BR2_powerpc_403
default "405" if BR2_powerpc_405
default "405fp" if BR2_powerpc_405fp
default "440" if BR2_powerpc_440
default "440fp" if BR2_powerpc_440fp
default "464" if BR2_powerpc_464
default "464fp" if BR2_powerpc_464fp
default "476" if BR2_powerpc_476
default "476fp" if BR2_powerpc_476fp
default "505" if BR2_powerpc_505
default "602" if BR2_powerpc_602
default "603" if BR2_powerpc_603
default "603e" if BR2_powerpc_603e
default "604" if BR2_powerpc_604
default "604e" if BR2_powerpc_604e
default "620" if BR2_powerpc_620
default "630" if BR2_powerpc_630
default "740" if BR2_powerpc_740
default "7400" if BR2_powerpc_7400
default "7450" if BR2_powerpc_7450
default "750" if BR2_powerpc_750
default "821" if BR2_powerpc_821
default "823" if BR2_powerpc_823
default "860" if BR2_powerpc_860
default "970" if BR2_powerpc_970
default "8540" if BR2_powerpc_8540
default "8548" if BR2_powerpc_8548
default "e300c2" if BR2_powerpc_e300c2
default "e300c3" if BR2_powerpc_e300c3
default "e500mc" if BR2_powerpc_e500mc
default "e5500" if BR2_powerpc_e5500
default "e6500" if BR2_powerpc_e6500
default "power4" if BR2_powerpc_power4
default "power5" if BR2_powerpc_power5
default "power6" if BR2_powerpc_power6
default "power7" if BR2_powerpc_power7
default "power8" if BR2_powerpc_power8
config BR2_READELF_ARCH_NAME
default "PowerPC" if BR2_powerpc
default "PowerPC64" if BR2_powerpc64 || BR2_powerpc64le
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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# RISC-V CPU ISA extensions.
config BR2_RISCV_ISA_RVI
bool
config BR2_RISCV_ISA_RVM
bool
config BR2_RISCV_ISA_RVA
bool
config BR2_RISCV_ISA_RVF
bool
config BR2_RISCV_ISA_RVD
bool
config BR2_RISCV_ISA_RVC
bool
choice
prompt "Target Architecture Variant"
default BR2_riscv_g
config BR2_riscv_g
bool "General purpose (G)"
select BR2_RISCV_ISA_RVI
select BR2_RISCV_ISA_RVM
select BR2_RISCV_ISA_RVA
select BR2_RISCV_ISA_RVF
select BR2_RISCV_ISA_RVD
help
General purpose (G) is equivalent to IMAFD.
config BR2_riscv_custom
bool "Custom architecture"
select BR2_RISCV_ISA_RVI
select BR2_RISCV_ISA_CUSTOM_RVA
endchoice
if BR2_riscv_custom
comment "Instruction Set Extensions"
config BR2_RISCV_ISA_CUSTOM_RVM
bool "Integer Multiplication and Division (M)"
select BR2_RISCV_ISA_RVM
config BR2_RISCV_ISA_CUSTOM_RVA
bool "Atomic Instructions (A)"
select BR2_RISCV_ISA_RVA
config BR2_RISCV_ISA_CUSTOM_RVF
bool "Single-precision Floating-point (F)"
select BR2_RISCV_ISA_RVF
config BR2_RISCV_ISA_CUSTOM_RVD
bool "Double-precision Floating-point (D)"
depends on BR2_RISCV_ISA_RVF
select BR2_RISCV_ISA_RVD
config BR2_RISCV_ISA_CUSTOM_RVC
bool "Compressed Instructions (C)"
select BR2_RISCV_ISA_RVC
endif
choice
prompt "Target Architecture Size"
default BR2_RISCV_64
config BR2_RISCV_32
bool "32-bit"
select BR2_USE_MMU
config BR2_RISCV_64
bool "64-bit"
select BR2_ARCH_IS_64
endchoice
config BR2_RISCV_USE_MMU
bool "MMU support"
default y
depends on BR2_RISCV_64
select BR2_USE_MMU
help
Enable this option if your RISC-V core has a MMU (Memory
Management Unit).
choice
prompt "Target ABI"
default BR2_RISCV_ABI_ILP32D if !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
default BR2_RISCV_ABI_ILP32F if !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
default BR2_RISCV_ABI_ILP32 if !BR2_ARCH_IS_64
default BR2_RISCV_ABI_LP64D if BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
default BR2_RISCV_ABI_LP64F if BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
default BR2_RISCV_ABI_LP64 if BR2_ARCH_IS_64
config BR2_RISCV_ABI_ILP32
bool "ilp32"
depends on !BR2_ARCH_IS_64
config BR2_RISCV_ABI_ILP32F
bool "ilp32f"
depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
config BR2_RISCV_ABI_ILP32D
bool "ilp32d"
depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
config BR2_RISCV_ABI_LP64
bool "lp64"
depends on BR2_ARCH_IS_64
config BR2_RISCV_ABI_LP64F
bool "lp64f"
depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
depends on BR2_USE_MMU
config BR2_RISCV_ABI_LP64D
bool "lp64d"
depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
endchoice
config BR2_ARCH
default "riscv32" if !BR2_ARCH_IS_64
default "riscv64" if BR2_ARCH_IS_64
config BR2_NORMALIZED_ARCH
default "riscv"
config BR2_ENDIAN
default "LITTLE"
config BR2_GCC_TARGET_ABI
default "ilp32" if BR2_RISCV_ABI_ILP32
default "ilp32f" if BR2_RISCV_ABI_ILP32F
default "ilp32d" if BR2_RISCV_ABI_ILP32D
default "lp64" if BR2_RISCV_ABI_LP64
default "lp64f" if BR2_RISCV_ABI_LP64F
default "lp64d" if BR2_RISCV_ABI_LP64D
config BR2_READELF_ARCH_NAME
default "RISC-V"
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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choice
prompt "Target Architecture Variant"
help
Specific CPU variant to use
config BR2_s390x_z13
bool "z13"
config BR2_s390x_z14
bool "z14"
config BR2_s390x_z15
bool "z15"
endchoice
config BR2_ARCH
default "s390x" if BR2_s390x
config BR2_NORMALIZED_ARCH
default "s390"
config BR2_ENDIAN
default "BIG"
config BR2_GCC_TARGET_ARCH
default "arch11" if BR2_s390x_z13
default "arch12" if BR2_s390x_z14
default "arch13" if BR2_s390x_z15
config BR2_READELF_ARCH_NAME
default "IBM S/390" if BR2_s390x

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choice
prompt "Target Architecture Variant"
default BR2_sh4
depends on BR2_sh
help
Specific CPU variant to use
config BR2_sh4
bool "sh4 (SH4 little endian)"
config BR2_sh4eb
bool "sh4eb (SH4 big endian)"
config BR2_sh4a
bool "sh4a (SH4A little endian)"
config BR2_sh4aeb
bool "sh4aeb (SH4A big endian)"
endchoice
config BR2_ARCH
default "sh4" if BR2_sh4
default "sh4eb" if BR2_sh4eb
default "sh4a" if BR2_sh4a
default "sh4aeb" if BR2_sh4aeb
config BR2_NORMALIZED_ARCH
default "sh"
config BR2_ENDIAN
default "LITTLE" if BR2_sh4 || BR2_sh4a
default "BIG" if BR2_sh4eb || BR2_sh4aeb
config BR2_READELF_ARCH_NAME
default "Renesas / SuperH SH"
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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choice
prompt "Target Architecture Variant"
default BR2_sparc_v8 if BR2_sparc
default BR2_sparc_v9 if BR2_sparc64
depends on BR2_sparc || BR2_sparc64
help
Specific CPU variant to use
config BR2_sparc_v8
bool "v8"
depends on BR2_sparc
config BR2_sparc_leon3
bool "leon3"
depends on BR2_sparc
config BR2_sparc_v9
bool "v9"
depends on BR2_sparc64
endchoice
config BR2_ARCH
default "sparc" if BR2_sparc
default "sparc64" if BR2_sparc64
config BR2_NORMALIZED_ARCH
default "sparc" if BR2_sparc
default "sparc64" if BR2_sparc64
config BR2_ENDIAN
default "BIG"
config BR2_GCC_TARGET_CPU
default "leon3" if BR2_sparc_leon3
default "v8" if BR2_sparc_v8
default "ultrasparc" if BR2_sparc_v9
config BR2_READELF_ARCH_NAME
default "Sparc" if BR2_sparc
default "Sparc v9" if BR2_sparc64
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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# i386/x86_64 cpu features
config BR2_X86_CPU_HAS_MMX
bool
config BR2_X86_CPU_HAS_3DNOW
bool
config BR2_X86_CPU_HAS_SSE
bool
config BR2_X86_CPU_HAS_SSE2
bool
config BR2_X86_CPU_HAS_SSE3
bool
config BR2_X86_CPU_HAS_SSSE3
bool
config BR2_X86_CPU_HAS_SSE4
bool
config BR2_X86_CPU_HAS_SSE42
bool
config BR2_X86_CPU_HAS_AVX
bool
config BR2_X86_CPU_HAS_AVX2
bool
config BR2_X86_CPU_HAS_AVX512
bool
# This list of CPU architecture variant is (loosely) ordered according
# to the gcc documentation at
# https://gcc.gnu.org/onlinedocs/gcc-11.2.0/gcc/x86-Options.html
choice
prompt "Target Architecture Variant"
default BR2_x86_i586 if BR2_i386
depends on BR2_i386 || BR2_x86_64
help
Specific CPU variant to use
config BR2_x86_i486
bool "i486"
depends on !BR2_x86_64
config BR2_x86_i586
bool "i586"
depends on !BR2_x86_64
config BR2_x86_x1000
bool "x1000"
depends on !BR2_x86_64
help
The Intel X1000 is a Pentium class microprocessor in the
Quark (sub-Atom) Product Line. The X1000 has a bug on the
lock prefix requiring that prefix must be stripped at build
time.
See https://en.wikipedia.org/wiki/Intel_Quark
config BR2_x86_i686
bool "i686"
depends on !BR2_x86_64
config BR2_x86_pentiumpro
bool "pentium pro"
depends on !BR2_x86_64
config BR2_x86_pentium_mmx
bool "pentium MMX"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
config BR2_x86_pentium_m
bool "pentium mobile"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
config BR2_x86_pentium2
bool "pentium2"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
config BR2_x86_pentium3
bool "pentium3"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
config BR2_x86_pentium4
bool "pentium4"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
config BR2_x86_prescott
bool "prescott"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
config BR2_x86_x86_64
bool "x86-64"
depends on BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
help
This option corresponds to -march=x86-64, documented as a
"Generic CPU with 64-bit extensions" by the GCC
documentation. It is a 64-bit CPU with MMX, SSE and SSE2
support.
config BR2_x86_x86_64_v2
bool "x86-64-v2"
depends on BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
help
This option corresponds to the x86-64-v2 micro-architecture
level, as defined by the x86-64 psABI document, see
https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
It is close to the Nehalem CPU architecture, and is
applicable for CPUs that support CMPXCHG16B, LAHF-SAHF,
POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3.
config BR2_x86_x86_64_v3
bool "x86-64-v3"
depends on BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
help
This option corresponds to the x86-64-v3 micro-architecture
level, as defined by the x86-64 psABI document, see
https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
It is close to the Haswell CPU architecture, and is
applicable for CPUs that support all of x86-64-v2 plus AVX,
AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE.
config BR2_x86_x86_64_v4
bool "x86-64-v4"
depends on BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
help
This option corresponds to the x86-64-v4 micro-architecture
level, as defined by the x86-64 psABI document, see
https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
It is applicable for CPUs that support all of x86-64-v3 plus
AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL.
config BR2_x86_nocona
bool "nocona"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
config BR2_x86_core2
bool "core2"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
config BR2_x86_corei7
bool "corei7"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
help
This option is deprecated. Since gcc 4.9, the gcc option
"nehalem" is preferred. Use BR2_x86_nehalem instead.
config BR2_x86_nehalem
bool "nehalem"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_westmere
bool "westmere"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_corei7_avx
bool "corei7-avx"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
help
This option is deprecated. Since gcc 4.9, the gcc option
"sandybridge" is preferred. Use BR2_x86_sandybridge instead.
config BR2_x86_sandybridge
bool "sandybridge"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_core_avx2
bool "core-avx2"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
help
This option is deprecated. Since gcc 4.9, the gcc option
"haswell" is preferred. Use BR2_x86_haswell instead.
config BR2_x86_haswell
bool "haswell"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_broadwell
bool "broadwell"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_skylake
bool "skylake"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_x86_atom
bool "atom"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
help
This option is deprecated. Since gcc 4.9, the gcc option
"bonnell" is preferred. Use BR2_x86_bonnell instead.
config BR2_x86_bonnell
bool "bonnell"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_silvermont
bool "silvermont"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_x86_goldmont
bool "goldmont"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_x86_goldmont_plus
bool "goldmont-plus"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_x86_tremont
bool "tremont"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_x86_skylake_avx512
bool "skylake-avx512"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_x86_cannonlake
bool "cannonlake"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
config BR2_x86_icelake_client
bool "icelake-client"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
config BR2_x86_icelake_server
bool "icelake-server"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
config BR2_x86_cascadelake
bool "cascadelake"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_x86_cooperlake
bool "cooperlake"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_10
config BR2_x86_tigerlake
bool "tigerlake"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
config BR2_x86_sapphirerapids
bool "sapphirerapids"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
config BR2_x86_alderlake
bool "alderlake"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
config BR2_x86_rocketlake
bool "rocketlake"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
select BR2_X86_CPU_HAS_AVX512
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
config BR2_x86_k6
bool "k6"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
config BR2_x86_k6_2
bool "k6-2"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_3DNOW
config BR2_x86_athlon
bool "athlon"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_3DNOW
config BR2_x86_athlon_4
bool "athlon-4"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_3DNOW
config BR2_x86_opteron
bool "opteron"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
config BR2_x86_opteron_sse3
bool "opteron w/ SSE3"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
config BR2_x86_barcelona
bool "barcelona"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
config BR2_x86_jaguar
bool "jaguar"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
config BR2_x86_steamroller
bool "steamroller"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
config BR2_x86_geode
bool "geode"
# Don't include MMX support because there several variant of geode
# processor, some with MMX support, some without.
# See: http://en.wikipedia.org/wiki/Geode_%28processor%29
depends on !BR2_x86_64
config BR2_x86_c3
bool "Via/Cyrix C3 (Samuel/Ezra cores)"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_3DNOW
config BR2_x86_c32
bool "Via C3-2 (Nehemiah cores)"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
config BR2_x86_winchip_c6
bool "IDT Winchip C6"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
config BR2_x86_winchip2
bool "IDT Winchip 2"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
endchoice
config BR2_ARCH
default "i486" if BR2_x86_i486
default "i586" if BR2_x86_i586
default "i586" if BR2_x86_x1000
default "i586" if BR2_x86_pentium_mmx
default "i586" if BR2_x86_geode
default "i586" if BR2_x86_c3
default "i686" if BR2_x86_c32
default "i586" if BR2_x86_winchip_c6
default "i586" if BR2_x86_winchip2
# We use the property of Kconfig that the first match of a
# list of default will be chosen. So the following entry will
# not match for all BR2_i386=y configurations, but only the
# ones that didn't match any of the previous cases (i486,
# i586).
default "i686" if BR2_i386
default "x86_64" if BR2_x86_64
config BR2_NORMALIZED_ARCH
default "i386" if !BR2_x86_64
default "x86_64" if BR2_x86_64
config BR2_ENDIAN
default "LITTLE"
config BR2_GCC_TARGET_ARCH
default "i486" if BR2_x86_i486
default "i586" if BR2_x86_i586
default "i586" if BR2_x86_x1000
default "pentium-mmx" if BR2_x86_pentium_mmx
default "i686" if BR2_x86_i686
default "pentiumpro" if BR2_x86_pentiumpro
default "pentium-m" if BR2_x86_pentium_m
default "pentium2" if BR2_x86_pentium2
default "pentium3" if BR2_x86_pentium3
default "pentium4" if BR2_x86_pentium4
default "prescott" if BR2_x86_prescott
default "x86-64" if BR2_x86_x86_64
default "x86-64-v2" if BR2_x86_x86_64_v2
default "x86-64-v3" if BR2_x86_x86_64_v3
default "x86-64-v4" if BR2_x86_x86_64_v4
default "nocona" if BR2_x86_nocona
default "core2" if BR2_x86_core2
default "corei7" if BR2_x86_corei7
default "nehalem" if BR2_x86_nehalem
default "corei7-avx" if BR2_x86_corei7_avx
default "sandybridge" if BR2_x86_sandybridge
default "core-avx2" if BR2_x86_core_avx2
default "haswell" if BR2_x86_haswell
default "broadwell" if BR2_x86_broadwell
default "skylake" if BR2_x86_skylake
default "atom" if BR2_x86_atom
default "bonnell" if BR2_x86_bonnell
default "westmere" if BR2_x86_westmere
default "silvermont" if BR2_x86_silvermont
default "goldmont" if BR2_x86_goldmont
default "goldmont-plus" if BR2_x86_goldmont_plus
default "tremont" if BR2_x86_tremont
default "skylake-avx512" if BR2_x86_skylake_avx512
default "cannonlake" if BR2_x86_cannonlake
default "icelake-client" if BR2_x86_icelake_client
default "icelake-server" if BR2_x86_icelake_server
default "cascadelake" if BR2_x86_cascadelake
default "cooperlake" if BR2_x86_cooperlake
default "tigerlake" if BR2_x86_tigerlake
default "sapphirerapids" if BR2_x86_sapphirerapids
default "alderlake" if BR2_x86_alderlake
default "rocketlake" if BR2_x86_rocketlake
default "k8" if BR2_x86_opteron
default "k8-sse3" if BR2_x86_opteron_sse3
default "barcelona" if BR2_x86_barcelona
default "btver2" if BR2_x86_jaguar
default "bdver3" if BR2_x86_steamroller
default "k6" if BR2_x86_k6
default "k6-2" if BR2_x86_k6_2
default "athlon" if BR2_x86_athlon
default "athlon-4" if BR2_x86_athlon_4
default "winchip-c6" if BR2_x86_winchip_c6
default "winchip2" if BR2_x86_winchip2
default "c3" if BR2_x86_c3
default "c3-2" if BR2_x86_c32
default "geode" if BR2_x86_geode
config BR2_READELF_ARCH_NAME
default "Intel 80386" if BR2_i386
default "Advanced Micro Devices X86-64" if BR2_x86_64
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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choice
prompt "Target Architecture Variant"
default BR2_xtensa_fsf
depends on BR2_xtensa
config BR2_XTENSA_CUSTOM
bool "Custom Xtensa processor configuration"
config BR2_xtensa_fsf
bool "fsf - Default configuration"
select BR2_USE_MMU
endchoice
config BR2_XTENSA_OVERLAY_FILE
string "Overlay file for custom configuration"
depends on BR2_XTENSA_CUSTOM
help
Enter the path to the overlay tarball for a custom processor
configuration.
These overlay files are tar packages with updated
configuration files for various toolchain packages and Xtensa
processor configurations. They are provided by the processor
vendor or directly from Tensilica.
The path can be either absolute, or relative to the top
directory of buildroot.
choice
prompt "Target Architecture Endianness"
default BR2_XTENSA_LITTLE_ENDIAN
depends on BR2_XTENSA_CUSTOM
config BR2_XTENSA_LITTLE_ENDIAN
bool "Little endian"
config BR2_XTENSA_BIG_ENDIAN
bool "Big endian"
endchoice
config BR2_XTENSA_USE_MMU
bool "MMU support"
default y
depends on BR2_XTENSA_CUSTOM
select BR2_USE_MMU
help
Enable this option if your Xtensa core has a MMU (Memory
Management Unit).
config BR2_ENDIAN
default "LITTLE" if BR2_XTENSA_LITTLE_ENDIAN
default "BIG" if BR2_xtensa_fsf || BR2_XTENSA_BIG_ENDIAN
config BR2_ARCH
default "xtensa" if BR2_xtensa
config BR2_NORMALIZED_ARCH
default "xtensa"
config BR2_READELF_ARCH_NAME
default "Tensilica Xtensa Processor"
# vim: ft=kconfig
# -*- mode:kconfig; -*-

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################################################################################
#
# Architecture-specific definitions
#
################################################################################
# Allow GCC target configuration settings to be optionally
# overwritten by architecture specific makefiles.
# Makefiles must use the GCC_TARGET_* variables below instead
# of the BR2_GCC_TARGET_* versions.
GCC_TARGET_ARCH := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
GCC_TARGET_ABI := $(call qstrip,$(BR2_GCC_TARGET_ABI))
GCC_TARGET_NAN := $(call qstrip,$(BR2_GCC_TARGET_NAN))
GCC_TARGET_FP32_MODE := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE))
GCC_TARGET_CPU := $(call qstrip,$(BR2_GCC_TARGET_CPU))
GCC_TARGET_FPU := $(call qstrip,$(BR2_GCC_TARGET_FPU))
GCC_TARGET_FLOAT_ABI := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
GCC_TARGET_MODE := $(call qstrip,$(BR2_GCC_TARGET_MODE))
# Explicitly set LD's "max-page-size" instead of relying on some defaults
ifeq ($(BR2_ARC_PAGE_SIZE_4K)$(BR2_ARM64_PAGE_SIZE_4K),y)
ARCH_TOOLCHAIN_WRAPPER_OPTS += -Wl,-z,max-page-size=4096 -Wl,-z,common-page-size=4096
else ifeq ($(BR2_ARC_PAGE_SIZE_8K),y)
ARCH_TOOLCHAIN_WRAPPER_OPTS += -Wl,-z,max-page-size=8192 -Wl,-z,common-page-size=8192
else ifeq ($(BR2_ARC_PAGE_SIZE_16K),y)
ARCH_TOOLCHAIN_WRAPPER_OPTS += -Wl,-z,max-page-size=16384 -Wl,-z,common-page-size=16384
else ifeq ($(BR2_ARM64_PAGE_SIZE_64K),y)
ARCH_TOOLCHAIN_WRAPPER_OPTS += -Wl,-z,max-page-size=65536 -Wl,-z,common-page-size=65536
endif
# Include any architecture specific makefiles.
-include $(sort $(wildcard arch/arch.mk.*))

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ifeq ($(BR2_arc),y)
# -matomic is always required when the ARC core has the atomic extensions
ifeq ($(BR2_ARC_ATOMIC_EXT),y)
ARCH_TOOLCHAIN_WRAPPER_OPTS += -matomic
endif
endif

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#
# Configure the GCC_TARGET_ARCH variable and append the
# appropriate RISC-V ISA extensions.
#
ifeq ($(BR2_riscv),y)
ifeq ($(BR2_RISCV_64),y)
GCC_TARGET_ARCH := rv64i
else
GCC_TARGET_ARCH := rv32i
endif
ifeq ($(BR2_RISCV_ISA_RVM),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)m
endif
ifeq ($(BR2_RISCV_ISA_RVA),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)a
endif
ifeq ($(BR2_RISCV_ISA_RVF),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)f
endif
ifeq ($(BR2_RISCV_ISA_RVD),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)d
endif
ifeq ($(BR2_RISCV_ISA_RVC),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
endif
# Starting from gcc 12.x, csr and fence instructions have been
# separated from the base I instruction set, and special -march
# suffixes are needed to enable their support. In Buildroot, we assume
# all RISC-V cores that support Linux implement those instructions, so
# we unconditionally enable those extensions.
ifeq ($(BR2_TOOLCHAIN_GCC_AT_LEAST_12),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zicsr_zifencei
endif
endif

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BR_ARCH_XTENSA_OVERLAY_FILE = $(call qstrip,$(BR2_XTENSA_OVERLAY_FILE))
ifeq ($(BR_BUILDING)$(BR2_XTENSA_CUSTOM):$(BR_ARCH_XTENSA_OVERLAY_FILE),yy:)
$(error No xtensa overlay file provided. Check your BR2_XTENSA_OVERLAY_FILE setting)
endif
################################################################################
# This variable can be used by packages that need to extract the overlay.
#
# ARCH_XTENSA_OVERLAY_FILE is the path to the overlay tarball; empty if not
# using any overlay
#
# Example:
# ifneq ($(ARCH_XTENSA_OVERLAY_FILE),)
# tar xf $(ARCH_XTENSA_OVERLAY_FILE) -C $(@D) --strip-components=1 gcc
# endif
################################################################################
ifneq ($(filter http://% https://% ftp://% scp://%,$(BR_ARCH_XTENSA_OVERLAY_FILE)),)
ARCH_XTENSA_OVERLAY_URL = $(BR_ARCH_XTENSA_OVERLAY_FILE)
ARCH_XTENSA_OVERLAY_FILE = $($(PKG)_DL_DIR)/$(notdir $(BR_ARCH_XTENSA_OVERLAY_FILE))
# Do not check that file, we can't know its hash
BR_NO_CHECK_HASH_FOR += $(notdir $(ARCH_XTENSA_OVERLAY_URL))
else
ARCH_XTENSA_OVERLAY_FILE = $(BR_ARCH_XTENSA_OVERLAY_FILE)
endif
################################################################################
# arch-xtensa-overlay-extract -- extract an extensa overlay
#
# argument 1 is the path in which to extract
# argument 2 is the component to extract, one of: gcc, binutils, gdb, linux,
# u-boot
#
# Example:
# $(call arch-xtensa-overlay-extract,/path/to/overlay.tar,$(@D),gcc)
################################################################################
define arch-xtensa-overlay-extract
$(call suitable-extractor,$(ARCH_XTENSA_OVERLAY_FILE)) \
$(ARCH_XTENSA_OVERLAY_FILE) | \
$(TAR) --strip-components=1 -C $(1) $(TAR_OPTIONS) - $(2)
endef