generated from gaoyang3513/SDK_RK3288
1041 lines
27 KiB
C
1041 lines
27 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/video.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include "../common/pfuze.h"
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#include <asm/arch/mx6-ddr.h>
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#include <usb.h>
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#include <micrel.h>
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#ifdef CONFIG_CMD_SATA
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#include <asm/imx-common/sata.h>
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#endif
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#ifdef CONFIG_FSL_FASTBOOT
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#include <fsl_fastboot.h>
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#ifdef CONFIG_ANDROID_RECOVERY
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#include <recovery.h>
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#endif
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#endif /*CONFIG_FSL_FASTBOOT*/
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define I2C_PMIC 1
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#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
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#ifdef CONFIG_SCMEVB
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#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
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#else
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#define DISP0_PWR_EN IMX_GPIO_NR(1, 18)
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#endif
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int dram_init(void)
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{
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#ifdef CONFIG_INTERLEAVING_MODE
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u32 mdmisc = readl(MMDC_P0_BASE_ADDR + 0x18);
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gd->ram_size = imx_ddr_size() << ((mdmisc & 0x00000004) ? 1 : 0);
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#else
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gd->ram_size = imx_ddr_size();
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#endif
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return 0;
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}
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#if !defined(CONFIG_INTERLEAVING_MODE) && !defined(CONFIG_SCM_LPDDR2_512MB)
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
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}
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#endif
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#ifdef CONFIG_SCMHVB
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iomux_v3_cfg_t const uart_pads[] = {
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MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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#else
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static iomux_v3_cfg_t const uart_pads[] = {
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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#endif
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static iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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#ifdef CONFIG_QWKS_REV3
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MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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#else
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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#endif
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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/* AR8031 PHY Reset */
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MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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/* Reset AR8031 PHY */
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gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
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mdelay(10);
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gpio_set_value(IMX_GPIO_NR(1, 25), 1);
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udelay(100);
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}
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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#ifdef CONFIG_SCMEVB
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MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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#else
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MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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#endif
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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#ifndef CONFIG_QWKS_REV3
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MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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#endif
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MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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#ifdef CONFIG_MXC_SPI
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static iomux_v3_cfg_t const ecspi1_pads[] = {
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MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_spi(void)
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{
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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
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}
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
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}
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#endif
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static iomux_v3_cfg_t const rgb_pads[] = {
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MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void enable_rgb(struct display_info_t const *dev)
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{
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imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
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gpio_direction_output(DISP0_PWR_EN, 1);
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}
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
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.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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iomux_v3_cfg_t const pcie_pads[] = {
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MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
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MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
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};
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static void setup_pcie(void)
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{
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imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
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}
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iomux_v3_cfg_t const di0_pads[] = {
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MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
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MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
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MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
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};
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iomux_v3_cfg_t const lvds_pwr_en_pads[] = {
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MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg usdhc_cfg[3] = {
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{USDHC2_BASE_ADDR},
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{USDHC3_BASE_ADDR},
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{USDHC4_BASE_ADDR},
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};
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#ifdef CONFIG_SCMEVB
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
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#else
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#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
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#endif
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#ifdef CONFIG_QWKS_REV3
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#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 1)
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#else
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#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
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#endif
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int board_mmc_get_env_dev(int devno)
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{
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return devno - 1;
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}
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int mmc_map_to_kernel_blk(int devno)
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{
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return devno + 1;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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break;
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case USDHC3_BASE_ADDR:
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#ifdef CONFIG_SCMHVB
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ret = 1;
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#else
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ret = !gpio_get_value(USDHC3_CD_GPIO);
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#endif
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break;
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case USDHC4_BASE_ADDR:
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ret = 1; /* eMMC/uSDHC4 is always present */
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int ret;
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int i;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 SD2
|
|
* mmc1 SD3
|
|
* mmc2 eMMC
|
|
*/
|
|
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
|
switch (i) {
|
|
case 0:
|
|
imx_iomux_v3_setup_multiple_pads(
|
|
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
|
gpio_direction_input(USDHC2_CD_GPIO);
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
break;
|
|
case 1:
|
|
#ifndef CONFIG_SCMHVB
|
|
imx_iomux_v3_setup_multiple_pads(
|
|
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
|
gpio_direction_input(USDHC3_CD_GPIO);
|
|
#endif
|
|
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
break;
|
|
case 2:
|
|
imx_iomux_v3_setup_multiple_pads(
|
|
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
|
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
|
break;
|
|
default:
|
|
printf("Warning: you configured more ");
|
|
printf("USDHC controllers ");
|
|
printf("(%d) than supported by the board (%d)\n",
|
|
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int mx6_rgmii_rework(struct phy_device *phydev)
|
|
{
|
|
/* add necessary delays for RGMII,
|
|
* there are no board skew delays added
|
|
* additional rx data delay = 0, rx clk delay = 0.3ns, total = 1.5ns
|
|
* additional tx data delay = -0.42ns, tx clk delay = 0.96ns,
|
|
* total = 1.38ns
|
|
*/
|
|
|
|
if (ksz9031_phy_extended_write(phydev, 0x2,
|
|
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
|
|
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
|
0x0070))
|
|
return -EIO;
|
|
|
|
if (ksz9031_phy_extended_write(phydev, 0x2,
|
|
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
|
|
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
|
0x7777))
|
|
return -EIO;
|
|
|
|
if (ksz9031_phy_extended_write(phydev, 0x2,
|
|
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
|
|
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
|
0x0000))
|
|
return -EIO;
|
|
|
|
if (ksz9031_phy_extended_write(phydev, 0x2,
|
|
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
|
|
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
|
0x03f4))
|
|
return -EIO;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_phy_config(struct phy_device *phydev)
|
|
{
|
|
mx6_rgmii_rework(phydev);
|
|
|
|
if (phydev->drv->config)
|
|
phydev->drv->config(phydev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_VIDEO_IPUV3)
|
|
static void disable_lvds(struct display_info_t const *dev)
|
|
{
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
|
|
int reg = readl(&iomux->gpr[2]);
|
|
|
|
reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
|
|
IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
|
|
|
|
writel(reg, &iomux->gpr[2]);
|
|
#ifndef CONFIG_SCMEVB
|
|
gpio_direction_output(DISP0_PWR_EN, 0);
|
|
#endif
|
|
}
|
|
|
|
static void do_enable_hdmi(struct display_info_t const *dev)
|
|
{
|
|
disable_lvds(dev);
|
|
imx_enable_hdmi_phy();
|
|
}
|
|
|
|
static void enable_lvds(struct display_info_t const *dev)
|
|
{
|
|
struct iomuxc *iomux = (struct iomuxc *)
|
|
IOMUXC_BASE_ADDR;
|
|
u32 reg = readl(&iomux->gpr[2]);
|
|
|
|
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
|
|
IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
|
|
writel(reg, &iomux->gpr[2]);
|
|
#ifndef CONFIG_SCMEVB
|
|
gpio_direction_output(DISP0_PWR_EN, 1);
|
|
#endif
|
|
}
|
|
|
|
struct display_info_t const displays[] = {{
|
|
.bus = -1,
|
|
.addr = 0,
|
|
.pixfmt = IPU_PIX_FMT_RGB666,
|
|
.detect = NULL,
|
|
.enable = enable_lvds,
|
|
.mode = {
|
|
.name = "Hannstar-XGA",
|
|
.refresh = 60,
|
|
.xres = 1024,
|
|
.yres = 768,
|
|
.pixclock = 15385,
|
|
.left_margin = 220,
|
|
.right_margin = 40,
|
|
.upper_margin = 21,
|
|
.lower_margin = 7,
|
|
.hsync_len = 60,
|
|
.vsync_len = 10,
|
|
.sync = FB_SYNC_EXT,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
} }, {
|
|
.bus = -1,
|
|
.addr = 0,
|
|
.pixfmt = IPU_PIX_FMT_RGB24,
|
|
.detect = NULL,
|
|
.enable = do_enable_hdmi,
|
|
.mode = {
|
|
.name = "HDMI",
|
|
.refresh = 60,
|
|
.xres = 640,
|
|
.yres = 480,
|
|
.pixclock = 39721,
|
|
.left_margin = 48,
|
|
.right_margin = 16,
|
|
.upper_margin = 33,
|
|
.lower_margin = 10,
|
|
.hsync_len = 96,
|
|
.vsync_len = 2,
|
|
.sync = 0,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
} }, {
|
|
.bus = 0,
|
|
.addr = 0,
|
|
.pixfmt = IPU_PIX_FMT_RGB24,
|
|
.detect = NULL,
|
|
.enable = enable_rgb,
|
|
.mode = {
|
|
.name = "SEIKO-WVGA",
|
|
.refresh = 60,
|
|
.xres = 800,
|
|
.yres = 480,
|
|
.pixclock = 29850,
|
|
.left_margin = 89,
|
|
.right_margin = 164,
|
|
.upper_margin = 23,
|
|
.lower_margin = 10,
|
|
.hsync_len = 10,
|
|
.vsync_len = 10,
|
|
.sync = 0,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
} } };
|
|
size_t display_count = ARRAY_SIZE(displays);
|
|
|
|
static void setup_display(void)
|
|
{
|
|
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
int reg;
|
|
|
|
/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
|
|
imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
|
|
|
|
enable_ipu_clock();
|
|
imx_setup_hdmi();
|
|
|
|
/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
|
|
reg = readl(&mxc_ccm->CCGR3);
|
|
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
|
|
writel(reg, &mxc_ccm->CCGR3);
|
|
|
|
/* set LDB0, LDB1 clk select to 011/011 */
|
|
reg = readl(&mxc_ccm->cs2cdr);
|
|
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|
|
| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
|
|
reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
|
|
| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
|
|
writel(reg, &mxc_ccm->cs2cdr);
|
|
|
|
reg = readl(&mxc_ccm->cscmr2);
|
|
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
|
|
writel(reg, &mxc_ccm->cscmr2);
|
|
|
|
reg = readl(&mxc_ccm->chsccdr);
|
|
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
|
|
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
|
|
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
|
|
<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
|
|
writel(reg, &mxc_ccm->chsccdr);
|
|
|
|
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|
|
| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
|
|
| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|
|
| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
|
|
| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
|
|
| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|
|
| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
|
|
| IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
|
|
| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
|
|
writel(reg, &iomux->gpr[2]);
|
|
|
|
reg = readl(&iomux->gpr[3]);
|
|
reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
|
|
| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
|
|
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
|
|
<< IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
|
|
writel(reg, &iomux->gpr[3]);
|
|
#ifndef CONFIG_SCMEVB
|
|
imx_iomux_v3_setup_multiple_pads(lvds_pwr_en_pads,
|
|
ARRAY_SIZE(lvds_pwr_en_pads));
|
|
#endif
|
|
}
|
|
#endif /* CONFIG_VIDEO_IPUV3 */
|
|
|
|
/*
|
|
* Do not overwrite the console
|
|
* Use always serial for U-Boot console
|
|
*/
|
|
int overwrite_console(void)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
static void setup_fec(void)
|
|
{
|
|
return;
|
|
}
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
setup_iomux_enet();
|
|
setup_pcie();
|
|
|
|
return cpu_eth_init(bis);
|
|
}
|
|
|
|
#ifdef CONFIG_USB_EHCI_MX6
|
|
#define USB_OTHERREGS_OFFSET 0x800
|
|
#define UCTRL_PWR_POL (1 << 9)
|
|
|
|
static iomux_v3_cfg_t const usb_otg_pads[] = {
|
|
#ifdef CONFIG_QWKS_REV3
|
|
MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
#else
|
|
MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
#endif
|
|
#ifdef CONFIG_SCMEVB
|
|
MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
|
#else
|
|
MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
|
#endif
|
|
};
|
|
|
|
static iomux_v3_cfg_t const usb_hc1_pads[] = {
|
|
MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
static void setup_usb(void)
|
|
{
|
|
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
|
|
ARRAY_SIZE(usb_otg_pads));
|
|
|
|
/*
|
|
* set daisy chain for otg_pin_id on 6q.
|
|
* for 6dl, this bit is reserved
|
|
*/
|
|
#ifdef CONFIG_SCMEVB
|
|
imx_iomux_set_gpr_register(1, 13, 1, 0);
|
|
#else
|
|
imx_iomux_set_gpr_register(1, 13, 1, 1);
|
|
#endif
|
|
|
|
imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
|
|
ARRAY_SIZE(usb_hc1_pads));
|
|
}
|
|
|
|
int board_ehci_hcd_init(int port)
|
|
{
|
|
u32 *usbnc_usb_ctrl;
|
|
|
|
if (port > 1)
|
|
return -EINVAL;
|
|
|
|
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
|
port * 4);
|
|
|
|
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_ehci_power(int port, int on)
|
|
{
|
|
switch (port) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
if (on)
|
|
gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
|
|
else
|
|
gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
|
|
break;
|
|
default:
|
|
printf("MXC USB port %d not yet supported\n", port);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
setup_iomux_uart();
|
|
#if defined(CONFIG_VIDEO_IPUV3)
|
|
setup_display();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
#ifdef CONFIG_MXC_SPI
|
|
setup_spi();
|
|
#endif
|
|
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
|
|
|
#ifdef CONFIG_USB_EHCI_MX6
|
|
setup_usb();
|
|
#endif
|
|
|
|
#ifdef CONFIG_CMD_SATA
|
|
setup_sata();
|
|
#endif
|
|
|
|
#ifdef CONFIG_FEC_MXC
|
|
setup_fec();
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int power_init_board(void)
|
|
{
|
|
struct pmic *pfuze;
|
|
unsigned int reg;
|
|
int ret;
|
|
|
|
pfuze = pfuze_common_init(I2C_PMIC);
|
|
if (!pfuze)
|
|
return -ENODEV;
|
|
|
|
ret = pfuze_mode_init(pfuze, APS_PFM);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* set SW3A to 1.25V for LPDDR2 */
|
|
pmic_reg_read(pfuze, PFUZE100_SW3AVOL, ®);
|
|
reg &= ~0x3f;
|
|
reg |= 0x22;
|
|
pmic_reg_write(pfuze, PFUZE100_SW3AVOL, reg);
|
|
|
|
/* set SW2 to 3.2V */
|
|
pmic_reg_read(pfuze, PFUZE100_SW2VOL, ®);
|
|
reg &= ~0x7f;
|
|
reg |= 0x72;
|
|
pmic_reg_write(pfuze, PFUZE100_SW2VOL, reg);
|
|
|
|
/* set VGEN1 to 1.5V */
|
|
pmic_reg_read(pfuze, PFUZE100_VGEN1VOL, ®);
|
|
reg &= ~0x0f;
|
|
reg |= 0x0e;
|
|
pmic_reg_write(pfuze, PFUZE100_VGEN1VOL, reg);
|
|
|
|
/* set VGEN3 to 2.8V */
|
|
pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, ®);
|
|
reg &= ~0x0f;
|
|
reg |= 0x0a;
|
|
pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg);
|
|
|
|
/* set VGEN4 to 2.5V */
|
|
pmic_reg_read(pfuze, PFUZE100_VGEN4VOL, ®);
|
|
reg &= ~0x0f;
|
|
reg |= 0x07;
|
|
pmic_reg_write(pfuze, PFUZE100_VGEN4VOL, reg);
|
|
|
|
/* set VGEN5 to 3.3V */
|
|
pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®);
|
|
reg &= ~0x0f;
|
|
#ifdef CONFIG_QWKS_REV3
|
|
reg |= 0x07;
|
|
#else
|
|
reg |= 0x0f;
|
|
#endif
|
|
pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
|
|
|
|
/* set VGEN6 to 3.2V */
|
|
pmic_reg_read(pfuze, PFUZE100_VGEN6VOL, ®);
|
|
reg &= ~0x0f;
|
|
reg |= 0x0e;
|
|
pmic_reg_write(pfuze, PFUZE100_VGEN6VOL, reg);
|
|
|
|
/* set SW1AB staby volatage 0.975V*/
|
|
pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®);
|
|
reg &= ~0x3f;
|
|
reg |= 0x1b;
|
|
pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
|
|
|
|
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
|
|
pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®);
|
|
reg &= ~0xc0;
|
|
reg |= 0x40;
|
|
pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
|
|
|
|
/* set SW1C staby volatage 0.975V*/
|
|
pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®);
|
|
reg &= ~0x3f;
|
|
reg |= 0x1b;
|
|
pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
|
|
|
|
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
|
|
pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®);
|
|
reg &= ~0xc0;
|
|
reg |= 0x40;
|
|
pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_LDO_BYPASS_CHECK
|
|
void ldo_mode_set(int ldo_bypass)
|
|
{
|
|
unsigned int value;
|
|
int is_400M;
|
|
unsigned char vddarm;
|
|
struct pmic *p = pmic_get("PFUZE100");
|
|
|
|
if (!p) {
|
|
printf("No PMIC found!\n");
|
|
return;
|
|
}
|
|
|
|
/* increase VDDARM/VDDSOC to support 1.2G chip */
|
|
if (check_1_2G()) {
|
|
ldo_bypass = 0; /* ldo_enable on 1.2G chip */
|
|
printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
|
|
/* increase VDDARM to 1.425V */
|
|
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
|
|
value &= ~0x3f;
|
|
value |= 0x2d;
|
|
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
|
|
|
|
/* increase VDDSOC to 1.425V */
|
|
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
|
|
value &= ~0x3f;
|
|
value |= 0x2d;
|
|
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
|
|
}
|
|
/* switch to ldo_bypass mode , boot on 800Mhz */
|
|
if (ldo_bypass) {
|
|
prep_anatop_bypass();
|
|
|
|
/* decrease VDDARM for 400Mhz DQ:1.1V */
|
|
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
|
|
value &= ~0x3f;
|
|
value |= 0x20;
|
|
|
|
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
|
|
|
|
/* increase VDDSOC to 1.3V */
|
|
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
|
|
value &= ~0x3f;
|
|
value |= 0x28;
|
|
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
|
|
|
|
/*
|
|
* MX6Q:
|
|
* VDDARM:1.15V@800M; VDDSOC:1.175V@800M
|
|
* VDDARM:0.975V@400M; VDDSOC:1.175V@400M
|
|
*/
|
|
is_400M = set_anatop_bypass(2);
|
|
|
|
if (is_400M)
|
|
vddarm = 0x1b;
|
|
else
|
|
vddarm = 0x22;
|
|
|
|
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
|
|
value &= ~0x3f;
|
|
value |= vddarm;
|
|
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
|
|
|
|
/* decrease VDDSOC to 1.175V */
|
|
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
|
|
value &= ~0x3f;
|
|
value |= 0x23;
|
|
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
|
|
|
|
finish_anatop_bypass();
|
|
printf("switch to ldo_bypass mode!\n");
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
static const struct boot_mode board_boot_modes[] = {
|
|
/* 4 bit bus width */
|
|
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
|
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
|
/* 8 bit bus width */
|
|
{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
|
|
{NULL, 0},
|
|
};
|
|
#endif
|
|
|
|
int board_late_init(void)
|
|
{
|
|
#ifdef CONFIG_CMD_BMODE
|
|
add_board_boot_modes(board_boot_modes);
|
|
#endif
|
|
|
|
#ifdef CONFIG_ENV_IS_IN_MMC
|
|
board_late_mmc_env_init();
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
#ifdef CONFIG_SCMHVB
|
|
puts("Board: MX6DQSCM-HVB\n");
|
|
#elif CONFIG_SCMEVB
|
|
puts("Board: MX6DQSCM-EVB\n");
|
|
#elif CONFIG_QWKS_REV3
|
|
puts("Board: MX6DQSCM-QWKS-REV3\n");
|
|
#else
|
|
puts("Board: MX6DQSCM-QWKS\n");
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_FASTBOOT
|
|
|
|
void board_fastboot_setup(void)
|
|
{
|
|
switch (get_boot_device()) {
|
|
#if defined(CONFIG_FASTBOOT_STORAGE_SATA)
|
|
case SATA_BOOT:
|
|
if (!getenv("fastboot_dev"))
|
|
setenv("fastboot_dev", "sata");
|
|
if (!getenv("bootcmd"))
|
|
setenv("bootcmd", "boota sata");
|
|
break;
|
|
#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
|
|
#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
|
|
case SD2_BOOT:
|
|
case MMC2_BOOT:
|
|
if (!getenv("fastboot_dev"))
|
|
setenv("fastboot_dev", "mmc0");
|
|
if (!getenv("bootcmd"))
|
|
setenv("bootcmd", "boota mmc0");
|
|
break;
|
|
case SD3_BOOT:
|
|
case MMC3_BOOT:
|
|
if (!getenv("fastboot_dev"))
|
|
setenv("fastboot_dev", "mmc1");
|
|
if (!getenv("bootcmd"))
|
|
setenv("bootcmd", "boota mmc1");
|
|
break;
|
|
case MMC4_BOOT:
|
|
if (!getenv("fastboot_dev"))
|
|
setenv("fastboot_dev", "mmc2");
|
|
if (!getenv("bootcmd"))
|
|
setenv("bootcmd", "boota mmc2");
|
|
break;
|
|
#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
|
|
default:
|
|
printf("unsupported boot devices\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_ANDROID_RECOVERY
|
|
|
|
#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)
|
|
iomux_v3_cfg_t const recovery_key_pads[] = {
|
|
(MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
};
|
|
|
|
int check_recovery_cmd_file(void)
|
|
{
|
|
int button_pressed = 0;
|
|
int recovery_mode = 0;
|
|
|
|
recovery_mode = recovery_check_and_clean_flag();
|
|
#ifdef CONFIG_EVB_SETTINGS
|
|
/* Check Recovery Combo Button press or not. */
|
|
imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
|
|
ARRAY_SIZE(recovery_key_pads));
|
|
|
|
gpio_direction_input(GPIO_VOL_DN_KEY);
|
|
|
|
if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN is low assert */
|
|
button_pressed = 1;
|
|
printf("Recovery key pressed\n");
|
|
}
|
|
#endif
|
|
|
|
return recovery_mode || button_pressed;
|
|
}
|
|
|
|
void board_recovery_setup(void)
|
|
{
|
|
int bootdev = get_boot_device();
|
|
|
|
switch (bootdev) {
|
|
#if defined(CONFIG_FASTBOOT_STORAGE_SATA)
|
|
case SATA_BOOT:
|
|
if (!getenv("bootcmd_android_recovery"))
|
|
setenv("bootcmd_android_recovery",
|
|
"boota sata recovery");
|
|
break;
|
|
#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
|
|
#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
|
|
case SD2_BOOT:
|
|
case MMC2_BOOT:
|
|
if (!getenv("bootcmd_android_recovery"))
|
|
setenv("bootcmd_android_recovery",
|
|
"boota mmc0 recovery");
|
|
break;
|
|
case SD3_BOOT:
|
|
case MMC3_BOOT:
|
|
if (!getenv("bootcmd_android_recovery"))
|
|
setenv("bootcmd_android_recovery",
|
|
"boota mmc1 recovery");
|
|
break;
|
|
case MMC4_BOOT:
|
|
if (!getenv("bootcmd_android_recovery"))
|
|
setenv("bootcmd_android_recovery",
|
|
"boota mmc2 recovery");
|
|
break;
|
|
#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
|
|
default:
|
|
printf("Unsupported bootup device for recovery: dev: %d\n",
|
|
bootdev);
|
|
return;
|
|
}
|
|
|
|
printf("setup env for recovery..\n");
|
|
setenv("bootcmd", "run bootcmd_android_recovery");
|
|
}
|
|
|
|
#endif /*CONFIG_ANDROID_RECOVERY*/
|
|
|
|
#endif /*CONFIG_FSL_FASTBOOT*/
|