generated from gaoyang3513/SDK_RK3288
118 lines
3.8 KiB
C
118 lines
3.8 KiB
C
/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef MXC_PXP_H
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#define MXC_PXP_H
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#include <asm/imx-common/regs-common.h>
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struct mxs_pxp_regs{
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mxs_reg_32(pxp_ctrl) /* 0x00 */
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mxs_reg_32(pxp_stat) /* 0x10 */
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mxs_reg_32(pxp_out_ctrl) /* 0x20 */
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mxs_reg_32(pxp_out_buf) /* 0x30 */
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mxs_reg_32(pxp_out_buf2) /* 0x40 */
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mxs_reg_32(pxp_out_pitch) /* 0x50 */
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mxs_reg_32(pxp_out_lrc) /* 0x60 */
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mxs_reg_32(pxp_out_ps_ulc) /* 0x70 */
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mxs_reg_32(pxp_out_ps_lrc) /* 0x80 */
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mxs_reg_32(pxp_out_as_ulc) /* 0x90 */
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mxs_reg_32(pxp_out_as_lrc) /* 0xa0 */
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mxs_reg_32(pxp_ps_ctrl) /* 0xb0 */
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mxs_reg_32(pxp_ps_buf) /* 0xc0 */
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mxs_reg_32(pxp_ps_ubuf) /* 0xd0 */
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mxs_reg_32(pxp_ps_vbuf) /* 0xe0 */
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mxs_reg_32(pxp_ps_pitch) /* 0xf0 */
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mxs_reg_32(pxp_ps_background) /* 0x100 */
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mxs_reg_32(pxp_ps_scale) /* 0x110 */
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mxs_reg_32(pxp_ps_offset) /* 0x120 */
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mxs_reg_32(pxp_ps_clrkeylow) /* 0x130 */
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mxs_reg_32(pxp_ps_clrkeyhigh) /* 0x140 */
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mxs_reg_32(pxp_as_ctrl) /* 0x150 */
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mxs_reg_32(pxp_as_buf) /* 0x160 */
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mxs_reg_32(pxp_as_pitch) /* 0x170 */
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mxs_reg_32(pxp_as_clrkeylow) /* 0x180 */
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mxs_reg_32(pxp_as_clrkeyhigh) /* 0x190 */
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mxs_reg_32(pxp_csc1_coef0) /* 0x1a0 */
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mxs_reg_32(pxp_csc1_coef1) /* 0x1b0 */
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mxs_reg_32(pxp_csc1_coef2) /* 0x1c0 */
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mxs_reg_32(pxp_csc2_ctrl) /* 0x1d0 */
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mxs_reg_32(pxp_csc2_coef0) /* 0x1e0 */
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mxs_reg_32(pxp_csc2_coef1) /* 0x1f0 */
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mxs_reg_32(pxp_csc2_coef2) /* 0x200 */
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mxs_reg_32(pxp_csc2_coef3) /* 0x210 */
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mxs_reg_32(pxp_csc2_coef4) /* 0x220 */
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mxs_reg_32(pxp_csc2_coef5) /* 0x230 */
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mxs_reg_32(pxp_lut_ctrl) /* 0x240 */
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mxs_reg_32(pxp_lut_addr) /* 0x250 */
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mxs_reg_32(pxp_lut_data) /* 0x260 */
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mxs_reg_32(pxp_lut_extmem) /* 0x270 */
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mxs_reg_32(pxp_cfa) /* 0x280 */
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mxs_reg_32(pxp_hist_ctrl) /* 0x290 */
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mxs_reg_32(pxp_hist2_param) /* 0x2a0 */
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mxs_reg_32(pxp_hist4_param) /* 0x2b0 */
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mxs_reg_32(pxp_hist8_param0) /* 0x2c0 */
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mxs_reg_32(pxp_hist8_param1) /* 0x2d0 */
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mxs_reg_32(pxp_hist16_param0) /* 0x2e0 */
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mxs_reg_32(pxp_hist16_param1) /* 0x2f0 */
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mxs_reg_32(pxp_hist16_param2) /* 0x300 */
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mxs_reg_32(pxp_hist16_param3) /* 0x310 */
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mxs_reg_32(pxp_power) /* 0x320 */
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uint32_t reserved1[4*13];
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mxs_reg_32(pxp_next) /* 0x400 */
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};
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#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
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#define BM_PXP_CTRL_ENABLE 0x00000001
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#define BM_PXP_STAT_IRQ 0x00000001
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#define BP_PXP_OUT_CTRL_FORMAT 0
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#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F
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#define BF_PXP_OUT_CTRL_FORMAT(v) \
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(((v) << 0) & BM_PXP_OUT_CTRL_FORMAT)
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#define HW_PXP_PS_SCALE (0x00000110)
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#define BM_PXP_PS_SCALE_RSVD2 0x80000000
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#define BP_PXP_PS_SCALE_YSCALE 16
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#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000
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#define BF_PXP_PS_SCALE_YSCALE(v) \
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(((v) << 16) & BM_PXP_PS_SCALE_YSCALE)
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#define BM_PXP_PS_SCALE_RSVD1 0x00008000
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#define BP_PXP_PS_SCALE_XSCALE 0
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#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF
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#define BF_PXP_PS_SCALE_XSCALE(v) \
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(((v) << 0) & BM_PXP_PS_SCALE_XSCALE)
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#define BP_PXP_PS_CTRL_SWAP 5
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#define BM_PXP_PS_CTRL_SWAP 0x000000E0
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#define BF_PXP_PS_CTRL_SWAP(v) \
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(((v) << 5) & BM_PXP_PS_CTRL_SWAP)
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#define BP_PXP_PS_CTRL_FORMAT 0
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#define BM_PXP_PS_CTRL_FORMAT 0x0000001F
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#define BF_PXP_PS_CTRL_FORMAT(v) \
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(((v) << 0) & BM_PXP_PS_CTRL_FORMAT)
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#define BM_PXP_CTRL_SFTRST 0x80000000
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#define BM_PXP_CTRL_CLKGATE 0x40000000
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struct pxp_layer_param {
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unsigned short width;
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unsigned short height;
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unsigned short stride; /* aka pitch */
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unsigned int pixel_fmt;
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void *paddr;
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};
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struct pxp_config_data {
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struct pxp_layer_param s0_param;
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struct pxp_layer_param out_param;
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};
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void pxp_config(struct pxp_config_data *pxp_conf);
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#endif
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