gaoyang3513/SDK_RK3288
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[kernel] Revert "clk: rockchip: dclk_lcdc0 and g_aclk_lcdc0 are always div from cpll for HDMI"

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This commit is contained in:
zouxf
2016-02-24 10:08:47 +08:00
committed by cjp
parent d08de59bea
commit 14b005cf9b
1 changed files with 2 additions and 4 deletions
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6
kernel/drivers/clk/rockchip/clk-ops.c
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@ -609,8 +609,7 @@ static long clk_3288_dclk_lcdc0_determine_rate(struct clk_hw *hw, unsigned long
gpll_rate = __clk_get_rate(gpll);
//if ((rate <= (297*MHZ)) && (gpll_rate%rate == 0)) {
if(0) {
if ((rate <= (297*MHZ)) && (gpll_rate%rate == 0)) {
*best_parent_p = gpll;
best = rate;
*best_parent_rate = gpll_rate;
@ -644,8 +643,7 @@ static int clk_3288_dclk_lcdc0_set_rate(struct clk_hw *hw, unsigned long rate,
clk_divider_ops.set_rate(hw, rate, parent_rate);
/* set aclk_vio */
//if (parent_rate == __clk_get_rate(gpll)) {
if(0) {
if (parent_rate == __clk_get_rate(gpll)) {
parent = clk_get(NULL, "clk_gpll");
clk_set_parent(aclk_vio0, gpll);
clk_set_rate(aclk_vio0, 300*MHZ);