970 lines
33 KiB
C++
970 lines
33 KiB
C++
/*
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* Copyright (C) 2011 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "assembler_mips.h"
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#include "base/casts.h"
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#include "entrypoints/quick/quick_entrypoints.h"
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#include "memory_region.h"
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#include "thread.h"
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namespace art {
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namespace mips {
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std::ostream& operator<<(std::ostream& os, const DRegister& rhs) {
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if (rhs >= D0 && rhs < kNumberOfDRegisters) {
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os << "d" << static_cast<int>(rhs);
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} else {
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os << "DRegister[" << static_cast<int>(rhs) << "]";
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}
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return os;
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}
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void MipsAssembler::Emit(int32_t value) {
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AssemblerBuffer::EnsureCapacity ensured(&buffer_);
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buffer_.Emit<int32_t>(value);
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}
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void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) {
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CHECK_NE(rs, kNoRegister);
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CHECK_NE(rt, kNoRegister);
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CHECK_NE(rd, kNoRegister);
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int32_t encoding = opcode << kOpcodeShift |
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static_cast<int32_t>(rs) << kRsShift |
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static_cast<int32_t>(rt) << kRtShift |
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static_cast<int32_t>(rd) << kRdShift |
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shamt << kShamtShift |
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funct;
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Emit(encoding);
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}
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void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) {
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CHECK_NE(rs, kNoRegister);
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CHECK_NE(rt, kNoRegister);
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int32_t encoding = opcode << kOpcodeShift |
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static_cast<int32_t>(rs) << kRsShift |
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static_cast<int32_t>(rt) << kRtShift |
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imm;
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Emit(encoding);
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}
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void MipsAssembler::EmitJ(int opcode, int address) {
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int32_t encoding = opcode << kOpcodeShift |
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address;
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Emit(encoding);
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}
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void MipsAssembler::EmitFR(int opcode, int fmt, FRegister ft, FRegister fs, FRegister fd, int funct) {
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CHECK_NE(ft, kNoFRegister);
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CHECK_NE(fs, kNoFRegister);
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CHECK_NE(fd, kNoFRegister);
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int32_t encoding = opcode << kOpcodeShift |
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fmt << kFmtShift |
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static_cast<int32_t>(ft) << kFtShift |
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static_cast<int32_t>(fs) << kFsShift |
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static_cast<int32_t>(fd) << kFdShift |
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funct;
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Emit(encoding);
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}
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void MipsAssembler::EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm) {
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CHECK_NE(rt, kNoFRegister);
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int32_t encoding = opcode << kOpcodeShift |
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fmt << kFmtShift |
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static_cast<int32_t>(rt) << kRtShift |
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imm;
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Emit(encoding);
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}
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void MipsAssembler::EmitBranch(Register rt, Register rs, Label* label, bool equal) {
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int offset;
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if (label->IsBound()) {
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offset = label->Position() - buffer_.Size();
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} else {
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// Use the offset field of the branch instruction for linking the sites.
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offset = label->position_;
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label->LinkTo(buffer_.Size());
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}
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if (equal) {
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Beq(rt, rs, (offset >> 2) & kBranchOffsetMask);
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} else {
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Bne(rt, rs, (offset >> 2) & kBranchOffsetMask);
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}
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}
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void MipsAssembler::EmitJump(Label* label, bool link) {
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int offset;
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if (label->IsBound()) {
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offset = label->Position() - buffer_.Size();
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} else {
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// Use the offset field of the jump instruction for linking the sites.
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offset = label->position_;
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label->LinkTo(buffer_.Size());
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}
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if (link) {
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Jal((offset >> 2) & kJumpOffsetMask);
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} else {
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J((offset >> 2) & kJumpOffsetMask);
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}
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}
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int32_t MipsAssembler::EncodeBranchOffset(int offset, int32_t inst, bool is_jump) {
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CHECK_ALIGNED(offset, 4);
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CHECK(IsInt(POPCOUNT(kBranchOffsetMask), offset)) << offset;
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// Properly preserve only the bits supported in the instruction.
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offset >>= 2;
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if (is_jump) {
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offset &= kJumpOffsetMask;
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return (inst & ~kJumpOffsetMask) | offset;
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} else {
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offset &= kBranchOffsetMask;
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return (inst & ~kBranchOffsetMask) | offset;
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}
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}
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int MipsAssembler::DecodeBranchOffset(int32_t inst, bool is_jump) {
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// Sign-extend, then left-shift by 2.
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if (is_jump) {
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return (((inst & kJumpOffsetMask) << 6) >> 4);
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} else {
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return (((inst & kBranchOffsetMask) << 16) >> 14);
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}
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}
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void MipsAssembler::Bind(Label* label, bool is_jump) {
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CHECK(!label->IsBound());
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int bound_pc = buffer_.Size();
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while (label->IsLinked()) {
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int32_t position = label->Position();
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int32_t next = buffer_.Load<int32_t>(position);
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int32_t offset = is_jump ? bound_pc - position : bound_pc - position - 4;
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int32_t encoded = MipsAssembler::EncodeBranchOffset(offset, next, is_jump);
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buffer_.Store<int32_t>(position, encoded);
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label->position_ = MipsAssembler::DecodeBranchOffset(next, is_jump);
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}
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label->BindTo(bound_pc);
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}
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void MipsAssembler::Add(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x20);
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}
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void MipsAssembler::Addu(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x21);
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}
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void MipsAssembler::Addi(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x8, rs, rt, imm16);
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}
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void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x9, rs, rt, imm16);
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}
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void MipsAssembler::Sub(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x22);
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}
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void MipsAssembler::Subu(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x23);
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}
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void MipsAssembler::Mult(Register rs, Register rt) {
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EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x18);
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}
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void MipsAssembler::Multu(Register rs, Register rt) {
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EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x19);
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}
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void MipsAssembler::Div(Register rs, Register rt) {
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EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x1a);
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}
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void MipsAssembler::Divu(Register rs, Register rt) {
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EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x1b);
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}
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void MipsAssembler::And(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x24);
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}
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void MipsAssembler::Andi(Register rt, Register rs, uint16_t imm16) {
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EmitI(0xc, rs, rt, imm16);
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}
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void MipsAssembler::Or(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x25);
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}
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void MipsAssembler::Ori(Register rt, Register rs, uint16_t imm16) {
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EmitI(0xd, rs, rt, imm16);
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}
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void MipsAssembler::Xor(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x26);
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}
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void MipsAssembler::Xori(Register rt, Register rs, uint16_t imm16) {
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EmitI(0xe, rs, rt, imm16);
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}
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void MipsAssembler::Nor(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x27);
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}
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void MipsAssembler::Sll(Register rd, Register rs, int shamt) {
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EmitR(0, rs, static_cast<Register>(0), rd, shamt, 0x00);
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}
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void MipsAssembler::Srl(Register rd, Register rs, int shamt) {
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EmitR(0, rs, static_cast<Register>(0), rd, shamt, 0x02);
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}
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void MipsAssembler::Sra(Register rd, Register rs, int shamt) {
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EmitR(0, rs, static_cast<Register>(0), rd, shamt, 0x03);
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}
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void MipsAssembler::Sllv(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x04);
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}
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void MipsAssembler::Srlv(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x06);
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}
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void MipsAssembler::Srav(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x07);
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}
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void MipsAssembler::Lb(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x20, rs, rt, imm16);
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}
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void MipsAssembler::Lh(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x21, rs, rt, imm16);
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}
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void MipsAssembler::Lw(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x23, rs, rt, imm16);
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}
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void MipsAssembler::Lbu(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x24, rs, rt, imm16);
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}
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void MipsAssembler::Lhu(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x25, rs, rt, imm16);
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}
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void MipsAssembler::Lui(Register rt, uint16_t imm16) {
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EmitI(0xf, static_cast<Register>(0), rt, imm16);
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}
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void MipsAssembler::Mfhi(Register rd) {
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EmitR(0, static_cast<Register>(0), static_cast<Register>(0), rd, 0, 0x10);
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}
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void MipsAssembler::Mflo(Register rd) {
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EmitR(0, static_cast<Register>(0), static_cast<Register>(0), rd, 0, 0x12);
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}
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void MipsAssembler::Sb(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x28, rs, rt, imm16);
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}
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void MipsAssembler::Sh(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x29, rs, rt, imm16);
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}
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void MipsAssembler::Sw(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x2b, rs, rt, imm16);
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}
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void MipsAssembler::Slt(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x2a);
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}
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void MipsAssembler::Sltu(Register rd, Register rs, Register rt) {
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EmitR(0, rs, rt, rd, 0, 0x2b);
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}
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void MipsAssembler::Slti(Register rt, Register rs, uint16_t imm16) {
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EmitI(0xa, rs, rt, imm16);
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}
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void MipsAssembler::Sltiu(Register rt, Register rs, uint16_t imm16) {
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EmitI(0xb, rs, rt, imm16);
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}
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void MipsAssembler::Beq(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x4, rs, rt, imm16);
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Nop();
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}
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void MipsAssembler::Bne(Register rt, Register rs, uint16_t imm16) {
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EmitI(0x5, rs, rt, imm16);
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Nop();
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}
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void MipsAssembler::J(uint32_t address) {
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EmitJ(0x2, address);
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Nop();
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}
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void MipsAssembler::Jal(uint32_t address) {
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EmitJ(0x2, address);
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Nop();
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}
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void MipsAssembler::Jr(Register rs) {
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EmitR(0, rs, static_cast<Register>(0), static_cast<Register>(0), 0, 0x08);
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Nop();
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}
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void MipsAssembler::Jalr(Register rs) {
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EmitR(0, rs, static_cast<Register>(0), RA, 0, 0x09);
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Nop();
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}
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void MipsAssembler::AddS(FRegister fd, FRegister fs, FRegister ft) {
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EmitFR(0x11, 0x10, ft, fs, fd, 0x0);
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}
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void MipsAssembler::SubS(FRegister fd, FRegister fs, FRegister ft) {
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EmitFR(0x11, 0x10, ft, fs, fd, 0x1);
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}
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void MipsAssembler::MulS(FRegister fd, FRegister fs, FRegister ft) {
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EmitFR(0x11, 0x10, ft, fs, fd, 0x2);
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}
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void MipsAssembler::DivS(FRegister fd, FRegister fs, FRegister ft) {
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EmitFR(0x11, 0x10, ft, fs, fd, 0x3);
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}
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void MipsAssembler::AddD(DRegister fd, DRegister fs, DRegister ft) {
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EmitFR(0x11, 0x11, static_cast<FRegister>(ft), static_cast<FRegister>(fs),
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static_cast<FRegister>(fd), 0x0);
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}
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void MipsAssembler::SubD(DRegister fd, DRegister fs, DRegister ft) {
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EmitFR(0x11, 0x11, static_cast<FRegister>(ft), static_cast<FRegister>(fs),
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static_cast<FRegister>(fd), 0x1);
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}
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void MipsAssembler::MulD(DRegister fd, DRegister fs, DRegister ft) {
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EmitFR(0x11, 0x11, static_cast<FRegister>(ft), static_cast<FRegister>(fs),
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static_cast<FRegister>(fd), 0x2);
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}
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void MipsAssembler::DivD(DRegister fd, DRegister fs, DRegister ft) {
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EmitFR(0x11, 0x11, static_cast<FRegister>(ft), static_cast<FRegister>(fs),
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static_cast<FRegister>(fd), 0x3);
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}
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void MipsAssembler::MovS(FRegister fd, FRegister fs) {
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EmitFR(0x11, 0x10, static_cast<FRegister>(0), fs, fd, 0x6);
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}
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void MipsAssembler::MovD(DRegister fd, DRegister fs) {
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EmitFR(0x11, 0x11, static_cast<FRegister>(0), static_cast<FRegister>(fs),
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static_cast<FRegister>(fd), 0x6);
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}
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void MipsAssembler::Mfc1(Register rt, FRegister fs) {
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EmitFR(0x11, 0x00, static_cast<FRegister>(rt), fs, static_cast<FRegister>(0), 0x0);
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}
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void MipsAssembler::Mtc1(FRegister ft, Register rs) {
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EmitFR(0x11, 0x04, ft, static_cast<FRegister>(rs), static_cast<FRegister>(0), 0x0);
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}
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void MipsAssembler::Lwc1(FRegister ft, Register rs, uint16_t imm16) {
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EmitI(0x31, rs, static_cast<Register>(ft), imm16);
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}
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void MipsAssembler::Ldc1(DRegister ft, Register rs, uint16_t imm16) {
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EmitI(0x35, rs, static_cast<Register>(ft), imm16);
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}
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void MipsAssembler::Swc1(FRegister ft, Register rs, uint16_t imm16) {
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EmitI(0x39, rs, static_cast<Register>(ft), imm16);
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}
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void MipsAssembler::Sdc1(DRegister ft, Register rs, uint16_t imm16) {
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EmitI(0x3d, rs, static_cast<Register>(ft), imm16);
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}
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void MipsAssembler::Break() {
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EmitR(0, static_cast<Register>(0), static_cast<Register>(0),
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static_cast<Register>(0), 0, 0xD);
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}
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void MipsAssembler::Nop() {
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EmitR(0x0, static_cast<Register>(0), static_cast<Register>(0), static_cast<Register>(0), 0, 0x0);
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}
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void MipsAssembler::Move(Register rt, Register rs) {
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EmitI(0x8, rs, rt, 0);
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}
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void MipsAssembler::Clear(Register rt) {
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EmitR(0, static_cast<Register>(0), static_cast<Register>(0), rt, 0, 0x20);
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}
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void MipsAssembler::Not(Register rt, Register rs) {
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EmitR(0, static_cast<Register>(0), rs, rt, 0, 0x27);
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}
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void MipsAssembler::Mul(Register rd, Register rs, Register rt) {
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Mult(rs, rt);
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Mflo(rd);
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}
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void MipsAssembler::Div(Register rd, Register rs, Register rt) {
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Div(rs, rt);
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Mflo(rd);
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}
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void MipsAssembler::Rem(Register rd, Register rs, Register rt) {
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Div(rs, rt);
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Mfhi(rd);
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}
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void MipsAssembler::AddConstant(Register rt, Register rs, int32_t value) {
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Addi(rt, rs, value);
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}
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void MipsAssembler::LoadImmediate(Register rt, int32_t value) {
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Addi(rt, ZERO, value);
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}
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void MipsAssembler::EmitLoad(ManagedRegister m_dst, Register src_register, int32_t src_offset,
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size_t size) {
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MipsManagedRegister dst = m_dst.AsMips();
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if (dst.IsNoRegister()) {
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CHECK_EQ(0u, size) << dst;
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} else if (dst.IsCoreRegister()) {
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CHECK_EQ(4u, size) << dst;
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LoadFromOffset(kLoadWord, dst.AsCoreRegister(), src_register, src_offset);
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} else if (dst.IsRegisterPair()) {
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CHECK_EQ(8u, size) << dst;
|
|
LoadFromOffset(kLoadWord, dst.AsRegisterPairLow(), src_register, src_offset);
|
|
LoadFromOffset(kLoadWord, dst.AsRegisterPairHigh(), src_register, src_offset + 4);
|
|
} else if (dst.IsFRegister()) {
|
|
LoadSFromOffset(dst.AsFRegister(), src_register, src_offset);
|
|
} else {
|
|
CHECK(dst.IsDRegister()) << dst;
|
|
LoadDFromOffset(dst.AsDRegister(), src_register, src_offset);
|
|
}
|
|
}
|
|
|
|
void MipsAssembler::LoadFromOffset(LoadOperandType type, Register reg, Register base,
|
|
int32_t offset) {
|
|
switch (type) {
|
|
case kLoadSignedByte:
|
|
Lb(reg, base, offset);
|
|
break;
|
|
case kLoadUnsignedByte:
|
|
Lbu(reg, base, offset);
|
|
break;
|
|
case kLoadSignedHalfword:
|
|
Lh(reg, base, offset);
|
|
break;
|
|
case kLoadUnsignedHalfword:
|
|
Lhu(reg, base, offset);
|
|
break;
|
|
case kLoadWord:
|
|
Lw(reg, base, offset);
|
|
break;
|
|
case kLoadWordPair:
|
|
LOG(FATAL) << "UNREACHABLE";
|
|
break;
|
|
default:
|
|
LOG(FATAL) << "UNREACHABLE";
|
|
}
|
|
}
|
|
|
|
void MipsAssembler::LoadSFromOffset(FRegister reg, Register base, int32_t offset) {
|
|
Lwc1(reg, base, offset);
|
|
}
|
|
|
|
void MipsAssembler::LoadDFromOffset(DRegister reg, Register base, int32_t offset) {
|
|
Ldc1(reg, base, offset);
|
|
}
|
|
|
|
void MipsAssembler::StoreToOffset(StoreOperandType type, Register reg, Register base,
|
|
int32_t offset) {
|
|
switch (type) {
|
|
case kStoreByte:
|
|
Sb(reg, base, offset);
|
|
break;
|
|
case kStoreHalfword:
|
|
Sh(reg, base, offset);
|
|
break;
|
|
case kStoreWord:
|
|
Sw(reg, base, offset);
|
|
break;
|
|
case kStoreWordPair:
|
|
LOG(FATAL) << "UNREACHABLE";
|
|
break;
|
|
default:
|
|
LOG(FATAL) << "UNREACHABLE";
|
|
}
|
|
}
|
|
|
|
void MipsAssembler::StoreFToOffset(FRegister reg, Register base, int32_t offset) {
|
|
Swc1(reg, base, offset);
|
|
}
|
|
|
|
void MipsAssembler::StoreDToOffset(DRegister reg, Register base, int32_t offset) {
|
|
Sdc1(reg, base, offset);
|
|
}
|
|
|
|
constexpr size_t kFramePointerSize = 4;
|
|
|
|
void MipsAssembler::BuildFrame(size_t frame_size, ManagedRegister method_reg,
|
|
const std::vector<ManagedRegister>& callee_save_regs,
|
|
const ManagedRegisterEntrySpills& entry_spills) {
|
|
CHECK_ALIGNED(frame_size, kStackAlignment);
|
|
|
|
// Increase frame to required size.
|
|
IncreaseFrameSize(frame_size);
|
|
|
|
// Push callee saves and return address
|
|
int stack_offset = frame_size - kFramePointerSize;
|
|
StoreToOffset(kStoreWord, RA, SP, stack_offset);
|
|
for (int i = callee_save_regs.size() - 1; i >= 0; --i) {
|
|
stack_offset -= kFramePointerSize;
|
|
Register reg = callee_save_regs.at(i).AsMips().AsCoreRegister();
|
|
StoreToOffset(kStoreWord, reg, SP, stack_offset);
|
|
}
|
|
|
|
// Write out Method*.
|
|
StoreToOffset(kStoreWord, method_reg.AsMips().AsCoreRegister(), SP, 0);
|
|
|
|
// Write out entry spills.
|
|
for (size_t i = 0; i < entry_spills.size(); ++i) {
|
|
Register reg = entry_spills.at(i).AsMips().AsCoreRegister();
|
|
StoreToOffset(kStoreWord, reg, SP, frame_size + kFramePointerSize + (i * kFramePointerSize));
|
|
}
|
|
}
|
|
|
|
void MipsAssembler::RemoveFrame(size_t frame_size,
|
|
const std::vector<ManagedRegister>& callee_save_regs) {
|
|
CHECK_ALIGNED(frame_size, kStackAlignment);
|
|
|
|
// Pop callee saves and return address
|
|
int stack_offset = frame_size - (callee_save_regs.size() * kFramePointerSize) - kFramePointerSize;
|
|
for (size_t i = 0; i < callee_save_regs.size(); ++i) {
|
|
Register reg = callee_save_regs.at(i).AsMips().AsCoreRegister();
|
|
LoadFromOffset(kLoadWord, reg, SP, stack_offset);
|
|
stack_offset += kFramePointerSize;
|
|
}
|
|
LoadFromOffset(kLoadWord, RA, SP, stack_offset);
|
|
|
|
// Decrease frame to required size.
|
|
DecreaseFrameSize(frame_size);
|
|
|
|
// Then jump to the return address.
|
|
Jr(RA);
|
|
}
|
|
|
|
void MipsAssembler::IncreaseFrameSize(size_t adjust) {
|
|
CHECK_ALIGNED(adjust, kStackAlignment);
|
|
AddConstant(SP, SP, -adjust);
|
|
}
|
|
|
|
void MipsAssembler::DecreaseFrameSize(size_t adjust) {
|
|
CHECK_ALIGNED(adjust, kStackAlignment);
|
|
AddConstant(SP, SP, adjust);
|
|
}
|
|
|
|
void MipsAssembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) {
|
|
MipsManagedRegister src = msrc.AsMips();
|
|
if (src.IsNoRegister()) {
|
|
CHECK_EQ(0u, size);
|
|
} else if (src.IsCoreRegister()) {
|
|
CHECK_EQ(4u, size);
|
|
StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
|
|
} else if (src.IsRegisterPair()) {
|
|
CHECK_EQ(8u, size);
|
|
StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value());
|
|
StoreToOffset(kStoreWord, src.AsRegisterPairHigh(),
|
|
SP, dest.Int32Value() + 4);
|
|
} else if (src.IsFRegister()) {
|
|
StoreFToOffset(src.AsFRegister(), SP, dest.Int32Value());
|
|
} else {
|
|
CHECK(src.IsDRegister());
|
|
StoreDToOffset(src.AsDRegister(), SP, dest.Int32Value());
|
|
}
|
|
}
|
|
|
|
void MipsAssembler::StoreRef(FrameOffset dest, ManagedRegister msrc) {
|
|
MipsManagedRegister src = msrc.AsMips();
|
|
CHECK(src.IsCoreRegister());
|
|
StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) {
|
|
MipsManagedRegister src = msrc.AsMips();
|
|
CHECK(src.IsCoreRegister());
|
|
StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
|
|
ManagedRegister mscratch) {
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
CHECK(scratch.IsCoreRegister()) << scratch;
|
|
LoadImmediate(scratch.AsCoreRegister(), imm);
|
|
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm,
|
|
ManagedRegister mscratch) {
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
CHECK(scratch.IsCoreRegister()) << scratch;
|
|
LoadImmediate(scratch.AsCoreRegister(), imm);
|
|
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), S1, dest.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::StoreStackOffsetToThread32(ThreadOffset<4> thr_offs,
|
|
FrameOffset fr_offs,
|
|
ManagedRegister mscratch) {
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
CHECK(scratch.IsCoreRegister()) << scratch;
|
|
AddConstant(scratch.AsCoreRegister(), SP, fr_offs.Int32Value());
|
|
StoreToOffset(kStoreWord, scratch.AsCoreRegister(),
|
|
S1, thr_offs.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::StoreStackPointerToThread32(ThreadOffset<4> thr_offs) {
|
|
StoreToOffset(kStoreWord, SP, S1, thr_offs.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::StoreSpanning(FrameOffset dest, ManagedRegister msrc,
|
|
FrameOffset in_off, ManagedRegister mscratch) {
|
|
MipsManagedRegister src = msrc.AsMips();
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value());
|
|
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4);
|
|
}
|
|
|
|
void MipsAssembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) {
|
|
return EmitLoad(mdest, SP, src.Int32Value(), size);
|
|
}
|
|
|
|
void MipsAssembler::LoadFromThread32(ManagedRegister mdest, ThreadOffset<4> src, size_t size) {
|
|
return EmitLoad(mdest, S1, src.Int32Value(), size);
|
|
}
|
|
|
|
void MipsAssembler::LoadRef(ManagedRegister mdest, FrameOffset src) {
|
|
MipsManagedRegister dest = mdest.AsMips();
|
|
CHECK(dest.IsCoreRegister());
|
|
LoadFromOffset(kLoadWord, dest.AsCoreRegister(), SP, src.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base,
|
|
MemberOffset offs) {
|
|
MipsManagedRegister dest = mdest.AsMips();
|
|
CHECK(dest.IsCoreRegister() && dest.IsCoreRegister());
|
|
LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
|
|
base.AsMips().AsCoreRegister(), offs.Int32Value());
|
|
if (kPoisonHeapReferences) {
|
|
Subu(dest.AsCoreRegister(), ZERO, dest.AsCoreRegister());
|
|
}
|
|
}
|
|
|
|
void MipsAssembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base,
|
|
Offset offs) {
|
|
MipsManagedRegister dest = mdest.AsMips();
|
|
CHECK(dest.IsCoreRegister() && dest.IsCoreRegister()) << dest;
|
|
LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
|
|
base.AsMips().AsCoreRegister(), offs.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::LoadRawPtrFromThread32(ManagedRegister mdest,
|
|
ThreadOffset<4> offs) {
|
|
MipsManagedRegister dest = mdest.AsMips();
|
|
CHECK(dest.IsCoreRegister());
|
|
LoadFromOffset(kLoadWord, dest.AsCoreRegister(), S1, offs.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::SignExtend(ManagedRegister /*mreg*/, size_t /*size*/) {
|
|
UNIMPLEMENTED(FATAL) << "no sign extension necessary for mips";
|
|
}
|
|
|
|
void MipsAssembler::ZeroExtend(ManagedRegister /*mreg*/, size_t /*size*/) {
|
|
UNIMPLEMENTED(FATAL) << "no zero extension necessary for mips";
|
|
}
|
|
|
|
void MipsAssembler::Move(ManagedRegister mdest, ManagedRegister msrc, size_t /*size*/) {
|
|
MipsManagedRegister dest = mdest.AsMips();
|
|
MipsManagedRegister src = msrc.AsMips();
|
|
if (!dest.Equals(src)) {
|
|
if (dest.IsCoreRegister()) {
|
|
CHECK(src.IsCoreRegister()) << src;
|
|
Move(dest.AsCoreRegister(), src.AsCoreRegister());
|
|
} else if (dest.IsFRegister()) {
|
|
CHECK(src.IsFRegister()) << src;
|
|
MovS(dest.AsFRegister(), src.AsFRegister());
|
|
} else if (dest.IsDRegister()) {
|
|
CHECK(src.IsDRegister()) << src;
|
|
MovD(dest.AsDRegister(), src.AsDRegister());
|
|
} else {
|
|
CHECK(dest.IsRegisterPair()) << dest;
|
|
CHECK(src.IsRegisterPair()) << src;
|
|
// Ensure that the first move doesn't clobber the input of the second
|
|
if (src.AsRegisterPairHigh() != dest.AsRegisterPairLow()) {
|
|
Move(dest.AsRegisterPairLow(), src.AsRegisterPairLow());
|
|
Move(dest.AsRegisterPairHigh(), src.AsRegisterPairHigh());
|
|
} else {
|
|
Move(dest.AsRegisterPairHigh(), src.AsRegisterPairHigh());
|
|
Move(dest.AsRegisterPairLow(), src.AsRegisterPairLow());
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void MipsAssembler::CopyRef(FrameOffset dest, FrameOffset src,
|
|
ManagedRegister mscratch) {
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
CHECK(scratch.IsCoreRegister()) << scratch;
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value());
|
|
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::CopyRawPtrFromThread32(FrameOffset fr_offs,
|
|
ThreadOffset<4> thr_offs,
|
|
ManagedRegister mscratch) {
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
CHECK(scratch.IsCoreRegister()) << scratch;
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
|
|
S1, thr_offs.Int32Value());
|
|
StoreToOffset(kStoreWord, scratch.AsCoreRegister(),
|
|
SP, fr_offs.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::CopyRawPtrToThread32(ThreadOffset<4> thr_offs,
|
|
FrameOffset fr_offs,
|
|
ManagedRegister mscratch) {
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
CHECK(scratch.IsCoreRegister()) << scratch;
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
|
|
SP, fr_offs.Int32Value());
|
|
StoreToOffset(kStoreWord, scratch.AsCoreRegister(),
|
|
S1, thr_offs.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::Copy(FrameOffset dest, FrameOffset src,
|
|
ManagedRegister mscratch, size_t size) {
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
CHECK(scratch.IsCoreRegister()) << scratch;
|
|
CHECK(size == 4 || size == 8) << size;
|
|
if (size == 4) {
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value());
|
|
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
|
|
} else if (size == 8) {
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value());
|
|
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value() + 4);
|
|
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4);
|
|
}
|
|
}
|
|
|
|
void MipsAssembler::Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset,
|
|
ManagedRegister mscratch, size_t size) {
|
|
Register scratch = mscratch.AsMips().AsCoreRegister();
|
|
CHECK_EQ(size, 4u);
|
|
LoadFromOffset(kLoadWord, scratch, src_base.AsMips().AsCoreRegister(), src_offset.Int32Value());
|
|
StoreToOffset(kStoreWord, scratch, SP, dest.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
|
|
ManagedRegister mscratch, size_t size) {
|
|
Register scratch = mscratch.AsMips().AsCoreRegister();
|
|
CHECK_EQ(size, 4u);
|
|
LoadFromOffset(kLoadWord, scratch, SP, src.Int32Value());
|
|
StoreToOffset(kStoreWord, scratch, dest_base.AsMips().AsCoreRegister(), dest_offset.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::Copy(FrameOffset /*dest*/, FrameOffset /*src_base*/, Offset /*src_offset*/,
|
|
ManagedRegister /*mscratch*/, size_t /*size*/) {
|
|
UNIMPLEMENTED(FATAL) << "no mips implementation";
|
|
}
|
|
|
|
void MipsAssembler::Copy(ManagedRegister dest, Offset dest_offset,
|
|
ManagedRegister src, Offset src_offset,
|
|
ManagedRegister mscratch, size_t size) {
|
|
CHECK_EQ(size, 4u);
|
|
Register scratch = mscratch.AsMips().AsCoreRegister();
|
|
LoadFromOffset(kLoadWord, scratch, src.AsMips().AsCoreRegister(), src_offset.Int32Value());
|
|
StoreToOffset(kStoreWord, scratch, dest.AsMips().AsCoreRegister(), dest_offset.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::Copy(FrameOffset /*dest*/, Offset /*dest_offset*/, FrameOffset /*src*/, Offset /*src_offset*/,
|
|
ManagedRegister /*mscratch*/, size_t /*size*/) {
|
|
UNIMPLEMENTED(FATAL) << "no mips implementation";
|
|
}
|
|
|
|
void MipsAssembler::MemoryBarrier(ManagedRegister) {
|
|
UNIMPLEMENTED(FATAL) << "no mips implementation";
|
|
}
|
|
|
|
void MipsAssembler::CreateHandleScopeEntry(ManagedRegister mout_reg,
|
|
FrameOffset handle_scope_offset,
|
|
ManagedRegister min_reg, bool null_allowed) {
|
|
MipsManagedRegister out_reg = mout_reg.AsMips();
|
|
MipsManagedRegister in_reg = min_reg.AsMips();
|
|
CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister()) << in_reg;
|
|
CHECK(out_reg.IsCoreRegister()) << out_reg;
|
|
if (null_allowed) {
|
|
Label null_arg;
|
|
// Null values get a handle scope entry value of 0. Otherwise, the handle scope entry is
|
|
// the address in the handle scope holding the reference.
|
|
// e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset)
|
|
if (in_reg.IsNoRegister()) {
|
|
LoadFromOffset(kLoadWord, out_reg.AsCoreRegister(),
|
|
SP, handle_scope_offset.Int32Value());
|
|
in_reg = out_reg;
|
|
}
|
|
if (!out_reg.Equals(in_reg)) {
|
|
LoadImmediate(out_reg.AsCoreRegister(), 0);
|
|
}
|
|
EmitBranch(in_reg.AsCoreRegister(), ZERO, &null_arg, true);
|
|
AddConstant(out_reg.AsCoreRegister(), SP, handle_scope_offset.Int32Value());
|
|
Bind(&null_arg, false);
|
|
} else {
|
|
AddConstant(out_reg.AsCoreRegister(), SP, handle_scope_offset.Int32Value());
|
|
}
|
|
}
|
|
|
|
void MipsAssembler::CreateHandleScopeEntry(FrameOffset out_off,
|
|
FrameOffset handle_scope_offset,
|
|
ManagedRegister mscratch,
|
|
bool null_allowed) {
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
CHECK(scratch.IsCoreRegister()) << scratch;
|
|
if (null_allowed) {
|
|
Label null_arg;
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP,
|
|
handle_scope_offset.Int32Value());
|
|
// Null values get a handle scope entry value of 0. Otherwise, the handle scope entry is
|
|
// the address in the handle scope holding the reference.
|
|
// e.g. scratch = (scratch == 0) ? 0 : (SP+handle_scope_offset)
|
|
EmitBranch(scratch.AsCoreRegister(), ZERO, &null_arg, true);
|
|
AddConstant(scratch.AsCoreRegister(), SP, handle_scope_offset.Int32Value());
|
|
Bind(&null_arg, false);
|
|
} else {
|
|
AddConstant(scratch.AsCoreRegister(), SP, handle_scope_offset.Int32Value());
|
|
}
|
|
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, out_off.Int32Value());
|
|
}
|
|
|
|
// Given a handle scope entry, load the associated reference.
|
|
void MipsAssembler::LoadReferenceFromHandleScope(ManagedRegister mout_reg,
|
|
ManagedRegister min_reg) {
|
|
MipsManagedRegister out_reg = mout_reg.AsMips();
|
|
MipsManagedRegister in_reg = min_reg.AsMips();
|
|
CHECK(out_reg.IsCoreRegister()) << out_reg;
|
|
CHECK(in_reg.IsCoreRegister()) << in_reg;
|
|
Label null_arg;
|
|
if (!out_reg.Equals(in_reg)) {
|
|
LoadImmediate(out_reg.AsCoreRegister(), 0);
|
|
}
|
|
EmitBranch(in_reg.AsCoreRegister(), ZERO, &null_arg, true);
|
|
LoadFromOffset(kLoadWord, out_reg.AsCoreRegister(),
|
|
in_reg.AsCoreRegister(), 0);
|
|
Bind(&null_arg, false);
|
|
}
|
|
|
|
void MipsAssembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) {
|
|
// TODO: not validating references
|
|
}
|
|
|
|
void MipsAssembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) {
|
|
// TODO: not validating references
|
|
}
|
|
|
|
void MipsAssembler::Call(ManagedRegister mbase, Offset offset, ManagedRegister mscratch) {
|
|
MipsManagedRegister base = mbase.AsMips();
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
CHECK(base.IsCoreRegister()) << base;
|
|
CHECK(scratch.IsCoreRegister()) << scratch;
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
|
|
base.AsCoreRegister(), offset.Int32Value());
|
|
Jalr(scratch.AsCoreRegister());
|
|
// TODO: place reference map on call
|
|
}
|
|
|
|
void MipsAssembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) {
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
CHECK(scratch.IsCoreRegister()) << scratch;
|
|
// Call *(*(SP + base) + offset)
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
|
|
SP, base.Int32Value());
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
|
|
scratch.AsCoreRegister(), offset.Int32Value());
|
|
Jalr(scratch.AsCoreRegister());
|
|
// TODO: place reference map on call
|
|
}
|
|
|
|
void MipsAssembler::CallFromThread32(ThreadOffset<4> /*offset*/, ManagedRegister /*mscratch*/) {
|
|
UNIMPLEMENTED(FATAL) << "no mips implementation";
|
|
}
|
|
|
|
void MipsAssembler::GetCurrentThread(ManagedRegister tr) {
|
|
Move(tr.AsMips().AsCoreRegister(), S1);
|
|
}
|
|
|
|
void MipsAssembler::GetCurrentThread(FrameOffset offset,
|
|
ManagedRegister /*mscratch*/) {
|
|
StoreToOffset(kStoreWord, S1, SP, offset.Int32Value());
|
|
}
|
|
|
|
void MipsAssembler::ExceptionPoll(ManagedRegister mscratch, size_t stack_adjust) {
|
|
MipsManagedRegister scratch = mscratch.AsMips();
|
|
MipsExceptionSlowPath* slow = new MipsExceptionSlowPath(scratch, stack_adjust);
|
|
buffer_.EnqueueSlowPath(slow);
|
|
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
|
|
S1, Thread::ExceptionOffset<4>().Int32Value());
|
|
EmitBranch(scratch.AsCoreRegister(), ZERO, slow->Entry(), false);
|
|
}
|
|
|
|
void MipsExceptionSlowPath::Emit(Assembler* sasm) {
|
|
MipsAssembler* sp_asm = down_cast<MipsAssembler*>(sasm);
|
|
#define __ sp_asm->
|
|
__ Bind(&entry_, false);
|
|
if (stack_adjust_ != 0) { // Fix up the frame.
|
|
__ DecreaseFrameSize(stack_adjust_);
|
|
}
|
|
// Pass exception object as argument
|
|
// Don't care about preserving A0 as this call won't return
|
|
__ Move(A0, scratch_.AsCoreRegister());
|
|
// Set up call to Thread::Current()->pDeliverException
|
|
__ LoadFromOffset(kLoadWord, T9, S1, QUICK_ENTRYPOINT_OFFSET(4, pDeliverException).Int32Value());
|
|
__ Jr(T9);
|
|
// Call never returns
|
|
__ Break();
|
|
#undef __
|
|
}
|
|
|
|
} // namespace mips
|
|
} // namespace art
|