From 2330e10fa02e4ffbad2591bfe6b7c923f7311552 Mon Sep 17 00:00:00 2001
From: sophgo-forum-service <forum_service@sophgo.com>
Date: Sat, 20 Jul 2024 21:38:22 +0800
Subject: [PATCH] u-boot-2021.10: weekly rls 2024.07.20

-36551c, fix complie err when set BUILD_FOR_DEBUG=n.
-a94f64, uboot SD clk enable should delay 1ms.
-ac3559, support new spinand flash:HYF1GQ4UDACAE.

Change-Id: Ibc050c06044f76c148955e425746b93f58610be2
---
 u-boot-2021.10/arch/riscv/lib/fdt_fixup.c     |  4 ++--
 .../drivers/mmc/cvitek/sdhci-cv180x.c         |  1 +
 .../drivers/mmc/cvitek/sdhci-cv181x.c         |  1 +
 .../mtd/nand/raw/cvitek/cvsnfc_spi_ids.c      | 24 +++++++++++++++++++
 4 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/u-boot-2021.10/arch/riscv/lib/fdt_fixup.c b/u-boot-2021.10/arch/riscv/lib/fdt_fixup.c
index 238f2f129..ed38ac2b7 100644
--- a/u-boot-2021.10/arch/riscv/lib/fdt_fixup.c
+++ b/u-boot-2021.10/arch/riscv/lib/fdt_fixup.c
@@ -138,7 +138,7 @@ int board_fix_fdt(void *fdt)
 
 int arch_fixup_fdt(void *blob)
 {
-	int err;
+	int err = 0;
 #ifdef CONFIG_EFI_LOADER
 	u32 size;
 	int chosen_offset;
@@ -170,5 +170,5 @@ int arch_fixup_fdt(void *blob)
 	if (err < 0)
 		return err;
 #endif
-	return 0;
+	return err;
 }
diff --git a/u-boot-2021.10/drivers/mmc/cvitek/sdhci-cv180x.c b/u-boot-2021.10/drivers/mmc/cvitek/sdhci-cv180x.c
index 781cd91cf..72fb358b8 100644
--- a/u-boot-2021.10/drivers/mmc/cvitek/sdhci-cv180x.c
+++ b/u-boot-2021.10/drivers/mmc/cvitek/sdhci-cv180x.c
@@ -221,6 +221,7 @@ static void cvi_mmc_set_tap(struct sdhci_host *host, u16 tap)
 	sdhci_writel(host, 0, CVI_SDHCI_PHY_CONFIG);
 	// Set sd_clk_en(0x2c[2]) to 1
 	sdhci_writew(host, sdhci_readw(host, SDHCI_CLOCK_CONTROL) | (0x1 << 2), SDHCI_CLOCK_CONTROL);
+	mdelay(1);
 }
 
 static inline uint32_t CHECK_MASK_BIT(void *_mask, uint32_t bit)
diff --git a/u-boot-2021.10/drivers/mmc/cvitek/sdhci-cv181x.c b/u-boot-2021.10/drivers/mmc/cvitek/sdhci-cv181x.c
index 83561a20c..b81000476 100644
--- a/u-boot-2021.10/drivers/mmc/cvitek/sdhci-cv181x.c
+++ b/u-boot-2021.10/drivers/mmc/cvitek/sdhci-cv181x.c
@@ -223,6 +223,7 @@ static void cvi_mmc_set_tap(struct sdhci_host *host, u16 tap)
 	sdhci_writel(host, 0, CVI_SDHCI_PHY_CONFIG);
 	// Set sd_clk_en(0x2c[2]) to 1
 	sdhci_writew(host, sdhci_readw(host, SDHCI_CLOCK_CONTROL) | BIT(2), SDHCI_CLOCK_CONTROL);
+	mdelay(1);
 }
 
 static inline uint32_t CHECK_MASK_BIT(void *_mask, uint32_t bit)
diff --git a/u-boot-2021.10/drivers/mtd/nand/raw/cvitek/cvsnfc_spi_ids.c b/u-boot-2021.10/drivers/mtd/nand/raw/cvitek/cvsnfc_spi_ids.c
index 48c26a9ba..c79542f4a 100644
--- a/u-boot-2021.10/drivers/mtd/nand/raw/cvitek/cvsnfc_spi_ids.c
+++ b/u-boot-2021.10/drivers/mtd/nand/raw/cvitek/cvsnfc_spi_ids.c
@@ -1380,6 +1380,30 @@ struct cvsnfc_chip_info cvsnfc_spi_nand_flash_table[] = {
 		.xtal_switch = 1,
 	},
 
+	{
+		.name      = "HYF1GQ4UDACAE",
+		.id        = {0xC9, 0x21},
+		.id_len    = 2,
+		.chipsize  = _128M,
+		.erasesize = _128K,
+		.pagesize  = _2K,
+		.oobsize   = 64,
+		.badblock_pos = BBP_FIRST_PAGE,
+		.driver    = &spi_nand_driver_gd,
+		.flags = FLAGS_SET_QE_BIT | FLAGS_ENABLE_X2_BIT | FLAGS_ENABLE_X4_BIT,
+		.ecc_en_feature_offset = 0xb0, /* Configuration register */
+		.ecc_en_mask = 1 << 4, /* bit 4 */
+		.ecc_status_offset = 0xc0, /* Status register */
+		.ecc_status_mask = 0x30, /* bit 4 & 5 */
+		.ecc_status_shift = 4,
+		.ecc_status_uncorr_val = 0x2,
+		.sck_l = 1,
+		.sck_h = 1,
+		.max_freq = SPI_NAND_FREQ_62MHz,
+		.sample_param = 0x40001000,
+		.xtal_switch = 1,
+	},
+
 	{
 		.name      = "FM25S01A",
 		.id        = {0xA1, 0xE4},