From b3bc7af043c44046a576fa1d082528f89e6db844 Mon Sep 17 00:00:00 2001 From: sophgo-forum-service Date: Sat, 20 Jul 2024 21:47:31 +0800 Subject: [PATCH] SensorSupportList: weekly rls 2024.7.20 -c984f7, add sensor ov_os02n10_1l -bf26fc, fixed sc2331_switch can not init when sensors use the same i2c bus. --- middleware/v2/component/isp/sensor.mk | 4 + middleware/v2/component/isp/sensor.mk.orig | 154 +++ .../v2/component/isp/sensor/cv182x/Makefile | 12 + .../component/isp/sensor/cv182x/Makefile.orig | 324 +++++ .../sensor/cv182x/cvsens_cv2003_1L/Makefile | 36 + .../cv182x/cvsens_cv2003_1L/cv2003_1L_cmos.c | 1039 ++++++++++++++ .../cvsens_cv2003_1L/cv2003_1L_cmos_ex.h | 90 ++ .../cvsens_cv2003_1L/cv2003_1L_cmos_param.h | 124 ++ .../cvsens_cv2003_1L/cv2003_1L_sensor_ctl.c | 289 ++++ .../cv182x/gcore_gc2053/gc2053_sensor_ctl.c | 2 +- .../sensor/cv182x/gcore_gc2385_1L/Makefile | 36 + .../cv182x/gcore_gc2385_1L/gc2385_1l_cmos.c | 985 ++++++++++++++ .../gcore_gc2385_1L/gc2385_1l_cmos_ex.h | 95 ++ .../gcore_gc2385_1L/gc2385_1l_cmos_param.h | 125 ++ .../gcore_gc2385_1L/gc2385_1l_sensor_ctl.c | 319 +++++ .../isp/sensor/cv182x/ov_os02n10_1L/Makefile | 36 + .../cv182x/ov_os02n10_1L/os02n10_1l_cmos.c | 1149 ++++++++++++++++ .../cv182x/ov_os02n10_1L/os02n10_1l_cmos_ex.h | 93 ++ .../ov_os02n10_1L/os02n10_1l_cmos_param.h | 126 ++ .../ov_os02n10_1L/os02n10_1l_sensor_ctl.c | 414 ++++++ .../sc2331_1L_slave1_sensor_ctl.c | 3 +- .../isp/sensor/cv182x/sony_imx675/Makefile | 36 + .../sensor/cv182x/sony_imx675/imx675_cmos.c | 1199 +++++++++++++++++ .../cv182x/sony_imx675/imx675_cmos_ex.h | 121 ++ .../cv182x/sony_imx675/imx675_cmos_param.h | 216 +++ .../cv182x/sony_imx675/imx675_sensor_ctl.c | 700 ++++++++++ 26 files changed, 7724 insertions(+), 3 deletions(-) create mode 100644 middleware/v2/component/isp/sensor.mk.orig create mode 100644 middleware/v2/component/isp/sensor/cv182x/Makefile.orig create mode 100644 middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/Makefile create mode 100644 middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos.c create mode 100644 middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos_ex.h create mode 100644 middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos_param.h create mode 100644 middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_sensor_ctl.c create mode 100644 middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/Makefile create mode 100644 middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos.c create mode 100644 middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos_ex.h create mode 100644 middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos_param.h create mode 100644 middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_sensor_ctl.c create mode 100644 middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/Makefile create mode 100644 middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos.c create mode 100644 middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos_ex.h create mode 100644 middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos_param.h create mode 100644 middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_sensor_ctl.c create mode 100644 middleware/v2/component/isp/sensor/cv182x/sony_imx675/Makefile create mode 100644 middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos.c create mode 100644 middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos_ex.h create mode 100644 middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos_param.h create mode 100644 middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_sensor_ctl.c diff --git a/middleware/v2/component/isp/sensor.mk b/middleware/v2/component/isp/sensor.mk index f2778bdce..af95cc10f 100644 --- a/middleware/v2/component/isp/sensor.mk +++ b/middleware/v2/component/isp/sensor.mk @@ -55,6 +55,7 @@ else ifeq ($(CHIP_ARCH), $(filter $(CHIP_ARCH), CV180X CV181X CV182X SG200X)) sensor-$(CONFIG_SENSOR_BRIGATES_BG0808) += brigates_bg0808 sensor-$(CONFIG_SENSOR_CHIPUP_XS9922B) += chipup_xs9922b sensor-$(CONFIG_SENSOR_CVSENS_CV2003) += cvsens_cv2003 +sensor-$(CONFIG_SENSOR_CVSENS_CV2003_1L) += cvsens_cv2003_1L sensor-$(CONFIG_SENSOR_CVSENS_CV2003_1L_SLAVE) += cvsens_cv2003_1L_slave sensor-$(CONFIG_SENSOR_CVSENS_CV2003_1L_SLAVE1) += cvsens_cv2003_1L_slave1 sensor-$(CONFIG_SENSOR_CVSENS_CV4001) += cvsens_cv4001 @@ -73,6 +74,7 @@ sensor-$(CONFIG_SENSOR_GCORE_GC2053_1L) += gcore_gc2053_1L sensor-$(CONFIG_SENSOR_GCORE_GC2083) += gcore_gc2083 sensor-$(CONFIG_SENSOR_GCORE_GC2093) += gcore_gc2093 sensor-$(CONFIG_SENSOR_GCORE_GC2145) += gcore_gc2145 +sensor-$(CONFIG_SENSOR_GCORE_GC2385_1L) += gcore_gc2385_1L sensor-$(CONFIG_SENSOR_GCORE_GC4023) += gcore_gc4023 sensor-$(CONFIG_SENSOR_GCORE_GC4653) += gcore_gc4653 sensor-$(CONFIG_SENSOR_GCORE_GC4653_SLAVE) += gcore_gc4653_slave @@ -80,6 +82,7 @@ sensor-$(CONFIG_SENSOR_IMGDS_MIS2008) += imgds_mis2008 sensor-$(CONFIG_SENSOR_IMGDS_MIS2008_1L) += imgds_mis2008_1L sensor-$(CONFIG_SENSOR_NEXTCHIP_N5) += nextchip_n5 sensor-$(CONFIG_SENSOR_NEXTCHIP_N6) += nextchip_n6 +sensor-$(CONFIG_SENSOR_OV_OS02N10_1L) += ov_os02n10_1L sensor-$(CONFIG_SENSOR_OV_OS04A10) += ov_os04a10 sensor-$(CONFIG_SENSOR_OV_OS04C10) += ov_os04c10 sensor-$(CONFIG_SENSOR_OV_OS08A20) += ov_os08a20 @@ -142,6 +145,7 @@ sensor-$(CONFIG_SENSOR_SONY_IMX327_2L) += sony_imx327_2L sensor-$(CONFIG_SENSOR_SONY_IMX327_FPGA) += sony_imx327_fpga sensor-$(CONFIG_SENSOR_SONY_IMX327_SUBLVDS) += sony_imx327_sublvds sensor-$(CONFIG_SENSOR_SONY_IMX335) += sony_imx335 +sensor-$(CONFIG_SENSOR_SONY_IMX675) += sony_imx675 sensor-$(CONFIG_SENSOR_TECHPOINT_TP2825) += techpoint_tp2825 sensor-$(CONFIG_SENSOR_TECHPOINT_TP2863) += techpoint_tp2863 sensor-$(CONFIG_SENSOR_LONTIUM_LT6911) += lontium_lt6911 diff --git a/middleware/v2/component/isp/sensor.mk.orig b/middleware/v2/component/isp/sensor.mk.orig new file mode 100644 index 000000000..72d641889 --- /dev/null +++ b/middleware/v2/component/isp/sensor.mk.orig @@ -0,0 +1,154 @@ +ifeq ($(CHIP_ARCH),CV183X) +sensor-$(CONFIG_SENSOR_GCORE_GC2053) += gcore_gc2053 +sensor-$(CONFIG_SENSOR_GCORE_GC2053_SLAVE) += gcore_gc2053_slave +sensor-$(CONFIG_SENSOR_GCORE_GC2053_1L) += gcore_gc2053_1L +sensor-$(CONFIG_SENSOR_GCORE_GC2093) += gcore_gc2093 +sensor-$(CONFIG_SENSOR_GCORE_GC2093_SLAVE) += gcore_gc2093_slave +sensor-$(CONFIG_SENSOR_GCORE_GC4653) += gcore_gc4653 +sensor-$(CONFIG_SENSOR_GCORE_GC4653_SLAVE) += gcore_gc4653_slave +sensor-$(CONFIG_SENSOR_NEXTCHIP_N5) += nextchip_n5 +sensor-$(CONFIG_SENSOR_OV_OS02D10) += ov_os02d10 +sensor-$(CONFIG_SENSOR_OV_OS02D10_SLAVE) += ov_os02d10_slave +sensor-$(CONFIG_SENSOR_OV_OS02K10_SLAVE) += ov_os02k10_slave +sensor-$(CONFIG_SENSOR_OV_OS04C10) += ov_os04c10 +sensor-$(CONFIG_SENSOR_OV_OS04C10_SLAVE) += ov_os04c10_slave +sensor-$(CONFIG_SENSOR_OV_OS08A20) += ov_os08a20 +sensor-$(CONFIG_SENSOR_OV_OS08A20_SLAVE) += ov_os08a20_slave +sensor-$(CONFIG_SENSOR_PICO_384) += pico_384 +sensor-$(CONFIG_SENSOR_PICO_640) += pico_640 +sensor-$(CONFIG_SENSOR_PIXELPLUS_PR2020) += pixelplus_pr2020 +sensor-$(CONFIG_SENSOR_PIXELPLUS_PR2100) += pixelplus_pr2100 +sensor-$(CONFIG_SENSOR_SMS_SC035HGS) += sms_sc035hgs +sensor-$(CONFIG_SENSOR_SMS_SC200AI) += sms_sc200ai +sensor-$(CONFIG_SENSOR_SMS_SC401AI) += sms_sc401ai +sensor-$(CONFIG_SENSOR_SMS_SC850SL) += sms_sc850sl +sensor-$(CONFIG_SENSOR_SMS_SC3335) += sms_sc3335 +sensor-$(CONFIG_SENSOR_SMS_SC3335_SLAVE) += sms_sc3335_slave +sensor-$(CONFIG_SENSOR_SMS_SC3336) += sms_sc3336 +sensor-$(CONFIG_SENSOR_SMS_SC3336P) += sms_sc3336p +sensor-$(CONFIG_SENSOR_SMS_SC4210) += sms_sc4210 +sensor-$(CONFIG_SENSOR_SMS_SC8238) += sms_sc8238 +sensor-$(CONFIG_SENSOR_SOI_F23) += soi_f23 +sensor-$(CONFIG_SENSOR_SOI_F35) += soi_f35 +sensor-$(CONFIG_SENSOR_SOI_F35_SLAVE) += soi_f35_slave +sensor-$(CONFIG_SENSOR_SOI_H65) += soi_h65 +sensor-$(CONFIG_SENSOR_SONY_IMX290_2L) += sony_imx290_2L +sensor-$(CONFIG_SENSOR_SONY_IMX307) += sony_imx307 +sensor-$(CONFIG_SENSOR_SONY_IMX307_SLAVE) += sony_imx307_slave +sensor-$(CONFIG_SENSOR_SONY_IMX307_2L) += sony_imx307_2L +sensor-$(CONFIG_SENSOR_SONY_IMX307_SUBLVDS) += sony_imx307_sublvds +sensor-$(CONFIG_SENSOR_SONY_IMX327) += sony_imx327 +sensor-$(CONFIG_SENSOR_SONY_IMX327_SLAVE) += sony_imx327_slave +sensor-$(CONFIG_SENSOR_SONY_IMX327_2L) += sony_imx327_2L +sensor-$(CONFIG_SENSOR_SONY_IMX327_SUBLVDS) += sony_imx327_sublvds +sensor-$(CONFIG_SENSOR_SONY_IMX334) += sony_imx334 +sensor-$(CONFIG_SENSOR_SONY_IMX335) += sony_imx335 +sensor-$(CONFIG_SENSOR_SONY_IMX347) += sony_imx347 +sensor-$(CONFIG_SENSOR_SONY_IMX385) += sony_imx385 +sensor-$(CONFIG_SENSOR_TECHPOINT_TP2850) += techpoint_tp2850 +sensor-$(CONFIG_SENSOR_TECHPOINT_TP2825) += techpoint_tp2825 +sensor-$(CONFIG_SENSOR_TECHPOINT_TP2863) += techpoint_tp2863 +sensor-$(CONFIG_SENSOR_VIVO_MCS369) += vivo_mcs369 +sensor-$(CONFIG_SENSOR_VIVO_MCS369Q) += vivo_mcs369q +sensor-$(CONFIG_SENSOR_VIVO_MM308M2) += vivo_mm308m2 +else ifeq ($(CHIP_ARCH), $(filter $(CHIP_ARCH), CV180X CV181X CV182X SG200X)) +sensor-$(CONFIG_SENSOR_BRIGATES_BG0808) += brigates_bg0808 +sensor-$(CONFIG_SENSOR_CHIPUP_XS9922B) += chipup_xs9922b +sensor-$(CONFIG_SENSOR_CVSENS_CV2003) += cvsens_cv2003 +sensor-$(CONFIG_SENSOR_CVSENS_CV2003_1L) += cvsens_cv2003_1L +sensor-$(CONFIG_SENSOR_CVSENS_CV2003_1L_SLAVE) += cvsens_cv2003_1L_slave +sensor-$(CONFIG_SENSOR_CVSENS_CV2003_1L_SLAVE1) += cvsens_cv2003_1L_slave1 +sensor-$(CONFIG_SENSOR_CVSENS_CV4001) += cvsens_cv4001 +sensor-$(CONFIG_SENSOR_BYD_BF2253L) += byd_bf2253l +sensor-$(CONFIG_SENSOR_GCORE_GC02M1) += gcore_gc02m1 +sensor-$(CONFIG_SENSOR_GCORE_GC0312) += gcore_gc0312 +sensor-$(CONFIG_SENSOR_GCORE_GC0329) += gcore_gc0329 +sensor-$(CONFIG_SENSOR_GCORE_GC1054) += gcore_gc1054 +sensor-$(CONFIG_SENSOR_GCORE_GC1084) += gcore_gc1084 +sensor-$(CONFIG_SENSOR_GCORE_GC1084_SLAVE) += gcore_gc1084_slave +sensor-$(CONFIG_SENSOR_GCORE_GC1084_SLAVE1) += gcore_gc1084_slave1 +sensor-$(CONFIG_SENSOR_GCORE_GC1084_SLAVE2) += gcore_gc1084_slave2 +sensor-$(CONFIG_SENSOR_GCORE_GC2053) += gcore_gc2053 +sensor-$(CONFIG_SENSOR_GCORE_GC2053_SLAVE) += gcore_gc2053_slave +sensor-$(CONFIG_SENSOR_GCORE_GC2053_1L) += gcore_gc2053_1L +sensor-$(CONFIG_SENSOR_GCORE_GC2083) += gcore_gc2083 +sensor-$(CONFIG_SENSOR_GCORE_GC2093) += gcore_gc2093 +sensor-$(CONFIG_SENSOR_GCORE_GC2145) += gcore_gc2145 +sensor-$(CONFIG_SENSOR_GCORE_GC2385_1L) += gcore_gc2385_1L +sensor-$(CONFIG_SENSOR_GCORE_GC4023) += gcore_gc4023 +sensor-$(CONFIG_SENSOR_GCORE_GC4653) += gcore_gc4653 +sensor-$(CONFIG_SENSOR_GCORE_GC4653_SLAVE) += gcore_gc4653_slave +sensor-$(CONFIG_SENSOR_IMGDS_MIS2008) += imgds_mis2008 +sensor-$(CONFIG_SENSOR_IMGDS_MIS2008_1L) += imgds_mis2008_1L +sensor-$(CONFIG_SENSOR_NEXTCHIP_N5) += nextchip_n5 +sensor-$(CONFIG_SENSOR_NEXTCHIP_N6) += nextchip_n6 +sensor-$(CONFIG_SENSOR_OV_OS04A10) += ov_os04a10 +sensor-$(CONFIG_SENSOR_OV_OS04C10) += ov_os04c10 +sensor-$(CONFIG_SENSOR_OV_OS08A20) += ov_os08a20 +sensor-$(CONFIG_SENSOR_OV_OV4689) += ov_ov4689 +sensor-$(CONFIG_SENSOR_OV_OV5647) += ov_ov5647 +sensor-$(CONFIG_SENSOR_OV_OV6211) += ov_ov6211 +sensor-$(CONFIG_SENSOR_OV_OV7251) += ov_ov7251 +sensor-$(CONFIG_SENSOR_PIXELPLUS_PR2020) += pixelplus_pr2020 +sensor-$(CONFIG_SENSOR_PIXELPLUS_PR2100) += pixelplus_pr2100 +sensor-$(CONFIG_SENSOR_SMS_SC035GS) += sms_sc035gs +sensor-$(CONFIG_SENSOR_SMS_SC035GS_1L) += sms_sc035gs_1L +sensor-$(CONFIG_SENSOR_SMS_SC035HGS) += sms_sc035hgs +sensor-$(CONFIG_SENSOR_SMS_SC035HGS_1L) += sms_sc035hgs_1L +sensor-$(CONFIG_SENSOR_SMS_SC132GS) += sms_sc132gs +sensor-$(CONFIG_SENSOR_SMS_SC132GS_SLAVE) += sms_sc132gs_slave +sensor-$(CONFIG_SENSOR_SMS_SC1336_1L) += sms_sc1336_1L +sensor-$(CONFIG_SENSOR_SMS_SC1346_1L) += sms_sc1346_1L +sensor-$(CONFIG_SENSOR_SMS_SC1346_1L_SLAVE) += sms_sc1346_1L_slave +sensor-$(CONFIG_SENSOR_SMS_SC200AI) += sms_sc200ai +sensor-$(CONFIG_SENSOR_SMS_SC200AI_1L) += sms_sc200ai_1L +sensor-$(CONFIG_SENSOR_SMS_SC301IOT) += sms_sc301iot +sensor-$(CONFIG_SENSOR_SMS_SC401AI) += sms_sc401ai +sensor-$(CONFIG_SENSOR_SMS_SC500AI) += sms_sc500ai +sensor-$(CONFIG_SENSOR_SMS_SC501AI_2L) += sms_sc501ai_2L +sensor-$(CONFIG_SENSOR_SMS_SC531AI_2L) += sms_sc531ai_2L +sensor-$(CONFIG_SENSOR_SMS_SC3332) += sms_sc3332 +sensor-$(CONFIG_SENSOR_SMS_SC3335) += sms_sc3335 +sensor-$(CONFIG_SENSOR_SMS_SC3336) += sms_sc3336 +sensor-$(CONFIG_SENSOR_SMS_SC3336_1L) += sms_sc3336_1L +sensor-$(CONFIG_SENSOR_SMS_SC3336P) += sms_sc3336p +sensor-$(CONFIG_SENSOR_SMS_SC2331_1L) += sms_sc2331_1L +sensor-$(CONFIG_SENSOR_SMS_SC2331_1L_SLAVE) += sms_sc2331_1L_slave +sensor-$(CONFIG_SENSOR_SMS_SC2331_1L_SLAVE1) += sms_sc2331_1L_slave1 +sensor-$(CONFIG_SENSOR_SMS_SC2335) += sms_sc2335 +sensor-$(CONFIG_SENSOR_SMS_SC2336) += sms_sc2336 +sensor-$(CONFIG_SENSOR_SMS_SC2336_SLAVE) += sms_sc2336_slave +sensor-$(CONFIG_SENSOR_SMS_SC2336_SLAVE1) += sms_sc2336_slave1 +sensor-$(CONFIG_SENSOR_SMS_SC2336_1L) += sms_sc2336_1L +sensor-$(CONFIG_SENSOR_SMS_SC2336P) += sms_sc2336p +sensor-$(CONFIG_SENSOR_SMS_SC2336P_1L) += sms_sc2336p_1L +sensor-$(CONFIG_SENSOR_SMS_SC223A_1L) += sms_sc223a_1L +sensor-$(CONFIG_SENSOR_SMS_SC4336) += sms_sc4336 +sensor-$(CONFIG_SENSOR_SMS_SC4336P) += sms_sc4336p +sensor-$(CONFIG_SENSOR_SMS_SC5336_2L) += sms_sc5336_2L +sensor-$(CONFIG_SENSOR_SOI_F23) += soi_f23 +sensor-$(CONFIG_SENSOR_SOI_F35) += soi_f35 +sensor-$(CONFIG_SENSOR_SOI_F37P) += soi_f37p +sensor-$(CONFIG_SENSOR_SOI_Q03) += soi_q03 +sensor-$(CONFIG_SENSOR_SOI_Q03P) += soi_q03p +sensor-$(CONFIG_SENSOR_SOI_K06) += soi_k06 +sensor-$(CONFIG_SENSOR_SOI_F53) += soi_f53 +sensor-$(CONFIG_SENSOR_SOI_F352) += soi_f352 +sensor-$(CONFIG_SENSOR_SOI_K306) += soi_k306 +sensor-$(CONFIG_SENSOR_SONY_IMX307) += sony_imx307 +sensor-$(CONFIG_SENSOR_SONY_IMX307_SLAVE) += sony_imx307_slave +sensor-$(CONFIG_SENSOR_SONY_IMX307_2L) += sony_imx307_2L +sensor-$(CONFIG_SENSOR_SONY_IMX327) += sony_imx327 +sensor-$(CONFIG_SENSOR_SONY_IMX327_SLAVE) += sony_imx327_slave +sensor-$(CONFIG_SENSOR_SONY_IMX327_2L) += sony_imx327_2L +sensor-$(CONFIG_SENSOR_SONY_IMX327_FPGA) += sony_imx327_fpga +sensor-$(CONFIG_SENSOR_SONY_IMX327_SUBLVDS) += sony_imx327_sublvds +sensor-$(CONFIG_SENSOR_SONY_IMX335) += sony_imx335 +sensor-$(CONFIG_SENSOR_SONY_IMX675) += sony_imx675 +sensor-$(CONFIG_SENSOR_TECHPOINT_TP2825) += techpoint_tp2825 +sensor-$(CONFIG_SENSOR_TECHPOINT_TP2863) += techpoint_tp2863 +sensor-$(CONFIG_SENSOR_LONTIUM_LT6911) += lontium_lt6911 +sensor-$(CONFIG_SENSOR_LONTIUM_LT7911) += lontium_lt7911 +else +$(error not supported chip arch cv180x/cv181x/cv182x/cv183x) +endif diff --git a/middleware/v2/component/isp/sensor/cv182x/Makefile b/middleware/v2/component/isp/sensor/cv182x/Makefile index c11102548..64d89b99e 100644 --- a/middleware/v2/component/isp/sensor/cv182x/Makefile +++ b/middleware/v2/component/isp/sensor/cv182x/Makefile @@ -35,6 +35,9 @@ chipup_xs9922b: cvsens_cv2003: $(call MAKE_SENSOR, ${@}) +cvsens_cv2003_1L: + $(call MAKE_SENSOR, ${@}) + cvsens_cv2003_1L_slave: $(call MAKE_SENSOR, ${@}) @@ -86,6 +89,9 @@ gcore_gc2093: gcore_gc2145: $(call MAKE_SENSOR, ${@}) +gcore_gc2385_1L: + $(call MAKE_SENSOR, ${@}) + gcore_gc4023: $(call MAKE_SENSOR, ${@}) @@ -107,6 +113,9 @@ nextchip_n5: nextchip_n6: $(call MAKE_SENSOR, ${@}) +ov_os02n10_1L: + $(call MAKE_SENSOR, ${@}) + ov_os04a10: $(call MAKE_SENSOR, ${@}) @@ -293,6 +302,9 @@ sony_imx327_sublvds: sony_imx335: $(call MAKE_SENSOR, ${@}) +sony_imx675: + $(call MAKE_SENSOR, ${@}) + techpoint_tp2825: $(call MAKE_SENSOR, ${@}) diff --git a/middleware/v2/component/isp/sensor/cv182x/Makefile.orig b/middleware/v2/component/isp/sensor/cv182x/Makefile.orig new file mode 100644 index 000000000..ec6d47102 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/Makefile.orig @@ -0,0 +1,324 @@ +SHELL = /bin/bash + +ifeq ($(PARAM_FILE), ) +PARAM_FILE=../../../../../$(shell echo $(MW_VER))/Makefile.param +include $(PARAM_FILE) +endif +include ../../../../../$(shell echo $(MW_VER))/component/isp/sensor.mk + +define MAKE_SENSOR + pushd $(1) && \ + $(MAKE) all && \ + popd +endef + +.PHONY : prepare clean $(sensor-y) +all: prepare $(sensor-y) all_sensor + +prepare: + @echo "#################################################" + @echo "#" + @echo "# Compiling 'component libs' Configs as below..." + @echo "# SENSOR_LIST=$(sensor-y)" + @echo "#" + @echo "#################################################" + +brigates_bg0808: + $(call MAKE_SENSOR, ${@}) + +byd_bf2253l: + $(call MAKE_SENSOR, ${@}) + +chipup_xs9922b: + $(call MAKE_SENSOR, ${@}) + +cvsens_cv2003: + $(call MAKE_SENSOR, ${@}) + +cvsens_cv2003_1L: + $(call MAKE_SENSOR, ${@}) + +cvsens_cv2003_1L_slave: + $(call MAKE_SENSOR, ${@}) + +cvsens_cv2003_1L_slave1: + $(call MAKE_SENSOR, ${@}) + +cvsens_cv4001: + $(call MAKE_SENSOR, ${@}) + +gcore_gc02m1: + $(call MAKE_SENSOR, ${@}) + +gcore_gc0312: + $(call MAKE_SENSOR, ${@}) + +gcore_gc0329: + $(call MAKE_SENSOR, ${@}) + +gcore_gc1054: + $(call MAKE_SENSOR, ${@}) + +gcore_gc1084: + $(call MAKE_SENSOR, ${@}) + +gcore_gc1084_slave: + $(call MAKE_SENSOR, ${@}) + +gcore_gc1084_slave1: + $(call MAKE_SENSOR, ${@}) + +gcore_gc1084_slave2: + $(call MAKE_SENSOR, ${@}) + +gcore_gc2053: + $(call MAKE_SENSOR, ${@}) + +gcore_gc2053_slave: + $(call MAKE_SENSOR, ${@}) + +gcore_gc2053_1L: + $(call MAKE_SENSOR, ${@}) + +gcore_gc2083: + $(call MAKE_SENSOR, ${@}) + +gcore_gc2093: + $(call MAKE_SENSOR, ${@}) + +gcore_gc2145: + $(call MAKE_SENSOR, ${@}) + +gcore_gc2385_1L: + $(call MAKE_SENSOR, ${@}) + +gcore_gc4023: + $(call MAKE_SENSOR, ${@}) + +gcore_gc4653: + $(call MAKE_SENSOR, ${@}) + +gcore_gc4653_slave: + $(call MAKE_SENSOR, ${@}) + +imgds_mis2008: + $(call MAKE_SENSOR, ${@}) + +imgds_mis2008_1L: + $(call MAKE_SENSOR, ${@}) + +nextchip_n5: + $(call MAKE_SENSOR, ${@}) + +nextchip_n6: + $(call MAKE_SENSOR, ${@}) + +ov_os04a10: + $(call MAKE_SENSOR, ${@}) + +ov_os04c10: + $(call MAKE_SENSOR, ${@}) + +ov_os08a20: + $(call MAKE_SENSOR, ${@}) + +ov_ov4689: + $(call MAKE_SENSOR, ${@}) + +ov_ov5647: + $(call MAKE_SENSOR, ${@}) + +ov_ov6211: + $(call MAKE_SENSOR, ${@}) + +ov_ov7251: + $(call MAKE_SENSOR, ${@}) + +pixelplus_pr2020: + $(call MAKE_SENSOR, ${@}) + +pixelplus_pr2100: + $(call MAKE_SENSOR, ${@}) + +sms_sc035gs: + $(call MAKE_SENSOR, ${@}) + +sms_sc035gs_1L: + $(call MAKE_SENSOR, ${@}) + +sms_sc035hgs: + $(call MAKE_SENSOR, ${@}) + +sms_sc035hgs_1L: + $(call MAKE_SENSOR, ${@}) + +sms_sc132gs: + $(call MAKE_SENSOR, ${@}) + +sms_sc132gs_slave: + $(call MAKE_SENSOR, ${@}) + +sms_sc1336_1L: + $(call MAKE_SENSOR, ${@}) + +sms_sc1346_1L: + $(call MAKE_SENSOR, ${@}) + +sms_sc1346_1L_slave: + $(call MAKE_SENSOR, ${@}) + +sms_sc200ai: + $(call MAKE_SENSOR, ${@}) + +sms_sc200ai_1L: + $(call MAKE_SENSOR, ${@}) + +sms_sc301iot: + $(call MAKE_SENSOR, ${@}) + +sms_sc401ai: + $(call MAKE_SENSOR, ${@}) + +sms_sc500ai: + $(call MAKE_SENSOR, ${@}) + +sms_sc501ai_2L: + $(call MAKE_SENSOR, ${@}) + +sms_sc3332: + $(call MAKE_SENSOR, ${@}) + +sms_sc531ai_2L: + $(call MAKE_SENSOR, ${@}) + +sms_sc3335: + $(call MAKE_SENSOR, ${@}) + +sms_sc3336: + $(call MAKE_SENSOR, ${@}) + +sms_sc3336_1L: + $(call MAKE_SENSOR, ${@}) + +sms_sc3336p: + $(call MAKE_SENSOR, ${@}) + +sms_sc2331_1L: + $(call MAKE_SENSOR, ${@}) + +sms_sc2331_1L_slave: + $(call MAKE_SENSOR, ${@}) + +sms_sc2331_1L_slave1: + $(call MAKE_SENSOR, ${@}) + +sms_sc2335: + $(call MAKE_SENSOR, ${@}) + +sms_sc2336: + $(call MAKE_SENSOR, ${@}) + +sms_sc2336_slave: + $(call MAKE_SENSOR, ${@}) + +sms_sc2336_slave1: + $(call MAKE_SENSOR, ${@}) + +sms_sc2336_1L: + $(call MAKE_SENSOR, ${@}) + +sms_sc2336p: + $(call MAKE_SENSOR, ${@}) + +sms_sc2336p_1L: + $(call MAKE_SENSOR, ${@}) + +sms_sc223a_1L: + $(call MAKE_SENSOR, ${@}) + +sms_sc4336: + $(call MAKE_SENSOR, ${@}) + +sms_sc4336p: + $(call MAKE_SENSOR, ${@}) + +sms_sc5336_2L: + $(call MAKE_SENSOR, ${@}) + +soi_f23: + $(call MAKE_SENSOR, ${@}) + +soi_f35: + $(call MAKE_SENSOR, ${@}) + +soi_f37p: + $(call MAKE_SENSOR, ${@}) + +soi_q03: + $(call MAKE_SENSOR, ${@}) + +soi_q03p: + $(call MAKE_SENSOR, ${@}) + +soi_k06: + $(call MAKE_SENSOR, ${@}) + +soi_f53: + $(call MAKE_SENSOR, ${@}) + +soi_f352: + $(call MAKE_SENSOR, ${@}) + +soi_k306: + $(call MAKE_SENSOR, ${@}) + +sony_imx307: + $(call MAKE_SENSOR, ${@}) + +sony_imx307_slave: + $(call MAKE_SENSOR, ${@}) + +sony_imx307_2L: + $(call MAKE_SENSOR, ${@}) + +sony_imx327: + $(call MAKE_SENSOR, ${@}) + +sony_imx327_slave: + $(call MAKE_SENSOR, ${@}) + +sony_imx327_2L: + $(call MAKE_SENSOR, ${@}) + +sony_imx327_fpga: + $(call MAKE_SENSOR, ${@}) + +sony_imx327_sublvds: + $(call MAKE_SENSOR, ${@}) + +sony_imx335: + $(call MAKE_SENSOR, ${@}) + +sony_imx675: + $(call MAKE_SENSOR, ${@}) + +techpoint_tp2825: + $(call MAKE_SENSOR, ${@}) + +techpoint_tp2863: + $(call MAKE_SENSOR, ${@}) + +lontium_lt6911: + $(call MAKE_SENSOR, ${@}) + +lontium_lt7911: + $(call MAKE_SENSOR, ${@}) + +all_sensor: + @$(MAKE) -f Makefile_full || exit 1; + +clean: + @for x in `find ./ -maxdepth 2 -mindepth 2 -name "Makefile" `; \ + do cd `dirname $$x`; if [ $$? ]; then $(MAKE) clean; cd -; fi; done + @echo "#" + @$(MAKE) clean -f Makefile_full || exit 1; diff --git a/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/Makefile b/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/Makefile new file mode 100644 index 000000000..a88f8641b --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_cv2003_1L.a +TARGET_SO = $(MW_LIB)/libsns_cv2003_1L.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos.c b/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos.c new file mode 100644 index 000000000..36a96a32e --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos.c @@ -0,0 +1,1039 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "cv2003_1L_cmos_ex.h" +#include "cv2003_1L_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define CV2003_1L_ID 2003 +#define CV2003_1L_I2C_ADDR_1 0x35 +#define CV2003_1L_I2C_ADDR_2 0x36 +#define CV2003_1L_I2C_ADDR_IS_VALID(addr) ((addr) == CV2003_1L_I2C_ADDR_1 || (addr) == CV2003_1L_I2C_ADDR_2) + +/**************************************************************************** + * global variables * + ***************************************************************************/ + +ISP_SNS_STATE_S *g_pastCV2003_1L[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define CV2003_1L_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastCV2003_1L[dev]) +#define CV2003_1L_SENSOR_SET_CTX(dev, pstCtx) (g_pastCV2003_1L[dev] = pstCtx) +#define CV2003_1L_SENSOR_RESET_CTX(dev) (g_pastCV2003_1L[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunCV2003_1L_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 3}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +ISP_SNS_MIRRORFLIP_TYPE_E g_aeCV2003_1L_MirrorFip[VI_MAX_PIPE_NUM] = {0}; + +CVI_U16 g_au16CV2003_1L_GainMode[VI_MAX_PIPE_NUM] = {0}; + +/**************************************************************************** + * local variables and functions * + ***************************************************************************/ +static ISP_FSWDR_MODE_E genFSWDRMode[VI_MAX_PIPE_NUM] = { + [0 ... VI_MAX_PIPE_NUM - 1] = ISP_FSWDR_NORMAL_MODE +}; + +static CVI_U32 gu32MaxTimeGetCnt[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****CV2003_1L Lines Range*****/ +#define CV2003_1L_FULL_LINES_MAX (0xfffff / 2)//liner mode: vts_reg value is double real_vts +// #define CV2003_1L_FULL_LINES_MAX_2TO1_WDR (0xfffff / 4)//wdr mode: four + +/*****CV2003_1L_1L Register Address*****/ +#define CV2003_1L_EXP1_ADDR0 0x304a //bit[19:16] +#define CV2003_1L_EXP1_ADDR1 0x3049 +#define CV2003_1L_EXP1_ADDR2 0x3048 +#define CV2003_1L_EXP2_ADDR0 0x3066 +#define CV2003_1L_EXP2_ADDR1 0x3065 +#define CV2003_1L_EXP2_ADDR2 0x3064 + +#define CV2003_1L_GAINENABLE_ADDR 0x3141 //bit[7:0] + +#define CV2003_1L_AGAIN1_ADDR 0x3154 //bit[7:0] + +#define CV2003_1L_DGAIN1_H_ADDR 0x314d //bit[15:8] +#define CV2003_1L_DGAIN1_L_ADDR 0x314c //bit[7:0] + +#define CV2003_1L_VTS_ADDR0 0x3022 //bit[19:16] +#define CV2003_1L_VTS_ADDR1 0x3021 +#define CV2003_1L_VTS_ADDR2 0x3020 + +#define CV2003_1L_FLIP_MIRROR_ADDR 0x3028 + +#define CV2003_1L_RES_IS_1080P(w, h) ((w) == 1920 && (h) == 1080) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + const CV2003_1L_MODE_S *pstMode; + + CVI_U32 FpsMax; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astCV2003_1L_mode[pstSnsState->u8ImgMode]; + FpsMax = g_astCV2003_1L_mode[pstSnsState->u8ImgMode].f32MaxFps; + + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = CV2003_1L_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * FpsMax); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * FpsMax / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + + switch (pstSnsState->enWDRMode) { + default: + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = pstMode->f32MaxFps; + pstAeSnsDft->f32MinFps = pstMode->f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max; + pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + + pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u32Max; + pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u32Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u32Max; + pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u32Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 2; + pstAeSnsDft->u32AEResponseFrame = 3; + pstAeSnsDft->u32SnsResponseFrame = 5; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? + g_au32InitExposure[ViPipe] : pstMode->stExp[0].u16Def; + + break; + } + CVI_TRACE_SNS(CVI_DBG_INFO, "again[%d, %d], dgain[%d, %d]\n", + pstAeSnsDft->u32MinAgain, pstAeSnsDft->u32MaxAgain, pstAeSnsDft->u32MinDgain, pstAeSnsDft->u32MaxDgain); + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX = 0; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + u32Vts = g_astCV2003_1L_mode[pstSnsState->u8ImgMode].u32VtsDef; + f32MaxFps = g_astCV2003_1L_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astCV2003_1L_mode[pstSnsState->u8ImgMode].f32MinFps; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + + u32VMAX = (u32VMAX > CV2003_1L_FULL_LINES_MAX) ? + CV2003_1L_FULL_LINES_MAX : u32VMAX; + pstSnsRegsInfo->astI2cData[LINEAR_VTS_0].u32Data = (((u32VMAX * 2) & 0xFF0000) >> 16); + pstSnsRegsInfo->astI2cData[LINEAR_VTS_1].u32Data = (((u32VMAX * 2) & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_VTS_2].u32Data = ((u32VMAX * 2) & 0xFF); + } + + pstSnsState->u32FLStd = u32VMAX; + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_S32 Reg_IntTime1; + // CVI_S32 Reg_IntTime2; + + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + Reg_IntTime1 = (pstSnsState->u32FLStd - u32IntTime[0]) * 2; + + pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = ((Reg_IntTime1 >> 16) & 0x0F); + pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = ((Reg_IntTime1 >> 8) & 0xFF); + pstSnsRegsInfo->astI2cData[LINEAR_EXP_2].u32Data = (Reg_IntTime1 & 0xFF); + } + + return CVI_SUCCESS; +} + +static CVI_U32 gain_table[250] = { + 1024, 1024, 1024, 1024, 1040, + 1040, 1040, 1040, 1056, 1056, + 1056, 1056, 1072, 1072, 1072, + 1072, 1088, 1088, 1088, 1104, + 1104, 1104, 1120, 1120, 1120, + 1120, 1136, 1136, 1136, 1152, + 1152, 1152, 1168, 1168, 1168, + 1184, 1184, 1184, 1200, 1200, + 1200, 1216, 1216, 1216, 1232, + 1232, 1248, 1248, 1248, 1264, + 1264, 1264, 1280, 1280, 1296, + 1296, 1296, 1312, 1312, 1328, + 1328, 1344, 1344, 1344, 1360, + 1360, 1376, 1376, 1392, 1392, + 1408, 1408, 1424, 1424, 1440, + 1440, 1456, 1456, 1472, 1472, + 1488, 1488, 1504, 1504, 1520, + 1520, 1536, 1536, 1552, 1568, + 1568, 1584, 1584, 1600, 1616, + 1616, 1632, 1648, 1648, 1664, + 1680, 1680, 1696, 1712, 1712, + 1728, 1744, 1744, 1760, 1776, + 1792, 1808, 1808, 1824, 1840, + 1856, 1872, 1872, 1904, 1904, + 1920, 1936, 1952, 1968, 1984, + 2000, 2016, 2016, 2048, 2064, + 2080, 2096, 2112, 2128, 2144, + 2160, 2176, 2192, 2208, 2240, + 2256, 2272, 2288, 2304, 2336, + 2352, 2368, 2400, 2416, 2448, + 2464, 2496, 2512, 2544, 2560, + 2576, 2608, 2640, 2672, 2688, + 2720, 2752, 2784, 2816, 2848, + 2880, 2912, 2944, 2976, 2008, + 3040, 3072, 3120, 3152, 3184, + 3232, 3264, 3312, 3360, 3392, + 3440, 3488, 3536, 3584, 3632, + 3680, 3744, 3792, 3840, 3904, + 3968, 4032, 4096, 4160, 4224, + 4288, 4368, 4432, 4512, 4592, + 4672, 4752, 4848, 4944, 5040, + 5136, 5232, 5344, 5456, 5568, + 5696, 5824, 5952, 6080, 6240, + 6384, 6384, 6720, 6896, 7072, + 7280, 7488, 7696, 7936, 8192, + 8448, 8736, 9024, 9360, 9696, + 10080, 10480, 10912, 11392, 11904, + 12480, 13104, 13792, 14560, 15408, + 16384, 17472, 18720, 20160, 21840, + 23824, 26208, 29120, 32768, 0xFFFF, +}; + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + int i, total; + CVI_U32 pregain; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + UNUSED(ViPipe); + total = sizeof(gain_table) / sizeof(CVI_U32); + + if (*pu32AgainLin >= gain_table[total - 1]) { + *pu32AgainLin = *pu32AgainDb = gain_table[total - 1]; + return CVI_SUCCESS; + } + + for (i = 1; i < total; i++) { + if (*pu32AgainLin < gain_table[i]) + break; + } + i--; + // find the pregain + pregain = *pu32AgainLin * 64 / gain_table[i]; + // set the Db as the AE algo gain, we need this to do gain update + *pu32AgainDb = *pu32AgainLin; + // set the Lin as the closest sensor gain for AE algo reference + *pu32AgainLin = pregain * gain_table[i] / 64; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + CVI_U32 pregain; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + UNUSED(ViPipe); + // find the pregain + pregain = *pu32DgainLin * 64 / 1024; + // set the Db as the AE algo gain, we need this to do gain update + *pu32DgainDb = *pu32DgainLin; + // set the Lin as the closest sensor gain for AE algo reference + *pu32DgainLin = pregain * 16; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + int i, total; + + total = sizeof(gain_table) / sizeof(CVI_U32); + + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + /* only surpport linear mode */ + for (i = 0; i < total; i++) { + if ((gain_table[i] <= pu32Again[0]) && (gain_table[i+1] >= pu32Again[0])) { + break; + } + } + + u32Again = i; + u32Dgain = pu32Dgain[0] / 16; + if (u32Dgain < 64) { + u32Dgain = 64; + } + if (u32Dgain > 1024) { + u32Dgain = 1024; + } + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstSnsRegsInfo->astI2cData[LINEAR_GAINENABLE].u32Data = 1; + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN].u32Data = u32Again; + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_H].u32Data = (u32Dgain >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_L].u32Data = (u32Dgain & 0xFF); + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio, + CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime) +{ + CVI_U32 u32IntTimeMaxTmp = 0, u32IntTimeMaxTmp0 = 0; + CVI_U32 u32RatioTmp = 0x40; + CVI_U32 u32ShortTimeMinLimit = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(au32Ratio); + CMOS_CHECK_POINTER(au32IntTimeMax); + CMOS_CHECK_POINTER(au32IntTimeMin); + CMOS_CHECK_POINTER(pu32LFMaxIntTime); + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32ShortTimeMinLimit = 1; + /* + * Long exp + Short exp < VTS + */ + u32IntTimeMaxTmp0 = ((pstSnsState->au32FL[1] - 1 - g_astCV2003_1L_mode[pstSnsState->u8ImgMode].u32IspResTime - + pstSnsState->au32WDRIntTime[0]) * 0x40) / DIV_0_TO_1(au32Ratio[0]); + u32IntTimeMaxTmp = ((pstSnsState->au32FL[0] - 1 - g_astCV2003_1L_mode[pstSnsState->u8ImgMode].u32IspResTime) + * 0x40) / DIV_0_TO_1(au32Ratio[0] + 0x40); + u32IntTimeMaxTmp = (u32IntTimeMaxTmp > u32IntTimeMaxTmp0) ? u32IntTimeMaxTmp0 : u32IntTimeMaxTmp; + u32IntTimeMaxTmp = (!u32IntTimeMaxTmp) ? u32ShortTimeMinLimit : u32IntTimeMaxTmp; + + if (u32IntTimeMaxTmp >= u32ShortTimeMinLimit) { + if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) { + au32IntTimeMax[0] = u32IntTimeMaxTmp; + au32IntTimeMax[1] = au32IntTimeMax[0] * au32Ratio[0] >> 6; + au32IntTimeMax[2] = au32IntTimeMax[1] * au32Ratio[1] >> 6; + au32IntTimeMax[3] = au32IntTimeMax[2] * au32Ratio[2] >> 6; + au32IntTimeMin[0] = u32ShortTimeMinLimit; + au32IntTimeMin[1] = au32IntTimeMin[0] * au32Ratio[0] >> 6; + au32IntTimeMin[2] = au32IntTimeMin[1] * au32Ratio[1] >> 6; + au32IntTimeMin[3] = au32IntTimeMin[2] * au32Ratio[2] >> 6; + } else { + } + } else { + if (u16ManRatioEnable) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Manaul ExpRatio is too large!\n"); + return CVI_FAILURE; + } + u32IntTimeMaxTmp = u32ShortTimeMinLimit; + + if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) { + u32RatioTmp = 0xFFF; + au32IntTimeMax[0] = u32IntTimeMaxTmp; + au32IntTimeMax[1] = au32IntTimeMax[0] * u32RatioTmp >> 6; + } else { + } + au32IntTimeMin[0] = au32IntTimeMax[0]; + au32IntTimeMin[1] = au32IntTimeMax[1]; + au32IntTimeMin[2] = au32IntTimeMax[2]; + au32IntTimeMin[3] = au32IntTimeMax[3]; + } + CVI_TRACE_SNS(CVI_DBG_DEBUG, "sexp[%d, %d], lexp[%d, %d], ratio:%d\n", + au32IntTimeMin[0], au32IntTimeMax[0], au32IntTimeMin[1], au32IntTimeMax[1], au32Ratio[0]); + + return CVI_SUCCESS; +} + +/* Only used in LINE_WDR mode */ +static CVI_S32 cmos_ae_fswdr_attr_set(VI_PIPE ViPipe, AE_FSWDR_ATTR_S *pstAeFSWDRAttr) +{ + CMOS_CHECK_POINTER(pstAeFSWDRAttr); + + genFSWDRMode[ViPipe] = pstAeFSWDRAttr->enFSWDRMode; + gu32MaxTimeGetCnt[ViPipe] = 0; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + UNUSED(ViPipe); + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + UNUSED(ViPipe); + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + UNUSED(ViPipe); + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const CV2003_1L_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astCV2003_1L_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } else { + pstIspCfg->frm_num = 2; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S)); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + if (pstSnsState->u8ImgMode == CV2003_1L_MODE_1920X1080P15_WDR) + pstSnsState->u8ImgMode = CV2003_1L_MODE_1920X1080P30; + + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astCV2003_1L_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "WDR_MODE_NONE\n"); + break; + + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunCV2003_1L_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = cv2003_1l_i2c_addr; + pstI2c_data[i].u32AddrByteNum = cv2003_1l_addr_byte; + pstI2c_data[i].u32DataByteNum = cv2003_1l_data_byte; + } + + switch (pstSnsState->enWDRMode) { + default: + pstI2c_data[LINEAR_EXP_0].u32RegAddr = CV2003_1L_EXP1_ADDR0; + pstI2c_data[LINEAR_EXP_1].u32RegAddr = CV2003_1L_EXP1_ADDR1; + pstI2c_data[LINEAR_EXP_2].u32RegAddr = CV2003_1L_EXP1_ADDR2; + pstI2c_data[LINEAR_GAINENABLE].u32RegAddr = CV2003_1L_GAINENABLE_ADDR; + pstI2c_data[LINEAR_AGAIN].u32RegAddr = CV2003_1L_AGAIN1_ADDR; + pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = CV2003_1L_DGAIN1_H_ADDR; + pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = CV2003_1L_DGAIN1_L_ADDR; + pstI2c_data[LINEAR_VTS_0].u32RegAddr = CV2003_1L_VTS_ADDR0; + pstI2c_data[LINEAR_VTS_1].u32RegAddr = CV2003_1L_VTS_ADDR1; + pstI2c_data[LINEAR_VTS_2].u32RegAddr = CV2003_1L_VTS_ADDR2; + pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = CV2003_1L_FLIP_MIRROR_ADDR; + break; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) + pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (CV2003_1L_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) + u8SensorImageMode = CV2003_1L_MODE_1920X1080P30; + else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps); + return CVI_FAILURE; + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 value = 0x0; + CVI_U8 start_x = 0; + CVI_U8 start_y = 0; + + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_ISP_INFO_S *pstIspCfg0 = CVI_NULL; + + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + pstIspCfg0 = &pstSnsState->astSyncInfo[0].ispCfg; + + /* Apply the setting on the fly */ + if (pstSnsState->bInit == CVI_TRUE && g_aeCV2003_1L_MirrorFip[ViPipe] != eSnsMirrorFlip) { + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + value = 0x0; + start_x = 0; + start_y = 0; + break; + case ISP_SNS_MIRROR: + value = 0x1; + start_x = 1; + start_y = 0; + break; + case ISP_SNS_FLIP: + value = 0x2; + start_x = 0; + start_y = 1; + break; + case ISP_SNS_MIRROR_FLIP: + value = 0x3; + start_x = 1; + start_y = 1; + break; + default: + return; + } + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value; + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1; + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2; + } + g_aeCV2003_1L_MirrorFip[ViPipe] = eSnsMirrorFlip; + pstIspCfg0->img_size[0].stWndRect.s32X = start_x; + pstIspCfg0->img_size[0].stWndRect.s32Y = start_y; + + } +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = CV2003_1L_MODE_1920X1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astCV2003_1L_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsState->au32FL[0] = g_astCV2003_1L_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsState->au32FL[1] = g_astCV2003_1L_mode[pstSnsState->u8ImgMode].u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CV2003_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &CV2003_1L_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astCV2003_1L_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astCV2003_1L_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } else { + pstRxAttr->mac_clk = RX_MAC_CLK_400M; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &CV2003_1L_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= VI_MAX_DEV_NUM) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = CV2003_1L_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = CV2003_1L_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (CV2003_1L_I2C_ADDR_IS_VALID(s32I2cAddr)) + cv2003_1l_i2c_addr = s32I2cAddr; +} + +static CVI_S32 CV2003_1L_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunCV2003_1L_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + CV2003_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + CV2003_1L_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + CV2003_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + CV2003_1L_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = CV2003_1L_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, CV2003_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, CV2003_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, CV2003_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16CV2003_1L_GainMode[ViPipe] = pstInitAttr->enGainMode; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_probe(VI_PIPE ViPipe) +{ + return CV2003_1L_probe(ViPipe); +} + +ISP_SNS_OBJ_S stSnsCV2003_1L_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = CV2003_1L_standby, + .pfnRestart = CV2003_1L_restart, + .pfnWriteReg = CV2003_1L_write_register, + .pfnReadReg = CV2003_1L_read_register, + .pfnSetBusInfo = CV2003_1L_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sensor_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos_ex.h b/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos_ex.h new file mode 100644 index 000000000..1a3ec64bc --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos_ex.h @@ -0,0 +1,90 @@ +#ifndef __CV2003_1L_CMOS_EX_H_ +#define __CV2003_1L_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +#ifndef UNUSED +#define UNUSED(x) ((void)(x)) +#endif + +enum CV2003_1L_linear_regs_e { + LINEAR_EXP_0, //0x3062 bit[19:16] + LINEAR_EXP_1, //0x3061 + LINEAR_EXP_2, //0x3060 + LINEAR_GAINENABLE, //0x3180 bit[7:0] + LINEAR_AGAIN, //0x3180 bit[7:0] + LINEAR_DGAIN_H, //0x3179 bit[15:8] + LINEAR_DGAIN_L, //0x3178 bit[7:0] + LINEAR_VTS_0, //0x302A bit[19:16] + LINEAR_VTS_1, //0x3029 + LINEAR_VTS_2, //0x3028 + LINEAR_FLIP_MIRROR, //0x3034 + LINEAR_REGS_NUM +}; + +typedef enum _CV2003_1L_MODE_E { + CV2003_1L_MODE_1920X1080P30 = 0, + CV2003_1L_MODE_LINEAR_NUM, + CV2003_1L_MODE_1920X1080P15_WDR = CV2003_1L_MODE_LINEAR_NUM, + CV2003_1L_MODE_NUM +} CV2003_1L_MODE_E; + +typedef struct _CV2003_1L_STATE_S { + CVI_U32 u32Sexp_MAX; +} CV2003_1L_STATE_S; + +typedef struct _CV2003_1L_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + CVI_U32 u32IspResTime; + SNS_ATTR_LARGE_S stAgain[2]; + SNS_ATTR_LARGE_S stDgain[2]; + char name[64]; +} CV2003_1L_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastCV2003_1L[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunCV2003_1L_BusInfo[]; +extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeCV2003_1L_MirrorFip[VI_MAX_PIPE_NUM]; +extern CVI_U8 cv2003_1l_i2c_addr; +extern const CVI_U32 cv2003_1l_addr_byte; +extern const CVI_U32 cv2003_1l_data_byte; +extern void CV2003_1L_init(VI_PIPE ViPipe); +extern void CV2003_1L_exit(VI_PIPE ViPipe); +extern void CV2003_1L_standby(VI_PIPE ViPipe); +extern void CV2003_1L_restart(VI_PIPE ViPipe); +extern int CV2003_1L_write_register(VI_PIPE ViPipe, int addr, int data); +extern int CV2003_1L_read_register(VI_PIPE ViPipe, int addr); +extern int CV2003_1L_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __CV2003_1L_CMOS_EX_H_ */ + diff --git a/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos_param.h b/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos_param.h new file mode 100644 index 000000000..441dd77c9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_cmos_param.h @@ -0,0 +1,124 @@ +#ifndef __CV2003_1L_CMOS_PARAM_H_ +#define __CV2003_1L_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "cv2003_1L_cmos_ex.h" + +static const CV2003_1L_MODE_S g_astCV2003_1L_mode[CV2003_1L_MODE_NUM] = { + [CV2003_1L_MODE_1920X1080P30] = { + .name = "1920X1080P30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1928, + .u32Height = 1088, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1928, + .u32Height = 1088, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 0.064, /* 1125 * 30 / (0x0FFFFF / 2) */ + .u32HtsDef = 720, //hts_reg + .u32VtsDef = 1125, //vts_reg / 2 + .stExp[0] = { + .u16Min = 4, + .u16Max = 1125-2, + .u16Def = 4, + .u16Step = 1, + }, + .stAgain[0] = { + .u32Min = 1024, + .u32Max = 16384, + .u32Def = 1024, + .u32Step = 1, + }, + .stDgain[0] = { + .u32Min = 1024, + .u32Max = 16384, + .u32Def = 1024, + .u32Step = 64, + }, + }, +}; + + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {200, 200, 200, 200, 0, 0, 0, 0 +#ifdef ARCH_CV182X + , 1075, 1075, 1075, 1075 +#endif + }, + .stAuto = { + {200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200 }, + {200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200 }, + {200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200 }, + {200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200 }, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, + 1075, 1075}, + {1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, + 1075, 1075}, + {1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, + 1075, 1075}, + {1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, + 1075, 1075}, +#endif + }, + }, +}; + +struct combo_dev_attr_s CV2003_1L_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {3, 2, -1, -1, -1}, + .pn_swap = {0, 0, 0, 0, 0}, + .wdr_mode = CVI_MIPI_WDR_MODE_VC, + }, + .mclk = { + .cam = 1, + .freq = CAMPLL_FREQ_24M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __CV2003_1L_CMOS_PARAM_H_ */ + diff --git a/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_sensor_ctl.c new file mode 100644 index 000000000..ea75f4474 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/cvsens_cv2003_1L/cv2003_1L_sensor_ctl.c @@ -0,0 +1,289 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "cv2003_1L_cmos_ex.h" + +#define CV2003_1L_CHIP_ID_ADDR_H 0x307A +#define CV2003_1L_CHIP_ID_ADDR_L 0x3138 +#define CV2003_1L_CHIP_ID 0x0203 + +static void CV2003_1L_linear_1080P30_init(VI_PIPE ViPipe); + +CVI_U8 cv2003_1l_i2c_addr = 0x36; +const CVI_U32 cv2003_1l_addr_byte = 2; +const CVI_U32 cv2003_1l_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int CV2003_1L_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunCV2003_1L_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, cv2003_1l_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int CV2003_1L_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int CV2003_1L_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (cv2003_1l_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, cv2003_1l_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, cv2003_1l_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (cv2003_1l_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int CV2003_1L_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (cv2003_1l_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + if (cv2003_1l_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, cv2003_1l_addr_byte + cv2003_1l_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + ret = read(g_fd[ViPipe], buf, cv2003_1l_addr_byte + cv2003_1l_data_byte); + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void CV2003_1L_standby(VI_PIPE ViPipe) +{ + CV2003_1L_write_register(ViPipe, 0x3000, 0x1); + + printf("%s\n", __func__); +} + +void CV2003_1L_restart(VI_PIPE ViPipe) +{ + CV2003_1L_write_register(ViPipe, 0x3000, 0x01); + delay_ms(20); + CV2003_1L_write_register(ViPipe, 0x3000, 0x00); + + printf("%s\n", __func__); +} + +void CV2003_1L_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastCV2003_1L[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + CV2003_1L_write_register(ViPipe, + g_pastCV2003_1L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastCV2003_1L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +int CV2003_1L_probe(VI_PIPE ViPipe) +{ + int nVal; + int nVal2; + + usleep(50); + if (CV2003_1L_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = CV2003_1L_read_register(ViPipe, CV2003_1L_CHIP_ID_ADDR_H); + nVal2 = CV2003_1L_read_register(ViPipe, CV2003_1L_CHIP_ID_ADDR_L); + if (nVal < 0 || nVal2 < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + + if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != CV2003_1L_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +void CV2003_1L_init(VI_PIPE ViPipe) +{ + CVI_U8 u8ImgMode; + + u8ImgMode = g_pastCV2003_1L[ViPipe]->u8ImgMode; + + CV2003_1L_i2c_init(ViPipe); + + if (u8ImgMode == CV2003_1L_MODE_1920X1080P30) { + CV2003_1L_linear_1080P30_init(ViPipe); + } + // } + + g_pastCV2003_1L[ViPipe]->bInit = CVI_TRUE; +} + +void CV2003_1L_exit(VI_PIPE ViPipe) +{ + CV2003_1L_i2c_exit(ViPipe); +} + +static void CV2003_1L_linear_1080P30_init(VI_PIPE ViPipe) +{ + delay_ms(10); + + //30fps + CV2003_1L_write_register(ViPipe, 0x3300, 0x03); + CV2003_1L_write_register(ViPipe, 0x3422, 0xBF); + CV2003_1L_write_register(ViPipe, 0x3401, 0x00); + CV2003_1L_write_register(ViPipe, 0x3440, 0x01); + CV2003_1L_write_register(ViPipe, 0x3442, 0x00); + // CV2003_1L_write_register(ViPipe, 0x3460, 0x03);//drive capability + CV2003_1L_write_register(ViPipe, 0x3806, 0x00); + CV2003_1L_write_register(ViPipe, 0x3908, 0x5F); + CV2003_1L_write_register(ViPipe, 0x3909, 0x00); + CV2003_1L_write_register(ViPipe, 0x3929, 0x01); + CV2003_1L_write_register(ViPipe, 0x3158, 0x01); + CV2003_1L_write_register(ViPipe, 0x3159, 0x01); + CV2003_1L_write_register(ViPipe, 0x315A, 0x01); + CV2003_1L_write_register(ViPipe, 0x315B, 0x01); + CV2003_1L_write_register(ViPipe, 0x35b3, 0x15); + CV2003_1L_write_register(ViPipe, 0x3148, 0x64); + CV2003_1L_write_register(ViPipe, 0x3031, 0x00); + CV2003_1L_write_register(ViPipe, 0x3118, 0x01); + CV2003_1L_write_register(ViPipe, 0x3119, 0x06); + CV2003_1L_write_register(ViPipe, 0x3670, 0x00); + CV2003_1L_write_register(ViPipe, 0x3679, 0x02); + CV2003_1L_write_register(ViPipe, 0x3330, 0x00); + CV2003_1L_write_register(ViPipe, 0x320e, 0x02); + CV2003_1L_write_register(ViPipe, 0x3804, 0x10); + CV2003_1L_write_register(ViPipe, 0x35a1, 0x06); + CV2003_1L_write_register(ViPipe, 0x35a8, 0x06); + CV2003_1L_write_register(ViPipe, 0x35a9, 0x06); + CV2003_1L_write_register(ViPipe, 0x35aa, 0x06); + CV2003_1L_write_register(ViPipe, 0x35ab, 0x06); + CV2003_1L_write_register(ViPipe, 0x35ac, 0x06); + CV2003_1L_write_register(ViPipe, 0x35ad, 0x06); + CV2003_1L_write_register(ViPipe, 0x35ae, 0x07); + CV2003_1L_write_register(ViPipe, 0x35af, 0x07); + CV2003_1L_write_register(ViPipe, 0x333B, 0x01); + CV2003_1L_write_register(ViPipe, 0x3338, 0x08); + CV2003_1L_write_register(ViPipe, 0x3339, 0x00); + CV2003_1L_write_register(ViPipe, 0x3144, 0x20); + CV2003_1L_write_register(ViPipe, 0x301c, 0x00); + CV2003_1L_write_register(ViPipe, 0x3030, 0x01); + CV2003_1L_write_register(ViPipe, 0x3020, 0xCA); + CV2003_1L_write_register(ViPipe, 0x3021, 0x08); + CV2003_1L_write_register(ViPipe, 0x3024, 0x80); + CV2003_1L_write_register(ViPipe, 0x3025, 0x02); + CV2003_1L_write_register(ViPipe, 0x3038, 0x00); + CV2003_1L_write_register(ViPipe, 0x3039, 0x00); + CV2003_1L_write_register(ViPipe, 0x303A, 0x88); + CV2003_1L_write_register(ViPipe, 0x303B, 0x07); + CV2003_1L_write_register(ViPipe, 0x3034, 0x00); + CV2003_1L_write_register(ViPipe, 0x3035, 0x00); + CV2003_1L_write_register(ViPipe, 0x3036, 0x40); + CV2003_1L_write_register(ViPipe, 0x3037, 0x04); + CV2003_1L_write_register(ViPipe, 0x3908, 0x48); + CV2003_1L_write_register(ViPipe, 0x390A, 0x02); + + //slave mode + // CV2003_1L_write_register(ViPipe, 0x3001, 0x01); + // CV2003_1L_write_register(ViPipe, 0x307A, 0x02); + // CV2003_1L_write_register(ViPipe, 0x306D, 0x0F); + + CV2003_1L_default_reg_init(ViPipe); + delay_ms(100); + CV2003_1L_write_register(ViPipe, 0x3000, 0x00); + + printf("ViPipe:%d,===CV2003_1L 1080P 30fps 12bit LINEAR Init OK!===\n", ViPipe); +} diff --git a/middleware/v2/component/isp/sensor/cv182x/gcore_gc2053/gc2053_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2053/gc2053_sensor_ctl.c index 007ac86bf..b357cea71 100644 --- a/middleware/v2/component/isp/sensor/cv182x/gcore_gc2053/gc2053_sensor_ctl.c +++ b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2053/gc2053_sensor_ctl.c @@ -385,7 +385,7 @@ static void gc2053_linear_1080p30_init(VI_PIPE ViPipe) gc2053_write_register(ViPipe, 0x03, 0x8e); gc2053_write_register(ViPipe, 0x12, 0x80); gc2053_write_register(ViPipe, 0x13, 0x07); - gc2053_write_register(ViPipe, 0x15, 0x12); + gc2053_write_register(ViPipe, 0x15, 0x10); gc2053_write_register(ViPipe, 0xfe, 0x00); gc2053_write_register(ViPipe, 0x3e, 0x91); diff --git a/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/Makefile b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/Makefile new file mode 100644 index 000000000..548a8fc76 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_gc2385_1l.a +TARGET_SO = $(MW_LIB)/libsns_gc2385_1l.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos.c b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos.c new file mode 100644 index 000000000..2f49ad050 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos.c @@ -0,0 +1,985 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "gc2385_1l_cmos_ex.h" +#include "gc2385_1l_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define GC2385_1L_ID 2385 + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastGc2385_1L[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define GC2385_1L_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc2385_1L[dev]) +#define GC2385_1L_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc2385_1L[dev] = pstCtx) +#define GC2385_1L_SENSOR_RESET_CTX(dev) (g_pastGc2385_1L[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunGc2385_1L_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +GC2385_1L_STATE_S g_astGc2385_1L_State[VI_MAX_PIPE_NUM] = { {0} }; +ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc2385_1L_MirrorFip[VI_MAX_PIPE_NUM] = {0}; + +CVI_U16 g_au16Gc2385_1L_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16Gc2385_1L_L2SMode[VI_MAX_PIPE_NUM] = {0}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static ISP_FSWDR_MODE_E genFSWDRMode[VI_MAX_PIPE_NUM] = { + [0 ... VI_MAX_PIPE_NUM - 1] = ISP_FSWDR_NORMAL_MODE +}; + +static CVI_U32 gu32MaxTimeGetCnt[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****Gc2385_1L Lines Range*****/ +#define GC2385_1L_FULL_LINES_MAX (0x3fff) + +/*****Gc2385_1L Register Address*****/ +#define GC2385_1L_EXP_PAGE_ADDR 0xfe +#define GC2385_1L_EXP_H_ADDR 0x03 +#define GC2385_1L_EXP_L_ADDR 0x04 +#define GC2385_1L_VB_PAGE_ADDR 0xfe +#define GC2385_1L_VB_H_ADDR 0x07 +#define GC2385_1L_VB_L_ADDR 0x08 +#define GC2385_1L_FLIP_MIRROR_PAGE_ADDR 0xfe +#define GC2385_1L_FLIP_MIRROR_ADDR 0x17 +#define GC2385_1L_CROP_START_X_ADDR 0x94 +#define GC2385_1L_CROP_START_Y_ADDR 0x92 +#define GC2385_1L_BLK_SELECT1_H_ADDR 0x4e +#define GC2385_1L_BLK_SELECT1_L_ADDR 0x4f +#define GC2385_1L_AGAIN_PAGE_ADDR 0xfe +#define GC2385_1L_T_INIT_SET_ADDR 0x20 +#define GC2385_1L_T_CLK_HS_ADDR 0x22 +#define GC2385_1L_COL_CODE_ADDR 0xb6 +#define GC2385_1L_AUTO_PREGAIN_SYNC_ADDR 0xb1 +#define GC2385_1L_AUTO_PREGAIN_ADDR 0xb2 + +#define GC2385_1L_RES_IS_1200P(w, h) ((w) <= 1600 && (h) <= 1200) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + const GC2385_1L_MODE_S *pstMode; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + GC2385_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_stGc2385_1L_mode; + + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = GC2385_1L_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; +#if 0 + pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0; + pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0; + + pstAeSnsDft->bAERouteExValid = CVI_FALSE; + pstAeSnsDft->stAERouteAttr.u32TotalNum = 0; + pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0; +#endif + switch (pstSnsState->enWDRMode) { + default: + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = pstMode->f32MaxFps; + pstAeSnsDft->f32MinFps = pstMode->f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = pstMode->stAgain.u32Max; + pstAeSnsDft->u32MinAgain = pstMode->stAgain.u32Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = pstMode->stDgain.u32Max; + pstAeSnsDft->u32MinDgain = pstMode->stDgain.u32Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : + pstMode->stExp.u16Def; + + pstAeSnsDft->u32MaxIntTime = pstMode->stExp.u16Max; + pstAeSnsDft->u32MinIntTime = pstMode->stExp.u16Min; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + + case WDR_MODE_2To1_LINE: + break; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX = 0; + CVI_U32 u32VB = 0; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + GC2385_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_stGc2385_1L_mode.u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_stGc2385_1L_mode.f32MaxFps; + f32MinFps = g_stGc2385_1L_mode.f32MinFps; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > GC2385_1L_FULL_LINES_MAX) ? GC2385_1L_FULL_LINES_MAX : u32VMAX; + + u32VB = u32VMAX - 1200 - 32; + pstSnsRegsInfo->astI2cData[LINEAR_VB_H].u32Data = ((u32VB & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_VB_L].u32Data = (u32VB & 0xFF); + } + + pstSnsState->u32FLStd = u32VMAX; + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 1; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + GC2385_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + pstSnsRegsInfo->astI2cData[LINEAR_EXP_H].u32Data = ((u32IntTime[0] >> 8 )& 0x3F); + pstSnsRegsInfo->astI2cData[LINEAR_EXP_L].u32Data = (u32IntTime[0] & 0xFF); + + return CVI_SUCCESS; +} + +static CVI_U32 regValTable[9][3] = { + /* [reg] 0x20, 0x22, 0xb6 + * [name] T_init_set, T_CLK_HS_PREPARE_set, Buf_col_code + */ + {0x73, 0xa2, 0x00}, + {0x73, 0xa2, 0x01}, + {0x73, 0xa2, 0x02}, + {0x73, 0xa2, 0x03}, + {0x73, 0xa3, 0x04}, + {0x74, 0xa3, 0x05}, + {0x74, 0xa3, 0x06}, + {0x74, 0xa3, 0x07}, + {0x75, 0xa4, 0x08}, +}; + +static CVI_U32 gain_table[10] = { + 16*64, + 16*92, + 16*127, + 16*183, + 16*257, + 16*369, + 16*531, + 16*750, + 16*1092, + 16*2048, +}; + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + int i, total; + CVI_U32 pregain; + + UNUSED(ViPipe); + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + total = sizeof(gain_table) / sizeof(CVI_U32); + + if (*pu32AgainLin >= gain_table[total- 1]) { + *pu32AgainLin = *pu32AgainDb = gain_table[total - 1]; + return CVI_SUCCESS; + } + + for (i = 1; i < total; i++) { + if (*pu32AgainLin < gain_table[i]) { + break; + } + } + + i--; + pregain = *pu32AgainLin * 256 / gain_table[i]; + + *pu32AgainDb = *pu32AgainLin; + // set the Lin as the closest sensor gain for AE algo reference + if (*pu32AgainLin < 16*92) { + *pu32AgainDb = *pu32AgainLin = 1024; + } else { + *pu32AgainLin = pregain * gain_table[i] / 256; + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + UNUSED(ViPipe); + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + *pu32DgainLin = 1024; + *pu32DgainDb = 0; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + int i, total; + + total = sizeof(gain_table) / sizeof(CVI_U32); + + GC2385_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + if (pu32Again[0] < gain_table[total - 1]) { + for (i = 1; i < total; i++) { + if (*pu32Again < gain_table[i]) + break; + } + + i--; + // find the pregain + u32Again = pu32Again[0] * 256 / gain_table[i]; + + pstSnsRegsInfo->astI2cData[LINEAR_T_INIT_SET].u32Data = regValTable[i][0]; + pstSnsRegsInfo->astI2cData[LINEAR_T_CLK_HS].u32Data = regValTable[i][1]; + pstSnsRegsInfo->astI2cData[LINEAR_COL_CODE].u32Data = regValTable[i][2]; + pstSnsRegsInfo->astI2cData[LINEAR_AUTO_PREGAIN_SYNC].u32Data = u32Again >> 8; + pstSnsRegsInfo->astI2cData[LINEAR_AUTO_PREGAIN].u32Data = u32Again & 0xff; + } else { + u32Again = pu32Again[0] * 256 / gain_table[total - 1]; + i = total - 1; + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio, + CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime) +{ + UNUSED(ViPipe); + UNUSED(u16ManRatioEnable); + UNUSED(au32Ratio); + UNUSED(au32IntTimeMax); + UNUSED(au32IntTimeMin); + UNUSED(pu32LFMaxIntTime); + + return CVI_SUCCESS; +} + +/* Only used in LINE_WDR mode */ +static CVI_S32 cmos_ae_fswdr_attr_set(VI_PIPE ViPipe, AE_FSWDR_ATTR_S *pstAeFSWDRAttr) +{ + CMOS_CHECK_POINTER(pstAeFSWDRAttr); + + genFSWDRMode[ViPipe] = pstAeFSWDRAttr->enFSWDRMode; + gu32MaxTimeGetCnt[ViPipe] = 0; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + CMOS_CHECK_POINTER(pstAwbSnsDft); + UNUSED(ViPipe); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + UNUSED(ViPipe); + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + CMOS_CHECK_POINTER(pstBlc); + UNUSED(ViPipe); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const GC2385_1L_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC2385_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_stGc2385_1L_mode; + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->stImg, sizeof(ISP_WDR_SIZE_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC2385_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = GC2385_1L_MODE_1600X1200P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_stGc2385_1L_mode.u32VtsDef; + syslog(LOG_INFO, "WDR_MODE_NONE\n"); + break; + + case WDR_MODE_2To1_LINE: + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + GC2385_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunGc2385_1L_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = gc2385_1l_i2c_addr; + pstI2c_data[i].u32AddrByteNum = gc2385_1l_addr_byte; + pstI2c_data[i].u32DataByteNum = gc2385_1l_data_byte; + } + + pstI2c_data[LINEAR_EXP_PAGE].u32RegAddr = GC2385_1L_EXP_PAGE_ADDR; + pstI2c_data[LINEAR_EXP_PAGE].u32Data = 0; + pstI2c_data[LINEAR_EXP_H].u32RegAddr = GC2385_1L_EXP_H_ADDR; + pstI2c_data[LINEAR_EXP_L].u32RegAddr = GC2385_1L_EXP_L_ADDR; + pstI2c_data[LINEAR_VB_PAGE].u32RegAddr = GC2385_1L_VB_PAGE_ADDR; + pstI2c_data[LINEAR_VB_PAGE].u32Data = 0; + pstI2c_data[LINEAR_VB_H].u32RegAddr = GC2385_1L_VB_H_ADDR; + pstI2c_data[LINEAR_VB_L].u32RegAddr = GC2385_1L_VB_L_ADDR; + pstI2c_data[LINEAR_FLIP_MIRROR_PAGE].u32RegAddr = GC2385_1L_FLIP_MIRROR_PAGE_ADDR; + pstI2c_data[LINEAR_FLIP_MIRROR_PAGE].u32Data = 0; + pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = GC2385_1L_FLIP_MIRROR_ADDR; + pstI2c_data[LINEAR_FLIP_MIRROR].u32Data = 0xd4; + pstI2c_data[LINEAR_CROP_START_X].u32RegAddr = GC2385_1L_CROP_START_X_ADDR; + pstI2c_data[LINEAR_CROP_START_X].u32Data = 0x05; + pstI2c_data[LINEAR_CROP_START_Y].u32RegAddr = GC2385_1L_CROP_START_Y_ADDR; + pstI2c_data[LINEAR_CROP_START_Y].u32Data = 0x03; + pstI2c_data[LINEAR_BLK_Select1_H].u32RegAddr = GC2385_1L_BLK_SELECT1_H_ADDR; + pstI2c_data[LINEAR_BLK_Select1_H].u32Data = 0x3c; + pstI2c_data[LINEAR_BLK_Select1_L].u32RegAddr = GC2385_1L_BLK_SELECT1_L_ADDR; + pstI2c_data[LINEAR_BLK_Select1_L].u32Data = 0x00; + pstI2c_data[LINEAR_GAIN_PAGE].u32RegAddr = GC2385_1L_AGAIN_PAGE_ADDR; + pstI2c_data[LINEAR_GAIN_PAGE].u32Data = 0; + pstI2c_data[LINEAR_T_INIT_SET].u32RegAddr = GC2385_1L_T_INIT_SET_ADDR; + pstI2c_data[LINEAR_T_INIT_SET].u32Data = 0x73; + pstI2c_data[LINEAR_T_CLK_HS].u32RegAddr = GC2385_1L_T_CLK_HS_ADDR; + pstI2c_data[LINEAR_T_CLK_HS].u32Data = 0xa2; + pstI2c_data[LINEAR_COL_CODE].u32RegAddr = GC2385_1L_COL_CODE_ADDR; + pstI2c_data[LINEAR_COL_CODE].u32Data = 0x00; + pstI2c_data[LINEAR_AUTO_PREGAIN_SYNC].u32RegAddr = GC2385_1L_AUTO_PREGAIN_SYNC_ADDR; + pstI2c_data[LINEAR_AUTO_PREGAIN_SYNC].u32Data = 0x01; + pstI2c_data[LINEAR_AUTO_PREGAIN].u32RegAddr = GC2385_1L_AUTO_PREGAIN_ADDR; + pstI2c_data[LINEAR_AUTO_PREGAIN].u32Data = 0x00; + + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + + CVI_U32 gainsUpdate = 0, expUpdate = 0, vbUpdate = 0; + + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + + if ((i >= LINEAR_T_INIT_SET) && (i <= LINEAR_AUTO_PREGAIN)) + gainsUpdate = 1; + + if ((i >= LINEAR_EXP_H) && (i <= LINEAR_EXP_L)) + expUpdate = 1; + + if ((i >= LINEAR_VB_H) && (i <= LINEAR_VB_L)) + vbUpdate = 1; + + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + + if (gainsUpdate) { + pstCfg0->snsCfg.astI2cData[LINEAR_GAIN_PAGE].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_T_INIT_SET].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_T_CLK_HS].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_COL_CODE].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_AUTO_PREGAIN_SYNC].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_AUTO_PREGAIN].bUpdate = CVI_TRUE; + + } + if (expUpdate) { + pstCfg0->snsCfg.astI2cData[LINEAR_EXP_PAGE].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_EXP_H].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_EXP_L].bUpdate = CVI_TRUE; + } + if (vbUpdate) { + pstCfg0->snsCfg.astI2cData[LINEAR_VB_PAGE].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_VB_H].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_VB_L].bUpdate = CVI_TRUE; + } + if (pstI2c_data[LINEAR_FLIP_MIRROR].bUpdate == CVI_TRUE) { + pstI2c_data[LINEAR_FLIP_MIRROR_PAGE].bUpdate = CVI_TRUE; + } + + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + pstCfg0->ispCfg.u8DelayFrmNum = 1; + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + GC2385_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (GC2385_1L_RES_IS_1200P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) + u8SensorImageMode = GC2385_1L_MODE_1600X1200P30; + else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps); + return CVI_FAILURE; + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 value, start_x, start_y, blk_h, blk_l; + + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + GC2385_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + /* Apply the setting on the fly */ + if (pstSnsState->bInit == CVI_TRUE && g_aeGc2385_1L_MirrorFip[ViPipe] != eSnsMirrorFlip) { + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + value = 0xd4; + start_x = 0x05; + start_y = 0x03; + blk_h = 0x3c; + blk_l = 0x00; + break; + case ISP_SNS_MIRROR: + value = 0xd5; + start_x = 0x06; + start_y = 0x03; + blk_h = 0x3c; + blk_l = 0x00; + break; + case ISP_SNS_FLIP: + value = 0xd6; + start_x = 0x05; + start_y = 0x02; + blk_h = 0x00; + blk_l = 0x3c; + break; + case ISP_SNS_MIRROR_FLIP: + value = 0xd7; + start_x = 0x06; + start_y = 0x02; + blk_h = 0x00; + blk_l = 0x3c; + break; + default: + return; + } + + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value; + pstSnsRegsInfo->astI2cData[LINEAR_CROP_START_X].u32Data = start_x; + pstSnsRegsInfo->astI2cData[LINEAR_CROP_START_Y].u32Data = start_y; + pstSnsRegsInfo->astI2cData[LINEAR_BLK_Select1_H].u32Data = blk_h; + pstSnsRegsInfo->astI2cData[LINEAR_BLK_Select1_L].u32Data = blk_l; + + g_aeGc2385_1L_MirrorFip[ViPipe] = eSnsMirrorFlip; + } +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC2385_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = GC2385_1L_MODE_1600X1200P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_stGc2385_1L_mode.u32VtsDef; + pstSnsState->au32FL[0] = g_stGc2385_1L_mode.u32VtsDef; + pstSnsState->au32FL[1] = g_stGc2385_1L_mode.u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC2385_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &gc2385_1l_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_stGc2385_1L_mode.stImg.stSnsSize.u32Width; + pstRxAttr->img_size.height = g_stGc2385_1L_mode.stImg.stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc2385_1l_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->MipiDev >= VI_MAX_DEV_NUM) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = gc2385_1l_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = gc2385_1l_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 gc2385_1l_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunGc2385_1L_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + GC2385_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + GC2385_1L_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + GC2385_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + GC2385_1L_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = GC2385_1L_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC2385_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, GC2385_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, GC2385_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16Gc2385_1L_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16Gc2385_1L_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_probe(VI_PIPE ViPipe) +{ + return gc2385_1l_probe(ViPipe); +} + +ISP_SNS_OBJ_S stSnsGc2385_1L_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = gc2385_1l_standby, + .pfnRestart = gc2385_1l_restart, + .pfnWriteReg = gc2385_1l_write_register, + .pfnReadReg = gc2385_1l_read_register, + .pfnSetBusInfo = gc2385_1l_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sensor_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos_ex.h b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos_ex.h new file mode 100644 index 000000000..f17066280 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos_ex.h @@ -0,0 +1,95 @@ +#ifndef __GC2385_1L_CMOS_EX_H_ +#define __GC2385_1L_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +#ifndef UNUSED +#define UNUSED(x) ((void)(x)) +#endif + +enum gc2385_1l_linear_regs_e { + LINEAR_EXP_PAGE = 0, + LINEAR_EXP_H, + LINEAR_EXP_L, + LINEAR_VB_PAGE, + LINEAR_VB_H, + LINEAR_VB_L, + LINEAR_FLIP_MIRROR_PAGE, + LINEAR_FLIP_MIRROR, + LINEAR_CROP_START_X, + LINEAR_CROP_START_Y, + LINEAR_BLK_Select1_H, + LINEAR_BLK_Select1_L, + LINEAR_GAIN_PAGE, + LINEAR_T_INIT_SET, + LINEAR_T_CLK_HS, + LINEAR_COL_CODE, + LINEAR_AUTO_PREGAIN_SYNC, + LINEAR_AUTO_PREGAIN, + LINEAR_REGS_NUM +}; + + +typedef enum _GC2385_1L_MODE_E { + GC2385_1L_MODE_1600X1200P30 = 0, + GC2385_1L_MODE_NUM +} GC2385_1L_MODE_E; + +typedef struct _GC2385_1L_STATE_S { + CVI_U32 u32Sexp_MAX; +} GC2385_1L_STATE_S; + +typedef struct _GC2385_1L_MODE_S { + ISP_WDR_SIZE_S stImg; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp; + SNS_ATTR_LARGE_S stAgain; + SNS_ATTR_LARGE_S stDgain; + char name[64]; +} GC2385_1L_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastGc2385_1L[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunGc2385_1L_BusInfo[]; +extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc2385_1L_MirrorFip[VI_MAX_PIPE_NUM]; +extern const CVI_U8 gc2385_1l_i2c_addr; +extern const CVI_U32 gc2385_1l_addr_byte; +extern const CVI_U32 gc2385_1l_data_byte; +extern void gc2385_1l_init(VI_PIPE ViPipe); +extern void gc2385_1l_exit(VI_PIPE ViPipe); +extern void gc2385_1l_standby(VI_PIPE ViPipe); +extern void gc2385_1l_restart(VI_PIPE ViPipe); +extern int gc2385_1l_write_register(VI_PIPE ViPipe, int addr, int data); +extern int gc2385_1l_read_register(VI_PIPE ViPipe, int addr); +extern int gc2385_1l_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __GC2385_1L_CMOS_EX_H_ */ + diff --git a/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos_param.h b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos_param.h new file mode 100644 index 000000000..ee69ee7a5 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_cmos_param.h @@ -0,0 +1,125 @@ +#ifndef __GC2385_1L_CMOS_PARAM_H_ +#define __GC2385_1L_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "gc2385_1l_cmos_ex.h" + +static const GC2385_1L_MODE_S g_stGc2385_1L_mode = { + .name = "1600X1200P30", + .stImg = { + .stSnsSize = { + .u32Width = 1600, + .u32Height = 1200, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1600, + .u32Height = 1200, + }, + .stMaxSize = { + .u32Width = 1600, + .u32Height = 1200, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 2.285, /* 1248*30/3fff */ + .u32HtsDef = 2157, + .u32VtsDef = 1248, + .stExp = { + .u16Min = 1, + .u16Max = 1248 - 1, /* VtsDef - 1*/ + .u16Def = 100, + .u16Step = 1, + }, + .stAgain = { + .u32Min = 1024, + .u32Max = 16 * 2048, + .u32Def = 1024, + .u32Step = 1, + }, + .stDgain = { + .u32Min = 1024, + .u32Max = 1024, + .u32Def = 1024, + .u32Step = 1, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {256, 256, 256, 256, 0, 0, 0, 0 +#ifdef ARCH_CV182X + , 1092, 1092, 1092, 1092 +#endif + }, + .stAuto = { + {256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1092, 1092, 1093, 1093, 1093, 1093, 1093, 1095, + 1099, 1104, 1125, 1130, 1125, 1127, 1126, 1126}, + {1092, 1092, 1093, 1093, 1093, 1093, 1094, 1095, + 1097, 1104, 1128, 1128, 1126, 1124, 1127, 1127}, + {1092, 1092, 1093, 1093, 1093, 1093, 1094, 1095, + 1098, 1104, 1128, 1131, 1125, 1127, 1128, 1126}, + {1092, 1092, 1093, 1093, 1093, 1093, 1093, 1095, + 1097, 1103, 1123, 1124, 1124, 1123, 1121, 1125}, +#endif + }, + }, +}; + +struct combo_dev_attr_s gc2385_1l_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_400M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {2, 0, -1, -1, -1}, + .pn_swap = {1, 1, 0, 0, 0}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + .dphy = { + .enable = 1, + .hs_settle = 8, + }, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_24M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __GC2385_1L_CMOS_PARAM_H_ */ + diff --git a/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_sensor_ctl.c new file mode 100644 index 000000000..ecd864cd9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/gcore_gc2385_1L/gc2385_1l_sensor_ctl.c @@ -0,0 +1,319 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "gc2385_1l_cmos_ex.h" + +#define GC2385_1L_CHIP_ID_ADDR_H 0xf0 +#define GC2385_1L_CHIP_ID_ADDR_L 0xf1 +#define GC2385_1L_CHIP_ID 0x2385 + +static void gc2385_1l_linear_1200p30_init(VI_PIPE ViPipe); + +const CVI_U8 gc2385_1l_i2c_addr = 0x37; +const CVI_U32 gc2385_1l_addr_byte = 1; +const CVI_U32 gc2385_1l_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int gc2385_1l_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunGc2385_1L_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc2385_1l_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + return CVI_SUCCESS; +} + +int gc2385_1l_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int gc2385_1l_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (gc2385_1l_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, gc2385_1l_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, gc2385_1l_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (gc2385_1l_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int gc2385_1l_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (gc2385_1l_addr_byte == 1) { + buf[idx] = addr & 0xff; + idx++; + } + if (gc2385_1l_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, gc2385_1l_addr_byte + gc2385_1l_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + //ret = read(g_fd[ViPipe], buf, gc2385_1l_addr_byte + gc2385_1l_data_byte); + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void gc2385_1l_standby(VI_PIPE ViPipe) +{ + UNUSED(ViPipe); + printf("gc2385_1l_standby\n"); +} + +void gc2385_1l_restart(VI_PIPE ViPipe) +{ + UNUSED(ViPipe); + printf("gc2385_1l_restart\n"); +} + +void gc2385_1l_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastGc2385_1L[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + gc2385_1l_write_register(ViPipe, + g_pastGc2385_1L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastGc2385_1L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +int gc2385_1l_probe(VI_PIPE ViPipe) +{ + int nVal; + int nVal2; + + usleep(50); + if (gc2385_1l_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = gc2385_1l_read_register(ViPipe, GC2385_1L_CHIP_ID_ADDR_H); + nVal2 = gc2385_1l_read_register(ViPipe, GC2385_1L_CHIP_ID_ADDR_L); + if (nVal < 0 || nVal2 < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + + if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != GC2385_1L_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + return CVI_SUCCESS; +} + +void gc2385_1l_init(VI_PIPE ViPipe) +{ + WDR_MODE_E enWDRMode = g_pastGc2385_1L[ViPipe]->enWDRMode; + + gc2385_1l_i2c_init(ViPipe); + + if (enWDRMode == WDR_MODE_2To1_LINE) { + CVI_TRACE_SNS(CVI_DBG_ERR, "not surpport this WDR_MODE_E!\n"); + } else { + gc2385_1l_linear_1200p30_init(ViPipe); + } + g_pastGc2385_1L[ViPipe]->bInit = CVI_TRUE; +} + +void gc2385_1l_exit(VI_PIPE ViPipe) +{ + gc2385_1l_i2c_exit(ViPipe); +} + +static void gc2385_1l_linear_1200p30_init(VI_PIPE ViPipe) +{ + /****system****/ + gc2385_1l_write_register(ViPipe, 0xfe,0x00); + gc2385_1l_write_register(ViPipe, 0xfe,0x00); + gc2385_1l_write_register(ViPipe, 0xfe,0x00); + gc2385_1l_write_register(ViPipe, 0xf2,0x02); + gc2385_1l_write_register(ViPipe, 0xf4,0x03); + gc2385_1l_write_register(ViPipe, 0xf7,0x01); + gc2385_1l_write_register(ViPipe, 0xf8,0x28); + gc2385_1l_write_register(ViPipe, 0xf9,0x02); + gc2385_1l_write_register(ViPipe, 0xfa,0x08); + gc2385_1l_write_register(ViPipe, 0xfc,0x8e); + gc2385_1l_write_register(ViPipe, 0xe7,0xcc); + gc2385_1l_write_register(ViPipe, 0x88,0x03); + + /****************************************/ + /*analog*/ + /****************************************/ + gc2385_1l_write_register(ViPipe, 0x03,0x04); + gc2385_1l_write_register(ViPipe, 0x04,0x80); + gc2385_1l_write_register(ViPipe, 0x05,0x02); + gc2385_1l_write_register(ViPipe, 0x06,0x86); + gc2385_1l_write_register(ViPipe, 0x07,0x00); + + gc2385_1l_write_register(ViPipe, 0x08,0x10); + gc2385_1l_write_register(ViPipe, 0x09,0x00); + gc2385_1l_write_register(ViPipe, 0x0a,0x04);//00 + gc2385_1l_write_register(ViPipe, 0x0b,0x00); + gc2385_1l_write_register(ViPipe, 0x0c,0x02);//04 + gc2385_1l_write_register(ViPipe, 0x17,0xd4); + gc2385_1l_write_register(ViPipe, 0x18,0x02); + gc2385_1l_write_register(ViPipe, 0x19,0x17); + gc2385_1l_write_register(ViPipe, 0x1c,0x18);//10 + gc2385_1l_write_register(ViPipe, 0x20,0x73);//71 + gc2385_1l_write_register(ViPipe, 0x21,0x38); + gc2385_1l_write_register(ViPipe, 0x22,0xa2);//a1 + gc2385_1l_write_register(ViPipe, 0x29,0x20); + gc2385_1l_write_register(ViPipe, 0x2f,0x14); + gc2385_1l_write_register(ViPipe, 0x3f,0x40); + gc2385_1l_write_register(ViPipe, 0xcd,0x94); + gc2385_1l_write_register(ViPipe, 0xce,0x45); + gc2385_1l_write_register(ViPipe, 0xd1,0x0c); + gc2385_1l_write_register(ViPipe, 0xd7,0x9b); + gc2385_1l_write_register(ViPipe, 0xd8,0x99); + gc2385_1l_write_register(ViPipe, 0xda,0x3b); + gc2385_1l_write_register(ViPipe, 0xd9,0xb5); + gc2385_1l_write_register(ViPipe, 0xdb,0x75); + gc2385_1l_write_register(ViPipe, 0xe3,0x1b); + gc2385_1l_write_register(ViPipe, 0xe4,0xf8); + /****************************************/ + /*BLk*/ + /****************************************/ + gc2385_1l_write_register(ViPipe, 0x40,0x22); + gc2385_1l_write_register(ViPipe, 0x43,0x07); + gc2385_1l_write_register(ViPipe, 0x4e,0x3c); + gc2385_1l_write_register(ViPipe, 0x4f,0x00); + gc2385_1l_write_register(ViPipe, 0x68,0x00); + /****************************************/ + /*gain*/ + /****************************************/ + gc2385_1l_write_register(ViPipe, 0xb0,0x46); + gc2385_1l_write_register(ViPipe, 0xb1,0x01); + gc2385_1l_write_register(ViPipe, 0xb2,0x00); + gc2385_1l_write_register(ViPipe, 0xb6,0x00); + /****************************************/ + /*out crop*/ + /****************************************/ + gc2385_1l_write_register(ViPipe, 0x90,0x01); + gc2385_1l_write_register(ViPipe, 0x92,0x03); //crop_win_y1 + gc2385_1l_write_register(ViPipe, 0x94,0x05); //crop_win_x1 + gc2385_1l_write_register(ViPipe, 0x95,0x04); + gc2385_1l_write_register(ViPipe, 0x96,0xb0); + gc2385_1l_write_register(ViPipe, 0x97,0x06); + gc2385_1l_write_register(ViPipe, 0x98,0x40); + /****************************************/ + /*mipi set*/ + /****************************************/ + gc2385_1l_write_register(ViPipe, 0xfe,0x00); + gc2385_1l_write_register(ViPipe, 0xed,0x90); + gc2385_1l_write_register(ViPipe, 0xfe,0x03); + gc2385_1l_write_register(ViPipe, 0x01,0x03); + gc2385_1l_write_register(ViPipe, 0x02,0x82); + gc2385_1l_write_register(ViPipe, 0x03,0xd0);//e0->d0 20170223 + gc2385_1l_write_register(ViPipe, 0x04,0x04); + gc2385_1l_write_register(ViPipe, 0x05,0x00); + gc2385_1l_write_register(ViPipe, 0x06,0x80); + gc2385_1l_write_register(ViPipe, 0x11,0x2b); + gc2385_1l_write_register(ViPipe, 0x12,0xd0); + gc2385_1l_write_register(ViPipe, 0x13,0x07); + gc2385_1l_write_register(ViPipe, 0x15,0x00); + gc2385_1l_write_register(ViPipe, 0x1b,0x10); + gc2385_1l_write_register(ViPipe, 0x1c,0x10); + gc2385_1l_write_register(ViPipe, 0x21,0x08); + gc2385_1l_write_register(ViPipe, 0x22,0x05); + gc2385_1l_write_register(ViPipe, 0x23,0x13); + gc2385_1l_write_register(ViPipe, 0x24,0x02); + gc2385_1l_write_register(ViPipe, 0x25,0x13); + gc2385_1l_write_register(ViPipe, 0x26,0x06);//08 + gc2385_1l_write_register(ViPipe, 0x29,0x06); + gc2385_1l_write_register(ViPipe, 0x2a,0x08); + gc2385_1l_write_register(ViPipe, 0x2b,0x06);//08 + gc2385_1l_write_register(ViPipe, 0xfe,0x00); + + gc2385_1l_default_reg_init(ViPipe); + delay_ms(10); + + printf("ViPipe:%d,===GC2385_1L 1200P 30fps 10bit LINEAR Init OK!===\n", ViPipe); +} + diff --git a/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/Makefile b/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/Makefile new file mode 100644 index 000000000..d1f05ca39 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_os02d10.a +TARGET_SO = $(MW_LIB)/libsns_os02d10.so + +EXTRA_CFLAGS = $(INCS) $(PROJ_CFLAGS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $@) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $@) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos.c b/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos.c new file mode 100644 index 000000000..1e2d4f0e3 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos.c @@ -0,0 +1,1149 @@ +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "os02n10_1l_cmos_ex.h" +#include "os02n10_1l_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define OS02N10_1L_ID 0x2309 +#define OS02N10_1L_I2C_ADDR_1 0x3C +#define OS02N10_1L_I2C_ADDR_2 0x3C +#define OS02N10_1L_I2C_ADDR_IS_VALID(addr) ((addr) == OS02N10_1L_I2C_ADDR_1 || (addr) == OS02N10_1L_I2C_ADDR_2) +#define OS02N10_1L_PCLK (84) +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastOs02n10_1l[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define OS02N10_1L_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastOs02n10_1l[dev]) +#define OS02N10_1L_SENSOR_SET_CTX(dev, pstCtx) (g_pastOs02n10_1l[dev] = pstCtx) +#define OS02N10_1L_SENSOR_RESET_CTX(dev) (g_pastOs02n10_1l[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunOs02n10_1l_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16Os02n10_1l_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16Os02n10_1l_UseHwSync[VI_MAX_PIPE_NUM] = {0}; + +OS02N10_1L_STATE_S g_astOs02n10_1l_State[VI_MAX_PIPE_NUM] = {{0} }; +ISP_SNS_MIRRORFLIP_TYPE_E g_aeOs02n10_1l_MirrorFip[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ + +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +/*****Os02n10_1l Lines Range*****/ +#define OS02N10_1L_FULL_LINES_MAX (0xFFFF) + +/*****Os02n10 Register Address*****/ +#define OS02N10_1L_PAGE_SWITCH_ADDR 0xFD +#define OS02N10_1L_TRIGGER_ADDR 0xFE +#define OS02N10_1L_EXP0_ADDR 0x0E +#define OS02N10_1L_AGAIN_ADDR 0x24 +#define OS02N10_1L_DGAIN0_ADDR 0x1F +#define OS02N10_1L_VB0_ADDR 0x14 +#define OS02N10_1L_TABLE_END 0xffff +#define OS02N10_1L_FLIP_MIRROR_ADDR 0x12 + +#define OS02N10_1L_RES_IS_1080P(w, h) ((w) <= 1920 && (h) <= 1080) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + const OS02N10_1L_MODE_S *pstMode; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astOs02n10_1l_mode[pstSnsState->u8ImgMode]; +#if 0 + memset(&pstAeSnsDft->stAERouteAttr, 0, sizeof(ISP_AE_ROUTE_S)); +#endif + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = OS02N10_1L_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; + /* OV sensor cannot update new setting before the old setting takes effect */ + pstAeSnsDft->u8AERunInterval = 4; +#if 0 + pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0; + pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0; + + pstAeSnsDft->bAERouteExValid = CVI_FALSE; + pstAeSnsDft->stAERouteAttr.u32TotalNum = 0; + pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0; +#endif + switch (pstSnsState->enWDRMode) { + default: + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = pstMode->f32MaxFps; + pstAeSnsDft->f32MinFps = pstMode->f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u32Max; + pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u32Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u32Max; + pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u32Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 2; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; + + pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max; + pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX = 0; + CVI_U32 u32VB = 0; + CVI_U32 nVal0, nVal1; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astOs02n10_1l_mode->u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astOs02n10_1l_mode->f32MaxFps; + f32MinFps = g_astOs02n10_1l_mode->f32MinFps; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + + u32VMAX = (u32VMAX > OS02N10_1L_FULL_LINES_MAX) ? OS02N10_1L_FULL_LINES_MAX : u32VMAX; + + nVal0 = os02n10_1l_read_register(ViPipe, OS02N10_1L_VB0_ADDR); + nVal1 = os02n10_1l_read_register(ViPipe, OS02N10_1L_VB0_ADDR + 1); + u32VB = ((nVal0 & 0xFF) << 8 | (nVal1 & 0xFF)) + u32VMAX - u32Vts ; + + pstSnsRegsInfo->astI2cData[LINEAR_VB_0].u32Data = (u32VB >> 8 & 0xFF); + pstSnsRegsInfo->astI2cData[LINEAR_VB_1].u32Data = (u32VB & 0xFF); + } + + pstSnsState->u32FLStd = u32VMAX; + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps /2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 9; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear exposure reg range: + * min : 2 + * max : vts - 9 + * step : 1 + */ + CVI_U32 u32TmpIntTime = u32IntTime[0]; + CVI_U32 mimExp = 2; + CVI_U32 maxExp = pstSnsState->au32FL[0] - 9; + + u32TmpIntTime = (u32TmpIntTime > maxExp) ? maxExp : u32TmpIntTime; + u32TmpIntTime = (u32TmpIntTime < mimExp) ? mimExp : u32TmpIntTime; + u32IntTime[0] = u32TmpIntTime; + + pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = (u32TmpIntTime >> 8 & 0xFF ); + pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = (u32TmpIntTime & 0xFF); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + return CVI_SUCCESS; +} + +typedef struct gain_tbl_info_s { + CVI_U32 gainMax; + CVI_U16 idxBase; + CVI_U8 regGain; + CVI_U8 regGainFineBase; + CVI_U8 regGainFineStep; +} gain_tbl_info_s; + +static struct gain_tbl_info_s AgainInfo[4] = { + { + .gainMax = 1984, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x10, + .regGainFineStep = 0x1, + }, + { + .gainMax = 3968, + .idxBase = 16, + .regGain = 0x00, + .regGainFineBase = 0x20, + .regGainFineStep = 0x2, + }, + { + .gainMax = 7936, + .idxBase = 32, + .regGain = 0x00, + .regGainFineBase = 0x40, + .regGainFineStep = 0x4, + }, + { + .gainMax = 15872, + .idxBase = 48, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 0x8, + }, +}; + +/* + * regGainFineBase {P1:0x24} + * AGain + * 0x10~0xF8 1x-15.5x + */ +static CVI_U32 Again_table[] = { + 1024, 1088, 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664, 1728, 1792, 1856, 1920, + 1984, 2048, 2176, 2304, 2432, 2560, 2688, 2816, 2944, 3072, 3200, 3328, 3456, 3584, 3712, + 3840, 3968, 4096, 4352, 4608, 4864, 5120, 5376, 5632, 5888, 6144, 6400, 6656, 6912, 7168, + 7424, 7680, 7936, 8192, 8704, 9216, 9728, 10240, 10752, 11264, 11776, 12288, 12800, 13312, + 13824, 14336, 14848, 15360, 15872 +}; + +static struct gain_tbl_info_s DgainInfo[9] = { + { + .gainMax = 2048, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x40, + .regGainFineStep = 1, + }, + { + .gainMax = 4064, + .idxBase = 65, + .regGain = 0x00, + .regGainFineBase = 0x82, + .regGainFineStep = 0x02, + }, + { + .gainMax = 6144, + .idxBase = 128, + .regGain = 0x01, + .regGainFineBase = 0x00, + .regGainFineStep = 0x80, + }, + { + .gainMax = 10240, + .idxBase = 130, + .regGain = 0x02, + .regGainFineBase = 0x00, + .regGainFineStep = 0x80, + }, + { + .gainMax = 14336, + .idxBase = 132, + .regGain = 0x03, + .regGainFineBase = 0x00, + .regGainFineStep = 0x80, + }, + { + .gainMax = 18432, + .idxBase = 134, + .regGain = 0x04, + .regGainFineBase = 0x00, + .regGainFineStep = 0x80, + }, + { + .gainMax = 22528, + .idxBase = 136, + .regGain = 0x05, + .regGainFineBase = 0x00, + .regGainFineStep = 0x80, + }, + { + .gainMax = 26624, + .idxBase = 138, + .regGain = 0x06, + .regGainFineBase = 0x00, + .regGainFineStep = 0x80, + }, + { + .gainMax = 32768, + .idxBase = 140, + .regGain = 0x07, + .regGainFineBase = 0x00, + .regGainFineStep = 0x80, + }, +}; + +/* + * GainReg {P1:0x1F P1:0x20} + * DGain + * 1x: 0x1F=0x00;0x20=0x40 + * 32x:0x1F=0x07;0x20=0xFF + * minmum step is 1/64 + */ +static CVI_U32 Dgain_table[] = { + 1024, 1040, 1056, 1072, 1088, 1104, 1120, 1136, 1152, 1168, 1184, 1200, 1216, 1232, 1248, + 1264, 1280, 1296, 1312, 1328, 1344, 1360, 1376, 1392, 1408, 1424, 1440, 1456, 1472, 1488, + 1504, 1520, 1536, 1552, 1568, 1584, 1600, 1616, 1632, 1648, 1664, 1680, 1696, 1712, 1728, + 1744, 1760, 1776, 1792, 1808, 1824, 1840, 1856, 1872, 1888, 1904, 1920, 1936, 1952, 1968, + 1984, 2000, 2016, 2032, 2048, 2080, 2112, 2144, 2176, 2208, 2240, 2272, 2304, 2336, 2368, + 2400, 2432, 2464, 2496, 2528, 2560, 2592, 2624, 2656, 2688, 2720, 2752, 2784, 2816, 2848, + 2880, 2912, 2944, 2976, 3008, 3040, 3072, 3104, 3136, 3168, 3200, 3232, 3264, 3296, 3328, + 3360, 3392, 3424, 3456, 3488, 3520, 3552, 3584, 3616, 3648, 3680, 3712, 3744, 3776, 3808, + 3840, 3872, 3904, 3936, 3968, 4000, 4032, 4064, 4096, 6144, 8192, 10240, 12288, 14336, 16384, + 18432, 20480, 22528, 24576, 26624, 28672, 30720, 32768, +}; + +static const CVI_U32 again_table_size = ARRAY_SIZE(Again_table); +static const CVI_U32 dgain_table_size = ARRAY_SIZE(Dgain_table); + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + CVI_U32 i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (*pu32AgainLin >= Again_table[again_table_size - 1]) { + *pu32AgainLin = Again_table[again_table_size - 1]; + *pu32AgainDb = again_table_size - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < again_table_size; i++) { + if (*pu32AgainLin < Again_table[i]) { + *pu32AgainLin = Again_table[i - 1]; + *pu32AgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + CVI_U32 i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= Dgain_table[dgain_table_size - 1]) { + *pu32DgainLin = Dgain_table[dgain_table_size - 1]; + *pu32DgainDb = dgain_table_size - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < dgain_table_size; i++) { + if (*pu32DgainLin < Dgain_table[i]) { + *pu32DgainLin = Dgain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + struct gain_tbl_info_s *info; + int i, tbl_num; + + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear mode */ + + /* find Again register setting. */ + tbl_num = sizeof(AgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &AgainInfo[i]; + + if (u32Again >= info->idxBase) + break; + } + + u32Again = info->regGainFineBase + (u32Again - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN].u32Data = u32Again & 0xFF; + + /* find Dgain register setting. */ + tbl_num = sizeof(DgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &DgainInfo[i]; + + if (u32Dgain >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_0].u32Data = (info->regGain & 0xFF); + u32Dgain = info->regGainFineBase + (u32Dgain - info->idxBase) * info->regGainFineStep; + u32Dgain = (u32Dgain > 0xff) ? 0xff : u32Dgain; + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_1].u32Data = u32Dgain & 0xFF; + } + return CVI_SUCCESS; +} + + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + // pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + // pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const OS02N10_1L_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astOs02n10_1l_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode != WDR_MODE_NONE) { + pstIspCfg->frm_num = 2; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S)); + } else { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = OS02N10_1L_MODE_1080P15; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astOs02n10_1l_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "WDR_MODE_NONE\n"); + break; + + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunOs02n10_1l_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = os02n10_1l_i2c_addr; + pstI2c_data[i].u32AddrByteNum = os02n10_1l_addr_byte; + pstI2c_data[i].u32DataByteNum = os02n10_1l_data_byte; + } + + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: + // switch page 1 + pstI2c_data[LINEAR_PAGE_SWITCH].u32RegAddr = OS02N10_1L_PAGE_SWITCH_ADDR; + pstI2c_data[LINEAR_PAGE_SWITCH].u32Data = 0x01; + pstI2c_data[LINEAR_EXP_0].u32RegAddr = OS02N10_1L_EXP0_ADDR; + pstI2c_data[LINEAR_EXP_1].u32RegAddr = OS02N10_1L_EXP0_ADDR + 1; + pstI2c_data[LINEAR_EXP_TRIGGER].u32RegAddr = OS02N10_1L_TRIGGER_ADDR; + pstI2c_data[LINEAR_EXP_TRIGGER].u32Data = 0x02; + + pstI2c_data[LINEAR_AGAIN].u32RegAddr = OS02N10_1L_AGAIN_ADDR; + pstI2c_data[LINEAR_DGAIN_0].u32RegAddr = OS02N10_1L_DGAIN0_ADDR; + pstI2c_data[LINEAR_DGAIN_1].u32RegAddr = OS02N10_1L_DGAIN0_ADDR + 1; + pstI2c_data[LINEAR_GAIN_TRIGGER].u32RegAddr = OS02N10_1L_TRIGGER_ADDR; + pstI2c_data[LINEAR_GAIN_TRIGGER].u32Data = 0x02; + + pstI2c_data[LINEAR_VB_0].u32RegAddr = OS02N10_1L_VB0_ADDR; + pstI2c_data[LINEAR_VB_1].u32RegAddr = OS02N10_1L_VB0_ADDR + 1; + pstI2c_data[LINEAR_VB_1].u32Data = 0x90; + pstI2c_data[LINEAR_VB_TRIGGER].u32RegAddr = OS02N10_1L_TRIGGER_ADDR; + pstI2c_data[LINEAR_VB_TRIGGER].u32Data = 0x02; + + pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = OS02N10_1L_FLIP_MIRROR_ADDR; + + break; + default: + break; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + + CVI_U32 gainsUpdate = 0; + CVI_U32 vtsUpdate = 0; + CVI_U32 shutterUpdate = 0; + CVI_U32 flipmirrorUpdate = 0; + + + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + if ((i >= LINEAR_AGAIN) && (i <= LINEAR_GAIN_TRIGGER)) + gainsUpdate = 1; + if ((i >= LINEAR_VB_0) && (i <= LINEAR_VB_TRIGGER)) + vtsUpdate = 1; + if ((i >= LINEAR_EXP_0 ) && (i <= LINEAR_EXP_TRIGGER)) + shutterUpdate = 1; + if ((i == LINEAR_FLIP_MIRROR )) + flipmirrorUpdate = 1; + + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + if (gainsUpdate) { + pstCfg0->snsCfg.astI2cData[LINEAR_PAGE_SWITCH].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_0].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_1].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_GAIN_TRIGGER].bUpdate = CVI_TRUE; + } + if (shutterUpdate) { + pstCfg0->snsCfg.astI2cData[LINEAR_PAGE_SWITCH].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_EXP_0].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_EXP_1].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_EXP_TRIGGER].bUpdate = CVI_TRUE; + } + if (vtsUpdate) { + pstCfg0->snsCfg.astI2cData[LINEAR_PAGE_SWITCH].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_VB_0].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_VB_1].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_VB_TRIGGER].bUpdate = CVI_TRUE; + } + + if (flipmirrorUpdate) { + pstCfg0->snsCfg.astI2cData[LINEAR_PAGE_SWITCH].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bUpdate = CVI_TRUE; + } + + + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (OS02N10_1L_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = OS02N10_1L_MODE_1080P15; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_ISP_INFO_S *pstIspCfg0 = CVI_NULL; + + CVI_U8 value, value0, value1, value2, col_offset, row_offset_0, row_offset_1, start_x, start_y; + + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + pstIspCfg0 = &pstSnsState->astSyncInfo[0].ispCfg; + + if (pstSnsState->bInit == CVI_TRUE && g_aeOs02n10_1l_MirrorFip[ViPipe] != eSnsMirrorFlip) { + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + value = 0x00; + value0 = 0x10; + value1 = 0xe2; + value2 = 0x50; + col_offset = 0x00; + row_offset_0 = 0x00; + row_offset_1 = 0x00; + start_x = 4; + start_y = 4; + break; + case ISP_SNS_MIRROR: + value = 0x02; + value0 = 0x10; + value1 = 0xe2; + value2 = 0x5c; + col_offset = 0xc3; + row_offset_0 = 0x00; + row_offset_1 = 0x00; + start_x = 5; + start_y = 4; + break; + case ISP_SNS_FLIP: + value = 0x01; + value0 = 0x10; + value1 = 0xe2; + value2 = 0x50; + col_offset = 0x00; + row_offset_0 = 0x3f; + row_offset_1 = 0x04; + start_x = 5; + start_y = 5; + break; + case ISP_SNS_MIRROR_FLIP: + value = 0x03; + value0 = 0x10; + value1 = 0xe2; + value2 = 0x5c; + col_offset = 0x00; + row_offset_0 = 0x3f; + row_offset_1 = 0x04; + start_x = 4; + start_y = 5; + break; + default: + return; + } + + os02n10_1l_write_register(ViPipe, 0xfd, 0x03); + os02n10_1l_write_register(ViPipe, 0x46, value0); + os02n10_1l_write_register(ViPipe, 0x47, value1); + os02n10_1l_write_register(ViPipe, 0x45, value2); + os02n10_1l_write_register(ViPipe, 0x48, col_offset); + os02n10_1l_write_register(ViPipe, 0x49, row_offset_0); + os02n10_1l_write_register(ViPipe, 0x4A, row_offset_1); + + pstSnsRegsInfo->astI2cData[LINEAR_PAGE_SWITCH].u32Data = 0x01; + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data =value; + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1; + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2; + + g_aeOs02n10_1l_MirrorFip[ViPipe] = eSnsMirrorFlip; + pstIspCfg0->img_size[0].stWndRect.s32X = start_x; + pstIspCfg0->img_size[0].stWndRect.s32Y = start_y; + } +} + + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = OS02N10_1L_MODE_1080P15; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astOs02n10_1l_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsState->au32FL[0] = g_astOs02n10_1l_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsState->au32FL[1] = g_astOs02n10_1l_mode[pstSnsState->u8ImgMode].u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &os02n10_1l_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astOs02n10_1l_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astOs02n10_1l_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + else + pstRxAttr->mac_clk = RX_MAC_CLK_400M; + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &os02n10_1l_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= VI_MAX_DEV_NUM) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = os02n10_1l_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = os02n10_1l_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (OS02N10_1L_I2C_ADDR_IS_VALID(s32I2cAddr)) + os02n10_1l_i2c_addr = s32I2cAddr; +} + +static CVI_S32 os02n10_1l_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunOs02n10_1l_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + OS02N10_1L_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + OS02N10_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + OS02N10_1L_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = OS02N10_1L_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, OS02N10_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, OS02N10_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, OS02N10_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16Os02n10_1l_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16Os02n10_1l_UseHwSync[ViPipe] = pstInitAttr->u16UseHwSync; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_probe(VI_PIPE ViPipe) +{ + return os02n10_1l_probe(ViPipe); +} + +ISP_SNS_OBJ_S stSnsOs02n10_1l_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = os02n10_1l_standby, + .pfnRestart = os02n10_1l_restart, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnWriteReg = os02n10_1l_write_register, + .pfnReadReg = os02n10_1l_read_register, + .pfnSetBusInfo = os02n10_1l_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sensor_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos_ex.h b/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos_ex.h new file mode 100644 index 000000000..c817b354d --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos_ex.h @@ -0,0 +1,93 @@ +#ifndef __OS02N10_1L_CMOS_EX_H_ +#define __OS02N10_1L_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +#ifndef UNUSED +#define UNUSED(x) ((void)(x)) +#endif + +enum os02n10_1l_linear_regs_e { + LINEAR_PAGE_SWITCH, + LINEAR_EXP_0, + LINEAR_EXP_1, + LINEAR_EXP_TRIGGER, + LINEAR_AGAIN, + LINEAR_DGAIN_0, + LINEAR_DGAIN_1, + LINEAR_GAIN_TRIGGER, + LINEAR_VB_0, + LINEAR_VB_1, + LINEAR_VB_TRIGGER, + LINEAR_FLIP_MIRROR, + LINEAR_REGS_NUM +}; + +typedef enum _OS02N10_1L_MODE_E { + OS02N10_1L_MODE_1080P15= 0, + OS02N10_1L_MODE_LINEAR_NUM, + OS02N10_1L_MODE_NUM +} OS02N10_1L_MODE_E; + +typedef struct _OS02N10_1L_STATE_S { + CVI_U32 u32Sexp_MAX; +} OS02N10_1L_STATE_S; + +typedef struct _OS02N10_1L_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_LARGE_S stAgain[2]; + SNS_ATTR_LARGE_S stDgain[2]; + char name[64]; + CVI_U32 u32L2S_offset; + CVI_U32 u32IspResTime; + CVI_U32 u32VStart; + CVI_U32 u32VEnd; +} OS02N10_1L_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastOs02n10_1l[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunOs02n10_1l_BusInfo[]; +extern CVI_U16 g_au16Os02n10_1l_GainMode[]; +extern CVI_U16 g_au16Os02n10_1l_UseHwSync[VI_MAX_PIPE_NUM]; +extern CVI_U8 os02n10_1l_i2c_addr; +extern const CVI_U32 os02n10_1l_addr_byte; +extern const CVI_U32 os02n10_1l_data_byte; +extern void os02n10_1l_init(VI_PIPE ViPipe); +extern void os02n10_1l_exit(VI_PIPE ViPipe); +extern void os02n10_1l_standby(VI_PIPE ViPipe); +extern void os02n10_1l_restart(VI_PIPE ViPipe); +extern int os02n10_1l_write_register(VI_PIPE ViPipe, int addr, int data); +extern int os02n10_1l_read_register(VI_PIPE ViPipe, int addr); +extern int os02n10_1l_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __OS02N10_1L_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos_param.h b/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos_param.h new file mode 100644 index 000000000..111f9def0 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_cmos_param.h @@ -0,0 +1,126 @@ +#ifndef __OS02N10_1L_CMOS_PARAM_H_ +#define __OS02N10_1L_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "os02n10_1l_cmos_ex.h" + +static const OS02N10_1L_MODE_S g_astOs02n10_1l_mode[OS02N10_1L_MODE_NUM] = { + [OS02N10_1L_MODE_1080P15] = { + .name = "1080P15", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1928, + .u32Height = 1088, + }, + .stWndRect = { + .s32X = 4, + .s32Y = 4, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1928, + .u32Height = 1088, + }, + }, + .f32MaxFps = 15, + .f32MinFps = 0.508, /* 1109 * 30 / 0xFFFF = 0.508 */ + .u32HtsDef = 272, + .u32VtsDef = 1109, + .stExp[0] = { + .u16Min = 2, + .u16Max = 1109 - 9, + .u16Def = 500, + .u16Step = 1, + }, + .stAgain[0] = { + .u32Min = 1024, + .u32Max = 15872, + .u32Def = 1024, + .u32Step = 1, + }, + .stDgain[0] = { + .u32Min = 1024, + .u32Max = 32768, + .u32Def = 1024, + .u32Step = 1, + }, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = { 256, 256, 256, 256, 0, 0, 0, 0 +#ifdef ARCH_CV182X + , 1057, 1057, 1057, 1057 +#endif + }, + .stAuto = { + {256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057, + /*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057}, + {1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057, + /*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057}, + {1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057, + /*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057}, + {1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057, + /*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057}, +#endif + }, + }, +}; + +struct combo_dev_attr_s os02n10_1l_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_400M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {3, 2, -1, -1, -1}, + .pn_swap = {0, 0, 0, 0, 0}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + .dphy = { + .enable = 1, + .hs_settle = 8, + }, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_25M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __OS02N10_1L_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_sensor_ctl.c new file mode 100644 index 000000000..4e58af225 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/ov_os02n10_1L/os02n10_1l_sensor_ctl.c @@ -0,0 +1,414 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "os02n10_1l_cmos_ex.h" + +static void os02n10_1l_linear_1080p15_init(VI_PIPE ViPipe); + +CVI_U8 os02n10_1l_i2c_addr = 0x3c; /* I2C Address of OS02N10_1L */ +const CVI_U32 os02n10_1l_addr_byte = 1; +const CVI_U32 os02n10_1l_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; +ISP_SNS_MIRRORFLIP_TYPE_E g_aeOs02n10_1l_MirrorFip_Initial[VI_MAX_PIPE_NUM] = { + ISP_SNS_MIRROR, ISP_SNS_MIRROR, ISP_SNS_MIRROR, ISP_SNS_MIRROR}; + +int os02n10_1l_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunOs02n10_1l_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, os02n10_1l_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + return CVI_SUCCESS; +} + +int os02n10_1l_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int os02n10_1l_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (os02n10_1l_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, os02n10_1l_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return 0; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, os02n10_1l_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return 0; + } + + // pack read back data + data = 0; + if (os02n10_1l_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int os02n10_1l_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (os02n10_1l_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + } + buf[idx] = addr & 0xff; + idx++; + + if (os02n10_1l_data_byte == 2) { + buf[idx] = (data >> 8) & 0xff; + idx++; + } + buf[idx] = data & 0xff; + idx++; + + ret = write(g_fd[ViPipe], buf, os02n10_1l_addr_byte + os02n10_1l_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error! %#x\n", addr); + return CVI_FAILURE; + } + + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void os02n10_1l_standby(VI_PIPE ViPipe) +{ + UNUSED(ViPipe); + printf("os02n10_1l_standby\n"); +} + +void os02n10_1l_restart(VI_PIPE ViPipe) +{ + UNUSED(ViPipe); + printf("os02n10_1l_restart\n"); +} + +void os02n10_1l_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastOs02n10_1l[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + os02n10_1l_write_register(ViPipe, + g_pastOs02n10_1l[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastOs02n10_1l[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } + +} + +#define OS02N10_1L_CHIP_ID_ADDR_HH 0x02 +#define OS02N10_1L_CHIP_ID_ADDR_HL 0x03 +#define OS02N10_1L_CHIP_ID_ADDR_LH 0x04 +#define OS02N10_1L_CHIP_ID_ADDR_LL 0x05 +#define OS02N10_1L_CHIP_ID 0x53024E10 + +int os02n10_1l_probe(VI_PIPE ViPipe) +{ + int nVal, nVal2, nVal3, nVal4; + + usleep(500); + if (os02n10_1l_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + os02n10_1l_write_register(ViPipe, 0xfd, 0x00); + nVal = os02n10_1l_read_register(ViPipe, OS02N10_1L_CHIP_ID_ADDR_HH); + nVal2 = os02n10_1l_read_register(ViPipe, OS02N10_1L_CHIP_ID_ADDR_HL); + nVal3 = os02n10_1l_read_register(ViPipe, OS02N10_1L_CHIP_ID_ADDR_LH); + nVal4 = os02n10_1l_read_register(ViPipe, OS02N10_1L_CHIP_ID_ADDR_LL); + + if (nVal < 0 || nVal2 < 0 || nVal3 < 0 || nVal4 < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + + if ((((nVal & 0xFF) << 24) | ((nVal2 & 0xFF) << 16) | (nVal3 & 0xFF) << 8 | (nVal4 & 0xFF)) != OS02N10_1L_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +void os02n10_1l_init(VI_PIPE ViPipe) +{ + WDR_MODE_E enWDRMode; + CVI_U8 u8ImgMode; + + enWDRMode = g_pastOs02n10_1l[ViPipe]->enWDRMode; + u8ImgMode = g_pastOs02n10_1l[ViPipe]->u8ImgMode; + + os02n10_1l_i2c_init(ViPipe); + + if (enWDRMode == WDR_MODE_NONE) { + if (u8ImgMode == OS02N10_1L_MODE_1080P15) + os02n10_1l_linear_1080p15_init(ViPipe); + } + g_pastOs02n10_1l[ViPipe]->bInit = CVI_TRUE; +} + +void os02n10_1l_exit(VI_PIPE ViPipe) +{ + os02n10_1l_i2c_exit(ViPipe); +} + +//MIPI_1LANE_1920x1080_750M_raw10_15fps +static void os02n10_1l_linear_1080p15_init(VI_PIPE ViPipe) +{ + os02n10_1l_write_register(ViPipe, 0xfc, 0x01); + os02n10_1l_write_register(ViPipe, 0xfd, 0x00); + os02n10_1l_write_register(ViPipe, 0xba, 0x02); + os02n10_1l_write_register(ViPipe, 0xfd, 0x00); + os02n10_1l_write_register(ViPipe, 0xb1, 0x14); + os02n10_1l_write_register(ViPipe, 0xba, 0x00); + os02n10_1l_write_register(ViPipe, 0x1a, 0x00); + os02n10_1l_write_register(ViPipe, 0x1b, 0x00); + + os02n10_1l_write_register(ViPipe, 0xfd, 0x01); + os02n10_1l_write_register(ViPipe, 0x0e, 0x01); + os02n10_1l_write_register(ViPipe, 0x0f, 0x02); + os02n10_1l_write_register(ViPipe, 0x14, 0x04); + os02n10_1l_write_register(ViPipe, 0x15, 0x90); + os02n10_1l_write_register(ViPipe, 0x24, 0xff); + os02n10_1l_write_register(ViPipe, 0x2f, 0x30); + os02n10_1l_write_register(ViPipe, 0xfe, 0x02); + os02n10_1l_write_register(ViPipe, 0x2b, 0xff); + os02n10_1l_write_register(ViPipe, 0x30, 0x00); + os02n10_1l_write_register(ViPipe, 0x31, 0x16); + os02n10_1l_write_register(ViPipe, 0x32, 0x25); + os02n10_1l_write_register(ViPipe, 0x33, 0xfb); + os02n10_1l_write_register(ViPipe, 0xfd, 0x01); + os02n10_1l_write_register(ViPipe, 0x50, 0x03); + os02n10_1l_write_register(ViPipe, 0x51, 0x07); + os02n10_1l_write_register(ViPipe, 0x52, 0x04); + os02n10_1l_write_register(ViPipe, 0x53, 0x05); + os02n10_1l_write_register(ViPipe, 0x57, 0x40); + os02n10_1l_write_register(ViPipe, 0x66, 0x04); + os02n10_1l_write_register(ViPipe, 0x6d, 0x58); + os02n10_1l_write_register(ViPipe, 0x77, 0x01); + os02n10_1l_write_register(ViPipe, 0x79, 0x32); + os02n10_1l_write_register(ViPipe, 0x7c, 0x01); + os02n10_1l_write_register(ViPipe, 0x90, 0x3b); + os02n10_1l_write_register(ViPipe, 0x91, 0x0b); + os02n10_1l_write_register(ViPipe, 0x92, 0x18); + os02n10_1l_write_register(ViPipe, 0x95, 0x40); + os02n10_1l_write_register(ViPipe, 0x99, 0x05); + os02n10_1l_write_register(ViPipe, 0xaa, 0x0e); + os02n10_1l_write_register(ViPipe, 0xab, 0x0c); + os02n10_1l_write_register(ViPipe, 0xac, 0x10); + os02n10_1l_write_register(ViPipe, 0xad, 0x10); + os02n10_1l_write_register(ViPipe, 0xae, 0x20); + os02n10_1l_write_register(ViPipe, 0xb0, 0x0e); + os02n10_1l_write_register(ViPipe, 0xb1, 0x0f); + os02n10_1l_write_register(ViPipe, 0xb2, 0x1a); + os02n10_1l_write_register(ViPipe, 0xb3, 0x1c); + + os02n10_1l_write_register(ViPipe, 0xfd, 0x00); + os02n10_1l_write_register(ViPipe, 0xb0, 0x00); + os02n10_1l_write_register(ViPipe, 0xb1, 0x14); + os02n10_1l_write_register(ViPipe, 0xb2, 0x00); + os02n10_1l_write_register(ViPipe, 0xb3, 0x10); + + os02n10_1l_write_register(ViPipe, 0xfd, 0x03); + os02n10_1l_write_register(ViPipe, 0x08, 0x00); + os02n10_1l_write_register(ViPipe, 0x09, 0x20); + os02n10_1l_write_register(ViPipe, 0x0a, 0x02); + os02n10_1l_write_register(ViPipe, 0x0b, 0x80); + os02n10_1l_write_register(ViPipe, 0x11, 0x41); + os02n10_1l_write_register(ViPipe, 0x12, 0x41); + os02n10_1l_write_register(ViPipe, 0x13, 0x41); + os02n10_1l_write_register(ViPipe, 0x14, 0x41); + os02n10_1l_write_register(ViPipe, 0x17, 0x72); + os02n10_1l_write_register(ViPipe, 0x18, 0x6f); + os02n10_1l_write_register(ViPipe, 0x19, 0x70); + os02n10_1l_write_register(ViPipe, 0x1a, 0x6f); + os02n10_1l_write_register(ViPipe, 0x1b, 0xc0); + os02n10_1l_write_register(ViPipe, 0x1d, 0x01); + os02n10_1l_write_register(ViPipe, 0x1f, 0x80); + os02n10_1l_write_register(ViPipe, 0x20, 0x40); + os02n10_1l_write_register(ViPipe, 0x21, 0x80); + os02n10_1l_write_register(ViPipe, 0x22, 0x40); + os02n10_1l_write_register(ViPipe, 0x23, 0x88); + os02n10_1l_write_register(ViPipe, 0x4b, 0x06); + os02n10_1l_write_register(ViPipe, 0x0e, 0x03); + os02n10_1l_write_register(ViPipe, 0x58, 0x7b); + os02n10_1l_write_register(ViPipe, 0x59, 0x17); + os02n10_1l_write_register(ViPipe, 0x5a, 0x32); + + os02n10_1l_write_register(ViPipe, 0xfd, 0x03); + os02n10_1l_write_register(ViPipe, 0x4c, 0x01); + os02n10_1l_write_register(ViPipe, 0x4d, 0x01); + os02n10_1l_write_register(ViPipe, 0x4e, 0x01); + os02n10_1l_write_register(ViPipe, 0x4f, 0x02); + + os02n10_1l_write_register(ViPipe, 0xfd, 0x00); + os02n10_1l_write_register(ViPipe, 0x13, 0xbe); + os02n10_1l_write_register(ViPipe, 0x14, 0x02); + os02n10_1l_write_register(ViPipe, 0x4c, 0x24); + os02n10_1l_write_register(ViPipe, 0xb6, 0x00); + os02n10_1l_write_register(ViPipe, 0xb7, 0x08); + os02n10_1l_write_register(ViPipe, 0xb9, 0xd6); + os02n10_1l_write_register(ViPipe, 0xc6, 0x95); + os02n10_1l_write_register(ViPipe, 0xc7, 0x77); + os02n10_1l_write_register(ViPipe, 0xc9, 0x22); + os02n10_1l_write_register(ViPipe, 0xca, 0x32); + os02n10_1l_write_register(ViPipe, 0xd7, 0xaa); + os02n10_1l_write_register(ViPipe, 0xbc, 0x1f); + os02n10_1l_write_register(ViPipe, 0xbd, 0x60); + os02n10_1l_write_register(ViPipe, 0xbe, 0x78); + os02n10_1l_write_register(ViPipe, 0xbf, 0xa5); + os02n10_1l_write_register(ViPipe, 0xcb, 0x00); + os02n10_1l_write_register(ViPipe, 0xcc, 0x00); + os02n10_1l_write_register(ViPipe, 0xce, 0x20); + os02n10_1l_write_register(ViPipe, 0xcf, 0x3f); + os02n10_1l_write_register(ViPipe, 0xd0, 0x76); + os02n10_1l_write_register(ViPipe, 0xd1, 0xec); + + os02n10_1l_write_register(ViPipe, 0xfd, 0x04); + os02n10_1l_write_register(ViPipe, 0x1b, 0x01); + + // os02n10_1l_write_register(ViPipe, 0xfd, 0x03); + // os02n10_1l_write_register(ViPipe, 0x01, 0x04); + // os02n10_1l_write_register(ViPipe, 0x02, 0x07); + // os02n10_1l_write_register(ViPipe, 0x03, 0x80); + // os02n10_1l_write_register(ViPipe, 0x05, 0x04); + // os02n10_1l_write_register(ViPipe, 0x06, 0x04); + // os02n10_1l_write_register(ViPipe, 0x07, 0x38); //modify output size + + os02n10_1l_write_register(ViPipe, 0xfd, 0x00); + os02n10_1l_write_register(ViPipe, 0x1e, 0x5f); + os02n10_1l_write_register(ViPipe, 0x3e, 0x00); + os02n10_1l_write_register(ViPipe, 0x0a, 0x00); + os02n10_1l_write_register(ViPipe, 0x1d, 0xa0); + os02n10_1l_write_register(ViPipe, 0x21, 0x04); + os02n10_1l_write_register(ViPipe, 0x24, 0x02); + os02n10_1l_write_register(ViPipe, 0x27, 0x07); + os02n10_1l_write_register(ViPipe, 0x28, 0x88); //780 1920 to 788 1928 + os02n10_1l_write_register(ViPipe, 0x29, 0x04); + os02n10_1l_write_register(ViPipe, 0x2a, 0x40); //438 1080 to 440 1088 + + os02n10_1l_write_register(ViPipe, 0x2d, 0x04); + os02n10_1l_write_register(ViPipe, 0x2e, 0x03); + os02n10_1l_write_register(ViPipe, 0x2f, 0x0c); + os02n10_1l_write_register(ViPipe, 0x31, 0x04); + os02n10_1l_write_register(ViPipe, 0x32, 0x1a); + os02n10_1l_write_register(ViPipe, 0x33, 0x04); + os02n10_1l_write_register(ViPipe, 0x34, 0x03); + os02n10_1l_write_register(ViPipe, 0x3f, 0x41); + os02n10_1l_write_register(ViPipe, 0x40, 0x34); + os02n10_1l_write_register(ViPipe, 0x23, 0x01); + + os02n10_1l_write_register(ViPipe, 0xfd, 0x03); + os02n10_1l_write_register(ViPipe, 0x26, 0x01); + os02n10_1l_write_register(ViPipe, 0xe8, 0x00); //color bar + + os02n10_1l_write_register(ViPipe, 0x28, 0x0a); + os02n10_1l_write_register(ViPipe, 0x29, 0x0a); + os02n10_1l_write_register(ViPipe, 0x2a, 0x52); + os02n10_1l_write_register(ViPipe, 0x2b, 0x5a); + + os02n10_1l_write_register(ViPipe, 0x2c, 0x0a); + os02n10_1l_write_register(ViPipe, 0x2d, 0x0a); + os02n10_1l_write_register(ViPipe, 0x2e, 0x52); + os02n10_1l_write_register(ViPipe, 0x2f, 0x5a); + os02n10_1l_write_register(ViPipe, 0x31, 0x0a); + os02n10_1l_write_register(ViPipe, 0x32, 0x0a); + os02n10_1l_write_register(ViPipe, 0x33, 0x52); + os02n10_1l_write_register(ViPipe, 0x34, 0x5a); + os02n10_1l_write_register(ViPipe, 0x35, 0x0c); + os02n10_1l_write_register(ViPipe, 0x36, 0x10); + os02n10_1l_write_register(ViPipe, 0x37, 0x07); + os02n10_1l_write_register(ViPipe, 0x38, 0x0a); + os02n10_1l_write_register(ViPipe, 0x39, 0x0c); + os02n10_1l_write_register(ViPipe, 0x3a, 0x10); + os02n10_1l_write_register(ViPipe, 0x3b, 0x07); + os02n10_1l_write_register(ViPipe, 0x3c, 0x0a); + os02n10_1l_write_register(ViPipe, 0x3d, 0x0c); + os02n10_1l_write_register(ViPipe, 0x3e, 0x10); + os02n10_1l_write_register(ViPipe, 0x3f, 0x07); + os02n10_1l_write_register(ViPipe, 0x40, 0x0a); + os02n10_1l_write_register(ViPipe, 0x41, 0x07); + os02n10_1l_write_register(ViPipe, 0x42, 0x07); + os02n10_1l_write_register(ViPipe, 0x43, 0x07); + os02n10_1l_write_register(ViPipe, 0x44, 0x07); + os02n10_1l_write_register(ViPipe, 0x46, 0x10); + os02n10_1l_write_register(ViPipe, 0x47, 0xe2); + os02n10_1l_write_register(ViPipe, 0x45, 0x50); + os02n10_1l_write_register(ViPipe, 0xfb, 0x03); + + os02n10_1l_default_reg_init(ViPipe); + delay_ms(100); + printf("ViPipe:%d,===OS02N10_1L 1080P 15fps 10bit LINE Init OK!===\n", ViPipe); +} diff --git a/middleware/v2/component/isp/sensor/cv182x/sms_sc2331_1L_slave1/sc2331_1L_slave1_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv182x/sms_sc2331_1L_slave1/sc2331_1L_slave1_sensor_ctl.c index dcf98663f..490461afe 100644 --- a/middleware/v2/component/isp/sensor/cv182x/sms_sc2331_1L_slave1/sc2331_1L_slave1_sensor_ctl.c +++ b/middleware/v2/component/isp/sensor/cv182x/sms_sc2331_1L_slave1/sc2331_1L_slave1_sensor_ctl.c @@ -24,7 +24,7 @@ static void sc2331_1L_slave1_linear_1080p30_init(VI_PIPE ViPipe); -const CVI_U8 sc2331_1L_slave1_i2c_addr = 0x30; /* I2C Address of SC2331_1L */ +const CVI_U8 sc2331_1L_slave1_i2c_addr = 0x32; /* I2C Address of SC2331_1L */ const CVI_U32 sc2331_1L_slave1_addr_byte = 2; const CVI_U32 sc2331_1L_slave1_data_byte = 1; static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; @@ -257,7 +257,6 @@ static void sc2331_1L_slave1_linear_1080p30_init(VI_PIPE ViPipe) sc2331_1L_slave1_write_register(ViPipe, 0x3018, 0x1a); sc2331_1L_slave1_write_register(ViPipe, 0x3019, 0x0e); sc2331_1L_slave1_write_register(ViPipe, 0x301f, 0x20); - printf("awei 22 hao 14:15 sc2331_1L_slave1\n"); // sc2331_1L_slave1_write_register(ViPipe, 0x320e, 0x04); // sc2331_1L_slave1_write_register(ViPipe, 0x320f, 0x65); diff --git a/middleware/v2/component/isp/sensor/cv182x/sony_imx675/Makefile b/middleware/v2/component/isp/sensor/cv182x/sony_imx675/Makefile new file mode 100644 index 000000000..a662867b7 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/sony_imx675/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_imx675.a +TARGET_SO = $(MW_LIB)/libsns_imx675.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $@) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $@) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos.c b/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos.c new file mode 100644 index 000000000..f44d0f22d --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos.c @@ -0,0 +1,1199 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "imx675_cmos_ex.h" +#include "imx675_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define IMX675_ID 675 +#define SENSOR_IMX675_WIDTH 2560 +#define SENSOR_IMX675_HEIGHT 1944 +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastImx675[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define IMX675_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastImx675[dev]) +#define IMX675_SENSOR_SET_CTX(dev, pstCtx) (g_pastImx675[dev] = pstCtx) +#define IMX675_SENSOR_RESET_CTX(dev) (g_pastImx675[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunImx675_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16Imx675_GainMode[VI_MAX_PIPE_NUM] = {0}; + +IMX675_STATE_S g_astImx675_State[VI_MAX_PIPE_NUM] = {{0} }; +ISP_SNS_MIRRORFLIP_TYPE_E g_aeImx675_MirrorFip[VI_MAX_PIPE_NUM] = {0}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static ISP_FSWDR_MODE_E genFSWDRMode[VI_MAX_PIPE_NUM] = { + [0 ... VI_MAX_PIPE_NUM - 1] = ISP_FSWDR_NORMAL_MODE +}; + +static CVI_U32 gu32MaxTimeGetCnt[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0}}; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****Imx675 Lines Range*****/ +#define IMX675_FULL_LINES_MAX (0xFFFFFF) +#define IMX675_FULL_LINES_MAX_2TO1_WDR (0xFFFFFF) + +/*****Imx675 Register Address*****/ +#define IMX675_HOLD_ADDR 0x3001 +#define IMX675_SHR0_ADDR 0X3050 //Shutter setting of LEF +#define IMX675_SHR1_ADDR 0X3054 +#define IMX675_GAIN_ADDR 0X3070 +#define IMX675_GAIN1_ADDR 0x3072 +#define IMX675_HCG_ADDR 0x3030 +#define IMX675_VMAX_ADDR 0X3028 //Number of vertical lines per 1 Frame +#define IMX675_RHS1_ADDR 0X3060 //Readout timing setting of SEF1 +#define IMX675_TABLE_END 0xffff + +#define IMX675_RES_IS_5M(w, h) ((w) <= 2560 && (h) <= 1944) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); +#if 0 + memset(&pstAeSnsDft->stAERouteAttr, 0, sizeof(ISP_AE_ROUTE_S)); +#endif + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = IMX675_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 8; +#if 0 + pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0; + pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0; + + pstAeSnsDft->bAERouteExValid = CVI_FALSE; + pstAeSnsDft->stAERouteAttr.u32TotalNum = 0; + pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0; +#endif + switch (pstSnsState->enWDRMode) { + default: + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = g_astImx675_mode[IMX675_MODE_5M30].f32MaxFps; + pstAeSnsDft->f32MinFps = g_astImx675_mode[IMX675_MODE_5M30].f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = 32381; + pstAeSnsDft->u32MinAgain = 1024; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = 128914; + pstAeSnsDft->u32MinDgain = 1024; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; //? + //4 to (Number of lines per frame - 1) + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 1; + pstAeSnsDft->u32MinIntTime = 4; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 4; + break; + + case WDR_MODE_2To1_LINE: + pstAeSnsDft->f32Fps = g_astImx675_mode[IMX675_MODE_5M25_WDR].f32MaxFps; + pstAeSnsDft->f32MinFps = g_astImx675_mode[IMX675_MODE_5M25_WDR].f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xC; + pstAeSnsDft->au8HistThresh[1] = 0x18; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 1; + pstAeSnsDft->u32MinIntTime = 4; + + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = pstAeSnsDft->u32MinIntTime; + + pstAeSnsDft->u32MaxAgain = 32381; //30dB + pstAeSnsDft->u32MinAgain = 1024; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = 128914; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + pstAeSnsDft->u32MaxISPDgainTarget = 16 << pstAeSnsDft->u32ISPDgainShift; + + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 52000; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 5; + if (genFSWDRMode[ViPipe] == ISP_FSWDR_LONG_FRAME_MODE) { + pstAeSnsDft->u8AeCompensation = 64; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + } else { + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->enAeExpMode = AE_EXP_LOWLIGHT_PRIOR; + /* [TODO] */ +#if 0 + pstAeSnsDft->u16ManRatioEnable = CVI_TRUE; + pstAeSnsDft->au32Ratio[0] = 0x400; + pstAeSnsDft->au32Ratio[1] = 0x40; + pstAeSnsDft->au32Ratio[2] = 0x40; +#endif + } + break; + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astImx675_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astImx675_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astImx675_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case IMX675_MODE_5M25_WDR: + + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > IMX675_FULL_LINES_MAX_2TO1_WDR) ? IMX675_FULL_LINES_MAX_2TO1_WDR : u32VMAX; + break; + + case IMX675_MODE_5M30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > IMX675_FULL_LINES_MAX) ? IMX675_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_INFO, "Unsupport sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_0].u32Data = (u32VMAX & 0xFF); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_1].u32Data = ((u32VMAX & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_2].u32Data = ((u32VMAX & 0xF0000) >> 16); + } else { + pstSnsRegsInfo->astI2cData[DOL2_VMAX_0].u32Data = (u32VMAX & 0xFF); + pstSnsRegsInfo->astI2cData[DOL2_VMAX_1].u32Data = ((u32VMAX & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[DOL2_VMAX_2].u32Data = ((u32VMAX & 0xF0000) >> 16); + } + + if (WDR_MODE_2To1_LINE == pstSnsState->enWDRMode) { + pstSnsState->u32FLStd = u32VMAX * 2; + g_astImx675_State[ViPipe].u32RHS1_MAX = (u32VMAX - g_astImx675_State[ViPipe].u32BRL) * 2 - 21; + + } else { + pstSnsState->u32FLStd = u32VMAX; + } + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 1; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + + +/* DOL 2 frame +* FSC:Frame Set Count VMAX × 2 and 4n (n = 0, 1, 2 ...) +* SHR1:Shutter timing of SEF1 5 ≤ SHR1 ≤ (RHS1 – 2) , 2n + 1 +* RHS1:Readout timing of SEF1 (All-Pixel) (SHR1 + 2) ≤ RHS1 ≤ (SHR0 – 5) , 4n + 1 +* RHS1 < (BRL × 2) +* SHR0:Shutter timing of LEF (RHS1 + 5) ≤ SHR0 ≤ (FSC – 2), 2n +* Exposure time of SEF1 : RHS1 - SHR1 +* Exposure time of LEF: FSC - SHR0 //FSC= ELEF +SHR0 +* Max Sexp = RHS1 - SHR1 = RHS1 - 5 +* Max Lexp = FSC - RHS1 - 5 +* Max Sexp + Lexp = FSC - 10 +* Sexp = (FSC - 10) / (1 + Ratio) +*/ + +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Value = 0; + CVI_U32 u32RHS1 = 0; + CVI_U32 u32SHR0 = 0; + CVI_U32 u32SHR1 = 0; + CVI_U32 module4 = 0, module2 = 0; + + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + if (WDR_MODE_2To1_LINE == pstSnsState->enWDRMode) { + CVI_U32 u32ShortIntTime = u32IntTime[0]; + CVI_U32 u32LongIntTime = u32IntTime[1]; + + if (pstSnsState->au32FL[1] < u32LongIntTime + 2) { // FSC ≥ SHR0 + 2 + CVI_TRACE_SNS(CVI_DBG_DEBUG, "FL %d is smaller than = %d\n", + pstSnsState->au32FL[1], u32LongIntTime + 2); + return CVI_FAILURE; + } + /* SHR0 shall be 2n */ + + u32SHR0 = ((pstSnsState->au32FL[1] - u32LongIntTime) & ~1UL); + + module4 = u32ShortIntTime % 4; + module2 = u32ShortIntTime % 2; + + /* SHS1 is 5 or 7. + * when tSef is multiple of 4, SHS1 = 5, RHS1 = 5 + tSEF = 4*n+1. + * otherwise, when mod(tSef, 4) = 3, 2, SHS1 = 7, RHS1 = 7 + tSEF - mod(tSef, 2) = 4*n+1. + * when mod(tSef,4) = 0 or 1, SHS1 = 5, RHS1 = 5 + tSEF - mod(tSef, 2) = 4*n+1 + */ + if (!module4) { + u32SHR1 = 5; + u32RHS1 = u32ShortIntTime + u32SHR1; + g_astImx675_State[ViPipe].u32RHS1 = u32RHS1; + } else { + if (module4 == module2) { + u32SHR1 = 5; + u32RHS1 = u32ShortIntTime + u32SHR1 - module2; + g_astImx675_State[ViPipe].u32RHS1 = u32RHS1; + } else { + u32SHR1 = 7; + u32RHS1 = u32ShortIntTime + u32SHR1 - module2; + g_astImx675_State[ViPipe].u32RHS1 = u32RHS1; + } + } + + if (u32SHR0 < (u32SHR1 + u32RHS1)) { + u32SHR0 = u32SHR1 + u32RHS1; + } + + /* short exposure */ + pstSnsState->au32WDRIntTime[0] = u32RHS1 - u32SHR1; + /* long exposure */ + pstSnsState->au32WDRIntTime[1] = pstSnsState->au32FL[1] - u32SHR0; + /* Return the actual exposure lines*/ + u32IntTime[0] = pstSnsState->au32WDRIntTime[0]; + u32IntTime[1] = pstSnsState->au32WDRIntTime[1]; + + pstSnsRegsInfo->astI2cData[DOL2_SHR0_0].u32Data = (u32SHR0 & 0xFF); + pstSnsRegsInfo->astI2cData[DOL2_SHR0_1].u32Data = ((u32SHR0 & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[DOL2_SHR0_2].u32Data = ((u32SHR0 & 0xF0000) >> 16); + + pstSnsRegsInfo->astI2cData[DOL2_SHR1_0].u32Data = (u32SHR1 & 0xFF); + pstSnsRegsInfo->astI2cData[DOL2_SHR1_1].u32Data = ((u32SHR1 & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[DOL2_SHR1_2].u32Data = ((u32SHR1 & 0xF0000) >> 16); + + pstSnsRegsInfo->astI2cData[DOL2_RHS1_0].u32Data = (u32RHS1 & 0xFF); + pstSnsRegsInfo->astI2cData[DOL2_RHS1_1].u32Data = ((u32RHS1 & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[DOL2_RHS1_2].u32Data = ((u32RHS1 & 0xF0000) >> 16); + + /* update isp */ + cmos_get_wdr_size(ViPipe, &pstSnsState->astSyncInfo[0].ispCfg); + } else { + u32Value = pstSnsState->au32FL[0] - *u32IntTime; + u32Value = (u32Value > (pstSnsState->au32FL[0] - 1)) ? (pstSnsState->au32FL[0] - 1) : + ((u32Value < 5) ? 5 : u32Value); + + pstSnsRegsInfo->astI2cData[LINEAR_SHR0_0].u32Data = (u32Value & 0xFF); + pstSnsRegsInfo->astI2cData[LINEAR_SHR0_1].u32Data = ((u32Value & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_SHR0_2].u32Data = ((u32Value & 0x30000) >> 16); + } + + return CVI_SUCCESS; +} + +static CVI_U32 gain_table[241] = { + 1024, 1059, 1097, 1135, 1175, 1217, 1259, 1304, 1349, 1397, 1446, 1497, 1549, 1604, 1660, 1719, 1779, 1842, + 1906, 1973, 2043, 2114, 2189, 2266, 2345, 2428, 2513, 2602, 2693, 2788, 2886, 2987, 3092, 3201, 3313, 3430, + 3550, 3675, 3804, 3938, 4076, 4219, 4368, 4521, 4680, 4845, 5015, 5191, 5374, 5562, 5758, 5960, 6170, 6387, + 6611, 6843, 7084, 7333, 7591, 7857, 8134, 8419, 8715, 9022, 9339, 9667, 10007, 10358, 10722, 11099, 11489, + 11893, 12311, 12743, 13191, 13655, 14135, 14631, 15146, 15678, 16229, 16799, 17390, 18001, 18633, 19288, + 19966, 20668, 21394, 22146, 22924, 23730, 24564, 25427, 26320, 27245, 28203, 29194, 30220, 31282, 32381, + 33519, 34697, 35917, 37179, 38485, 39838, 41238, 42687, 44187, 45740, 47347, 49011, 50734, 52517, 54362, 56272, + 58250, 60297, 62416, 64610, 66880, 69231, 71663, 74182, 76789, 79487, 82281, 85172, 88165, 91264, 94471, 97791, + 101227, 104785, 108467, 112279, 116225, 120309, 124537, 128913, 133444, 138133, 142988, 148013, 153214, 158599, + 164172, 169941, 175913, 182095, 188495, 195119, 201976, 209073, 216421, 224026, 231899, 240049, 248485, 257217, + 266256, 275613, 285298, 295324, 305703, 320110, 675567, 339078, 350994, 363329, 376097, 389314, 402995, 417157, + 431817, 446992, 462700, 478960, 495792, 513215, 531251, 549920, 569246, 589250, 609958, 631393, 653581, 676550, + 700325, 724936, 750412, 776783, 804081, 832338, 861588, 891866, 923208, 955652, 989236, 1024000, 1059985, + 1097235, 1135795, 1175709, 1217026, 1259795, 1304067, 1349894, 1397333, 1446438, 1497269, 1549886, 1604353, + 1660733, 1719095, 1779508, 1842043, 1906777, 1913785, 2043148, 2114949, 2189273, 2266208, 2345848, 2428286, + 2513621, 2601956, 2662563, 2788046, 2886024, 2987445, 3092430, 3201105, 3313599, 3430046, 3550585, 3675361, + 3804521, 3938220, 4076617 +}; + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + int i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (*pu32AgainLin >= gain_table[240]) { + *pu32AgainLin = gain_table[240]; + *pu32AgainDb = 240; + return CVI_SUCCESS; + } + + for (i = 1; i < 241; i++) { + if (*pu32AgainLin < gain_table[i]) { + *pu32AgainLin = gain_table[i - 1]; + *pu32AgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + int i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= gain_table[140]) { //again 30dB + *pu32DgainLin = gain_table[140]; + *pu32DgainDb = 140; + return CVI_SUCCESS; + } + + for (i = 1; i < 141; i++) { + if (*pu32DgainLin < gain_table[i]) { + *pu32DgainLin = gain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32HCG = g_astImx675_State[ViPipe].u8Hcg; + CVI_U32 u16Mode = g_au16Imx675_GainMode[ViPipe]; + CVI_U32 u32Tmp; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear mode */ + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + if (u32Again >= 30) { + /* hcg bit[2]*/ + u32HCG = u32HCG | 0x10; + u32Again = u32Again - 30; + } + + u32Tmp = u32Again + u32Dgain; + + pstSnsRegsInfo->astI2cData[LINEAR_GAIN].u32Data = (u32Tmp & 0xFF); + pstSnsRegsInfo->astI2cData[LINEAR_HCG].u32Data = (u32HCG & 0xFF); + } else { + /* DOL mode */ + if (u16Mode == SNS_GAIN_MODE_WDR_2F) { + /* don't support gain conversion in this mode. */ + u32Again = pu32Again[1]; + u32Dgain = pu32Dgain[1]; + + u32Tmp = u32Again + u32Dgain; + if (u32Tmp > 0xFF) { + u32Tmp = 0xFF; + } + if (u32HCG > 0xFF) { + u32HCG = 0xFF; + } + pstSnsRegsInfo->astI2cData[DOL2_GAIN].u32Data = (u32Tmp & 0xFF); + pstSnsRegsInfo->astI2cData[DOL2_HCG].u32Data = (u32HCG & 0xFF); + + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + u32Tmp = u32Again + u32Dgain; + if (u32Tmp > 0xFF) { + u32Tmp = 0xFF; + } + pstSnsRegsInfo->astI2cData[DOL2_GAIN1].u32Data = (u32Tmp & 0xFF); + } else if (u16Mode == SNS_GAIN_MODE_SHARE) { + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + if (u32Again >= 30) { + /* hcg bit[2]*/ + u32HCG = u32HCG | 0x10; + u32Again = u32Again - 30; + } + + u32Tmp = u32Again + u32Dgain; + if (u32Tmp > 0xFF) { + u32Tmp = 0xFF; + } + if (u32HCG > 0xFF) { + u32HCG = 0xFF; + } + pstSnsRegsInfo->astI2cData[DOL2_GAIN].u32Data = (u32Tmp & 0xFF); + pstSnsRegsInfo->astI2cData[DOL2_HCG].u32Data = (u32HCG & 0xFF); + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio, + CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime) +{ + CVI_U32 u32IntTimeMaxTmp = 0, u32IntTimeMaxTmp0 = 0; + CVI_U32 u32RatioTmp = 0x40; + CVI_U32 u32ShortTimeMinLimit = 0; + + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(au32Ratio); + CMOS_CHECK_POINTER(au32IntTimeMax); + CMOS_CHECK_POINTER(au32IntTimeMin); + CMOS_CHECK_POINTER(pu32LFMaxIntTime); + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32ShortTimeMinLimit = (WDR_MODE_2To1_LINE == pstSnsState->enWDRMode) ? 2 : 2; + + if (WDR_MODE_2To1_LINE == pstSnsState->enWDRMode) { + if (genFSWDRMode[ViPipe] == ISP_FSWDR_LONG_FRAME_MODE) { + u32IntTimeMaxTmp = pstSnsState->au32FL[0] - 12; + au32IntTimeMax[0] = u32IntTimeMaxTmp; + au32IntTimeMin[0] = u32ShortTimeMinLimit; + return CVI_SUCCESS; + } + u32IntTimeMaxTmp0 = ((pstSnsState->au32FL[1] - 12 - pstSnsState->au32WDRIntTime[0]) * 0x40) / + DIV_0_TO_1(au32Ratio[0]); + u32IntTimeMaxTmp = ((pstSnsState->au32FL[0] - 12) * 0x40) / DIV_0_TO_1(au32Ratio[0] + 0x40); + u32IntTimeMaxTmp = (u32IntTimeMaxTmp > u32IntTimeMaxTmp0) ? u32IntTimeMaxTmp0 : u32IntTimeMaxTmp; + u32IntTimeMaxTmp = (u32IntTimeMaxTmp > (g_astImx675_State[ViPipe].u32RHS1_MAX - 7)) ? + (g_astImx675_State[ViPipe].u32RHS1_MAX - 7) : u32IntTimeMaxTmp; + u32IntTimeMaxTmp = (!u32IntTimeMaxTmp) ? 1 : u32IntTimeMaxTmp; + + } + + if (u32IntTimeMaxTmp >= u32ShortTimeMinLimit) { + if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) { + au32IntTimeMax[0] = u32IntTimeMaxTmp; + au32IntTimeMax[1] = au32IntTimeMax[0] * au32Ratio[0] >> 6; + au32IntTimeMax[2] = au32IntTimeMax[1] * au32Ratio[1] >> 6; + au32IntTimeMax[3] = au32IntTimeMax[2] * au32Ratio[2] >> 6; + au32IntTimeMin[0] = u32ShortTimeMinLimit; + au32IntTimeMin[1] = au32IntTimeMin[0] * au32Ratio[0] >> 6; + au32IntTimeMin[2] = au32IntTimeMin[1] * au32Ratio[1] >> 6; + au32IntTimeMin[3] = au32IntTimeMin[2] * au32Ratio[2] >> 6; + } else { + } + } else { + if (u16ManRatioEnable) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Manaul ExpRatio out of range!\n"); + return CVI_FAILURE; + } + u32IntTimeMaxTmp = u32ShortTimeMinLimit; + + if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) { + u32RatioTmp = 0xFFF; + au32IntTimeMax[0] = u32IntTimeMaxTmp; + au32IntTimeMax[1] = au32IntTimeMax[0] * u32RatioTmp >> 6; + } else { + } + au32IntTimeMin[0] = au32IntTimeMax[0]; + au32IntTimeMin[1] = au32IntTimeMax[1]; + au32IntTimeMin[2] = au32IntTimeMax[2]; + au32IntTimeMin[3] = au32IntTimeMax[3]; + } + + return CVI_SUCCESS; +} + +/* Only used in LINE_WDR mode */ +static CVI_S32 cmos_ae_fswdr_attr_set(VI_PIPE ViPipe, AE_FSWDR_ATTR_S *pstAeFSWDRAttr) +{ + CMOS_CHECK_POINTER(pstAeFSWDRAttr); + + genFSWDRMode[ViPipe] = pstAeFSWDRAttr->enFSWDRMode; + gu32MaxTimeGetCnt[ViPipe] = 0; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const IMX675_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astImx675_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode != WDR_MODE_NONE) { + pstIspCfg->frm_num = 2; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S)); + } else { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + if (pstSnsState->u8ImgMode == IMX675_MODE_5M25_WDR) + pstSnsState->u8ImgMode = IMX675_MODE_5M30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astImx675_mode[pstSnsState->u8ImgMode].u32VtsDef; + g_astImx675_State[ViPipe].u8Hcg = 0x1; + CVI_TRACE_SNS(CVI_DBG_INFO, "WDR_MODE_NONE\n"); + break; + + case WDR_MODE_2To1_LINE: + if (pstSnsState->u8ImgMode == IMX675_MODE_5M30) + pstSnsState->u8ImgMode = IMX675_MODE_5M25_WDR; + pstSnsState->enWDRMode = WDR_MODE_2To1_LINE; + g_astImx675_State[ViPipe].u8Hcg = 0x1; + if (pstSnsState->u8ImgMode == IMX675_MODE_5M25_WDR) { + pstSnsState->u32FLStd = g_astImx675_mode[pstSnsState->u8ImgMode].u32VtsDef * 2; + g_astImx675_State[ViPipe].u32BRL = g_astImx675_mode[pstSnsState->u8ImgMode].u16BRL; + CVI_TRACE_SNS(CVI_DBG_INFO, "WDR_MODE_2To1_LINE 5M\n"); + } + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Unknown mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunImx675_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 2; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = (WDR_MODE_2To1_LINE == pstSnsState->enWDRMode) ? + DOL2_REGS_NUM : LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = imx675_i2c_addr; + pstI2c_data[i].u32AddrByteNum = imx675_addr_byte; + pstI2c_data[i].u32DataByteNum = imx675_data_byte; + } + + switch (pstSnsState->enWDRMode) { + case WDR_MODE_2To1_LINE: + pstI2c_data[DOL2_HOLD].u32RegAddr = IMX675_HOLD_ADDR; + pstI2c_data[DOL2_HOLD].u32Data = 1; + pstI2c_data[DOL2_SHR0_0].u32RegAddr = IMX675_SHR0_ADDR; + pstI2c_data[DOL2_SHR0_1].u32RegAddr = IMX675_SHR0_ADDR + 1; + pstI2c_data[DOL2_SHR0_2].u32RegAddr = IMX675_SHR0_ADDR + 2; + + pstI2c_data[DOL2_GAIN].u32RegAddr = IMX675_GAIN_ADDR; + pstI2c_data[DOL2_HCG].u32RegAddr = IMX675_HCG_ADDR; + pstI2c_data[DOL2_GAIN1].u32RegAddr = IMX675_GAIN1_ADDR; + pstI2c_data[DOL2_RHS1_0].u32RegAddr = IMX675_RHS1_ADDR; + pstI2c_data[DOL2_RHS1_1].u32RegAddr = IMX675_RHS1_ADDR + 1; + pstI2c_data[DOL2_RHS1_2].u32RegAddr = IMX675_RHS1_ADDR + 2; + pstI2c_data[DOL2_SHR1_0].u32RegAddr = IMX675_SHR1_ADDR; + pstI2c_data[DOL2_SHR1_1].u32RegAddr = IMX675_SHR1_ADDR + 1; + pstI2c_data[DOL2_SHR1_2].u32RegAddr = IMX675_SHR1_ADDR + 2; + pstI2c_data[DOL2_VMAX_0].u32RegAddr = IMX675_VMAX_ADDR; + pstI2c_data[DOL2_VMAX_1].u32RegAddr = IMX675_VMAX_ADDR + 1; + pstI2c_data[DOL2_VMAX_2].u32RegAddr = IMX675_VMAX_ADDR + 2; + pstI2c_data[DOL2_REL].u32RegAddr = IMX675_HOLD_ADDR; + pstI2c_data[DOL2_REL].u32Data = 0; + pstCfg0->ispCfg.u8DelayFrmNum = 1; + break; + default: + pstI2c_data[LINEAR_HOLD].u32RegAddr = IMX675_HOLD_ADDR; + pstI2c_data[LINEAR_HOLD].u32Data = 1; + pstI2c_data[LINEAR_SHR0_0].u32RegAddr = IMX675_SHR0_ADDR; + pstI2c_data[LINEAR_SHR0_1].u32RegAddr = IMX675_SHR0_ADDR + 1; + pstI2c_data[LINEAR_SHR0_2].u32RegAddr = IMX675_SHR0_ADDR + 2; + pstI2c_data[LINEAR_GAIN].u32RegAddr = IMX675_GAIN_ADDR; + pstI2c_data[LINEAR_HCG].u32RegAddr = IMX675_HCG_ADDR; + pstI2c_data[LINEAR_VMAX_0].u32RegAddr = IMX675_VMAX_ADDR; + pstI2c_data[LINEAR_VMAX_1].u32RegAddr = IMX675_VMAX_ADDR + 1; + pstI2c_data[LINEAR_VMAX_2].u32RegAddr = IMX675_VMAX_ADDR + 2; + pstI2c_data[LINEAR_REL].u32RegAddr = IMX675_HOLD_ADDR; + pstI2c_data[LINEAR_REL].u32Data = 0; + pstCfg0->ispCfg.u8DelayFrmNum = 0; + break; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + if (pstCfg0->snsCfg.need_update == CVI_TRUE) { + if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) { + pstI2c_data[DOL2_HOLD].u32Data = 1; + pstI2c_data[DOL2_HOLD].bUpdate = CVI_TRUE; + pstI2c_data[DOL2_REL].u32Data = 0; + pstI2c_data[DOL2_REL].bUpdate = CVI_TRUE; + } else { + pstI2c_data[LINEAR_HOLD].u32Data = 1; + pstI2c_data[LINEAR_HOLD].bUpdate = CVI_TRUE; + pstI2c_data[LINEAR_REL].u32Data = 0; + pstI2c_data[LINEAR_REL].bUpdate = CVI_TRUE; + } + } + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (IMX675_RES_IS_5M(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = IMX675_MODE_5M30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) { + if (IMX675_RES_IS_5M(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = IMX675_MODE_5M25_WDR; + g_astImx675_State[ViPipe].u32BRL = 1109; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + if (pstSnsState->bInit == CVI_TRUE && g_aeImx675_MirrorFip[ViPipe] != eSnsMirrorFlip) { + imx675_mirror_flip(ViPipe, eSnsMirrorFlip); + g_aeImx675_MirrorFip[ViPipe] = eSnsMirrorFlip; + } +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const IMX675_MODE_S *pstMode = CVI_NULL; + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = IMX675_MODE_5M30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astImx675_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + IMX675_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &imx675_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astImx675_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astImx675_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &imx675_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = imx675_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = imx675_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + return CVI_SUCCESS; +} + + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 imx675_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunImx675_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + IMX675_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + IMX675_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + IMX675_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + IMX675_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = IMX675_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret = CVI_SUCCESS; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, IMX675_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, IMX675_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, IMX675_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return s32Ret; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16Imx675_GainMode[ViPipe] = pstInitAttr->enGainMode; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_probe(VI_PIPE ViPipe) +{ + return imx675_probe(ViPipe); +} + +ISP_SNS_OBJ_S stSnsImx675_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = imx675_standby, + .pfnRestart = imx675_restart, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnWriteReg = imx675_write_register, + .pfnReadReg = imx675_read_register, + .pfnSetBusInfo = imx675_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sensor_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos_ex.h b/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos_ex.h new file mode 100644 index 000000000..8210449ad --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos_ex.h @@ -0,0 +1,121 @@ +#ifndef __IMX675_CMOS_EX_H_ +#define __IMX675_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +#define syslog(level, fmt, ...) \ +do { \ + printf(fmt, ##__VA_ARGS__); \ +} while (0) + +/* [TODO] ======== Temporarily definitions end ========*/ +enum imx675_linear_regs_e { + LINEAR_HOLD = 0, + LINEAR_SHR0_0, + LINEAR_SHR0_1, + LINEAR_SHR0_2, + LINEAR_GAIN, + LINEAR_HCG, + LINEAR_VMAX_0, + LINEAR_VMAX_1, + LINEAR_VMAX_2, + LINEAR_REL, + LINEAR_REGS_NUM +}; + +enum imx675_dol2_regs_e { + DOL2_HOLD = 0, + DOL2_SHR0_0, + DOL2_SHR0_1, + DOL2_SHR0_2, + DOL2_GAIN, + DOL2_HCG, + DOL2_GAIN1, + DOL2_RHS1_0, + DOL2_RHS1_1, + DOL2_RHS1_2, + DOL2_SHR1_0, + DOL2_SHR1_1, + DOL2_SHR1_2, + DOL2_VMAX_0, + DOL2_VMAX_1, + DOL2_VMAX_2, + DOL2_REL, + DOL2_REGS_NUM +}; + +typedef enum _IMX675_MODE_E { + IMX675_MODE_5M30 = 0, + IMX675_MODE_LINEAR_NUM, + IMX675_MODE_5M25_WDR = IMX675_MODE_LINEAR_NUM, + IMX675_MODE_NUM +} IMX675_MODE_E; + +typedef struct _IMX675_STATE_S { + CVI_U8 u8Hcg; + CVI_U32 u32BRL; + CVI_U32 u32SHR1; + CVI_U32 u32RHS1; + CVI_U32 u32RHS1_MAX; +} IMX675_STATE_S; + +typedef struct _IMX675_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_S stAgain[2]; + SNS_ATTR_S stDgain[2]; + CVI_U16 u16RHS1; + CVI_U16 u16BRL; + CVI_U16 u16OpbSize; + CVI_U16 u16MarginVtop; + CVI_U16 u16MarginVbot; + char name[64]; +} IMX675_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastImx675[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunImx675_BusInfo[]; +extern CVI_U16 g_au16Imx675_GainMode[]; +extern const CVI_U8 imx675_i2c_addr; +extern const CVI_U32 imx675_addr_byte; +extern const CVI_U32 imx675_data_byte; +extern void imx675_init(VI_PIPE ViPipe); +extern void imx675_exit(VI_PIPE ViPipe); +extern void imx675_standby(VI_PIPE ViPipe); +extern void imx675_restart(VI_PIPE ViPipe); +extern int imx675_write_register(VI_PIPE ViPipe, int addr, int data); +extern int imx675_read_register(VI_PIPE ViPipe, int addr); +extern void imx675_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int imx675_probe(VI_PIPE ViPipe); + + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __IMX675_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos_param.h b/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos_param.h new file mode 100644 index 000000000..5a79f4f62 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_cmos_param.h @@ -0,0 +1,216 @@ +#ifndef __IMX675_CMOS_PARAM_H_ +#define __IMX675_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "imx675_cmos_ex.h" + +static const IMX675_MODE_S g_astImx675_mode[IMX675_MODE_NUM] = { + [IMX675_MODE_5M30] = { + .name = "5M30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 2608, + .u32Height = 1964, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 2560, + .u32Height = 1944, + }, + .stMaxSize = { + .u32Width = 2608, + .u32Height = 1964, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 0.0066, + .u32HtsDef = 0x1130, + .u32VtsDef = 3666, + .stExp[0] = { + .u16Min = 1, + .u16Max = 1123, + .u16Def = 400, + .u16Step = 1, + }, + .stAgain[0] = { + .u16Min = 1024, + .u16Max = 32381, + .u16Def = 1024, + .u16Step = 1, + }, + .stDgain[0] = { + .u16Min = 1024, + .u16Max = 65535, + .u16Def = 1024, + .u16Step = 1, + }, + .u16RHS1 = 7, + .u16BRL = 1984, + .u16OpbSize = 10, + .u16MarginVtop = 8, + .u16MarginVbot = 9, + }, + [IMX675_MODE_5M25_WDR] = { + .name = "5M25wdr", + /* sef */ + .astImg[0] = { + .stSnsSize = { + .u32Width = 2608, + .u32Height = 1964, + + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 2560, + .u32Height = 1944, + }, + .stMaxSize = { + .u32Width = 2608, + .u32Height = 1964, + }, + }, + /* lef */ + .astImg[1] = { + .stSnsSize = { + .u32Width = 2608, + .u32Height = 1964, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 2560, + .u32Height = 1944, + + }, + .stMaxSize = { + .u32Width = 2608, + .u32Height = 1964, + }, + }, + .f32MaxFps = 25, + .f32MinFps = 0.0033, /* 2200 * 25 / 0xFFFFFF */ + .u32HtsDef = 0x0898, + .u32VtsDef = 2200, + .stExp[0] = { + .u16Min = 1, + .u16Max = 8, + .u16Def = 8, + .u16Step = 1, + }, + .stExp[1] = { + .u16Min = 1, + .u16Max = 2236, + .u16Def = 828, + .u16Step = 1, + }, + .stAgain[0] = { + .u16Min = 1024, + .u16Max = 62416, + .u16Def = 1024, + .u16Step = 1, + }, + .stAgain[1] = { + .u16Min = 1024, + .u16Max = 62416, + .u16Def = 1024, + .u16Step = 1, + }, + .stDgain[0] = { + .u16Min = 1024, + .u16Max = 38485, + .u16Def = 1024, + .u16Step = 1, + }, + .stDgain[1] = { + .u16Min = 1024, + .u16Max = 38485, + .u16Def = 1024, + .u16Step = 1, + }, + .u16RHS1 = 7, + .u16BRL = 1984, + .u16OpbSize = 7, + .u16MarginVtop = 8, + .u16MarginVbot = 9, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {50, 50, 50, 50, 0, 0, 0, 0 +#ifdef ARCH_CV182X + , 1088, 1088, 1088, 1088 +#endif + }, + .stAuto = { + {50, 50, 50, 50, 50, 50, 50, 50, /*8*/50, 50, 50, 50, 50, 50, 50, 50}, + {50, 50, 50, 50, 50, 50, 50, 50, /*8*/50, 50, 50, 50, 50, 50, 50, 50}, + {50, 50, 50, 50, 50, 50, 50, 50, /*8*/50, 50, 50, 50, 50, 50, 50, 50}, + {50, 50, 50, 50, 50, 50, 50, 50, /*8*/50, 50, 50, 50, 50, 50, 50, 50}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1089, 1089, 1089, 1089, 1088, 1088, 1088, 1088, + /*8*/1085, 1084, 1098, 1122, 1204, 1365, 1365, 1365}, + {1089, 1089, 1089, 1089, 1088, 1088, 1088, 1088, + /*8*/1085, 1084, 1098, 1122, 1204, 1365, 1365, 1365}, + {1089, 1089, 1089, 1089, 1088, 1088, 1088, 1088, + /*8*/1085, 1084, 1098, 1122, 1204, 1365, 1365, 1365}, + {1089, 1089, 1089, 1089, 1088, 1088, 1088, 1088, + /*8*/1085, 1084, 1098, 1122, 1204, 1365, 1365, 1365}, +#endif + }, + }, +}; + +struct combo_dev_attr_s imx675_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_400M, //400 for linear 500 for wdr25 + .mipi_attr = { + .raw_data_type = RAW_DATA_12BIT, + .lane_id = {0, 1, 2, 3, 4}, + .pn_swap = {1, 1, 1, 1, 1}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + .dphy = { + .enable = 1, + .hs_settle = 14, + }, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_27M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __IMX675_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_sensor_ctl.c new file mode 100644 index 000000000..338603173 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv182x/sony_imx675/imx675_sensor_ctl.c @@ -0,0 +1,700 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "imx675_cmos_ex.h" + +static void imx675_linear_5M30_init(VI_PIPE ViPipe); +static void imx675_wdr_5M25_2to1_init(VI_PIPE ViPipe); + +const CVI_U8 imx675_i2c_addr = 0x1A; +const CVI_U32 imx675_addr_byte = 2; +const CVI_U32 imx675_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int imx675_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunImx675_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, imx675_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int imx675_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int imx675_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (imx675_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, imx675_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, imx675_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (imx675_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int imx675_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (imx675_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + + if (imx675_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, imx675_addr_byte + imx675_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void imx675_standby(VI_PIPE ViPipe) +{ + imx675_write_register(ViPipe, 0x3000, 0x01); /* STANDBY */ + imx675_write_register(ViPipe, 0x3002, 0x01); /* XTMSTA */ +} + +void imx675_restart(VI_PIPE ViPipe) +{ + imx675_write_register(ViPipe, 0x3000, 0x00); /* standby */ + delay_ms(20); + imx675_write_register(ViPipe, 0x3002, 0x00); /* master mode start */ +} + +void imx675_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastImx675[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + imx675_write_register(ViPipe, + g_pastImx675[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastImx675[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +void imx675_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 flip, mirror; + + flip = imx675_read_register(ViPipe, 0x3021); + mirror = imx675_read_register(ViPipe, 0x3020); + + flip &= ~0x1; + mirror &= ~0x1; + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + break; + case ISP_SNS_MIRROR: + mirror |= 0x1; + break; + case ISP_SNS_FLIP: + flip |= 0x1; + break; + case ISP_SNS_MIRROR_FLIP: + mirror |= 0x1; + flip |= 0x1; + break; + default: + return; + } + + imx675_write_register(ViPipe, 0x3021, flip); + imx675_write_register(ViPipe, 0x3020, mirror); +} + +#define IMX675_CHIP_ID_ADDR_1 0x4d13 +#define IMX675_CHIP_ID_ADDR_2 0x4d12 +#define IMX675_CHIP_ID 0x576 + +int imx675_probe(VI_PIPE ViPipe) +{ + int nVal_1; + int nVal_2; + + delay_ms(1); //waitting i2c stable + if (imx675_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + imx675_write_register(ViPipe, 0x3000, 0x00); + delay_ms(80); //registers become accessible after waiting 80 ms after standby cancel (STANDBY= 0) + + nVal_1 = imx675_read_register(ViPipe, IMX675_CHIP_ID_ADDR_1); + nVal_2 = imx675_read_register(ViPipe, IMX675_CHIP_ID_ADDR_2); + + if (nVal_1 < 0 || nVal_2 < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error\n"); + return nVal_1; + } + + if ((((nVal_1 & 0xFF) << 8) | (nVal_2 & 0xFF)) != IMX675_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +void imx675_init(VI_PIPE ViPipe) +{ + WDR_MODE_E enWDRMode; + CVI_U8 u8ImgMode; + + enWDRMode = g_pastImx675[ViPipe]->enWDRMode; + u8ImgMode = g_pastImx675[ViPipe]->u8ImgMode; + + delay_ms(1); //waitting i2c stable + if (imx675_i2c_init(ViPipe) != CVI_SUCCESS) { + return ; + } + + if (enWDRMode == WDR_MODE_2To1_LINE) { + if (u8ImgMode == IMX675_MODE_5M25_WDR) { + imx675_wdr_5M25_2to1_init(ViPipe); + } + } else { + imx675_linear_5M30_init(ViPipe); + } + g_pastImx675[ViPipe]->bInit = CVI_TRUE; +} + +void imx675_exit(VI_PIPE ViPipe) +{ + imx675_i2c_exit(ViPipe); +} + +static void imx675_linear_5M30_init(VI_PIPE ViPipe) +{ + delay_ms(4); + + imx675_write_register(ViPipe, 0X3000, 0X01); //STANDBY + imx675_write_register(ViPipe, 0X3001, 0X00); //REGHOLD + imx675_write_register(ViPipe, 0X3002, 0X01); //XMSTA + imx675_write_register(ViPipe, 0X3014, 0X03); //INCK_SEL[3:0] 3:27 1:37.125 + imx675_write_register(ViPipe, 0X3015, 0X04); //DATARATE_SEL[3:0] + imx675_write_register(ViPipe, 0X3018, 0X00); //WINMODE[3:0] + imx675_write_register(ViPipe, 0X3019, 0X00); //CFMODE + imx675_write_register(ViPipe, 0X301A, 0X00); //WDMODE[7:0] + imx675_write_register(ViPipe, 0X301B, 0X00); //ADDMODE[1:0] + imx675_write_register(ViPipe, 0X301C, 0X00); //THIN_V_EN[7:0] + imx675_write_register(ViPipe, 0X301E, 0X01); //VCMODE[7:0] + imx675_write_register(ViPipe, 0X3020, 0X00); //HREVERSE + imx675_write_register(ViPipe, 0X3021, 0X00); //VREVERSE + imx675_write_register(ViPipe, 0X3022, 0X01); //ADBIT[1:0] + imx675_write_register(ViPipe, 0X3023, 0X01); //MDBIT + imx675_write_register(ViPipe, 0X3028, 0X52); //VMAX[19:0] + imx675_write_register(ViPipe, 0X3029, 0X0E); //VMAX[19:0] + imx675_write_register(ViPipe, 0X302A, 0X00); //VMAX[19:0] + imx675_write_register(ViPipe, 0X302C, 0XA3); //HMAX[15:0] + imx675_write_register(ViPipe, 0X302D, 0X02); //HMAX[15:0] + imx675_write_register(ViPipe, 0X3030, 0X00); //FDG_SEL0[1:0] + imx675_write_register(ViPipe, 0X3031, 0X00); //FDG_SEL1[1:0] + imx675_write_register(ViPipe, 0X3032, 0X00); //FDG_SEL2[1:0] + imx675_write_register(ViPipe, 0X303C, 0X00); //PIX_HST[12:0] + imx675_write_register(ViPipe, 0X303D, 0X00); //PIX_HST[12:0] + imx675_write_register(ViPipe, 0X303E, 0X30); //PIX_HWIDTH[12:0] + imx675_write_register(ViPipe, 0X303F, 0X0A); //PIX_HWIDTH[12:0] + imx675_write_register(ViPipe, 0X3040, 0X03); //LANEMODE[2:0] + imx675_write_register(ViPipe, 0X3044, 0X00); //PIX_VST[11:0] + imx675_write_register(ViPipe, 0X3045, 0X00); //PIX_VST[11:0] + imx675_write_register(ViPipe, 0X3046, 0XAC); //PIX_VWIDTH[11:0] + imx675_write_register(ViPipe, 0X3047, 0X07); //PIX_VWIDTH[11:0] + imx675_write_register(ViPipe, 0X304C, 0X00); //GAIN_HG0[10:0] + imx675_write_register(ViPipe, 0X304D, 0X00); //GAIN_HG0[10:0] + imx675_write_register(ViPipe, 0X3050, 0X04); //SHR0[19:0] + imx675_write_register(ViPipe, 0X3051, 0X00); //SHR0[19:0] + imx675_write_register(ViPipe, 0X3052, 0X00); //SHR0[19:0] + imx675_write_register(ViPipe, 0X3054, 0X93); //SHR1[19:0] + imx675_write_register(ViPipe, 0X3055, 0X00); //SHR1[19:0] + imx675_write_register(ViPipe, 0X3056, 0X00); //SHR1[19:0] + imx675_write_register(ViPipe, 0X3058, 0X53); //SHR2[19:0] + imx675_write_register(ViPipe, 0X3059, 0X00); //SHR2[19:0] + imx675_write_register(ViPipe, 0X305A, 0X00); //SHR2[19:0] + imx675_write_register(ViPipe, 0X3060, 0X95); //RHS1[19:0] + imx675_write_register(ViPipe, 0X3061, 0X00); //RHS1[19:0] + imx675_write_register(ViPipe, 0X3062, 0X00); //RHS1[19:0] + imx675_write_register(ViPipe, 0X3064, 0X56); //RHS2[19:0] + imx675_write_register(ViPipe, 0X3065, 0X00); //RHS2[19:0] + imx675_write_register(ViPipe, 0X3066, 0X00); //RHS2[19:0] + imx675_write_register(ViPipe, 0X3070, 0X00); //GAIN_0[10:0] + imx675_write_register(ViPipe, 0X3071, 0X00); //GAIN_0[10:0] + imx675_write_register(ViPipe, 0X3072, 0X00); //GAIN_1[10:0] + imx675_write_register(ViPipe, 0X3073, 0X00); //GAIN_1[10:0] + imx675_write_register(ViPipe, 0X3074, 0X00); //GAIN_2[10:0] + imx675_write_register(ViPipe, 0X3075, 0X00); //GAIN_2[10:0] + imx675_write_register(ViPipe, 0X30A4, 0XAA); //XVSOUTSEL[1:0] + imx675_write_register(ViPipe, 0X30A6, 0X00); //XVS_DRV[1:0] + imx675_write_register(ViPipe, 0X30CC, 0X00); + imx675_write_register(ViPipe, 0X30CD, 0X00); + imx675_write_register(ViPipe, 0X30CE, 0X02); + imx675_write_register(ViPipe, 0X30DC, 0X32); //BLKLEVEL[9:0] + imx675_write_register(ViPipe, 0X30DD, 0X40); //BLKLEVEL[9:0] + imx675_write_register(ViPipe, 0X310C, 0X01); + imx675_write_register(ViPipe, 0X3130, 0X01); + imx675_write_register(ViPipe, 0X3148, 0X00); + imx675_write_register(ViPipe, 0X315E, 0X10); + imx675_write_register(ViPipe, 0X3400, 0X01); //GAIN_PGC_FIDMD + imx675_write_register(ViPipe, 0X3460, 0X22); + imx675_write_register(ViPipe, 0X347B, 0X02); + imx675_write_register(ViPipe, 0X3492, 0X08); + imx675_write_register(ViPipe, 0X3890, 0X08); //HFR_EN[3:0] + imx675_write_register(ViPipe, 0X3891, 0X00); //HFR_EN[3:0] + imx675_write_register(ViPipe, 0X3893, 0X00); + imx675_write_register(ViPipe, 0X3B1D, 0X17); + imx675_write_register(ViPipe, 0X3B44, 0X3F); + imx675_write_register(ViPipe, 0X3B60, 0X03); + imx675_write_register(ViPipe, 0X3C03, 0X04); + imx675_write_register(ViPipe, 0X3C04, 0X04); + imx675_write_register(ViPipe, 0X3C0A, 0X1F); + imx675_write_register(ViPipe, 0X3C0B, 0X1F); + imx675_write_register(ViPipe, 0X3C0C, 0X1F); + imx675_write_register(ViPipe, 0X3C0D, 0X1F); + imx675_write_register(ViPipe, 0X3C0E, 0X1F); + imx675_write_register(ViPipe, 0X3C0F, 0X1F); + imx675_write_register(ViPipe, 0X3C30, 0X73); + imx675_write_register(ViPipe, 0X3C3C, 0X20); + imx675_write_register(ViPipe, 0X3C44, 0X06); + imx675_write_register(ViPipe, 0X3C7C, 0XB9); + imx675_write_register(ViPipe, 0X3C7D, 0X01); + imx675_write_register(ViPipe, 0X3C7E, 0XB7); + imx675_write_register(ViPipe, 0X3C7F, 0X01); + imx675_write_register(ViPipe, 0X3CB0, 0X00); + imx675_write_register(ViPipe, 0X3CB2, 0XFF); + imx675_write_register(ViPipe, 0X3CB3, 0X03); + imx675_write_register(ViPipe, 0X3CB4, 0XFF); + imx675_write_register(ViPipe, 0X3CB5, 0X03); + imx675_write_register(ViPipe, 0X3CBA, 0XFF); + imx675_write_register(ViPipe, 0X3CBB, 0X03); + imx675_write_register(ViPipe, 0X3CC0, 0XFF); + imx675_write_register(ViPipe, 0X3CC1, 0X03); + imx675_write_register(ViPipe, 0X3CC2, 0X00); + imx675_write_register(ViPipe, 0X3CC6, 0XFF); + imx675_write_register(ViPipe, 0X3CC7, 0X03); + imx675_write_register(ViPipe, 0X3CC8, 0XFF); + imx675_write_register(ViPipe, 0X3CC9, 0X03); + imx675_write_register(ViPipe, 0X3E00, 0X1E); + imx675_write_register(ViPipe, 0X3E02, 0X04); + imx675_write_register(ViPipe, 0X3E03, 0X00); + imx675_write_register(ViPipe, 0X3E20, 0X04); + imx675_write_register(ViPipe, 0X3E21, 0X00); + imx675_write_register(ViPipe, 0X3E22, 0X1E); + imx675_write_register(ViPipe, 0X3E24, 0XBA); + imx675_write_register(ViPipe, 0X3E72, 0X85); + imx675_write_register(ViPipe, 0X3E76, 0X0C); + imx675_write_register(ViPipe, 0X3E77, 0X01); + imx675_write_register(ViPipe, 0X3E7A, 0X85); + imx675_write_register(ViPipe, 0X3E7E, 0X1F); + imx675_write_register(ViPipe, 0X3E82, 0XA6); + imx675_write_register(ViPipe, 0X3E86, 0X2D); + imx675_write_register(ViPipe, 0X3EE2, 0X33); + imx675_write_register(ViPipe, 0X3EE3, 0X03); + imx675_write_register(ViPipe, 0X4490, 0X07); + imx675_write_register(ViPipe, 0X4494, 0X19); + imx675_write_register(ViPipe, 0X4495, 0X00); + imx675_write_register(ViPipe, 0X4496, 0XBB); + imx675_write_register(ViPipe, 0X4497, 0X00); + imx675_write_register(ViPipe, 0X4498, 0X55); + imx675_write_register(ViPipe, 0X449A, 0X50); + imx675_write_register(ViPipe, 0X449C, 0X50); + imx675_write_register(ViPipe, 0X449E, 0X50); + imx675_write_register(ViPipe, 0X44A0, 0X3C); + imx675_write_register(ViPipe, 0X44A2, 0X19); + imx675_write_register(ViPipe, 0X44A4, 0X19); + imx675_write_register(ViPipe, 0X44A6, 0X19); + imx675_write_register(ViPipe, 0X44A8, 0X4B); + imx675_write_register(ViPipe, 0X44AA, 0X4B); + imx675_write_register(ViPipe, 0X44AC, 0X4B); + imx675_write_register(ViPipe, 0X44AE, 0X4B); + imx675_write_register(ViPipe, 0X44B0, 0X3C); + imx675_write_register(ViPipe, 0X44B2, 0X19); + imx675_write_register(ViPipe, 0X44B4, 0X19); + imx675_write_register(ViPipe, 0X44B6, 0X19); + imx675_write_register(ViPipe, 0X44B8, 0X4B); + imx675_write_register(ViPipe, 0X44BA, 0X4B); + imx675_write_register(ViPipe, 0X44BC, 0X4B); + imx675_write_register(ViPipe, 0X44BE, 0X4B); + imx675_write_register(ViPipe, 0X44C0, 0X3C); + imx675_write_register(ViPipe, 0X44C2, 0X19); + imx675_write_register(ViPipe, 0X44C4, 0X19); + imx675_write_register(ViPipe, 0X44C6, 0X19); + imx675_write_register(ViPipe, 0X44C8, 0XF0); + imx675_write_register(ViPipe, 0X44CA, 0XEB); + imx675_write_register(ViPipe, 0X44CC, 0XEB); + imx675_write_register(ViPipe, 0X44CE, 0XE6); + imx675_write_register(ViPipe, 0X44D0, 0XE6); + imx675_write_register(ViPipe, 0X44D2, 0XBB); + imx675_write_register(ViPipe, 0X44D4, 0XBB); + imx675_write_register(ViPipe, 0X44D6, 0XBB); + imx675_write_register(ViPipe, 0X44D8, 0XE6); + imx675_write_register(ViPipe, 0X44DA, 0XE6); + imx675_write_register(ViPipe, 0X44DC, 0XE6); + imx675_write_register(ViPipe, 0X44DE, 0XE6); + imx675_write_register(ViPipe, 0X44E0, 0XE6); + imx675_write_register(ViPipe, 0X44E2, 0XBB); + imx675_write_register(ViPipe, 0X44E4, 0XBB); + imx675_write_register(ViPipe, 0X44E6, 0XBB); + imx675_write_register(ViPipe, 0X44E8, 0XE6); + imx675_write_register(ViPipe, 0X44EA, 0XE6); + imx675_write_register(ViPipe, 0X44EC, 0XE6); + imx675_write_register(ViPipe, 0X44EE, 0XE6); + imx675_write_register(ViPipe, 0X44F0, 0XE6); + imx675_write_register(ViPipe, 0X44F2, 0XBB); + imx675_write_register(ViPipe, 0X44F4, 0XBB); + imx675_write_register(ViPipe, 0X44F6, 0XBB); + imx675_write_register(ViPipe, 0X4538, 0X15); + imx675_write_register(ViPipe, 0X4539, 0X15); + imx675_write_register(ViPipe, 0X453A, 0X15); + imx675_write_register(ViPipe, 0X4544, 0X15); + imx675_write_register(ViPipe, 0X4545, 0X15); + imx675_write_register(ViPipe, 0X4546, 0X15); + imx675_write_register(ViPipe, 0X4550, 0X10); + imx675_write_register(ViPipe, 0X4551, 0X10); + imx675_write_register(ViPipe, 0X4552, 0X10); + imx675_write_register(ViPipe, 0X4553, 0X10); + imx675_write_register(ViPipe, 0X4554, 0X10); + imx675_write_register(ViPipe, 0X4555, 0X10); + imx675_write_register(ViPipe, 0X4556, 0X10); + imx675_write_register(ViPipe, 0X4557, 0X10); + imx675_write_register(ViPipe, 0X4558, 0X10); + imx675_write_register(ViPipe, 0X455C, 0X10); + imx675_write_register(ViPipe, 0X455D, 0X10); + imx675_write_register(ViPipe, 0X455E, 0X10); + imx675_write_register(ViPipe, 0X455F, 0X10); + imx675_write_register(ViPipe, 0X4560, 0X10); + imx675_write_register(ViPipe, 0X4561, 0X10); + imx675_write_register(ViPipe, 0X4562, 0X10); + imx675_write_register(ViPipe, 0X4563, 0X10); + imx675_write_register(ViPipe, 0X4564, 0X10); + imx675_write_register(ViPipe, 0X4569, 0X01); + imx675_write_register(ViPipe, 0X456A, 0X01); + imx675_write_register(ViPipe, 0X456B, 0X06); + imx675_write_register(ViPipe, 0X456C, 0X06); + imx675_write_register(ViPipe, 0X456D, 0X06); + imx675_write_register(ViPipe, 0X456E, 0X06); + imx675_write_register(ViPipe, 0X456F, 0X06); + imx675_write_register(ViPipe, 0X4570, 0X06); + + imx675_default_reg_init(ViPipe); + + imx675_write_register(ViPipe, 0x3000, 0x00); /* standby */ + delay_ms(80); + + imx675_write_register(ViPipe, 0x3002, 0x00); /* master mode start */ + + printf("ViPipe:%d,===IMX675 5M30fps 12bit LINE Init OK!===\n", ViPipe); +} + +//25fps 1440Mbps vmax 2200 +static void imx675_wdr_5M25_2to1_init(VI_PIPE ViPipe) +{ + delay_ms(4); + + imx675_write_register(ViPipe, 0X3000, 0X01); //STANDBY + imx675_write_register(ViPipe, 0X3001, 0X00); //REGHOLD + imx675_write_register(ViPipe, 0X3002, 0X01); //XMSTA + imx675_write_register(ViPipe, 0X3014, 0X03); //INCK_SEL[3:0] + imx675_write_register(ViPipe, 0X3015, 0X03); //DATARATE_SEL[3:0] + imx675_write_register(ViPipe, 0X3018, 0X00); //WINMODE[3:0] + imx675_write_register(ViPipe, 0X3019, 0X00); //CFMODE + imx675_write_register(ViPipe, 0X301A, 0X01); //WDMODE[7:0] + imx675_write_register(ViPipe, 0X301B, 0X00); //ADDMODE[1:0] + imx675_write_register(ViPipe, 0X301C, 0X01); //THIN_V_EN[7:0] + imx675_write_register(ViPipe, 0X301E, 0X01); //VCMODE[7:0] + imx675_write_register(ViPipe, 0X3020, 0X00); //HREVERSE + imx675_write_register(ViPipe, 0X3021, 0X00); //VREVERSE + imx675_write_register(ViPipe, 0X3022, 0X01); //ADBIT[1:0] + imx675_write_register(ViPipe, 0X3023, 0X01); //MDBIT + imx675_write_register(ViPipe, 0X3028, 0X98); //VMAX[19:0] + imx675_write_register(ViPipe, 0X3029, 0X08); //VMAX[19:0] + imx675_write_register(ViPipe, 0X302A, 0X00); //VMAX[19:0] + imx675_write_register(ViPipe, 0X302C, 0XA3); //HMAX[15:0] + imx675_write_register(ViPipe, 0X302D, 0X02); //HMAX[15:0] + imx675_write_register(ViPipe, 0X3030, 0X00); //FDG_SEL0[1:0] + imx675_write_register(ViPipe, 0X3031, 0X00); //FDG_SEL1[1:0] + imx675_write_register(ViPipe, 0X3032, 0X00); //FDG_SEL2[1:0] + imx675_write_register(ViPipe, 0X303C, 0X00); //PIX_HST[12:0] + imx675_write_register(ViPipe, 0X303D, 0X00); //PIX_HST[12:0] + imx675_write_register(ViPipe, 0X303E, 0X30); //PIX_HWIDTH[12:0] + imx675_write_register(ViPipe, 0X303F, 0X0A); //PIX_HWIDTH[12:0] + imx675_write_register(ViPipe, 0X3040, 0X03); //LANEMODE[2:0] + imx675_write_register(ViPipe, 0X3044, 0X00); //PIX_VST[11:0] + imx675_write_register(ViPipe, 0X3045, 0X00); //PIX_VST[11:0] + imx675_write_register(ViPipe, 0X3046, 0XAC); //PIX_VWIDTH[11:0] + imx675_write_register(ViPipe, 0X3047, 0X07); //PIX_VWIDTH[11:0] + imx675_write_register(ViPipe, 0X304C, 0X00); //GAIN_HG0[10:0] + imx675_write_register(ViPipe, 0X304D, 0X00); //GAIN_HG0[10:0] + imx675_write_register(ViPipe, 0X3050, 0X50); //SHR0[19:0] + imx675_write_register(ViPipe, 0X3051, 0X0A); //SHR0[19:0] + imx675_write_register(ViPipe, 0X3052, 0X00); //SHR0[19:0] + imx675_write_register(ViPipe, 0X3054, 0X05); //SHR1[19:0] + imx675_write_register(ViPipe, 0X3055, 0X00); //SHR1[19:0] + imx675_write_register(ViPipe, 0X3056, 0X00); //SHR1[19:0] + imx675_write_register(ViPipe, 0X3058, 0X53); //SHR2[19:0] + imx675_write_register(ViPipe, 0X3059, 0X00); //SHR2[19:0] + imx675_write_register(ViPipe, 0X305A, 0X00); //SHR2[19:0] + imx675_write_register(ViPipe, 0X3060, 0X75); //RHS1[19:0] + imx675_write_register(ViPipe, 0X3061, 0X00); //RHS1[19:0] + imx675_write_register(ViPipe, 0X3062, 0X00); //RHS1[19:0] + imx675_write_register(ViPipe, 0X3064, 0X56); //RHS2[19:0] + imx675_write_register(ViPipe, 0X3065, 0X00); //RHS2[19:0] + imx675_write_register(ViPipe, 0X3066, 0X00); //RHS2[19:0] + imx675_write_register(ViPipe, 0X3070, 0X00); //GAIN_0[10:0] + imx675_write_register(ViPipe, 0X3071, 0X00); //GAIN_0[10:0] + imx675_write_register(ViPipe, 0X3072, 0X00); //GAIN_1[10:0] + imx675_write_register(ViPipe, 0X3073, 0X00); //GAIN_1[10:0] + imx675_write_register(ViPipe, 0X3074, 0X00); //GAIN_2[10:0] + imx675_write_register(ViPipe, 0X3075, 0X00); //GAIN_2[10:0] + imx675_write_register(ViPipe, 0X30A4, 0XAA); //XVSOUTSEL[1:0] + imx675_write_register(ViPipe, 0X30A6, 0X00); //XVS_DRV[1:0] + imx675_write_register(ViPipe, 0X30CC, 0X00); + imx675_write_register(ViPipe, 0X30CD, 0X00); + imx675_write_register(ViPipe, 0X30CE, 0X02); + imx675_write_register(ViPipe, 0X30DC, 0X32); //BLKLEVEL[9:0] + imx675_write_register(ViPipe, 0X30DD, 0X40); //BLKLEVEL[9:0] + imx675_write_register(ViPipe, 0X310C, 0X01); + imx675_write_register(ViPipe, 0X3130, 0X01); + imx675_write_register(ViPipe, 0X3148, 0X00); + imx675_write_register(ViPipe, 0X315E, 0X10); + imx675_write_register(ViPipe, 0X3400, 0X01); //GAIN_PGC_FIDMD + imx675_write_register(ViPipe, 0X3460, 0X22); + imx675_write_register(ViPipe, 0X347B, 0X02); + imx675_write_register(ViPipe, 0X3492, 0X08); + imx675_write_register(ViPipe, 0X3890, 0X08); //HFR_EN[3:0] + imx675_write_register(ViPipe, 0X3891, 0X00); //HFR_EN[3:0] + imx675_write_register(ViPipe, 0X3893, 0X00); + imx675_write_register(ViPipe, 0X3B1D, 0X17); + imx675_write_register(ViPipe, 0X3B44, 0X3F); + imx675_write_register(ViPipe, 0X3B60, 0X03); + imx675_write_register(ViPipe, 0X3C03, 0X04); + imx675_write_register(ViPipe, 0X3C04, 0X04); + imx675_write_register(ViPipe, 0X3C0A, 0X1F); + imx675_write_register(ViPipe, 0X3C0B, 0X1F); + imx675_write_register(ViPipe, 0X3C0C, 0X1F); + imx675_write_register(ViPipe, 0X3C0D, 0X1F); + imx675_write_register(ViPipe, 0X3C0E, 0X1F); + imx675_write_register(ViPipe, 0X3C0F, 0X1F); + imx675_write_register(ViPipe, 0X3C30, 0X73); + imx675_write_register(ViPipe, 0X3C3C, 0X20); + imx675_write_register(ViPipe, 0X3C44, 0X06); + imx675_write_register(ViPipe, 0X3C7C, 0XB9); + imx675_write_register(ViPipe, 0X3C7D, 0X01); + imx675_write_register(ViPipe, 0X3C7E, 0XB7); + imx675_write_register(ViPipe, 0X3C7F, 0X01); + imx675_write_register(ViPipe, 0X3CB0, 0X00); + imx675_write_register(ViPipe, 0X3CB2, 0XFF); + imx675_write_register(ViPipe, 0X3CB3, 0X03); + imx675_write_register(ViPipe, 0X3CB4, 0XFF); + imx675_write_register(ViPipe, 0X3CB5, 0X03); + imx675_write_register(ViPipe, 0X3CBA, 0XFF); + imx675_write_register(ViPipe, 0X3CBB, 0X03); + imx675_write_register(ViPipe, 0X3CC0, 0XFF); + imx675_write_register(ViPipe, 0X3CC1, 0X03); + imx675_write_register(ViPipe, 0X3CC2, 0X00); + imx675_write_register(ViPipe, 0X3CC6, 0XFF); + imx675_write_register(ViPipe, 0X3CC7, 0X03); + imx675_write_register(ViPipe, 0X3CC8, 0XFF); + imx675_write_register(ViPipe, 0X3CC9, 0X03); + imx675_write_register(ViPipe, 0X3E00, 0X1E); + imx675_write_register(ViPipe, 0X3E02, 0X04); + imx675_write_register(ViPipe, 0X3E03, 0X00); + imx675_write_register(ViPipe, 0X3E20, 0X04); + imx675_write_register(ViPipe, 0X3E21, 0X00); + imx675_write_register(ViPipe, 0X3E22, 0X1E); + imx675_write_register(ViPipe, 0X3E24, 0XBA); + imx675_write_register(ViPipe, 0X3E72, 0X85); + imx675_write_register(ViPipe, 0X3E76, 0X0C); + imx675_write_register(ViPipe, 0X3E77, 0X01); + imx675_write_register(ViPipe, 0X3E7A, 0X85); + imx675_write_register(ViPipe, 0X3E7E, 0X1F); + imx675_write_register(ViPipe, 0X3E82, 0XA6); + imx675_write_register(ViPipe, 0X3E86, 0X2D); + imx675_write_register(ViPipe, 0X3EE2, 0X33); + imx675_write_register(ViPipe, 0X3EE3, 0X03); + imx675_write_register(ViPipe, 0X4490, 0X07); + imx675_write_register(ViPipe, 0X4494, 0X19); + imx675_write_register(ViPipe, 0X4495, 0X00); + imx675_write_register(ViPipe, 0X4496, 0XBB); + imx675_write_register(ViPipe, 0X4497, 0X00); + imx675_write_register(ViPipe, 0X4498, 0X55); + imx675_write_register(ViPipe, 0X449A, 0X50); + imx675_write_register(ViPipe, 0X449C, 0X50); + imx675_write_register(ViPipe, 0X449E, 0X50); + imx675_write_register(ViPipe, 0X44A0, 0X3C); + imx675_write_register(ViPipe, 0X44A2, 0X19); + imx675_write_register(ViPipe, 0X44A4, 0X19); + imx675_write_register(ViPipe, 0X44A6, 0X19); + imx675_write_register(ViPipe, 0X44A8, 0X4B); + imx675_write_register(ViPipe, 0X44AA, 0X4B); + imx675_write_register(ViPipe, 0X44AC, 0X4B); + imx675_write_register(ViPipe, 0X44AE, 0X4B); + imx675_write_register(ViPipe, 0X44B0, 0X3C); + imx675_write_register(ViPipe, 0X44B2, 0X19); + imx675_write_register(ViPipe, 0X44B4, 0X19); + imx675_write_register(ViPipe, 0X44B6, 0X19); + imx675_write_register(ViPipe, 0X44B8, 0X4B); + imx675_write_register(ViPipe, 0X44BA, 0X4B); + imx675_write_register(ViPipe, 0X44BC, 0X4B); + imx675_write_register(ViPipe, 0X44BE, 0X4B); + imx675_write_register(ViPipe, 0X44C0, 0X3C); + imx675_write_register(ViPipe, 0X44C2, 0X19); + imx675_write_register(ViPipe, 0X44C4, 0X19); + imx675_write_register(ViPipe, 0X44C6, 0X19); + imx675_write_register(ViPipe, 0X44C8, 0XF0); + imx675_write_register(ViPipe, 0X44CA, 0XEB); + imx675_write_register(ViPipe, 0X44CC, 0XEB); + imx675_write_register(ViPipe, 0X44CE, 0XE6); + imx675_write_register(ViPipe, 0X44D0, 0XE6); + imx675_write_register(ViPipe, 0X44D2, 0XBB); + imx675_write_register(ViPipe, 0X44D4, 0XBB); + imx675_write_register(ViPipe, 0X44D6, 0XBB); + imx675_write_register(ViPipe, 0X44D8, 0XE6); + imx675_write_register(ViPipe, 0X44DA, 0XE6); + imx675_write_register(ViPipe, 0X44DC, 0XE6); + imx675_write_register(ViPipe, 0X44DE, 0XE6); + imx675_write_register(ViPipe, 0X44E0, 0XE6); + imx675_write_register(ViPipe, 0X44E2, 0XBB); + imx675_write_register(ViPipe, 0X44E4, 0XBB); + imx675_write_register(ViPipe, 0X44E6, 0XBB); + imx675_write_register(ViPipe, 0X44E8, 0XE6); + imx675_write_register(ViPipe, 0X44EA, 0XE6); + imx675_write_register(ViPipe, 0X44EC, 0XE6); + imx675_write_register(ViPipe, 0X44EE, 0XE6); + imx675_write_register(ViPipe, 0X44F0, 0XE6); + imx675_write_register(ViPipe, 0X44F2, 0XBB); + imx675_write_register(ViPipe, 0X44F4, 0XBB); + imx675_write_register(ViPipe, 0X44F6, 0XBB); + imx675_write_register(ViPipe, 0X4538, 0X15); + imx675_write_register(ViPipe, 0X4539, 0X15); + imx675_write_register(ViPipe, 0X453A, 0X15); + imx675_write_register(ViPipe, 0X4544, 0X15); + imx675_write_register(ViPipe, 0X4545, 0X15); + imx675_write_register(ViPipe, 0X4546, 0X15); + imx675_write_register(ViPipe, 0X4550, 0X10); + imx675_write_register(ViPipe, 0X4551, 0X10); + imx675_write_register(ViPipe, 0X4552, 0X10); + imx675_write_register(ViPipe, 0X4553, 0X10); + imx675_write_register(ViPipe, 0X4554, 0X10); + imx675_write_register(ViPipe, 0X4555, 0X10); + imx675_write_register(ViPipe, 0X4556, 0X10); + imx675_write_register(ViPipe, 0X4557, 0X10); + imx675_write_register(ViPipe, 0X4558, 0X10); + imx675_write_register(ViPipe, 0X455C, 0X10); + imx675_write_register(ViPipe, 0X455D, 0X10); + imx675_write_register(ViPipe, 0X455E, 0X10); + imx675_write_register(ViPipe, 0X455F, 0X10); + imx675_write_register(ViPipe, 0X4560, 0X10); + imx675_write_register(ViPipe, 0X4561, 0X10); + imx675_write_register(ViPipe, 0X4562, 0X10); + imx675_write_register(ViPipe, 0X4563, 0X10); + imx675_write_register(ViPipe, 0X4564, 0X10); + imx675_write_register(ViPipe, 0X4569, 0X01); + imx675_write_register(ViPipe, 0X456A, 0X01); + imx675_write_register(ViPipe, 0X456B, 0X06); + imx675_write_register(ViPipe, 0X456C, 0X06); + imx675_write_register(ViPipe, 0X456D, 0X06); + imx675_write_register(ViPipe, 0X456E, 0X06); + imx675_write_register(ViPipe, 0X456F, 0X06); + imx675_write_register(ViPipe, 0X4570, 0X06); + + imx675_default_reg_init(ViPipe); + + imx675_write_register(ViPipe, 0x3000, 0x00); /* standby */ + delay_ms(80); + imx675_write_register(ViPipe, 0x3002, 0x00); /* master mode start */ + + printf("ViPipe:%d,===Imx675 5M25fps 12bit 2to1 WDR Init Ok!====\n", ViPipe); +} \ No newline at end of file