diff --git a/middleware/v2/modules/gdc/include/gdc_ctx.h b/middleware/v2/modules/gdc/include/gdc_ctx.h new file mode 100644 index 000000000..efb9dd0d5 --- /dev/null +++ b/middleware/v2/modules/gdc/include/gdc_ctx.h @@ -0,0 +1,11 @@ +#ifndef __GDC_CTX_H_ +#define __GDC_CTX_H_ + +#include +#include "cvi_base.h" + +extern struct cvi_gdc_mesh mesh[VPSS_MAX_GRP_NUM][VPSS_MAX_CHN_NUM]; +extern struct cvi_gdc_mesh g_vi_mesh[VI_MAX_CHN_NUM]; +extern struct cvi_vi_ctx *gViCtx; + +#endif /* __GDC_CTX_H_ */ \ No newline at end of file diff --git a/middleware/v2/modules/gdc/include/gdc_mesh.h b/middleware/v2/modules/gdc/include/gdc_mesh.h new file mode 100644 index 000000000..91fed110b --- /dev/null +++ b/middleware/v2/modules/gdc/include/gdc_mesh.h @@ -0,0 +1,123 @@ +/* + * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved. + * + * File Name: module/vpu/include/gdc_mesh.h + * Description: + * GDC's mesh generator for hw. + */ + +#ifndef __GDC_MESH_H_ +#define __GDC_MESH_H_ + +#define CVI_GDC_MAGIC 0xbabeface + +#define CVI_GDC_MESH_SIZE_ROT 0x60000 +#define CVI_GDC_MESH_SIZE_AFFINE 0x20000 +#define CVI_GDC_MESH_SIZE_FISHEYE 0xB0000 + +enum gdc_task_type { + GDC_TASK_TYPE_ROT = 0, + GDC_TASK_TYPE_FISHEYE, + GDC_TASK_TYPE_AFFINE, + GDC_TASK_TYPE_LDC, + GDC_TASK_TYPE_MAX, +}; + +/* gdc_task_param: the gdc task. + * + * stTask: define the in/out image info. + * type: the type of gdc task. + * param: the parameters for gdc task. + */ +struct gdc_task_param { + STAILQ_ENTRY(gdc_task_param) stailq; + + GDC_TASK_ATTR_S stTask; + enum gdc_task_type type; + union { + ROTATION_E enRotation; + FISHEYE_ATTR_S stFishEyeAttr; + AFFINE_ATTR_S stAffineAttr; + LDC_ATTR_S stLDCAttr; + }; +}; + +/* gdc_job: the handle of gdc. + * + * ctx: the list of gdc task in the gdc job. + * mutex: used if this job is sync-io. + * cond: used if this job is sync-io. + * sync_io: CVI_GDC_EndJob() will blocked until done is this is true. + * only meaningful if internal module use gdc. + * Default true; + */ +struct gdc_job { + STAILQ_ENTRY(gdc_job) stailq; + + STAILQ_HEAD(gdc_job_ctx, gdc_task_param) ctx; + pthread_cond_t cond; + CVI_BOOL sync_io; +}; + +enum gdc_job_state { + GDC_JOB_SUCCESS = 0, + GDC_JOB_FAIL, + GDC_JOB_WORKING, +}; + +struct gdc_job_info { + CVI_S64 hHandle; + MOD_ID_E enModId; // the module submitted gdc job + CVI_U32 u32TaskNum; // number of tasks + enum gdc_job_state eState; // job state + CVI_U32 u32InSize; + CVI_U32 u32OutSize; + CVI_U32 u32CostTime; // From job submitted to job done + CVI_U32 u32HwTime; // HW cost time + CVI_U32 u32BusyTime; // From job submitted to job commit to driver + CVI_U64 u64SubmitTime; // us +}; + +struct gdc_job_status { + CVI_U32 u32Success; + CVI_U32 u32Fail; + CVI_U32 u32Cancel; + CVI_U32 u32BeginNum; + CVI_U32 u32BusyNum; + CVI_U32 u32ProcingNum; +}; + +struct gdc_task_status { + CVI_U32 u32Success; + CVI_U32 u32Fail; + CVI_U32 u32Cancel; + CVI_U32 u32BusyNum; +}; + +struct gdc_operation_status { + CVI_U32 u32AddTaskSuc; + CVI_U32 u32AddTaskFail; + CVI_U32 u32EndSuc; + CVI_U32 u32EndFail; + CVI_U32 u32CbCnt; +}; + +int get_mesh_size(int *p_mesh_hor, int *p_mesh_ver); +int set_mesh_size(int mesh_hor, int mesh_ver); +void mesh_gen_get_size(SIZE_S in_size, SIZE_S out_size, CVI_U32 *mesh_id_size, CVI_U32 *mesh_tbl_size); +void mesh_gen_rotation(SIZE_S in_size, SIZE_S out_size, ROTATION_E rot, uint64_t mesh_phy_addr, void *mesh_vir_addr); +void mesh_gen_affine(SIZE_S in_size, SIZE_S out_size, const AFFINE_ATTR_S *pstAffineAttr, uint64_t mesh_phy_addr, + void *mesh_vir_addr); +void mesh_gen_fisheye(SIZE_S in_size, SIZE_S out_size, const FISHEYE_ATTR_S *pstFisheyeAttr, uint64_t mesh_phy_addr, + void *mesh_vir_addr, ROTATION_E rot); +CVI_S32 mesh_gen_ldc(SIZE_S in_size, SIZE_S out_size, const LDC_ATTR_S *pstLDCAttr, + uint64_t mesh_phy_addr, void *mesh_vir_addr, ROTATION_E rot); + +// cnv +void mesh_gen_cnv(const float *pfmesh_data, SIZE_S in_size, SIZE_S out_size, const FISHEYE_ATTR_S *pstFisheyeAttr, + uint64_t mesh_phy_addr, void *mesh_vir_addr); + +void get_cnv_warp_mesh_tbl(SIZE_S in_size, SIZE_S out_size, const AFFINE_ATTR_S *pstAffineAttr, uint64_t mesh_phy_addr, + void *mesh_vir_addr); + +#endif // MODULES_VPU_INCLUDE_GDC_MESH_H_ \ No newline at end of file diff --git a/middleware/v2/modules/gdc/include/grid_info.h b/middleware/v2/modules/gdc/include/grid_info.h new file mode 100644 index 000000000..ad1828de2 --- /dev/null +++ b/middleware/v2/modules/gdc/include/grid_info.h @@ -0,0 +1,55 @@ +#ifndef __GRID_INFO_H__ +#define __GRID_INFO_H__ + +#include +#include + +#ifdef __cplusplus +#if __cplusplus + extern "C"{ +#endif +#endif /* End of #ifdef __cplusplus */ + +typedef struct _MESH_DATA_ALL_S { + char grid_name[64]; + bool balloc; + int num_pairs, imgw, imgh, node_index; + int *pgrid_src, *pgrid_dst; + int *pmesh_src, *pmesh_dst; + int *pnode_src, *pnode_dst; + int mesh_w; // unit: pixel + int mesh_h; // unit: pixel + int mesh_horcnt; // unit: mesh_w + int mesh_vercnt; // unit: mesh_h + int unit_rx; // unit: mesh_w + int unit_ry; // unit: mesh_h + //int unit_ex; // = rx + mesh_horcnt - 1 + //int unit_ey; // = ry + mesh_vercnt - 1 + int _nbr_mesh_x, _nbr_mesh_y; + bool _bhomo; + float _homography[10]; + int corners[10]; + float *_pmapx, *_pmapy; +} MESH_DATA_ALL_S; + +#define SAFE_FREE_POINTER(ptr) \ + do { \ + if (ptr != NULL) { \ + free(ptr); \ + ptr = NULL; \ + } \ + } while (0) + +typedef MESH_DATA_ALL_S meshdata_all; + +int load_meshdata(const char *path, MESH_DATA_ALL_S *pmeshdata, const char *bindName); + +int free_cur_meshdata(MESH_DATA_ALL_S *pmeshdata); + +#ifdef __cplusplus +#if __cplusplus + } +#endif +#endif /* End of #ifdef __cplusplus */ + +#endif /* __GRID_INFO_H__ */ diff --git a/middleware/v2/modules/gdc/include/ldc_ioctl.h b/middleware/v2/modules/gdc/include/ldc_ioctl.h new file mode 100644 index 000000000..c0721a548 --- /dev/null +++ b/middleware/v2/modules/gdc/include/ldc_ioctl.h @@ -0,0 +1,19 @@ +#ifndef _LDC_IOCTL_H_ +#define _LDC_IOCTL_H_ + +#include + +#include + +/* Configured from user */ +CVI_S32 gdc_begin_job(CVI_S32 fd, struct gdc_handle_data *cfg); +CVI_S32 gdc_end_job(CVI_S32 fd, struct gdc_handle_data *cfg); +CVI_S32 gdc_cancel_job(CVI_S32 fd, struct gdc_handle_data *cfg); +CVI_S32 gdc_add_rotation_task(CVI_S32 fd, struct gdc_task_attr *attr); +CVI_S32 gdc_add_ldc_task(CVI_S32 fd, struct gdc_task_attr *attr); + +/* INTERNAL */ +CVI_S32 gdc_set_chn_buf_wrap(CVI_S32 fd, const struct dwa_buf_wrap_cfg *cfg); +CVI_S32 gdc_get_chn_buf_wrap(CVI_S32 fd, struct dwa_buf_wrap_cfg *cfg); + +#endif /* _LDC_IOCTL_H_ */ \ No newline at end of file diff --git a/middleware/v2/modules/rgn/include/rgn_ioctl.h b/middleware/v2/modules/rgn/include/rgn_ioctl.h new file mode 100644 index 000000000..4f7543937 --- /dev/null +++ b/middleware/v2/modules/rgn/include/rgn_ioctl.h @@ -0,0 +1,21 @@ +#ifndef __RGN_IOCTL_H_ +#define __RGN_IOCTL_H_ + +#include +#include + +int rgn_create(int fd, int Handle, const RGN_ATTR_S *pstRegion); +int rgn_destroy(int fd, int Handle); +int rgn_get_attr(int fd, int Handle, RGN_ATTR_S *pstRegion); +int rgn_set_attr(int fd, int Handle, const RGN_ATTR_S *pstRegion); +int rgn_set_bit_map(int fd, int Handle, const BITMAP_S *pstBitmap); +int rgn_attach_to_chn(int fd, int Handle, const MMF_CHN_S *pstChn, const RGN_CHN_ATTR_S *pstChnAttr); +int rgn_detach_from_chn(int fd, int Handle, const MMF_CHN_S *pstChn); +int rgn_set_display_attr(int fd, int Handle, const MMF_CHN_S *pstChn, const RGN_CHN_ATTR_S *pstChnAttr); +int rgn_get_display_attr(int fd, int Handle, const MMF_CHN_S *pstChn, RGN_CHN_ATTR_S *pstChnAttr); +int rgn_get_canvas_info(int fd, int Handle, RGN_CANVAS_INFO_S *pstCanvasInfo); +int rgn_update_canvas(int fd, int Handle); +int rgn_invert_color(int fd, int Handle, MMF_CHN_S *pstChn, void *pu32Color); +int rgn_set_chn_palette(int fd, int Handle, const MMF_CHN_S *pstChn, RGN_PALETTE_S *pstPalette); + +#endif // __RGN_IOCTL_H_ \ No newline at end of file diff --git a/middleware/v2/modules/vi/include/dump_register.h b/middleware/v2/modules/vi/include/dump_register.h new file mode 100644 index 000000000..c08a891dc --- /dev/null +++ b/middleware/v2/modules/vi/include/dump_register.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved. + * + * File Name: module/vi/include/dump_register.h + * Description: + * dump hw register and lut for ISP module. + */ + +#ifndef __DUMP_REGISTER_H__ +#define __DUMP_REGISTER_H__ + +#include + +#ifdef __cplusplus +#if __cplusplus +extern "C" +{ +#endif +#endif /* __cplusplus */ + +CVI_S32 dump_register_182x(VI_PIPE ViPipe, FILE *fp, VI_DUMP_REGISTER_TABLE_S *pstRegTbl); +CVI_S32 dump_register_183x(VI_PIPE ViPipe, FILE *fp, VI_DUMP_REGISTER_TABLE_S *pstRegTbl); +CVI_S32 dump_hw_register(VI_PIPE ViPipe, FILE *fp, VI_DUMP_REGISTER_TABLE_S *pstRegTbl); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +#endif /*__DUMP_REGISTER_H__ */ \ No newline at end of file diff --git a/middleware/v2/modules/vi/include/vi_ioctl.h b/middleware/v2/modules/vi/include/vi_ioctl.h new file mode 100644 index 000000000..44756aed0 --- /dev/null +++ b/middleware/v2/modules/vi/include/vi_ioctl.h @@ -0,0 +1,77 @@ +#ifndef __VI_IOCTL_H_ +#define __VI_IOCTL_H_ + +#include +#include +#include +#include + +int vi_enable_usr_pic(int fd, bool enable); +int vi_set_usr_pic(int fd, struct cvi_isp_usr_pic_cfg *cfg); +int vi_put_usr_pic(int fd, CVI_U64 phyAddr); +int vi_set_usr_pic_timing(int fd, CVI_U32 fps); +int vi_set_be_online(int fd, CVI_BOOL online); +int vi_set_online(int fd, CVI_BOOL online); +int vi_set_hdr(int fd, CVI_BOOL is_hdr_on); +int vi_set_3dnr(int fd, CVI_BOOL is_3dnr_on); +int vi_get_pipe_dump(int fd, struct cvi_vip_isp_raw_blk *memAddr); +int vi_put_pipe_dump(int fd, CVI_U32 dev_num); +int vi_set_yuv_bypass_path(int fd, struct cvi_vip_isp_yuv_param *param); +int vi_set_compress_mode(int fd, CVI_BOOL is_compress_on); +int vi_set_lvds_flow(int fd, CVI_BOOL is_lvds_flow_on); +int vi_get_ip_dump_list(int fd, struct ip_info *ip_info_list); +int vi_set_trig_preraw(int fd, CVI_U32 dev_num); +int vi_set_online2sc(int fd, struct cvi_isp_sc_online *online); +int vi_get_tun_addr(int fd, struct isp_tuning_cfg *tun_buf_info); +int vi_set_clk(int fd, CVI_BOOL clk_on); +int vi_get_dma_size(int fd, CVI_U32 *size); +int vi_set_dma_buf_info(int fd, struct cvi_vi_dma_buf_info *param); +int vi_set_enq_buf(int fd, struct vi_buffer *buf); +int vi_set_start_streaming(int fd); +int vi_set_stop_streaming(int fd); +int vi_get_rgbmap_le_buf(int fd, struct cvi_vip_memblock *buf); +int vi_get_rgbmap_se_buf(int fd, struct cvi_vip_memblock *buf); +int vi_enable_singel_frame(int fd, CVI_BOOL flag); +#ifdef ARCH_CV182X +int vi_set_rgbir(int fd, CVI_BOOL is_rgbir); +#endif + +#if (defined ARCH_CV181X) || (defined ARCH_CV180X) +int vi_sdk_get_dev_status(int fd, int dev, CVI_BOOL *pbStatus); +#endif + +int vi_sdk_set_dev_attr(int fd, int dev, VI_DEV_ATTR_S *pstDevAttr); +int vi_sdk_get_dev_attr(int fd, int dev, VI_DEV_ATTR_S *pstDevAttr); +int vi_sdk_enable_dev(int fd, int dev); +int vi_sdk_create_pipe(int fd, int pipe, VI_PIPE_ATTR_S *pstPipeAttr); +int vi_sdk_start_pipe(int fd, int pipe); +int vi_sdk_set_chn_attr(int fd, int pipe, int chn, VI_CHN_ATTR_S *pstChnAttr); +int vi_sdk_get_chn_attr(int fd, int pipe, int chn, VI_CHN_ATTR_S *pstChnAttr); +int vi_sdk_set_pipe_attr(int fd, int pipe, VI_PIPE_ATTR_S *pstPipeAttr); +int vi_sdk_get_pipe_attr(int fd, int pipe, VI_PIPE_ATTR_S *pstPipeAttr); +int vi_sdk_get_pipe_dump_attr(int fd, int pipe, VI_DUMP_ATTR_S *pstDumpAttr); +int vi_sdk_set_pipe_dump_attr(int fd, int pipe, VI_DUMP_ATTR_S *pstDumpAttr); +int vi_sdk_enable_chn(int fd, int pipe, int chn); +int vi_sdk_disable_chn(int fd, int pipe, int chn); +int vi_sdk_set_motion_lv(int fd, struct mlv_info_s *mlv_i); +int vi_sdk_enable_dis(int fd, int pipe); +int vi_sdk_disable_dis(int fd, int pipe); +int vi_sdk_set_dis_info(int fd, struct dis_info_s *pdis_i); +int vi_sdk_set_pipe_frm_src(int fd, int pipe, VI_PIPE_FRAME_SOURCE_E *source); +int vi_sdk_send_pipe_raw(int fd, int pipe, VIDEO_FRAME_INFO_S *sVideoFrm); +int vi_sdk_set_dev_timing_attr(int fd, int dev, VI_DEV_TIMING_ATTR_S *pstDevTimingAttr); +int vi_sdk_get_chn_frame(int fd, int pipe, int chn, VIDEO_FRAME_INFO_S *pstFrameInfo, CVI_S32 s32MilliSec); +int vi_sdk_release_chn_frame(int fd, int pipe, int chn, VIDEO_FRAME_INFO_S *pstFrameInfo); +int vi_sdk_set_chn_crop(int fd, int pipe, int chn, VI_CROP_INFO_S *pstCropInfo); +int vi_sdk_get_chn_crop(int fd, int pipe, int chn, VI_CROP_INFO_S *pstCropInfo); +int vi_sdk_get_pipe_frame(int fd, int pipe, VIDEO_FRAME_INFO_S *pstFrameInfo, CVI_S32 s32MilliSec); +int vi_sdk_release_pipe_frame(int fd, int pipe, VIDEO_FRAME_INFO_S *pstFrameInfo); +int vi_sdk_start_smooth_rawdump(int fd, int pipe, struct cvi_vip_isp_smooth_raw_param *smooth_raw_param); +int vi_sdk_stop_smooth_rawdump(int fd, int pipe, struct cvi_vip_isp_smooth_raw_param *smooth_raw_param); +int vi_sdk_get_smooth_rawdump(int fd, int pipe, VIDEO_FRAME_INFO_S *pstFrameInfo, CVI_S32 s32MilliSec); +int vi_sdk_put_smooth_rawdump(int fd, int pipe, VIDEO_FRAME_INFO_S *pstFrameInfo); +int vi_sdk_set_chn_rotation(int fd, const struct vi_chn_rot_cfg *cfg); +int vi_sdk_set_chn_ldc(int fd, const struct vi_chn_ldc_cfg *cfg); +int vi_sdk_attach_vbpool(int fd, const struct vi_vb_pool_cfg *cfg); +int vi_sdk_detach_vbpool(int fd, const struct vi_vb_pool_cfg *cfg); +#endif // __VI_IOCTL_H_ diff --git a/middleware/v2/modules/vo/include/vo_ioctl.h b/middleware/v2/modules/vo/include/vo_ioctl.h new file mode 100644 index 000000000..61ad81758 --- /dev/null +++ b/middleware/v2/modules/vo/include/vo_ioctl.h @@ -0,0 +1,61 @@ +#ifndef __VO_IOCTL_H__ +#define __VO_IOCTL_H__ + +#include +#include +#include + +#include +#include + +#include "cvi_base.h" + +int vo_set_pattern(int fd, enum cvi_vip_pattern pattern); +int vo_set_mode(int fd, int mode); +int vo_set_frame_bgcolor(int fd, void *rgb); +int vo_set_window_bgcolor(int fd, void *rgb); +int vo_set_intf(int fd, struct cvi_disp_intf_cfg *cfg); +int vo_enable_window_bgcolor(int fd, int enable); +int vo_set_align(int fd, int align); +int vo_set_rgn(int fd, struct cvi_rgn_cfg *cfg); +int vo_set_csc(int fd, struct cvi_csc_cfg *cfg); +int vo_set_clk(int fd, CVI_U32 clk_freq); +int vo_set_i80_sw_mode(int fd, CVI_U32 enable); +int vo_send_i80_cmd(int fd, CVI_U32 cmd); +int vo_get_videolayer_size(int fd, SIZE_S *vsize); +int vo_get_panel_status(int fd, CVI_U32 *is_init); +int vo_get_intf_type(int fd, CVI_S32 *vo_sel); +int vo_set_gamma_ctrl(int fd, VO_GAMMA_INFO_S *gamma_attr); +int vo_get_gamma_ctrl(int fd, VO_GAMMA_INFO_S *gamma_attr); +int vo_set_tgt_compose(int fd, struct vo_rect *sel); +int vo_set_tgt_crop(int fd, struct vo_rect *sel); +int vo_set_dv_timings(int fd, struct vo_dv_timings *timings); +int vo_get_dv_timings(int fd, struct vo_dv_timings *timings); +int vo_set_start_streaming(int fd); +int vo_set_stop_streaming(int fd); +int vo_enq_buf(int fd, struct vo_buffer *buf); + +//vo sdk layer apis +int vo_sdk_send_frame(int fd, struct vo_snd_frm_cfg *cfg); +int vo_sdk_get_panelstatue(int fd, struct vo_panel_status_cfg *cfg); +int vo_sdk_get_pubattr(int fd, struct vo_pub_attr_cfg *cfg); +int vo_sdk_set_pubattr(int fd, struct vo_pub_attr_cfg *cfg); +int vo_sdk_get_displaybuflen(int fd, struct vo_display_buflen_cfg *cfg); +int vo_sdk_set_displaybuflen(int fd, struct vo_display_buflen_cfg *cfg); +int vo_sdk_set_videolayerattr(int fd, struct vo_video_layer_attr_cfg *cfg); +int vo_sdk_get_videolayerattr(int fd, struct vo_video_layer_attr_cfg *cfg); +int vo_sdk_enable_videolayer(int fd, struct vo_video_layer_cfg *cfg); +int vo_sdk_disable_videolayer(int fd, struct vo_video_layer_cfg *cfg); +int vo_sdk_set_chnattr(int fd, struct vo_chn_attr_cfg *cfg); +int vo_sdk_get_chnattr(int fd, struct vo_chn_attr_cfg *cfg); +int vo_sdk_enable_chn(int fd, struct vo_chn_cfg *cfg); +int vo_sdk_disable_chn(int fd, struct vo_chn_cfg *cfg); +int vo_sdk_enable(int fd, struct vo_dev_cfg *cfg); +int vo_sdk_disable(int fd, struct vo_dev_cfg *cfg); +int vo_sdk_suspend(int fd); +int vo_sdk_resume(int fd); +int vo_sdk_clearchnbuf(int fd, struct vo_clear_chn_buf_cfg *cfg); +int vo_sdk_set_chnrotation(int fd, struct vo_chn_rotation_cfg *cfg); +int vo_sdk_get_chnrotation(int fd, struct vo_chn_rotation_cfg *cfg); + +#endif // __VO_IOCTL_H__ diff --git a/middleware/v2/modules/vpss/include/vpss_ioctl.h b/middleware/v2/modules/vpss/include/vpss_ioctl.h new file mode 100644 index 000000000..518c40767 --- /dev/null +++ b/middleware/v2/modules/vpss/include/vpss_ioctl.h @@ -0,0 +1,75 @@ +#ifndef __VPSS_IOCTL_H_ +#define __VPSS_IOCTL_H_ + +#include + +#include + +/* Configured from user */ +CVI_S32 vpss_create_grp(CVI_S32 fd, struct vpss_crt_grp_cfg *cfg); +CVI_S32 vpss_destroy_grp(CVI_S32 fd, VPSS_GRP VpssGrp); +CVI_S32 vpss_get_available_grp(CVI_S32 fd, VPSS_GRP *pVpssGrp); + +CVI_S32 vpss_start_grp(CVI_S32 fd, struct vpss_str_grp_cfg *cfg); +CVI_S32 vpss_stop_grp(CVI_S32 fd, VPSS_GRP VpssGrp); + +CVI_S32 vpss_reset_grp(CVI_S32 fd, VPSS_GRP VpssGrp); + +CVI_S32 vpss_set_grp_attr(CVI_S32 fd, const struct vpss_grp_attr *cfg); +CVI_S32 vpss_get_grp_attr(CVI_S32 fd, struct vpss_grp_attr *cfg); + +CVI_S32 vpss_set_grp_crop(CVI_S32 fd, const struct vpss_grp_crop_cfg *cfg); +CVI_S32 vpss_get_grp_crop(CVI_S32 fd, struct vpss_grp_crop_cfg *cfg); + +CVI_S32 vpss_send_frame(CVI_S32 fd, struct vpss_snd_frm_cfg *cfg); +CVI_S32 vpss_send_chn_frame(CVI_S32 fd, struct vpss_chn_frm_cfg *cfg); + +CVI_S32 vpss_set_chn_attr(CVI_S32 fd, struct vpss_chn_attr *attr); +CVI_S32 vpss_get_chn_attr(CVI_S32 fd, struct vpss_chn_attr *attr); + +CVI_S32 vpss_enable_chn(CVI_S32 fd, struct vpss_en_chn_cfg *cfg); +CVI_S32 vpss_disable_chn(CVI_S32 fd, struct vpss_en_chn_cfg *cfg); + +CVI_S32 vpss_set_chn_crop(CVI_S32 fd, const struct vpss_chn_crop_cfg *cfg); +CVI_S32 vpss_get_chn_crop(CVI_S32 fd, struct vpss_chn_crop_cfg *cfg); + +CVI_S32 vpss_set_chn_rotation(CVI_S32 fd, const struct vpss_chn_rot_cfg *cfg); +CVI_S32 vpss_get_chn_rotation(CVI_S32 fd, struct vpss_chn_rot_cfg *cfg); + +CVI_S32 vpss_show_chn(CVI_S32 fd, struct vpss_en_chn_cfg *cfg); +CVI_S32 vpss_hide_chn(CVI_S32 fd, struct vpss_en_chn_cfg *cfg); + +CVI_S32 vpss_set_chn_ldc(CVI_S32 fd, const struct vpss_chn_ldc_cfg *cfg); +CVI_S32 vpss_get_chn_ldc(CVI_S32 fd, struct vpss_chn_ldc_cfg *cfg); + +CVI_S32 vpss_get_chn_frame(CVI_S32 fd, struct vpss_chn_frm_cfg *cfg); + +CVI_S32 vpss_release_chn_frame(CVI_S32 fd, const struct vpss_chn_frm_cfg *cfg); + +CVI_S32 vpss_attach_vbpool(CVI_S32 fd, const struct vpss_vb_pool_cfg *cfg); +CVI_S32 vpss_detach_vbpool(CVI_S32 fd, const struct vpss_vb_pool_cfg *cfg); + +CVI_S32 vpss_set_chn_align(CVI_S32 fd, const struct vpss_chn_align_cfg *cfg); +CVI_S32 vpss_get_chn_align(CVI_S32 fd, struct vpss_chn_align_cfg *cfg); + +CVI_S32 vpss_set_chn_yratio(CVI_S32 fd, const struct vpss_chn_yratio_cfg *cfg); +CVI_S32 vpss_get_chn_yratio(CVI_S32 fd, struct vpss_chn_yratio_cfg *cfg); + +CVI_S32 vpss_set_coef_level(CVI_S32 fd, const struct vpss_chn_coef_level_cfg *cfg); +CVI_S32 vpss_get_coef_level(CVI_S32 fd, struct vpss_chn_coef_level_cfg *cfg); + +CVI_S32 vpss_set_chn_wrap(CVI_S32 fd, const struct vpss_chn_wrap_cfg *cfg); +CVI_S32 vpss_get_chn_wrap(CVI_S32 fd, struct vpss_chn_wrap_cfg *cfg); + +CVI_S32 vpss_trigger_snap_frame(CVI_S32 fd, struct vpss_snap_cfg *cfg); + +CVI_S32 vpss_get_proc_amp_ctrl(CVI_S32 fd, struct vpss_proc_amp_ctrl_cfg *cfg); +CVI_S32 vpss_get_proc_amp(CVI_S32 fd, struct vpss_proc_amp_cfg *cfg); +CVI_S32 vpss_get_all_proc_amp(CVI_S32 fd, struct vpss_all_proc_amp_cfg *cfg); + +/* INTERNAL */ +CVI_S32 vpss_set_grp_csc(CVI_S32 fd, const struct vpss_grp_csc_cfg *csc_cfg); +CVI_S32 vpss_get_binscene(CVI_S32 fd, struct vpss_scene *csc_cfg); + + +#endif /* __VPSS_IOCTL_H_ */