clear directory build
This commit is contained in:
carbon
@ -1,12 +0,0 @@
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&dac{
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mute-gpio-l = <&porta 15 GPIO_ACTIVE_LOW>;
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mute-gpio-r = <&porta 30 GPIO_ACTIVE_LOW>;
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};
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/ {
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/delete-node/ i2s@04110000;
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/delete-node/ i2s@04120000;
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/delete-node/ sound_ext1;
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/delete-node/ sound_ext2;
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/delete-node/ sound_PDM;
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};
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@ -1,66 +0,0 @@
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&sd {
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no-1-8-v;
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};
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&mipi_rx{
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snsr-reset = <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>;
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};
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&dac{
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mute-gpio-r = <&porte 2 GPIO_ACTIVE_LOW>;
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};
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&spi0 {
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status = "disabled";
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num-cs = <1>;
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spidev@0 {
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compatible = "rohm,dh2228fv";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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};
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||||
&spi1 {
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status = "disabled";
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num-cs = <1>;
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spidev@0 {
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compatible = "rohm,dh2228fv";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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};
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&spi2 {
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status = "disabled";
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num-cs = <1>;
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spidev@0 {
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compatible = "rohm,dh2228fv";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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};
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&spi3 {
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status = "okay";
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num-cs = <1>;
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spidev@0 {
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compatible = "rohm,dh2228fv";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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};
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/ {
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/delete-node/ wifi-sd@4320000;
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/delete-node/ i2s@04110000;
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/delete-node/ sound_ext1;
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/delete-node/ sound_ext2;
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/delete-node/ sound_PDM;
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wifi_pin {
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compatible = "cvitek,wifi-pin";
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poweron-gpio = <&porte 2 GPIO_ACTIVE_HIGH>;
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wakeup-gpio = <&porte 6 GPIO_ACTIVE_HIGH>;
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};
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};
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@ -1,4 +0,0 @@
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/ {
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/delete-node/ cv-emmc@4300000;
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/delete-node/ cv-spinf@4060000;
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};
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@ -1,5 +0,0 @@
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/ {
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/delete-node/ cvi-spif@10000000;
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/delete-node/ cv-emmc@4300000;
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};
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@ -1,5 +0,0 @@
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/ {
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/delete-node/ cv-emmc@4300000;
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/delete-node/ cv-spinf@4060000;
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};
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@ -1,892 +0,0 @@
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/ {
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compatible = "cvitek,cv180x";
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#size-cells = <0x2>;
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#address-cells = <0x2>;
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top_misc:top_misc_ctrl@3000000 {
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compatible = "syscon";
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reg = <0x0 0x03000000 0x0 0x8000>;
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};
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clk_rst: clk-reset-controller {
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#reset-cells = <1>;
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compatible = "cvitek,clk-reset";
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reg = <0x0 0x03002000 0x0 0x8>;
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};
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "osc";
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};
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clk: clock-controller {
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compatible = "cvitek,cv180x-clk";
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reg = <0x0 0x03002000 0x0 0x1000>;
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clocks = <&osc>;
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#clock-cells = <1>;
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};
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rst: reset-controller {
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#reset-cells = <1>;
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compatible = "cvitek,reset";
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reg = <0x0 0x03003000 0x0 0x10>;
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};
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restart: restart-controller {
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compatible = "cvitek,restart";
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reg = <0x0 0x05025000 0x0 0x2000>;
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};
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tpu {
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compatible = "cvitek,tpu";
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reg-names = "tdma", "tiu";
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reg = <0x0 0x0C100000 0x0 0x1000>,
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<0x0 0x0C101000 0x0 0x1000>;
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clocks = <&clk CV180X_CLK_TPU>, <&clk CV180X_CLK_TPU_FAB>;
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clock-names = "clk_tpu_axi", "clk_tpu_fab";
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resets = <&rst RST_TDMA>, <&rst RST_TPU>, <&rst RST_TPUSYS>;
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reset-names = "res_tdma", "res_tpu", "res_tpusys";
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};
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mon {
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compatible = "cvitek,mon";
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reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
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reg = <0x0 0x01040000 0x0 0x1000>,
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<0x0 0x08004000 0x0 0x1000>,
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<0x0 0x08006000 0x0 0x1000>,
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<0x0 0x08008000 0x0 0x1000>,
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<0x0 0x0800A000 0x0 0x1000>;
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};
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wiegand0 {
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compatible = "cvitek,wiegand";
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reg-names = "wiegand";
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reg = <0x0 0x03030000 0x0 0x1000>;
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clocks = <&clk CV180X_CLK_WGN>, <&clk CV180X_CLK_WGN0>;
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clock-names = "clk_wgn", "clk_wgn1";
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resets = <&rst RST_WGN0>;
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reset-names = "res_wgn";
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};
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wiegand1 {
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compatible = "cvitek,wiegand";
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reg-names = "wiegand";
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reg = <0x0 0x03031000 0x0 0x1000>;
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clocks = <&clk CV180X_CLK_WGN>, <&clk CV180X_CLK_WGN1>;
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clock-names = "clk_wgn", "clk_wgn1";
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resets = <&rst RST_WGN1>;
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reset-names = "res_wgn";
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};
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||||
wiegand2 {
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||||
compatible = "cvitek,wiegand";
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reg-names = "wiegand";
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reg = <0x0 0x03032000 0x0 0x1000>;
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clocks = <&clk CV180X_CLK_WGN>, <&clk CV180X_CLK_WGN2>;
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clock-names = "clk_wgn", "clk_wgn1";
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resets = <&rst RST_WGN2>;
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reset-names = "res_wgn";
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};
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saradc {
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compatible = "cvitek,saradc";
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reg-names = "top_domain_saradc", "rtc_domain_saradc";
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reg = <0x0 0x030F0000 0x0 0x1000>, <0x0 0x0502c000 0x0 0x1000>;
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clocks = <&clk CV180X_CLK_SARADC>;
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clock-names = "clk_saradc";
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||||
resets = <&rst RST_SARADC>;
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reset-names = "res_saradc";
|
||||
};
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||||
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||||
rtc {
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||||
compatible = "cvitek,rtc";
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reg = <0x0 0x05026000 0x0 0x1000>,<0x0 0x05025000 0x0 0x1000>;
|
||||
clocks = <&clk CV180X_CLK_RTC_25M>;
|
||||
clock-names = "clk_rtc";
|
||||
};
|
||||
|
||||
cvitek-ion {
|
||||
compatible = "cvitek,cvitek-ion";
|
||||
|
||||
heap_carveout@0 {
|
||||
compatible = "cvitek,carveout";
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||||
memory-region = <&ion_reserved>;
|
||||
};
|
||||
};
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||||
|
||||
sysdma_remap {
|
||||
compatible = "cvitek,sysdma_remap";
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||||
reg = <0x0 0x03000154 0x0 0x10>;
|
||||
ch-remap = <CVI_I2S0_RX CVI_I2S2_TX CVI_I2S1_RX CVI_I2S1_TX
|
||||
CVI_SPI_NAND CVI_SPI_NAND CVI_I2S2_RX CVI_I2S3_TX>;
|
||||
int_mux_base = <0x03000298>;
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
compatible = "snps,dmac-bm";
|
||||
reg = <0x0 0x04330000 0x0 0x1000>;
|
||||
clock-names = "clk_sdma_axi";
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||||
clocks = <&clk CV180X_CLK_SDMA_AXI>;
|
||||
|
||||
dma-channels = /bits/ 8 <8>;
|
||||
#dma-cells = <3>;
|
||||
dma-requests = /bits/ 8 <16>;
|
||||
chan_allocation_order = /bits/ 8 <0>;
|
||||
chan_priority = /bits/ 8 <1>;
|
||||
block_size = <1024>;
|
||||
dma-masters = /bits/ 8 <2>;
|
||||
data-width = <4 4>; /* bytes */
|
||||
axi_tr_width = <4>; /* bytes */
|
||||
block-ts = <15>;
|
||||
};
|
||||
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0x0 0x03010000 0x0 0x1000>;
|
||||
resets = <&rst RST_WDT>;
|
||||
clocks = <&pclk>;
|
||||
};
|
||||
|
||||
pwm0: pwm@3060000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3060000 0x0 0x1000>;
|
||||
clocks = <&clk CV180X_CLK_PWM>;
|
||||
#pwm-cells = <1>;
|
||||
};
|
||||
|
||||
pwm1: pwm@3061000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3061000 0x0 0x1000>;
|
||||
clocks = <&clk CV180X_CLK_PWM>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
pwm2: pwm@3062000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3062000 0x0 0x1000>;
|
||||
clocks = <&clk CV180X_CLK_PWM>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
pwm3: pwm@3063000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3063000 0x0 0x1000>;
|
||||
clocks = <&clk CV180X_CLK_PWM>;
|
||||
#pwm-cells = <4>;
|
||||
};
|
||||
|
||||
pclk: pclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
compatible = "cvitek,cv1835-spinf";
|
||||
reg = <0x0 0x4060000 0x0 0x1000>;
|
||||
reg-names = "core_mem";
|
||||
bus-width = <4>;
|
||||
dmas = <&dmac 4 1 1
|
||||
&dmac 5 1 1>;
|
||||
dma-names = "rx","tx";
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
compatible = "cvitek,cvi-spif";
|
||||
bus-num = <0>;
|
||||
reg = <0x0 0x10000000 0x0 0x10000000>;
|
||||
reg-names = "spif";
|
||||
sck-div = <3>;
|
||||
sck_mhz = <300>;
|
||||
spi-max-frequency = <75000000>;
|
||||
spiflash {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x04180000 0x0 0x10000>;
|
||||
clocks = <&clk CV180X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x04190000 0x0 0x10000>;
|
||||
clocks = <&clk CV180X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x041A0000 0x0 0x10000>;
|
||||
clocks = <&clk CV180X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x041B0000 0x0 0x10000>;
|
||||
clocks = <&clk CV180X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#if 0
|
||||
dmas = <&dmac 2 1 1
|
||||
&dmac 3 1 1>;
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
#endif
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04140000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04150000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04160000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04170000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x041C0000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03020000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "porta";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03021000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portb: gpio-controller@1 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portb";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03022000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portc: gpio-controller@2 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portc";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03023000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portd: gpio-controller@3 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portd";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x05021000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porte: gpio-controller@4 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "porte";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV180X_CLK_I2C>;
|
||||
reg = <0x0 0x04000000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
resets = <&rst RST_I2C0>;
|
||||
reset-names = "i2c0";
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV180X_CLK_I2C>;
|
||||
reg = <0x0 0x04010000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
resets = <&rst RST_I2C1>;
|
||||
reset-names = "i2c1";
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV180X_CLK_I2C>;
|
||||
reg = <0x0 0x04020000 0x0 0x1000>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
resets = <&rst RST_I2C2>;
|
||||
reset-names = "i2c2";
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV180X_CLK_I2C>;
|
||||
reg = <0x0 0x04030000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
resets = <&rst RST_I2C3>;
|
||||
reset-names = "i2c3";
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV180X_CLK_I2C>;
|
||||
reg = <0x0 0x04040000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
resets = <&rst RST_I2C4>;
|
||||
reset-names = "i2c4";
|
||||
};
|
||||
|
||||
eth_csrclk: eth_csrclk {
|
||||
clock-output-names = "eth_csrclk";
|
||||
clock-frequency = <250000000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
eth_ptpclk: eth_ptpclk {
|
||||
clock-output-names = "eth_ptpclk";
|
||||
clock-frequency = <50000000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,wr_osr_lmt = <1>;
|
||||
snps,rd_osr_lmt = <2>;
|
||||
snps,blen = <4 8 16 0 0 0 0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
|
||||
mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
compatible = "cvitek,ethernet";
|
||||
reg = <0x0 0x04070000 0x0 0x10000>;
|
||||
clock-names = "stmmaceth", "ptp_ref";
|
||||
clocks = <ð_csrclk>, <ð_ptpclk>;
|
||||
//phy-reset-gpios = <&porta 26 0>;
|
||||
|
||||
tx-fifo-depth = <8192>;
|
||||
rx-fifo-depth = <8192>;
|
||||
/* no hash filter and perfect filter support */
|
||||
snps,multicast-filter-bins = <0>;
|
||||
snps,perfect-filter-entries = <1>;
|
||||
|
||||
snps,txpbl = <8>;
|
||||
snps,rxpbl = <8>;
|
||||
snps,aal;
|
||||
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup>;
|
||||
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
sd:cv-sd@4310000 {
|
||||
compatible = "cvitek,cv180x-sd";
|
||||
reg = <0x0 0x4310000 0x0 0x1000>;
|
||||
reg-names = "core_mem";
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
/*no-1-8-v;*/
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>;
|
||||
max-frequency = <200000000>;
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
reset-names = "sdhci";
|
||||
pll_index = <0x6>;
|
||||
pll_reg = <0x3002070>;
|
||||
cvi-cd-gpios = <&porta 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
compatible = "cvitek,cv180x-sdio";
|
||||
bus-width = <4>;
|
||||
reg = <0x0 0x4320000 0x0 0x1000>;
|
||||
reg_names = "core_mem";
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>;
|
||||
max-frequency = <50000000>;
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
non-removable;
|
||||
pll_index = <0x7>;
|
||||
pll_reg = <0x300207C>;
|
||||
no-mmc;
|
||||
no-sd;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s_mclk: i2s_mclk {
|
||||
clock-output-names = "i2s_mclk";
|
||||
clock-frequency = <24576000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
i2s_subsys {
|
||||
compatible = "cvitek,i2s_tdm_subsys";
|
||||
reg = <0x0 0x04108000 0x0 0x100>;
|
||||
clocks = <&i2s_mclk>, <&clk CV180X_CLK_A0PLL>,
|
||||
<&clk CV180X_CLK_SDMA_AUD0>, <&clk CV180X_CLK_SDMA_AUD1>,
|
||||
<&clk CV180X_CLK_SDMA_AUD2>, <&clk CV180X_CLK_SDMA_AUD3>;
|
||||
clock-names = "i2sclk", "clk_a0pll",
|
||||
"clk_sdma_aud0", "clk_sdma_aud1",
|
||||
"clk_sdma_aud2", "clk_sdma_aud3";
|
||||
master_base = <0x04110000>; /* I2S1 is master, only useful while using multi I2S IPs work on same IO */
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04100000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <0>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 0 1 1>; /* read channel */
|
||||
dma-names = "rx";
|
||||
capability = "rx"; /* I2S0 connect to internal ADC as RX */
|
||||
mclk_out = "false";
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04110000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <1>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 2 1 1 /* read channel */
|
||||
&dmac 3 1 1>; /* write channel */
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
mclk_out = "false";
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04120000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <2>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 6 1 1 /* read channel */
|
||||
&dmac 1 1 1>; /* write channel */
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
mclk_out = "false";
|
||||
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04130000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <3>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 7 1 1>; /* write channel */
|
||||
dma-names = "tx";
|
||||
capability = "tx"; /* I2S3 connect to internal DAC as TX */
|
||||
mclk_out = "true";
|
||||
};
|
||||
|
||||
adc: adc@0300A100 {
|
||||
compatible = "cvitek,cv182xaadc";
|
||||
reg = <0x0 0x0300A100 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
clk_source = <0x04130000>; /* MCLK source is I2S3 */
|
||||
};
|
||||
|
||||
dac: dac@0300A000 {
|
||||
compatible = "cvitek,cv182xadac";
|
||||
reg = <0x0 0x0300A000 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
};
|
||||
|
||||
pdm: pdm@0x041D0C00 {
|
||||
compatible = "cvitek,cv1835pdm";
|
||||
reg = <0x0 0x041D0C00 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
};
|
||||
|
||||
sound_adc {
|
||||
compatible = "cvitek,cv182xa-adc";
|
||||
cvi,model = "CV182XA";
|
||||
cvi,card_name = "cv182xa_adc";
|
||||
};
|
||||
|
||||
sound_dac {
|
||||
compatible = "cvitek,cv182xa-dac";
|
||||
cvi,model = "CV182XA";
|
||||
cvi,card_name = "cv182xa_dac";
|
||||
};
|
||||
|
||||
sound_PDM {
|
||||
compatible = "cvitek,cv182x-pdm";
|
||||
cvi,model = "CV182X";
|
||||
cvi,card_name = "cv182x_internal_PDM";
|
||||
};
|
||||
lt9611 {
|
||||
compatible = "cvitek,cv1835-lt9611";
|
||||
cvi,model = "CV182X";
|
||||
cvi,card_name = "cv181x_lt9611";
|
||||
cvi,cpu_dai_name = "4120000.i2s";
|
||||
cvi,platform_name = "4120000.i2s";
|
||||
};
|
||||
|
||||
wifi_pin {
|
||||
compatible = "cvitek,wifi-pin";
|
||||
poweron-gpio = <&porta 18 GPIO_ACTIVE_HIGH>;
|
||||
wakeup-gpio = <&porte 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
bt_pin {
|
||||
compatible = "cvitek,bt-pin";
|
||||
poweron-gpio = <&porte 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
compatible = "cvitek,cif";
|
||||
reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
|
||||
<0x0 0x0a0c4000 0x0 0x2000>, <0x0 0x03001c30 0x0 0x30>;
|
||||
reg-names = "csi_mac0", "csi_wrap0", "csi_mac1", "pad_ctrl";
|
||||
snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>;
|
||||
resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
|
||||
<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
|
||||
reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
|
||||
clocks = <&clk CV180X_CLK_CAM0>, <&clk CV180X_CLK_CAM1>, <&clk CV180X_CLK_SRC_VIP_SYS_2>,
|
||||
<&clk CV180X_CLK_MIPIMPLL>, <&clk CV180X_CLK_DISPPLL>, <&clk CV180X_CLK_FPLL>;
|
||||
clock-names = "clk_cam0", "clk_cam1", "clk_sys_2",
|
||||
"clk_mipimpll", "clk_disppll", "clk_fpll";
|
||||
};
|
||||
|
||||
sys {
|
||||
compatible = "cvitek,sys";
|
||||
};
|
||||
|
||||
base {
|
||||
compatible = "cvitek,base";
|
||||
reg = <0x0 0x0a0c8000 0x0 0x20>;
|
||||
reg-names = "vip_sys";
|
||||
};
|
||||
|
||||
vi {
|
||||
compatible = "cvitek,vi";
|
||||
reg = <0x0 0x0a000000 0x0 0x80000>;
|
||||
clocks = <&clk CV180X_CLK_SRC_VIP_SYS_0>, <&clk CV180X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV180X_CLK_SRC_VIP_SYS_2>, <&clk CV180X_CLK_SRC_VIP_SYS_3>,
|
||||
<&clk CV180X_CLK_AXI_VIP>, <&clk CV180X_CLK_CSI_BE_VIP>,
|
||||
<&clk CV180X_CLK_RAW_VIP>, <&clk CV180X_CLK_ISP_TOP_VIP>,
|
||||
<&clk CV180X_CLK_CSI_MAC0_VIP>, <&clk CV180X_CLK_CSI_MAC1_VIP>,
|
||||
<&clk CV180X_CLK_CSI_MAC2_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1", "clk_sys_2", "clk_sys_3",
|
||||
"clk_axi", "clk_csi_be", "clk_raw", "clk_isp_top",
|
||||
"clk_csi_mac0", "clk_csi_mac1", "clk_csi_mac2";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
vpss {
|
||||
compatible = "cvitek,vpss";
|
||||
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
|
||||
reg-names = "sc";
|
||||
clocks = <&clk CV180X_CLK_SRC_VIP_SYS_0>, <&clk CV180X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV180X_CLK_SRC_VIP_SYS_2>, <&clk CV180X_CLK_IMG_D_VIP>,
|
||||
<&clk CV180X_CLK_IMG_V_VIP>, <&clk CV180X_CLK_SC_TOP_VIP>,
|
||||
<&clk CV180X_CLK_SC_D_VIP>, <&clk CV180X_CLK_SC_V1_VIP>,
|
||||
<&clk CV180X_CLK_SC_V2_VIP>, <&clk CV180X_CLK_SC_V3_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1",
|
||||
"clk_sys_2", "clk_img_d",
|
||||
"clk_img_v", "clk_sc_top",
|
||||
"clk_sc_d", "clk_sc_v1",
|
||||
"clk_sc_v2", "clk_sc_v3";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
dwa {
|
||||
compatible = "cvitek,dwa";
|
||||
reg = <0x0 0x0a0c0000 0x0 0x1000>;
|
||||
reg-names = "dwa";
|
||||
clocks = <&clk CV180X_CLK_SRC_VIP_SYS_0>, <&clk CV180X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV180X_CLK_SRC_VIP_SYS_2>, <&clk CV180X_CLK_SRC_VIP_SYS_3>,
|
||||
<&clk CV180X_CLK_SRC_VIP_SYS_4>, <&clk CV180X_CLK_DWA_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1",
|
||||
"clk_sys_2", "clk_sys_3",
|
||||
"clk_sys_4", "clk_dwa";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
rgn {
|
||||
compatible = "cvitek,rgn";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
compatible = "cvitek,asic-vcodec";
|
||||
reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>,
|
||||
<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
|
||||
reg-names = "h265","h264","vc_ctrl","vc_sbm","vc_addr_remap";
|
||||
clocks = <&clk CV180X_CLK_AXI_VIDEO_CODEC>,
|
||||
<&clk CV180X_CLK_H264C>, <&clk CV180X_CLK_APB_H264C>,
|
||||
<&clk CV180X_CLK_H265C>, <&clk CV180X_CLK_APB_H265C>,
|
||||
<&clk CV180X_CLK_VC_SRC0>, <&clk CV180X_CLK_VC_SRC1>,
|
||||
<&clk CV180X_CLK_VC_SRC2>, <&clk CV180X_CLK_CFG_REG_VC>;
|
||||
clock-names = "clk_axi_video_codec",
|
||||
"clk_h264c", "clk_apb_h264c",
|
||||
"clk_h265c", "clk_apb_h265c",
|
||||
"clk_vc_src0", "clk_vc_src1",
|
||||
"clk_vc_src2", "clk_cfg_reg_vc";
|
||||
};
|
||||
|
||||
jpu {
|
||||
compatible = "cvitek,asic-jpeg";
|
||||
reg = <0x0 0x0B000000 0x0 0x300>,<0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>;
|
||||
reg-names = "jpeg","vc_ctrl","vc_sbm";
|
||||
clocks = <&clk CV180X_CLK_AXI_VIDEO_CODEC>,
|
||||
<&clk CV180X_CLK_JPEG>, <&clk CV180X_CLK_APB_JPEG>,
|
||||
<&clk CV180X_CLK_VC_SRC0>, <&clk CV180X_CLK_VC_SRC1>,
|
||||
<&clk CV180X_CLK_VC_SRC2>, <&clk CV180X_CLK_CFG_REG_VC>;
|
||||
clock-names = "clk_axi_video_codec",
|
||||
"clk_jpeg", "clk_apb_jpeg",
|
||||
"clk_vc_src0", "clk_vc_src1",
|
||||
"clk_vc_src2", "clk_cfg_reg_vc";
|
||||
resets = <&rst RST_JPEG>;
|
||||
reset-names = "jpeg";
|
||||
};
|
||||
|
||||
cvi_vc_drv {
|
||||
compatible = "cvitek,cvi_vc_drv";
|
||||
reg = <0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
|
||||
reg-names = "vc_ctrl","vc_sbm","vc_addr_remap";
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
compatible = "cvitek,rtos_cmdqu";
|
||||
reg = <0x0 0x01900000 0x0 0x1000>;
|
||||
reg-names = "mailbox";
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
compatible = "cvitek,cv182x-usb";
|
||||
reg = <0x0 0x04340000 0x0 0x10000>,
|
||||
<0x0 0x03006000 0x0 0x58>; //USB 2.0 PHY
|
||||
dr_mode = "otg";
|
||||
g-use-dma;
|
||||
g-rx-fifo-size = <536>;
|
||||
g-np-tx-fifo-size = <32>;
|
||||
g-tx-fifo-size = <768 512 512 384 128 128>;
|
||||
clocks = <&clk CV180X_CLK_AXI4_USB>,
|
||||
<&clk CV180X_CLK_APB_USB>,
|
||||
<&clk CV180X_CLK_125M_USB>,
|
||||
<&clk CV180X_CLK_33K_USB>,
|
||||
<&clk CV180X_CLK_12M_USB>;
|
||||
clock-names = "clk_axi", "clk_apb", "clk_125m", "clk_33k", "clk_12m";
|
||||
vbus-gpio = <&portb 6 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
compatible = "cvitek,cv180x-thermal";
|
||||
reg = <0x0 0x030E0000 0x0 0x10000>;
|
||||
clocks = <&clk CV180X_CLK_TEMPSEN>;
|
||||
clock-names = "clk_tempsen";
|
||||
reset-names = "tempsen";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
#if 0
|
||||
cv182x_cooling:cv182x_cooling {
|
||||
clocks = <&clk CV180X_CLK_A53>, <&clk CV180X_CLK_TPU>;
|
||||
clock-names = "clk_a53", "clk_tpu_axi";
|
||||
dev-freqs = <1000000000 750000000>,
|
||||
<500000000 375000000>,
|
||||
<500000000 100000000>;
|
||||
compatible = "cvitek,cv182x-cooling";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
#endif
|
||||
|
||||
thermal-zones {
|
||||
soc_thermal_0: soc_thermal_0 {
|
||||
polling-delay-passive = <1000>; /* milliseconds */
|
||||
polling-delay = <1000>; /* milliseconds */
|
||||
thermal-sensors = <&thermal 0>;
|
||||
|
||||
trips {
|
||||
soc_thermal_trip_0: soc_thermal_trip_0 {
|
||||
temperature = <100000>; /* millicelsius */
|
||||
hysteresis = <5000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
soc_thermal_trip_1: soc_thermal_trip_1 {
|
||||
temperature = <110000>; /* millicelsius */
|
||||
hysteresis = <5000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
soc_thermal_crtical_0: soc_thermal_crtical_0 {
|
||||
temperature = <130000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#if 0
|
||||
cvipctrl: pinctrl@3001000 {
|
||||
compatible = "cvitek,pinctrl-cv182x";
|
||||
reg = <0 0x03001000 0 0x1000>;
|
||||
};
|
||||
#endif
|
||||
|
||||
cviaudio_core {
|
||||
compatible = "cvitek,audio";
|
||||
};
|
||||
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
#if 0
|
||||
clock-frequency = <12288000>;
|
||||
#else
|
||||
clock-frequency = <24576000>;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
ethernet0 = ðernet0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,25 +0,0 @@
|
||||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00 CVIMMAP_KERNEL_MEMORY_ADDR 0x00 CVIMMAP_KERNEL_MEMORY_SIZE>;
|
||||
};
|
||||
|
||||
|
||||
fast_image {
|
||||
compatible = "cvitek,rtos_image";
|
||||
reg-names = "rtos_region";
|
||||
reg = <0x0 CVIMMAP_FREERTOS_ADDR 0x0 CVIMMAP_FREERTOS_SIZE>;
|
||||
ion-size = <CVIMMAP_FREERTOS_RESERVED_ION_SIZE>; //reserved ion size for freertos
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
ranges;
|
||||
|
||||
ion_reserved: ion {
|
||||
compatible = "ion-region";
|
||||
size = <0x0 CVIMMAP_ION_SIZE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,374 +0,0 @@
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/cv180x-resets.h>
|
||||
#include <dt-bindings/clock/cv180x-clock.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/dma/cv180x-dmamap.h>
|
||||
#include "cvi_board_memmap.h"
|
||||
|
||||
/*
|
||||
* OpenSBI will add below subnode into reserved memory automatically
|
||||
* mmode_resv0@80000000 {
|
||||
* reg = <0x00 0x80000000 0x00 0x20000>;
|
||||
* phandle = <0x0d>;
|
||||
* };
|
||||
* Skip below to avoid lmb region reseved conflict in uboot.
|
||||
*
|
||||
*/
|
||||
#ifndef __UBOOT__
|
||||
/memreserve/ CVIMMAP_MONITOR_ADDR CVIMMAP_OPENSBI_SIZE; // OpenSBI
|
||||
#endif
|
||||
|
||||
#include "cv180x_base.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Cvitek. CV180X ASIC. C906.";
|
||||
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
c906_cpus:cpus {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
timebase-frequency = <25000000>;
|
||||
|
||||
cpu-map {
|
||||
|
||||
cluster0 {
|
||||
|
||||
core0 {
|
||||
cpu = <0x01>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x00>;
|
||||
status = "okay";
|
||||
compatible = "riscv";
|
||||
riscv,isa = "rv64imafdvcsu";
|
||||
mmu-type = "riscv,sv39";
|
||||
clock-frequency = <25000000>;
|
||||
|
||||
cpu0_intc: interrupt-controller {
|
||||
#interrupt-cells = <0x01>;
|
||||
interrupt-controller;
|
||||
compatible = "riscv,cpu-intc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <0x02>;
|
||||
#size-cells = <0x02>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
plic0: interrupt-controller@70000000 {
|
||||
riscv,ndev = <101>;
|
||||
riscv,max-priority = <0x07>;
|
||||
reg-names = "control";
|
||||
reg = <0x00 0x70000000 0x00 0x4000000>;
|
||||
interrupts-extended = <&cpu0_intc 0xffffffff &cpu0_intc 0x09>;
|
||||
interrupt-controller;
|
||||
compatible = "riscv,plic0";
|
||||
#interrupt-cells = <0x02>;
|
||||
#address-cells = <0x00>;
|
||||
};
|
||||
|
||||
clint@74000000 {
|
||||
interrupts-extended = <&cpu0_intc 0x03 &cpu0_intc 0x07>;
|
||||
reg = <0x00 0x74000000 0x00 0x10000>;
|
||||
compatible = "riscv,clint0";
|
||||
clint,has-no-64bit-mmio;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
|
||||
cv180x_cooling:cv180x_cooling {
|
||||
clocks = <&clk CV180X_CLK_C906_0>, <&clk CV180X_CLK_TPU>;
|
||||
clock-names = "clk_cpu", "clk_tpu_axi";
|
||||
dev-freqs = <850000000 500000000>,
|
||||
<425000000 375000000>,
|
||||
<425000000 300000000>;
|
||||
compatible = "cvitek,cv180x-cooling";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
tpu {
|
||||
interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tiu_irq", "tdma_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
mon {
|
||||
interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mon_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand0 {
|
||||
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand1 {
|
||||
interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand2 {
|
||||
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
saradc {
|
||||
interrupts = <100 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
sysdma_remap {
|
||||
int_mux = <0x7FC00>; /* enable bit [10..18] for CPU1(906B) */
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
porta: gpio-controller@0 {
|
||||
interrupt-controller;
|
||||
interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
portb: gpio-controller@1 {
|
||||
interrupt-controller;
|
||||
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
portc: gpio-controller@2 {
|
||||
interrupt-controller;
|
||||
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
portd: gpio-controller@3 {
|
||||
interrupt-controller;
|
||||
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
porte: gpio-controller@4 {
|
||||
interrupt-controller;
|
||||
interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
interrupt-names = "macirq";
|
||||
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
#if 0
|
||||
emmc:cv-emmc@4300000 {
|
||||
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
#endif
|
||||
sd:cv-sd@4310000 {
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
vi {
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupt-names = "isp";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "h265","h264","sbm";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
jpu {
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "jpeg";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mailbox";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "csi0", "csi1";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
#if 0
|
||||
ive {
|
||||
interrupt-names = "ive_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
#endif
|
||||
vpss {
|
||||
interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sc";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
dwa {
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dwa";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tempsen";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
};
|
||||
@ -1,16 +0,0 @@
|
||||
&dac{
|
||||
mute-gpio-l = <&porta 15 GPIO_ACTIVE_LOW>;
|
||||
mute-gpio-r = <&porta 30 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/ {
|
||||
/delete-node/ i2s@04110000;
|
||||
/delete-node/ i2s@04120000;
|
||||
/delete-node/ sound_ext1;
|
||||
/delete-node/ sound_ext2;
|
||||
/delete-node/ sound_PDM;
|
||||
};
|
||||
@ -1,4 +0,0 @@
|
||||
/ {
|
||||
/delete-node/ cvi-spif@10000000;
|
||||
/delete-node/ cv-spinf@4060000;
|
||||
};
|
||||
@ -1,118 +0,0 @@
|
||||
&sd {
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
&mipi_rx{
|
||||
snsr-reset = <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&mipi_tx {
|
||||
reset-gpio = <&porta 15 GPIO_ACTIVE_LOW>;
|
||||
pwm-gpio = <&porta 18 GPIO_ACTIVE_HIGH>;
|
||||
power-ct-gpio = <&porta 19 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&dac{
|
||||
mute-gpio-r = <&porte 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "disabled";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "disabled";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
status = "disabled";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi3 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x03001070 0x0 0x3>; // IIC0_SCL/IIC0_SCL/XGPIOA[28]
|
||||
sda-pinmux = <0x03001074 0x0 0x3>; // IIC0_SDA/IIC0_SDA/XGPIOA[29]
|
||||
/* gpio port */
|
||||
scl-gpios = <&porta 28 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&porta 29 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x03009408 0x2 0x3>; // SPI1_MOSI/IIC1_SCL/XGPIOB[7]
|
||||
sda-pinmux = <0x0300940c 0x2 0x3>; // SPI1_MISO/IIC1_SDA/XGPIOB[8]
|
||||
/* gpio port */
|
||||
scl-gpios = <&portb 7 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&portb 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x030011a0 0x4 0x3>; // PAD_MIPI_TXP1/IIC2_SCL/XGPIOC[15]
|
||||
sda-pinmux = <0x0300119c 0x4 0x3>; // PAD_MIPI_TXM1/IIC2_SDA/XGPIOC[14]
|
||||
/* gpio port */
|
||||
scl-gpios = <&portc 15 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&portc 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x03001014 0x0 0x3>; // IIC3_SCL/IIC3_SCL/XGPIOA[5]
|
||||
sda-pinmux = <0x03001018 0x0 0x3>; // IIC3_SDA/IIC3_SDA/XGPIOA[6]
|
||||
/* gpio port */
|
||||
scl-gpios = <&porta 5 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x030010f0 0x2 0x3>; // ADC3/IIC4_SCL/XGPIOB[1]
|
||||
sda-pinmux = <0x030010f4 0x2 0x3>; // ADC2/IIC4_SDA/XGPIOB[2]
|
||||
/* gpio port */
|
||||
scl-gpios = <&portb 1 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&portb 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/ {
|
||||
/delete-node/ wifi-sd@4320000;
|
||||
/delete-node/ i2s@04110000;
|
||||
/delete-node/ i2s@04120000;
|
||||
/delete-node/ sound_ext1;
|
||||
/delete-node/ sound_ext2;
|
||||
/delete-node/ sound_PDM;
|
||||
|
||||
wifi_pin {
|
||||
compatible = "cvitek,wifi-pin";
|
||||
poweron-gpio = <&porte 2 GPIO_ACTIVE_HIGH>;
|
||||
wakeup-gpio = <&porte 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
};
|
||||
@ -1,4 +0,0 @@
|
||||
/ {
|
||||
/delete-node/ cv-emmc@4300000;
|
||||
/delete-node/ cv-spinf@4060000;
|
||||
};
|
||||
@ -1,5 +0,0 @@
|
||||
/ {
|
||||
/delete-node/ cvi-spif@10000000;
|
||||
/delete-node/ cv-emmc@4300000;
|
||||
};
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
/ {
|
||||
/delete-node/ cv-emmc@4300000;
|
||||
/delete-node/ cv-spinf@4060000;
|
||||
};
|
||||
|
||||
@ -1,932 +0,0 @@
|
||||
|
||||
/ {
|
||||
compatible = "cvitek,cv181x";
|
||||
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
top_misc:top_misc_ctrl@3000000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0x03000000 0x0 0x8000>;
|
||||
};
|
||||
|
||||
clk_rst: clk-reset-controller {
|
||||
#reset-cells = <1>;
|
||||
compatible = "cvitek,clk-reset";
|
||||
reg = <0x0 0x03002000 0x0 0x8>;
|
||||
};
|
||||
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "osc";
|
||||
};
|
||||
|
||||
clk: clock-controller {
|
||||
compatible = "cvitek,cv181x-clk";
|
||||
reg = <0x0 0x03002000 0x0 0x1000>;
|
||||
clocks = <&osc>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
rst: reset-controller {
|
||||
#reset-cells = <1>;
|
||||
compatible = "cvitek,reset";
|
||||
reg = <0x0 0x03003000 0x0 0x10>;
|
||||
};
|
||||
|
||||
restart: restart-controller {
|
||||
compatible = "cvitek,restart";
|
||||
reg = <0x0 0x05025000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
tpu {
|
||||
compatible = "cvitek,tpu";
|
||||
reg-names = "tdma", "tiu";
|
||||
reg = <0x0 0x0C100000 0x0 0x1000>,
|
||||
<0x0 0x0C101000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_TPU>, <&clk CV181X_CLK_TPU_FAB>;
|
||||
clock-names = "clk_tpu_axi", "clk_tpu_fab";
|
||||
resets = <&rst RST_TDMA>, <&rst RST_TPU>, <&rst RST_TPUSYS>;
|
||||
reset-names = "res_tdma", "res_tpu", "res_tpusys";
|
||||
};
|
||||
|
||||
mon {
|
||||
compatible = "cvitek,mon";
|
||||
reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
|
||||
reg = <0x0 0x01040000 0x0 0x1000>,
|
||||
<0x0 0x08004000 0x0 0x1000>,
|
||||
<0x0 0x08006000 0x0 0x1000>,
|
||||
<0x0 0x08008000 0x0 0x1000>,
|
||||
<0x0 0x0800A000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
wiegand0 {
|
||||
compatible = "cvitek,wiegand";
|
||||
reg-names = "wiegand";
|
||||
reg = <0x0 0x03030000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN0>;
|
||||
clock-names = "clk_wgn", "clk_wgn1";
|
||||
resets = <&rst RST_WGN0>;
|
||||
reset-names = "res_wgn";
|
||||
};
|
||||
|
||||
wiegand1 {
|
||||
compatible = "cvitek,wiegand";
|
||||
reg-names = "wiegand";
|
||||
reg = <0x0 0x03031000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN1>;
|
||||
clock-names = "clk_wgn", "clk_wgn1";
|
||||
resets = <&rst RST_WGN1>;
|
||||
reset-names = "res_wgn";
|
||||
};
|
||||
|
||||
wiegand2 {
|
||||
compatible = "cvitek,wiegand";
|
||||
reg-names = "wiegand";
|
||||
reg = <0x0 0x03032000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN2>;
|
||||
clock-names = "clk_wgn", "clk_wgn1";
|
||||
resets = <&rst RST_WGN2>;
|
||||
reset-names = "res_wgn";
|
||||
};
|
||||
|
||||
saradc {
|
||||
compatible = "cvitek,saradc";
|
||||
reg-names = "top_domain_saradc", "rtc_domain_saradc";
|
||||
reg = <0x0 0x030F0000 0x0 0x1000>, <0x0 0x0502c000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_SARADC>;
|
||||
clock-names = "clk_saradc";
|
||||
resets = <&rst RST_SARADC>;
|
||||
reset-names = "res_saradc";
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "cvitek,rtc";
|
||||
reg = <0x0 0x05026000 0x0 0x1000>,<0x0 0x05025000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_RTC_25M>;
|
||||
clock-names = "clk_rtc";
|
||||
};
|
||||
|
||||
cvitek-ion {
|
||||
compatible = "cvitek,cvitek-ion";
|
||||
|
||||
heap_carveout@0 {
|
||||
compatible = "cvitek,carveout";
|
||||
memory-region = <&ion_reserved>;
|
||||
};
|
||||
};
|
||||
|
||||
sysdma_remap {
|
||||
compatible = "cvitek,sysdma_remap";
|
||||
reg = <0x0 0x03000154 0x0 0x10>;
|
||||
ch-remap = <CVI_I2S0_RX CVI_I2S2_TX CVI_I2S1_RX CVI_I2S1_TX
|
||||
CVI_SPI_NAND CVI_SPI_NAND CVI_I2S2_RX CVI_I2S3_TX>;
|
||||
int_mux_base = <0x03000298>;
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
compatible = "snps,dmac-bm";
|
||||
reg = <0x0 0x04330000 0x0 0x1000>;
|
||||
clock-names = "clk_sdma_axi";
|
||||
clocks = <&clk CV181X_CLK_SDMA_AXI>;
|
||||
|
||||
dma-channels = /bits/ 8 <8>;
|
||||
#dma-cells = <3>;
|
||||
dma-requests = /bits/ 8 <16>;
|
||||
chan_allocation_order = /bits/ 8 <0>;
|
||||
chan_priority = /bits/ 8 <1>;
|
||||
block_size = <1024>;
|
||||
dma-masters = /bits/ 8 <2>;
|
||||
data-width = <4 4>; /* bytes */
|
||||
axi_tr_width = <4>; /* bytes */
|
||||
block-ts = <15>;
|
||||
};
|
||||
|
||||
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0x0 0x03010000 0x0 0x1000>;
|
||||
resets = <&rst RST_WDT>;
|
||||
clocks = <&pclk>;
|
||||
};
|
||||
|
||||
pwm0: pwm@3060000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3060000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <1>;
|
||||
};
|
||||
|
||||
pwm1: pwm@3061000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3061000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
pwm2: pwm@3062000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3062000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
pwm3: pwm@3063000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3063000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <4>;
|
||||
};
|
||||
|
||||
pclk: pclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
compatible = "cvitek,cv1835-spinf";
|
||||
reg = <0x0 0x4060000 0x0 0x1000>;
|
||||
reg-names = "core_mem";
|
||||
bus-width = <4>;
|
||||
dmas = <&dmac 4 1 1
|
||||
&dmac 5 1 1>;
|
||||
dma-names = "rx","tx";
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
compatible = "cvitek,cvi-spif";
|
||||
bus-num = <0>;
|
||||
reg = <0x0 0x10000000 0x0 0x10000000>;
|
||||
reg-names = "spif";
|
||||
sck-div = <3>;
|
||||
sck_mhz = <300>;
|
||||
spi-max-frequency = <75000000>;
|
||||
spiflash {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x04180000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x04190000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x041A0000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x041B0000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#if 0
|
||||
dmas = <&dmac 2 1 1
|
||||
&dmac 3 1 1>;
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
#endif
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04140000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04150000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04160000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04170000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x041C0000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03020000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "porta";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03021000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portb: gpio-controller@1 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portb";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03022000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portc: gpio-controller@2 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portc";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03023000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portd: gpio-controller@3 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portd";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x05021000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porte: gpio-controller@4 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "porte";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04000000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
resets = <&rst RST_I2C0>;
|
||||
reset-names = "i2c0";
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04010000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
resets = <&rst RST_I2C1>;
|
||||
reset-names = "i2c1";
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04020000 0x0 0x1000>;
|
||||
clock-frequency = <100000>;
|
||||
resets = <&rst RST_I2C2>;
|
||||
reset-names = "i2c2";
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04030000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
resets = <&rst RST_I2C3>;
|
||||
reset-names = "i2c3";
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04040000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
resets = <&rst RST_I2C4>;
|
||||
reset-names = "i2c4";
|
||||
};
|
||||
|
||||
eth_csrclk: eth_csrclk {
|
||||
clock-output-names = "eth_csrclk";
|
||||
clock-frequency = <250000000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
eth_ptpclk: eth_ptpclk {
|
||||
clock-output-names = "eth_ptpclk";
|
||||
clock-frequency = <50000000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,wr_osr_lmt = <1>;
|
||||
snps,rd_osr_lmt = <2>;
|
||||
snps,blen = <4 8 16 0 0 0 0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
|
||||
mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
compatible = "cvitek,ethernet";
|
||||
reg = <0x0 0x04070000 0x0 0x10000>;
|
||||
clock-names = "stmmaceth", "ptp_ref";
|
||||
clocks = <ð_csrclk>, <ð_ptpclk>;
|
||||
//phy-reset-gpios = <&porta 26 0>;
|
||||
|
||||
tx-fifo-depth = <8192>;
|
||||
rx-fifo-depth = <8192>;
|
||||
/* no hash filter and perfect filter support */
|
||||
snps,multicast-filter-bins = <0>;
|
||||
snps,perfect-filter-entries = <1>;
|
||||
|
||||
snps,txpbl = <8>;
|
||||
snps,rxpbl = <8>;
|
||||
snps,aal;
|
||||
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup>;
|
||||
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
emmc:cv-emmc@4300000 {
|
||||
compatible = "cvitek,cv181x-emmc";
|
||||
reg = <0x0 0x4300000 0x0 0x1000>;
|
||||
reg-names = "core_mem";
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>;
|
||||
max-frequency = <200000000>;
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
pll_index = <0x5>;
|
||||
pll_reg = <0x3002064>;
|
||||
};
|
||||
|
||||
sd:cv-sd@4310000 {
|
||||
compatible = "cvitek,cv181x-sd";
|
||||
reg = <0x0 0x4310000 0x0 0x1000>;
|
||||
reg-names = "core_mem";
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
/*no-1-8-v;*/
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>;
|
||||
max-frequency = <200000000>;
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
reset-names = "sdhci";
|
||||
pll_index = <0x6>;
|
||||
pll_reg = <0x3002070>;
|
||||
cvi-cd-gpios = <&porta 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
compatible = "cvitek,cv181x-sdio";
|
||||
bus-width = <4>;
|
||||
reg = <0x0 0x4320000 0x0 0x1000>;
|
||||
reg_names = "core_mem";
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>;
|
||||
max-frequency = <50000000>;
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
non-removable;
|
||||
pll_index = <0x7>;
|
||||
pll_reg = <0x300207C>;
|
||||
no-mmc;
|
||||
no-sd;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s_mclk: i2s_mclk {
|
||||
clock-output-names = "i2s_mclk";
|
||||
clock-frequency = <24576000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
i2s_subsys {
|
||||
compatible = "cvitek,i2s_tdm_subsys";
|
||||
reg = <0x0 0x04108000 0x0 0x100>;
|
||||
clocks = <&i2s_mclk>, <&clk CV181X_CLK_A0PLL>,
|
||||
<&clk CV181X_CLK_SDMA_AUD0>, <&clk CV181X_CLK_SDMA_AUD1>,
|
||||
<&clk CV181X_CLK_SDMA_AUD2>, <&clk CV181X_CLK_SDMA_AUD3>;
|
||||
clock-names = "i2sclk", "clk_a0pll",
|
||||
"clk_sdma_aud0", "clk_sdma_aud1",
|
||||
"clk_sdma_aud2", "clk_sdma_aud3";
|
||||
master_base = <0x04110000>; /* I2S1 is master, only useful while using multi I2S IPs work on same IO */
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04100000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <0>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 0 1 1>; /* read channel */
|
||||
dma-names = "rx";
|
||||
capability = "rx"; /* I2S0 connect to internal ADC as RX */
|
||||
mclk_out = "false";
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04110000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <1>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 2 1 1 /* read channel */
|
||||
&dmac 3 1 1>; /* write channel */
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
mclk_out = "false";
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04120000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <2>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 6 1 1 /* read channel */
|
||||
&dmac 1 1 1>; /* write channel */
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
mclk_out = "false";
|
||||
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04130000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <3>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 7 1 1>; /* write channel */
|
||||
dma-names = "tx";
|
||||
capability = "tx"; /* I2S3 connect to internal DAC as TX */
|
||||
mclk_out = "true";
|
||||
};
|
||||
|
||||
adc: adc@0300A100 {
|
||||
compatible = "cvitek,cv182xaadc";
|
||||
reg = <0x0 0x0300A100 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
clk_source = <0x04130000>; /* MCLK source is I2S3 */
|
||||
};
|
||||
|
||||
dac: dac@0300A000 {
|
||||
compatible = "cvitek,cv182xadac";
|
||||
reg = <0x0 0x0300A000 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
};
|
||||
|
||||
pdm: pdm@0x041D0C00 {
|
||||
compatible = "cvitek,cv1835pdm";
|
||||
reg = <0x0 0x041D0C00 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
};
|
||||
|
||||
sound_adc {
|
||||
compatible = "cvitek,cv182xa-adc";
|
||||
cvi,model = "CV182XA";
|
||||
cvi,card_name = "cv182xa_adc";
|
||||
};
|
||||
|
||||
sound_dac {
|
||||
compatible = "cvitek,cv182xa-dac";
|
||||
cvi,model = "CV182XA";
|
||||
cvi,card_name = "cv182xa_dac";
|
||||
};
|
||||
|
||||
sound_PDM {
|
||||
compatible = "cvitek,cv182x-pdm";
|
||||
cvi,model = "CV182X";
|
||||
cvi,card_name = "cv182x_internal_PDM";
|
||||
};
|
||||
|
||||
wifi_pin {
|
||||
compatible = "cvitek,wifi-pin";
|
||||
poweron-gpio = <&porta 18 GPIO_ACTIVE_HIGH>;
|
||||
wakeup-gpio = <&porte 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
bt_pin {
|
||||
compatible = "cvitek,bt-pin";
|
||||
poweron-gpio = <&porte 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
compatible = "cvitek,cif";
|
||||
reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
|
||||
<0x0 0x0a0c4000 0x0 0x2000>, <0x0 0x0a0c6000 0x0 0x2000>,
|
||||
<0x0 0x03001c30 0x0 0x30>;
|
||||
reg-names = "csi_mac0", "csi_wrap0", "csi_mac1", "csi_mac2", "pad_ctrl";
|
||||
snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>;
|
||||
resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
|
||||
<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
|
||||
reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
|
||||
clocks = <&clk CV181X_CLK_CAM0>, <&clk CV181X_CLK_CAM1>, <&clk CV181X_CLK_SRC_VIP_SYS_2>,
|
||||
<&clk CV181X_CLK_MIPIMPLL>, <&clk CV181X_CLK_DISPPLL>, <&clk CV181X_CLK_FPLL>;
|
||||
clock-names = "clk_cam0", "clk_cam1", "clk_sys_2",
|
||||
"clk_mipimpll", "clk_disppll", "clk_fpll";
|
||||
};
|
||||
|
||||
mipi_tx: mipi_tx {
|
||||
compatible = "cvitek,mipi_tx";
|
||||
reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
|
||||
pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
|
||||
power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&clk CV181X_CLK_DISP_VIP>, <&clk CV181X_CLK_DSI_MAC_VIP>;
|
||||
clock-names = "clk_disp", "clk_dsi";
|
||||
};
|
||||
|
||||
sys {
|
||||
compatible = "cvitek,sys";
|
||||
};
|
||||
|
||||
base {
|
||||
compatible = "cvitek,base";
|
||||
reg = <0x0 0x0a0c8000 0x0 0x20>;
|
||||
reg-names = "vip_sys";
|
||||
};
|
||||
|
||||
vi {
|
||||
compatible = "cvitek,vi";
|
||||
reg = <0x0 0x0a000000 0x0 0x80000>;
|
||||
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_SRC_VIP_SYS_3>,
|
||||
<&clk CV181X_CLK_AXI_VIP>, <&clk CV181X_CLK_CSI_BE_VIP>,
|
||||
<&clk CV181X_CLK_RAW_VIP>, <&clk CV181X_CLK_ISP_TOP_VIP>,
|
||||
<&clk CV181X_CLK_CSI_MAC0_VIP>, <&clk CV181X_CLK_CSI_MAC1_VIP>,
|
||||
<&clk CV181X_CLK_CSI_MAC2_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1", "clk_sys_2", "clk_sys_3",
|
||||
"clk_axi", "clk_csi_be", "clk_raw", "clk_isp_top",
|
||||
"clk_csi_mac0", "clk_csi_mac1", "clk_csi_mac2";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
vpss {
|
||||
compatible = "cvitek,vpss";
|
||||
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
|
||||
reg-names = "sc";
|
||||
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_IMG_D_VIP>,
|
||||
<&clk CV181X_CLK_IMG_V_VIP>, <&clk CV181X_CLK_SC_TOP_VIP>,
|
||||
<&clk CV181X_CLK_SC_D_VIP>, <&clk CV181X_CLK_SC_V1_VIP>,
|
||||
<&clk CV181X_CLK_SC_V2_VIP>, <&clk CV181X_CLK_SC_V3_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1",
|
||||
"clk_sys_2", "clk_img_d",
|
||||
"clk_img_v", "clk_sc_top",
|
||||
"clk_sc_d", "clk_sc_v1",
|
||||
"clk_sc_v2", "clk_sc_v3";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
ive {
|
||||
compatible = "cvitek,ive";
|
||||
reg = <0x0 0x0A0A0000 0x0 0x3100>;
|
||||
reg-names = "ive_base";
|
||||
};
|
||||
|
||||
vo:vo {
|
||||
compatible = "cvitek,vo";
|
||||
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0c8000 0x0 0xa0>, <0x0 0x0a0d1000 0x0 0x100>;
|
||||
reg-names = "sc", "vip_sys", "dphy";
|
||||
clocks = <&clk CV181X_CLK_DISP_VIP>, <&clk CV181X_CLK_DSI_MAC_VIP>, <&clk CV181X_CLK_BT_VIP>;
|
||||
reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
|
||||
pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
|
||||
power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
|
||||
clock-names = "clk_disp", "clk_dsi", "clk_bt";
|
||||
};
|
||||
|
||||
#if (CVIMMAP_FRAMEBUFFER_SIZE > 0)
|
||||
reserved-memory {
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
ranges;
|
||||
|
||||
fb_reserved: cvifb {
|
||||
alloc-ranges = <0x0 CVIMMAP_FRAMEBUFFER_ADDR 0 CVIMMAP_FRAMEBUFFER_SIZE>;
|
||||
size = <0x0 CVIMMAP_FRAMEBUFFER_SIZE>;
|
||||
};
|
||||
};
|
||||
|
||||
cvifb {
|
||||
compatible = "cvitek,fb";
|
||||
memory-region = <&fb_reserved>;
|
||||
reg = <0x0 0x0a088000 0x0 0x1000>;
|
||||
reg-names = "disp";
|
||||
};
|
||||
#endif
|
||||
dwa {
|
||||
compatible = "cvitek,dwa";
|
||||
reg = <0x0 0x0a0c0000 0x0 0x1000>;
|
||||
reg-names = "dwa";
|
||||
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_SRC_VIP_SYS_3>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_4>, <&clk CV181X_CLK_DWA_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1",
|
||||
"clk_sys_2", "clk_sys_3",
|
||||
"clk_sys_4", "clk_dwa";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
rgn {
|
||||
compatible = "cvitek,rgn";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
compatible = "cvitek,asic-vcodec";
|
||||
reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>,
|
||||
<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
|
||||
reg-names = "h265","h264","vc_ctrl","vc_sbm","vc_addr_remap";
|
||||
clocks = <&clk CV181X_CLK_AXI_VIDEO_CODEC>,
|
||||
<&clk CV181X_CLK_H264C>, <&clk CV181X_CLK_APB_H264C>,
|
||||
<&clk CV181X_CLK_H265C>, <&clk CV181X_CLK_APB_H265C>,
|
||||
<&clk CV181X_CLK_VC_SRC0>, <&clk CV181X_CLK_VC_SRC1>,
|
||||
<&clk CV181X_CLK_VC_SRC2>, <&clk CV181X_CLK_CFG_REG_VC>;
|
||||
clock-names = "clk_axi_video_codec",
|
||||
"clk_h264c", "clk_apb_h264c",
|
||||
"clk_h265c", "clk_apb_h265c",
|
||||
"clk_vc_src0", "clk_vc_src1",
|
||||
"clk_vc_src2", "clk_cfg_reg_vc";
|
||||
};
|
||||
|
||||
jpu {
|
||||
compatible = "cvitek,asic-jpeg";
|
||||
reg = <0x0 0x0B000000 0x0 0x300>,<0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>;
|
||||
reg-names = "jpeg","vc_ctrl","vc_sbm";
|
||||
clocks = <&clk CV181X_CLK_AXI_VIDEO_CODEC>,
|
||||
<&clk CV181X_CLK_JPEG>, <&clk CV181X_CLK_APB_JPEG>,
|
||||
<&clk CV181X_CLK_VC_SRC0>, <&clk CV181X_CLK_VC_SRC1>,
|
||||
<&clk CV181X_CLK_VC_SRC2>, <&clk CV181X_CLK_CFG_REG_VC>;
|
||||
clock-names = "clk_axi_video_codec",
|
||||
"clk_jpeg", "clk_apb_jpeg",
|
||||
"clk_vc_src0", "clk_vc_src1",
|
||||
"clk_vc_src2", "clk_cfg_reg_vc";
|
||||
resets = <&rst RST_JPEG>;
|
||||
reset-names = "jpeg";
|
||||
};
|
||||
|
||||
cvi_vc_drv {
|
||||
compatible = "cvitek,cvi_vc_drv";
|
||||
reg = <0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
|
||||
reg-names = "vc_ctrl","vc_sbm","vc_addr_remap";
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
compatible = "cvitek,rtos_cmdqu";
|
||||
reg = <0x0 0x01900000 0x0 0x1000>;
|
||||
reg-names = "mailbox";
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
compatible = "cvitek,cv182x-usb";
|
||||
reg = <0x0 0x04340000 0x0 0x10000>,
|
||||
<0x0 0x03006000 0x0 0x58>; //USB 2.0 PHY
|
||||
dr_mode = "otg";
|
||||
g-use-dma;
|
||||
g-rx-fifo-size = <536>;
|
||||
g-np-tx-fifo-size = <32>;
|
||||
g-tx-fifo-size = <768 512 512 384 128 128>;
|
||||
clocks = <&clk CV181X_CLK_AXI4_USB>,
|
||||
<&clk CV181X_CLK_APB_USB>,
|
||||
<&clk CV181X_CLK_125M_USB>,
|
||||
<&clk CV181X_CLK_33K_USB>,
|
||||
<&clk CV181X_CLK_12M_USB>;
|
||||
clock-names = "clk_axi", "clk_apb", "clk_125m", "clk_33k", "clk_12m";
|
||||
vbus-gpio = <&portb 6 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
compatible = "cvitek,cv181x-thermal";
|
||||
reg = <0x0 0x030E0000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_TEMPSEN>;
|
||||
clock-names = "clk_tempsen";
|
||||
reset-names = "tempsen";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
soc_thermal_0: soc_thermal_0 {
|
||||
polling-delay-passive = <1000>; /* milliseconds */
|
||||
polling-delay = <1000>; /* milliseconds */
|
||||
thermal-sensors = <&thermal 0>;
|
||||
|
||||
trips {
|
||||
soc_thermal_trip_0: soc_thermal_trip_0 {
|
||||
temperature = <100000>; /* millicelsius */
|
||||
hysteresis = <5000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
soc_thermal_trip_1: soc_thermal_trip_1 {
|
||||
temperature = <110000>; /* millicelsius */
|
||||
hysteresis = <5000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
soc_thermal_crtical_0: soc_thermal_crtical_0 {
|
||||
temperature = <130000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#if 0
|
||||
cvipctrl: pinctrl@3001000 {
|
||||
compatible = "cvitek,pinctrl-cv182x";
|
||||
reg = <0 0x03001000 0 0x1000>;
|
||||
};
|
||||
#endif
|
||||
|
||||
cviaudio_core {
|
||||
compatible = "cvitek,audio";
|
||||
};
|
||||
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
#if 0
|
||||
clock-frequency = <12288000>;
|
||||
#else
|
||||
clock-frequency = <24576000>;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
//spi0 = &spi0;
|
||||
//spi1 = &spi1;
|
||||
//spi2 = &spi2;
|
||||
//spi3 = &spi3;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
ethernet0 = ðernet0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,25 +0,0 @@
|
||||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00 CVIMMAP_KERNEL_MEMORY_ADDR 0x00 CVIMMAP_KERNEL_MEMORY_SIZE>;
|
||||
};
|
||||
|
||||
|
||||
fast_image {
|
||||
compatible = "cvitek,rtos_image";
|
||||
reg-names = "rtos_region";
|
||||
reg = <0x0 CVIMMAP_FREERTOS_ADDR 0x0 CVIMMAP_FREERTOS_SIZE>;
|
||||
ion-size = <CVIMMAP_FREERTOS_RESERVED_ION_SIZE>; //reserved ion size for freertos
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
ranges;
|
||||
|
||||
ion_reserved: ion {
|
||||
compatible = "ion-region";
|
||||
size = <0x0 CVIMMAP_ION_SIZE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,320 +0,0 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/cv181x-resets.h>
|
||||
#include <dt-bindings/clock/cv181x-clock.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/dma/cv181x-dmamap.h>
|
||||
#include "cvi_board_memmap.h"
|
||||
|
||||
/memreserve/ CVIMMAP_MONITOR_ADDR CVIMMAP_ATF_SIZE; // ATF (BL31 + BL32) 512KB
|
||||
|
||||
#include "cv181x_base.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Cvitek. CV181X ASIC. ARM.";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
gic: interrupt-controller {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
ranges;
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x3>;
|
||||
reg = <0x0 0x01F01000 0x0 0x1000>,
|
||||
<0x0 0x01F02000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&A53_0>;
|
||||
};
|
||||
|
||||
psci {
|
||||
migrate = <0xc4000005>;
|
||||
cpu_on = <0xc4000003>;
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_suspend = <0xc4000001>;
|
||||
sys_poweroff = <0x84000008>;
|
||||
sys_reset = <0x84000009>;
|
||||
method = "smc";
|
||||
compatible = "arm,psci-0.2", "arm,psci";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
|
||||
A53_0: cpu@0 {
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&CA53_L2>;
|
||||
};
|
||||
|
||||
CA53_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
always-on;
|
||||
clock-frequency = <25000000>;
|
||||
compatible = "arm,armv8-timer";
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
cv181x_cooling:cv181x_cooling {
|
||||
clocks = <&clk CV181X_CLK_A53>, <&clk CV181X_CLK_TPU>;
|
||||
clock-names = "clk_cpu", "clk_tpu_axi";
|
||||
dev-freqs = <800000000 500000000>,
|
||||
<400000000 375000000>,
|
||||
<400000000 300000000>;
|
||||
compatible = "cvitek,cv181x-cooling";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
tpu {
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
mon {
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
wiegand0 {
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wiegand1 {
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wiegand2 {
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
saradc {
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sysdma_remap {
|
||||
int_mux = <0x1FF>; /* enable bit [0..8] for CPU0(CA53) */
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
#if 0
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
#endif
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
porta: gpio-controller@0 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
portb: gpio-controller@1 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
portc: gpio-controller@2 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
portd: gpio-controller@3 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
porte: gpio-controller@4 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
interrupt-names = "macirq";
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emmc:cv-emmc@4300000 {
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sd:cv-sd@4310000 {
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "csi0", "csi1";
|
||||
};
|
||||
|
||||
vi {
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "isp";
|
||||
};
|
||||
|
||||
ive {
|
||||
interrupt-names = "ive_irq";
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
vpss {
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sc";
|
||||
};
|
||||
|
||||
dwa {
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dwa";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "h265","h264","sbm";
|
||||
};
|
||||
|
||||
jpu {
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "jpeg";
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mailbox";
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tempsen";
|
||||
};
|
||||
|
||||
};
|
||||
@ -1,320 +0,0 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/cv181x-resets.h>
|
||||
#include <dt-bindings/clock/cv181x-clock.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/dma/cv181x-dmamap.h>
|
||||
#include "cvi_board_memmap.h"
|
||||
|
||||
/memreserve/ CVIMMAP_MONITOR_ADDR CVIMMAP_ATF_SIZE; // ATF (BL31 + BL32) 512KB
|
||||
|
||||
#include "cv181x_base.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Cvitek. CV181X ASIC. ARM.";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
gic: interrupt-controller {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
ranges;
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x3>;
|
||||
reg = <0x0 0x01F01000 0x0 0x1000>,
|
||||
<0x0 0x01F02000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&A53_0>;
|
||||
};
|
||||
|
||||
psci {
|
||||
migrate = <0xc4000005>;
|
||||
cpu_on = <0xc4000003>;
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_suspend = <0xc4000001>;
|
||||
sys_poweroff = <0x84000008>;
|
||||
sys_reset = <0x84000009>;
|
||||
method = "smc";
|
||||
compatible = "arm,psci-0.2", "arm,psci";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
|
||||
A53_0: cpu@0 {
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&CA53_L2>;
|
||||
};
|
||||
|
||||
CA53_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
always-on;
|
||||
clock-frequency = <25000000>;
|
||||
compatible = "arm,armv8-timer";
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
cv181x_cooling:cv181x_cooling {
|
||||
clocks = <&clk CV181X_CLK_A53>, <&clk CV181X_CLK_TPU>;
|
||||
clock-names = "clk_cpu", "clk_tpu_axi";
|
||||
dev-freqs = <800000000 500000000>,
|
||||
<400000000 375000000>,
|
||||
<400000000 300000000>;
|
||||
compatible = "cvitek,cv181x-cooling";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
tpu {
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
mon {
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
wiegand0 {
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wiegand1 {
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wiegand2 {
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
saradc {
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sysdma_remap {
|
||||
int_mux = <0x1FF>; /* enable bit [0..8] for CPU0(CA53) */
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
#if 0
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
#endif
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
porta: gpio-controller@0 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
portb: gpio-controller@1 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
portc: gpio-controller@2 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
portd: gpio-controller@3 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
porte: gpio-controller@4 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
interrupt-names = "macirq";
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emmc:cv-emmc@4300000 {
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sd:cv-sd@4310000 {
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "csi0", "csi1";
|
||||
};
|
||||
|
||||
vi {
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "isp";
|
||||
};
|
||||
|
||||
ive {
|
||||
interrupt-names = "ive_irq";
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
vpss {
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sc";
|
||||
};
|
||||
|
||||
dwa {
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dwa";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "h265","h264","sbm";
|
||||
};
|
||||
|
||||
jpu {
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "jpeg";
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mailbox";
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tempsen";
|
||||
};
|
||||
|
||||
};
|
||||
@ -1,372 +0,0 @@
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/cv181x-resets.h>
|
||||
#include <dt-bindings/clock/cv181x-clock.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/dma/cv181x-dmamap.h>
|
||||
#include "cvi_board_memmap.h"
|
||||
|
||||
/*
|
||||
* OpenSBI will add below subnode into reserved memory automatically
|
||||
* mmode_resv0@80000000 {
|
||||
* reg = <0x00 0x80000000 0x00 0x20000>;
|
||||
* phandle = <0x0d>;
|
||||
* };
|
||||
* Skip below to avoid lmb region reseved conflict in uboot.
|
||||
*
|
||||
*/
|
||||
#ifndef __UBOOT__
|
||||
/memreserve/ CVIMMAP_MONITOR_ADDR CVIMMAP_OPENSBI_SIZE; // OpenSBI
|
||||
#endif
|
||||
|
||||
#include "cv181x_base.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Cvitek. CV181X ASIC. C906.";
|
||||
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
timebase-frequency = <25000000>;
|
||||
|
||||
cpu-map {
|
||||
|
||||
cluster0 {
|
||||
|
||||
core0 {
|
||||
cpu = <0x01>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x00>;
|
||||
status = "okay";
|
||||
compatible = "riscv";
|
||||
riscv,isa = "rv64imafdvcsu";
|
||||
mmu-type = "riscv,sv39";
|
||||
clock-frequency = <25000000>;
|
||||
|
||||
cpu0_intc: interrupt-controller {
|
||||
#interrupt-cells = <0x01>;
|
||||
interrupt-controller;
|
||||
compatible = "riscv,cpu-intc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <0x02>;
|
||||
#size-cells = <0x02>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
plic0: interrupt-controller@70000000 {
|
||||
riscv,ndev = <101>;
|
||||
riscv,max-priority = <0x07>;
|
||||
reg-names = "control";
|
||||
reg = <0x00 0x70000000 0x00 0x4000000>;
|
||||
interrupts-extended = <&cpu0_intc 0xffffffff &cpu0_intc 0x09>;
|
||||
interrupt-controller;
|
||||
compatible = "riscv,plic0";
|
||||
#interrupt-cells = <0x02>;
|
||||
#address-cells = <0x00>;
|
||||
};
|
||||
|
||||
clint@74000000 {
|
||||
interrupts-extended = <&cpu0_intc 0x03 &cpu0_intc 0x07>;
|
||||
reg = <0x00 0x74000000 0x00 0x10000>;
|
||||
compatible = "riscv,clint0";
|
||||
clint,has-no-64bit-mmio;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
cv181x_cooling:cv181x_cooling {
|
||||
clocks = <&clk CV181X_CLK_C906_0>, <&clk CV181X_CLK_TPU>;
|
||||
clock-names = "clk_cpu", "clk_tpu_axi";
|
||||
dev-freqs = <850000000 500000000>,
|
||||
<425000000 375000000>,
|
||||
<425000000 300000000>;
|
||||
compatible = "cvitek,cv181x-cooling";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
tpu {
|
||||
interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tiu_irq", "tdma_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
mon {
|
||||
interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mon_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand0 {
|
||||
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand1 {
|
||||
interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand2 {
|
||||
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
saradc {
|
||||
interrupts = <100 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
sysdma_remap {
|
||||
int_mux = <0x7FC00>; /* enable bit [10..18] for CPU1(906B) */
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
porta: gpio-controller@0 {
|
||||
interrupt-controller;
|
||||
interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
portb: gpio-controller@1 {
|
||||
interrupt-controller;
|
||||
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
portc: gpio-controller@2 {
|
||||
interrupt-controller;
|
||||
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
portd: gpio-controller@3 {
|
||||
interrupt-controller;
|
||||
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
porte: gpio-controller@4 {
|
||||
interrupt-controller;
|
||||
interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
interrupt-names = "macirq";
|
||||
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
emmc:cv-emmc@4300000 {
|
||||
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
sd:cv-sd@4310000 {
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
vi {
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupt-names = "isp";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "h265","h264","sbm";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
jpu {
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "jpeg";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mailbox";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "csi0", "csi1";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
ive {
|
||||
interrupt-names = "ive_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
vpss {
|
||||
interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sc";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
dwa {
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dwa";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tempsen";
|
||||
};
|
||||
|
||||
};
|
||||
@ -1,16 +0,0 @@
|
||||
&dac{
|
||||
mute-gpio-l = <&porta 15 GPIO_ACTIVE_LOW>;
|
||||
mute-gpio-r = <&porta 30 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/ {
|
||||
/delete-node/ i2s@04110000;
|
||||
/delete-node/ i2s@04120000;
|
||||
/delete-node/ sound_ext1;
|
||||
/delete-node/ sound_ext2;
|
||||
/delete-node/ sound_PDM;
|
||||
};
|
||||
@ -1,4 +0,0 @@
|
||||
/ {
|
||||
/delete-node/ cvi-spif@10000000;
|
||||
/delete-node/ cv-spinf@4060000;
|
||||
};
|
||||
@ -1,118 +0,0 @@
|
||||
&sd {
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
&mipi_rx{
|
||||
snsr-reset = <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&mipi_tx {
|
||||
reset-gpio = <&porta 15 GPIO_ACTIVE_LOW>;
|
||||
pwm-gpio = <&porta 18 GPIO_ACTIVE_HIGH>;
|
||||
power-ct-gpio = <&porta 19 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&dac{
|
||||
mute-gpio-r = <&porte 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "disabled";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "disabled";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
status = "disabled";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi3 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x03001070 0x0 0x3>; // IIC0_SCL/IIC0_SCL/XGPIOA[28]
|
||||
sda-pinmux = <0x03001074 0x0 0x3>; // IIC0_SDA/IIC0_SDA/XGPIOA[29]
|
||||
/* gpio port */
|
||||
scl-gpios = <&porta 28 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&porta 29 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x03009408 0x2 0x3>; // SPI1_MOSI/IIC1_SCL/XGPIOB[7]
|
||||
sda-pinmux = <0x0300940c 0x2 0x3>; // SPI1_MISO/IIC1_SDA/XGPIOB[8]
|
||||
/* gpio port */
|
||||
scl-gpios = <&portb 7 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&portb 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x030011a0 0x4 0x3>; // PAD_MIPI_TXP1/IIC2_SCL/XGPIOC[15]
|
||||
sda-pinmux = <0x0300119c 0x4 0x3>; // PAD_MIPI_TXM1/IIC2_SDA/XGPIOC[14]
|
||||
/* gpio port */
|
||||
scl-gpios = <&portc 15 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&portc 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x03001014 0x0 0x3>; // IIC3_SCL/IIC3_SCL/XGPIOA[5]
|
||||
sda-pinmux = <0x03001018 0x0 0x3>; // IIC3_SDA/IIC3_SDA/XGPIOA[6]
|
||||
/* gpio port */
|
||||
scl-gpios = <&porta 5 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x030010f0 0x2 0x3>; // ADC3/IIC4_SCL/XGPIOB[1]
|
||||
sda-pinmux = <0x030010f4 0x2 0x3>; // ADC2/IIC4_SDA/XGPIOB[2]
|
||||
/* gpio port */
|
||||
scl-gpios = <&portb 1 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&portb 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/ {
|
||||
/delete-node/ wifi-sd@4320000;
|
||||
/delete-node/ i2s@04110000;
|
||||
/delete-node/ i2s@04120000;
|
||||
/delete-node/ sound_ext1;
|
||||
/delete-node/ sound_ext2;
|
||||
/delete-node/ sound_PDM;
|
||||
|
||||
wifi_pin {
|
||||
compatible = "cvitek,wifi-pin";
|
||||
poweron-gpio = <&porte 2 GPIO_ACTIVE_HIGH>;
|
||||
wakeup-gpio = <&porte 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
};
|
||||
@ -1,4 +0,0 @@
|
||||
/ {
|
||||
/delete-node/ cv-emmc@4300000;
|
||||
/delete-node/ cv-spinf@4060000;
|
||||
};
|
||||
@ -1,5 +0,0 @@
|
||||
/ {
|
||||
/delete-node/ cvi-spif@10000000;
|
||||
/delete-node/ cv-emmc@4300000;
|
||||
};
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
/ {
|
||||
/delete-node/ cv-emmc@4300000;
|
||||
/delete-node/ cv-spinf@4060000;
|
||||
};
|
||||
|
||||
@ -1,932 +0,0 @@
|
||||
|
||||
/ {
|
||||
compatible = "cvitek,cv181x";
|
||||
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
top_misc:top_misc_ctrl@3000000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0x03000000 0x0 0x8000>;
|
||||
};
|
||||
|
||||
clk_rst: clk-reset-controller {
|
||||
#reset-cells = <1>;
|
||||
compatible = "cvitek,clk-reset";
|
||||
reg = <0x0 0x03002000 0x0 0x8>;
|
||||
};
|
||||
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "osc";
|
||||
};
|
||||
|
||||
clk: clock-controller {
|
||||
compatible = "cvitek,cv181x-clk";
|
||||
reg = <0x0 0x03002000 0x0 0x1000>;
|
||||
clocks = <&osc>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
rst: reset-controller {
|
||||
#reset-cells = <1>;
|
||||
compatible = "cvitek,reset";
|
||||
reg = <0x0 0x03003000 0x0 0x10>;
|
||||
};
|
||||
|
||||
restart: restart-controller {
|
||||
compatible = "cvitek,restart";
|
||||
reg = <0x0 0x05025000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
tpu {
|
||||
compatible = "cvitek,tpu";
|
||||
reg-names = "tdma", "tiu";
|
||||
reg = <0x0 0x0C100000 0x0 0x1000>,
|
||||
<0x0 0x0C101000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_TPU>, <&clk CV181X_CLK_TPU_FAB>;
|
||||
clock-names = "clk_tpu_axi", "clk_tpu_fab";
|
||||
resets = <&rst RST_TDMA>, <&rst RST_TPU>, <&rst RST_TPUSYS>;
|
||||
reset-names = "res_tdma", "res_tpu", "res_tpusys";
|
||||
};
|
||||
|
||||
mon {
|
||||
compatible = "cvitek,mon";
|
||||
reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
|
||||
reg = <0x0 0x01040000 0x0 0x1000>,
|
||||
<0x0 0x08004000 0x0 0x1000>,
|
||||
<0x0 0x08006000 0x0 0x1000>,
|
||||
<0x0 0x08008000 0x0 0x1000>,
|
||||
<0x0 0x0800A000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
wiegand0 {
|
||||
compatible = "cvitek,wiegand";
|
||||
reg-names = "wiegand";
|
||||
reg = <0x0 0x03030000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN0>;
|
||||
clock-names = "clk_wgn", "clk_wgn1";
|
||||
resets = <&rst RST_WGN0>;
|
||||
reset-names = "res_wgn";
|
||||
};
|
||||
|
||||
wiegand1 {
|
||||
compatible = "cvitek,wiegand";
|
||||
reg-names = "wiegand";
|
||||
reg = <0x0 0x03031000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN1>;
|
||||
clock-names = "clk_wgn", "clk_wgn1";
|
||||
resets = <&rst RST_WGN1>;
|
||||
reset-names = "res_wgn";
|
||||
};
|
||||
|
||||
wiegand2 {
|
||||
compatible = "cvitek,wiegand";
|
||||
reg-names = "wiegand";
|
||||
reg = <0x0 0x03032000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN2>;
|
||||
clock-names = "clk_wgn", "clk_wgn1";
|
||||
resets = <&rst RST_WGN2>;
|
||||
reset-names = "res_wgn";
|
||||
};
|
||||
|
||||
saradc {
|
||||
compatible = "cvitek,saradc";
|
||||
reg-names = "top_domain_saradc", "rtc_domain_saradc";
|
||||
reg = <0x0 0x030F0000 0x0 0x1000>, <0x0 0x0502c000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_SARADC>;
|
||||
clock-names = "clk_saradc";
|
||||
resets = <&rst RST_SARADC>;
|
||||
reset-names = "res_saradc";
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "cvitek,rtc";
|
||||
reg = <0x0 0x05026000 0x0 0x1000>,<0x0 0x05025000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_RTC_25M>;
|
||||
clock-names = "clk_rtc";
|
||||
};
|
||||
|
||||
cvitek-ion {
|
||||
compatible = "cvitek,cvitek-ion";
|
||||
|
||||
heap_carveout@0 {
|
||||
compatible = "cvitek,carveout";
|
||||
memory-region = <&ion_reserved>;
|
||||
};
|
||||
};
|
||||
|
||||
sysdma_remap {
|
||||
compatible = "cvitek,sysdma_remap";
|
||||
reg = <0x0 0x03000154 0x0 0x10>;
|
||||
ch-remap = <CVI_I2S0_RX CVI_I2S2_TX CVI_I2S1_RX CVI_I2S1_TX
|
||||
CVI_SPI_NAND CVI_SPI_NAND CVI_I2S2_RX CVI_I2S3_TX>;
|
||||
int_mux_base = <0x03000298>;
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
compatible = "snps,dmac-bm";
|
||||
reg = <0x0 0x04330000 0x0 0x1000>;
|
||||
clock-names = "clk_sdma_axi";
|
||||
clocks = <&clk CV181X_CLK_SDMA_AXI>;
|
||||
|
||||
dma-channels = /bits/ 8 <8>;
|
||||
#dma-cells = <3>;
|
||||
dma-requests = /bits/ 8 <16>;
|
||||
chan_allocation_order = /bits/ 8 <0>;
|
||||
chan_priority = /bits/ 8 <1>;
|
||||
block_size = <1024>;
|
||||
dma-masters = /bits/ 8 <2>;
|
||||
data-width = <4 4>; /* bytes */
|
||||
axi_tr_width = <4>; /* bytes */
|
||||
block-ts = <15>;
|
||||
};
|
||||
|
||||
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0x0 0x03010000 0x0 0x1000>;
|
||||
resets = <&rst RST_WDT>;
|
||||
clocks = <&pclk>;
|
||||
};
|
||||
|
||||
pwm0: pwm@3060000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3060000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <1>;
|
||||
};
|
||||
|
||||
pwm1: pwm@3061000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3061000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
pwm2: pwm@3062000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3062000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
pwm3: pwm@3063000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3063000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <4>;
|
||||
};
|
||||
|
||||
pclk: pclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
compatible = "cvitek,cv1835-spinf";
|
||||
reg = <0x0 0x4060000 0x0 0x1000>;
|
||||
reg-names = "core_mem";
|
||||
bus-width = <4>;
|
||||
dmas = <&dmac 4 1 1
|
||||
&dmac 5 1 1>;
|
||||
dma-names = "rx","tx";
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
compatible = "cvitek,cvi-spif";
|
||||
bus-num = <0>;
|
||||
reg = <0x0 0x10000000 0x0 0x10000000>;
|
||||
reg-names = "spif";
|
||||
sck-div = <3>;
|
||||
sck_mhz = <300>;
|
||||
spi-max-frequency = <75000000>;
|
||||
spiflash {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x04180000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x04190000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x041A0000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x041B0000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#if 0
|
||||
dmas = <&dmac 2 1 1
|
||||
&dmac 3 1 1>;
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
#endif
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04140000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04150000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04160000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04170000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x041C0000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03020000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "porta";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03021000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portb: gpio-controller@1 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portb";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03022000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portc: gpio-controller@2 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portc";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03023000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portd: gpio-controller@3 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portd";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x05021000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porte: gpio-controller@4 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "porte";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04000000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
resets = <&rst RST_I2C0>;
|
||||
reset-names = "i2c0";
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04010000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
resets = <&rst RST_I2C1>;
|
||||
reset-names = "i2c1";
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04020000 0x0 0x1000>;
|
||||
clock-frequency = <100000>;
|
||||
resets = <&rst RST_I2C2>;
|
||||
reset-names = "i2c2";
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04030000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
resets = <&rst RST_I2C3>;
|
||||
reset-names = "i2c3";
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04040000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
resets = <&rst RST_I2C4>;
|
||||
reset-names = "i2c4";
|
||||
};
|
||||
|
||||
eth_csrclk: eth_csrclk {
|
||||
clock-output-names = "eth_csrclk";
|
||||
clock-frequency = <250000000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
eth_ptpclk: eth_ptpclk {
|
||||
clock-output-names = "eth_ptpclk";
|
||||
clock-frequency = <50000000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,wr_osr_lmt = <1>;
|
||||
snps,rd_osr_lmt = <2>;
|
||||
snps,blen = <4 8 16 0 0 0 0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
|
||||
mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
compatible = "cvitek,ethernet";
|
||||
reg = <0x0 0x04070000 0x0 0x10000>;
|
||||
clock-names = "stmmaceth", "ptp_ref";
|
||||
clocks = <ð_csrclk>, <ð_ptpclk>;
|
||||
//phy-reset-gpios = <&porta 26 0>;
|
||||
|
||||
tx-fifo-depth = <8192>;
|
||||
rx-fifo-depth = <8192>;
|
||||
/* no hash filter and perfect filter support */
|
||||
snps,multicast-filter-bins = <0>;
|
||||
snps,perfect-filter-entries = <1>;
|
||||
|
||||
snps,txpbl = <8>;
|
||||
snps,rxpbl = <8>;
|
||||
snps,aal;
|
||||
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup>;
|
||||
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
emmc:cv-emmc@4300000 {
|
||||
compatible = "cvitek,cv181x-emmc";
|
||||
reg = <0x0 0x4300000 0x0 0x1000>;
|
||||
reg-names = "core_mem";
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>;
|
||||
max-frequency = <200000000>;
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
pll_index = <0x5>;
|
||||
pll_reg = <0x3002064>;
|
||||
};
|
||||
|
||||
sd:cv-sd@4310000 {
|
||||
compatible = "cvitek,cv181x-sd";
|
||||
reg = <0x0 0x4310000 0x0 0x1000>;
|
||||
reg-names = "core_mem";
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
/*no-1-8-v;*/
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>;
|
||||
max-frequency = <200000000>;
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
reset-names = "sdhci";
|
||||
pll_index = <0x6>;
|
||||
pll_reg = <0x3002070>;
|
||||
cvi-cd-gpios = <&porta 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
compatible = "cvitek,cv181x-sdio";
|
||||
bus-width = <4>;
|
||||
reg = <0x0 0x4320000 0x0 0x1000>;
|
||||
reg_names = "core_mem";
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>;
|
||||
max-frequency = <50000000>;
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
non-removable;
|
||||
pll_index = <0x7>;
|
||||
pll_reg = <0x300207C>;
|
||||
no-mmc;
|
||||
no-sd;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s_mclk: i2s_mclk {
|
||||
clock-output-names = "i2s_mclk";
|
||||
clock-frequency = <24576000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
i2s_subsys {
|
||||
compatible = "cvitek,i2s_tdm_subsys";
|
||||
reg = <0x0 0x04108000 0x0 0x100>;
|
||||
clocks = <&i2s_mclk>, <&clk CV181X_CLK_A0PLL>,
|
||||
<&clk CV181X_CLK_SDMA_AUD0>, <&clk CV181X_CLK_SDMA_AUD1>,
|
||||
<&clk CV181X_CLK_SDMA_AUD2>, <&clk CV181X_CLK_SDMA_AUD3>;
|
||||
clock-names = "i2sclk", "clk_a0pll",
|
||||
"clk_sdma_aud0", "clk_sdma_aud1",
|
||||
"clk_sdma_aud2", "clk_sdma_aud3";
|
||||
master_base = <0x04110000>; /* I2S1 is master, only useful while using multi I2S IPs work on same IO */
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04100000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <0>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 0 1 1>; /* read channel */
|
||||
dma-names = "rx";
|
||||
capability = "rx"; /* I2S0 connect to internal ADC as RX */
|
||||
mclk_out = "false";
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04110000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <1>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 2 1 1 /* read channel */
|
||||
&dmac 3 1 1>; /* write channel */
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
mclk_out = "false";
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04120000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <2>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 6 1 1 /* read channel */
|
||||
&dmac 1 1 1>; /* write channel */
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
mclk_out = "false";
|
||||
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04130000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <3>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 7 1 1>; /* write channel */
|
||||
dma-names = "tx";
|
||||
capability = "tx"; /* I2S3 connect to internal DAC as TX */
|
||||
mclk_out = "true";
|
||||
};
|
||||
|
||||
adc: adc@0300A100 {
|
||||
compatible = "cvitek,cv182xaadc";
|
||||
reg = <0x0 0x0300A100 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
clk_source = <0x04130000>; /* MCLK source is I2S3 */
|
||||
};
|
||||
|
||||
dac: dac@0300A000 {
|
||||
compatible = "cvitek,cv182xadac";
|
||||
reg = <0x0 0x0300A000 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
};
|
||||
|
||||
pdm: pdm@0x041D0C00 {
|
||||
compatible = "cvitek,cv1835pdm";
|
||||
reg = <0x0 0x041D0C00 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
};
|
||||
|
||||
sound_adc {
|
||||
compatible = "cvitek,cv182xa-adc";
|
||||
cvi,model = "CV182XA";
|
||||
cvi,card_name = "cv182xa_adc";
|
||||
};
|
||||
|
||||
sound_dac {
|
||||
compatible = "cvitek,cv182xa-dac";
|
||||
cvi,model = "CV182XA";
|
||||
cvi,card_name = "cv182xa_dac";
|
||||
};
|
||||
|
||||
sound_PDM {
|
||||
compatible = "cvitek,cv182x-pdm";
|
||||
cvi,model = "CV182X";
|
||||
cvi,card_name = "cv182x_internal_PDM";
|
||||
};
|
||||
|
||||
wifi_pin {
|
||||
compatible = "cvitek,wifi-pin";
|
||||
poweron-gpio = <&porta 18 GPIO_ACTIVE_HIGH>;
|
||||
wakeup-gpio = <&porte 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
bt_pin {
|
||||
compatible = "cvitek,bt-pin";
|
||||
poweron-gpio = <&porte 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
compatible = "cvitek,cif";
|
||||
reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
|
||||
<0x0 0x0a0c4000 0x0 0x2000>, <0x0 0x0a0c6000 0x0 0x2000>,
|
||||
<0x0 0x03001c30 0x0 0x30>;
|
||||
reg-names = "csi_mac0", "csi_wrap0", "csi_mac1", "csi_mac2", "pad_ctrl";
|
||||
snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>;
|
||||
resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
|
||||
<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
|
||||
reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
|
||||
clocks = <&clk CV181X_CLK_CAM0>, <&clk CV181X_CLK_CAM1>, <&clk CV181X_CLK_SRC_VIP_SYS_2>,
|
||||
<&clk CV181X_CLK_MIPIMPLL>, <&clk CV181X_CLK_DISPPLL>, <&clk CV181X_CLK_FPLL>;
|
||||
clock-names = "clk_cam0", "clk_cam1", "clk_sys_2",
|
||||
"clk_mipimpll", "clk_disppll", "clk_fpll";
|
||||
};
|
||||
|
||||
mipi_tx: mipi_tx {
|
||||
compatible = "cvitek,mipi_tx";
|
||||
reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
|
||||
pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
|
||||
power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&clk CV181X_CLK_DISP_VIP>, <&clk CV181X_CLK_DSI_MAC_VIP>;
|
||||
clock-names = "clk_disp", "clk_dsi";
|
||||
};
|
||||
|
||||
sys {
|
||||
compatible = "cvitek,sys";
|
||||
};
|
||||
|
||||
base {
|
||||
compatible = "cvitek,base";
|
||||
reg = <0x0 0x0a0c8000 0x0 0x20>;
|
||||
reg-names = "vip_sys";
|
||||
};
|
||||
|
||||
vi {
|
||||
compatible = "cvitek,vi";
|
||||
reg = <0x0 0x0a000000 0x0 0x80000>;
|
||||
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_SRC_VIP_SYS_3>,
|
||||
<&clk CV181X_CLK_AXI_VIP>, <&clk CV181X_CLK_CSI_BE_VIP>,
|
||||
<&clk CV181X_CLK_RAW_VIP>, <&clk CV181X_CLK_ISP_TOP_VIP>,
|
||||
<&clk CV181X_CLK_CSI_MAC0_VIP>, <&clk CV181X_CLK_CSI_MAC1_VIP>,
|
||||
<&clk CV181X_CLK_CSI_MAC2_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1", "clk_sys_2", "clk_sys_3",
|
||||
"clk_axi", "clk_csi_be", "clk_raw", "clk_isp_top",
|
||||
"clk_csi_mac0", "clk_csi_mac1", "clk_csi_mac2";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
vpss {
|
||||
compatible = "cvitek,vpss";
|
||||
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
|
||||
reg-names = "sc";
|
||||
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_IMG_D_VIP>,
|
||||
<&clk CV181X_CLK_IMG_V_VIP>, <&clk CV181X_CLK_SC_TOP_VIP>,
|
||||
<&clk CV181X_CLK_SC_D_VIP>, <&clk CV181X_CLK_SC_V1_VIP>,
|
||||
<&clk CV181X_CLK_SC_V2_VIP>, <&clk CV181X_CLK_SC_V3_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1",
|
||||
"clk_sys_2", "clk_img_d",
|
||||
"clk_img_v", "clk_sc_top",
|
||||
"clk_sc_d", "clk_sc_v1",
|
||||
"clk_sc_v2", "clk_sc_v3";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
ive {
|
||||
compatible = "cvitek,ive";
|
||||
reg = <0x0 0x0A0A0000 0x0 0x3100>;
|
||||
reg-names = "ive_base";
|
||||
};
|
||||
|
||||
vo {
|
||||
compatible = "cvitek,vo";
|
||||
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0c8000 0x0 0xa0>, <0x0 0x0a0d1000 0x0 0x100>;
|
||||
reg-names = "sc", "vip_sys", "dphy";
|
||||
clocks = <&clk CV181X_CLK_DISP_VIP>, <&clk CV181X_CLK_DSI_MAC_VIP>, <&clk CV181X_CLK_BT_VIP>;
|
||||
reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
|
||||
pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
|
||||
power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
|
||||
clock-names = "clk_disp", "clk_dsi", "clk_bt";
|
||||
};
|
||||
|
||||
#if (CVIMMAP_FRAMEBUFFER_SIZE > 0)
|
||||
reserved-memory {
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
ranges;
|
||||
|
||||
fb_reserved: cvifb {
|
||||
alloc-ranges = <0x0 CVIMMAP_FRAMEBUFFER_ADDR 0 CVIMMAP_FRAMEBUFFER_SIZE>;
|
||||
size = <0x0 CVIMMAP_FRAMEBUFFER_SIZE>;
|
||||
};
|
||||
};
|
||||
|
||||
cvifb {
|
||||
compatible = "cvitek,fb";
|
||||
memory-region = <&fb_reserved>;
|
||||
reg = <0x0 0x0a088000 0x0 0x1000>;
|
||||
reg-names = "disp";
|
||||
};
|
||||
#endif
|
||||
dwa {
|
||||
compatible = "cvitek,dwa";
|
||||
reg = <0x0 0x0a0c0000 0x0 0x1000>;
|
||||
reg-names = "dwa";
|
||||
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_SRC_VIP_SYS_3>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_4>, <&clk CV181X_CLK_DWA_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1",
|
||||
"clk_sys_2", "clk_sys_3",
|
||||
"clk_sys_4", "clk_dwa";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
rgn {
|
||||
compatible = "cvitek,rgn";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
compatible = "cvitek,asic-vcodec";
|
||||
reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>,
|
||||
<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
|
||||
reg-names = "h265","h264","vc_ctrl","vc_sbm","vc_addr_remap";
|
||||
clocks = <&clk CV181X_CLK_AXI_VIDEO_CODEC>,
|
||||
<&clk CV181X_CLK_H264C>, <&clk CV181X_CLK_APB_H264C>,
|
||||
<&clk CV181X_CLK_H265C>, <&clk CV181X_CLK_APB_H265C>,
|
||||
<&clk CV181X_CLK_VC_SRC0>, <&clk CV181X_CLK_VC_SRC1>,
|
||||
<&clk CV181X_CLK_VC_SRC2>, <&clk CV181X_CLK_CFG_REG_VC>;
|
||||
clock-names = "clk_axi_video_codec",
|
||||
"clk_h264c", "clk_apb_h264c",
|
||||
"clk_h265c", "clk_apb_h265c",
|
||||
"clk_vc_src0", "clk_vc_src1",
|
||||
"clk_vc_src2", "clk_cfg_reg_vc";
|
||||
};
|
||||
|
||||
jpu {
|
||||
compatible = "cvitek,asic-jpeg";
|
||||
reg = <0x0 0x0B000000 0x0 0x300>,<0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>;
|
||||
reg-names = "jpeg","vc_ctrl","vc_sbm";
|
||||
clocks = <&clk CV181X_CLK_AXI_VIDEO_CODEC>,
|
||||
<&clk CV181X_CLK_JPEG>, <&clk CV181X_CLK_APB_JPEG>,
|
||||
<&clk CV181X_CLK_VC_SRC0>, <&clk CV181X_CLK_VC_SRC1>,
|
||||
<&clk CV181X_CLK_VC_SRC2>, <&clk CV181X_CLK_CFG_REG_VC>;
|
||||
clock-names = "clk_axi_video_codec",
|
||||
"clk_jpeg", "clk_apb_jpeg",
|
||||
"clk_vc_src0", "clk_vc_src1",
|
||||
"clk_vc_src2", "clk_cfg_reg_vc";
|
||||
resets = <&rst RST_JPEG>;
|
||||
reset-names = "jpeg";
|
||||
};
|
||||
|
||||
cvi_vc_drv {
|
||||
compatible = "cvitek,cvi_vc_drv";
|
||||
reg = <0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
|
||||
reg-names = "vc_ctrl","vc_sbm","vc_addr_remap";
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
compatible = "cvitek,rtos_cmdqu";
|
||||
reg = <0x0 0x01900000 0x0 0x1000>;
|
||||
reg-names = "mailbox";
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
compatible = "cvitek,cv182x-usb";
|
||||
reg = <0x0 0x04340000 0x0 0x10000>,
|
||||
<0x0 0x03006000 0x0 0x58>; //USB 2.0 PHY
|
||||
dr_mode = "otg";
|
||||
g-use-dma;
|
||||
g-rx-fifo-size = <536>;
|
||||
g-np-tx-fifo-size = <32>;
|
||||
g-tx-fifo-size = <768 512 512 384 128 128>;
|
||||
clocks = <&clk CV181X_CLK_AXI4_USB>,
|
||||
<&clk CV181X_CLK_APB_USB>,
|
||||
<&clk CV181X_CLK_125M_USB>,
|
||||
<&clk CV181X_CLK_33K_USB>,
|
||||
<&clk CV181X_CLK_12M_USB>;
|
||||
clock-names = "clk_axi", "clk_apb", "clk_125m", "clk_33k", "clk_12m";
|
||||
vbus-gpio = <&portb 6 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
compatible = "cvitek,cv181x-thermal";
|
||||
reg = <0x0 0x030E0000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_TEMPSEN>;
|
||||
clock-names = "clk_tempsen";
|
||||
reset-names = "tempsen";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
soc_thermal_0: soc_thermal_0 {
|
||||
polling-delay-passive = <1000>; /* milliseconds */
|
||||
polling-delay = <1000>; /* milliseconds */
|
||||
thermal-sensors = <&thermal 0>;
|
||||
|
||||
trips {
|
||||
soc_thermal_trip_0: soc_thermal_trip_0 {
|
||||
temperature = <100000>; /* millicelsius */
|
||||
hysteresis = <5000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
soc_thermal_trip_1: soc_thermal_trip_1 {
|
||||
temperature = <110000>; /* millicelsius */
|
||||
hysteresis = <5000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
soc_thermal_crtical_0: soc_thermal_crtical_0 {
|
||||
temperature = <130000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#if 0
|
||||
cvipctrl: pinctrl@3001000 {
|
||||
compatible = "cvitek,pinctrl-cv182x";
|
||||
reg = <0 0x03001000 0 0x1000>;
|
||||
};
|
||||
#endif
|
||||
|
||||
cviaudio_core {
|
||||
compatible = "cvitek,audio";
|
||||
};
|
||||
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
#if 0
|
||||
clock-frequency = <12288000>;
|
||||
#else
|
||||
clock-frequency = <24576000>;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
//spi0 = &spi0;
|
||||
//spi1 = &spi1;
|
||||
//spi2 = &spi2;
|
||||
//spi3 = &spi3;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
ethernet0 = ðernet0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,320 +0,0 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/cv181x-resets.h>
|
||||
#include <dt-bindings/clock/cv181x-clock.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/dma/cv181x-dmamap.h>
|
||||
#include "cvi_board_memmap.h"
|
||||
|
||||
/memreserve/ CVIMMAP_MONITOR_ADDR CVIMMAP_ATF_SIZE; // ATF (BL31 + BL32) 512KB
|
||||
|
||||
#include "soph_base.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SOPHGO ASIC. ARM.";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
gic: interrupt-controller {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
ranges;
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x3>;
|
||||
reg = <0x0 0x01F01000 0x0 0x1000>,
|
||||
<0x0 0x01F02000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&A53_0>;
|
||||
};
|
||||
|
||||
psci {
|
||||
migrate = <0xc4000005>;
|
||||
cpu_on = <0xc4000003>;
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_suspend = <0xc4000001>;
|
||||
sys_poweroff = <0x84000008>;
|
||||
sys_reset = <0x84000009>;
|
||||
method = "smc";
|
||||
compatible = "arm,psci-0.2", "arm,psci";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
|
||||
A53_0: cpu@0 {
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&CA53_L2>;
|
||||
};
|
||||
|
||||
CA53_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
always-on;
|
||||
clock-frequency = <25000000>;
|
||||
compatible = "arm,armv8-timer";
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
cooling:cooling {
|
||||
clocks = <&clk CV181X_CLK_A53>, <&clk CV181X_CLK_TPU>;
|
||||
clock-names = "clk_cpu", "clk_tpu_axi";
|
||||
dev-freqs = <800000000 500000000>,
|
||||
<400000000 375000000>,
|
||||
<400000000 300000000>;
|
||||
compatible = "sophgo,cooling";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
tpu {
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
mon {
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
wiegand0 {
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wiegand1 {
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wiegand2 {
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
saradc {
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sysdma_remap {
|
||||
int_mux = <0x1FF>; /* enable bit [0..8] for CPU0(CA53) */
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
#if 0
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
#endif
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
porta: gpio-controller@0 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
portb: gpio-controller@1 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
portc: gpio-controller@2 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
portd: gpio-controller@3 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
porte: gpio-controller@4 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
interrupt-names = "macirq";
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emmc:cv-emmc@4300000 {
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sd:cv-sd@4310000 {
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "csi0", "csi1";
|
||||
};
|
||||
|
||||
vi {
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "isp";
|
||||
};
|
||||
|
||||
ive {
|
||||
interrupt-names = "ive_irq";
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
vpss {
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sc";
|
||||
};
|
||||
|
||||
dwa {
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dwa";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "h265","h264","sbm";
|
||||
};
|
||||
|
||||
jpu {
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "jpeg";
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mailbox";
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tempsen";
|
||||
};
|
||||
|
||||
};
|
||||
@ -1,372 +0,0 @@
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/cv181x-resets.h>
|
||||
#include <dt-bindings/clock/cv181x-clock.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/dma/cv181x-dmamap.h>
|
||||
#include "cvi_board_memmap.h"
|
||||
|
||||
/*
|
||||
* OpenSBI will add below subnode into reserved memory automatically
|
||||
* mmode_resv0@80000000 {
|
||||
* reg = <0x00 0x80000000 0x00 0x20000>;
|
||||
* phandle = <0x0d>;
|
||||
* };
|
||||
* Skip below to avoid lmb region reseved conflict in uboot.
|
||||
*
|
||||
*/
|
||||
#ifndef __UBOOT__
|
||||
/memreserve/ CVIMMAP_MONITOR_ADDR CVIMMAP_OPENSBI_SIZE; // OpenSBI
|
||||
#endif
|
||||
|
||||
#include "soph_base.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SOPHGO ASIC. C906.";
|
||||
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
timebase-frequency = <25000000>;
|
||||
|
||||
cpu-map {
|
||||
|
||||
cluster0 {
|
||||
|
||||
core0 {
|
||||
cpu = <0x01>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x00>;
|
||||
status = "okay";
|
||||
compatible = "riscv";
|
||||
riscv,isa = "rv64imafdvcsu";
|
||||
mmu-type = "riscv,sv39";
|
||||
clock-frequency = <25000000>;
|
||||
|
||||
cpu0_intc: interrupt-controller {
|
||||
#interrupt-cells = <0x01>;
|
||||
interrupt-controller;
|
||||
compatible = "riscv,cpu-intc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <0x02>;
|
||||
#size-cells = <0x02>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
plic0: interrupt-controller@70000000 {
|
||||
riscv,ndev = <101>;
|
||||
riscv,max-priority = <0x07>;
|
||||
reg-names = "control";
|
||||
reg = <0x00 0x70000000 0x00 0x4000000>;
|
||||
interrupts-extended = <&cpu0_intc 0xffffffff &cpu0_intc 0x09>;
|
||||
interrupt-controller;
|
||||
compatible = "riscv,plic0";
|
||||
#interrupt-cells = <0x02>;
|
||||
#address-cells = <0x00>;
|
||||
};
|
||||
|
||||
clint@74000000 {
|
||||
interrupts-extended = <&cpu0_intc 0x03 &cpu0_intc 0x07>;
|
||||
reg = <0x00 0x74000000 0x00 0x10000>;
|
||||
compatible = "riscv,clint0";
|
||||
clint,has-no-64bit-mmio;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
cooling:cooling {
|
||||
clocks = <&clk CV181X_CLK_C906_0>, <&clk CV181X_CLK_TPU>;
|
||||
clock-names = "clk_cpu", "clk_tpu_axi";
|
||||
dev-freqs = <850000000 500000000>,
|
||||
<425000000 375000000>,
|
||||
<425000000 300000000>;
|
||||
compatible = "sophgo,cooling";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
tpu {
|
||||
interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tiu_irq", "tdma_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
mon {
|
||||
interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mon_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand0 {
|
||||
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand1 {
|
||||
interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand2 {
|
||||
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
saradc {
|
||||
interrupts = <100 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
sysdma_remap {
|
||||
int_mux = <0x7FC00>; /* enable bit [10..18] for CPU1(906B) */
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
porta: gpio-controller@0 {
|
||||
interrupt-controller;
|
||||
interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
portb: gpio-controller@1 {
|
||||
interrupt-controller;
|
||||
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
portc: gpio-controller@2 {
|
||||
interrupt-controller;
|
||||
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
portd: gpio-controller@3 {
|
||||
interrupt-controller;
|
||||
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
porte: gpio-controller@4 {
|
||||
interrupt-controller;
|
||||
interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
interrupt-names = "macirq";
|
||||
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
emmc:cv-emmc@4300000 {
|
||||
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
sd:cv-sd@4310000 {
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
vi {
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupt-names = "isp";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "h265","h264","sbm";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
jpu {
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "jpeg";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mailbox";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "csi0", "csi1";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
ive {
|
||||
interrupt-names = "ive_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
vpss {
|
||||
interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sc";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
dwa {
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dwa";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tempsen";
|
||||
};
|
||||
|
||||
};
|
||||
@ -1,25 +0,0 @@
|
||||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00 CVIMMAP_KERNEL_MEMORY_ADDR 0x00 CVIMMAP_KERNEL_MEMORY_SIZE>;
|
||||
};
|
||||
|
||||
|
||||
fast_image {
|
||||
compatible = "cvitek,rtos_image";
|
||||
reg-names = "rtos_region";
|
||||
reg = <0x0 CVIMMAP_FREERTOS_ADDR 0x0 CVIMMAP_FREERTOS_SIZE>;
|
||||
ion-size = <CVIMMAP_FREERTOS_RESERVED_ION_SIZE>; //reserved ion size for freertos
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
ranges;
|
||||
|
||||
ion_reserved: ion {
|
||||
compatible = "ion-region";
|
||||
size = <0x0 CVIMMAP_ION_SIZE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,276 +0,0 @@
|
||||
CONFIG_KERNEL_XZ=y
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_LOG_BUF_SHIFT=15
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
# CONFIG_UID16 is not set
|
||||
# CONFIG_SYSFS_SYSCALL is not set
|
||||
# CONFIG_FHANDLE is not set
|
||||
# CONFIG_BASE_FULL is not set
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_AIO is not set
|
||||
# CONFIG_KALLSYMS is not set
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
CONFIG_ARM_LPAE=y
|
||||
CONFIG_SWP_EMULATE=y
|
||||
# CONFIG_VDSO is not set
|
||||
CONFIG_HAVE_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_PSCI=y
|
||||
CONFIG_THUMB2_KERNEL=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=10
|
||||
# CONFIG_ATAGS is not set
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_ARCH_CVITEK=y
|
||||
CONFIG_ARCH_=y
|
||||
CONFIG_ARCH_CVITEK_CHIP="cv181x"
|
||||
CONFIG_ARCH_CV181X_ASIC=y
|
||||
CONFIG_POWER_RESET=y
|
||||
# CONFIG_STACKPROTECTOR is not set
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_FORCE_LOAD=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
# CONFIG_MQ_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_MQ_IOSCHED_KYBER is not set
|
||||
# CONFIG_COREDUMP is not set
|
||||
CONFIG_CMA=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_CMA_SIZE_MBYTES=0
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_OF_PARTS is not set
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_CVSNFC=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_SPI_CVI_SPIF=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_CORE is not set
|
||||
# CONFIG_NET_VENDOR_ALACRITECH is not set
|
||||
# CONFIG_NET_VENDOR_AMAZON is not set
|
||||
# CONFIG_NET_VENDOR_AQUANTIA is not set
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
# CONFIG_NET_VENDOR_AURORA is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CADENCE is not set
|
||||
# CONFIG_NET_VENDOR_CAVIUM is not set
|
||||
# CONFIG_NET_VENDOR_CIRRUS is not set
|
||||
# CONFIG_NET_VENDOR_CORTINA is not set
|
||||
# CONFIG_NET_VENDOR_EZCHIP is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_HISILICON is not set
|
||||
# CONFIG_NET_VENDOR_HUAWEI is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MELLANOX is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
||||
# CONFIG_NET_VENDOR_MICROSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NETRONOME is not set
|
||||
# CONFIG_NET_VENDOR_NI is not set
|
||||
# CONFIG_NET_VENDOR_QUALCOMM is not set
|
||||
# CONFIG_NET_VENDOR_RENESAS is not set
|
||||
# CONFIG_NET_VENDOR_ROCKER is not set
|
||||
# CONFIG_NET_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SOLARFLARE is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
# CONFIG_NET_VENDOR_SOCIONEXT is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_DWMAC_GENERIC is not set
|
||||
# CONFIG_NET_VENDOR_SYNOPSYS is not set
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_CVITEK_PHY=y
|
||||
# CONFIG_USB_NET_DRIVERS is not set
|
||||
# CONFIG_WLAN_VENDOR_ADMTEK is not set
|
||||
# CONFIG_WLAN_VENDOR_ATH is not set
|
||||
# CONFIG_WLAN_VENDOR_ATMEL is not set
|
||||
# CONFIG_WLAN_VENDOR_BROADCOM is not set
|
||||
# CONFIG_WLAN_VENDOR_CISCO is not set
|
||||
# CONFIG_WLAN_VENDOR_INTEL is not set
|
||||
# CONFIG_WLAN_VENDOR_INTERSIL is not set
|
||||
# CONFIG_WLAN_VENDOR_MARVELL is not set
|
||||
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
|
||||
# CONFIG_WLAN_VENDOR_RALINK is not set
|
||||
CONFIG_RTL8188FU=m
|
||||
# CONFIG_WLAN_VENDOR_RSI is not set
|
||||
# CONFIG_WLAN_VENDOR_ST is not set
|
||||
# CONFIG_WLAN_VENDOR_TI is not set
|
||||
# CONFIG_WLAN_VENDOR_ZYDAS is not set
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=5
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_PTP_1588_CLOCK is not set
|
||||
CONFIG_CVITEK_PINCTRL_CV1835=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_NETLINK=y
|
||||
CONFIG_THERMAL_WRITABLE_TRIPS=y
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_SOC_CAMERA=y
|
||||
CONFIG_V4L_MEM2MEM_DRIVERS=y
|
||||
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
|
||||
CONFIG_VIDEO_CVITEK=m
|
||||
CONFIG_VIDEO_CVITEK_CIF=m
|
||||
CONFIG_VIDEO_CVITEK_SNS_I2C=m
|
||||
CONFIG_VIDEO_CVITEK_MIPI_TX=m
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_CVITEK=m
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
# CONFIG_SND_PROC_FS is not set
|
||||
# CONFIG_SND_DRIVERS is not set
|
||||
CONFIG_SND_HDA_PREALLOC_SIZE=1
|
||||
# CONFIG_SND_ARM is not set
|
||||
# CONFIG_SND_SPI is not set
|
||||
# CONFIG_SND_USB is not set
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_CV182XA_CV182XAADC=y
|
||||
CONFIG_SND_SOC_CV182XA_CV182XADAC=y
|
||||
CONFIG_SND_CV1835_I2S=y
|
||||
CONFIG_SND_SOC_CV182XAADC=y
|
||||
CONFIG_SND_SOC_CV182XADAC=y
|
||||
# CONFIG_SND_SOC_CV182X_CV182XPDM is not set
|
||||
# CONFIG_SND_SOC_CV1835PDM is not set
|
||||
# CONFIG_SND_SOC_CV1835_CONCURRENT_I2S is not set
|
||||
CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
|
||||
CONFIG_CV1835_I2S_SUBSYS=y
|
||||
CONFIG_USB=m
|
||||
CONFIG_USB_DWC2=m
|
||||
CONFIG_USB_GADGET=m
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_CVI=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DW_DMAC_CVITEK=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ION=y
|
||||
CONFIG_ION_SYSTEM_HEAP=y
|
||||
CONFIG_ION_CARVEOUT_HEAP=y
|
||||
CONFIG_ION_CMA_HEAP=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_CV1835_SYSDMA_REMAP=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
# CONFIG_MANDATORY_FILE_LOCKING is not set
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_CONFIGFS_FS=m
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_FS_WBUF_VERIFY=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_SQUASHFS=y
|
||||
CONFIG_SQUASHFS_FILE_DIRECT=y
|
||||
# CONFIG_SQUASHFS_ZLIB is not set
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_SQUASHFS_EMBEDDED=y
|
||||
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=1
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V2=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_2=y
|
||||
CONFIG_NLS_ISO8859_3=y
|
||||
# CONFIG_CRYPTO_ECHAINIV is not set
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
# CONFIG_XZ_DEC_X86 is not set
|
||||
# CONFIG_XZ_DEC_POWERPC is not set
|
||||
# CONFIG_XZ_DEC_IA64 is not set
|
||||
# CONFIG_XZ_DEC_ARMTHUMB is not set
|
||||
# CONFIG_XZ_DEC_SPARC is not set
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
# CONFIG_ARM_UNWIND is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
CONFIG_BLK_CMDLINE_PARSER=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_CMDLINE_PARTITION=y
|
||||
CONFIG_EFI_PARTITION=n
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_DESIGNWARE_CORE=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
|
||||
#
|
||||
# SPI
|
||||
#
|
||||
# CONFIG_SPI is not set
|
||||
# CONFIG_SPI_MASTER is not set
|
||||
# CONFIG_SPI_DESIGNWARE is not set
|
||||
# CONFIG_SPI_DW_MMIO is not set
|
||||
# CONFIG_SPI_SPIDEV is not set
|
||||
@ -1,464 +0,0 @@
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=15
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_SYSFS_SYSCALL is not set
|
||||
# CONFIG_FHANDLE is not set
|
||||
# CONFIG_BASE_FULL is not set
|
||||
# CONFIG_AIO is not set
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
CONFIG_FORCE_MAX_ZONEORDER=10
|
||||
CONFIG_ARCH_CVITEK=y
|
||||
CONFIG_SOC_THEAD=y
|
||||
# CONFIG_RISCV_SWIOTLB is not set
|
||||
CONFIG_VECTOR=y
|
||||
CONFIG_VECTOR_0_7=y
|
||||
# CONFIG_COMPAT is not set
|
||||
CONFIG_ARCH_CVITEK_CHIP="cv181x"
|
||||
CONFIG_ARCH_CV181X_ASIC=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_COMPAT_32BIT_TIME=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_FORCE_LOAD=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_MQ_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_MQ_IOSCHED_KYBER is not set
|
||||
# CONFIG_COREDUMP is not set
|
||||
CONFIG_CMA=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_UEVENT_HELPER=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_OF_PARTS is not set
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_CORE is not set
|
||||
# CONFIG_NET_VENDOR_ALACRITECH is not set
|
||||
# CONFIG_NET_VENDOR_AMAZON is not set
|
||||
# CONFIG_NET_VENDOR_AQUANTIA is not set
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
# CONFIG_NET_VENDOR_AURORA is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CADENCE is not set
|
||||
# CONFIG_NET_VENDOR_CAVIUM is not set
|
||||
# CONFIG_NET_VENDOR_CORTINA is not set
|
||||
# CONFIG_NET_VENDOR_EZCHIP is not set
|
||||
# CONFIG_NET_VENDOR_HUAWEI is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
||||
# CONFIG_NET_VENDOR_MICROSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NETRONOME is not set
|
||||
# CONFIG_NET_VENDOR_NI is not set
|
||||
# CONFIG_NET_VENDOR_QUALCOMM is not set
|
||||
# CONFIG_NET_VENDOR_RENESAS is not set
|
||||
# CONFIG_NET_VENDOR_ROCKER is not set
|
||||
# CONFIG_NET_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SOLARFLARE is not set
|
||||
# CONFIG_NET_VENDOR_SOCIONEXT is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_DWMAC_GENERIC is not set
|
||||
# CONFIG_NET_VENDOR_SYNOPSYS is not set
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_CVITEK_PHY=y
|
||||
CONFIG_CVITEK_PHY_UAPS=y
|
||||
# CONFIG_USB_NET_DRIVERS is not set
|
||||
# CONFIG_WLAN_VENDOR_ADMTEK is not set
|
||||
# CONFIG_WLAN_VENDOR_ATH is not set
|
||||
# CONFIG_WLAN_VENDOR_ATMEL is not set
|
||||
# CONFIG_WLAN_VENDOR_BROADCOM is not set
|
||||
# CONFIG_WLAN_VENDOR_CISCO is not set
|
||||
# CONFIG_WLAN_VENDOR_INTEL is not set
|
||||
# CONFIG_WLAN_VENDOR_INTERSIL is not set
|
||||
# CONFIG_WLAN_VENDOR_MARVELL is not set
|
||||
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
|
||||
# CONFIG_WLAN_VENDOR_RALINK is not set
|
||||
# CONFIG_RTL8188FU is not set
|
||||
# CONFIG_WLAN_VENDOR_RSI is not set
|
||||
# CONFIG_WLAN_VENDOR_ST is not set
|
||||
# CONFIG_WLAN_VENDOR_TI is not set
|
||||
# CONFIG_WLAN_VENDOR_ZYDAS is not set
|
||||
CONFIG_INPUT=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=5
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
# CONFIG_PTP_1588_CLOCK is not set
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_CVITEK_PINCTRL_CV1835=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_NETLINK=y
|
||||
CONFIG_THERMAL_WRITABLE_TRIPS=y
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_V4L_MEM2MEM_DRIVERS=y
|
||||
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
|
||||
CONFIG_VIDEO_CVITEK=m
|
||||
CONFIG_VIDEO_CVITEK_CIF=m
|
||||
CONFIG_VIDEO_CVITEK_SNS_I2C=m
|
||||
CONFIG_VIDEO_CVITEK_MIPI_TX=m
|
||||
#
|
||||
# Media SPI Adapters
|
||||
#
|
||||
# CONFIG_CXD2880_SPI_DRV is not set
|
||||
# end of Media SPI Adapters
|
||||
#
|
||||
# Customize TV tuners
|
||||
#
|
||||
# CONFIG_MEDIA_TUNER_SIMPLE is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18250 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA8290 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA827X is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18271 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA9887 is not set
|
||||
# CONFIG_MEDIA_TUNER_TEA5761 is not set
|
||||
# CONFIG_MEDIA_TUNER_TEA5767 is not set
|
||||
# CONFIG_MEDIA_TUNER_MSI001 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT20XX is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2060 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2063 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2266 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2131 is not set
|
||||
# CONFIG_MEDIA_TUNER_QT1010 is not set
|
||||
# CONFIG_MEDIA_TUNER_XC2028 is not set
|
||||
# CONFIG_MEDIA_TUNER_XC5000 is not set
|
||||
# CONFIG_MEDIA_TUNER_XC4000 is not set
|
||||
# CONFIG_MEDIA_TUNER_MXL5005S is not set
|
||||
# CONFIG_MEDIA_TUNER_MXL5007T is not set
|
||||
# CONFIG_MEDIA_TUNER_MC44S803 is not set
|
||||
# CONFIG_MEDIA_TUNER_MAX2165 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18218 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC0011 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC0012 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC0013 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18212 is not set
|
||||
# CONFIG_MEDIA_TUNER_E4000 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC2580 is not set
|
||||
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
|
||||
# CONFIG_MEDIA_TUNER_TUA9001 is not set
|
||||
# CONFIG_MEDIA_TUNER_SI2157 is not set
|
||||
# CONFIG_MEDIA_TUNER_IT913X is not set
|
||||
# CONFIG_MEDIA_TUNER_R820T is not set
|
||||
# CONFIG_MEDIA_TUNER_MXL301RF is not set
|
||||
# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
|
||||
# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
|
||||
# end of Customize TV tuners
|
||||
#
|
||||
# Customise DVB Frontends
|
||||
#
|
||||
|
||||
#
|
||||
# Multistandard (satellite) frontends
|
||||
#
|
||||
# CONFIG_DVB_STB0899 is not set
|
||||
# CONFIG_DVB_STB6100 is not set
|
||||
# CONFIG_DVB_STV090x is not set
|
||||
# CONFIG_DVB_STV0910 is not set
|
||||
# CONFIG_DVB_STV6110x is not set
|
||||
# CONFIG_DVB_STV6111 is not set
|
||||
# CONFIG_DVB_MXL5XX is not set
|
||||
# CONFIG_DVB_M88DS3103 is not set
|
||||
|
||||
#
|
||||
# Multistandard (cable + terrestrial) frontends
|
||||
#
|
||||
# CONFIG_DVB_DRXK is not set
|
||||
# CONFIG_DVB_TDA18271C2DD is not set
|
||||
# CONFIG_DVB_SI2165 is not set
|
||||
# CONFIG_DVB_MN88472 is not set
|
||||
# CONFIG_DVB_MN88473 is not set
|
||||
|
||||
#
|
||||
# DVB-S (satellite) frontends
|
||||
#
|
||||
# CONFIG_DVB_CX24110 is not set
|
||||
# CONFIG_DVB_CX24123 is not set
|
||||
# CONFIG_DVB_MT312 is not set
|
||||
# CONFIG_DVB_ZL10036 is not set
|
||||
# CONFIG_DVB_ZL10039 is not set
|
||||
# CONFIG_DVB_S5H1420 is not set
|
||||
# CONFIG_DVB_STV0288 is not set
|
||||
# CONFIG_DVB_STB6000 is not set
|
||||
# CONFIG_DVB_STV0299 is not set
|
||||
# CONFIG_DVB_STV6110 is not set
|
||||
# CONFIG_DVB_STV0900 is not set
|
||||
# CONFIG_DVB_TDA8083 is not set
|
||||
# CONFIG_DVB_TDA10086 is not set
|
||||
# CONFIG_DVB_TDA8261 is not set
|
||||
# CONFIG_DVB_VES1X93 is not set
|
||||
# CONFIG_DVB_TUNER_ITD1000 is not set
|
||||
# CONFIG_DVB_TUNER_CX24113 is not set
|
||||
# CONFIG_DVB_TDA826X is not set
|
||||
# CONFIG_DVB_TUA6100 is not set
|
||||
# CONFIG_DVB_CX24116 is not set
|
||||
# CONFIG_DVB_CX24117 is not set
|
||||
# CONFIG_DVB_CX24120 is not set
|
||||
# CONFIG_DVB_SI21XX is not set
|
||||
# CONFIG_DVB_TS2020 is not set
|
||||
# CONFIG_DVB_DS3000 is not set
|
||||
# CONFIG_DVB_MB86A16 is not set
|
||||
# CONFIG_DVB_TDA10071 is not set
|
||||
|
||||
#
|
||||
# DVB-T (terrestrial) frontends
|
||||
#
|
||||
# CONFIG_DVB_SP8870 is not set
|
||||
# CONFIG_DVB_SP887X is not set
|
||||
# CONFIG_DVB_CX22700 is not set
|
||||
# CONFIG_DVB_CX22702 is not set
|
||||
# CONFIG_DVB_S5H1432 is not set
|
||||
# CONFIG_DVB_DRXD is not set
|
||||
# CONFIG_DVB_L64781 is not set
|
||||
# CONFIG_DVB_TDA1004X is not set
|
||||
# CONFIG_DVB_NXT6000 is not set
|
||||
# CONFIG_DVB_MT352 is not set
|
||||
# CONFIG_DVB_ZL10353 is not set
|
||||
# CONFIG_DVB_DIB3000MB is not set
|
||||
# CONFIG_DVB_DIB3000MC is not set
|
||||
# CONFIG_DVB_DIB7000M is not set
|
||||
# CONFIG_DVB_DIB7000P is not set
|
||||
# CONFIG_DVB_DIB9000 is not set
|
||||
# CONFIG_DVB_TDA10048 is not set
|
||||
# CONFIG_DVB_AF9013 is not set
|
||||
# CONFIG_DVB_EC100 is not set
|
||||
# CONFIG_DVB_STV0367 is not set
|
||||
# CONFIG_DVB_CXD2820R is not set
|
||||
# CONFIG_DVB_CXD2841ER is not set
|
||||
# CONFIG_DVB_RTL2830 is not set
|
||||
# CONFIG_DVB_RTL2832 is not set
|
||||
# CONFIG_DVB_RTL2832_SDR is not set
|
||||
# CONFIG_DVB_SI2168 is not set
|
||||
# CONFIG_DVB_ZD1301_DEMOD is not set
|
||||
# CONFIG_DVB_CXD2880 is not set
|
||||
|
||||
#
|
||||
# DVB-C (cable) frontends
|
||||
#
|
||||
# CONFIG_DVB_VES1820 is not set
|
||||
# CONFIG_DVB_TDA10021 is not set
|
||||
# CONFIG_DVB_TDA10023 is not set
|
||||
# CONFIG_DVB_STV0297 is not set
|
||||
|
||||
#
|
||||
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
|
||||
#
|
||||
# CONFIG_DVB_NXT200X is not set
|
||||
# CONFIG_DVB_OR51211 is not set
|
||||
# CONFIG_DVB_OR51132 is not set
|
||||
# CONFIG_DVB_BCM3510 is not set
|
||||
# CONFIG_DVB_LGDT330X is not set
|
||||
# CONFIG_DVB_LGDT3305 is not set
|
||||
# CONFIG_DVB_LGDT3306A is not set
|
||||
# CONFIG_DVB_LG2160 is not set
|
||||
# CONFIG_DVB_S5H1409 is not set
|
||||
# CONFIG_DVB_AU8522_DTV is not set
|
||||
# CONFIG_DVB_AU8522_V4L is not set
|
||||
# CONFIG_DVB_S5H1411 is not set
|
||||
|
||||
#
|
||||
# ISDB-T (terrestrial) frontends
|
||||
#
|
||||
# CONFIG_DVB_S921 is not set
|
||||
# CONFIG_DVB_DIB8000 is not set
|
||||
# CONFIG_DVB_MB86A20S is not set
|
||||
|
||||
#
|
||||
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
|
||||
#
|
||||
# CONFIG_DVB_TC90522 is not set
|
||||
# CONFIG_DVB_MN88443X is not set
|
||||
|
||||
#
|
||||
# Digital terrestrial only tuners/PLL
|
||||
#
|
||||
# CONFIG_DVB_PLL is not set
|
||||
# CONFIG_DVB_TUNER_DIB0070 is not set
|
||||
# CONFIG_DVB_TUNER_DIB0090 is not set
|
||||
#
|
||||
# SEC control devices for DVB-S
|
||||
#
|
||||
# CONFIG_DVB_DRX39XYJ is not set
|
||||
# CONFIG_DVB_LNBH25 is not set
|
||||
# CONFIG_DVB_LNBH29 is not set
|
||||
# CONFIG_DVB_LNBP21 is not set
|
||||
# CONFIG_DVB_LNBP22 is not set
|
||||
# CONFIG_DVB_ISL6405 is not set
|
||||
# CONFIG_DVB_ISL6421 is not set
|
||||
# CONFIG_DVB_ISL6423 is not set
|
||||
# CONFIG_DVB_A8293 is not set
|
||||
# CONFIG_DVB_LGS8GL5 is not set
|
||||
# CONFIG_DVB_LGS8GXX is not set
|
||||
# CONFIG_DVB_ATBM8830 is not set
|
||||
# CONFIG_DVB_TDA665x is not set
|
||||
# CONFIG_DVB_IX2505V is not set
|
||||
# CONFIG_DVB_M88RS2000 is not set
|
||||
# CONFIG_DVB_AF9033 is not set
|
||||
# CONFIG_DVB_HORUS3A is not set
|
||||
# CONFIG_DVB_ASCOT2E is not set
|
||||
# CONFIG_DVB_HELENE is not set
|
||||
#
|
||||
# Common Interface (EN50221) controller drivers
|
||||
#
|
||||
# CONFIG_DVB_CXD2099 is not set
|
||||
# CONFIG_DVB_SP2 is not set
|
||||
# end of Customise DVB Frontends
|
||||
#
|
||||
# Digital TV options
|
||||
#
|
||||
# CONFIG_DVB_NET is not set
|
||||
# CONFIG_DVB_DYNAMIC_MINORS is not set
|
||||
# end of Digital TV options
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_CVITEK=m
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
# CONFIG_SND_PROC_FS is not set
|
||||
# CONFIG_SND_DRIVERS is not set
|
||||
CONFIG_SND_HDA_PREALLOC_SIZE=1
|
||||
# CONFIG_SND_SPI is not set
|
||||
# CONFIG_SND_USB is not set
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_CV182XA_CV182XAADC=y
|
||||
CONFIG_SND_SOC_CV182XA_CV182XADAC=y
|
||||
CONFIG_SND_CV1835_I2S=y
|
||||
CONFIG_SND_SOC_CV182XAADC=y
|
||||
CONFIG_SND_SOC_CV182XADAC=y
|
||||
CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
|
||||
CONFIG_CV1835_I2S_SUBSYS=y
|
||||
CONFIG_USB=m
|
||||
CONFIG_USB_DWC2=m
|
||||
CONFIG_USB_GADGET=m
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_CVI=y
|
||||
CONFIG_BLK_CMDLINE_PARSER=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_CMDLINE_PARTITION=y
|
||||
CONFIG_EFI_PARTITION=n
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DW_DMAC_CVITEK=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ION=y
|
||||
CONFIG_ION_SYSTEM_HEAP=y
|
||||
CONFIG_ION_CARVEOUT_HEAP=y
|
||||
CONFIG_ION_CMA_HEAP=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_CV1835_SYSDMA_REMAP=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_ANDROID=y
|
||||
# CONFIG_MANDATORY_FILE_LOCKING is not set
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_CONFIGFS_FS=m
|
||||
CONFIG_SQUASHFS=y
|
||||
# CONFIG_SQUASHFS_ZLIB is not set
|
||||
CONFIG_SQUASHFS_LZ4=y
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V2=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_2=y
|
||||
CONFIG_NLS_ISO8859_3=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
# CONFIG_XZ_DEC_X86 is not set
|
||||
# CONFIG_XZ_DEC_POWERPC is not set
|
||||
# CONFIG_XZ_DEC_IA64 is not set
|
||||
# CONFIG_XZ_DEC_ARMTHUMB is not set
|
||||
# CONFIG_XZ_DEC_SPARC is not set
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_CMA_SIZE_MBYTES=0
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_INFO=n
|
||||
CONFIG_DEBUG_INFO_DWARF4=n
|
||||
CONFIG_GDB_SCRIPTS=y
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_BLK_DEV_INITRD=n
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_FRAME_POINTER=n
|
||||
CONFIG_DEBUG_MISC=n
|
||||
CONFIG_RCU_TRACE=n
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
CONFIG_USB_LIBCOMPOSITE=y
|
||||
CONFIG_USB_F_ACM=y
|
||||
CONFIG_USB_U_SERIAL=y
|
||||
CONFIG_USB_U_ETHER=y
|
||||
CONFIG_USB_U_AUDIO=y
|
||||
CONFIG_USB_F_SERIAL=y
|
||||
CONFIG_USB_F_ECM=y
|
||||
CONFIG_USB_F_EEM=y
|
||||
CONFIG_USB_F_RNDIS=y
|
||||
CONFIG_USB_F_MASS_STORAGE=y
|
||||
CONFIG_USB_F_FS=y
|
||||
CONFIG_USB_F_UAC1=y
|
||||
CONFIG_USB_F_UVC=y
|
||||
CONFIG_USB_CONFIGFS=y
|
||||
CONFIG_USB_CONFIGFS_SERIAL=y
|
||||
CONFIG_USB_CONFIGFS_ACM=y
|
||||
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
|
||||
CONFIG_BUG=n
|
||||
CONFIG_IO_URING=n
|
||||
CONFIG_ADVISE_SYSCALLS=n
|
||||
CONFIG_SIGNALFD=n
|
||||
CONFIG_TIMERFD=n
|
||||
CONFIG_EPOLL=n
|
||||
@ -1,282 +0,0 @@
|
||||
CONFIG_KERNEL_XZ=y
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_LOG_BUF_SHIFT=15
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
# CONFIG_UID16 is not set
|
||||
# CONFIG_SYSFS_SYSCALL is not set
|
||||
# CONFIG_FHANDLE is not set
|
||||
# CONFIG_BASE_FULL is not set
|
||||
# CONFIG_AIO is not set
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
CONFIG_ARM_LPAE=y
|
||||
CONFIG_SWP_EMULATE=y
|
||||
# CONFIG_VDSO is not set
|
||||
CONFIG_HAVE_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_PSCI=y
|
||||
CONFIG_THUMB2_KERNEL=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=10
|
||||
# CONFIG_ATAGS is not set
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_ARCH_CVITEK=y
|
||||
CONFIG_ARCH_CV181X=y
|
||||
CONFIG_ARCH_CVITEK_CHIP="cv181x"
|
||||
CONFIG_ARCH_CV181X_ASIC=y
|
||||
CONFIG_POWER_RESET=y
|
||||
# CONFIG_STACKPROTECTOR is not set
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_FORCE_LOAD=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_LBDAF is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
# CONFIG_MQ_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_MQ_IOSCHED_KYBER is not set
|
||||
# CONFIG_COREDUMP is not set
|
||||
CONFIG_CMA=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_CMA_SIZE_MBYTES=0
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_OF_PARTS is not set
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_CVSNFC=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_SPI_CVI_SPIF=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_CORE is not set
|
||||
# CONFIG_NET_VENDOR_ALACRITECH is not set
|
||||
# CONFIG_NET_VENDOR_AMAZON is not set
|
||||
# CONFIG_NET_VENDOR_AQUANTIA is not set
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
# CONFIG_NET_VENDOR_AURORA is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CADENCE is not set
|
||||
# CONFIG_NET_VENDOR_CAVIUM is not set
|
||||
# CONFIG_NET_VENDOR_CIRRUS is not set
|
||||
# CONFIG_NET_VENDOR_CORTINA is not set
|
||||
# CONFIG_NET_VENDOR_EZCHIP is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_HISILICON is not set
|
||||
# CONFIG_NET_VENDOR_HUAWEI is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MELLANOX is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
||||
# CONFIG_NET_VENDOR_MICROSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NETRONOME is not set
|
||||
# CONFIG_NET_VENDOR_NI is not set
|
||||
# CONFIG_NET_VENDOR_QUALCOMM is not set
|
||||
# CONFIG_NET_VENDOR_RENESAS is not set
|
||||
# CONFIG_NET_VENDOR_ROCKER is not set
|
||||
# CONFIG_NET_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SOLARFLARE is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
# CONFIG_NET_VENDOR_SOCIONEXT is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_DWMAC_GENERIC is not set
|
||||
# CONFIG_NET_VENDOR_SYNOPSYS is not set
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_CVITEK_PHY=y
|
||||
# CONFIG_USB_NET_DRIVERS is not set
|
||||
# CONFIG_WLAN_VENDOR_ADMTEK is not set
|
||||
# CONFIG_WLAN_VENDOR_ATH is not set
|
||||
# CONFIG_WLAN_VENDOR_ATMEL is not set
|
||||
# CONFIG_WLAN_VENDOR_BROADCOM is not set
|
||||
# CONFIG_WLAN_VENDOR_CISCO is not set
|
||||
# CONFIG_WLAN_VENDOR_INTEL is not set
|
||||
# CONFIG_WLAN_VENDOR_INTERSIL is not set
|
||||
# CONFIG_WLAN_VENDOR_MARVELL is not set
|
||||
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
|
||||
# CONFIG_WLAN_VENDOR_RALINK is not set
|
||||
CONFIG_RTL8188FU=m
|
||||
# CONFIG_WLAN_VENDOR_RSI is not set
|
||||
# CONFIG_WLAN_VENDOR_ST is not set
|
||||
# CONFIG_WLAN_VENDOR_TI is not set
|
||||
# CONFIG_WLAN_VENDOR_ZYDAS is not set
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=5
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
CONFIG_SPI=y
|
||||
# CONFIG_PTP_1588_CLOCK is not set
|
||||
CONFIG_CVITEK_PINCTRL_CV1835=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_NETLINK=y
|
||||
CONFIG_THERMAL_WRITABLE_TRIPS=y
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_SOC_CAMERA=y
|
||||
CONFIG_V4L_MEM2MEM_DRIVERS=y
|
||||
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
|
||||
CONFIG_VIDEO_CVITEK=m
|
||||
CONFIG_VIDEO_CVITEK_CIF=m
|
||||
CONFIG_VIDEO_CVITEK_SNS_I2C=m
|
||||
CONFIG_VIDEO_CVITEK_MIPI_TX=m
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_CVITEK=m
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
# CONFIG_SND_PROC_FS is not set
|
||||
# CONFIG_SND_DRIVERS is not set
|
||||
CONFIG_SND_HDA_PREALLOC_SIZE=1
|
||||
# CONFIG_SND_ARM is not set
|
||||
# CONFIG_SND_SPI is not set
|
||||
# CONFIG_SND_USB is not set
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_CV182XA_CV182XAADC=y
|
||||
CONFIG_SND_SOC_CV182XA_CV182XADAC=y
|
||||
CONFIG_SND_CV1835_I2S=y
|
||||
CONFIG_SND_SOC_CV182XAADC=y
|
||||
CONFIG_SND_SOC_CV182XADAC=y
|
||||
# CONFIG_SND_SOC_CV182X_CV182XPDM is not set
|
||||
# CONFIG_SND_SOC_CV1835PDM is not set
|
||||
# CONFIG_SND_SOC_CV1835_CONCURRENT_I2S is not set
|
||||
CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
|
||||
CONFIG_CV1835_I2S_SUBSYS=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_CVI=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DW_DMAC_CVITEK=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ION=y
|
||||
CONFIG_ION_SYSTEM_HEAP=y
|
||||
CONFIG_ION_CARVEOUT_HEAP=y
|
||||
CONFIG_ION_CMA_HEAP=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_CV1835_SYSDMA_REMAP=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
# CONFIG_MANDATORY_FILE_LOCKING is not set
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_CONFIGFS_FS=m
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_FS_WBUF_VERIFY=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_SQUASHFS=y
|
||||
CONFIG_SQUASHFS_FILE_DIRECT=y
|
||||
# CONFIG_SQUASHFS_ZLIB is not set
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_SQUASHFS_EMBEDDED=y
|
||||
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=1
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V2=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_2=y
|
||||
CONFIG_NLS_ISO8859_3=y
|
||||
# CONFIG_CRYPTO_ECHAINIV is not set
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
# CONFIG_XZ_DEC_X86 is not set
|
||||
# CONFIG_XZ_DEC_POWERPC is not set
|
||||
# CONFIG_XZ_DEC_IA64 is not set
|
||||
# CONFIG_XZ_DEC_ARMTHUMB is not set
|
||||
# CONFIG_XZ_DEC_SPARC is not set
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
|
||||
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_OTG=y
|
||||
CONFIG_USB_OTG_FSM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_LIBCOMPOSITE=y
|
||||
CONFIG_USB_F_ACM=y
|
||||
CONFIG_USB_U_SERIAL=y
|
||||
CONFIG_USB_U_ETHER=y
|
||||
CONFIG_USB_U_AUDIO=y
|
||||
CONFIG_USB_F_SERIAL=y
|
||||
CONFIG_USB_F_ECM=y
|
||||
CONFIG_USB_F_EEM=y
|
||||
CONFIG_USB_F_RNDIS=y
|
||||
CONFIG_USB_F_MASS_STORAGE=y
|
||||
CONFIG_USB_F_UAC1=y
|
||||
CONFIG_USB_F_UVC=y
|
||||
CONFIG_USB_UAS=y
|
||||
CONFIG_USB_DWC2=m
|
||||
CONFIG_USB_DWC2_DUAL_ROLE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_U_SERIAL_CONSOLE=y
|
||||
CONFIG_USB_CONFIGFS=y
|
||||
CONFIG_USB_CONFIGFS_SERIAL=y
|
||||
CONFIG_USB_CONFIGFS_ACM=y
|
||||
CONFIG_USB_CONFIGFS_ECM=y
|
||||
CONFIG_USB_CONFIGFS_RNDIS=y
|
||||
CONFIG_USB_CONFIGFS_EEM=y
|
||||
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
|
||||
CONFIG_USB_CONFIGFS_F_FS=y
|
||||
CONFIG_USB_CONFIGFS_F_UAC1=y
|
||||
CONFIG_USB_CONFIGFS_F_UVC=y
|
||||
CONFIG_USB_CONFIGFS_F_FS=y
|
||||
CONFIG_USB_CONFIGFS_UEVENT=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_GPIO_VBUS=y
|
||||
@ -1,459 +0,0 @@
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=15
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_SYSFS_SYSCALL is not set
|
||||
# CONFIG_FHANDLE is not set
|
||||
# CONFIG_BASE_FULL is not set
|
||||
# CONFIG_AIO is not set
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
CONFIG_FORCE_MAX_ZONEORDER=10
|
||||
CONFIG_ARCH_CVITEK=y
|
||||
CONFIG_SOC_THEAD=y
|
||||
# CONFIG_RISCV_SWIOTLB is not set
|
||||
CONFIG_VECTOR=y
|
||||
CONFIG_VECTOR_0_7=y
|
||||
# CONFIG_COMPAT is not set
|
||||
CONFIG_ARCH_CVITEK_CHIP="cv181x"
|
||||
CONFIG_ARCH_CV181X_ASIC=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_COMPAT_32BIT_TIME=y
|
||||
CONFIG_STRICT_KERNEL_RWX=n
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_FORCE_LOAD=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_MQ_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_MQ_IOSCHED_KYBER is not set
|
||||
# CONFIG_COREDUMP is not set
|
||||
CONFIG_CMA=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_UEVENT_HELPER=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_OF_PARTS is not set
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_MTD_NAND_PLATFORM=y
|
||||
CONFIG_MTD_NAND_CVSNFC=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_SPI_CVI_SPIF=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_CORE is not set
|
||||
# CONFIG_NET_VENDOR_ALACRITECH is not set
|
||||
# CONFIG_NET_VENDOR_AMAZON is not set
|
||||
# CONFIG_NET_VENDOR_AQUANTIA is not set
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
# CONFIG_NET_VENDOR_AURORA is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CADENCE is not set
|
||||
# CONFIG_NET_VENDOR_CAVIUM is not set
|
||||
# CONFIG_NET_VENDOR_CORTINA is not set
|
||||
# CONFIG_NET_VENDOR_EZCHIP is not set
|
||||
# CONFIG_NET_VENDOR_HUAWEI is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
||||
# CONFIG_NET_VENDOR_MICROSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NETRONOME is not set
|
||||
# CONFIG_NET_VENDOR_NI is not set
|
||||
# CONFIG_NET_VENDOR_QUALCOMM is not set
|
||||
# CONFIG_NET_VENDOR_RENESAS is not set
|
||||
# CONFIG_NET_VENDOR_ROCKER is not set
|
||||
# CONFIG_NET_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SOLARFLARE is not set
|
||||
# CONFIG_NET_VENDOR_SOCIONEXT is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_DWMAC_GENERIC is not set
|
||||
# CONFIG_NET_VENDOR_SYNOPSYS is not set
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_CVITEK_PHY=y
|
||||
# CONFIG_USB_NET_DRIVERS is not set
|
||||
# CONFIG_WLAN_VENDOR_ADMTEK is not set
|
||||
# CONFIG_WLAN_VENDOR_ATH is not set
|
||||
# CONFIG_WLAN_VENDOR_ATMEL is not set
|
||||
# CONFIG_WLAN_VENDOR_BROADCOM is not set
|
||||
# CONFIG_WLAN_VENDOR_CISCO is not set
|
||||
# CONFIG_WLAN_VENDOR_INTEL is not set
|
||||
# CONFIG_WLAN_VENDOR_INTERSIL is not set
|
||||
# CONFIG_WLAN_VENDOR_MARVELL is not set
|
||||
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
|
||||
# CONFIG_WLAN_VENDOR_RALINK is not set
|
||||
# CONFIG_RTL8188FU is not set
|
||||
# CONFIG_WLAN_VENDOR_RSI is not set
|
||||
# CONFIG_WLAN_VENDOR_ST is not set
|
||||
# CONFIG_WLAN_VENDOR_TI is not set
|
||||
# CONFIG_WLAN_VENDOR_ZYDAS is not set
|
||||
CONFIG_INPUT=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=5
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
CONFIG_SPI=y
|
||||
# CONFIG_PTP_1588_CLOCK is not set
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_CVITEK_PINCTRL_CV1835=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_NETLINK=y
|
||||
CONFIG_THERMAL_WRITABLE_TRIPS=y
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_MEDIA_SUPPORT=n
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=n
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=n
|
||||
CONFIG_V4L_MEM2MEM_DRIVERS=n
|
||||
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=n
|
||||
CONFIG_VIDEO_CVITEK=m
|
||||
CONFIG_VIDEO_CVITEK_CIF=m
|
||||
CONFIG_VIDEO_CVITEK_SNS_I2C=m
|
||||
CONFIG_VIDEO_CVITEK_MIPI_TX=m
|
||||
#
|
||||
# Media SPI Adapters
|
||||
#
|
||||
# CONFIG_CXD2880_SPI_DRV is not set
|
||||
# end of Media SPI Adapters
|
||||
#
|
||||
# Customize TV tuners
|
||||
#
|
||||
# CONFIG_MEDIA_TUNER_SIMPLE is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18250 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA8290 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA827X is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18271 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA9887 is not set
|
||||
# CONFIG_MEDIA_TUNER_TEA5761 is not set
|
||||
# CONFIG_MEDIA_TUNER_TEA5767 is not set
|
||||
# CONFIG_MEDIA_TUNER_MSI001 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT20XX is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2060 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2063 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2266 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2131 is not set
|
||||
# CONFIG_MEDIA_TUNER_QT1010 is not set
|
||||
# CONFIG_MEDIA_TUNER_XC2028 is not set
|
||||
# CONFIG_MEDIA_TUNER_XC5000 is not set
|
||||
# CONFIG_MEDIA_TUNER_XC4000 is not set
|
||||
# CONFIG_MEDIA_TUNER_MXL5005S is not set
|
||||
# CONFIG_MEDIA_TUNER_MXL5007T is not set
|
||||
# CONFIG_MEDIA_TUNER_MC44S803 is not set
|
||||
# CONFIG_MEDIA_TUNER_MAX2165 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18218 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC0011 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC0012 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC0013 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18212 is not set
|
||||
# CONFIG_MEDIA_TUNER_E4000 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC2580 is not set
|
||||
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
|
||||
# CONFIG_MEDIA_TUNER_TUA9001 is not set
|
||||
# CONFIG_MEDIA_TUNER_SI2157 is not set
|
||||
# CONFIG_MEDIA_TUNER_IT913X is not set
|
||||
# CONFIG_MEDIA_TUNER_R820T is not set
|
||||
# CONFIG_MEDIA_TUNER_MXL301RF is not set
|
||||
# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
|
||||
# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
|
||||
# end of Customize TV tuners
|
||||
#
|
||||
# Customise DVB Frontends
|
||||
#
|
||||
|
||||
#
|
||||
# Multistandard (satellite) frontends
|
||||
#
|
||||
# CONFIG_DVB_STB0899 is not set
|
||||
# CONFIG_DVB_STB6100 is not set
|
||||
# CONFIG_DVB_STV090x is not set
|
||||
# CONFIG_DVB_STV0910 is not set
|
||||
# CONFIG_DVB_STV6110x is not set
|
||||
# CONFIG_DVB_STV6111 is not set
|
||||
# CONFIG_DVB_MXL5XX is not set
|
||||
# CONFIG_DVB_M88DS3103 is not set
|
||||
|
||||
#
|
||||
# Multistandard (cable + terrestrial) frontends
|
||||
#
|
||||
# CONFIG_DVB_DRXK is not set
|
||||
# CONFIG_DVB_TDA18271C2DD is not set
|
||||
# CONFIG_DVB_SI2165 is not set
|
||||
# CONFIG_DVB_MN88472 is not set
|
||||
# CONFIG_DVB_MN88473 is not set
|
||||
|
||||
#
|
||||
# DVB-S (satellite) frontends
|
||||
#
|
||||
# CONFIG_DVB_CX24110 is not set
|
||||
# CONFIG_DVB_CX24123 is not set
|
||||
# CONFIG_DVB_MT312 is not set
|
||||
# CONFIG_DVB_ZL10036 is not set
|
||||
# CONFIG_DVB_ZL10039 is not set
|
||||
# CONFIG_DVB_S5H1420 is not set
|
||||
# CONFIG_DVB_STV0288 is not set
|
||||
# CONFIG_DVB_STB6000 is not set
|
||||
# CONFIG_DVB_STV0299 is not set
|
||||
# CONFIG_DVB_STV6110 is not set
|
||||
# CONFIG_DVB_STV0900 is not set
|
||||
# CONFIG_DVB_TDA8083 is not set
|
||||
# CONFIG_DVB_TDA10086 is not set
|
||||
# CONFIG_DVB_TDA8261 is not set
|
||||
# CONFIG_DVB_VES1X93 is not set
|
||||
# CONFIG_DVB_TUNER_ITD1000 is not set
|
||||
# CONFIG_DVB_TUNER_CX24113 is not set
|
||||
# CONFIG_DVB_TDA826X is not set
|
||||
# CONFIG_DVB_TUA6100 is not set
|
||||
# CONFIG_DVB_CX24116 is not set
|
||||
# CONFIG_DVB_CX24117 is not set
|
||||
# CONFIG_DVB_CX24120 is not set
|
||||
# CONFIG_DVB_SI21XX is not set
|
||||
# CONFIG_DVB_TS2020 is not set
|
||||
# CONFIG_DVB_DS3000 is not set
|
||||
# CONFIG_DVB_MB86A16 is not set
|
||||
# CONFIG_DVB_TDA10071 is not set
|
||||
|
||||
#
|
||||
# DVB-T (terrestrial) frontends
|
||||
#
|
||||
# CONFIG_DVB_SP8870 is not set
|
||||
# CONFIG_DVB_SP887X is not set
|
||||
# CONFIG_DVB_CX22700 is not set
|
||||
# CONFIG_DVB_CX22702 is not set
|
||||
# CONFIG_DVB_S5H1432 is not set
|
||||
# CONFIG_DVB_DRXD is not set
|
||||
# CONFIG_DVB_L64781 is not set
|
||||
# CONFIG_DVB_TDA1004X is not set
|
||||
# CONFIG_DVB_NXT6000 is not set
|
||||
# CONFIG_DVB_MT352 is not set
|
||||
# CONFIG_DVB_ZL10353 is not set
|
||||
# CONFIG_DVB_DIB3000MB is not set
|
||||
# CONFIG_DVB_DIB3000MC is not set
|
||||
# CONFIG_DVB_DIB7000M is not set
|
||||
# CONFIG_DVB_DIB7000P is not set
|
||||
# CONFIG_DVB_DIB9000 is not set
|
||||
# CONFIG_DVB_TDA10048 is not set
|
||||
# CONFIG_DVB_AF9013 is not set
|
||||
# CONFIG_DVB_EC100 is not set
|
||||
# CONFIG_DVB_STV0367 is not set
|
||||
# CONFIG_DVB_CXD2820R is not set
|
||||
# CONFIG_DVB_CXD2841ER is not set
|
||||
# CONFIG_DVB_RTL2830 is not set
|
||||
# CONFIG_DVB_RTL2832 is not set
|
||||
# CONFIG_DVB_RTL2832_SDR is not set
|
||||
# CONFIG_DVB_SI2168 is not set
|
||||
# CONFIG_DVB_ZD1301_DEMOD is not set
|
||||
# CONFIG_DVB_CXD2880 is not set
|
||||
|
||||
#
|
||||
# DVB-C (cable) frontends
|
||||
#
|
||||
# CONFIG_DVB_VES1820 is not set
|
||||
# CONFIG_DVB_TDA10021 is not set
|
||||
# CONFIG_DVB_TDA10023 is not set
|
||||
# CONFIG_DVB_STV0297 is not set
|
||||
|
||||
#
|
||||
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
|
||||
#
|
||||
# CONFIG_DVB_NXT200X is not set
|
||||
# CONFIG_DVB_OR51211 is not set
|
||||
# CONFIG_DVB_OR51132 is not set
|
||||
# CONFIG_DVB_BCM3510 is not set
|
||||
# CONFIG_DVB_LGDT330X is not set
|
||||
# CONFIG_DVB_LGDT3305 is not set
|
||||
# CONFIG_DVB_LGDT3306A is not set
|
||||
# CONFIG_DVB_LG2160 is not set
|
||||
# CONFIG_DVB_S5H1409 is not set
|
||||
# CONFIG_DVB_AU8522_DTV is not set
|
||||
# CONFIG_DVB_AU8522_V4L is not set
|
||||
# CONFIG_DVB_S5H1411 is not set
|
||||
|
||||
#
|
||||
# ISDB-T (terrestrial) frontends
|
||||
#
|
||||
# CONFIG_DVB_S921 is not set
|
||||
# CONFIG_DVB_DIB8000 is not set
|
||||
# CONFIG_DVB_MB86A20S is not set
|
||||
|
||||
#
|
||||
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
|
||||
#
|
||||
# CONFIG_DVB_TC90522 is not set
|
||||
# CONFIG_DVB_MN88443X is not set
|
||||
|
||||
#
|
||||
# Digital terrestrial only tuners/PLL
|
||||
#
|
||||
# CONFIG_DVB_PLL is not set
|
||||
# CONFIG_DVB_TUNER_DIB0070 is not set
|
||||
# CONFIG_DVB_TUNER_DIB0090 is not set
|
||||
#
|
||||
# SEC control devices for DVB-S
|
||||
#
|
||||
# CONFIG_DVB_DRX39XYJ is not set
|
||||
# CONFIG_DVB_LNBH25 is not set
|
||||
# CONFIG_DVB_LNBH29 is not set
|
||||
# CONFIG_DVB_LNBP21 is not set
|
||||
# CONFIG_DVB_LNBP22 is not set
|
||||
# CONFIG_DVB_ISL6405 is not set
|
||||
# CONFIG_DVB_ISL6421 is not set
|
||||
# CONFIG_DVB_ISL6423 is not set
|
||||
# CONFIG_DVB_A8293 is not set
|
||||
# CONFIG_DVB_LGS8GL5 is not set
|
||||
# CONFIG_DVB_LGS8GXX is not set
|
||||
# CONFIG_DVB_ATBM8830 is not set
|
||||
# CONFIG_DVB_TDA665x is not set
|
||||
# CONFIG_DVB_IX2505V is not set
|
||||
# CONFIG_DVB_M88RS2000 is not set
|
||||
# CONFIG_DVB_AF9033 is not set
|
||||
# CONFIG_DVB_HORUS3A is not set
|
||||
# CONFIG_DVB_ASCOT2E is not set
|
||||
# CONFIG_DVB_HELENE is not set
|
||||
#
|
||||
# Common Interface (EN50221) controller drivers
|
||||
#
|
||||
# CONFIG_DVB_CXD2099 is not set
|
||||
# CONFIG_DVB_SP2 is not set
|
||||
# end of Customise DVB Frontends
|
||||
#
|
||||
# Digital TV options
|
||||
#
|
||||
# CONFIG_DVB_NET is not set
|
||||
# CONFIG_DVB_DYNAMIC_MINORS is not set
|
||||
# end of Digital TV options
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_CVITEK=m
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
# CONFIG_SND_PROC_FS is not set
|
||||
# CONFIG_SND_DRIVERS is not set
|
||||
CONFIG_SND_HDA_PREALLOC_SIZE=1
|
||||
# CONFIG_SND_SPI is not set
|
||||
# CONFIG_SND_USB is not set
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_CV182XA_CV182XAADC=y
|
||||
CONFIG_SND_SOC_CV182XA_CV182XADAC=y
|
||||
CONFIG_SND_CV1835_I2S=y
|
||||
CONFIG_SND_SOC_CV182XAADC=y
|
||||
CONFIG_SND_SOC_CV182XADAC=y
|
||||
CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
|
||||
CONFIG_CV1835_I2S_SUBSYS=y
|
||||
CONFIG_USB=m
|
||||
CONFIG_USB_DWC2=m
|
||||
CONFIG_USB_GADGET=m
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_CVI=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DW_DMAC_CVITEK=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ION=y
|
||||
CONFIG_ION_SYSTEM_HEAP=y
|
||||
CONFIG_ION_CARVEOUT_HEAP=y
|
||||
CONFIG_ION_CMA_HEAP=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_CV1835_SYSDMA_REMAP=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_ANDROID=y
|
||||
# CONFIG_MANDATORY_FILE_LOCKING is not set
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_CONFIGFS_FS=m
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_FS_WBUF_VERIFY=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_SQUASHFS=y
|
||||
# CONFIG_SQUASHFS_ZLIB is not set
|
||||
CONFIG_SQUASHFS_LZ4=y
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V2=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_2=y
|
||||
CONFIG_NLS_ISO8859_3=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
# CONFIG_XZ_DEC_X86 is not set
|
||||
# CONFIG_XZ_DEC_POWERPC is not set
|
||||
# CONFIG_XZ_DEC_IA64 is not set
|
||||
# CONFIG_XZ_DEC_ARMTHUMB is not set
|
||||
# CONFIG_XZ_DEC_SPARC is not set
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_CMA_SIZE_MBYTES=0
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_INFO=n
|
||||
CONFIG_DEBUG_INFO_DWARF4=n
|
||||
CONFIG_GDB_SCRIPTS=y
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_DEBUG_MISC=n
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
CONFIG_USB_LIBCOMPOSITE=y
|
||||
CONFIG_USB_F_ACM=y
|
||||
CONFIG_USB_U_SERIAL=y
|
||||
CONFIG_USB_U_ETHER=y
|
||||
CONFIG_USB_U_AUDIO=y
|
||||
CONFIG_USB_F_SERIAL=y
|
||||
CONFIG_USB_F_ECM=y
|
||||
CONFIG_USB_F_EEM=y
|
||||
CONFIG_USB_F_RNDIS=y
|
||||
CONFIG_USB_F_MASS_STORAGE=y
|
||||
CONFIG_USB_F_FS=y
|
||||
CONFIG_USB_F_UAC1=y
|
||||
CONFIG_USB_F_UVC=y
|
||||
CONFIG_USB_CONFIGFS=y
|
||||
CONFIG_USB_CONFIGFS_SERIAL=y
|
||||
CONFIG_USB_CONFIGFS_ACM=y
|
||||
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
|
||||
CONFIG_BUG=n
|
||||
@ -1,85 +0,0 @@
|
||||
SIZE_1M = 0x100000
|
||||
SIZE_1K = 1024
|
||||
|
||||
|
||||
# Only attributes in class MemoryMap are generated to .h
|
||||
class MemoryMap:
|
||||
# No prefix "CVIMMAP_" for the items in _no_prefix[]
|
||||
_no_prefix = [
|
||||
"CONFIG_SYS_TEXT_BASE" # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
|
||||
]
|
||||
|
||||
DRAM_BASE = 0x80000000
|
||||
DRAM_SIZE = 128 * SIZE_1M
|
||||
|
||||
# ==============
|
||||
# C906L FreeRTOS
|
||||
# ==============
|
||||
FREERTOS_SIZE = 2 * SIZE_1M
|
||||
# FreeRTOS is at the end of DRAM
|
||||
FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
|
||||
FSBL_C906L_START_ADDR = FREERTOS_ADDR
|
||||
|
||||
# ==============================
|
||||
# OpenSBI | arm-trusted-firmware
|
||||
# ==============================
|
||||
# Monitor is at the begining of DRAM
|
||||
MONITOR_ADDR = DRAM_BASE
|
||||
|
||||
ATF_SIZE = 512 * SIZE_1K
|
||||
OPENSBI_SIZE = 512 * SIZE_1K
|
||||
OPENSBI_FDT_ADDR = MONITOR_ADDR + OPENSBI_SIZE
|
||||
|
||||
# =========================
|
||||
# memory@DRAM_BASE in .dts.
|
||||
# =========================
|
||||
# Ignore the area of FreeRTOS in u-boot and kernel
|
||||
KERNEL_MEMORY_ADDR = DRAM_BASE
|
||||
KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
|
||||
|
||||
# =================
|
||||
# Multimedia buffer. Used by u-boot/kernel/FreeRTOS
|
||||
# =================
|
||||
ION_SIZE = 70 * SIZE_1M
|
||||
H26X_BITSTREAM_SIZE = 2 * SIZE_1M
|
||||
H26X_ENC_BUFF_SIZE = 0
|
||||
ISP_MEM_BASE_SIZE = 20 * SIZE_1M
|
||||
FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE
|
||||
|
||||
# ION after FreeRTOS
|
||||
ION_ADDR = FREERTOS_ADDR - ION_SIZE
|
||||
|
||||
# Buffers of the fast image are inside the ION buffer
|
||||
H26X_BITSTREAM_ADDR = ION_ADDR
|
||||
H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
|
||||
ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
|
||||
|
||||
assert ISP_MEM_BASE_ADDR + ISP_MEM_BASE_SIZE <= ION_ADDR + ION_SIZE
|
||||
|
||||
# Boot logo is after the ION buffer
|
||||
# Framebuffer uses boot logo's reserved memory
|
||||
BOOTLOGO_SIZE = 1800 * SIZE_1K
|
||||
BOOTLOGO_ADDR = ION_ADDR - BOOTLOGO_SIZE
|
||||
FRAMEBUFFER_SIZE = BOOTLOGO_SIZE
|
||||
FRAMEBUFFER_ADDR = BOOTLOGO_ADDR
|
||||
|
||||
# ===================
|
||||
# FSBL and u-boot-2021
|
||||
# ===================
|
||||
CVI_UPDATE_HEADER_SIZE = SIZE_1K
|
||||
UIMAG_SIZE = 16 * SIZE_1M
|
||||
|
||||
# kernel image loading buffer
|
||||
UIMAG_ADDR = DRAM_BASE + 24 * SIZE_1M
|
||||
CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR - CVI_UPDATE_HEADER_SIZE
|
||||
|
||||
# FSBL decompress buffer
|
||||
FSBL_UNZIP_ADDR = UIMAG_ADDR
|
||||
FSBL_UNZIP_SIZE = UIMAG_SIZE
|
||||
|
||||
assert UIMAG_ADDR + UIMAG_SIZE <= BOOTLOGO_ADDR
|
||||
|
||||
# u-boot's run address and entry point
|
||||
CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
|
||||
# u-boot's init stack point is only used before board_init_f()
|
||||
CONFIG_SYS_INIT_SP_ADDR = UIMAG_ADDR + UIMAG_SIZE
|
||||
@ -1,61 +0,0 @@
|
||||
SIZE_1M = 0x100000
|
||||
SIZE_1K = 1024
|
||||
|
||||
|
||||
# Only attributes in class MemoryMap are generated to .h
|
||||
class MemoryMap:
|
||||
# No prefix "CVIMMAP_" for the items in _no_prefix[]
|
||||
_no_prefix = [
|
||||
"CONFIG_SYS_TEXT_BASE" # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
|
||||
]
|
||||
|
||||
DRAM_BASE = 0x80000000
|
||||
DRAM_SIZE = 2047 * SIZE_1M
|
||||
|
||||
# Bootlogo
|
||||
BOOTLOGO_ADDR = DRAM_BASE + 24 * SIZE_1M
|
||||
BOOTLOGO_SIZE = 1.5 * SIZE_1M
|
||||
|
||||
# C906L freertos
|
||||
FREERTOS_SIZE = 2 * SIZE_1M
|
||||
FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
|
||||
# psu_ddr_0_MEM_0 : ORIGIN = FREERTOS_ADDR, LENGTH = FREERTOS_SIZE
|
||||
|
||||
# OpenSBI | arm-trusted-firmware
|
||||
MONITOR_ADDR = DRAM_BASE
|
||||
|
||||
ATF_SIZE = 512 * SIZE_1K
|
||||
|
||||
OPENSBI_SIZE = 512 * SIZE_1K
|
||||
OPENSBI_FDT_ADDR = DRAM_BASE + SIZE_1M
|
||||
|
||||
# FSBL
|
||||
FSBL_UNZIP_ADDR = DRAM_BASE + 16 * SIZE_1M
|
||||
FSBL_UNZIP_SIZE = DRAM_BASE + 4 * SIZE_1M
|
||||
FSBL_C906L_START_ADDR = FREERTOS_ADDR
|
||||
|
||||
# uboot-2021 defconfig
|
||||
CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
|
||||
CONFIG_SYS_INIT_SP_ADDR = DRAM_BASE + 63 * SIZE_1M
|
||||
|
||||
UIMAG_ADDR = DRAM_BASE + 18 * SIZE_1M
|
||||
CVI_UPDATE_HEADER_SIZE = SIZE_1K
|
||||
CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR + CVI_UPDATE_HEADER_SIZE
|
||||
|
||||
# memory@DRAM_BASE
|
||||
KERNEL_MEMORY_ADDR = DRAM_BASE
|
||||
KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
|
||||
|
||||
ION_ADDR = DRAM_BASE + 0x3C80000
|
||||
ION_SIZE = 65.5 * SIZE_1M
|
||||
|
||||
# Fast image buffer
|
||||
H26X_BITSTREAM_ADDR = DRAM_BASE + 39 * SIZE_1M
|
||||
H26X_BITSTREAM_SIZE = 2 * SIZE_1M
|
||||
|
||||
H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
|
||||
H26X_ENC_BUFF_SIZE = 0
|
||||
|
||||
ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
|
||||
ISP_MEM_BASE_SIZE = 10 * SIZE_1M
|
||||
FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE
|
||||
@ -1,85 +0,0 @@
|
||||
SIZE_1M = 0x100000
|
||||
SIZE_1K = 1024
|
||||
|
||||
|
||||
# Only attributes in class MemoryMap are generated to .h
|
||||
class MemoryMap:
|
||||
# No prefix "CVIMMAP_" for the items in _no_prefix[]
|
||||
_no_prefix = [
|
||||
"CONFIG_SYS_TEXT_BASE" # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
|
||||
]
|
||||
|
||||
DRAM_BASE = 0x80000000
|
||||
DRAM_SIZE = 64 * SIZE_1M
|
||||
|
||||
# ==============
|
||||
# C906L FreeRTOS
|
||||
# ==============
|
||||
FREERTOS_SIZE = 768 * SIZE_1K
|
||||
# FreeRTOS is at the end of DRAM
|
||||
FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
|
||||
FSBL_C906L_START_ADDR = FREERTOS_ADDR
|
||||
|
||||
# ==============================
|
||||
# OpenSBI | arm-trusted-firmware
|
||||
# ==============================
|
||||
# Monitor is at the begining of DRAM
|
||||
MONITOR_ADDR = DRAM_BASE
|
||||
|
||||
ATF_SIZE = 512 * SIZE_1K
|
||||
OPENSBI_SIZE = 512 * SIZE_1K
|
||||
OPENSBI_FDT_ADDR = MONITOR_ADDR + OPENSBI_SIZE
|
||||
|
||||
# =========================
|
||||
# memory@DRAM_BASE in .dts.
|
||||
# =========================
|
||||
# Ignore the area of FreeRTOS in u-boot and kernel
|
||||
KERNEL_MEMORY_ADDR = DRAM_BASE
|
||||
KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
|
||||
|
||||
# =================
|
||||
# Multimedia buffer. Used by u-boot/kernel/FreeRTOS
|
||||
# =================
|
||||
ION_SIZE = 26.5 * SIZE_1M
|
||||
H26X_BITSTREAM_SIZE = 0 * SIZE_1M
|
||||
H26X_ENC_BUFF_SIZE = 0
|
||||
ISP_MEM_BASE_SIZE = 0 * SIZE_1M
|
||||
FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE
|
||||
|
||||
# ION after FreeRTOS
|
||||
ION_ADDR = FREERTOS_ADDR - ION_SIZE
|
||||
|
||||
# Buffers of the fast image are inside the ION buffer
|
||||
H26X_BITSTREAM_ADDR = ION_ADDR
|
||||
H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
|
||||
ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
|
||||
|
||||
assert ISP_MEM_BASE_ADDR + ISP_MEM_BASE_SIZE <= ION_ADDR + ION_SIZE
|
||||
|
||||
# Boot logo is after the ION buffer
|
||||
# Framebuffer uses boot logo's reserved memory
|
||||
BOOTLOGO_SIZE = 0 * SIZE_1M
|
||||
BOOTLOGO_ADDR = ION_ADDR - BOOTLOGO_SIZE
|
||||
FRAMEBUFFER_SIZE = BOOTLOGO_SIZE
|
||||
FRAMEBUFFER_ADDR = BOOTLOGO_ADDR
|
||||
|
||||
# ===================
|
||||
# FSBL and u-boot-2021
|
||||
# ===================
|
||||
CVI_UPDATE_HEADER_SIZE = SIZE_1K
|
||||
UIMAG_SIZE = 15 * SIZE_1M
|
||||
|
||||
# kernel image loading buffer
|
||||
UIMAG_ADDR = DRAM_BASE + 20 * SIZE_1M
|
||||
CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR - CVI_UPDATE_HEADER_SIZE
|
||||
|
||||
# FSBL decompress buffer
|
||||
FSBL_UNZIP_ADDR = UIMAG_ADDR
|
||||
FSBL_UNZIP_SIZE = UIMAG_SIZE
|
||||
|
||||
assert UIMAG_ADDR + UIMAG_SIZE <= BOOTLOGO_ADDR
|
||||
|
||||
# u-boot's run address and entry point
|
||||
CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
|
||||
# u-boot's init stack point is only used before board_init_f()
|
||||
CONFIG_SYS_INIT_SP_ADDR = UIMAG_ADDR + UIMAG_SIZE
|
||||
@ -1,91 +0,0 @@
|
||||
SIZE_1M = 0x100000
|
||||
SIZE_1K = 1024
|
||||
|
||||
|
||||
# Only attributes in class MemoryMap are generated to .h
|
||||
class MemoryMap:
|
||||
# No prefix "CVIMMAP_" for the items in _no_prefix[]
|
||||
_no_prefix = [
|
||||
"CONFIG_SYS_TEXT_BASE", # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
|
||||
"CONFIG_SPL_SIZE_LIMIT",
|
||||
"CONFIG_SPL_TEXT_BASE",
|
||||
]
|
||||
|
||||
DRAM_BASE = 0x80000000
|
||||
DRAM_SIZE = 128 * SIZE_1M
|
||||
|
||||
# ==============
|
||||
# C906L FreeRTOS
|
||||
# ==============
|
||||
FREERTOS_SIZE = 768 * SIZE_1K
|
||||
# FreeRTOS is at the end of DRAM
|
||||
FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
|
||||
FSBL_C906L_START_ADDR = FREERTOS_ADDR
|
||||
|
||||
# ==============================
|
||||
# OpenSBI | arm-trusted-firmware
|
||||
# ==============================
|
||||
# Monitor is at the begining of DRAM
|
||||
MONITOR_ADDR = DRAM_BASE
|
||||
|
||||
ATF_SIZE = 512 * SIZE_1K
|
||||
OPENSBI_SIZE = 512 * SIZE_1K
|
||||
OPENSBI_FDT_ADDR = MONITOR_ADDR + OPENSBI_SIZE
|
||||
|
||||
# =========================
|
||||
# memory@DRAM_BASE in .dts.
|
||||
# =========================
|
||||
# Ignore the area of FreeRTOS in u-boot and kernel
|
||||
KERNEL_MEMORY_ADDR = DRAM_BASE
|
||||
KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
|
||||
|
||||
# =================
|
||||
# Multimedia buffer. Used by u-boot/kernel/FreeRTOS
|
||||
# =================
|
||||
ION_SIZE = 70 * SIZE_1M
|
||||
H26X_BITSTREAM_SIZE = 2 * SIZE_1M
|
||||
H26X_ENC_BUFF_SIZE = 0
|
||||
ISP_MEM_BASE_SIZE = 20 * SIZE_1M
|
||||
FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE
|
||||
|
||||
# ION after FreeRTOS
|
||||
ION_ADDR = FREERTOS_ADDR - ION_SIZE
|
||||
|
||||
# Buffers of the fast image are inside the ION buffer
|
||||
H26X_BITSTREAM_ADDR = ION_ADDR
|
||||
H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
|
||||
ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
|
||||
|
||||
assert ISP_MEM_BASE_ADDR + ISP_MEM_BASE_SIZE <= ION_ADDR + ION_SIZE
|
||||
|
||||
# Boot logo is after the ION buffer
|
||||
# Framebuffer uses boot logo's reserved memory
|
||||
BOOTLOGO_SIZE = 1800 * SIZE_1K
|
||||
BOOTLOGO_ADDR = ION_ADDR - BOOTLOGO_SIZE
|
||||
FRAMEBUFFER_SIZE = BOOTLOGO_SIZE
|
||||
FRAMEBUFFER_ADDR = BOOTLOGO_ADDR
|
||||
|
||||
# ===================
|
||||
# FSBL and u-boot-2021
|
||||
# ===================
|
||||
CVI_UPDATE_HEADER_SIZE = SIZE_1K
|
||||
UIMAG_SIZE = 16 * SIZE_1M
|
||||
|
||||
# kernel image loading buffer
|
||||
UIMAG_ADDR = DRAM_BASE + 24 * SIZE_1M
|
||||
CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR - CVI_UPDATE_HEADER_SIZE
|
||||
|
||||
# FSBL decompress buffer
|
||||
FSBL_UNZIP_ADDR = UIMAG_ADDR
|
||||
FSBL_UNZIP_SIZE = UIMAG_SIZE
|
||||
|
||||
assert UIMAG_ADDR + UIMAG_SIZE <= BOOTLOGO_ADDR
|
||||
|
||||
# u-boot's run address and entry point
|
||||
CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
|
||||
# u-boot's init stack point is only used before board_init_f()
|
||||
CONFIG_SYS_INIT_SP_ADDR = UIMAG_ADDR + UIMAG_SIZE
|
||||
|
||||
# uboot-spl
|
||||
CONFIG_SPL_SIZE_LIMIT = SIZE_1M
|
||||
CONFIG_SPL_TEXT_BASE = BOOTLOGO_ADDR - CONFIG_SPL_SIZE_LIMIT
|
||||
@ -1,61 +0,0 @@
|
||||
SIZE_1M = 0x100000
|
||||
SIZE_1K = 1024
|
||||
|
||||
|
||||
# Only attributes in class MemoryMap are generated to .h
|
||||
class MemoryMap:
|
||||
# No prefix "CVIMMAP_" for the items in _no_prefix[]
|
||||
_no_prefix = [
|
||||
"CONFIG_SYS_TEXT_BASE" # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
|
||||
]
|
||||
|
||||
DRAM_BASE = 0x80000000
|
||||
DRAM_SIZE = 2047 * SIZE_1M
|
||||
|
||||
# Bootlogo
|
||||
BOOTLOGO_ADDR = DRAM_BASE + 24 * SIZE_1M
|
||||
BOOTLOGO_SIZE = 1.5 * SIZE_1M
|
||||
|
||||
# C906L freertos
|
||||
FREERTOS_SIZE = 2 * SIZE_1M
|
||||
FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
|
||||
# psu_ddr_0_MEM_0 : ORIGIN = FREERTOS_ADDR, LENGTH = FREERTOS_SIZE
|
||||
|
||||
# OpenSBI | arm-trusted-firmware
|
||||
MONITOR_ADDR = DRAM_BASE
|
||||
|
||||
ATF_SIZE = 512 * SIZE_1K
|
||||
|
||||
OPENSBI_SIZE = 512 * SIZE_1K
|
||||
OPENSBI_FDT_ADDR = DRAM_BASE + SIZE_1M
|
||||
|
||||
# FSBL
|
||||
FSBL_UNZIP_ADDR = DRAM_BASE + 16 * SIZE_1M
|
||||
FSBL_UNZIP_SIZE = DRAM_BASE + 4 * SIZE_1M
|
||||
FSBL_C906L_START_ADDR = FREERTOS_ADDR
|
||||
|
||||
# uboot-2021 defconfig
|
||||
CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
|
||||
CONFIG_SYS_INIT_SP_ADDR = DRAM_BASE + 63 * SIZE_1M
|
||||
|
||||
UIMAG_ADDR = DRAM_BASE + 18 * SIZE_1M
|
||||
CVI_UPDATE_HEADER_SIZE = SIZE_1K
|
||||
CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR + CVI_UPDATE_HEADER_SIZE
|
||||
|
||||
# memory@DRAM_BASE
|
||||
KERNEL_MEMORY_ADDR = DRAM_BASE
|
||||
KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
|
||||
|
||||
ION_ADDR = DRAM_BASE + 0x3C80000
|
||||
ION_SIZE = 65.5 * SIZE_1M
|
||||
|
||||
# Fast image buffer
|
||||
H26X_BITSTREAM_ADDR = DRAM_BASE + 39 * SIZE_1M
|
||||
H26X_BITSTREAM_SIZE = 2 * SIZE_1M
|
||||
|
||||
H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
|
||||
H26X_ENC_BUFF_SIZE = 0
|
||||
|
||||
ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
|
||||
ISP_MEM_BASE_SIZE = 10 * SIZE_1M
|
||||
FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE
|
||||
@ -1,91 +0,0 @@
|
||||
SIZE_1M = 0x100000
|
||||
SIZE_1K = 1024
|
||||
|
||||
|
||||
# Only attributes in class MemoryMap are generated to .h
|
||||
class MemoryMap:
|
||||
# No prefix "CVIMMAP_" for the items in _no_prefix[]
|
||||
_no_prefix = [
|
||||
"CONFIG_SYS_TEXT_BASE", # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
|
||||
"CONFIG_SPL_SIZE_LIMIT",
|
||||
"CONFIG_SPL_TEXT_BASE",
|
||||
]
|
||||
|
||||
DRAM_BASE = 0x80000000
|
||||
DRAM_SIZE = 64 * SIZE_1M
|
||||
|
||||
# ==============
|
||||
# C906L FreeRTOS
|
||||
# ==============
|
||||
FREERTOS_SIZE = 768 * SIZE_1K
|
||||
# FreeRTOS is at the end of DRAM
|
||||
FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
|
||||
FSBL_C906L_START_ADDR = FREERTOS_ADDR
|
||||
|
||||
# ==============================
|
||||
# OpenSBI | arm-trusted-firmware
|
||||
# ==============================
|
||||
# Monitor is at the begining of DRAM
|
||||
MONITOR_ADDR = DRAM_BASE
|
||||
|
||||
ATF_SIZE = 256 * SIZE_1K
|
||||
OPENSBI_SIZE = 256 * SIZE_1K
|
||||
OPENSBI_FDT_ADDR = MONITOR_ADDR + OPENSBI_SIZE
|
||||
|
||||
# =========================
|
||||
# memory@DRAM_BASE in .dts.
|
||||
# =========================
|
||||
# Ignore the area of FreeRTOS in u-boot and kernel
|
||||
KERNEL_MEMORY_ADDR = DRAM_BASE
|
||||
KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
|
||||
|
||||
# =================
|
||||
# Multimedia buffer. Used by u-boot/kernel/FreeRTOS
|
||||
# =================
|
||||
ION_SIZE = 26.5 * SIZE_1M
|
||||
H26X_BITSTREAM_SIZE = 0 * SIZE_1M
|
||||
H26X_ENC_BUFF_SIZE = 0
|
||||
ISP_MEM_BASE_SIZE = 0 * SIZE_1M
|
||||
FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE
|
||||
|
||||
# ION after FreeRTOS
|
||||
ION_ADDR = FREERTOS_ADDR - ION_SIZE
|
||||
|
||||
# Buffers of the fast image are inside the ION buffer
|
||||
H26X_BITSTREAM_ADDR = ION_ADDR
|
||||
H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
|
||||
ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
|
||||
|
||||
assert ISP_MEM_BASE_ADDR + ISP_MEM_BASE_SIZE <= ION_ADDR + ION_SIZE
|
||||
|
||||
# Boot logo is after the ION buffer
|
||||
# Framebuffer uses boot logo's reserved memory
|
||||
BOOTLOGO_SIZE = 0 * SIZE_1K
|
||||
BOOTLOGO_ADDR = ION_ADDR - BOOTLOGO_SIZE
|
||||
FRAMEBUFFER_SIZE = BOOTLOGO_SIZE
|
||||
FRAMEBUFFER_ADDR = BOOTLOGO_ADDR
|
||||
|
||||
# ===================
|
||||
# FSBL and u-boot-2021
|
||||
# ===================
|
||||
CVI_UPDATE_HEADER_SIZE = SIZE_1K
|
||||
UIMAG_SIZE = 15 * SIZE_1M
|
||||
|
||||
# kernel image loading buffer
|
||||
UIMAG_ADDR = DRAM_BASE + 20 * SIZE_1M
|
||||
CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR - CVI_UPDATE_HEADER_SIZE
|
||||
|
||||
# FSBL decompress buffer
|
||||
FSBL_UNZIP_ADDR = UIMAG_ADDR
|
||||
FSBL_UNZIP_SIZE = UIMAG_SIZE
|
||||
|
||||
assert UIMAG_ADDR + UIMAG_SIZE <= BOOTLOGO_ADDR
|
||||
|
||||
# u-boot's run address and entry point
|
||||
CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
|
||||
# u-boot's init stack point is only used before board_init_f()
|
||||
CONFIG_SYS_INIT_SP_ADDR = UIMAG_ADDR + UIMAG_SIZE
|
||||
|
||||
# uboot-spl
|
||||
CONFIG_SPL_SIZE_LIMIT = SIZE_1M
|
||||
CONFIG_SPL_TEXT_BASE = BOOTLOGO_ADDR - CONFIG_SPL_SIZE_LIMIT
|
||||
@ -1,11 +0,0 @@
|
||||
<physical_partition type="emmc">
|
||||
<partition label="BOOT" size_in_kb="8192" file="boot.emmc" />
|
||||
<partition label="MISC" size_in_kb="512" file="logo.jpg" />
|
||||
<!-- Beware that in emmc u-boot environment should be 0x40000 alignment -->
|
||||
<partition label="ENV" size_in_kb="128" file="" />
|
||||
<partition label="ROOTFS" size_in_kb="70656" file="rootfs.emmc" />
|
||||
<partition label="SYSTEM" size_in_kb="40960" file="system.emmc" type="ext4" />
|
||||
<partition label="CFG" size_in_kb="15240" file="cfg.emmc" mountpoint="/mnt/cfg" type="ext4" />
|
||||
<partition label="DATA" size_in_kb="3145728" file="" mountpoint="/mnt/data" type="ext4"/>
|
||||
</physical_partition>
|
||||
|
||||
@ -1,3 +0,0 @@
|
||||
<physical_partition type="none">
|
||||
</physical_partition>
|
||||
|
||||
@ -1,7 +0,0 @@
|
||||
<physical_partition type="sd">
|
||||
<partition label="fip" size_in_kb="2560" file="fip.bin"/>
|
||||
<partition label="BOOT" size_in_kb="8192" file="boot.sd"/>
|
||||
<partition label="MISC" size_in_kb="384" file="logo.jpg" />
|
||||
<partition label="ROOTFS" size_in_kb="71680" file="rootfs.sd" />
|
||||
</physical_partition>
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
<physical_partition type="spinand">
|
||||
<partition label="fip" size_in_kb="2560" file="fip.bin"/>
|
||||
<partition label="BOOT" size_in_kb="4096" file="boot.spinand"/>
|
||||
<partition label="MISC" size_in_kb="384" file="logo.jpg" />
|
||||
<partition label="ENV" size_in_kb="128" file="" />
|
||||
<partition label="ENV_BAK" size_in_kb="128" file="" />
|
||||
<partition label="ROOTFS" size_in_kb="71680" file="rootfs.spinand" />
|
||||
<partition label="SYSTEM" size_in_kb="20480" file="system.spinand" mountpoint="" type="ubifs" />
|
||||
<partition label="CFG" size_in_kb="4096" file="cfg.spinand" mountpoint="/mnt/cfg" type="ubifs" />
|
||||
<partition label="DATA" file="" mountpoint="/mnt/data" type="ubifs" />
|
||||
</physical_partition>
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
<physical_partition type="spinand">
|
||||
<partition label="fip" size_in_kb="5120" file="fip.bin"/>
|
||||
<partition label="BOOT" size_in_kb="8192" file="boot.spinand"/>
|
||||
<partition label="MISC" size_in_kb="512" file="logo.jpg" />
|
||||
<partition label="ENV" size_in_kb="256" file="" />
|
||||
<partition label="ENV_BAK" size_in_kb="256" file="" />
|
||||
<partition label="ROOTFS" size_in_kb="71680" file="rootfs.spinand" />
|
||||
<partition label="SYSTEM" size_in_kb="20480" file="system.spinand" mountpoint="" type="ubifs" />
|
||||
<partition label="CFG" size_in_kb="8192" file="cfg.spinand" mountpoint="/mnt/cfg" type="ubifs" />
|
||||
<partition label="DATA" file="" mountpoint="/mnt/data" type="ubifs" />
|
||||
</physical_partition>
|
||||
|
||||
@ -1,9 +0,0 @@
|
||||
<physical_partition type="spinor">
|
||||
<partition label="fip" size_in_kb="640" readonly="false" file="fip.bin"/>
|
||||
<partition label="BOOT" size_in_kb="3072" readonly="false" file="boot.spinor"/>
|
||||
<partition label="ENV" size_in_kb="64" file="" />
|
||||
<partition label="ENV_BAK" size_in_kb="64" file="" />
|
||||
<partition label="ROOTFS" size_in_kb="11520" readonly="false" file="rootfs.spinor" />
|
||||
<partition label="DATA" size_in_kb="512" readonly="false" file="data.spinor" mountpoint="/mnt/data" type="jffs2" />
|
||||
</physical_partition>
|
||||
|
||||
@ -1,9 +0,0 @@
|
||||
<physical_partition type="spinor">
|
||||
<partition label="fip" size_in_kb="1024" readonly="false" file="fip.bin"/>
|
||||
<partition label="BOOT" size_in_kb="3072" readonly="false" file="boot.spinor"/>
|
||||
<partition label="ENV" size_in_kb="64" file="" />
|
||||
<partition label="ENV_BAK" size_in_kb="64" file="" />
|
||||
<partition label="ROOTFS" size_in_kb="10240" readonly="false" file="rootfs.spinor" />
|
||||
<partition label="DATA" size_in_kb="512" readonly="false" file="data.spinor" mountpoint="/mnt/data" type="jffs2" />
|
||||
</physical_partition>
|
||||
|
||||
@ -1,67 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
SYSTEM_DIR=$1
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libz*
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libz*
|
||||
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/3rd/libcvi*
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/3rd/libmad*
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/3rd/libmp3*
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/3rd/libopencv*
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libopencv*
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libcvi_rtsp.so
|
||||
rm -f $SYSTEM_DIR/mnt/system/data/install/lib/libcvi_rtsp.so
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libcvikernel.so
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/*.a
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libgst*
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libg*
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/gstreamer-1.0/libgst*
|
||||
rm -f $SYSTEM_DIR/mnt/system/data/install/lib/libcrypto.so*
|
||||
rm -f $SYSTEM_DIR/mnt/system/data/install/lib/libssl.so*
|
||||
rm -f $SYSTEM_DIR/mnt/system/data/install/lib/libcvi_protobuf.so*
|
||||
rm -f $SYSTEM_DIR/mnt/system/data/install/lib/libprotobuf-lite.so*
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libcviai*
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libcvi_ispd.so*
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libraw_replay.so*
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libcvi_ive_tpu.so*
|
||||
rm -rf $SYSTEM_DIR/mnt/system/usr/lib/gio
|
||||
rm -rf $SYSTEM_DIR/mnt/system/usr/lib/glib*
|
||||
rm -rf $SYSTEM_DIR/mnt/system/usr/lib/gstreamer-1.0*
|
||||
rm -rf $SYSTEM_DIR/mnt/system/usr/libexec*
|
||||
rm -rf $SYSTEM_DIR/mnt/system/usr/bin
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libcvimath.so
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libcviruntime.so
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libcnpy.so
|
||||
rm -f $SYSTEM_DIR/mnt/system/usr/lib/libcipher.so
|
||||
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libcipher.so*
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libcvi_ispd.so*
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libraw_replay.so*
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libmad.so*
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libmp3*
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libnanomsg*
|
||||
|
||||
#del 3rdparty lib
|
||||
#del thttpd/libwebsockets lib
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libthttpd*
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libwebsocket*
|
||||
if [ $SDK_VER = "uclibc" ]
|
||||
then
|
||||
#del opencv lib
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libopencv*
|
||||
#del ffmpeg lib
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libav*
|
||||
#save /mnt/system/lib/ openssl lib; need by ntpdate/wpa_supplicant
|
||||
else
|
||||
#glibc ramdisk(rootfs/common_arm/usr/lib/) has libcrypto.so and libssl.so
|
||||
#del openssl
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libssl*
|
||||
rm -f $SYSTEM_DIR/mnt/system/lib/libcrypto*
|
||||
fi
|
||||
|
||||
du -sh $SYSTEM_DIR/* |sort -rh
|
||||
du -sh $SYSTEM_DIR/mnt/* |sort -rh
|
||||
du -sh $SYSTEM_DIR/mnt/system/* |sort -rh
|
||||
du -sh $SYSTEM_DIR/mnt/system/lib/* |sort -rh
|
||||
du -sh $SYSTEM_DIR/mnt/system/data/install/* |sort -rh
|
||||
du -sh $SYSTEM_DIR/usr/* |sort -rh
|
||||
@ -1,45 +0,0 @@
|
||||
#!/bin/bash
|
||||
function print_usage(){
|
||||
echo "usage: $0 path"
|
||||
exit 1
|
||||
}
|
||||
|
||||
if [[ -z $1 ]];then
|
||||
print_usage
|
||||
fi
|
||||
|
||||
pushd $1
|
||||
|
||||
sed -i 's/\/etc\/resolv.conf/\/run\/resolv.conf/g' usr/default.script
|
||||
sed -i 's/\/etc\/resolv.conf/\/run\/resolv.conf/g' usr/share/udhcpc/default.script
|
||||
|
||||
# modify rootfs/init to remove busybox install
|
||||
cp init_ramboot.sh.sqsh init
|
||||
rm init.*sh
|
||||
|
||||
mkdir -p mnt/tmp
|
||||
mkdir -p mnt/system
|
||||
mkdir -p mnt/data
|
||||
mkdir -p mnt/usb
|
||||
mkdir -p mnt/sd
|
||||
mkdir -p mnt/nfs
|
||||
mkdir -p mnt/cfg
|
||||
mkdir -p dev
|
||||
mkdir -p sys/dev
|
||||
mkdir -p proc
|
||||
mkdir -p tmp
|
||||
mkdir -p var/empty
|
||||
mkdir -p var/lib
|
||||
mkdir -p var/lock
|
||||
mkdir -p var/log
|
||||
mkdir -p var/run
|
||||
mkdir -p var/spool
|
||||
mkdir -p root
|
||||
mkdir -p run
|
||||
mkdir -p overlay
|
||||
|
||||
chmod 0600 etc/ssh/*_key
|
||||
chmod 0600 etc/ssh/*.pub
|
||||
ln -sf /proc/mounts etc/mtab
|
||||
|
||||
popd
|
||||
@ -1,41 +0,0 @@
|
||||
int cvi_board_init(void)
|
||||
{
|
||||
#if defined(CV180X_QFN_88_PIN)
|
||||
PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL);
|
||||
PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA);
|
||||
PINMUX_CONFIG(PAD_MIPI_TXP0, XGPIOC_13);
|
||||
PINMUX_CONFIG(PAD_MIPI_TXM0, CAM_MCLK1);
|
||||
#elif defined(CV180X_QFN_88_PIN_38)
|
||||
//I2C2
|
||||
PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL);
|
||||
PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA);
|
||||
//CAM_RST0
|
||||
PINMUX_CONFIG(PAD_MIPI_TXP2, XGPIOC_17);
|
||||
PINMUX_CONFIG(PAD_MIPI_TXM2, XGPIOC_16);
|
||||
//CAM_MCLK0
|
||||
PINMUX_CONFIG(PAD_MIPI_TXP0, CAM_MCLK0);
|
||||
PINMUX_CONFIG(PAD_MIPI_TXM0, XGPIOC_12);
|
||||
//IRCUT
|
||||
//PINMUX_CONFIG(SD1_D2, PWR_GPIO19);
|
||||
//PINMUX_CONFIG(SD1_D3, PWR_GPIO18);
|
||||
|
||||
#elif defined(CV180X_QFN_68_PIN)
|
||||
// PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA);
|
||||
// PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL);
|
||||
// PINMUX_CONFIG(PAD_MIPIRX1N, XGPIOC_8);
|
||||
// PINMUX_CONFIG(PAD_MIPIRX0P, CAM_MCLK0);
|
||||
//IRCUT
|
||||
//PINMUX_CONFIG(SD1_D2, PWR_GPIO19);
|
||||
//PINMUX_CONFIG(SD1_D3, PWR_GPIO18);
|
||||
|
||||
#endif
|
||||
PINMUX_CONFIG(PAD_MIPIRX4N, XGPIOC_2);
|
||||
PINMUX_CONFIG(PAD_MIPIRX4P, XGPIOC_3);
|
||||
PINMUX_CONFIG(SD1_D0, PWR_GPIO_21);
|
||||
PINMUX_CONFIG(SD1_CMD, IIC3_SCL);
|
||||
PINMUX_CONFIG(SD1_CLK, IIC3_SDA);
|
||||
PINMUX_CONFIG(PAD_ETH_TXP, IIS2_LRCK);
|
||||
PINMUX_CONFIG(PAD_ETH_TXM, IIS2_BCLK);
|
||||
PINMUX_CONFIG(PAD_ETH_RXM, IIS2_DI);
|
||||
return 0;
|
||||
}
|
||||
@ -1,44 +0,0 @@
|
||||
CONFIG_RISCV=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="cv180x_asic"
|
||||
CONFIG_IDENT_STRING=" cvitek_cv180x"
|
||||
CONFIG_ARCH_RV64I=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
CONFIG_TARGET_CVITEK_CV180X=y
|
||||
CONFIG_CVITEK_SPI_FLASH=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTDELAY=1
|
||||
CONFIG_SYS_PROMPT="cv180x_c906# "
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_CVI_SD_UPDATE=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_CVITEK=y
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_PHY_SMSC is not set
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_PHY_CVITEK=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_LZMA=y
|
||||
# CONFIG_TOOLS_LIBCRYPTO is not set
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
@ -1,12 +0,0 @@
|
||||
int cvi_board_init(void)
|
||||
{
|
||||
PINMUX_CONFIG(CAM_MCLK0, CAM_MCLK0);
|
||||
|
||||
PINMUX_CONFIG(IIC2_SCL, IIC2_SCL);
|
||||
PINMUX_CONFIG(IIC2_SDA, IIC2_SDA);
|
||||
|
||||
PINMUX_CONFIG(IIC3_SCL, IIC3_SCL);
|
||||
PINMUX_CONFIG(IIC3_SDA, IIC3_SDA);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,12 +0,0 @@
|
||||
int cvi_board_init(void)
|
||||
{
|
||||
PINMUX_CONFIG(IIC0_SCL, CV_SCL0__CR_4WTDI);
|
||||
PINMUX_CONFIG(IIC0_SDA, CV_SDA0__CR_4WTDO);
|
||||
|
||||
PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL);
|
||||
PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA);
|
||||
PINMUX_CONFIG(PAD_MIPI_TXP0, XGPIOC_13);
|
||||
PINMUX_CONFIG(PAD_MIPI_TXM0, CAM_MCLK1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,45 +0,0 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
|
||||
CONFIG_IDENT_STRING=" cvitek_cv181x"
|
||||
CONFIG_ARMV8_SET_SMPEN=y
|
||||
CONFIG_TARGET_CVITEK_CV181X=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTDELAY=1
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_SYS_PROMPT="cv181x# "
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_CVI_SD_UPDATE=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_CVITEK=y
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_PHY_SMSC is not set
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_PHY_CVITEK=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_LZMA=y
|
||||
# CONFIG_TOOLS_LIBCRYPTO is not set
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
@ -1,49 +0,0 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
|
||||
CONFIG_IDENT_STRING=" cvitek_cv181x"
|
||||
CONFIG_ARMV8_SET_SMPEN=y
|
||||
CONFIG_TARGET_CVITEK_CV181X=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTDELAY=1
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_SYS_PROMPT="cv181x# "
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_CVI_SD_UPDATE=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_CVITEK=y
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_SPI_FLASH is not set
|
||||
# CONFIG_PHY_SMSC is not set
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_PHY_CVITEK=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_LZMA=y
|
||||
# CONFIG_TOOLS_LIBCRYPTO is not set
|
||||
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FLASH_CVSNFC_V3=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
@ -1,45 +0,0 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
|
||||
CONFIG_IDENT_STRING=" cvitek_cv181x"
|
||||
CONFIG_ARMV8_SET_SMPEN=y
|
||||
CONFIG_TARGET_CVITEK_CV181X=y
|
||||
CONFIG_CVITEK_SPI_FLASH=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTDELAY=1
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_SYS_PROMPT="cv181x# "
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_CVI_SD_UPDATE=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_CVITEK=y
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_PHY_SMSC is not set
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_PHY_CVITEK=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_LZMA=y
|
||||
# CONFIG_TOOLS_LIBCRYPTO is not set
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
@ -1,43 +0,0 @@
|
||||
CONFIG_RISCV=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
|
||||
CONFIG_IDENT_STRING=" cvitek_cv181x"
|
||||
CONFIG_ARCH_RV64I=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
CONFIG_TARGET_CVITEK_CV181X=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTDELAY=1
|
||||
CONFIG_SYS_PROMPT="cv181x_c906# "
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_CVI_SD_UPDATE=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_CVITEK=y
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_PHY_SMSC is not set
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_PHY_CVITEK=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_LZMA=y
|
||||
# CONFIG_TOOLS_LIBCRYPTO is not set
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
@ -1,47 +0,0 @@
|
||||
CONFIG_RISCV=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
|
||||
CONFIG_IDENT_STRING=" cvitek_cv181x"
|
||||
CONFIG_ARCH_RV64I=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
CONFIG_TARGET_CVITEK_CV181X=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTDELAY=1
|
||||
CONFIG_SYS_PROMPT="cv181x_c906# "
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_CVI_SD_UPDATE=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_CVITEK=y
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_SPI_FLASH is not set
|
||||
# CONFIG_PHY_SMSC is not set
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_PHY_CVITEK=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_LZMA=y
|
||||
# CONFIG_TOOLS_LIBCRYPTO is not set
|
||||
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FLASH_CVSNFC_V3=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
@ -1,44 +0,0 @@
|
||||
CONFIG_RISCV=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
|
||||
CONFIG_IDENT_STRING=" cvitek_cv181x"
|
||||
CONFIG_ARCH_RV64I=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
CONFIG_TARGET_CVITEK_CV181X=y
|
||||
CONFIG_CVITEK_SPI_FLASH=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTDELAY=1
|
||||
CONFIG_SYS_PROMPT="cv181x_c906# "
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_CVI_SD_UPDATE=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_CVITEK=y
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_PHY_SMSC is not set
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_PHY_CVITEK=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_LZMA=y
|
||||
# CONFIG_TOOLS_LIBCRYPTO is not set
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
@ -1,13 +0,0 @@
|
||||
/*
|
||||
*VO control GPIOs
|
||||
*/
|
||||
#define VO_GPIO_RESET_PORT portb
|
||||
#define VO_GPIO_RESET_INDEX 5
|
||||
#define VO_GPIO_RESET_ACTIVE GPIO_ACTIVE_LOW
|
||||
#define VO_GPIO_PWM_PORT portb
|
||||
#define VO_GPIO_PWM_INDEX 4
|
||||
#define VO_GPIO_PWM_ACTIVE GPIO_ACTIVE_HIGH
|
||||
#define VO_GPIO_POWER_CT_PORT portb
|
||||
#define VO_GPIO_POWER_CT_INDEX 3
|
||||
#define VO_GPIO_POWER_CT_ACTIVE GPIO_ACTIVE_HIGH
|
||||
|
||||
@ -1,13 +0,0 @@
|
||||
/*
|
||||
*VO control GPIOs
|
||||
*/
|
||||
#define VO_GPIO_RESET_PORT portb
|
||||
#define VO_GPIO_RESET_INDEX 5
|
||||
#define VO_GPIO_RESET_ACTIVE GPIO_ACTIVE_LOW
|
||||
#define VO_GPIO_PWM_PORT portb
|
||||
#define VO_GPIO_PWM_INDEX 4
|
||||
#define VO_GPIO_PWM_ACTIVE GPIO_ACTIVE_HIGH
|
||||
#define VO_GPIO_POWER_CT_PORT portb
|
||||
#define VO_GPIO_POWER_CT_INDEX 3
|
||||
#define VO_GPIO_POWER_CT_ACTIVE GPIO_ACTIVE_HIGH
|
||||
|
||||
@ -1,27 +0,0 @@
|
||||
# uboot-spl
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x200000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SUPPORT_SPL=y
|
||||
CONFIG_SPL_RISCV_SMODE=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
# CONFIG_SPL_SIZE_LIMIT=0x100000
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_FRAMEWORK_BOARD_INIT_F=y
|
||||
CONFIG_SPL_SHOW_ERRORS=y
|
||||
# CONFIG_SPL_BANNER_PRINT is not set
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_LZ4=y
|
||||
CONFIG_SPL_LZMA=y
|
||||
# CONFIG_BINMAN_FDT is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE=""
|
||||
# CONFIG_SPL_ENV_SUPPORT=y
|
||||
# CONFIG_SPL_DM_SPI_FLASH=y
|
||||
# CONFIG_SPL_SPI_SUPPORT=y
|
||||
# CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
# CONFIG_SPL_DM_SPI=y
|
||||
# CONFIG_SPL_SPI_FLASH_TINY=n
|
||||
@ -1,27 +0,0 @@
|
||||
# uboot-spl
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x200000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SUPPORT_SPL=y
|
||||
CONFIG_SPL_RISCV_SMODE=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
# CONFIG_SPL_SIZE_LIMIT=0x100000
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_FRAMEWORK_BOARD_INIT_F=y
|
||||
CONFIG_SPL_SHOW_ERRORS=y
|
||||
# CONFIG_SPL_BANNER_PRINT is not set
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_LZ4=y
|
||||
CONFIG_SPL_LZMA=y
|
||||
# CONFIG_BINMAN_FDT is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE=""
|
||||
# CONFIG_SPL_ENV_SUPPORT=y
|
||||
# CONFIG_SPL_DM_SPI_FLASH=y
|
||||
# CONFIG_SPL_SPI_SUPPORT=y
|
||||
# CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
# CONFIG_SPL_DM_SPI=y
|
||||
# CONFIG_SPL_SPI_FLASH_TINY=n
|
||||
Reference in New Issue
Block a user