4df417855c
-8ead06, add new feature for cv181x/cv180x suspend to ram. Change-Id: I4b4f0fc51b9028d6d006ebcf579b0f4c19007780
182 lines
5.6 KiB
C
182 lines
5.6 KiB
C
#ifndef __DDR_SYS_H__
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#define __DDR_SYS_H__
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#include <mmio.h>
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#include <debug.h>
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extern uint32_t freq_in;
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extern uint32_t tar_freq;
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extern uint32_t mod_freq;
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extern uint32_t dev_freq;
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extern uint64_t reg_set;
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extern uint64_t reg_span;
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extern uint64_t reg_step;
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//extern uint64_t debug_seqnum;
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//extern uint64_t debug_seqnum1;
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extern uint32_t rddata;
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enum bist_mode {
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E_PRBS,
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E_SRAM,
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};
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enum train_mode {
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E_WRLVL,
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E_RDGLVL,
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E_WDQLVL,
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E_RDLVL,
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E_WDQLVL_SW,
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E_RDLVL_SW,
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};
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#define PHY_BASE_ADDR 2048
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#define PI_BASE_ADDR 0
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#define CADENCE_PHYD 0x08000000
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#define CADENCE_PHYD_APB 0x08006000
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#define cfg_base 0x08004000
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#define DDR_SYS_BASE 0x08000000
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// #define PI_BASE (DDR_SYS_BASE + 0x0000)
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#define PHY_BASE (DDR_SYS_BASE + 0x2000)
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#define DDRC_BASE (DDR_SYS_BASE + 0x4000)
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#define PHYD_BASE (DDR_SYS_BASE + 0x6000)
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#define CV_DDR_PHYD_APB (DDR_SYS_BASE + 0x6000)
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#define AXI_MON_BASE (DDR_SYS_BASE + 0x8000)
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// #define TOP_BASE (DDR_SYS_BASE + 0xa000)
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#define DDR_TOP_BASE (DDR_SYS_BASE + 0xa000)
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#define PHYD_BASE_ADDR (DDR_SYS_BASE)
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#define DDR_BIST_BASE 0x08010000
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#define DDR_BIST_SRAM_DQ_BASE 0x08011000
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#define DDR_BIST_SRAM_DM_BASE 0x08011800
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#define mmio_wr32 mmio_write_32
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#define mmio_rd32 mmio_read_32
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// #define ddr_mmio_rd32(a, b) do { if (1) b = mmio_rd32(a); } while (0)
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// #define ddr_sram_rd32(a, b) do { if (1) b = mmio_rd32(a); } while (0)
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#define ddr_sram_wr32(a, b) mmio_wr32(a, b)
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#define ddr_debug_wr32(b)
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// #define uartlog(...) tf_printf(MSG_NOTICE "U: " __VA_ARGS__)
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// #define KC_MSG(...) tf_printf(MSG_NOTICE "[KC_DBG] " __VA_ARGS__)
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// #define KC_MSG_TR(...) tf_printf(MSG_NOTICE "[KC_DBG_training]" __VA_ARGS__)
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// #define TJ_MSG(...) tf_printf(MSG_NOTICE "[TJ Info] : " __VA_ARGS__)
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#define uartlog(...)
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#define KC_MSG(...)
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#define KC_MSG_TR(...)
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#define TJ_MSG(...)
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#ifdef DBG_SHMOO
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#define SHMOO_MSG(...) tf_printf(MSG_NOTICE __VA_ARGS__)
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#else
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#define SHMOO_MSG(...)
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#endif
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#ifdef DBG_SHMOO_CA
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#define SHMOO_MSG_CA(...) tf_printf(MSG_NOTICE __VA_ARGS__)
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#else
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#define SHMOO_MSG_CA(...)
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#endif
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#ifdef DBG_SHMOO_CS
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#define SHMOO_MSG_CS(...) tf_printf(MSG_NOTICE __VA_ARGS__)
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#else
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#define SHMOO_MSG_CS(...)
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#endif
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// void check_rd32(uintptr_t addr, uint32_t expected); //unused
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void ddr_debug_num_write(void);
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void ddr_patch_set(void);
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void cvx16_rdvld_train(void);
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void ddr_sys_suspend(void);
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void ddr_sys_resume(void);
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void cvx16_ddr_sub_resume2(void);
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void cvx16_ddr_sub_resume3(void);
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void cvx16_ddrc_suspend(void);
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void cvx16_bist_wr_prbs_init(void);
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void cvx16_bist_wr_sram_init(void);
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void cvx16_bist_wrlvl_init(void);
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void cvx16_bist_rdglvl_init(void);
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void cvx16_bist_rdlvl_init(uint32_t mode);
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void cvx16_bist_wdqlvl_init(uint32_t mode);
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void cvx16_bist_wdmlvl_init(void);
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void cvx16_bist_start_check(uint32_t *bist_result, uint64_t *err_data_odd, uint64_t *err_data_even);
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void cvx16_bist_tx_shift_delay(uint32_t shift_delay);
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void cvx16_bist_rx_delay(uint32_t delay);
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void cvx16_bist_rx_deskew_delay(uint32_t delay);
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void cvx16_ca_shift_delay(uint32_t shift_delay);
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void cvx16_cs_shift_delay(uint32_t shift_delay);
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void cvx16_synp_mrw(uint32_t addr, uint32_t data);
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void cvx16_chg_pll_freq(void);
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void cvx16_dll_cal(void);
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void cvx16_dll_cal_phyd_hw(void);
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void cvx16_dll_cal_phya_enautok(void);
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void cvx16_ddr_zqcal_isr8(void);
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void cvx16_ddr_zqcal_hw_isr8(uint32_t hw_mode);
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void cvx16_clk_normal(void);
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void cvx16_clk_div2(void);
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void cvx16_INT_ISR_08(void);
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void cvx16_clk_div40(void);
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void cvx16_ddr_phy_power_on_seq1(void);
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void cvx16_ddr_phy_power_on_seq2(void);
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void cvx16_ddr_phy_power_on_seq3(void);
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void cvx16_wait_for_dfi_init_complete(void);
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void cvx16_ctrlupd_short(void);
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void cvx16_polling_dfi_init_start(void);
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void cvx16_set_dfi_init_complete(void);
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void cvx16_polling_synp_normal_mode(void);
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void cvx16_dfi_ca_park_prbs(uint32_t cap_enable);
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void cvx16_wrlvl_req(void);
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void cvx16_rdglvl_req(void);
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void cvx16_rdlvl_req(uint32_t mode);
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void cvx16_rdlvl_sw_req(uint32_t mode);
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void cvx16_wdqlvl_req(uint32_t data_mode, uint32_t lvl_mode);
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void cvx16_wdqlvl_sw_req(uint32_t data_mode, uint32_t lvl_mode);
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void cvx16_wrlvl_status(void);
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void cvx16_rdglvl_status(void);
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void cvx16_rdlvl_status(void);
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void cvx16_wdqlvl_status(void);
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void cvx16_dll_cal_status(void);
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void cvx16_zqcal_status(void);
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void cvx16_training_status(void);
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void cvx16_setting_check(void);
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void cvx16_ddr_freq_change_htol(void);
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void cvx16_ddr_freq_change_ltoh(void);
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void cvx16_set_dq_vref(uint32_t vref);
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void cvx16_set_dfi_init_start(void);
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void cvx16_ddr_phya_pd(void);
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void cvx16_ddr_phyd_save(uint32_t sram_base_addr);
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void cvx16_ddr_phyd_restore(uint32_t sram_base_addr);
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void cvx16_dll_sw_upd(void);
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void cvx16_bist_mask_shift_delay(uint32_t shift_delay, uint32_t en_lead);
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void cvx16_set_dq_trig_lvl(uint32_t trig_lvl);
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void cvx16_pll_init(void);
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void cvx16_lb_0_phase40(void);
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void cvx16_lb_0_external(void);
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void cvx16_lb_1_dq_set_highlow(void);
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void cvx16_lb_2_mux_demux(void);
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void cvx16_lb_3_ca_set_highlow(void);
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void cvx16_lb_4_ca_clk_pat(void);
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void cvx16_clk_gating_disable(void);
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void cvx16_clk_gating_enable(void);
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void cvx16_dfi_phyupd_req(void);
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void cvx16_en_rec_vol_mode(void);
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void cvx16_dll_sw_clr(void);
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void cvx16_reg_toggle(void);
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void cvx16_ana_test(void);
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void cvx16_ddr_zq240(void);
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void cvx16_ddr_zq240_ate(void);
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void cvx16_ddr_zq240_cal(void);
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void ctrl_init_detect_dram_size(uint8_t *dram_cap_in_mbyte);
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uint32_t ddr_bist_all(uint32_t mode, uint32_t capacity, uint32_t x16_mode);
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uint32_t bist_all_dram(uint32_t mode, uint32_t capacity);
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void bist_all_dram_forever(uint32_t capacity);
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void calvl_req(uint32_t capacity);
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void cslvl_req(uint32_t capacity);
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void ddr_training(enum train_mode t_mode);
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#endif /* __DDR_SYS_H__ */
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