824f3ac23c
-e4ccbc, surport cv1810c arm32. -921783, add sensor ov_os02n10_1l. -8b96e4, support 180zb uboot spl. -937493, Sync spacc config. -3e99d9, add phy config for cv180x. -333b4d, fixed the dts file of cv1812cpa. Change-Id: I86ce96f27d890af09a2b26d2cc955936bbc35903
939 lines
23 KiB
Plaintext
939 lines
23 KiB
Plaintext
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/ {
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compatible = "cvitek,cv181x";
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#size-cells = <0x2>;
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#address-cells = <0x2>;
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top_misc:top_misc_ctrl@3000000 {
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compatible = "syscon";
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reg = <0x0 0x03000000 0x0 0x8000>;
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};
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clk_rst: clk-reset-controller {
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#reset-cells = <1>;
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compatible = "cvitek,clk-reset";
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reg = <0x0 0x03002000 0x0 0x8>;
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};
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "osc";
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};
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clk: clock-controller {
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compatible = "cvitek,cv181x-clk";
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reg = <0x0 0x03002000 0x0 0x1000>;
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clocks = <&osc>;
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#clock-cells = <1>;
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};
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rst: reset-controller {
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#reset-cells = <1>;
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compatible = "cvitek,reset";
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reg = <0x0 0x03003000 0x0 0x10>;
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};
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restart: restart-controller {
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compatible = "cvitek,restart";
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reg = <0x0 0x05025000 0x0 0x2000>;
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};
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tpu {
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compatible = "cvitek,tpu";
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reg-names = "tdma", "tiu";
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reg = <0x0 0x0C100000 0x0 0x1000>,
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<0x0 0x0C101000 0x0 0x1000>;
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clocks = <&clk CV181X_CLK_TPU>, <&clk CV181X_CLK_TPU_FAB>;
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clock-names = "clk_tpu_axi", "clk_tpu_fab";
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resets = <&rst RST_TDMA>, <&rst RST_TPU>, <&rst RST_TPUSYS>;
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reset-names = "res_tdma", "res_tpu", "res_tpusys";
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};
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mon {
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compatible = "cvitek,mon";
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reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
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reg = <0x0 0x01040000 0x0 0x1000>,
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<0x0 0x08004000 0x0 0x1000>,
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<0x0 0x08006000 0x0 0x1000>,
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<0x0 0x08008000 0x0 0x1000>,
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<0x0 0x0800A000 0x0 0x1000>;
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};
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wiegand0 {
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compatible = "cvitek,wiegand";
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reg-names = "wiegand";
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reg = <0x0 0x03030000 0x0 0x1000>;
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clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN0>;
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clock-names = "clk_wgn", "clk_wgn1";
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resets = <&rst RST_WGN0>;
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reset-names = "res_wgn";
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};
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wiegand1 {
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compatible = "cvitek,wiegand";
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reg-names = "wiegand";
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reg = <0x0 0x03031000 0x0 0x1000>;
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clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN1>;
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clock-names = "clk_wgn", "clk_wgn1";
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resets = <&rst RST_WGN1>;
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reset-names = "res_wgn";
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};
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wiegand2 {
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compatible = "cvitek,wiegand";
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reg-names = "wiegand";
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reg = <0x0 0x03032000 0x0 0x1000>;
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clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN2>;
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clock-names = "clk_wgn", "clk_wgn1";
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resets = <&rst RST_WGN2>;
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reset-names = "res_wgn";
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};
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saradc {
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compatible = "cvitek,saradc";
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reg-names = "top_domain_saradc", "rtc_domain_saradc";
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reg = <0x0 0x030F0000 0x0 0x1000>, <0x0 0x0502c000 0x0 0x1000>;
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clocks = <&clk CV181X_CLK_SARADC>;
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clock-names = "clk_saradc";
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resets = <&rst RST_SARADC>;
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reset-names = "res_saradc";
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};
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rtc {
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compatible = "cvitek,rtc";
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reg = <0x0 0x05026000 0x0 0x1000>,<0x0 0x05025000 0x0 0x1000>;
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clocks = <&clk CV181X_CLK_RTC_25M>;
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clock-names = "clk_rtc";
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};
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cvitek-ion {
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compatible = "cvitek,cvitek-ion";
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heap_carveout@0 {
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compatible = "cvitek,carveout";
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memory-region = <&ion_reserved>;
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};
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};
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sysdma_remap {
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compatible = "cvitek,sysdma_remap";
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reg = <0x0 0x03000154 0x0 0x10>;
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ch-remap = <CVI_I2S0_RX CVI_I2S2_TX CVI_I2S1_RX CVI_I2S1_TX
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CVI_SPI_NAND CVI_SPI_NAND CVI_I2S2_RX CVI_I2S3_TX>;
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int_mux_base = <0x03000298>;
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};
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dmac: dma@0x4330000 {
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compatible = "snps,dmac-bm";
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reg = <0x0 0x04330000 0x0 0x1000>;
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clock-names = "clk_sdma_axi";
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clocks = <&clk CV181X_CLK_SDMA_AXI>;
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dma-channels = /bits/ 8 <8>;
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#dma-cells = <3>;
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dma-requests = /bits/ 8 <16>;
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chan_allocation_order = /bits/ 8 <0>;
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chan_priority = /bits/ 8 <1>;
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block_size = <1024>;
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dma-masters = /bits/ 8 <2>;
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data-width = <4 4>; /* bytes */
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axi_tr_width = <4>; /* bytes */
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block-ts = <15>;
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};
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watchdog0: cv-wd@0x3010000 {
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compatible = "snps,dw-wdt";
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reg = <0x0 0x03010000 0x0 0x1000>;
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resets = <&rst RST_WDT>;
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clocks = <&pclk>;
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};
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spacc: cvi_spacc@02060000 {
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reg = <0x0 0x02060000 0x0 0x1000>;
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compatible = "cvitek,spacc";
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};
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pwm0: pwm@3060000 {
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compatible = "cvitek,cvi-pwm";
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reg = <0x0 0x3060000 0x0 0x1000>;
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clocks = <&clk CV181X_CLK_PWM>;
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#pwm-cells = <1>;
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};
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pwm1: pwm@3061000 {
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compatible = "cvitek,cvi-pwm";
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reg = <0x0 0x3061000 0x0 0x1000>;
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clocks = <&clk CV181X_CLK_PWM>;
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#pwm-cells = <2>;
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};
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pwm2: pwm@3062000 {
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compatible = "cvitek,cvi-pwm";
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reg = <0x0 0x3062000 0x0 0x1000>;
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clocks = <&clk CV181X_CLK_PWM>;
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#pwm-cells = <3>;
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};
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pwm3: pwm@3063000 {
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compatible = "cvitek,cvi-pwm";
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reg = <0x0 0x3063000 0x0 0x1000>;
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clocks = <&clk CV181X_CLK_PWM>;
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#pwm-cells = <4>;
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};
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pclk: pclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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spinand:cv-spinf@4060000 {
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compatible = "cvitek,cv1835-spinf";
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reg = <0x0 0x4060000 0x0 0x1000>;
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reg-names = "core_mem";
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bus-width = <4>;
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dmas = <&dmac 4 1 1
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&dmac 5 1 1>;
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dma-names = "rx","tx";
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};
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spif:cvi-spif@10000000 {
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compatible = "cvitek,cvi-spif";
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bus-num = <0>;
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reg = <0x0 0x10000000 0x0 0x10000000>;
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reg-names = "spif";
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sck-div = <3>;
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sck_mhz = <300>;
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spi-max-frequency = <75000000>;
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spiflash {
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compatible = "jedec,spi-nor";
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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};
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};
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spi0:spi0@04180000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x0 0x04180000 0x0 0x10000>;
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clocks = <&clk CV181X_CLK_SPI>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1:spi1@04190000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x0 0x04190000 0x0 0x10000>;
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clocks = <&clk CV181X_CLK_SPI>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi2:spi2@041A0000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x0 0x041A0000 0x0 0x10000>;
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clocks = <&clk CV181X_CLK_SPI>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi3:spi3@041B0000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x0 0x041B0000 0x0 0x10000>;
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clocks = <&clk CV181X_CLK_SPI>;
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#address-cells = <1>;
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#size-cells = <0>;
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#if 0
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dmas = <&dmac 2 1 1
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&dmac 3 1 1>;
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dma-names = "rx", "tx";
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capability = "txrx";
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#endif
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};
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uart0: serial@04140000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x04140000 0x0 0x1000>;
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clock-frequency = <25000000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "okay";
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};
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uart1: serial@04150000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x04150000 0x0 0x1000>;
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clock-frequency = <25000000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@04160000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x04160000 0x0 0x1000>;
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clock-frequency = <25000000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@04170000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x04170000 0x0 0x1000>;
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clock-frequency = <25000000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart4: serial@041C0000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x041C0000 0x0 0x1000>;
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clock-frequency = <25000000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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gpio0: gpio@03020000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x03020000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "porta";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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gpio1: gpio@03021000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x03021000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portb: gpio-controller@1 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "portb";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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gpio2: gpio@03022000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x03022000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portc: gpio-controller@2 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "portc";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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gpio3: gpio@03023000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x03023000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portd: gpio-controller@3 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "portd";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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gpio4: gpio@05021000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x05021000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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porte: gpio-controller@4 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "porte";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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i2c0: i2c@04000000 {
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compatible = "snps,designware-i2c";
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clocks = <&clk CV181X_CLK_I2C>;
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reg = <0x0 0x04000000 0x0 0x1000>;
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clock-frequency = <400000>;
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#size-cells = <0x0>;
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#address-cells = <0x1>;
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resets = <&rst RST_I2C0>;
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reset-names = "i2c0";
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};
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i2c1: i2c@04010000 {
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compatible = "snps,designware-i2c";
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clocks = <&clk CV181X_CLK_I2C>;
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reg = <0x0 0x04010000 0x0 0x1000>;
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clock-frequency = <400000>;
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#size-cells = <0x0>;
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#address-cells = <0x1>;
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resets = <&rst RST_I2C1>;
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reset-names = "i2c1";
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};
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i2c2: i2c@04020000 {
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compatible = "snps,designware-i2c";
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clocks = <&clk CV181X_CLK_I2C>;
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reg = <0x0 0x04020000 0x0 0x1000>;
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clock-frequency = <100000>;
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resets = <&rst RST_I2C2>;
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reset-names = "i2c2";
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};
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i2c3: i2c@04030000 {
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compatible = "snps,designware-i2c";
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clocks = <&clk CV181X_CLK_I2C>;
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reg = <0x0 0x04030000 0x0 0x1000>;
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clock-frequency = <400000>;
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resets = <&rst RST_I2C3>;
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reset-names = "i2c3";
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};
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i2c4: i2c@04040000 {
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compatible = "snps,designware-i2c";
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clocks = <&clk CV181X_CLK_I2C>;
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reg = <0x0 0x04040000 0x0 0x1000>;
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clock-frequency = <400000>;
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resets = <&rst RST_I2C4>;
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reset-names = "i2c4";
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};
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eth_csrclk: eth_csrclk {
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clock-output-names = "eth_csrclk";
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clock-frequency = <250000000>;
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#clock-cells = <0x0>;
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compatible = "fixed-clock";
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};
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eth_ptpclk: eth_ptpclk {
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clock-output-names = "eth_ptpclk";
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clock-frequency = <50000000>;
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#clock-cells = <0x0>;
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compatible = "fixed-clock";
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};
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stmmac_axi_setup: stmmac-axi-config {
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snps,wr_osr_lmt = <1>;
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snps,rd_osr_lmt = <2>;
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snps,blen = <4 8 16 0 0 0 0>;
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};
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mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <1>;
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queue0 {};
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};
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mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <1>;
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queue0 {};
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};
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ethernet0: ethernet@4070000 {
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compatible = "cvitek,ethernet";
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reg = <0x0 0x04070000 0x0 0x10000>;
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clock-names = "stmmaceth", "ptp_ref";
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clocks = <ð_csrclk>, <ð_ptpclk>;
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//phy-reset-gpios = <&porta 26 0>;
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ephy_base_reg = <0x3009000>;
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ephy_top_reg = <0x3009800>;
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tx-fifo-depth = <8192>;
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rx-fifo-depth = <8192>;
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/* no hash filter and perfect filter support */
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snps,multicast-filter-bins = <0>;
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snps,perfect-filter-entries = <1>;
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snps,txpbl = <8>;
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snps,rxpbl = <8>;
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snps,aal;
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snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,mtl-rx-config = <&mtl_rx_setup>;
|
|
snps,mtl-tx-config = <&mtl_tx_setup>;
|
|
|
|
phy-mode = "rmii";
|
|
};
|
|
|
|
emmc:cv-emmc@4300000 {
|
|
compatible = "cvitek,cv181x-emmc";
|
|
reg = <0x0 0x4300000 0x0 0x1000>;
|
|
reg-names = "core_mem";
|
|
bus-width = <4>;
|
|
non-removable;
|
|
no-sdio;
|
|
no-sd;
|
|
src-frequency = <375000000>;
|
|
min-frequency = <400000>;
|
|
max-frequency = <200000000>;
|
|
64_addressing;
|
|
reset_tx_rx_phy;
|
|
pll_index = <0x5>;
|
|
pll_reg = <0x3002064>;
|
|
};
|
|
|
|
sd:cv-sd@4310000 {
|
|
compatible = "cvitek,cv181x-sd";
|
|
reg = <0x0 0x4310000 0x0 0x1000>;
|
|
reg-names = "core_mem";
|
|
bus-width = <4>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
sd-uhs-sdr12;
|
|
sd-uhs-sdr25;
|
|
sd-uhs-sdr50;
|
|
sd-uhs-sdr104;
|
|
no-sdio;
|
|
no-mmc;
|
|
/*no-1-8-v;*/
|
|
src-frequency = <375000000>;
|
|
min-frequency = <400000>;
|
|
max-frequency = <200000000>;
|
|
64_addressing;
|
|
reset_tx_rx_phy;
|
|
reset-names = "sdhci";
|
|
pll_index = <0x6>;
|
|
pll_reg = <0x3002070>;
|
|
cvi-cd-gpios = <&porta 13 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wifisd:wifi-sd@4320000 {
|
|
compatible = "cvitek,cv181x-sdio";
|
|
bus-width = <4>;
|
|
reg = <0x0 0x4320000 0x0 0x1000>;
|
|
reg_names = "core_mem";
|
|
src-frequency = <375000000>;
|
|
min-frequency = <400000>;
|
|
max-frequency = <50000000>;
|
|
64_addressing;
|
|
reset_tx_rx_phy;
|
|
non-removable;
|
|
pll_index = <0x7>;
|
|
pll_reg = <0x300207C>;
|
|
no-mmc;
|
|
no-sd;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_mclk: i2s_mclk {
|
|
clock-output-names = "i2s_mclk";
|
|
clock-frequency = <24576000>;
|
|
#clock-cells = <0x0>;
|
|
compatible = "fixed-clock";
|
|
};
|
|
|
|
i2s_subsys {
|
|
compatible = "cvitek,i2s_tdm_subsys";
|
|
reg = <0x0 0x04108000 0x0 0x100>;
|
|
clocks = <&i2s_mclk>, <&clk CV181X_CLK_A0PLL>,
|
|
<&clk CV181X_CLK_SDMA_AUD0>, <&clk CV181X_CLK_SDMA_AUD1>,
|
|
<&clk CV181X_CLK_SDMA_AUD2>, <&clk CV181X_CLK_SDMA_AUD3>;
|
|
clock-names = "i2sclk", "clk_a0pll",
|
|
"clk_sdma_aud0", "clk_sdma_aud1",
|
|
"clk_sdma_aud2", "clk_sdma_aud3";
|
|
master_base = <0x04110000>; /* I2S1 is master, only useful while using multi I2S IPs work on same IO */
|
|
};
|
|
|
|
i2s0: i2s@04100000 {
|
|
compatible = "cvitek,cv1835-i2s";
|
|
reg = <0x0 0x04100000 0x0 0x2000>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
dev-id = <0>;
|
|
#sound-dai-cells = <0>;
|
|
dmas = <&dmac 0 1 1>; /* read channel */
|
|
dma-names = "rx";
|
|
capability = "rx"; /* I2S0 connect to internal ADC as RX */
|
|
mclk_out = "false";
|
|
};
|
|
|
|
i2s1: i2s@04110000 {
|
|
compatible = "cvitek,cv1835-i2s";
|
|
reg = <0x0 0x04110000 0x0 0x2000>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
dev-id = <1>;
|
|
#sound-dai-cells = <0>;
|
|
dmas = <&dmac 2 1 1 /* read channel */
|
|
&dmac 3 1 1>; /* write channel */
|
|
dma-names = "rx", "tx";
|
|
capability = "txrx";
|
|
mclk_out = "false";
|
|
};
|
|
|
|
i2s2: i2s@04120000 {
|
|
compatible = "cvitek,cv1835-i2s";
|
|
reg = <0x0 0x04120000 0x0 0x2000>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
dev-id = <2>;
|
|
#sound-dai-cells = <0>;
|
|
dmas = <&dmac 6 1 1 /* read channel */
|
|
&dmac 1 1 1>; /* write channel */
|
|
dma-names = "rx", "tx";
|
|
capability = "txrx";
|
|
mclk_out = "false";
|
|
|
|
};
|
|
|
|
i2s3: i2s@04130000 {
|
|
compatible = "cvitek,cv1835-i2s";
|
|
reg = <0x0 0x04130000 0x0 0x2000>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
dev-id = <3>;
|
|
#sound-dai-cells = <0>;
|
|
dmas = <&dmac 7 1 1>; /* write channel */
|
|
dma-names = "tx";
|
|
capability = "tx"; /* I2S3 connect to internal DAC as TX */
|
|
mclk_out = "true";
|
|
};
|
|
|
|
adc: adc@0300A100 {
|
|
compatible = "cvitek,cv182xaadc";
|
|
reg = <0x0 0x0300A100 0x0 0x100>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
clk_source = <0x04130000>; /* MCLK source is I2S3 */
|
|
};
|
|
|
|
dac: dac@0300A000 {
|
|
compatible = "cvitek,cv182xadac";
|
|
reg = <0x0 0x0300A000 0x0 0x100>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
};
|
|
|
|
pdm: pdm@0x041D0C00 {
|
|
compatible = "cvitek,cv1835pdm";
|
|
reg = <0x0 0x041D0C00 0x0 0x100>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
};
|
|
|
|
sound_adc {
|
|
compatible = "cvitek,cv182xa-adc";
|
|
cvi,model = "CV182XA";
|
|
cvi,card_name = "cv182xa_adc";
|
|
};
|
|
|
|
sound_dac {
|
|
compatible = "cvitek,cv182xa-dac";
|
|
cvi,model = "CV182XA";
|
|
cvi,card_name = "cv182xa_dac";
|
|
};
|
|
|
|
sound_PDM {
|
|
compatible = "cvitek,cv182x-pdm";
|
|
cvi,model = "CV182X";
|
|
cvi,card_name = "cv182x_internal_PDM";
|
|
};
|
|
|
|
wifi_pin {
|
|
compatible = "cvitek,wifi-pin";
|
|
poweron-gpio = <&porta 18 GPIO_ACTIVE_HIGH>;
|
|
wakeup-gpio = <&porte 7 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
bt_pin {
|
|
compatible = "cvitek,bt-pin";
|
|
poweron-gpio = <&porte 9 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
mipi_rx: cif {
|
|
compatible = "cvitek,cif";
|
|
reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
|
|
<0x0 0x0a0c4000 0x0 0x2000>, <0x0 0x0a0c6000 0x0 0x2000>,
|
|
<0x0 0x03001c30 0x0 0x30>;
|
|
reg-names = "csi_mac0", "csi_wrap0", "csi_mac1", "csi_mac2", "pad_ctrl";
|
|
snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>;
|
|
resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
|
|
<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
|
|
reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
|
|
clocks = <&clk CV181X_CLK_CAM0>, <&clk CV181X_CLK_CAM1>, <&clk CV181X_CLK_SRC_VIP_SYS_2>,
|
|
<&clk CV181X_CLK_MIPIMPLL>, <&clk CV181X_CLK_DISPPLL>, <&clk CV181X_CLK_FPLL>;
|
|
clock-names = "clk_cam0", "clk_cam1", "clk_sys_2",
|
|
"clk_mipimpll", "clk_disppll", "clk_fpll";
|
|
};
|
|
|
|
mipi_tx: mipi_tx {
|
|
compatible = "cvitek,mipi_tx";
|
|
reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
|
|
pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
|
|
power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
|
|
clocks = <&clk CV181X_CLK_DISP_VIP>, <&clk CV181X_CLK_DSI_MAC_VIP>;
|
|
clock-names = "clk_disp", "clk_dsi";
|
|
};
|
|
|
|
sys {
|
|
compatible = "cvitek,sys";
|
|
};
|
|
|
|
base {
|
|
compatible = "cvitek,base";
|
|
reg = <0x0 0x0a0c8000 0x0 0x20>;
|
|
reg-names = "vip_sys";
|
|
};
|
|
|
|
vi {
|
|
compatible = "cvitek,vi";
|
|
reg = <0x0 0x0a000000 0x0 0x80000>;
|
|
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
|
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_SRC_VIP_SYS_3>,
|
|
<&clk CV181X_CLK_AXI_VIP>, <&clk CV181X_CLK_CSI_BE_VIP>,
|
|
<&clk CV181X_CLK_RAW_VIP>, <&clk CV181X_CLK_ISP_TOP_VIP>,
|
|
<&clk CV181X_CLK_CSI_MAC0_VIP>, <&clk CV181X_CLK_CSI_MAC1_VIP>,
|
|
<&clk CV181X_CLK_CSI_MAC2_VIP>;
|
|
clock-names = "clk_sys_0", "clk_sys_1", "clk_sys_2", "clk_sys_3",
|
|
"clk_axi", "clk_csi_be", "clk_raw", "clk_isp_top",
|
|
"clk_csi_mac0", "clk_csi_mac1", "clk_csi_mac2";
|
|
clock-freq-vip-sys1 = <300000000>;
|
|
};
|
|
|
|
vpss {
|
|
compatible = "cvitek,vpss";
|
|
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
|
|
reg-names = "sc";
|
|
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
|
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_IMG_D_VIP>,
|
|
<&clk CV181X_CLK_IMG_V_VIP>, <&clk CV181X_CLK_SC_TOP_VIP>,
|
|
<&clk CV181X_CLK_SC_D_VIP>, <&clk CV181X_CLK_SC_V1_VIP>,
|
|
<&clk CV181X_CLK_SC_V2_VIP>, <&clk CV181X_CLK_SC_V3_VIP>;
|
|
clock-names = "clk_sys_0", "clk_sys_1",
|
|
"clk_sys_2", "clk_img_d",
|
|
"clk_img_v", "clk_sc_top",
|
|
"clk_sc_d", "clk_sc_v1",
|
|
"clk_sc_v2", "clk_sc_v3";
|
|
clock-freq-vip-sys1 = <300000000>;
|
|
};
|
|
|
|
ive {
|
|
compatible = "cvitek,ive";
|
|
reg = <0x0 0x0A0A0000 0x0 0x3100>;
|
|
reg-names = "ive_base";
|
|
};
|
|
|
|
vo:vo {
|
|
compatible = "cvitek,vo";
|
|
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0c8000 0x0 0xa0>, <0x0 0x0a0d1000 0x0 0x100>;
|
|
reg-names = "sc", "vip_sys", "dphy";
|
|
clocks = <&clk CV181X_CLK_DISP_VIP>, <&clk CV181X_CLK_DSI_MAC_VIP>, <&clk CV181X_CLK_BT_VIP>;
|
|
reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
|
|
pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
|
|
power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
|
|
clock-names = "clk_disp", "clk_dsi", "clk_bt";
|
|
};
|
|
|
|
#if (CVIMMAP_FRAMEBUFFER_SIZE > 0)
|
|
reserved-memory {
|
|
#size-cells = <0x2>;
|
|
#address-cells = <0x2>;
|
|
ranges;
|
|
|
|
fb_reserved: cvifb {
|
|
alloc-ranges = <0x0 CVIMMAP_FRAMEBUFFER_ADDR 0 CVIMMAP_FRAMEBUFFER_SIZE>;
|
|
size = <0x0 CVIMMAP_FRAMEBUFFER_SIZE>;
|
|
};
|
|
};
|
|
|
|
cvifb {
|
|
compatible = "cvitek,fb";
|
|
memory-region = <&fb_reserved>;
|
|
reg = <0x0 0x0a088000 0x0 0x1000>;
|
|
reg-names = "disp";
|
|
};
|
|
#endif
|
|
dwa {
|
|
compatible = "cvitek,dwa";
|
|
reg = <0x0 0x0a0c0000 0x0 0x1000>;
|
|
reg-names = "dwa";
|
|
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
|
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_SRC_VIP_SYS_3>,
|
|
<&clk CV181X_CLK_SRC_VIP_SYS_4>, <&clk CV181X_CLK_DWA_VIP>;
|
|
clock-names = "clk_sys_0", "clk_sys_1",
|
|
"clk_sys_2", "clk_sys_3",
|
|
"clk_sys_4", "clk_dwa";
|
|
clock-freq-vip-sys1 = <300000000>;
|
|
};
|
|
|
|
rgn {
|
|
compatible = "cvitek,rgn";
|
|
};
|
|
|
|
vcodec {
|
|
compatible = "cvitek,asic-vcodec";
|
|
reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>,
|
|
<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
|
|
reg-names = "h265","h264","vc_ctrl","vc_sbm","vc_addr_remap";
|
|
clocks = <&clk CV181X_CLK_AXI_VIDEO_CODEC>,
|
|
<&clk CV181X_CLK_H264C>, <&clk CV181X_CLK_APB_H264C>,
|
|
<&clk CV181X_CLK_H265C>, <&clk CV181X_CLK_APB_H265C>,
|
|
<&clk CV181X_CLK_VC_SRC0>, <&clk CV181X_CLK_VC_SRC1>,
|
|
<&clk CV181X_CLK_VC_SRC2>, <&clk CV181X_CLK_CFG_REG_VC>;
|
|
clock-names = "clk_axi_video_codec",
|
|
"clk_h264c", "clk_apb_h264c",
|
|
"clk_h265c", "clk_apb_h265c",
|
|
"clk_vc_src0", "clk_vc_src1",
|
|
"clk_vc_src2", "clk_cfg_reg_vc";
|
|
};
|
|
|
|
jpu {
|
|
compatible = "cvitek,asic-jpeg";
|
|
reg = <0x0 0x0B000000 0x0 0x300>,<0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>;
|
|
reg-names = "jpeg","vc_ctrl","vc_sbm";
|
|
clocks = <&clk CV181X_CLK_AXI_VIDEO_CODEC>,
|
|
<&clk CV181X_CLK_JPEG>, <&clk CV181X_CLK_APB_JPEG>,
|
|
<&clk CV181X_CLK_VC_SRC0>, <&clk CV181X_CLK_VC_SRC1>,
|
|
<&clk CV181X_CLK_VC_SRC2>, <&clk CV181X_CLK_CFG_REG_VC>;
|
|
clock-names = "clk_axi_video_codec",
|
|
"clk_jpeg", "clk_apb_jpeg",
|
|
"clk_vc_src0", "clk_vc_src1",
|
|
"clk_vc_src2", "clk_cfg_reg_vc";
|
|
resets = <&rst RST_JPEG>;
|
|
reset-names = "jpeg";
|
|
};
|
|
|
|
cvi_vc_drv {
|
|
compatible = "cvitek,cvi_vc_drv";
|
|
reg = <0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
|
|
reg-names = "vc_ctrl","vc_sbm","vc_addr_remap";
|
|
};
|
|
|
|
rtos_cmdqu {
|
|
compatible = "cvitek,rtos_cmdqu";
|
|
reg = <0x0 0x01900000 0x0 0x1000>;
|
|
reg-names = "mailbox";
|
|
};
|
|
|
|
usb: usb@04340000 {
|
|
compatible = "cvitek,cv182x-usb";
|
|
reg = <0x0 0x04340000 0x0 0x10000>,
|
|
<0x0 0x03006000 0x0 0x58>; //USB 2.0 PHY
|
|
dr_mode = "otg";
|
|
g-use-dma;
|
|
g-rx-fifo-size = <536>;
|
|
g-np-tx-fifo-size = <32>;
|
|
g-tx-fifo-size = <768 512 512 384 128 128>;
|
|
clocks = <&clk CV181X_CLK_AXI4_USB>,
|
|
<&clk CV181X_CLK_APB_USB>,
|
|
<&clk CV181X_CLK_125M_USB>,
|
|
<&clk CV181X_CLK_33K_USB>,
|
|
<&clk CV181X_CLK_12M_USB>;
|
|
clock-names = "clk_axi", "clk_apb", "clk_125m", "clk_33k", "clk_12m";
|
|
vbus-gpio = <&portb 6 0>;
|
|
status = "okay";
|
|
};
|
|
|
|
thermal:thermal@030E0000 {
|
|
compatible = "cvitek,cv181x-thermal";
|
|
reg = <0x0 0x030E0000 0x0 0x10000>;
|
|
clocks = <&clk CV181X_CLK_TEMPSEN>;
|
|
clock-names = "clk_tempsen";
|
|
reset-names = "tempsen";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
thermal-zones {
|
|
soc_thermal_0: soc_thermal_0 {
|
|
polling-delay-passive = <1000>; /* milliseconds */
|
|
polling-delay = <1000>; /* milliseconds */
|
|
thermal-sensors = <&thermal 0>;
|
|
|
|
trips {
|
|
soc_thermal_trip_0: soc_thermal_trip_0 {
|
|
temperature = <100000>; /* millicelsius */
|
|
hysteresis = <5000>; /* millicelsius */
|
|
type = "passive";
|
|
};
|
|
|
|
soc_thermal_trip_1: soc_thermal_trip_1 {
|
|
temperature = <110000>; /* millicelsius */
|
|
hysteresis = <5000>; /* millicelsius */
|
|
type = "passive";
|
|
};
|
|
|
|
soc_thermal_crtical_0: soc_thermal_crtical_0 {
|
|
temperature = <130000>; /* millicelsius */
|
|
hysteresis = <0>; /* millicelsius */
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
#if 1
|
|
cvipctrl: pinctrl@3001000 {
|
|
compatible = "cvitek,pinctrl-cv182x";
|
|
reg = <0 0x03001000 0 0x1000>;
|
|
};
|
|
#endif
|
|
|
|
cviaudio_core {
|
|
compatible = "cvitek,audio";
|
|
};
|
|
|
|
audio_clock: audio_clock {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
#if 0
|
|
clock-frequency = <12288000>;
|
|
#else
|
|
clock-frequency = <24576000>;
|
|
#endif
|
|
};
|
|
|
|
|
|
aliases {
|
|
i2c0 = &i2c0;
|
|
i2c1 = &i2c1;
|
|
i2c2 = &i2c2;
|
|
i2c3 = &i2c3;
|
|
i2c4 = &i2c4;
|
|
//spi0 = &spi0;
|
|
//spi1 = &spi1;
|
|
//spi2 = &spi2;
|
|
//spi3 = &spi3;
|
|
serial0 = &uart0;
|
|
serial1 = &uart1;
|
|
serial2 = &uart2;
|
|
serial3 = &uart3;
|
|
serial4 = &uart4;
|
|
ethernet0 = ðernet0;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0";
|
|
};
|
|
};
|
|
|