88a2fed916
commit 9f1f57a19c3c281a931dfc71b318494487193d56 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Mon May 13 13:58:23 2024 +0800 [feat] cvikernel opensource for cv18xx soc. - 79b6a7, set lookup_interp_table layer_id.
302 lines
9.4 KiB
C
302 lines
9.4 KiB
C
#ifndef BM1880v2_TDMA_REG_V1_32_H
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#define BM1880v2_TDMA_REG_V1_32_H
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/*
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* This file is generated by tools. Do not edit it manually.
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*/
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#include <stdint.h>
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#include <stdio.h>
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typedef unsigned long long ullong;
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typedef struct {
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uint32_t vld;
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uint32_t compress_en;
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uint32_t eod;
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uint32_t intp_en;
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uint32_t bar_en;
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uint32_t check_bf16_value;
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uint32_t trans_dir;
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uint32_t rsv00;
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uint32_t trans_fmt;
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uint32_t transpose_md;
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uint32_t rsv01;
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uint32_t outstanding_en;
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uint32_t cmd_id;
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uint32_t spec_func;
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uint32_t dst_fmt;
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uint32_t src_fmt;
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uint32_t cmprs_fmt;
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uint32_t sys_dtype;
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uint32_t rsv2_1;
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uint32_t int8_sign;
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uint32_t compress_zero_guard;
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uint32_t int8_rnd_mode;
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uint32_t wait_id_tpu;
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uint32_t wait_id_other_tdma;
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uint32_t wait_id_sdma;
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uint32_t const_val;
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uint32_t src_base_reg_sel;
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uint32_t mv_lut_idx;
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uint32_t dst_base_reg_sel;
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uint32_t mv_lut_base;
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uint32_t rsv4_5;
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uint32_t dst_h_stride;
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uint32_t dst_c_stride_low;
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uint32_t dst_n_stride;
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uint32_t src_h_stride;
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uint32_t src_c_stride_low;
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uint32_t src_n_stride;
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uint32_t dst_c;
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uint32_t src_c;
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uint32_t dst_w;
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uint32_t dst_h;
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uint32_t src_w;
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uint32_t src_h;
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uint32_t dst_base_addr_low;
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uint32_t src_base_addr_low;
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uint32_t src_n;
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uint32_t dst_base_addr_high;
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uint32_t src_base_addr_high;
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uint32_t src_c_stride_high;
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uint32_t dst_c_stride_high;
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uint32_t compress_bias0;
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uint32_t compress_bias1;
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uint32_t layer_ID;
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} tdma_reg_t;
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static inline void parse_tdma_reg(tdma_reg_t *r, const uint32_t *p)
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{
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r->vld = p[0] & 1;
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r->compress_en = (p[0] >> 1) & 1;
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r->eod = (p[0] >> 2) & 1;
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r->intp_en = (p[0] >> 3) & 1;
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r->bar_en = (p[0] >> 4) & 1;
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r->check_bf16_value = (p[0] >> 5) & 1;
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r->trans_dir = (p[0] >> 6) & ((1u << 2) - 1);
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r->rsv00 = (p[0] >> 8) & ((1u << 2) - 1);
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r->trans_fmt = (p[0] >> 10) & 1;
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r->transpose_md = (p[0] >> 11) & ((1u << 2) - 1);
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r->rsv01 = (p[0] >> 13) & ((1u << 2) - 1);
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r->outstanding_en = (p[0] >> 15) & 1;
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r->cmd_id = (p[0] >> 16) & ((1u << 16) - 1);
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r->spec_func = p[1] & ((1u << 3) - 1);
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r->dst_fmt = (p[1] >> 3) & ((1u << 2) - 1);
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r->src_fmt = (p[1] >> 5) & ((1u << 2) - 1);
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r->cmprs_fmt = (p[1] >> 7) & 1;
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r->sys_dtype = (p[1] >> 8) & 1;
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r->rsv2_1 = (p[1] >> 9) & ((1u << 4) - 1);
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r->int8_sign = (p[1] >> 13) & 1;
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r->compress_zero_guard = (p[1] >> 14) & 1;
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r->int8_rnd_mode = (p[1] >> 15) & 1;
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r->wait_id_tpu = (p[1] >> 16) & ((1u << 16) - 1);
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r->wait_id_other_tdma = p[2] & ((1u << 16) - 1);
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r->wait_id_sdma = (p[2] >> 16) & ((1u << 16) - 1);
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r->const_val = p[3] & ((1u << 16) - 1);
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r->src_base_reg_sel = (p[3] >> 16) & ((1u << 3) - 1);
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r->mv_lut_idx = (p[3] >> 19) & 1;
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r->dst_base_reg_sel = (p[3] >> 20) & ((1u << 3) - 1);
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r->mv_lut_base = (p[3] >> 23) & 1;
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r->rsv4_5 = (p[3] >> 24) & ((1u << 8) - 1);
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r->dst_h_stride = p[4] & ((1u << 16) - 1);
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r->dst_c_stride_low = (p[4] >> 16) & ((1u << 16) - 1);
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r->dst_n_stride = p[5];
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r->src_h_stride = p[6] & ((1u << 16) - 1);
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r->src_c_stride_low = (p[6] >> 16) & ((1u << 16) - 1);
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r->src_n_stride = p[7];
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r->dst_c = p[8] & ((1u << 16) - 1);
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r->src_c = (p[8] >> 16) & ((1u << 16) - 1);
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r->dst_w = p[9] & ((1u << 16) - 1);
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r->dst_h = (p[9] >> 16) & ((1u << 16) - 1);
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r->src_w = p[10] & ((1u << 16) - 1);
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r->src_h = (p[10] >> 16) & ((1u << 16) - 1);
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r->dst_base_addr_low = p[11];
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r->src_base_addr_low = p[12];
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r->src_n = p[13] & ((1u << 16) - 1);
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r->dst_base_addr_high = (p[13] >> 16) & ((1u << 8) - 1);
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r->src_base_addr_high = (p[13] >> 24) & ((1u << 8) - 1);
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r->src_c_stride_high = p[14] & ((1u << 16) - 1);
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r->dst_c_stride_high = (p[14] >> 16) & ((1u << 16) - 1);
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r->compress_bias0 = p[15] & ((1u << 8) - 1);
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r->compress_bias1 = (p[15] >> 8) & ((1u << 8) - 1);
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r->layer_ID = (p[15] >> 16) & ((1u << 16) - 1);
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}
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static inline void emit_tdma_reg(const tdma_reg_t *r, uint32_t *_p)
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{
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volatile uint32_t *p = (typeof(p))_p;
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p[15] = (r->compress_bias0 & ((1u << 8) - 1)) |
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((r->compress_bias1 & ((1u << 8) - 1)) << 8) |
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((r->layer_ID & ((1u << 16) - 1)) << 16);
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p[14] = (r->src_c_stride_high & ((1u << 16) - 1)) |
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((r->dst_c_stride_high & ((1u << 16) - 1)) << 16);
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p[13] = (r->src_n & ((1u << 16) - 1)) |
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((r->dst_base_addr_high & ((1u << 8) - 1)) << 16) |
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((r->src_base_addr_high & ((1u << 8) - 1)) << 24);
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p[12] = (r->src_base_addr_low & (((uint64_t)1 << 32) - 1));
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p[11] = (r->dst_base_addr_low & (((uint64_t)1 << 32) - 1));
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p[10] = (r->src_w & ((1u << 16) - 1)) |
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((r->src_h & ((1u << 16) - 1)) << 16);
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p[9] = (r->dst_w & ((1u << 16) - 1)) |
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((r->dst_h & ((1u << 16) - 1)) << 16);
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p[8] = (r->dst_c & ((1u << 16) - 1)) |
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((r->src_c & ((1u << 16) - 1)) << 16);
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p[7] = (r->src_n_stride & (((uint64_t)1 << 32) - 1));
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p[6] = (r->src_h_stride & ((1u << 16) - 1)) |
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((r->src_c_stride_low & ((1u << 16) - 1)) << 16);
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p[5] = (r->dst_n_stride & (((uint64_t)1 << 32) - 1));
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p[4] = (r->dst_h_stride & ((1u << 16) - 1)) |
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((r->dst_c_stride_low & ((1u << 16) - 1)) << 16);
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p[3] = (r->const_val & ((1u << 16) - 1)) |
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((r->src_base_reg_sel & ((1u << 3) - 1)) << 16) |
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((r->mv_lut_idx & 1) << 19) |
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((r->dst_base_reg_sel & ((1u << 3) - 1)) << 20) |
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((r->mv_lut_base & 1) << 23) |
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((r->rsv4_5 & ((1u << 8) - 1)) << 24);
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p[2] = (r->wait_id_other_tdma & ((1u << 16) - 1)) |
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((r->wait_id_sdma & ((1u << 16) - 1)) << 16);
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p[1] = (r->spec_func & ((1u << 3) - 1)) |
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((r->dst_fmt & ((1u << 2) - 1)) << 3) |
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((r->src_fmt & ((1u << 2) - 1)) << 5) |
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((r->cmprs_fmt & 1) << 7) |
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((r->sys_dtype & 1) << 8) |
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((r->rsv2_1 & ((1u << 4) - 1)) << 9) |
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((r->int8_sign & 1) << 13) |
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((r->compress_zero_guard & 1) << 14) |
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((r->int8_rnd_mode & 1) << 15) |
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((r->wait_id_tpu & ((1u << 16) - 1)) << 16);
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p[0] = (r->vld & 1) |
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((r->compress_en & 1) << 1) |
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((r->eod & 1) << 2) |
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((r->intp_en & 1) << 3) |
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((r->bar_en & 1) << 4) |
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((r->check_bf16_value & 1) << 5) |
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((r->trans_dir & ((1u << 2) - 1)) << 6) |
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((r->rsv00 & ((1u << 2) - 1)) << 8) |
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((r->trans_fmt & 1) << 10) |
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((r->transpose_md & ((1u << 2) - 1)) << 11) |
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((r->rsv01 & ((1u << 2) - 1)) << 13) |
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((r->outstanding_en & 1) << 15) |
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((r->cmd_id & ((1u << 16) - 1)) << 16);
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}
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static inline void reset_tdma_reg(tdma_reg_t *r)
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{
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r->vld = 0x0;
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r->compress_en = 0x0;
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r->eod = 0x0;
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r->intp_en = 0x0;
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r->bar_en = 0x0;
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r->check_bf16_value = 0x0;
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r->trans_dir = 0x0;
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r->rsv00 = 0x0;
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r->trans_fmt = 0x0;
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r->transpose_md = 0x0;
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r->rsv01 = 0x0;
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r->outstanding_en = 0x0;
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r->cmd_id = 0x0;
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r->spec_func = 0x0;
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r->dst_fmt = 0x1;
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r->src_fmt = 0x1;
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r->cmprs_fmt = 0x0;
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r->sys_dtype = 0x0;
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r->rsv2_1 = 0x0;
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r->int8_sign = 0x0;
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r->compress_zero_guard = 0x0;
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r->int8_rnd_mode = 0x0;
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r->wait_id_tpu = 0x0;
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r->wait_id_other_tdma = 0x0;
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r->wait_id_sdma = 0x0;
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r->const_val = 0x0;
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r->src_base_reg_sel = 0x0;
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r->mv_lut_idx = 0x0;
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r->dst_base_reg_sel = 0x0;
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r->mv_lut_base = 0x0;
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r->rsv4_5 = 0x0;
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r->dst_h_stride = 0x1;
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r->dst_c_stride_low = 0x1;
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r->dst_n_stride = 0x1;
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r->src_h_stride = 0x1;
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r->src_c_stride_low = 0x1;
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r->src_n_stride = 0x1;
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r->dst_c = 0x1;
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r->src_c = 0x1;
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r->dst_w = 0x1;
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r->dst_h = 0x1;
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r->src_w = 0x1;
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r->src_h = 0x1;
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r->dst_base_addr_low = 0x0;
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r->src_base_addr_low = 0x0;
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r->src_n = 0x1;
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r->dst_base_addr_high = 0x0;
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r->src_base_addr_high = 0x0;
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r->src_c_stride_high = 0x0;
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r->dst_c_stride_high = 0x0;
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r->compress_bias0 = 0x0;
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r->compress_bias1 = 0x0;
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r->layer_ID = 0x0;
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}
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static inline void trace_tdma_reg(tdma_reg_t *r, const char *tag)
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{
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#define trace_one_reg(name) \
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printf(" %s: 0x%llx\n", #name, (ullong)r->name)
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printf("--- %s ---\n", tag);
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trace_one_reg(vld);
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trace_one_reg(compress_en);
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trace_one_reg(eod);
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trace_one_reg(intp_en);
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trace_one_reg(bar_en);
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trace_one_reg(check_bf16_value);
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trace_one_reg(trans_dir);
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trace_one_reg(rsv00);
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trace_one_reg(trans_fmt);
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trace_one_reg(transpose_md);
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trace_one_reg(rsv01);
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trace_one_reg(outstanding_en);
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trace_one_reg(cmd_id);
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trace_one_reg(spec_func);
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trace_one_reg(dst_fmt);
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trace_one_reg(src_fmt);
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trace_one_reg(cmprs_fmt);
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trace_one_reg(sys_dtype);
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trace_one_reg(rsv2_1);
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trace_one_reg(int8_sign);
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trace_one_reg(compress_zero_guard);
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trace_one_reg(int8_rnd_mode);
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trace_one_reg(wait_id_tpu);
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trace_one_reg(wait_id_other_tdma);
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trace_one_reg(wait_id_sdma);
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trace_one_reg(const_val);
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trace_one_reg(src_base_reg_sel);
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trace_one_reg(mv_lut_idx);
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trace_one_reg(dst_base_reg_sel);
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trace_one_reg(mv_lut_base);
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trace_one_reg(rsv4_5);
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trace_one_reg(dst_h_stride);
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trace_one_reg(dst_c_stride_low);
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trace_one_reg(dst_n_stride);
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trace_one_reg(src_h_stride);
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trace_one_reg(src_c_stride_low);
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trace_one_reg(src_n_stride);
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trace_one_reg(dst_c);
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trace_one_reg(src_c);
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trace_one_reg(dst_w);
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trace_one_reg(dst_h);
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trace_one_reg(src_w);
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trace_one_reg(src_h);
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trace_one_reg(dst_base_addr_low);
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trace_one_reg(src_base_addr_low);
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trace_one_reg(src_n);
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trace_one_reg(dst_base_addr_high);
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trace_one_reg(src_base_addr_high);
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trace_one_reg(src_c_stride_high);
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trace_one_reg(dst_c_stride_high);
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trace_one_reg(compress_bias0);
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trace_one_reg(compress_bias1);
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trace_one_reg(layer_ID);
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}
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#endif /* BM1880v2_TDMA_REG_V1_32_H */
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