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[freertos] Upgrade the MMF SDK from V4.0.0 to V4.1.0

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1. Delete some useless files
	2. Add .gitignore file
	3. Some function update

Change-Id: Ie0b31dc20739fbceba20fd78f4fdfeaea4d526b2
This commit is contained in:
wangliang.wang
2023-03-10 00:19:01 +08:00
committed by sam.xiang
parent 909f5d4edb
commit 3818ecf1c0
24 changed files with 1214 additions and 32222 deletions
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4
freertos/.gitignore vendored Normal file
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@ -0,0 +1,4 @@
*.bin
cvitek/task/isp/isp
cvitek/build/

BIN
freertos/cvitek/install/bin/cvirtos.bin
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freertos/cvitek/install/bin/cvirtos.dis
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freertos/cvitek/install/bin/cvirtos.elf
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freertos/cvitek/install/bin/cvirtos.map
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2
freertos/cvitek/install/include/common/cvi_awb_comm.h
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@ -69,6 +69,8 @@ typedef struct _ISP_WB_Q_INFO_S {
CVI_U32 u32FirstStableTime; CVI_U32 u32FirstStableTime;
ISP_AWB_INDOOR_OUTDOOR_STATUS_E enInOutStatus; ISP_AWB_INDOOR_OUTDOOR_STATUS_E enInOutStatus;
CVI_S16 s16Bv; CVI_S16 s16Bv;
CVI_U16 u16GrayWorldRgain;
CVI_U16 u16GrayWorldBgain;
} ISP_WB_Q_INFO_S; } ISP_WB_Q_INFO_S;
#ifdef __cplusplus #ifdef __cplusplus

5
freertos/cvitek/install/include/common/cvi_comm_isp.h
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@ -146,6 +146,7 @@ typedef union _ISP_SNS_COMMBUS_U {
typedef struct _ISP_I2C_DATA_S { typedef struct _ISP_I2C_DATA_S {
CVI_BOOL bUpdate; CVI_BOOL bUpdate;
CVI_BOOL bDropFrm; CVI_BOOL bDropFrm;
CVI_BOOL bvblankUpdate;
CVI_U8 u8DelayFrmNum; /*RW; Number of delayed frames for the sensor register*/ CVI_U8 u8DelayFrmNum; /*RW; Number of delayed frames for the sensor register*/
CVI_U8 u8DropFrmNum; /*RW; Number of frame to drop*/ CVI_U8 u8DropFrmNum; /*RW; Number of frame to drop*/
CVI_U8 u8IntPos; /*RW;Position where the configuration of the sensor register takes effect */ CVI_U8 u8IntPos; /*RW;Position where the configuration of the sensor register takes effect */
@ -904,11 +905,11 @@ enum ISP_AWB_TEMP_E {
struct ST_ISP_AWB_SHIFT_LV_S { struct ST_ISP_AWB_SHIFT_LV_S {
CVI_U8 u8LowLvMode; /*RW; Range:[0x0, 0x1]*/ CVI_U8 u8LowLvMode; /*RW; Range:[0x0, 0x1]*/
CVI_U16 u16LowLvCT[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x0, 0xFF]*/ CVI_U16 u16LowLvCT[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x0, 0xFF]*/
CVI_U16 u16LowLvThr[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x0, 0xF]*/ CVI_U16 u16LowLvThr[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x0, 0x5DC]*/
CVI_U16 u16LowLvRatio[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x64, 0x3E8]*/ CVI_U16 u16LowLvRatio[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x64, 0x3E8]*/
CVI_U8 u8HighLvMode; /*RW; Range:[0x0, 0x1]*/ CVI_U8 u8HighLvMode; /*RW; Range:[0x0, 0x1]*/
CVI_U16 u16HighLvCT[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x0, 0xFF]*/ CVI_U16 u16HighLvCT[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x0, 0xFF]*/
CVI_U16 u16HighLvThr[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x0, 0xF]*/ CVI_U16 u16HighLvThr[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x0, 0x5DC]*/
CVI_U16 u16HighLvRatio[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x64, 0x3E8]*/ CVI_U16 u16HighLvRatio[ISP_AWB_COLORTEMP_NUM]; /*RW; Range:[0x64, 0x3E8]*/
}; };

653
freertos/cvitek/install/include/hal/config/cv181x_pinlist_swconfig.h Normal file
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@ -0,0 +1,653 @@
#define CAM_MCLK0__CAM_MCLK0 0
#define CAM_MCLK0__AUX1 2
#define CAM_MCLK0__XGPIOA_0 3
#define CAM_PD0__IIS1_MCLK 1
#define CAM_PD0__XGPIOA_1 3
#define CAM_PD0__CAM_HS0 4
#define CAM_RST0__XGPIOA_2 3
#define CAM_RST0__CAM_VS0 4
#define CAM_RST0__IIC4_SCL 6
#define CAM_MCLK1__CAM_MCLK1 0
#define CAM_MCLK1__AUX2 2
#define CAM_MCLK1__XGPIOA_3 3
#define CAM_MCLK1__CAM_HS0 4
#define CAM_PD1__IIS1_MCLK 1
#define CAM_PD1__XGPIOA_4 3
#define CAM_PD1__CAM_VS0 4
#define CAM_PD1__IIC4_SDA 6
#define IIC3_SCL__IIC3_SCL 0
#define IIC3_SCL__XGPIOA_5 3
#define IIC3_SDA__IIC3_SDA 0
#define IIC3_SDA__XGPIOA_6 3
#define SD0_CLK__SDIO0_CLK 0
#define SD0_CLK__IIC1_SDA 1
#define SD0_CLK__SPI0_SCK 2
#define SD0_CLK__XGPIOA_7 3
#define SD0_CLK__PWM_15 5
#define SD0_CLK__EPHY_LNK_LED 6
#define SD0_CLK__DBG_0 7
#define SD0_CMD__SDIO0_CMD 0
#define SD0_CMD__IIC1_SCL 1
#define SD0_CMD__SPI0_SDO 2
#define SD0_CMD__XGPIOA_8 3
#define SD0_CMD__PWM_14 5
#define SD0_CMD__EPHY_SPD_LED 6
#define SD0_CMD__DBG_1 7
#define SD0_D0__SDIO0_D_0 0
#define SD0_D0__CAM_MCLK1 1
#define SD0_D0__SPI0_SDI 2
#define SD0_D0__XGPIOA_9 3
#define SD0_D0__UART3_TX 4
#define SD0_D0__PWM_13 5
#define SD0_D0__WG0_D0 6
#define SD0_D0__DBG_2 7
#define SD0_D1__SDIO0_D_1 0
#define SD0_D1__IIC1_SDA 1
#define SD0_D1__AUX0 2
#define SD0_D1__XGPIOA_10 3
#define SD0_D1__UART1_TX 4
#define SD0_D1__PWM_12 5
#define SD0_D1__WG0_D1 6
#define SD0_D1__DBG_3 7
#define SD0_D2__SDIO0_D_2 0
#define SD0_D2__IIC1_SCL 1
#define SD0_D2__AUX1 2
#define SD0_D2__XGPIOA_11 3
#define SD0_D2__UART1_RX 4
#define SD0_D2__PWM_11 5
#define SD0_D2__WG1_D0 6
#define SD0_D2__DBG_4 7
#define SD0_D3__SDIO0_D_3 0
#define SD0_D3__CAM_MCLK0 1
#define SD0_D3__SPI0_CS_X 2
#define SD0_D3__XGPIOA_12 3
#define SD0_D3__UART3_RX 4
#define SD0_D3__PWM_10 5
#define SD0_D3__WG1_D1 6
#define SD0_D3__DBG_5 7
#define SD0_CD__SDIO0_CD 0
#define SD0_CD__XGPIOA_13 3
#define SD0_PWR_EN__SDIO0_PWR_EN 0
#define SD0_PWR_EN__XGPIOA_14 3
#define SPK_EN__XGPIOA_15 3
#define UART0_TX__UART0_TX 0
#define UART0_TX__CAM_MCLK1 1
#define UART0_TX__PWM_4 2
#define UART0_TX__XGPIOA_16 3
#define UART0_TX__UART1_TX 4
#define UART0_TX__AUX1 5
#define UART0_TX__DBG_6 7
#define UART0_RX__UART0_RX 0
#define UART0_RX__CAM_MCLK0 1
#define UART0_RX__PWM_5 2
#define UART0_RX__XGPIOA_17 3
#define UART0_RX__UART1_RX 4
#define UART0_RX__AUX0 5
#define UART0_RX__DBG_7 7
#define EMMC_RSTN__EMMC_RSTN 0
#define EMMC_RSTN__XGPIOA_21 3
#define EMMC_RSTN__AUX2 4
#define EMMC_DAT2__EMMC_DAT_2 0
#define EMMC_DAT2__SPINOR_HOLD_X 1
#define EMMC_DAT2__SPINAND_HOLD 2
#define EMMC_DAT2__XGPIOA_26 3
#define EMMC_CLK__EMMC_CLK 0
#define EMMC_CLK__SPINOR_SCK 1
#define EMMC_CLK__SPINAND_CLK 2
#define EMMC_CLK__XGPIOA_22 3
#define EMMC_DAT0__EMMC_DAT_0 0
#define EMMC_DAT0__SPINOR_MOSI 1
#define EMMC_DAT0__SPINAND_MOSI 2
#define EMMC_DAT0__XGPIOA_25 3
#define EMMC_DAT3__EMMC_DAT_3 0
#define EMMC_DAT3__SPINOR_WP_X 1
#define EMMC_DAT3__SPINAND_WP 2
#define EMMC_DAT3__XGPIOA_27 3
#define EMMC_CMD__EMMC_CMD 0
#define EMMC_CMD__SPINOR_MISO 1
#define EMMC_CMD__SPINAND_MISO 2
#define EMMC_CMD__XGPIOA_23 3
#define EMMC_DAT1__EMMC_DAT_1 0
#define EMMC_DAT1__SPINOR_CS_X 1
#define EMMC_DAT1__SPINAND_CS 2
#define EMMC_DAT1__XGPIOA_24 3
#define JTAG_CPU_TMS__JTAG_CPU_TMS 0
#define JTAG_CPU_TMS__CAM_MCLK0 1
#define JTAG_CPU_TMS__PWM_7 2
#define JTAG_CPU_TMS__XGPIOA_19 3
#define JTAG_CPU_TMS__UART1_RTS 4
#define JTAG_CPU_TMS__AUX0 5
#define JTAG_CPU_TMS__UART1_TX 6
#define JTAG_CPU_TMS__VO_D_28 7
#define JTAG_CPU_TCK__JTAG_CPU_TCK 0
#define JTAG_CPU_TCK__CAM_MCLK1 1
#define JTAG_CPU_TCK__PWM_6 2
#define JTAG_CPU_TCK__XGPIOA_18 3
#define JTAG_CPU_TCK__UART1_CTS 4
#define JTAG_CPU_TCK__AUX1 5
#define JTAG_CPU_TCK__UART1_RX 6
#define JTAG_CPU_TCK__VO_D_29 7
#define JTAG_CPU_TRST__JTAG_CPU_TRST 0
#define JTAG_CPU_TRST__XGPIOA_20 3
#define JTAG_CPU_TRST__VO_D_30 6
#define IIC0_SCL__IIC0_SCL 0
#define IIC0_SCL__UART1_TX 1
#define IIC0_SCL__UART2_TX 2
#define IIC0_SCL__XGPIOA_28 3
#define IIC0_SCL__WG0_D0 5
#define IIC0_SCL__DBG_10 7
#define IIC0_SDA__IIC0_SDA 0
#define IIC0_SDA__UART1_RX 1
#define IIC0_SDA__UART2_RX 2
#define IIC0_SDA__XGPIOA_29 3
#define IIC0_SDA__WG0_D1 5
#define IIC0_SDA__WG1_D0 6
#define IIC0_SDA__DBG_11 7
#define AUX0__AUX0 0
#define AUX0__XGPIOA_30 3
#define AUX0__IIS1_MCLK 4
#define AUX0__VO_D_31 5
#define AUX0__WG1_D1 6
#define AUX0__DBG_12 7
#define PWR_VBAT_DET__PWR_VBAT_DET 0
#define PWR_RSTN__PWR_RSTN 0
#define PWR_SEQ1__PWR_SEQ1 0
#define PWR_SEQ1__PWR_GPIO_3 3
#define PWR_SEQ2__PWR_SEQ2 0
#define PWR_SEQ2__PWR_GPIO_4 3
#define PWR_SEQ3__PWR_SEQ3 0
#define PWR_SEQ3__PWR_GPIO_5 3
#define PTEST__PWR_PTEST 0
#define PWR_WAKEUP0__PWR_WAKEUP0 0
#define PWR_WAKEUP0__PWR_IR0 1
#define PWR_WAKEUP0__PWR_UART0_TX 2
#define PWR_WAKEUP0__PWR_GPIO_6 3
#define PWR_WAKEUP0__UART1_TX 4
#define PWR_WAKEUP0__IIC4_SCL 5
#define PWR_WAKEUP0__EPHY_LNK_LED 6
#define PWR_WAKEUP0__WG2_D0 7
#define PWR_WAKEUP1__PWR_WAKEUP1 0
#define PWR_WAKEUP1__PWR_IR1 1
#define PWR_WAKEUP1__PWR_GPIO_7 3
#define PWR_WAKEUP1__UART1_TX 4
#define PWR_WAKEUP1__IIC4_SCL 5
#define PWR_WAKEUP1__EPHY_LNK_LED 6
#define PWR_WAKEUP1__WG0_D0 7
#define PWR_BUTTON1__PWR_BUTTON1 0
#define PWR_BUTTON1__PWR_GPIO_8 3
#define PWR_BUTTON1__UART1_RX 4
#define PWR_BUTTON1__IIC4_SDA 5
#define PWR_BUTTON1__EPHY_SPD_LED 6
#define PWR_BUTTON1__WG2_D1 7
#define PWR_ON__PWR_ON 0
#define PWR_ON__PWR_GPIO_9 3
#define PWR_ON__UART1_RX 4
#define PWR_ON__IIC4_SDA 5
#define PWR_ON__EPHY_SPD_LED 6
#define PWR_ON__WG0_D1 7
#define XTAL_XIN__PWR_XTAL_CLKIN 0
#define PWR_GPIO0__PWR_GPIO_0 0
#define PWR_GPIO0__UART2_TX 1
#define PWR_GPIO0__PWR_UART0_RX 2
#define PWR_GPIO0__PWM_8 4
#define PWR_GPIO1__PWR_GPIO_1 0
#define PWR_GPIO1__UART2_RX 1
#define PWR_GPIO1__EPHY_LNK_LED 3
#define PWR_GPIO1__PWM_9 4
#define PWR_GPIO1__PWR_IIC_SCL 5
#define PWR_GPIO1__IIC2_SCL 6
#define PWR_GPIO1__PWR_MCU_JTAG_TMS 7
#define PWR_GPIO2__PWR_GPIO_2 0
#define PWR_GPIO2__PWR_SECTICK 2
#define PWR_GPIO2__EPHY_SPD_LED 3
#define PWR_GPIO2__PWM_10 4
#define PWR_GPIO2__PWR_IIC_SDA 5
#define PWR_GPIO2__IIC2_SDA 6
#define PWR_GPIO2__PWR_MCU_JTAG_TCK 7
#define CLK32K__CLK32K 0
#define CLK32K__AUX0 1
#define CLK32K__PWR_MCU_JTAG_TDI 2
#define CLK32K__PWR_GPIO_10 3
#define CLK32K__PWM_2 4
#define CLK32K__KEY_COL0 5
#define CLK32K__CAM_MCLK0 6
#define CLK32K__DBG_0 7
#define CLK25M__CLK25M 0
#define CLK25M__AUX1 1
#define CLK25M__PWR_MCU_JTAG_TDO 2
#define CLK25M__PWR_GPIO_11 3
#define CLK25M__PWM_3 4
#define CLK25M__KEY_COL1 5
#define CLK25M__CAM_MCLK1 6
#define CLK25M__DBG_1 7
#define IIC2_SCL__IIC2_SCL 0
#define IIC2_SCL__PWM_14 1
#define IIC2_SCL__PWR_GPIO_12 3
#define IIC2_SCL__UART2_RX 4
#define IIC2_SCL__KEY_COL2 7
#define IIC2_SDA__IIC2_SDA 0
#define IIC2_SDA__PWM_15 1
#define IIC2_SDA__PWR_GPIO_13 3
#define IIC2_SDA__UART2_TX 4
#define IIC2_SDA__IIS1_MCLK 5
#define IIC2_SDA__IIS2_MCLK 6
#define IIC2_SDA__KEY_COL3 7
#define UART2_TX__UART2_TX 0
#define UART2_TX__PWM_11 1
#define UART2_TX__PWR_UART1_TX 2
#define UART2_TX__PWR_GPIO_14 3
#define UART2_TX__KEY_ROW3 4
#define UART2_TX__UART4_TX 5
#define UART2_TX__IIS2_BCLK 6
#define UART2_TX__WG2_D0 7
#define UART2_RTS__UART2_RTS 0
#define UART2_RTS__PWM_8 1
#define UART2_RTS__PWR_GPIO_15 3
#define UART2_RTS__KEY_ROW0 4
#define UART2_RTS__UART4_RTS 5
#define UART2_RTS__IIS2_DO 6
#define UART2_RTS__WG1_D0 7
#define UART2_RX__UART2_RX 0
#define UART2_RX__PWM_10 1
#define UART2_RX__PWR_UART1_RX 2
#define UART2_RX__PWR_GPIO_16 3
#define UART2_RX__KEY_COL3 4
#define UART2_RX__UART4_RX 5
#define UART2_RX__IIS2_DI 6
#define UART2_RX__WG2_D1 7
#define UART2_CTS__UART2_CTS 0
#define UART2_CTS__PWM_9 1
#define UART2_CTS__PWR_GPIO_17 3
#define UART2_CTS__KEY_ROW1 4
#define UART2_CTS__UART4_CTS 5
#define UART2_CTS__IIS2_LRCK 6
#define UART2_CTS__WG1_D1 7
#define SD1_D3__PWR_SD1_D3_VO32 0
#define SD1_D3__SPI2_CS_X 1
#define SD1_D3__IIC1_SCL 2
#define SD1_D3__PWR_GPIO_18 3
#define SD1_D3__CAM_MCLK0 4
#define SD1_D3__UART3_CTS 5
#define SD1_D3__PWR_SPINOR1_CS_X 6
#define SD1_D3__PWM_4 7
#define SD1_D2__PWR_SD1_D2_VO33 0
#define SD1_D2__IIC1_SCL 1
#define SD1_D2__UART2_TX 2
#define SD1_D2__PWR_GPIO_19 3
#define SD1_D2__CAM_MCLK0 4
#define SD1_D2__UART3_TX 5
#define SD1_D2__PWR_SPINOR1_HOLD_X 6
#define SD1_D2__PWM_5 7
#define SD1_D1__PWR_SD1_D1_VO34 0
#define SD1_D1__IIC1_SDA 1
#define SD1_D1__UART2_RX 2
#define SD1_D1__PWR_GPIO_20 3
#define SD1_D1__CAM_MCLK1 4
#define SD1_D1__UART3_RX 5
#define SD1_D1__PWR_SPINOR1_WP_X 6
#define SD1_D1__PWM_6 7
#define SD1_D0__PWR_SD1_D0_VO35 0
#define SD1_D0__SPI2_SDI 1
#define SD1_D0__IIC1_SDA 2
#define SD1_D0__PWR_GPIO_21 3
#define SD1_D0__CAM_MCLK1 4
#define SD1_D0__UART3_RTS 5
#define SD1_D0__PWR_SPINOR1_MISO 6
#define SD1_D0__PWM_7 7
#define SD1_CMD__PWR_SD1_CMD_VO36 0
#define SD1_CMD__SPI2_SDO 1
#define SD1_CMD__IIC3_SCL 2
#define SD1_CMD__PWR_GPIO_22 3
#define SD1_CMD__CAM_VS0 4
#define SD1_CMD__EPHY_LNK_LED 5
#define SD1_CMD__PWR_SPINOR1_MOSI 6
#define SD1_CMD__PWM_8 7
#define SD1_CLK__PWR_SD1_CLK_VO37 0
#define SD1_CLK__SPI2_SCK 1
#define SD1_CLK__IIC3_SDA 2
#define SD1_CLK__PWR_GPIO_23 3
#define SD1_CLK__CAM_HS0 4
#define SD1_CLK__EPHY_SPD_LED 5
#define SD1_CLK__PWR_SPINOR1_SCK 6
#define SD1_CLK__PWM_9 7
#define RSTN__RSTN 0
#define PWM0_BUCK__PWM_0 0
#define PWM0_BUCK__XGPIOB_0 3
#define ADC3__CAM_MCLK0 1
#define ADC3__IIC4_SCL 2
#define ADC3__XGPIOB_1 3
#define ADC3__PWM_12 4
#define ADC3__EPHY_LNK_LED 5
#define ADC3__WG2_D0 6
#define ADC3__UART3_TX 7
#define ADC2__CAM_MCLK1 1
#define ADC2__IIC4_SDA 2
#define ADC2__XGPIOB_2 3
#define ADC2__PWM_13 4
#define ADC2__EPHY_SPD_LED 5
#define ADC2__WG2_D1 6
#define ADC2__UART3_RX 7
#define ADC1__XGPIOB_3 3
#define ADC1__KEY_COL2 4
#define USB_ID__USB_ID 0
#define USB_ID__XGPIOB_4 3
#define USB_VBUS_EN__USB_VBUS_EN 0
#define USB_VBUS_EN__XGPIOB_5 3
#define PKG_TYPE0__PKG_TYPE0 0
#define USB_VBUS_DET__USB_VBUS_DET 0
#define USB_VBUS_DET__XGPIOB_6 3
#define USB_VBUS_DET__CAM_MCLK0 4
#define USB_VBUS_DET__CAM_MCLK1 5
#define PKG_TYPE1__PKG_TYPE1 0
#define PKG_TYPE2__PKG_TYPE2 0
#define MUX_SPI1_MISO__UART3_RTS 1
#define MUX_SPI1_MISO__IIC1_SDA 2
#define MUX_SPI1_MISO__XGPIOB_8 3
#define MUX_SPI1_MISO__PWM_9 4
#define MUX_SPI1_MISO__KEY_COL1 5
#define MUX_SPI1_MISO__SPI1_SDI 6
#define MUX_SPI1_MISO__DBG_14 7
#define MUX_SPI1_MOSI__UART3_RX 1
#define MUX_SPI1_MOSI__IIC1_SCL 2
#define MUX_SPI1_MOSI__XGPIOB_7 3
#define MUX_SPI1_MOSI__PWM_8 4
#define MUX_SPI1_MOSI__KEY_COL0 5
#define MUX_SPI1_MOSI__SPI1_SDO 6
#define MUX_SPI1_MOSI__DBG_13 7
#define MUX_SPI1_CS__UART3_CTS 1
#define MUX_SPI1_CS__CAM_MCLK0 2
#define MUX_SPI1_CS__XGPIOB_10 3
#define MUX_SPI1_CS__PWM_11 4
#define MUX_SPI1_CS__KEY_ROW3 5
#define MUX_SPI1_CS__SPI1_CS_X 6
#define MUX_SPI1_CS__DBG_16 7
#define MUX_SPI1_SCK__UART3_TX 1
#define MUX_SPI1_SCK__CAM_MCLK1 2
#define MUX_SPI1_SCK__XGPIOB_9 3
#define MUX_SPI1_SCK__PWM_10 4
#define MUX_SPI1_SCK__KEY_ROW2 5
#define MUX_SPI1_SCK__SPI1_SCK 6
#define MUX_SPI1_SCK__DBG_15 7
#define PAD_ETH_TXM__UART3_RTS 1
#define PAD_ETH_TXM__IIC1_SDA 2
#define PAD_ETH_TXM__XGPIOB_24 3
#define PAD_ETH_TXM__PWM_12 4
#define PAD_ETH_TXM__CAM_MCLK1 5
#define PAD_ETH_TXM__SPI1_SDI 6
#define PAD_ETH_TXM__IIS2_BCLK 7
#define PAD_ETH_TXP__UART3_RX 1
#define PAD_ETH_TXP__IIC1_SCL 2
#define PAD_ETH_TXP__XGPIOB_25 3
#define PAD_ETH_TXP__PWM_13 4
#define PAD_ETH_TXP__CAM_MCLK0 5
#define PAD_ETH_TXP__SPI1_SDO 6
#define PAD_ETH_TXP__IIS2_LRCK 7
#define PAD_ETH_RXM__UART3_CTS 1
#define PAD_ETH_RXM__CAM_MCLK0 2
#define PAD_ETH_RXM__XGPIOB_26 3
#define PAD_ETH_RXM__PWM_14 4
#define PAD_ETH_RXM__CAM_VS0 5
#define PAD_ETH_RXM__SPI1_CS_X 6
#define PAD_ETH_RXM__IIS2_DI 7
#define PAD_ETH_RXP__UART3_TX 1
#define PAD_ETH_RXP__CAM_MCLK1 2
#define PAD_ETH_RXP__XGPIOB_27 3
#define PAD_ETH_RXP__PWM_15 4
#define PAD_ETH_RXP__CAM_HS0 5
#define PAD_ETH_RXP__SPI1_SCK 6
#define PAD_ETH_RXP__IIS2_DO 7
#define VIVO_D10__PWM_1 0
#define VIVO_D10__VI1_D_10 1
#define VIVO_D10__VO_D_23 2
#define VIVO_D10__XGPIOB_11 3
#define VIVO_D10__RMII0_IRQ 4
#define VIVO_D10__CAM_MCLK0 5
#define VIVO_D10__IIC1_SDA 6
#define VIVO_D10__UART2_TX 7
#define VIVO_D9__PWM_2 0
#define VIVO_D9__VI1_D_9 1
#define VIVO_D9__VO_D_22 2
#define VIVO_D9__XGPIOB_12 3
#define VIVO_D9__CAM_MCLK1 5
#define VIVO_D9__IIC1_SCL 6
#define VIVO_D9__UART2_RX 7
#define VIVO_D8__PWM_3 0
#define VIVO_D8__VI1_D_8 1
#define VIVO_D8__VO_D_21 2
#define VIVO_D8__XGPIOB_13 3
#define VIVO_D8__RMII0_MDIO 4
#define VIVO_D8__SPI3_SDO 5
#define VIVO_D8__IIC2_SCL 6
#define VIVO_D8__CAM_VS0 7
#define VIVO_D7__VI2_D_7 0
#define VIVO_D7__VI1_D_7 1
#define VIVO_D7__VO_D_20 2
#define VIVO_D7__XGPIOB_14 3
#define VIVO_D7__RMII0_RXD1 4
#define VIVO_D7__SPI3_SDI 5
#define VIVO_D7__IIC2_SDA 6
#define VIVO_D7__CAM_HS0 7
#define VIVO_D6__VI2_D_6 0
#define VIVO_D6__VI1_D_6 1
#define VIVO_D6__VO_D_19 2
#define VIVO_D6__XGPIOB_15 3
#define VIVO_D6__RMII0_REFCLKI 4
#define VIVO_D6__SPI3_SCK 5
#define VIVO_D6__UART2_TX 6
#define VIVO_D6__CAM_VS0 7
#define VIVO_D5__VI2_D_5 0
#define VIVO_D5__VI1_D_5 1
#define VIVO_D5__VO_D_18 2
#define VIVO_D5__XGPIOB_16 3
#define VIVO_D5__RMII0_RXD0 4
#define VIVO_D5__SPI3_CS_X 5
#define VIVO_D5__UART2_RX 6
#define VIVO_D5__CAM_HS0 7
#define VIVO_D4__VI2_D_4 0
#define VIVO_D4__VI1_D_4 1
#define VIVO_D4__VO_D_17 2
#define VIVO_D4__XGPIOB_17 3
#define VIVO_D4__RMII0_MDC 4
#define VIVO_D4__IIC1_SDA 5
#define VIVO_D4__UART2_CTS 6
#define VIVO_D4__CAM_VS0 7
#define VIVO_D3__VI2_D_3 0
#define VIVO_D3__VI1_D_3 1
#define VIVO_D3__VO_D_16 2
#define VIVO_D3__XGPIOB_18 3
#define VIVO_D3__RMII0_TXD0 4
#define VIVO_D3__IIC1_SCL 5
#define VIVO_D3__UART2_RTS 6
#define VIVO_D3__CAM_HS0 7
#define VIVO_D2__VI2_D_2 0
#define VIVO_D2__VI1_D_2 1
#define VIVO_D2__VO_D_15 2
#define VIVO_D2__XGPIOB_19 3
#define VIVO_D2__RMII0_TXD1 4
#define VIVO_D2__CAM_MCLK1 5
#define VIVO_D2__PWM_2 6
#define VIVO_D2__UART2_TX 7
#define VIVO_D1__VI2_D_1 0
#define VIVO_D1__VI1_D_1 1
#define VIVO_D1__VO_D_14 2
#define VIVO_D1__XGPIOB_20 3
#define VIVO_D1__RMII0_RXDV 4
#define VIVO_D1__IIC3_SDA 5
#define VIVO_D1__PWM_3 6
#define VIVO_D1__IIC4_SCL 7
#define VIVO_D0__VI2_D_0 0
#define VIVO_D0__VI1_D_0 1
#define VIVO_D0__VO_D_13 2
#define VIVO_D0__XGPIOB_21 3
#define VIVO_D0__RMII0_TXCLK 4
#define VIVO_D0__IIC3_SCL 5
#define VIVO_D0__WG1_D0 6
#define VIVO_D0__IIC4_SDA 7
#define VIVO_CLK__VI2_CLK 0
#define VIVO_CLK__VI1_CLK 1
#define VIVO_CLK__VO_CLK1 2
#define VIVO_CLK__XGPIOB_22 3
#define VIVO_CLK__RMII0_TXEN 4
#define VIVO_CLK__CAM_MCLK0 5
#define VIVO_CLK__WG1_D1 6
#define VIVO_CLK__UART2_RX 7
#define PAD_MIPIRX5N__VI1_D_11 1
#define PAD_MIPIRX5N__VO_D_12 2
#define PAD_MIPIRX5N__XGPIOC_0 3
#define PAD_MIPIRX5N__CAM_MCLK0 5
#define PAD_MIPIRX5N__WG0_D0 6
#define PAD_MIPIRX5N__DBG_0 7
#define PAD_MIPIRX5P__VI1_D_12 1
#define PAD_MIPIRX5P__VO_D_11 2
#define PAD_MIPIRX5P__XGPIOC_1 3
#define PAD_MIPIRX5P__IIS1_MCLK 4
#define PAD_MIPIRX5P__CAM_MCLK1 5
#define PAD_MIPIRX5P__WG0_D1 6
#define PAD_MIPIRX5P__DBG_1 7
#define PAD_MIPIRX4N__VI0_CLK 1
#define PAD_MIPIRX4N__VI1_D_13 2
#define PAD_MIPIRX4N__XGPIOC_2 3
#define PAD_MIPIRX4N__IIC1_SDA 4
#define PAD_MIPIRX4N__CAM_MCLK0 5
#define PAD_MIPIRX4N__KEY_ROW0 6
#define PAD_MIPIRX4N__MUX_SPI1_SCK 7
#define PAD_MIPIRX4P__VI0_D_0 1
#define PAD_MIPIRX4P__VI1_D_14 2
#define PAD_MIPIRX4P__XGPIOC_3 3
#define PAD_MIPIRX4P__IIC1_SCL 4
#define PAD_MIPIRX4P__CAM_MCLK1 5
#define PAD_MIPIRX4P__KEY_ROW1 6
#define PAD_MIPIRX4P__MUX_SPI1_CS 7
#define PAD_MIPIRX3N__VI0_D_1 1
#define PAD_MIPIRX3N__VI1_D_15 2
#define PAD_MIPIRX3N__XGPIOC_4 3
#define PAD_MIPIRX3N__CAM_MCLK0 4
#define PAD_MIPIRX3N__MUX_SPI1_MISO 7
#define PAD_MIPIRX3P__VI0_D_2 1
#define PAD_MIPIRX3P__VI1_D_16 2
#define PAD_MIPIRX3P__XGPIOC_5 3
#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7
#define PAD_MIPIRX2N__VI0_D_3 1
#define PAD_MIPIRX2N__VO_D_10 2
#define PAD_MIPIRX2N__XGPIOC_6 3
#define PAD_MIPIRX2N__VI1_D_17 4
#define PAD_MIPIRX2N__IIC4_SCL 5
#define PAD_MIPIRX2N__DBG_6 7
#define PAD_MIPIRX2P__VI0_D_4 1
#define PAD_MIPIRX2P__VO_D_9 2
#define PAD_MIPIRX2P__XGPIOC_7 3
#define PAD_MIPIRX2P__VI1_D_18 4
#define PAD_MIPIRX2P__IIC4_SDA 5
#define PAD_MIPIRX2P__DBG_7 7
#define PAD_MIPIRX1N__VI0_D_5 1
#define PAD_MIPIRX1N__VO_D_8 2
#define PAD_MIPIRX1N__XGPIOC_8 3
#define PAD_MIPIRX1N__KEY_ROW3 6
#define PAD_MIPIRX1N__DBG_8 7
#define PAD_MIPIRX1P__VI0_D_6 1
#define PAD_MIPIRX1P__VO_D_7 2
#define PAD_MIPIRX1P__XGPIOC_9 3
#define PAD_MIPIRX1P__IIC1_SDA 4
#define PAD_MIPIRX1P__KEY_ROW2 6
#define PAD_MIPIRX1P__DBG_9 7
#define PAD_MIPIRX0N__VI0_D_7 1
#define PAD_MIPIRX0N__VO_D_6 2
#define PAD_MIPIRX0N__XGPIOC_10 3
#define PAD_MIPIRX0N__IIC1_SCL 4
#define PAD_MIPIRX0N__CAM_MCLK1 5
#define PAD_MIPIRX0N__DBG_10 7
#define PAD_MIPIRX0P__VI0_D_8 1
#define PAD_MIPIRX0P__VO_D_5 2
#define PAD_MIPIRX0P__XGPIOC_11 3
#define PAD_MIPIRX0P__CAM_MCLK0 4
#define PAD_MIPIRX0P__DBG_11 7
#define PAD_MIPI_TXM4__SD1_CLK 1
#define PAD_MIPI_TXM4__VO_D_24 2
#define PAD_MIPI_TXM4__XGPIOC_18 3
#define PAD_MIPI_TXM4__CAM_MCLK1 4
#define PAD_MIPI_TXM4__PWM_12 5
#define PAD_MIPI_TXM4__IIC1_SDA 6
#define PAD_MIPI_TXM4__DBG_18 7
#define PAD_MIPI_TXP4__SD1_CMD 1
#define PAD_MIPI_TXP4__VO_D_25 2
#define PAD_MIPI_TXP4__XGPIOC_19 3
#define PAD_MIPI_TXP4__CAM_MCLK0 4
#define PAD_MIPI_TXP4__PWM_13 5
#define PAD_MIPI_TXP4__IIC1_SCL 6
#define PAD_MIPI_TXP4__DBG_19 7
#define PAD_MIPI_TXM3__SD1_D0 1
#define PAD_MIPI_TXM3__VO_D_26 2
#define PAD_MIPI_TXM3__XGPIOC_20 3
#define PAD_MIPI_TXM3__IIC2_SDA 4
#define PAD_MIPI_TXM3__PWM_14 5
#define PAD_MIPI_TXM3__IIC1_SDA 6
#define PAD_MIPI_TXM3__CAM_VS0 7
#define PAD_MIPI_TXP3__SD1_D1 1
#define PAD_MIPI_TXP3__VO_D_27 2
#define PAD_MIPI_TXP3__XGPIOC_21 3
#define PAD_MIPI_TXP3__IIC2_SCL 4
#define PAD_MIPI_TXP3__PWM_15 5
#define PAD_MIPI_TXP3__IIC1_SCL 6
#define PAD_MIPI_TXP3__CAM_HS0 7
#define PAD_MIPI_TXM2__VI0_D_13 1
#define PAD_MIPI_TXM2__VO_D_0 2
#define PAD_MIPI_TXM2__XGPIOC_16 3
#define PAD_MIPI_TXM2__IIC1_SDA 4
#define PAD_MIPI_TXM2__PWM_8 5
#define PAD_MIPI_TXM2__SPI0_SCK 6
#define PAD_MIPI_TXM2__SD1_D2 7
#define PAD_MIPI_TXP2__VI0_D_14 1
#define PAD_MIPI_TXP2__VO_CLK0 2
#define PAD_MIPI_TXP2__XGPIOC_17 3
#define PAD_MIPI_TXP2__IIC1_SCL 4
#define PAD_MIPI_TXP2__PWM_9 5
#define PAD_MIPI_TXP2__SPI0_CS_X 6
#define PAD_MIPI_TXP2__SD1_D3 7
#define PAD_MIPI_TXM1__VI0_D_11 1
#define PAD_MIPI_TXM1__VO_D_2 2
#define PAD_MIPI_TXM1__XGPIOC_14 3
#define PAD_MIPI_TXM1__IIC2_SDA 4
#define PAD_MIPI_TXM1__PWM_10 5
#define PAD_MIPI_TXM1__SPI0_SDO 6
#define PAD_MIPI_TXM1__DBG_14 7
#define PAD_MIPI_TXP1__VI0_D_12 1
#define PAD_MIPI_TXP1__VO_D_1 2
#define PAD_MIPI_TXP1__XGPIOC_15 3
#define PAD_MIPI_TXP1__IIC2_SCL 4
#define PAD_MIPI_TXP1__PWM_11 5
#define PAD_MIPI_TXP1__SPI0_SDI 6
#define PAD_MIPI_TXP1__DBG_15 7
#define PAD_MIPI_TXM0__VI0_D_9 1
#define PAD_MIPI_TXM0__VO_D_4 2
#define PAD_MIPI_TXM0__XGPIOC_12 3
#define PAD_MIPI_TXM0__CAM_MCLK1 4
#define PAD_MIPI_TXM0__PWM_14 5
#define PAD_MIPI_TXM0__CAM_VS0 6
#define PAD_MIPI_TXM0__DBG_12 7
#define PAD_MIPI_TXP0__VI0_D_10 1
#define PAD_MIPI_TXP0__VO_D_3 2
#define PAD_MIPI_TXP0__XGPIOC_13 3
#define PAD_MIPI_TXP0__CAM_MCLK0 4
#define PAD_MIPI_TXP0__PWM_15 5
#define PAD_MIPI_TXP0__CAM_HS0 6
#define PAD_MIPI_TXP0__DBG_13 7
#define PAD_AUD_AINL_MIC__XGPIOC_23 3
#define PAD_AUD_AINL_MIC__IIS1_BCLK 4
#define PAD_AUD_AINL_MIC__IIS2_BCLK 5
#define PAD_AUD_AINR_MIC__XGPIOC_22 3
#define PAD_AUD_AINR_MIC__IIS1_DO 4
#define PAD_AUD_AINR_MIC__IIS2_DI 5
#define PAD_AUD_AINR_MIC__IIS1_DI 6
#define PAD_AUD_AOUTL__XGPIOC_25 3
#define PAD_AUD_AOUTL__IIS1_LRCK 4
#define PAD_AUD_AOUTL__IIS2_LRCK 5
#define PAD_AUD_AOUTR__XGPIOC_24 3
#define PAD_AUD_AOUTR__IIS1_DI 4
#define PAD_AUD_AOUTR__IIS2_DO 5
#define PAD_AUD_AOUTR__IIS1_DO 6
#define GPIO_RTX__XGPIOB_23 3
#define GPIO_RTX__PWM_1 4
#define GPIO_RTX__CAM_MCLK0 5
#define GPIO_ZQ__PWR_GPIO_24 3
#define GPIO_ZQ__PWM_2 4

46
freertos/cvitek/install/include/hal/config/cv181x_pinmux.h Normal file
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@ -0,0 +1,46 @@
#ifndef _CV181X_PINMUX_H_
#define _CV181X_PINMUX_H_
#define PINMUX_UART0 0
#define PINMUX_UART1 1
#define PINMUX_UART2 2
#define PINMUX_UART3 3
#define PINMUX_UART3_2 4
#define PINMUX_I2C0 5
#define PINMUX_I2C1 6
#define PINMUX_I2C2 7
#define PINMUX_I2C3 8
#define PINMUX_I2C4 9
#define PINMUX_I2C4_2 10
#define PINMUX_SPI0 11
#define PINMUX_SPI1 12
#define PINMUX_SPI2 13
#define PINMUX_SPI2_2 14
#define PINMUX_SPI3 15
#define PINMUX_SPI3_2 16
#define PINMUX_I2S0 17
#define PINMUX_I2S1 18
#define PINMUX_I2S2 19
#define PINMUX_I2S3 20
#define PINMUX_USBID 21
#define PINMUX_SDIO0 22
#define PINMUX_SDIO1 23
#define PINMUX_ND 24
#define PINMUX_EMMC 25
#define PINMUX_SPI_NOR 26
#define PINMUX_SPI_NAND 27
#define PINMUX_CAM0 28
#define PINMUX_CAM1 29
#define PINMUX_PCM0 30
#define PINMUX_PCM1 31
#define PINMUX_CSI0 32
#define PINMUX_CSI1 33
#define PINMUX_CSI2 34
#define PINMUX_DSI 35
#define PINMUX_VI0 36
#define PINMUX_VO 37
#define PINMUX_PWM1 38
#define PINMUX_UART4 39
#define PINMUX_SPI_NOR1 40
#endif // end of _CV181X_PINMUX_H_

475
freertos/cvitek/install/include/hal/config/cv181x_reg_fmux_gpio.h Normal file
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// $Module: fmux_gpio $
// $RegisterBank Version: V 1.0.00 $
// $Author: ghost $
// $Date: Fri, 30 Jul 2021 08:58:54 PM $
//
//GEN REG ADDR/OFFSET/MASK
#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK0 0x0
#define FMUX_GPIO_REG_IOCTRL_CAM_PD0 0x4
#define FMUX_GPIO_REG_IOCTRL_CAM_RST0 0x8
#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK1 0xc
#define FMUX_GPIO_REG_IOCTRL_CAM_PD1 0x10
#define FMUX_GPIO_REG_IOCTRL_IIC3_SCL 0x14
#define FMUX_GPIO_REG_IOCTRL_IIC3_SDA 0x18
#define FMUX_GPIO_REG_IOCTRL_SD0_CLK 0x1c
#define FMUX_GPIO_REG_IOCTRL_SD0_CMD 0x20
#define FMUX_GPIO_REG_IOCTRL_SD0_D0 0x24
#define FMUX_GPIO_REG_IOCTRL_SD0_D1 0x28
#define FMUX_GPIO_REG_IOCTRL_SD0_D2 0x2c
#define FMUX_GPIO_REG_IOCTRL_SD0_D3 0x30
#define FMUX_GPIO_REG_IOCTRL_SD0_CD 0x34
#define FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN 0x38
#define FMUX_GPIO_REG_IOCTRL_SPK_EN 0x3c
#define FMUX_GPIO_REG_IOCTRL_UART0_TX 0x40
#define FMUX_GPIO_REG_IOCTRL_UART0_RX 0x44
#define FMUX_GPIO_REG_IOCTRL_EMMC_RSTN 0x48
#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT2 0x4c
#define FMUX_GPIO_REG_IOCTRL_EMMC_CLK 0x50
#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT0 0x54
#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT3 0x58
#define FMUX_GPIO_REG_IOCTRL_EMMC_CMD 0x5c
#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT1 0x60
#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS 0x64
#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK 0x68
#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TRST 0x6c
#define FMUX_GPIO_REG_IOCTRL_IIC0_SCL 0x70
#define FMUX_GPIO_REG_IOCTRL_IIC0_SDA 0x74
#define FMUX_GPIO_REG_IOCTRL_AUX0 0x78
#define FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET 0x7c
#define FMUX_GPIO_REG_IOCTRL_PWR_RSTN 0x80
#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ1 0x84
#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ2 0x88
#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ3 0x8c
#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0 0x90
#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP1 0x94
#define FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1 0x98
#define FMUX_GPIO_REG_IOCTRL_PWR_ON 0x9c
#define FMUX_GPIO_REG_IOCTRL_XTAL_XIN 0xa0
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO0 0xa4
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO1 0xa8
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO2 0xac
#define FMUX_GPIO_REG_IOCTRL_CLK32K 0xb0
#define FMUX_GPIO_REG_IOCTRL_CLK25M 0xb4
#define FMUX_GPIO_REG_IOCTRL_IIC2_SCL 0xb8
#define FMUX_GPIO_REG_IOCTRL_IIC2_SDA 0xbc
#define FMUX_GPIO_REG_IOCTRL_UART2_TX 0xc0
#define FMUX_GPIO_REG_IOCTRL_UART2_RTS 0xc4
#define FMUX_GPIO_REG_IOCTRL_UART2_RX 0xc8
#define FMUX_GPIO_REG_IOCTRL_UART2_CTS 0xcc
#define FMUX_GPIO_REG_IOCTRL_SD1_D3 0xd0
#define FMUX_GPIO_REG_IOCTRL_SD1_D2 0xd4
#define FMUX_GPIO_REG_IOCTRL_SD1_D1 0xd8
#define FMUX_GPIO_REG_IOCTRL_SD1_D0 0xdc
#define FMUX_GPIO_REG_IOCTRL_SD1_CMD 0xe0
#define FMUX_GPIO_REG_IOCTRL_SD1_CLK 0xe4
#define FMUX_GPIO_REG_IOCTRL_RSTN 0xe8
#define FMUX_GPIO_REG_IOCTRL_PWM0_BUCK 0xec
#define FMUX_GPIO_REG_IOCTRL_ADC3 0xf0
#define FMUX_GPIO_REG_IOCTRL_ADC2 0xf4
#define FMUX_GPIO_REG_IOCTRL_ADC1 0xf8
#define FMUX_GPIO_REG_IOCTRL_USB_ID 0xfc
#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_EN 0x100
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE0 0x104
#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET 0x108
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE1 0x10c
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE2 0x110
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO 0x114
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI 0x118
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS 0x11c
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK 0x120
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM 0x124
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP 0x128
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM 0x12c
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP 0x130
#define FMUX_GPIO_REG_IOCTRL_VIVO_D10 0x134
#define FMUX_GPIO_REG_IOCTRL_VIVO_D9 0x138
#define FMUX_GPIO_REG_IOCTRL_VIVO_D8 0x13c
#define FMUX_GPIO_REG_IOCTRL_VIVO_D7 0x140
#define FMUX_GPIO_REG_IOCTRL_VIVO_D6 0x144
#define FMUX_GPIO_REG_IOCTRL_VIVO_D5 0x148
#define FMUX_GPIO_REG_IOCTRL_VIVO_D4 0x14c
#define FMUX_GPIO_REG_IOCTRL_VIVO_D3 0x150
#define FMUX_GPIO_REG_IOCTRL_VIVO_D2 0x154
#define FMUX_GPIO_REG_IOCTRL_VIVO_D1 0x158
#define FMUX_GPIO_REG_IOCTRL_VIVO_D0 0x15c
#define FMUX_GPIO_REG_IOCTRL_VIVO_CLK 0x160
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5N 0x164
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5P 0x168
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N 0x16c
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P 0x170
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N 0x174
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P 0x178
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N 0x17c
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P 0x180
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N 0x184
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P 0x188
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N 0x18c
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P 0x190
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM4 0x194
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP4 0x198
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM3 0x19c
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP3 0x1a0
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2 0x1a4
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2 0x1a8
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1 0x1ac
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1 0x1b0
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0 0x1b4
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0 0x1b8
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC 0x1bc
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC 0x1c0
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL 0x1c4
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR 0x1c8
#define FMUX_GPIO_REG_IOCTRL_GPIO_RTX 0x1cc
#define FMUX_GPIO_REG_IOCTRL_GPIO_ZQ 0x1d0
#define FMUX_GPIO_FUNCSEL_CAM_MCLK0 0x0
#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CAM_PD0 0x4
#define FMUX_GPIO_FUNCSEL_CAM_PD0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CAM_PD0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CAM_RST0 0x8
#define FMUX_GPIO_FUNCSEL_CAM_RST0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CAM_RST0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CAM_MCLK1 0xc
#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CAM_PD1 0x10
#define FMUX_GPIO_FUNCSEL_CAM_PD1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CAM_PD1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC3_SCL 0x14
#define FMUX_GPIO_FUNCSEL_IIC3_SCL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC3_SCL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC3_SDA 0x18
#define FMUX_GPIO_FUNCSEL_IIC3_SDA_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC3_SDA_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_CLK 0x1c
#define FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_CMD 0x20
#define FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CMD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D0 0x24
#define FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D1 0x28
#define FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D2 0x2c
#define FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D3 0x30
#define FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_CD 0x34
#define FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN 0x38
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPK_EN 0x3c
#define FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPK_EN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART0_TX 0x40
#define FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART0_TX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART0_RX 0x44
#define FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART0_RX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_RSTN 0x48
#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_DAT2 0x4c
#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_CLK 0x50
#define FMUX_GPIO_FUNCSEL_EMMC_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_DAT0 0x54
#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_DAT3 0x58
#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_CMD 0x5c
#define FMUX_GPIO_FUNCSEL_EMMC_CMD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_CMD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_DAT1 0x60
#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS 0x64
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK 0x68
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST 0x6c
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_OFFSET 0
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC0_SCL 0x70
#define FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC0_SDA 0x74
#define FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK 0x7
#define FMUX_GPIO_FUNCSEL_AUX0 0x78
#define FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_AUX0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET 0x7c
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_RSTN 0x80
#define FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1 0x84
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2 0x88
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_SEQ3 0x8c
#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0 0x90
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1 0x94
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1 0x98
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_ON 0x9c
#define FMUX_GPIO_FUNCSEL_PWR_ON_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_ON_MASK 0x7
#define FMUX_GPIO_FUNCSEL_XTAL_XIN 0xa0
#define FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0 0xa4
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1 0xa8
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2 0xac
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CLK32K 0xb0
#define FMUX_GPIO_FUNCSEL_CLK32K_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CLK32K_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CLK25M 0xb4
#define FMUX_GPIO_FUNCSEL_CLK25M_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CLK25M_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC2_SCL 0xb8
#define FMUX_GPIO_FUNCSEL_IIC2_SCL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC2_SCL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC2_SDA 0xbc
#define FMUX_GPIO_FUNCSEL_IIC2_SDA_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC2_SDA_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART2_TX 0xc0
#define FMUX_GPIO_FUNCSEL_UART2_TX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART2_TX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART2_RTS 0xc4
#define FMUX_GPIO_FUNCSEL_UART2_RTS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART2_RTS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART2_RX 0xc8
#define FMUX_GPIO_FUNCSEL_UART2_RX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART2_RX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART2_CTS 0xcc
#define FMUX_GPIO_FUNCSEL_UART2_CTS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART2_CTS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D3 0xd0
#define FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D2 0xd4
#define FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D1 0xd8
#define FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D0 0xdc
#define FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_CMD 0xe0
#define FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_CMD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_CLK 0xe4
#define FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_RSTN 0xe8
#define FMUX_GPIO_FUNCSEL_RSTN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_RSTN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK 0xec
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_ADC3 0xf0
#define FMUX_GPIO_FUNCSEL_ADC3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_ADC3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_ADC2 0xf4
#define FMUX_GPIO_FUNCSEL_ADC2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_ADC2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_ADC1 0xf8
#define FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_ADC1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_USB_ID 0xfc
#define FMUX_GPIO_FUNCSEL_USB_ID_OFFSET 0
#define FMUX_GPIO_FUNCSEL_USB_ID_MASK 0x7
#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN 0x100
#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0 0x104
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET 0x108
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1 0x10c
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2 0x110
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO 0x114
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI 0x118
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS 0x11c
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK 0x120
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM 0x124
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP 0x128
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM 0x12c
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP 0x130
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D10 0x134
#define FMUX_GPIO_FUNCSEL_VIVO_D10_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D10_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D9 0x138
#define FMUX_GPIO_FUNCSEL_VIVO_D9_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D9_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D8 0x13c
#define FMUX_GPIO_FUNCSEL_VIVO_D8_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D8_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D7 0x140
#define FMUX_GPIO_FUNCSEL_VIVO_D7_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D7_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D6 0x144
#define FMUX_GPIO_FUNCSEL_VIVO_D6_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D6_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D5 0x148
#define FMUX_GPIO_FUNCSEL_VIVO_D5_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D5_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D4 0x14c
#define FMUX_GPIO_FUNCSEL_VIVO_D4_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D4_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D3 0x150
#define FMUX_GPIO_FUNCSEL_VIVO_D3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D2 0x154
#define FMUX_GPIO_FUNCSEL_VIVO_D2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D1 0x158
#define FMUX_GPIO_FUNCSEL_VIVO_D1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D0 0x15c
#define FMUX_GPIO_FUNCSEL_VIVO_D0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_CLK 0x160
#define FMUX_GPIO_FUNCSEL_VIVO_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N 0x164
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P 0x168
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N 0x16c
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P 0x170
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N 0x174
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P 0x178
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N 0x17c
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P 0x180
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N 0x184
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P 0x188
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N 0x18c
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P 0x190
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4 0x194
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4 0x198
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3 0x19c
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3 0x1a0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2 0x1a4
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2 0x1a8
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1 0x1ac
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1 0x1b0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0 0x1b4
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0 0x1b8
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC 0x1bc
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC 0x1c0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL 0x1c4
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR 0x1c8
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK 0x7
#define FMUX_GPIO_FUNCSEL_GPIO_RTX 0x1cc
#define FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ 0x1d0
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK 0x7

6
freertos/cvitek/install/include/hal/config/intr_conf.h
View File

@ -1,5 +1,5 @@
#ifndef _CV180X_INTERRUPT_CONFIG_H_ #ifndef _CV181X_INTERRUPT_CONFIG_H_
#define _CV180X_INTERRUPT_CONFIG_H_ #define _CV181X_INTERRUPT_CONFIG_H_
/* irq */ /* irq */
#define IRQ_LEVEL 0 #define IRQ_LEVEL 0
@ -137,4 +137,4 @@ void pinmux_config(int io_type);
*/ */
#define NUM_IRQ (62) #define NUM_IRQ (62)
#endif //end of_CV180X_INTERRUPT_CONFIG_H_ #endif //end of_CV181X_INTERRUPT_CONFIG_H_

18
freertos/cvitek/install/include/hal/config/pinctrl.h
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@ -5,11 +5,12 @@
* Description: * Description:
*/ */
#ifndef __PINCTRL_CV180X_H__ #ifndef __PINCTRL_CV181X_H__
#define __PINCTRL_CV180X_H__ #define __PINCTRL_CV181X_H__
#include "cv180x_pinlist_swconfig.h" //#include "../core.h"
#include "cv180x_reg_fmux_gpio.h" #include "cv181x_pinlist_swconfig.h"
#include "cv181x_reg_fmux_gpio.h"
#define PAD_MIPI_TXM4__MIPI_TXM4 0 #define PAD_MIPI_TXM4__MIPI_TXM4 0
#define PAD_MIPI_TXP4__MIPI_TXP4 0 #define PAD_MIPI_TXP4__MIPI_TXP4 0
@ -27,8 +28,9 @@
#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET #define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET
#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME #define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME
#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \ #define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \ mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \
FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK << FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET, \ PINMUX_MASK(PIN_NAME) << PINMUX_OFFSET(PIN_NAME), \
PIN_NAME##__##FUNC_NAME) PINMUX_VALUE(PIN_NAME, FUNC_NAME))
#endif /* __PINCTRL_CV181X_H__ */
#endif /* __PINCTRL_CV180X_H__ */

6
freertos/cvitek/install/include/hal/config/top_reg.h
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@ -1,5 +1,5 @@
#ifndef __CV180X_REG_H #ifndef __CV181X_REG_H
#define __CV180X_REG_H #define __CV181X_REG_H
#define SEC_BASE 0x02000000 #define SEC_BASE 0x02000000
#define TOP_BASE 0x03000000 #define TOP_BASE 0x03000000
@ -74,4 +74,4 @@
/* watchdog */ /* watchdog */
#endif /* __CV180X_REG_H */ #endif /* __CV181X_REG_H */

2
freertos/cvitek/install/include/hal/pinmux/hal_pinmux.h
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@ -1,6 +1,6 @@
#ifndef __HAL_PINMUX_CONFIG_H__ #ifndef __HAL_PINMUX_CONFIG_H__
#define __HAL_PINMUX_CONFIG_H__ #define __HAL_PINMUX_CONFIG_H__
#include "cv180x_pinmux.h" #include "cv181x_pinmux.h"
void hal_pinmux_config(int io_type); void hal_pinmux_config(int io_type);
#endif //end of __HAL_PINMUX_CONFIG_H__ #endif //end of __HAL_PINMUX_CONFIG_H__

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freertos/cvitek/install/lib/libarch.a
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freertos/cvitek/install/lib/libaudio.a
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freertos/cvitek/install/lib/libcomm.a
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freertos/cvitek/install/lib/libcommon.a
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freertos/cvitek/install/lib/libdriver.a
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freertos/cvitek/install/lib/libhal.a
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freertos/cvitek/install/lib/libkernel.a
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freertos/cvitek/install/lib/librgn.a
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22
freertos/cvitek/task/audio/src/riscv64/audio_main.c
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@ -581,18 +581,20 @@ void prvAudioRunTask(void *pvParameters)
pVqeConfigSsp->s32RevMask = _pstVqeConfig->s32RevMask; pVqeConfigSsp->s32RevMask = _pstVqeConfig->s32RevMask;
pVqeConfigSsp->para_notch_freq = _pstVqeConfig->para_notch_freq; pVqeConfigSsp->para_notch_freq = _pstVqeConfig->para_notch_freq;
if (paudio_ssp_block != NULL)
if (paudio_ssp_block == NULL) {
paudio_ssp_block = CviAud_Algo_Init(pVqeConfigSsp->u32OpenMask, pVqeConfigSsp);
if (paudio_ssp_block == NULL) {
aud_error("[CVIAUDIO_RTOS_CMD_SSP_INIT_BLOCK]paudio_ssp_block failure\n");
rtos_cmdq.param_ptr = CVIAUDIO_RTOS_BLOCK_MODE_FAILURE_FLAG;
clean_dcache_range((uintptr_t)pstAudBlockMailBox, sizeof(ST_CVIAUDIO_MAILBOX_BLOCK));
xQueueSend(xQueueAudioCmdqu, &rtos_cmdq, 0U);
break;
} else
aud_info("CVIAUDIO_RTOS_CMD_SSP_INIT_BLOCK init success!!\n");
} else
aud_error("warning paudio_ssp_blcok not Null..\n"); aud_error("warning paudio_ssp_blcok not Null..\n");
paudio_ssp_block = CviAud_Algo_Init(pVqeConfigSsp->u32OpenMask, pVqeConfigSsp);
if (paudio_ssp_block == NULL) {
aud_error("[CVIAUDIO_RTOS_CMD_SSP_INIT_BLOCK]paudio_ssp_block failure\n");
rtos_cmdq.param_ptr = CVIAUDIO_RTOS_BLOCK_MODE_FAILURE_FLAG;
clean_dcache_range((uintptr_t)pstAudBlockMailBox, sizeof(ST_CVIAUDIO_MAILBOX_BLOCK));
xQueueSend(xQueueAudioCmdqu, &rtos_cmdq, 0U);
break;
} else
aud_info("CVIAUDIO_RTOS_CMD_SSP_INIT_BLOCK init success!!\n");
xQueueSend(xQueueAudioCmdqu, &rtos_cmdq, 0U); xQueueSend(xQueueAudioCmdqu, &rtos_cmdq, 0U);
} }
break; break;

2
freertos/cvitek/task/rgn/src/riscv64/rgn_main.c
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@ -62,6 +62,8 @@ void prvRGNRunTask(void *pvParameters)
rgn_printf("xPortGetFreeHeapSize(%d)\n", xPortGetFreeHeapSize()); rgn_printf("xPortGetFreeHeapSize(%d)\n", xPortGetFreeHeapSize());
canvas_cmpr_attr = (RGN_CANVAS_CMPR_ATTR_S *)rtos_cmdq.param_ptr; canvas_cmpr_attr = (RGN_CANVAS_CMPR_ATTR_S *)rtos_cmdq.param_ptr;
inv_dcache_range((uintptr_t)canvas_cmpr_attr, ALIGN(sizeof(RGN_CANVAS_CMPR_ATTR_S), 64));
inv_dcache_range((uintptr_t)canvas_cmpr_attr, ALIGN(canvas_cmpr_attr->u32BsSize, 64));
rgn_printf("phyAddr(%x) u32Width(%d) u32Height(%d) u32BgColor(%x) enPixelFormat(%d) u32ObjNum(%d)\n", rgn_printf("phyAddr(%x) u32Width(%d) u32Height(%d) u32BgColor(%x) enPixelFormat(%d) u32ObjNum(%d)\n",
rtos_cmdq.param_ptr, rtos_cmdq.param_ptr,
canvas_cmpr_attr->u32Width, canvas_cmpr_attr->u32Width,