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[uboot] porting cvitek asic chips:

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1. add cvitek folders to u-boot-2021.10
	2. add cv183x/cv182x part
	3. add cv181x/cv180x part

Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
This commit is contained in:
sam.xiang
2023-02-22 13:43:23 +08:00
parent f8fc109960
commit 3a4bcfca2f
244 changed files with 41355 additions and 1273 deletions
Download Patch File Download Diff File Expand all files Collapse all files

105
u-boot-2021.10/.gitignore vendored Normal file
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@ -0,0 +1,105 @@
#
# NOTE! Don't add files that are generated in specific
# subdirectories here. Add them in the ".gitignore" file
# in that subdirectory instead.
#
# Normal rules (sorted alphabetically)
#
.*
*.a
*.asn1.[ch]
*.bin
*.cfgout
*.dtb
*.dtbo
*.dtb.S
*.elf
*.exe
*.gcda
*.gcno
*.i
*.img
*.lex.c
*.lst
*.mod.c
*.o
*.o.*
*.order
*.patch
*.s
*.su
*.swp
*.tab.[ch]
# Build tree
/build-*
#
# Top-level generic files
#
fit-dtb.blob*
/MLO*
/SPL*
/System.map
/u-boot*
/boards.cfg
/*.log
#
# git files that we don't want to ignore even it they are dot-files
#
!.gitignore
!.mailmap
#
# Generated files
#
/spl/
/tpl/
/defconfig
#
# Generated include files
#
/include/config/
/include/generated/
# stgit generated dirs
patches-*
.stgit-edit.txt
# quilt's files
patches
series
# gdb files
.gdb_history
# cscope files
cscope.*
# tags files
/tags
/ctags
/etags
# gnu global files
GPATH
GRTAGS
GSYMS
GTAGS
*.orig
*~
\#*#
# Python cache
__pycache__
# cvitek auto-generated files
/include/cvitek/cvitek.h
/include/cvipart.h
/include/imgs.h
/include/cvi_board_memmap.h
tags
build

5
u-boot-2021.10/Makefile
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@ -427,6 +427,7 @@ KBUILD_CFLAGS := -Wall -Wstrict-prototypes \
-Wno-format-security \ -Wno-format-security \
-fno-builtin -ffreestanding $(CSTD_FLAG) -fno-builtin -ffreestanding $(CSTD_FLAG)
KBUILD_CFLAGS += -fshort-wchar -fno-strict-aliasing KBUILD_CFLAGS += -fshort-wchar -fno-strict-aliasing
KBUILD_CFLAGS += -Werror
KBUILD_AFLAGS := -D__ASSEMBLY__ KBUILD_AFLAGS := -D__ASSEMBLY__
KBUILD_LDFLAGS := KBUILD_LDFLAGS :=
@ -454,6 +455,8 @@ KBUILD_AFLAGS += $(call cc-option,-fno-PIE)
UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null) UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null)
UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION)
include cvitek.mk
export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
export CONFIG_SHELL HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE AS LD CC export CONFIG_SHELL HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE AS LD CC
@ -782,6 +785,7 @@ KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g)
UBOOTINCLUDE := \ UBOOTINCLUDE := \
-Iinclude \ -Iinclude \
$(if $(KBUILD_SRC), -I$(srctree)/include) \ $(if $(KBUILD_SRC), -I$(srctree)/include) \
$(if $(CONFIG_TARGET_CVITEK), -I$(srctree)/include/cvitek) \
$(if $(CONFIG_$(SPL_)SYS_THUMB_BUILD), \ $(if $(CONFIG_$(SPL_)SYS_THUMB_BUILD), \
$(if $(CONFIG_HAS_THUMB2), \ $(if $(CONFIG_HAS_THUMB2), \
$(if $(CONFIG_CPU_V7M), \ $(if $(CONFIG_CPU_V7M), \
@ -813,6 +817,7 @@ libs-y += fs/
libs-y += net/ libs-y += net/
libs-y += disk/ libs-y += disk/
libs-y += drivers/ libs-y += drivers/
libs-y += drivers/cvi_usb/
libs-y += drivers/dma/ libs-y += drivers/dma/
libs-y += drivers/gpio/ libs-y += drivers/gpio/
libs-y += drivers/net/ libs-y += drivers/net/

18
u-boot-2021.10/arch/Kconfig
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@ -83,22 +83,7 @@ config RISCV
select SUPPORT_OF_CONTROL select SUPPORT_OF_CONTROL
select OF_CONTROL select OF_CONTROL
select DM select DM
imply DM_SERIAL
imply DM_ETH
imply DM_MMC
imply DM_SPI
imply DM_SPI_FLASH
imply BLK
imply CLK
imply MTD
imply TIMER imply TIMER
imply CMD_DM
imply SPL_DM
imply SPL_OF_CONTROL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_SERIAL_SUPPORT
imply SPL_TIMER
config SANDBOX config SANDBOX
bool "Sandbox" bool "Sandbox"
@ -338,3 +323,6 @@ source "arch/sh/Kconfig"
source "arch/x86/Kconfig" source "arch/x86/Kconfig"
source "arch/xtensa/Kconfig" source "arch/xtensa/Kconfig"
source "arch/riscv/Kconfig" source "arch/riscv/Kconfig"
# board/cvitek/Kconfig are shared by ARM/RISCV
source "board/cvitek/Kconfig"

6
u-boot-2021.10/arch/arm/Kconfig
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@ -517,7 +517,10 @@ config ARM64_SUPPORT_AARCH32
choice choice
prompt "Target select" prompt "Target select"
default TARGET_HIKEY default TARGET_CVITEK_ARM
config TARGET_CVITEK_ARM
prompt "Cvitek target for ARM"
config ARCH_AT91 config ARCH_AT91
bool "Atmel AT91" bool "Atmel AT91"
@ -2039,7 +2042,6 @@ source "arch/arm/mach-zynqmp-r5/Kconfig"
source "arch/arm/cpu/armv7/Kconfig" source "arch/arm/cpu/armv7/Kconfig"
source "arch/arm/cpu/armv8/Kconfig" source "arch/arm/cpu/armv8/Kconfig"
source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-nexell/Kconfig" source "arch/arm/mach-nexell/Kconfig"

5
u-boot-2021.10/arch/arm/dts/Makefile
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@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_CVITEK) += $(CHIP)_$(CVIBOARD).dtb
dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb
dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb
@ -497,7 +498,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-inet9f-rev03.dtb \ sun4i-a10-inet9f-rev03.dtb \
sun4i-a10-itead-iteaduino-plus.dtb \ sun4i-a10-itead-iteaduino-plus.dtb \
sun4i-a10-jesurun-q5.dtb \ sun4i-a10-jesurun-q5.dtb \
sun4i-a10-marsboard.dtb \ sun4i-a10-cv181xboard.dtb \
sun4i-a10-mini-xplus.dtb \ sun4i-a10-mini-xplus.dtb \
sun4i-a10-mk802.dtb \ sun4i-a10-mk802.dtb \
sun4i-a10-mk802ii.dtb \ sun4i-a10-mk802ii.dtb \
@ -772,7 +773,7 @@ dtb-y += \
imx6q-icore-rqs.dtb \ imx6q-icore-rqs.dtb \
imx6q-kp.dtb \ imx6q-kp.dtb \
imx6q-logicpd.dtb \ imx6q-logicpd.dtb \
imx6q-marsboard.dtb \ imx6q-cv181xboard.dtb \
imx6q-mba6a.dtb \ imx6q-mba6a.dtb \
imx6q-mba6b.dtb \ imx6q-mba6b.dtb \
imx6q-mccmon6.dtb\ imx6q-mccmon6.dtb\

28
u-boot-2021.10/arch/arm/include/asm/arch-armv8/boot0.h Normal file
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@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* CVITEK u-boot header
*/
#ifndef __BOOT0_H__
#define __BOOT0_H__
/* BOOT0 header information */
b boot0_time_recode
.word 0x33334c42 /* b'BL33' */
.word 0xdeadbee1 /* CKSUM */
.word 0xdeadbee4 /* SIZE */
.quad CONFIG_SYS_TEXT_BASE /* RUNADDR */
.word 0xdeadbee6
b boot0_time_recode
/* BOOT0 header end */
boot0_time_recode:
mrs x0, cntpct_el0
ldr x1, =BOOT0_START_TIME
str w0, [x1]
b reset
.global BOOT0_START_TIME
BOOT0_START_TIME:
.word 0
#endif /* __BOOT0_H__ */

4
u-boot-2021.10/arch/arm/include/asm/mach-types.h
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@ -1627,7 +1627,7 @@
#define MACH_TYPE_MX35EVB 1643 #define MACH_TYPE_MX35EVB 1643
#define MACH_TYPE_AML_M8050 1644 #define MACH_TYPE_AML_M8050 1644
#define MACH_TYPE_MX35_3DS 1645 #define MACH_TYPE_MX35_3DS 1645
#define MACH_TYPE_MARS 1646 #define MACH_TYPE_CV181X 1646
#define MACH_TYPE_NEUROS_OSD2 1647 #define MACH_TYPE_NEUROS_OSD2 1647
#define MACH_TYPE_BADGER 1648 #define MACH_TYPE_BADGER 1648
#define MACH_TYPE_TRIZEPS4WL 1649 #define MACH_TYPE_TRIZEPS4WL 1649
@ -4840,7 +4840,7 @@
#define MACH_TYPE_MX6S_HAWTHORNE 4901 #define MACH_TYPE_MX6S_HAWTHORNE 4901
#define MACH_TYPE_SEAH 4902 #define MACH_TYPE_SEAH 4902
#define MACH_TYPE_AM335X_EC3 4903 #define MACH_TYPE_AM335X_EC3 4903
#define MACH_TYPE_EMBEST_MARS 4904 #define MACH_TYPE_EMBEST_CV181X 4904
#define MACH_TYPE_MX6DL_VIKITOUCH 4905 #define MACH_TYPE_MX6DL_VIKITOUCH 4905
#define MACH_TYPE_IX2_NG 4906 #define MACH_TYPE_IX2_NG 4906
#define MACH_TYPE_PEKQSD 4907 #define MACH_TYPE_PEKQSD 4907

1
u-boot-2021.10/arch/arm/include/asm/u-boot-arm.h
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@ -36,6 +36,7 @@ int arch_misc_init(void);
/* board/.../... */ /* board/.../... */
int board_init(void); int board_init(void);
void board_save_time_record(uintptr_t saveaddr);
/* calls to c from vectors.S */ /* calls to c from vectors.S */
struct pt_regs; struct pt_regs;

3
u-boot-2021.10/arch/arm/lib/bootm.c
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@ -125,6 +125,9 @@ static void announce_and_cleanup(int fake)
dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
cleanup_before_linux(); cleanup_before_linux();
// Save kernel start time
board_save_time_record(TIME_RECORDS_FIELD_KERNEL_START);
} }
static void setup_start_tag (struct bd_info *bd) static void setup_start_tag (struct bd_info *bd)

5
u-boot-2021.10/arch/riscv/Kconfig
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@ -6,7 +6,10 @@ config SYS_ARCH
choice choice
prompt "Target select" prompt "Target select"
optional default TARGET_CVITEK_RISCV
config TARGET_CVITEK_RISCV
prompt "Cvitek target for RISCV"
config TARGET_AX25_AE350 config TARGET_AX25_AE350
bool "Support ax25-ae350" bool "Support ax25-ae350"

2
u-boot-2021.10/arch/riscv/config.mk
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@ -21,10 +21,12 @@ endif
ifdef CONFIG_64BIT ifdef CONFIG_64BIT
KBUILD_LDFLAGS += -m $(64bit-emul) KBUILD_LDFLAGS += -m $(64bit-emul)
EFI_LDS := elf_riscv64_efi.lds EFI_LDS := elf_riscv64_efi.lds
PLATFORM_ELFFLAGS += -B riscv:rv64 -O elf64-littleriscv
endif endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
PLATFORM_CPPFLAGS += -ffixed-gp -fpic PLATFORM_CPPFLAGS += -ffixed-gp -fpic
PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \ PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \
-fdata-sections -fdata-sections

1
u-boot-2021.10/arch/riscv/cpu/generic/Makefile
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@ -4,3 +4,4 @@
obj-y += dram.o obj-y += dram.o
obj-y += cpu.o obj-y += cpu.o
obj-y += cache.o

66
u-boot-2021.10/arch/riscv/cpu/generic/cache.c Normal file
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@ -0,0 +1,66 @@
#include <linux/types.h>
#include <cpu_func.h>
#define L1_CACHE_BYTES 64
#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
/*
* dcache.ipa rs1 (invalidate)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01010 rs1 000 00000 0001011
*
* dcache.cpa rs1 (clean)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01001 rs1 000 00000 0001011
*
* dcache.cipa rs1 (clean then invalidate)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01011 rs1 000 00000 0001011
*
* sync.s
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000000 11001 00000 000 00000 0001011
*/
#define DCACHE_IPA_A0 ".long 0x02a5000b"
#define DCACHE_CPA_A0 ".long 0x0295000b"
#define DCACHE_CIPA_A0 ".long 0x02b5000b"
#define SYNC_S ".long 0x0190000b"
#define CACHE_OP_RANGE(OP, start, size) \
register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1); \
for (; i < ALIGN(start + size, L1_CACHE_BYTES); i += L1_CACHE_BYTES) \
__asm__ __volatile__(OP); \
__asm__ __volatile__(SYNC_S)
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
CACHE_OP_RANGE(DCACHE_IPA_A0, start, end - start);
}
void flush_dcache_range(unsigned long start, unsigned long end)
{
CACHE_OP_RANGE(DCACHE_CIPA_A0, start, end - start);
}
/*
* Once uboot execute csrsi mhcr 0x2.
* Will enter trap mode.
* Comment the implement to avoid problem first
*/
#if CV181X_UBOOT_USE_DCACHE_API
void dcache_enable(void)
{
asm volatile(
"csrs mhcr, %0;" ::"rI"(0x2)
);
}
void dcache_disable(void)
{
flush_dcache_range(0x80000000, 0x80000000 + CONFIG_SYS_BOOTMAPSZ);
asm volatile(
"csrc mhcr, %0;" ::"rI"(0x2)
);
}
#endif

2
u-boot-2021.10/arch/riscv/cpu/start.S
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@ -39,6 +39,8 @@ secondary_harts_relocation_error:
.section .text .section .text
.globl _start .globl _start
_start: _start:
#include <asm/boot0.h>
_start_real:
#if CONFIG_IS_ENABLED(RISCV_MMODE) #if CONFIG_IS_ENABLED(RISCV_MMODE)
csrr a0, CSR_MHARTID csrr a0, CSR_MHARTID
#endif #endif

2
u-boot-2021.10/arch/riscv/dts/Makefile
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@ -8,6 +8,8 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
dtb-$(CONFIG_TARGET_CVITEK) += $(CHIP)_$(CVIBOARD).dtb
targets += $(dtb-y) targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000 DTC_FLAGS += -R 4 -p 0x1000

14
u-boot-2021.10/arch/riscv/dts/cv1800b_wdmb_0008a_spinor.dts Normal file
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@ -0,0 +1,14 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_qfn.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
&mipi_rx{
snsr-reset = <&portc 8 GPIO_ACTIVE_LOW>, <&portc 8 GPIO_ACTIVE_LOW>, <&portc 8 GPIO_ACTIVE_LOW>;
};
/ {
};

14
u-boot-2021.10/arch/riscv/dts/cv1800b_wevb_0008a_spinor.dts Normal file
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@ -0,0 +1,14 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_qfn.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
&i2c2 {
status = "disabled";
};
/ {
};

14
u-boot-2021.10/arch/riscv/dts/cv1800c_wevb_0009a_spinor.dts Normal file
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@ -0,0 +1,14 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_qfn.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
&i2c1 {
status = "disabled";
};
/ {
};

14
u-boot-2021.10/arch/riscv/dts/cv1801b_wevb_0008a_spinor.dts Normal file
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@ -0,0 +1,14 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_qfn.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
&i2c2 {
status = "disabled";
};
/ {
};

17
u-boot-2021.10/arch/riscv/dts/cv1801c_wdmb_0009a_spinor.dts Normal file
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@ -0,0 +1,17 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_qfn.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
&i2c1 {
status = "disabled";
};
&mipi_rx{
snsr-reset = <&portc 17 GPIO_ACTIVE_LOW>, <&portc 17 GPIO_ACTIVE_LOW>, <&portc 17 GPIO_ACTIVE_LOW>;
};
/ {
};

13
u-boot-2021.10/arch/riscv/dts/cv1801c_wevb_0009a_spinand.dts Normal file
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@ -0,0 +1,13 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_qfn.dtsi"
#include "cv180x_asic_spinand.dtsi"
#include "cv180x_default_memmap.dtsi"
&i2c1 {
status = "disabled";
};
/ {
};

14
u-boot-2021.10/arch/riscv/dts/cv1801c_wevb_0009a_spinor.dts Normal file
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@ -0,0 +1,14 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_qfn.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
&i2c1 {
status = "disabled";
};
/ {
};

12
u-boot-2021.10/arch/riscv/dts/cv180x_asic_bga.dtsi Normal file
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@ -0,0 +1,12 @@
&dac{
mute-gpio-l = <&porta 15 GPIO_ACTIVE_LOW>;
mute-gpio-r = <&porta 30 GPIO_ACTIVE_LOW>;
};
/ {
/delete-node/ i2s@04110000;
/delete-node/ i2s@04120000;
/delete-node/ sound_ext1;
/delete-node/ sound_ext2;
/delete-node/ sound_PDM;
};

114
u-boot-2021.10/arch/riscv/dts/cv180x_asic_qfn.dtsi Normal file
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@ -0,0 +1,114 @@
&sd {
no-1-8-v;
};
&mipi_rx{
snsr-reset = <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>;
};
&dac{
mute-gpio-r = <&porte 2 GPIO_ACTIVE_LOW>;
};
&spi0 {
status = "disabled";
num-cs = <1>;
spidev@0 {
compatible = "rohm,dh2228fv";
spi-max-frequency = <1000000>;
reg = <0>;
};
};
&spi1 {
status = "disabled";
num-cs = <1>;
spidev@0 {
compatible = "rohm,dh2228fv";
spi-max-frequency = <1000000>;
reg = <0>;
};
};
&spi2 {
status = "disabled";
num-cs = <1>;
spidev@0 {
compatible = "rohm,dh2228fv";
spi-max-frequency = <1000000>;
reg = <0>;
};
};
&spi3 {
status = "okay";
num-cs = <1>;
spidev@0 {
compatible = "rohm,dh2228fv";
spi-max-frequency = <1000000>;
reg = <0>;
};
};
&i2c0 {
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
scl-pinmux = <0x0300104c 0x4 0x3>; // IIC0_SCL/IIC0_SCL/XGPIOA[28]
sda-pinmux = <0x03001050 0x4 0x3>; // IIC0_SDA/IIC0_SDA/XGPIOA[29]
/* gpio port */
scl-gpios = <&porta 28 GPIO_ACTIVE_HIGH>;
sda-gpios = <&porta 29 GPIO_ACTIVE_HIGH>;
};
&i2c1 {
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
scl-pinmux = <0x030010f4 0x4 0x3>; // PAD_MIPIRX0N/IIC1_SCL/XGPIOC[10]
sda-pinmux = <0x030010f0 0x4 0x3>; // PAD_MIPIRX1P/IIC1_SDA/XGPIOC[9]
/* gpio port */
scl-gpios = <&portc 10 GPIO_ACTIVE_HIGH>;
sda-gpios = <&portc 9 GPIO_ACTIVE_HIGH>;
};
&i2c2 {
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
scl-pinmux = <0x03001108 0x4 0x3>; // PAD_MIPI_TXP1/IIC2_SCL/XGPIOC[15]
sda-pinmux = <0x03001104 0x4 0x3>; // PAD_MIPI_TXM1/IIC2_SDA/XGPIOC[14]
/* gpio port */
scl-gpios = <&portc 15 GPIO_ACTIVE_HIGH>;
sda-gpios = <&portc 14 GPIO_ACTIVE_HIGH>;
};
&i2c3 {
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
scl-pinmux = <0x0300109c 0x2 0x3>; // SD1_CMD/IIC3_SCL/PWR_GPIO[22]
sda-pinmux = <0x030010a0 0x2 0x3>; // SD1_CLK/IIC3_SDA/PWR_GPIO[23]
/* gpio port */
scl-gpios = <&porte 22 GPIO_ACTIVE_HIGH>;
sda-gpios = <&porte 23 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
&i2c4 {
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
scl-pinmux = <0x030010e4 0x5 0x3>; // PAD_MIPIRX2N/IIC4_SCL/XGPIOC[6]
sda-pinmux = <0x030010e8 0x5 0x3>; // PAD_MIPIRX2P/IIC4_SDA/XGPIOC[7]
/* gpio port */
scl-gpios = <&portc 6 GPIO_ACTIVE_HIGH>;
sda-gpios = <&portc 7 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
/ {
/delete-node/ wifi-sd@4320000;
/delete-node/ i2s@04110000;
/delete-node/ i2s@04120000;
/delete-node/ sound_ext1;
/delete-node/ sound_ext2;
/delete-node/ sound_PDM;
wifi_pin {
compatible = "cvitek,wifi-pin";
poweron-gpio = <&porte 2 GPIO_ACTIVE_HIGH>;
wakeup-gpio = <&porte 6 GPIO_ACTIVE_HIGH>;
};
};

5
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/ {
/delete-node/ cvi-spif@10000000;
/delete-node/ cv-emmc@4300000;
};

5
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/ {
/delete-node/ cv-emmc@4300000;
/delete-node/ cv-spinf@4060000;
};

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/ {
compatible = "cvitek,cv180x";
#size-cells = <0x2>;
#address-cells = <0x2>;
top_misc:top_misc_ctrl@3000000 {
compatible = "syscon";
reg = <0x0 0x03000000 0x0 0x8000>;
};
clk_rst: clk-reset-controller {
#reset-cells = <1>;
compatible = "cvitek,clk-reset";
reg = <0x0 0x03002000 0x0 0x8>;
};
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "osc";
};
clk: clock-controller {
compatible = "cvitek,cv180x-clk";
reg = <0x0 0x03002000 0x0 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
rst: reset-controller {
#reset-cells = <1>;
compatible = "cvitek,reset";
reg = <0x0 0x03003000 0x0 0x10>;
};
restart: restart-controller {
compatible = "cvitek,restart";
reg = <0x0 0x05025000 0x0 0x2000>;
};
tpu {
compatible = "cvitek,tpu";
reg-names = "tdma", "tiu";
reg = <0x0 0x0C100000 0x0 0x1000>,
<0x0 0x0C101000 0x0 0x1000>;
clocks = <&clk CV180X_CLK_TPU>, <&clk CV180X_CLK_TPU_FAB>;
clock-names = "clk_tpu_axi", "clk_tpu_fab";
resets = <&rst RST_TDMA>, <&rst RST_TPU>, <&rst RST_TPUSYS>;
reset-names = "res_tdma", "res_tpu", "res_tpusys";
};
mon {
compatible = "cvitek,mon";
reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
reg = <0x0 0x01040000 0x0 0x1000>,
<0x0 0x08004000 0x0 0x1000>,
<0x0 0x08006000 0x0 0x1000>,
<0x0 0x08008000 0x0 0x1000>,
<0x0 0x0800A000 0x0 0x1000>;
};
wiegand0 {
compatible = "cvitek,wiegand";
reg-names = "wiegand";
reg = <0x0 0x03030000 0x0 0x1000>;
clocks = <&clk CV180X_CLK_WGN>, <&clk CV180X_CLK_WGN0>;
clock-names = "clk_wgn", "clk_wgn1";
resets = <&rst RST_WGN0>;
reset-names = "res_wgn";
};
wiegand1 {
compatible = "cvitek,wiegand";
reg-names = "wiegand";
reg = <0x0 0x03031000 0x0 0x1000>;
clocks = <&clk CV180X_CLK_WGN>, <&clk CV180X_CLK_WGN1>;
clock-names = "clk_wgn", "clk_wgn1";
resets = <&rst RST_WGN1>;
reset-names = "res_wgn";
};
wiegand2 {
compatible = "cvitek,wiegand";
reg-names = "wiegand";
reg = <0x0 0x03032000 0x0 0x1000>;
clocks = <&clk CV180X_CLK_WGN>, <&clk CV180X_CLK_WGN2>;
clock-names = "clk_wgn", "clk_wgn1";
resets = <&rst RST_WGN2>;
reset-names = "res_wgn";
};
saradc {
compatible = "cvitek,saradc";
reg-names = "top_domain_saradc", "rtc_domain_saradc";
reg = <0x0 0x030F0000 0x0 0x1000>, <0x0 0x0502c000 0x0 0x1000>;
clocks = <&clk CV180X_CLK_SARADC>;
clock-names = "clk_saradc";
resets = <&rst RST_SARADC>;
reset-names = "res_saradc";
};
rtc {
compatible = "cvitek,rtc";
reg = <0x0 0x05026000 0x0 0x1000>,<0x0 0x05025000 0x0 0x1000>;
clocks = <&clk CV180X_CLK_RTC_25M>;
clock-names = "clk_rtc";
};
cvitek-ion {
compatible = "cvitek,cvitek-ion";
heap_carveout@0 {
compatible = "cvitek,carveout";
memory-region = <&ion_reserved>;
};
};
sysdma_remap {
compatible = "cvitek,sysdma_remap";
reg = <0x0 0x03000154 0x0 0x10>;
ch-remap = <CVI_I2S0_RX CVI_I2S2_TX CVI_I2S1_RX CVI_I2S1_TX
CVI_SPI_NAND CVI_SPI_NAND CVI_I2S2_RX CVI_I2S3_TX>;
int_mux_base = <0x03000298>;
};
dmac: dma@0x4330000 {
compatible = "snps,dmac-bm";
reg = <0x0 0x04330000 0x0 0x1000>;
clock-names = "clk_sdma_axi";
clocks = <&clk CV180X_CLK_SDMA_AXI>;
dma-channels = /bits/ 8 <8>;
#dma-cells = <3>;
dma-requests = /bits/ 8 <16>;
chan_allocation_order = /bits/ 8 <0>;
chan_priority = /bits/ 8 <1>;
block_size = <1024>;
dma-masters = /bits/ 8 <2>;
data-width = <4 4>; /* bytes */
axi_tr_width = <4>; /* bytes */
block-ts = <15>;
};
watchdog0: cv-wd@0x3010000 {
compatible = "snps,dw-wdt";
reg = <0x0 0x03010000 0x0 0x1000>;
resets = <&rst RST_WDT>;
clocks = <&pclk>;
};
pwm0: pwm@3060000 {
compatible = "cvitek,cvi-pwm";
reg = <0x0 0x3060000 0x0 0x1000>;
clocks = <&clk CV180X_CLK_PWM>;
#pwm-cells = <1>;
};
pwm1: pwm@3061000 {
compatible = "cvitek,cvi-pwm";
reg = <0x0 0x3061000 0x0 0x1000>;
clocks = <&clk CV180X_CLK_PWM>;
#pwm-cells = <2>;
};
pwm2: pwm@3062000 {
compatible = "cvitek,cvi-pwm";
reg = <0x0 0x3062000 0x0 0x1000>;
clocks = <&clk CV180X_CLK_PWM>;
#pwm-cells = <3>;
};
pwm3: pwm@3063000 {
compatible = "cvitek,cvi-pwm";
reg = <0x0 0x3063000 0x0 0x1000>;
clocks = <&clk CV180X_CLK_PWM>;
#pwm-cells = <4>;
};
pclk: pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
spinand:cv-spinf@4060000 {
compatible = "cvitek,cv1835-spinf";
reg = <0x0 0x4060000 0x0 0x1000>;
reg-names = "core_mem";
bus-width = <4>;
dmas = <&dmac 4 1 1
&dmac 5 1 1>;
dma-names = "rx","tx";
};
spif:cvi-spif@10000000 {
compatible = "cvitek,cvi-spif";
bus-num = <0>;
reg = <0x0 0x10000000 0x0 0x10000000>;
reg-names = "spif";
sck-div = <3>;
sck_mhz = <300>;
spi-max-frequency = <75000000>;
spiflash {
compatible = "jedec,spi-nor";
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
spi0:spi0@04180000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x04180000 0x0 0x10000>;
clocks = <&clk CV180X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
};
spi1:spi1@04190000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x04190000 0x0 0x10000>;
clocks = <&clk CV180X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
};
spi2:spi2@041A0000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x041A0000 0x0 0x10000>;
clocks = <&clk CV180X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
};
spi3:spi3@041B0000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x041B0000 0x0 0x10000>;
clocks = <&clk CV180X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
#if 0
dmas = <&dmac 2 1 1
&dmac 3 1 1>;
dma-names = "rx", "tx";
capability = "txrx";
#endif
};
uart0: serial@04140000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x04140000 0x0 0x1000>;
clock-frequency = <25000000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "okay";
};
uart1: serial@04150000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x04150000 0x0 0x1000>;
clock-frequency = <25000000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@04160000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x04160000 0x0 0x1000>;
clock-frequency = <25000000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@04170000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x04170000 0x0 0x1000>;
clock-frequency = <25000000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart4: serial@041C0000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x041C0000 0x0 0x1000>;
clock-frequency = <25000000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
gpio0: gpio@03020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x03020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
bank-name = "porta";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
gpio1: gpio@03021000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x03021000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
portb: gpio-controller@1 {
compatible = "snps,dw-apb-gpio-port";
bank-name = "portb";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
gpio2: gpio@03022000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x03022000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
portc: gpio-controller@2 {
compatible = "snps,dw-apb-gpio-port";
bank-name = "portc";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
gpio3: gpio@03023000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x03023000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
portd: gpio-controller@3 {
compatible = "snps,dw-apb-gpio-port";
bank-name = "portd";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <12>;
reg = <0>;
};
};
gpio4: gpio@05021000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x05021000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
porte: gpio-controller@4 {
compatible = "snps,dw-apb-gpio-port";
bank-name = "porte";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <24>;
reg = <0>;
};
};
i2c0: i2c@04000000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV180X_CLK_I2C>;
reg = <0x0 0x04000000 0x0 0x1000>;
clock-frequency = <400000>;
#size-cells = <0x0>;
#address-cells = <0x1>;
resets = <&rst RST_I2C0>;
reset-names = "i2c0";
};
i2c1: i2c@04010000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV180X_CLK_I2C>;
reg = <0x0 0x04010000 0x0 0x1000>;
clock-frequency = <400000>;
#size-cells = <0x0>;
#address-cells = <0x1>;
resets = <&rst RST_I2C1>;
reset-names = "i2c1";
};
i2c2: i2c@04020000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV180X_CLK_I2C>;
reg = <0x0 0x04020000 0x0 0x1000>;
clock-frequency = <100000>;
#size-cells = <0x0>;
#address-cells = <0x1>;
resets = <&rst RST_I2C2>;
reset-names = "i2c2";
};
i2c3: i2c@04030000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV180X_CLK_I2C>;
reg = <0x0 0x04030000 0x0 0x1000>;
clock-frequency = <400000>;
#size-cells = <0x0>;
#address-cells = <0x1>;
resets = <&rst RST_I2C3>;
reset-names = "i2c3";
};
i2c4: i2c@04040000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV180X_CLK_I2C>;
reg = <0x0 0x04040000 0x0 0x1000>;
clock-frequency = <400000>;
#size-cells = <0x0>;
#address-cells = <0x1>;
resets = <&rst RST_I2C4>;
reset-names = "i2c4";
};
eth_csrclk: eth_csrclk {
clock-output-names = "eth_csrclk";
clock-frequency = <250000000>;
#clock-cells = <0x0>;
compatible = "fixed-clock";
};
eth_ptpclk: eth_ptpclk {
clock-output-names = "eth_ptpclk";
clock-frequency = <50000000>;
#clock-cells = <0x0>;
compatible = "fixed-clock";
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <1>;
snps,rd_osr_lmt = <2>;
snps,blen = <4 8 16 0 0 0 0>;
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
ethernet0: ethernet@4070000 {
compatible = "cvitek,ethernet";
reg = <0x0 0x04070000 0x0 0x10000>;
clock-names = "stmmaceth", "ptp_ref";
clocks = <&eth_csrclk>, <&eth_ptpclk>;
//phy-reset-gpios = <&porta 26 0>;
tx-fifo-depth = <8192>;
rx-fifo-depth = <8192>;
/* no hash filter and perfect filter support */
snps,multicast-filter-bins = <0>;
snps,perfect-filter-entries = <1>;
snps,txpbl = <8>;
snps,rxpbl = <8>;
snps,aal;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
phy-mode = "rmii";
};
sd:cv-sd@4310000 {
compatible = "cvitek,cv180x-sd";
reg = <0x0 0x4310000 0x0 0x1000>;
reg-names = "core_mem";
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
no-sdio;
no-mmc;
/*no-1-8-v;*/
src-frequency = <375000000>;
min-frequency = <400000>;
max-frequency = <200000000>;
64_addressing;
reset_tx_rx_phy;
reset-names = "sdhci";
pll_index = <0x6>;
pll_reg = <0x3002070>;
cvi-cd-gpios = <&porta 13 GPIO_ACTIVE_LOW>;
};
wifisd:wifi-sd@4320000 {
compatible = "cvitek,cv180x-sdio";
bus-width = <4>;
reg = <0x0 0x4320000 0x0 0x1000>;
reg_names = "core_mem";
src-frequency = <375000000>;
min-frequency = <400000>;
max-frequency = <50000000>;
64_addressing;
reset_tx_rx_phy;
non-removable;
pll_index = <0x7>;
pll_reg = <0x300207C>;
no-mmc;
no-sd;
status = "disabled";
};
i2s_mclk: i2s_mclk {
clock-output-names = "i2s_mclk";
clock-frequency = <24576000>;
#clock-cells = <0x0>;
compatible = "fixed-clock";
};
i2s_subsys {
compatible = "cvitek,i2s_tdm_subsys";
reg = <0x0 0x04108000 0x0 0x100>;
clocks = <&i2s_mclk>, <&clk CV180X_CLK_A0PLL>,
<&clk CV180X_CLK_SDMA_AUD0>, <&clk CV180X_CLK_SDMA_AUD1>,
<&clk CV180X_CLK_SDMA_AUD2>, <&clk CV180X_CLK_SDMA_AUD3>;
clock-names = "i2sclk", "clk_a0pll",
"clk_sdma_aud0", "clk_sdma_aud1",
"clk_sdma_aud2", "clk_sdma_aud3";
master_base = <0x04110000>; /* I2S1 is master, only useful while using multi I2S IPs work on same IO */
};
i2s0: i2s@04100000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04100000 0x0 0x2000>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <0>;
#sound-dai-cells = <0>;
dmas = <&dmac 0 1 1>; /* read channel */
dma-names = "rx";
capability = "rx"; /* I2S0 connect to internal ADC as RX */
mclk_out = "false";
};
i2s1: i2s@04110000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04110000 0x0 0x2000>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <1>;
#sound-dai-cells = <0>;
dmas = <&dmac 2 1 1 /* read channel */
&dmac 3 1 1>; /* write channel */
dma-names = "rx", "tx";
capability = "txrx";
mclk_out = "false";
};
i2s2: i2s@04120000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04120000 0x0 0x2000>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <2>;
#sound-dai-cells = <0>;
dmas = <&dmac 6 1 1 /* read channel */
&dmac 1 1 1>; /* write channel */
dma-names = "rx", "tx";
capability = "txrx";
mclk_out = "false";
};
i2s3: i2s@04130000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04130000 0x0 0x2000>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <3>;
#sound-dai-cells = <0>;
dmas = <&dmac 7 1 1>; /* write channel */
dma-names = "tx";
capability = "tx"; /* I2S3 connect to internal DAC as TX */
mclk_out = "true";
};
adc: adc@0300A100 {
compatible = "cvitek,cv182xaadc";
reg = <0x0 0x0300A100 0x0 0x100>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
clk_source = <0x04130000>; /* MCLK source is I2S3 */
};
dac: dac@0300A000 {
compatible = "cvitek,cv182xadac";
reg = <0x0 0x0300A000 0x0 0x100>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
};
pdm: pdm@0x041D0C00 {
compatible = "cvitek,cv1835pdm";
reg = <0x0 0x041D0C00 0x0 0x100>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
};
sound_adc {
compatible = "cvitek,cv182xa-adc";
cvi,model = "CV182XA";
cvi,card_name = "cv182xa_adc";
};
sound_dac {
compatible = "cvitek,cv182xa-dac";
cvi,model = "CV182XA";
cvi,card_name = "cv182xa_dac";
};
sound_PDM {
compatible = "cvitek,cv182x-pdm";
cvi,model = "CV182X";
cvi,card_name = "cv182x_internal_PDM";
};
wifi_pin {
compatible = "cvitek,wifi-pin";
poweron-gpio = <&porta 18 GPIO_ACTIVE_HIGH>;
wakeup-gpio = <&porte 7 GPIO_ACTIVE_HIGH>;
};
bt_pin {
compatible = "cvitek,bt-pin";
poweron-gpio = <&porte 9 GPIO_ACTIVE_HIGH>;
};
mipi_rx: cif {
compatible = "cvitek,cif";
reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
<0x0 0x0a0c4000 0x0 0x2000>, <0x0 0x03001c30 0x0 0x30>;
reg-names = "csi_mac0", "csi_wrap0", "csi_mac1", "pad_ctrl";
snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>;
resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
clocks = <&clk CV180X_CLK_CAM0>, <&clk CV180X_CLK_CAM1>, <&clk CV180X_CLK_SRC_VIP_SYS_2>,
<&clk CV180X_CLK_MIPIMPLL>, <&clk CV180X_CLK_DISPPLL>, <&clk CV180X_CLK_FPLL>;
clock-names = "clk_cam0", "clk_cam1", "clk_sys_2",
"clk_mipimpll", "clk_disppll", "clk_fpll";
};
sys {
compatible = "cvitek,sys";
};
base {
compatible = "cvitek,base";
reg = <0x0 0x0a0c8000 0x0 0x20>;
reg-names = "vip_sys";
};
vi {
compatible = "cvitek,vi";
reg = <0x0 0x0a000000 0x0 0x80000>;
clocks = <&clk CV180X_CLK_SRC_VIP_SYS_0>, <&clk CV180X_CLK_SRC_VIP_SYS_1>,
<&clk CV180X_CLK_SRC_VIP_SYS_2>, <&clk CV180X_CLK_SRC_VIP_SYS_3>,
<&clk CV180X_CLK_AXI_VIP>, <&clk CV180X_CLK_CSI_BE_VIP>,
<&clk CV180X_CLK_RAW_VIP>, <&clk CV180X_CLK_ISP_TOP_VIP>,
<&clk CV180X_CLK_CSI_MAC0_VIP>, <&clk CV180X_CLK_CSI_MAC1_VIP>,
<&clk CV180X_CLK_CSI_MAC2_VIP>;
clock-names = "clk_sys_0", "clk_sys_1", "clk_sys_2", "clk_sys_3",
"clk_axi", "clk_csi_be", "clk_raw", "clk_isp_top",
"clk_csi_mac0", "clk_csi_mac1", "clk_csi_mac2";
clock-freq-vip-sys1 = <300000000>;
};
vpss {
compatible = "cvitek,vpss";
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
reg-names = "sc";
clocks = <&clk CV180X_CLK_SRC_VIP_SYS_0>, <&clk CV180X_CLK_SRC_VIP_SYS_1>,
<&clk CV180X_CLK_SRC_VIP_SYS_2>, <&clk CV180X_CLK_IMG_D_VIP>,
<&clk CV180X_CLK_IMG_V_VIP>, <&clk CV180X_CLK_SC_TOP_VIP>,
<&clk CV180X_CLK_SC_D_VIP>, <&clk CV180X_CLK_SC_V1_VIP>,
<&clk CV180X_CLK_SC_V2_VIP>, <&clk CV180X_CLK_SC_V3_VIP>;
clock-names = "clk_sys_0", "clk_sys_1",
"clk_sys_2", "clk_img_d",
"clk_img_v", "clk_sc_top",
"clk_sc_d", "clk_sc_v1",
"clk_sc_v2", "clk_sc_v3";
clock-freq-vip-sys1 = <300000000>;
};
dwa {
compatible = "cvitek,dwa";
reg = <0x0 0x0a0c0000 0x0 0x1000>;
reg-names = "dwa";
clocks = <&clk CV180X_CLK_SRC_VIP_SYS_0>, <&clk CV180X_CLK_SRC_VIP_SYS_1>,
<&clk CV180X_CLK_SRC_VIP_SYS_2>, <&clk CV180X_CLK_SRC_VIP_SYS_3>,
<&clk CV180X_CLK_SRC_VIP_SYS_4>, <&clk CV180X_CLK_DWA_VIP>;
clock-names = "clk_sys_0", "clk_sys_1",
"clk_sys_2", "clk_sys_3",
"clk_sys_4", "clk_dwa";
clock-freq-vip-sys1 = <300000000>;
};
rgn {
compatible = "cvitek,rgn";
};
vcodec {
compatible = "cvitek,asic-vcodec";
reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>,
<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
reg-names = "h265","h264","vc_ctrl","vc_sbm","vc_addr_remap";
clocks = <&clk CV180X_CLK_AXI_VIDEO_CODEC>,
<&clk CV180X_CLK_H264C>, <&clk CV180X_CLK_APB_H264C>,
<&clk CV180X_CLK_H265C>, <&clk CV180X_CLK_APB_H265C>,
<&clk CV180X_CLK_VC_SRC0>, <&clk CV180X_CLK_VC_SRC1>,
<&clk CV180X_CLK_VC_SRC2>, <&clk CV180X_CLK_CFG_REG_VC>;
clock-names = "clk_axi_video_codec",
"clk_h264c", "clk_apb_h264c",
"clk_h265c", "clk_apb_h265c",
"clk_vc_src0", "clk_vc_src1",
"clk_vc_src2", "clk_cfg_reg_vc";
};
jpu {
compatible = "cvitek,asic-jpeg";
reg = <0x0 0x0B000000 0x0 0x300>,<0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>;
reg-names = "jpeg","vc_ctrl","vc_sbm";
clocks = <&clk CV180X_CLK_AXI_VIDEO_CODEC>,
<&clk CV180X_CLK_JPEG>, <&clk CV180X_CLK_APB_JPEG>,
<&clk CV180X_CLK_VC_SRC0>, <&clk CV180X_CLK_VC_SRC1>,
<&clk CV180X_CLK_VC_SRC2>, <&clk CV180X_CLK_CFG_REG_VC>;
clock-names = "clk_axi_video_codec",
"clk_jpeg", "clk_apb_jpeg",
"clk_vc_src0", "clk_vc_src1",
"clk_vc_src2", "clk_cfg_reg_vc";
resets = <&rst RST_JPEG>;
reset-names = "jpeg";
};
cvi_vc_drv {
compatible = "cvitek,cvi_vc_drv";
reg = <0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
reg-names = "vc_ctrl","vc_sbm","vc_addr_remap";
};
rtos_cmdqu {
compatible = "cvitek,rtos_cmdqu";
reg = <0x0 0x01900000 0x0 0x1000>;
reg-names = "mailbox";
};
usb: usb@04340000 {
compatible = "cvitek,cv182x-usb";
reg = <0x0 0x04340000 0x0 0x10000>,
<0x0 0x03006000 0x0 0x58>; //USB 2.0 PHY
dr_mode = "otg";
g-use-dma;
g-rx-fifo-size = <536>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <768 512 512 384 128 128>;
clocks = <&clk CV180X_CLK_AXI4_USB>,
<&clk CV180X_CLK_APB_USB>,
<&clk CV180X_CLK_125M_USB>,
<&clk CV180X_CLK_33K_USB>,
<&clk CV180X_CLK_12M_USB>;
clock-names = "clk_axi", "clk_apb", "clk_125m", "clk_33k", "clk_12m";
vbus-gpio = <&portb 6 0>;
status = "okay";
};
thermal:thermal@030E0000 {
compatible = "cvitek,cv180x-thermal";
reg = <0x0 0x030E0000 0x0 0x10000>;
clocks = <&clk CV180X_CLK_TEMPSEN>;
clock-names = "clk_tempsen";
reset-names = "tempsen";
#thermal-sensor-cells = <1>;
};
#if 0
cv182x_cooling:cv182x_cooling {
clocks = <&clk CV180X_CLK_A53>, <&clk CV180X_CLK_TPU>;
clock-names = "clk_a53", "clk_tpu_axi";
dev-freqs = <1000000000 750000000>,
<500000000 375000000>,
<500000000 100000000>;
compatible = "cvitek,cv182x-cooling";
#cooling-cells = <2>;
};
#endif
thermal-zones {
soc_thermal_0: soc_thermal_0 {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&thermal 0>;
trips {
soc_thermal_trip_0: soc_thermal_trip_0 {
temperature = <100000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "passive";
};
soc_thermal_trip_1: soc_thermal_trip_1 {
temperature = <110000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "passive";
};
soc_thermal_crtical_0: soc_thermal_crtical_0 {
temperature = <130000>; /* millicelsius */
hysteresis = <0>; /* millicelsius */
type = "critical";
};
};
};
};
#if 0
cvipctrl: pinctrl@3001000 {
compatible = "cvitek,pinctrl-cv182x";
reg = <0 0x03001000 0 0x1000>;
};
#endif
cviaudio_core {
compatible = "cvitek,audio";
};
audio_clock: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
#if 0
clock-frequency = <12288000>;
#else
clock-frequency = <24576000>;
#endif
};
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
serial0 = &uart0;
ethernet0 = &ethernet0;
};
chosen {
stdout-path = "serial0";
};
};

374
u-boot-2021.10/arch/riscv/dts/cv180x_base_riscv.dtsi Normal file
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#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/cv180x-resets.h>
#include <dt-bindings/clock/cv180x-clock.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/dma/cv180x-dmamap.h>
#include "cvi_board_memmap.h"
/*
* OpenSBI will add below subnode into reserved memory automatically
* mmode_resv0@80000000 {
* reg = <0x00 0x80000000 0x00 0x20000>;
* phandle = <0x0d>;
* };
* Skip below to avoid lmb region reseved conflict in uboot.
*
*/
#ifndef __UBOOT__
/memreserve/ CVIMMAP_MONITOR_ADDR CVIMMAP_OPENSBI_SIZE; // OpenSBI
#endif
#include "cv180x_base.dtsi"
/ {
model = "Cvitek. CV180X ASIC. C906.";
#size-cells = <0x2>;
#address-cells = <0x2>;
c906_cpus:cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
timebase-frequency = <25000000>;
cpu-map {
cluster0 {
core0 {
cpu = <0x01>;
};
};
};
cpu@0 {
device_type = "cpu";
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdvcsu";
mmu-type = "riscv,sv39";
clock-frequency = <25000000>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <0x01>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
soc {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "simple-bus";
ranges;
plic0: interrupt-controller@70000000 {
riscv,ndev = <101>;
riscv,max-priority = <0x07>;
reg-names = "control";
reg = <0x00 0x70000000 0x00 0x4000000>;
interrupts-extended = <&cpu0_intc 0xffffffff &cpu0_intc 0x09>;
interrupt-controller;
compatible = "riscv,plic0";
#interrupt-cells = <0x02>;
#address-cells = <0x00>;
};
clint@74000000 {
interrupts-extended = <&cpu0_intc 0x03 &cpu0_intc 0x07>;
reg = <0x00 0x74000000 0x00 0x10000>;
compatible = "riscv,clint0";
clint,has-no-64bit-mmio;
};
};
cv180x_cooling:cv180x_cooling {
clocks = <&clk CV180X_CLK_C906_0>, <&clk CV180X_CLK_TPU>;
clock-names = "clk_cpu", "clk_tpu_axi";
dev-freqs = <850000000 500000000>,
<425000000 375000000>,
<425000000 300000000>;
compatible = "cvitek,cv180x-cooling";
#cooling-cells = <2>;
};
tpu {
interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
<76 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tiu_irq", "tdma_irq";
interrupt-parent = <&plic0>;
};
mon {
interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mon_irq";
interrupt-parent = <&plic0>;
};
wiegand0 {
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
wiegand1 {
interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
wiegand2 {
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
saradc {
interrupts = <100 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&plic0>;
};
rtc {
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
sysdma_remap {
int_mux = <0x7FC00>; /* enable bit [10..18] for CPU1(906B) */
};
dmac: dma@0x4330000 {
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
watchdog0: cv-wd@0x3010000 {
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
};
spinand:cv-spinf@4060000 {
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
spif:cvi-spif@10000000 {
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
spi0:spi0@04180000 {
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
spi1:spi1@04190000 {
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
spi2:spi2@041A0000 {
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
spi3:spi3@041B0000 {
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
uart0: serial@04140000 {
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
uart1: serial@04150000 {
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
uart2: serial@04160000 {
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
uart3: serial@04170000 {
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
uart4: serial@041C0000 {
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
gpio0: gpio@03020000 {
porta: gpio-controller@0 {
interrupt-controller;
interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
};
gpio1: gpio@03021000 {
portb: gpio-controller@1 {
interrupt-controller;
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
};
gpio2: gpio@03022000 {
portc: gpio-controller@2 {
interrupt-controller;
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
};
gpio3: gpio@03023000 {
portd: gpio-controller@3 {
interrupt-controller;
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
};
gpio4: gpio@05021000 {
porte: gpio-controller@4 {
interrupt-controller;
interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
};
i2c0: i2c@04000000 {
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
i2c1: i2c@04010000 {
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
i2c2: i2c@04020000 {
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
i2c3: i2c@04030000 {
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
i2c4: i2c@04040000 {
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
ethernet0: ethernet@4070000 {
interrupt-names = "macirq";
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
#if 0
emmc:cv-emmc@4300000 {
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
#endif
sd:cv-sd@4310000 {
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
i2s0: i2s@04100000 {
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
i2s1: i2s@04110000 {
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
i2s2: i2s@04120000 {
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
i2s3: i2s@04130000 {
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
vi {
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
interrupt-names = "isp";
};
vcodec {
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>,
<21 IRQ_TYPE_LEVEL_HIGH>,
<23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "h265","h264","sbm";
interrupt-parent = <&plic0>;
};
jpu {
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "jpeg";
interrupt-parent = <&plic0>;
};
rtos_cmdqu {
interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mailbox";
interrupt-parent = <&plic0>;
};
wifisd:wifi-sd@4320000 {
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
mipi_rx: cif {
interrupts = <26 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "csi0", "csi1";
interrupt-parent = <&plic0>;
};
#if 0
ive {
interrupt-names = "ive_irq";
interrupt-parent = <&plic0>;
interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
};
#endif
vpss {
interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sc";
interrupt-parent = <&plic0>;
};
dwa {
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dwa";
interrupt-parent = <&plic0>;
};
usb: usb@04340000 {
interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&plic0>;
};
thermal:thermal@030E0000 {
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tempsen";
interrupt-parent = <&plic0>;
};
};

26
u-boot-2021.10/arch/riscv/dts/cv180x_default_memmap.dtsi Normal file
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@ -0,0 +1,26 @@
/ {
memory@80000000 {
device_type = "memory";
reg = <0x00 CVIMMAP_KERNEL_MEMORY_ADDR 0x00 CVIMMAP_KERNEL_MEMORY_SIZE>;
};
fast_image {
compatible = "cvitek,rtos_image";
reg-names = "rtos_region";
reg = <0x0 CVIMMAP_FREERTOS_ADDR 0x0 CVIMMAP_FREERTOS_SIZE>;
ion-size = <CVIMMAP_FREERTOS_RESERVED_ION_SIZE>; //reserved ion size for freertos
};
reserved-memory {
#size-cells = <0x2>;
#address-cells = <0x2>;
ranges;
ion_reserved: ion {
compatible = "ion-region";
alloc-ranges = <0x0 CVIMMAP_ION_ADDR 0 CVIMMAP_ION_SIZE>;
size = <0x0 CVIMMAP_ION_SIZE>;
};
};
};

16
u-boot-2021.10/arch/riscv/dts/cv180x_fpga.dts Normal file
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@ -0,0 +1,16 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_bga.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
/ {
};
&sd {
no-1-8-v;
src-frequency = <25000000>;
min-frequency = <400000>;
max-frequency = <12000000>;
};

22
u-boot-2021.10/arch/riscv/dts/cv180x_palladium.dts Normal file
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@ -0,0 +1,22 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_bga.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
/ {
};
&c906_cpus {
timebase-frequency = <1000000000>;
cpu@0 {
clock-frequency = <850000000>;
};
};
&uart0 {
clock-frequency = <307200>;
current-speed = <19200>;
};

14
u-boot-2021.10/arch/riscv/dts/cv180zb_wdmb_0008a_spinor.dts Normal file
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@ -0,0 +1,14 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_qfn.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
&mipi_rx{
snsr-reset = <&portc 8 GPIO_ACTIVE_LOW>, <&portc 8 GPIO_ACTIVE_LOW>, <&portc 8 GPIO_ACTIVE_LOW>;
};
/ {
};

14
u-boot-2021.10/arch/riscv/dts/cv180zb_wevb_0008a_spinor.dts Normal file
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@ -0,0 +1,14 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_qfn.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
&mipi_rx{
snsr-reset = <&portc 8 GPIO_ACTIVE_LOW>, <&portc 8 GPIO_ACTIVE_LOW>, <&portc 8 GPIO_ACTIVE_LOW>;
};
/ {
};

31
u-boot-2021.10/arch/riscv/include/asm/boot0.h Normal file
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@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* CVITEK u-boot header
*/
#ifndef __BOOT0_H__
#define __BOOT0_H__
/* BOOT0 header information */
j boot0_time_recode
.balign 4
.word 0x33334c42 /* b'BL33' */
.word 0xdeadbeea /* CKSUM */
.word 0xdeadbeeb /* SIZE */
.quad CONFIG_SYS_TEXT_BASE /* RUNADDR */
.word 0xdeadbeec
.balign 4
j boot0_time_recode
.balign 4
/* BOOT0 header end */
boot0_time_recode:
csrr x1, time
la x2, BOOT0_START_TIME
sw x1, 0(x2)
j _start_real
.global BOOT0_START_TIME
BOOT0_START_TIME:
.word 0
#endif /* __BOOT0_H__ */

3
u-boot-2021.10/arch/riscv/include/asm/cache.h
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@ -9,7 +9,8 @@
/* cache */ /* cache */
void cache_flush(void); void cache_flush(void);
void invalidate_dcache_range(unsigned long start, unsigned long end);
void flush_dcache_range(unsigned long start, unsigned long end);
/* /*
* The current upper bound for RISCV L1 data cache line sizes is 32 bytes. * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
* We use that value for aligning DMA buffers unless the board config has * We use that value for aligning DMA buffers unless the board config has

16
u-boot-2021.10/arch/riscv/include/asm/io.h
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@ -44,15 +44,15 @@ static inline phys_addr_t map_to_sysmem(const void *ptr)
* read/writes. We define __arch_*[bl] here, and leave __arch_*w * read/writes. We define __arch_*[bl] here, and leave __arch_*w
* to the architecture specific code. * to the architecture specific code.
*/ */
#define __arch_getb(a) (*(unsigned char *)(a)) #define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(unsigned short *)(a)) #define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(unsigned int *)(a)) #define __arch_getl(a) (*(volatile unsigned int *)(a))
#define __arch_getq(a) (*(unsigned long long *)(a)) #define __arch_getq(a) (*(volatile unsigned long long *)(a))
#define __arch_putb(v, a) (*(unsigned char *)(a) = (v)) #define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v, a) (*(unsigned short *)(a) = (v)) #define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) #define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v)) #define __arch_putq(v, a) (*(volatile unsigned long long *)(a) = (v))
#define __raw_writeb(v, a) __arch_putb(v, a) #define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a) #define __raw_writew(v, a) __arch_putw(v, a)

1
u-boot-2021.10/arch/riscv/include/asm/u-boot-riscv.h
View File

@ -16,6 +16,7 @@ int cleanup_before_linux(void);
/* board/.../... */ /* board/.../... */
int board_init(void); int board_init(void);
void board_save_time_record(uintptr_t saveaddr);
void board_quiesce_devices(void); void board_quiesce_devices(void);
int riscv_board_reserved_mem_fixup(void *fdt); int riscv_board_reserved_mem_fixup(void *fdt);
int riscv_fdt_copy_resv_mem_node(const void *src_fdt, void *dest_fdt); int riscv_fdt_copy_resv_mem_node(const void *src_fdt, void *dest_fdt);

16
u-boot-2021.10/arch/riscv/lib/bootm.c
View File

@ -60,6 +60,9 @@ static void announce_and_cleanup(int fake)
dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
cleanup_before_linux(); cleanup_before_linux();
// Save kernel start time
board_save_time_record(TIME_RECORDS_FIELD_KERNEL_START);
} }
static void boot_prep_linux(bootm_headers_t *images) static void boot_prep_linux(bootm_headers_t *images)
@ -135,3 +138,16 @@ int do_bootm_vxworks(int flag, int argc, char *const argv[],
{ {
return do_bootm_linux(flag, argc, argv, images); return do_bootm_linux(flag, argc, argv, images);
} }
static ulong get_sp(void)
{
ulong ret;
asm("mv %0, sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}

5
u-boot-2021.10/arch/riscv/lib/reset.c
View File

@ -7,12 +7,13 @@
#include <command.h> #include <command.h>
#include <hang.h> #include <hang.h>
extern void cv_system_reset(void);
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{ {
printf("resetting ...\n"); printf("resetting ...\n");
printf("reset not supported yet\n"); cv_system_reset();
hang();
return 0; return 0;
} }

35
u-boot-2021.10/board/cvitek/Kconfig Normal file
View File

@ -0,0 +1,35 @@
if TARGET_CVITEK_ARM || TARGET_CVITEK_RISCV
config TARGET_CVITEK
def_bool n
select ARM64 if TARGET_CVITEK_ARM
select GENERIC_RISCV if TARGET_CVITEK_RISCV
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_CVITEK_ARM
choice
prompt "Cvitek target"
config TARGET_CVITEK_CV1835
bool "Support CVITEK CV1835"
select TARGET_CVITEK
config TARGET_CVITEK_CV1822
bool "Support CVITEK CV1822"
select TARGET_CVITEK
config TARGET_CVITEK_CV181X
bool "Support CVITEK CV181X"
select TARGET_CVITEK
config TARGET_CVITEK_CV180X
bool "Support CVITEK CV180X"
select TARGET_CVITEK
endchoice
source "board/cvitek/cv1835/Kconfig"
source "board/cvitek/cv1822/Kconfig"
source "board/cvitek/cv181x/Kconfig"
source "board/cvitek/cv180x/Kconfig"
endif

76
u-boot-2021.10/board/cvitek/cv180x/Kconfig Normal file
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@ -0,0 +1,76 @@
if TARGET_CVITEK_CV180X
choice
prompt "Cvitek CV180X verification platform type select"
help
Select the board version of the shc board.
config TARGET_CVITEK_CV180X_ASIC
bool "ASIC"
help
This enables support for Cvitek's CV180X SoC on ASIC platform.
If unsure, say N.
config TARGET_CVITEK_CV180X_PALLADIUM
bool "Palladium"
help
This enables support for Cvitek's CV180X SoC on PALLADIUM platform.
If unsure, say N.
config TARGET_CVITEK_CV180X_FPGA
bool "FPGA"
help
This enables support for Cvitek's CV180X SoC on FPGA platform.
If unsure, say N.
endchoice
config SYS_BOARD
default "cv180x"
config SYS_VENDOR
default "cvitek"
config SYS_CPU
default "generic"
config SYS_CONFIG_NAME
default "cv180x-asic" if TARGET_CVITEK_CV180X_ASIC
default "cv180x-palladium" if TARGET_CVITEK_CV180X_PALLADIUM
default "cv180x-fpga" if TARGET_CVITEK_CV180X_FPGA
config CVITEK_SPI_FLASH
bool
prompt "Support CVITEK SPINOR"
select SPI_FLASH
select DM
select DM_SPI
select DM_SPI_FLASH
select SPI_MEM
select CMD_SF
select CVI_SPIF
select ENV_IS_IN_SPI_FLASH
config ENV_SIZE
default 0x10000 if ENV_IS_IN_SPI_FLASH
default 0x20000 if ENV_IS_IN_MMC
default 0x20000 if ENV_IS_IN_NAND
config ENV_SECT_SIZE
default 0x10000 if ENV_IS_IN_SPI_FLASH
default 0x40000 if ENV_IS_IN_MMC
default 0x20000 if ENV_IS_IN_NAND
config ENV_OFFSET
default 0x3A0000 if ENV_IS_IN_SPI_FLASH
default 0x880000 if ENV_IS_IN_MMC
default 0xae0000 if ENV_IS_IN_NAND
config ENV_OFFSET_REDUND
default 0x3B0000 if ENV_IS_IN_SPI_FLASH
default 0xb00000 if ENV_IS_IN_NAND
endif

2
u-boot-2021.10/board/cvitek/cv180x/Makefile Normal file
View File

@ -0,0 +1,2 @@
obj-y := board.o

304
u-boot-2021.10/board/cvitek/cv180x/board.c Normal file
View File

@ -0,0 +1,304 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
* Sharma Bhupesh <bhupesh.sharma@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <errno.h>
#include <asm/io.h>
#include <linux/compiler.h>
#if defined(__aarch64__)
#include <asm/armv8/mmu.h>
#endif
#include <usb/dwc2_udc.h>
#include <usb.h>
#include "cv180x_reg.h"
#include "mmio.h"
#include "cv180x_reg_fmux_gpio.h"
#include "cv180x_pinlist_swconfig.h"
#include <linux/delay.h>
#include <bootstage.h>
#if defined(__riscv)
#include <asm/csr.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define SD1_SDIO_PAD
#if defined(CV1801C_WEVB_0009A_SPINOR) || \
defined(CV1800C_WEVB_0009A_SPINOR) || \
defined(CV1801C_WEVB_0009A_SPINAND)
#define CV180X_QFN_88_PIN
#elif defined(CV1801C_WDMB_0009A_SPINOR)
#define CV180X_QFN_88_PIN_38
#else
#define CV180X_QFN_68_PIN
#endif
#if defined(__aarch64__)
static struct mm_region cv180x_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = PHYS_SDRAM_1,
.phys = PHYS_SDRAM_1,
.size = PHYS_SDRAM_1_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = cv180x_mem_map;
#endif
// #define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) printf ("%s\n", PIN_NAME ##_ ##FUNC_NAME);
#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \
FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK << FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET, \
PIN_NAME##__##FUNC_NAME)
void pinmux_config(int io_type)
{
switch (io_type) {
case PINMUX_UART0:
PINMUX_CONFIG(UART0_RX, UART0_RX);
PINMUX_CONFIG(UART0_TX, UART0_TX);
break;
case PINMUX_SDIO0:
PINMUX_CONFIG(SD0_CD, SDIO0_CD);
PINMUX_CONFIG(SD0_PWR_EN, SDIO0_PWR_EN);
PINMUX_CONFIG(SD0_CMD, SDIO0_CMD);
PINMUX_CONFIG(SD0_CLK, SDIO0_CLK);
PINMUX_CONFIG(SD0_D0, SDIO0_D_0);
PINMUX_CONFIG(SD0_D1, SDIO0_D_1);
PINMUX_CONFIG(SD0_D2, SDIO0_D_2);
PINMUX_CONFIG(SD0_D3, SDIO0_D_3);
break;
case PINMUX_SPI0:
PINMUX_CONFIG(SD0_CMD, SPI0_SDO);
PINMUX_CONFIG(SD0_CLK, SPI0_SCK);
PINMUX_CONFIG(SD0_D0, SPI0_SDI);
PINMUX_CONFIG(SD0_D3, SPI0_CS_X);
break;
case PINMUX_SPI2:
PINMUX_CONFIG(SD1_CMD, SPI2_SDO);
PINMUX_CONFIG(SD1_CLK, SPI2_SCK);
PINMUX_CONFIG(SD1_D0, SPI2_SDI);
PINMUX_CONFIG(SD1_D3, SPI2_CS_X);
break;
case PINMUX_SDIO1:
#if defined(SD1_SDIO_PAD)
/*
* Name Address SD1 MIPI
* reg_sd1_phy_sel REG_0x300_0294[10] 0x0 0x1
*/
mmio_write_32(TOP_BASE + 0x294,
(mmio_read_32(TOP_BASE + 0x294) & 0xFFFFFBFF));
PINMUX_CONFIG(SD1_CMD, PWR_SD1_CMD);
PINMUX_CONFIG(SD1_CLK, PWR_SD1_CLK);
PINMUX_CONFIG(SD1_D0, PWR_SD1_D0);
PINMUX_CONFIG(SD1_D1, PWR_SD1_D1);
PINMUX_CONFIG(SD1_D2, PWR_SD1_D2);
PINMUX_CONFIG(SD1_D3, PWR_SD1_D3);
#endif
break;
case PINMUX_SPI_NOR:
PINMUX_CONFIG(SPINOR_HOLD_X, SPINOR_HOLD_X);
PINMUX_CONFIG(SPINOR_SCK, SPINOR_SCK);
PINMUX_CONFIG(SPINOR_MOSI, SPINOR_MOSI);
PINMUX_CONFIG(SPINOR_WP_X, SPINOR_WP_X);
PINMUX_CONFIG(SPINOR_MISO, SPINOR_MISO);
PINMUX_CONFIG(SPINOR_CS_X, SPINOR_CS_X);
break;
case PINMUX_SPI_NAND:
PINMUX_CONFIG(SPINOR_HOLD_X, SPINAND_HOLD);
PINMUX_CONFIG(SPINOR_SCK, SPINAND_CLK);
PINMUX_CONFIG(SPINOR_MOSI, SPINAND_MOSI);
PINMUX_CONFIG(SPINOR_WP_X, SPINAND_WP);
PINMUX_CONFIG(SPINOR_MISO, SPINAND_MISO);
PINMUX_CONFIG(SPINOR_CS_X, SPINAND_CS);
break;
case PINMUX_USB:
#if defined(CV180X_QFN_88_PIN)
PINMUX_CONFIG(PWR_GPIO0, PWR_GPIO_0);
PINMUX_CONFIG(PWR_GPIO1, PWR_GPIO_1);
PINMUX_CONFIG(ADC1, XGPIOB_3);
PINMUX_CONFIG(USB_VBUS_DET, USB_VBUS_DET);
#elif defined(CV180X_QFN_88_PIN_38)
PINMUX_CONFIG(ADC1, XGPIOB_3);
PINMUX_CONFIG(USB_VBUS_DET, USB_VBUS_DET);
#elif defined(CV180X_QFN_68_PIN)
PINMUX_CONFIG(SD1_GPIO0, PWR_GPIO_25);
PINMUX_CONFIG(SD1_GPIO1, PWR_GPIO_26);
PINMUX_CONFIG(ADC1, XGPIOB_3);
PINMUX_CONFIG(USB_VBUS_DET, USB_VBUS_DET);
#endif
break;
default:
break;
}
}
#include "../cvi_board_init.c"
#if defined(CONFIG_PHY_CVITEK_CV182XA)
static void cv182xa_ephy_id_init(void)
{
// set rg_ephy_apb_rw_sel 0x0804@[0]=1/APB by using APB interface
mmio_write_32(0x03009804, 0x0001);
// Release 0x0800[0]=0/shutdown
mmio_write_32(0x03009800, 0x0900);
// Release 0x0800[2]=1/dig_rst_n, Let mii_reg can be accessabile
mmio_write_32(0x03009800, 0x0904);
// PHY_ID
mmio_write_32(0x03009008, 0x0043);
mmio_write_32(0x0300900c, 0x5649);
// switch to MDIO control by ETH_MAC
mmio_write_32(0x03009804, 0x0000);
}
#endif
int board_init(void)
{
extern uint32_t BOOT0_START_TIME;
uint16_t start_time = DIV_ROUND_UP(BOOT0_START_TIME, SYS_COUNTER_FREQ_IN_SECOND / 1000);
// Save uboot start time. time is from boot0.h
mmio_write_16(TIME_RECORDS_FIELD_UBOOT_START, start_time);
#if defined(CONFIG_PHY_CVITEK_CV182XA) /* config cvitek cr181x/cr180x eth internal phy on ASIC board */
cv182xa_ephy_id_init();
#endif
#if defined(CONFIG_NAND_SUPPORT)
pinmux_config(PINMUX_SPI_NAND);
#elif defined(CONFIG_SPI_FLASH)
pinmux_config(PINMUX_SPI_NOR);
#endif
// pinmux_config(PINMUX_SDIO1);
pinmux_config(PINMUX_USB);
//pinmux_config(PINMUX_SPI0);
//pinmux_config(PINMUX_SPI2);
cvi_board_init();
return 0;
}
#if defined(__aarch64__)
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#endif
#ifdef CV_SYS_OFF
static void cv_system_off(void)
{
mmio_write_32(REG_RTC_BASE + RTC_EN_SHDN_REQ, 0x01);
while (mmio_read_32(REG_RTC_BASE + RTC_EN_SHDN_REQ) != 0x01)
;
mmio_write_32(REG_RTC_CTRL_BASE + RTC_CTRL0_UNLOCKKEY, 0xAB18);
mmio_setbits_32(REG_RTC_CTRL_BASE + RTC_CTRL0, 0xFFFF0800 | (0x1 << 0));
while (1)
;
}
#endif
void cv_system_reset(void)
{
mmio_write_32(REG_RTC_BASE + RTC_EN_WARM_RST_REQ, 0x01);
while (mmio_read_32(REG_RTC_BASE + RTC_EN_WARM_RST_REQ) != 0x01)
;
mmio_write_32(REG_RTC_CTRL_BASE + RTC_CTRL0_UNLOCKKEY, 0xAB18);
mmio_setbits_32(REG_RTC_CTRL_BASE + RTC_CTRL0, 0xFFFF0800 | (0x1 << 4));
while (1)
;
}
/*
* Board specific reset that is system reset.
*/
void reset_cpu(void)
{
cv_system_reset();
}
#ifdef CONFIG_USB_GADGET_DWC2_OTG
struct dwc2_plat_otg_data cv182x_otg_data = {
.regs_otg = USB_BASE,
.usb_gusbcfg = 0x40081400,
.rx_fifo_sz = 512,
.np_tx_fifo_sz = 512,
.tx_fifo_sz = 512,
};
int board_usb_init(int index, enum usb_init_type init)
{
uint32_t value;
value = mmio_read_32(TOP_BASE + REG_TOP_SOFT_RST) & (~BIT_TOP_SOFT_RST_USB);
mmio_write_32(TOP_BASE + REG_TOP_SOFT_RST, value);
udelay(50);
value = mmio_read_32(TOP_BASE + REG_TOP_SOFT_RST) | BIT_TOP_SOFT_RST_USB;
mmio_write_32(TOP_BASE + REG_TOP_SOFT_RST, value);
/* Set USB phy configuration */
value = mmio_read_32(REG_TOP_USB_PHY_CTRL);
mmio_write_32(REG_TOP_USB_PHY_CTRL, value | BIT_TOP_USB_PHY_CTRL_EXTVBUS
| USB_PHY_ID_OVERRIDE_ENABLE
| USB_PHY_ID_VALUE);
/* Enable ECO RXF */
mmio_write_32(REG_TOP_USB_ECO, mmio_read_32(REG_TOP_USB_ECO) | BIT_TOP_USB_ECO_RX_FLUSH);
printf("cvi_usb_hw_init done\n");
return dwc2_udc_probe(&cv182x_otg_data);
}
#endif
void board_save_time_record(uintptr_t saveaddr)
{
uint64_t boot_us = 0;
#if defined(__aarch64__)
boot_us = timer_get_boot_us();
#elif defined(__riscv)
// Read from CSR_TIME directly. RISC-V timers is initialized later.
boot_us = csr_read(CSR_TIME) / (SYS_COUNTER_FREQ_IN_SECOND / 1000000);
#else
#error "Unknown ARCH"
#endif
mmio_write_16(saveaddr, DIV_ROUND_UP(boot_us, 1000));
}

407
u-boot-2021.10/board/cvitek/cv180x/cv180x_pinlist_swconfig.h Normal file
View File

@ -0,0 +1,407 @@
//##==============================================================================
//##=== This script is generate by genswconfig.pl from .\00_cv180x_Pinlist_20220315.xls
//##=== Generate Time stamp is : 2022-03-17 14:04:49
//##==============================================================================
#ifndef __CV180X_PINLIST_SWCONFIG_H__
#define __CV180X_PINLIST_SWCONFIG_H__
#define SD0_CLK__SDIO0_CLK 0
#define SD0_CLK__IIC1_SDA 1
#define SD0_CLK__SPI0_SCK 2
#define SD0_CLK__XGPIOA_7 3
#define SD0_CLK__PWM_15 5
#define SD0_CLK__EPHY_LNK_LED 6
#define SD0_CLK__DBG_0 7
#define SD0_CMD__SDIO0_CMD 0
#define SD0_CMD__IIC1_SCL 1
#define SD0_CMD__SPI0_SDO 2
#define SD0_CMD__XGPIOA_8 3
#define SD0_CMD__PWM_14 5
#define SD0_CMD__EPHY_SPD_LED 6
#define SD0_CMD__DBG_1 7
#define SD0_D0__SDIO0_D_0 0
#define SD0_D0__CAM_MCLK1 1
#define SD0_D0__SPI0_SDI 2
#define SD0_D0__XGPIOA_9 3
#define SD0_D0__UART3_TX 4
#define SD0_D0__PWM_13 5
#define SD0_D0__WG0_D0 6
#define SD0_D0__DBG_2 7
#define SD0_D1__SDIO0_D_1 0
#define SD0_D1__IIC1_SDA 1
#define SD0_D1__AUX0 2
#define SD0_D1__XGPIOA_10 3
#define SD0_D1__UART1_TX 4
#define SD0_D1__PWM_12 5
#define SD0_D1__WG0_D1 6
#define SD0_D1__DBG_3 7
#define SD0_D2__SDIO0_D_2 0
#define SD0_D2__IIC1_SCL 1
#define SD0_D2__AUX1 2
#define SD0_D2__XGPIOA_11 3
#define SD0_D2__UART1_RX 4
#define SD0_D2__PWM_11 5
#define SD0_D2__WG1_D0 6
#define SD0_D2__DBG_4 7
#define SD0_D3__SDIO0_D_3 0
#define SD0_D3__CAM_MCLK0 1
#define SD0_D3__SPI0_CS_X 2
#define SD0_D3__XGPIOA_12 3
#define SD0_D3__UART3_RX 4
#define SD0_D3__PWM_10 5
#define SD0_D3__WG1_D1 6
#define SD0_D3__DBG_5 7
#define SD0_CD__SDIO0_CD 0
#define SD0_CD__XGPIOA_13 3
#define SD0_PWR_EN__SDIO0_PWR_EN 0
#define SD0_PWR_EN__XGPIOA_14 3
#define SPK_EN__XGPIOA_15 3
#define UART0_TX__UART0_TX 0
#define UART0_TX__CAM_MCLK1 1
#define UART0_TX__PWM_4 2
#define UART0_TX__XGPIOA_16 3
#define UART0_TX__UART1_TX 4
#define UART0_TX__AUX1 5
#define UART0_TX__JTAG_TMS 6
#define UART0_TX__DBG_6 7
#define UART0_RX__UART0_RX 0
#define UART0_RX__CAM_MCLK0 1
#define UART0_RX__PWM_5 2
#define UART0_RX__XGPIOA_17 3
#define UART0_RX__UART1_RX 4
#define UART0_RX__AUX0 5
#define UART0_RX__JTAG_TCK 6
#define UART0_RX__DBG_7 7
#define SPINOR_HOLD_X__SPINOR_HOLD_X 1
#define SPINOR_HOLD_X__SPINAND_HOLD 2
#define SPINOR_HOLD_X__XGPIOA_26 3
#define SPINOR_SCK__SPINOR_SCK 1
#define SPINOR_SCK__SPINAND_CLK 2
#define SPINOR_SCK__XGPIOA_22 3
#define SPINOR_MOSI__SPINOR_MOSI 1
#define SPINOR_MOSI__SPINAND_MOSI 2
#define SPINOR_MOSI__XGPIOA_25 3
#define SPINOR_WP_X__SPINOR_WP_X 1
#define SPINOR_WP_X__SPINAND_WP 2
#define SPINOR_WP_X__XGPIOA_27 3
#define SPINOR_MISO__SPINOR_MISO 1
#define SPINOR_MISO__SPINAND_MISO 2
#define SPINOR_MISO__XGPIOA_23 3
#define SPINOR_CS_X__SPINOR_CS_X 1
#define SPINOR_CS_X__SPINAND_CS 2
#define SPINOR_CS_X__XGPIOA_24 3
#define JTAG_CPU_TMS__JTAG_TMS 0
#define JTAG_CPU_TMS__CAM_MCLK0 1
#define JTAG_CPU_TMS__PWM_7 2
#define JTAG_CPU_TMS__XGPIOA_19 3
#define JTAG_CPU_TMS__UART1_RTS 4
#define JTAG_CPU_TMS__AUX0 5
#define JTAG_CPU_TMS__UART1_TX 6
#define JTAG_CPU_TCK__JTAG_TCK 0
#define JTAG_CPU_TCK__CAM_MCLK1 1
#define JTAG_CPU_TCK__PWM_6 2
#define JTAG_CPU_TCK__XGPIOA_18 3
#define JTAG_CPU_TCK__UART1_CTS 4
#define JTAG_CPU_TCK__AUX1 5
#define JTAG_CPU_TCK__UART1_RX 6
#define IIC0_SCL__CV_SCL0__CR_4WTDI 0
#define IIC0_SDA__CV_SDA0__CR_4WTDO 0
#define IIC0_SCL__JTAG_TDI 0
#define IIC0_SCL__UART1_TX 1
#define IIC0_SCL__UART2_TX 2
#define IIC0_SCL__XGPIOA_28 3
#define IIC0_SCL__IIC0_SCL 4
#define IIC0_SCL__WG0_D0 5
#define IIC0_SCL__DBG_10 7
#define IIC0_SDA__JTAG_TDO 0
#define IIC0_SDA__UART1_RX 1
#define IIC0_SDA__UART2_RX 2
#define IIC0_SDA__XGPIOA_29 3
#define IIC0_SDA__IIC0_SDA 4
#define IIC0_SDA__WG0_D1 5
#define IIC0_SDA__WG1_D0 6
#define IIC0_SDA__DBG_11 7
#define AUX0__AUX0 0
#define AUX0__XGPIOA_30 3
#define AUX0__IIS1_MCLK 4
#define AUX0__WG1_D1 6
#define AUX0__DBG_12 7
#define GPIO_ZQ__PWR_GPIO_24 3
#define GPIO_ZQ__PWM_2 4
#define PWR_VBAT_DET__PWR_VBAT_DET 0
#define PWR_RSTN__PWR_RSTN 0
#define PWR_SEQ1__PWR_SEQ1 0
#define PWR_SEQ1__PWR_GPIO_3 3
#define PWR_SEQ2__PWR_SEQ2 0
#define PWR_SEQ2__PWR_GPIO_4 3
#define PTEST__PWR_PTEST 0
#define PWR_WAKEUP0__PWR_WAKEUP0 0
#define PWR_WAKEUP0__PWR_IR0 1
#define PWR_WAKEUP0__PWR_UART0_TX 2
#define PWR_WAKEUP0__PWR_GPIO_6 3
#define PWR_WAKEUP0__UART1_TX 4
#define PWR_WAKEUP0__IIC4_SCL 5
#define PWR_WAKEUP0__EPHY_LNK_LED 6
#define PWR_WAKEUP0__WG2_D0 7
#define PWR_BUTTON1__PWR_BUTTON1 0
#define PWR_BUTTON1__PWR_GPIO_8 3
#define PWR_BUTTON1__UART1_RX 4
#define PWR_BUTTON1__IIC4_SDA 5
#define PWR_BUTTON1__EPHY_SPD_LED 6
#define PWR_BUTTON1__WG2_D1 7
#define XTAL_XIN__PWR_XTAL_CLKIN 0
#define PWR_GPIO0__PWR_GPIO_0 0
#define PWR_GPIO0__UART2_TX 1
#define PWR_GPIO0__PWR_UART0_RX 2
#define PWR_GPIO0__PWM_8 4
#define PWR_GPIO1__PWR_GPIO_1 0
#define PWR_GPIO1__UART2_RX 1
#define PWR_GPIO1__EPHY_LNK_LED 3
#define PWR_GPIO1__PWM_9 4
#define PWR_GPIO1__PWR_IIC_SCL 5
#define PWR_GPIO1__IIC2_SCL 6
#define PWR_GPIO1__IIC0_SDA 7
#define PWR_GPIO2__PWR_GPIO_2 0
#define PWR_GPIO2__PWR_SECTICK 2
#define PWR_GPIO2__EPHY_SPD_LED 3
#define PWR_GPIO2__PWM_10 4
#define PWR_GPIO2__PWR_IIC_SDA 5
#define PWR_GPIO2__IIC2_SDA 6
#define PWR_GPIO2__IIC0_SCL 7
#define SD1_GPIO1__UART4_TX 1
#define SD1_GPIO1__PWR_GPIO_26 3
#define SD1_GPIO1__PWM_10 7
#define SD1_GPIO0__UART4_RX 1
#define SD1_GPIO0__PWR_GPIO_25 3
#define SD1_GPIO0__PWM_11 7
#define SD1_D3__PWR_SD1_D3 0
#define SD1_D3__SPI2_CS_X 1
#define SD1_D3__IIC1_SCL 2
#define SD1_D3__PWR_GPIO_18 3
#define SD1_D3__CAM_MCLK0 4
#define SD1_D3__UART3_CTS 5
#define SD1_D3__PWR_SPINOR1_CS_X 6
#define SD1_D3__PWM_4 7
#define SD1_D2__PWR_SD1_D2 0
#define SD1_D2__IIC1_SCL 1
#define SD1_D2__UART2_TX 2
#define SD1_D2__PWR_GPIO_19 3
#define SD1_D2__CAM_MCLK0 4
#define SD1_D2__UART3_TX 5
#define SD1_D2__PWR_SPINOR1_HOLD_X 6
#define SD1_D2__PWM_5 7
#define SD1_D1__PWR_SD1_D1 0
#define SD1_D1__IIC1_SDA 1
#define SD1_D1__UART2_RX 2
#define SD1_D1__PWR_GPIO_20 3
#define SD1_D1__CAM_MCLK1 4
#define SD1_D1__UART3_RX 5
#define SD1_D1__PWR_SPINOR1_WP_X 6
#define SD1_D1__PWM_6 7
#define SD1_D0__PWR_SD1_D0 0
#define SD1_D0__SPI2_SDI 1
#define SD1_D0__IIC1_SDA 2
#define SD1_D0__PWR_GPIO_21 3
#define SD1_D0__CAM_MCLK1 4
#define SD1_D0__UART3_RTS 5
#define SD1_D0__PWR_SPINOR1_MISO 6
#define SD1_D0__PWM_7 7
#define SD1_CMD__PWR_SD1_CMD 0
#define SD1_CMD__SPI2_SDO 1
#define SD1_CMD__IIC3_SCL 2
#define SD1_CMD__PWR_GPIO_22 3
#define SD1_CMD__CAM_VS0 4
#define SD1_CMD__EPHY_LNK_LED 5
#define SD1_CMD__PWR_SPINOR1_MOSI 6
#define SD1_CMD__PWM_8 7
#define SD1_CLK__PWR_SD1_CLK 0
#define SD1_CLK__SPI2_SCK 1
#define SD1_CLK__IIC3_SDA 2
#define SD1_CLK__PWR_GPIO_23 3
#define SD1_CLK__CAM_HS0 4
#define SD1_CLK__EPHY_SPD_LED 5
#define SD1_CLK__PWR_SPINOR1_SCK 6
#define SD1_CLK__PWM_9 7
#define PWM0_BUCK__PWM_0 0
#define PWM0_BUCK__XGPIOB_0 3
#define ADC1__XGPIOB_3 3
#define ADC1__KEY_COL2 4
#define ADC1__PWM_3 6
#define USB_VBUS_DET__USB_VBUS_DET 0
#define USB_VBUS_DET__XGPIOB_6 3
#define USB_VBUS_DET__CAM_MCLK0 4
#define USB_VBUS_DET__CAM_MCLK1 5
#define USB_VBUS_DET__PWM_4 6
#define MUX_SPI1_MISO__UART3_RTS 1
#define MUX_SPI1_MISO__IIC1_SDA 2
#define MUX_SPI1_MISO__XGPIOB_8 3
#define MUX_SPI1_MISO__PWM_9 4
#define MUX_SPI1_MISO__KEY_COL1 5
#define MUX_SPI1_MISO__SPI1_SDI 6
#define MUX_SPI1_MISO__DBG_14 7
#define MUX_SPI1_MOSI__UART3_RX 1
#define MUX_SPI1_MOSI__IIC1_SCL 2
#define MUX_SPI1_MOSI__XGPIOB_7 3
#define MUX_SPI1_MOSI__PWM_8 4
#define MUX_SPI1_MOSI__KEY_COL0 5
#define MUX_SPI1_MOSI__SPI1_SDO 6
#define MUX_SPI1_MOSI__DBG_13 7
#define MUX_SPI1_CS__UART3_CTS 1
#define MUX_SPI1_CS__CAM_MCLK0 2
#define MUX_SPI1_CS__XGPIOB_10 3
#define MUX_SPI1_CS__PWM_11 4
#define MUX_SPI1_CS__KEY_ROW3 5
#define MUX_SPI1_CS__SPI1_CS_X 6
#define MUX_SPI1_CS__DBG_16 7
#define MUX_SPI1_SCK__UART3_TX 1
#define MUX_SPI1_SCK__CAM_MCLK1 2
#define MUX_SPI1_SCK__XGPIOB_9 3
#define MUX_SPI1_SCK__PWM_10 4
#define MUX_SPI1_SCK__KEY_ROW2 5
#define MUX_SPI1_SCK__SPI1_SCK 6
#define MUX_SPI1_SCK__DBG_15 7
#define PAD_ETH_TXP__UART3_RX 1
#define PAD_ETH_TXP__IIC1_SCL 2
#define PAD_ETH_TXP__XGPIOB_25 3
#define PAD_ETH_TXP__PWM_13 4
#define PAD_ETH_TXP__CAM_MCLK0 5
#define PAD_ETH_TXP__SPI1_SDO 6
#define PAD_ETH_TXP__IIS2_LRCK 7
#define PAD_ETH_TXM__UART3_RTS 1
#define PAD_ETH_TXM__IIC1_SDA 2
#define PAD_ETH_TXM__XGPIOB_24 3
#define PAD_ETH_TXM__PWM_12 4
#define PAD_ETH_TXM__CAM_MCLK1 5
#define PAD_ETH_TXM__SPI1_SDI 6
#define PAD_ETH_TXM__IIS2_BCLK 7
#define PAD_ETH_RXP__UART3_TX 1
#define PAD_ETH_RXP__CAM_MCLK1 2
#define PAD_ETH_RXP__XGPIOB_27 3
#define PAD_ETH_RXP__PWM_15 4
#define PAD_ETH_RXP__CAM_HS0 5
#define PAD_ETH_RXP__SPI1_SCK 6
#define PAD_ETH_RXP__IIS2_DO 7
#define PAD_ETH_RXM__UART3_CTS 1
#define PAD_ETH_RXM__CAM_MCLK0 2
#define PAD_ETH_RXM__XGPIOB_26 3
#define PAD_ETH_RXM__PWM_14 4
#define PAD_ETH_RXM__CAM_VS0 5
#define PAD_ETH_RXM__SPI1_CS_X 6
#define PAD_ETH_RXM__IIS2_DI 7
#define GPIO_RTX__VI0_D_15 1
#define GPIO_RTX__XGPIOB_23 3
#define GPIO_RTX__PWM_1 4
#define GPIO_RTX__CAM_MCLK0 5
#define GPIO_RTX__IIS2_MCLK 7
#define PAD_MIPIRX4N__VI0_CLK 1
#define PAD_MIPIRX4N__IIC0_SCL 2
#define PAD_MIPIRX4N__XGPIOC_2 3
#define PAD_MIPIRX4N__IIC1_SDA 4
#define PAD_MIPIRX4N__CAM_MCLK0 5
#define PAD_MIPIRX4N__KEY_ROW0 6
#define PAD_MIPIRX4N__MUX_SPI1_SCK 7
#define PAD_MIPIRX4P__VI0_D_0 1
#define PAD_MIPIRX4P__IIC0_SDA 2
#define PAD_MIPIRX4P__XGPIOC_3 3
#define PAD_MIPIRX4P__IIC1_SCL 4
#define PAD_MIPIRX4P__CAM_MCLK1 5
#define PAD_MIPIRX4P__KEY_ROW1 6
#define PAD_MIPIRX4P__MUX_SPI1_CS 7
#define PAD_MIPIRX3N__VI0_D_1 1
#define PAD_MIPIRX3N__XGPIOC_4 3
#define PAD_MIPIRX3N__CAM_MCLK0 4
#define PAD_MIPIRX3N__MUX_SPI1_MISO 7
#define PAD_MIPIRX3P__VI0_D_2 1
#define PAD_MIPIRX3P__XGPIOC_5 3
#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7
#define PAD_MIPIRX2N__VI0_D_3 1
#define PAD_MIPIRX2N__XGPIOC_6 3
#define PAD_MIPIRX2N__IIC4_SCL 5
#define PAD_MIPIRX2N__DBG_6 7
#define PAD_MIPIRX2P__VI0_D_4 1
#define PAD_MIPIRX2P__XGPIOC_7 3
#define PAD_MIPIRX2P__IIC4_SDA 5
#define PAD_MIPIRX2P__DBG_7 7
#define PAD_MIPIRX1N__VI0_D_5 1
#define PAD_MIPIRX1N__XGPIOC_8 3
#define PAD_MIPIRX1N__KEY_ROW3 6
#define PAD_MIPIRX1N__DBG_8 7
#define PAD_MIPIRX1P__VI0_D_6 1
#define PAD_MIPIRX1P__XGPIOC_9 3
#define PAD_MIPIRX1P__IIC1_SDA 4
#define PAD_MIPIRX1P__KEY_ROW2 6
#define PAD_MIPIRX1P__DBG_9 7
#define PAD_MIPIRX0N__VI0_D_7 1
#define PAD_MIPIRX0N__XGPIOC_10 3
#define PAD_MIPIRX0N__IIC1_SCL 4
#define PAD_MIPIRX0N__CAM_MCLK1 5
#define PAD_MIPIRX0N__DBG_10 7
#define PAD_MIPIRX0P__VI0_D_8 1
#define PAD_MIPIRX0P__XGPIOC_11 3
#define PAD_MIPIRX0P__CAM_MCLK0 4
#define PAD_MIPIRX0P__DBG_11 7
#define PAD_MIPI_TXM2__VI0_D_13 1
#define PAD_MIPI_TXM2__IIC0_SDA 2
#define PAD_MIPI_TXM2__XGPIOC_16 3
#define PAD_MIPI_TXM2__IIC1_SDA 4
#define PAD_MIPI_TXM2__PWM_8 5
#define PAD_MIPI_TXM2__SPI0_SCK 6
#define PAD_MIPI_TXP2__VI0_D_14 1
#define PAD_MIPI_TXP2__IIC0_SCL 2
#define PAD_MIPI_TXP2__XGPIOC_17 3
#define PAD_MIPI_TXP2__IIC1_SCL 4
#define PAD_MIPI_TXP2__PWM_9 5
#define PAD_MIPI_TXP2__SPI0_CS_X 6
#define PAD_MIPI_TXP2__IIS1_MCLK 7
#define PAD_MIPI_TXM1__SPI3_SDO 0
#define PAD_MIPI_TXM1__VI0_D_11 1
#define PAD_MIPI_TXM1__IIS1_LRCK 2
#define PAD_MIPI_TXM1__XGPIOC_14 3
#define PAD_MIPI_TXM1__IIC2_SDA 4
#define PAD_MIPI_TXM1__PWM_10 5
#define PAD_MIPI_TXM1__SPI0_SDO 6
#define PAD_MIPI_TXM1__DBG_14 7
#define PAD_MIPI_TXP1__SPI3_SDI 0
#define PAD_MIPI_TXP1__VI0_D_12 1
#define PAD_MIPI_TXP1__IIS1_DO 2
#define PAD_MIPI_TXP1__XGPIOC_15 3
#define PAD_MIPI_TXP1__IIC2_SCL 4
#define PAD_MIPI_TXP1__PWM_11 5
#define PAD_MIPI_TXP1__SPI0_SDI 6
#define PAD_MIPI_TXP1__DBG_15 7
#define PAD_MIPI_TXM0__SPI3_SCK 0
#define PAD_MIPI_TXM0__VI0_D_9 1
#define PAD_MIPI_TXM0__IIS1_DI 2
#define PAD_MIPI_TXM0__XGPIOC_12 3
#define PAD_MIPI_TXM0__CAM_MCLK1 4
#define PAD_MIPI_TXM0__PWM_14 5
#define PAD_MIPI_TXM0__CAM_VS0 6
#define PAD_MIPI_TXM0__DBG_12 7
#define PAD_MIPI_TXP0__SPI3_CS_X 0
#define PAD_MIPI_TXP0__VI0_D_10 1
#define PAD_MIPI_TXP0__IIS1_BCLK 2
#define PAD_MIPI_TXP0__XGPIOC_13 3
#define PAD_MIPI_TXP0__CAM_MCLK0 4
#define PAD_MIPI_TXP0__PWM_15 5
#define PAD_MIPI_TXP0__CAM_HS0 6
#define PAD_MIPI_TXP0__DBG_13 7
#define PKG_TYPE0__PKG_TYPE0 0
#define PKG_TYPE1__PKG_TYPE1 0
#define PKG_TYPE2__PKG_TYPE2 0
#define PAD_AUD_AINL_MIC__XGPIOC_23 3
#define PAD_AUD_AINL_MIC__IIS1_BCLK 4
#define PAD_AUD_AINL_MIC__IIS2_BCLK 5
#define PAD_AUD_AINR_MIC__XGPIOC_22 3
#define PAD_AUD_AINR_MIC__IIS1_DO 4
#define PAD_AUD_AINR_MIC__IIS2_DI 5
#define PAD_AUD_AINR_MIC__IIS1_DI 6
#define PAD_AUD_AOUTL__XGPIOC_25 3
#define PAD_AUD_AOUTL__IIS1_LRCK 4
#define PAD_AUD_AOUTL__IIS2_LRCK 5
#define PAD_AUD_AOUTR__XGPIOC_24 3
#define PAD_AUD_AOUTR__IIS1_DI 4
#define PAD_AUD_AOUTR__IIS2_DO 5
#define PAD_AUD_AOUTR__IIS1_DO 6
#endif /* __CV180X_PINLIST_SWCONFIG_H__ */

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#ifndef __CV180X_REG_H__
#define __CV180X_REG_H__
#define TOP_BASE 0x03000000
#define PINMUX_BASE (TOP_BASE + 0x1000)
#define WATCHDOG_BASE (TOP_BASE + 0x00010000)
#define RTC_BASE 0x05026000
/*
* RTC info registers
*/
#define RTC_INFO0 (RTC_BASE + 0x1C)
/*
* General purpose registers
*/
#define GP_REG0 (TOP_BASE + 0x80)
#define GP_REG1 (TOP_BASE + 0x84)
#define GP_REG2 (TOP_BASE + 0x88
#define GP_REG3 (TOP_BASE + 0x8C)
#define GP_REG4 (TOP_BASE + 0x90)
#define GP_REG5 (TOP_BASE + 0x94)
#define GP_REG6 (TOP_BASE + 0x98)
#define GP_REG7 (TOP_BASE + 0x9C)
#define GP_REG8 (TOP_BASE + 0xA0)
#define GP_REG9 (TOP_BASE + 0xA4)
#define GP_REG10 (TOP_BASE + 0xA8)
/*
* Pinmux definitions
*/
#define PINMUX_UART0 0
#define PINMUX_UART1 1
#define PINMUX_UART2 2
#define PINMUX_UART3 3
#define PINMUX_UART3_2 4
#define PINMUX_I2C0 5
#define PINMUX_I2C1 6
#define PINMUX_I2C2 7
#define PINMUX_I2C3 8
#define PINMUX_I2C4 9
#define PINMUX_I2C4_2 10
#define PINMUX_SPI0 11
#define PINMUX_SPI1 12
#define PINMUX_SPI2 13
#define PINMUX_SPI2_2 14
#define PINMUX_SPI3 15
#define PINMUX_SPI3_2 16
#define PINMUX_I2S0 17
#define PINMUX_I2S1 18
#define PINMUX_I2S2 19
#define PINMUX_I2S3 20
#define PINMUX_USBID 21
#define PINMUX_SDIO0 22
#define PINMUX_SDIO1 23
#define PINMUX_ND 24
#define PINMUX_EMMC 25
#define PINMUX_SPI_NOR 26
#define PINMUX_SPI_NAND 27
#define PINMUX_CAM0 28
#define PINMUX_CAM1 29
#define PINMUX_PCM0 30
#define PINMUX_PCM1 31
#define PINMUX_CSI0 32
#define PINMUX_CSI1 33
#define PINMUX_CSI2 34
#define PINMUX_DSI 35
#define PINMUX_VI0 36
#define PINMUX_VO 37
#define PINMUX_RMII1 38
#define PINMUX_EPHY_LED 39
#define PINMUX_I80 40
#define PINMUX_LVDS 41
#define PINMUX_USB 42
#define PINMUX_USB_VBUS_DET (PINMUX_BASE + 0x108)
#define REG_TOP_USB_ECO (TOP_BASE + 0xB4)
#define BIT_TOP_USB_ECO_RX_FLUSH 0x80
/* rst */
#define REG_TOP_SOFT_RST 0x3000
#define BIT_TOP_SOFT_RST_USB BIT(11)
#define BIT_TOP_SOFT_RST_SDIO BIT(14)
#define BIT_TOP_SOFT_RST_NAND BIT(12)
#define REG_TOP_USB_CTRSTS (TOP_BASE + 0x38)
#define REG_TOP_CONF_INFO (TOP_BASE + 0x4)
#define BIT_TOP_CONF_INFO_VBUS BIT(9)
#define REG_TOP_USB_PHY_CTRL (TOP_BASE + 0x48)
#define BIT_TOP_USB_PHY_CTRL_EXTVBUS BIT(0)
#define USB_PHY_ID_OVERRIDE_ENABLE BIT(6)
#define USB_PHY_ID_VALUE BIT(7)
#define REG_TOP_DDR_ADDR_MODE (TOP_BASE + 0x64)
/* irq */
#define IRQ_LEVEL 0
#define IRQ_EDGE 3
/* usb */
#define USB_BASE 0x04340000
/* ethernet phy */
#define ETH_PHY_BASE 0x03009000
#define ETH_PHY_INIT_MASK 0xFFFFFFF9
#define ETH_PHY_SHUTDOWN BIT(1)
#define ETH_PHY_POWERUP 0xFFFFFFFD
#define ETH_PHY_RESET 0xFFFFFFFB
#define ETH_PHY_RESET_N BIT(2)
#define ETH_PHY_LED_LOW_ACTIVE BIT(3)
/* watchdog */
#define CONFIG_DW_WDT_BASE WATCHDOG_BASE
#define CONFIG_DW_WDT_CLOCK_KHZ 25000
#define DW_WDT_CR 0x00
#define DW_WDT_TORR 0x04
#define DW_WDT_CRR 0x0C
#define DW_WDT_CR_EN_OFFSET 0x00
#define DW_WDT_CR_RMOD_OFFSET 0x01
#define DW_WDT_CR_RMOD_VAL 0x00
#define DW_WDT_CRR_RESTART_VAL 0x76
/* SDIO Wifi */
#define WIFI_CHIP_EN_BGA BIT(18)
#define WIFI_CHIP_EN_QFN BIT(2)
/* RTC */
#define RTC_SYS_BASE 0x05000000
#define RTC_MACRO_BASE (RTC_SYS_BASE + 0x00026400)
#define RTC_MACRO_DA_SOC_READY 0x8C
#define RTC_MACRO_RO_T 0xA8
#define RTC_CORE_SRAM_BASE (RTC_SYS_BASE + 0x00026800)
#define RTC_CORE_SRAM_SIZE 0x0800 // 2KB
#define REG_RTC_CTRL_BASE (RTC_SYS_BASE + 0x00025000)
#define RTC_CTRL0_UNLOCKKEY 0x4
#define RTC_CTRL0 0x8
#define RTC_CTRL0_STATUS0 0xC
#define RTCSYS_RST_CTRL 0x18
#define REG_RTC_BASE (RTC_SYS_BASE + 0x00026000)
#define RTC_EN_PWR_WAKEUP 0xBC
#define RTC_EN_SHDN_REQ 0xC0
#define RTC_EN_PWR_CYC_REQ 0xC8
#define RTC_EN_WARM_RST_REQ 0xCC
#define RTC_EN_WDT_RST_REQ 0xE0
#define RTC_EN_SUSPEND_REQ 0xE4
#define RTC_PG_REG 0xF0
#define RTC_ST_ON_REASON 0xF8
#define REG_RTC_ST_ON_REASON (REG_RTC_BASE + RTC_ST_ON_REASON)
#define RTCSYS_F32KLESS_BASE (RTC_SYS_BASE + 0x0002A000)
#define RTC_INTERNAL_32K 0
#define RTC_EXTERNAL_32K 1
/* eFuse */
#define EFUSE_BASE (TOP_BASE + 0x00050000)
/* AXI SRAM */
#define AXI_SRAM_BASE 0x0E000000
#define AXI_SRAM_SIZE 0x40
#define EFUSE_SW_INFO_ADDR (AXI_SRAM_BASE)
#define EFUSE_SW_INFO_SIZE 4
#define BOOT_SOURCE_FLAG_ADDR (EFUSE_SW_INFO_ADDR + EFUSE_SW_INFO_SIZE)
#define BOOT_SOURCE_FLAG_SIZE 4
#define MAGIC_NUM_USB_DL 0x4D474E31 // MGN1
#define MAGIC_NUM_SD_DL 0x4D474E32 // MGN2
#define BOOT_LOG_LEN_ADDR (BOOT_SOURCE_FLAG_ADDR + BOOT_SOURCE_FLAG_SIZE) // 0x0E000008
#define BOOT_LOG_LEN_SIZE 4
#define TIME_RECORDS_ADDR (AXI_SRAM_BASE + 0x10) // 0x0E000010
/* from fsbl/plat/cv180x/include/platform_def.h struct _time_records { ... } */
#define TIME_RECORDS_FIELD_UBOOT_START (TIME_RECORDS_ADDR + 0x10)
#define TIME_RECORDS_FIELD_BOOTCMD_START (TIME_RECORDS_ADDR + 0x12)
#define TIME_RECORDS_FIELD_DECOMPRESS_KERNEL_START (TIME_RECORDS_ADDR + 0x14)
#define TIME_RECORDS_FIELD_KERNEL_START (TIME_RECORDS_ADDR + 0x16)
#endif /* __CV180X_REG_H__ */

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// $Module: fmux_gpio $
// $RegisterBank Version: V 1.0.00 $
// $Author: ghost $
// $Date: Thu, 17 Mar 2022 04:53:31 PM $
//
//GEN REG ADDR/OFFSET/MASK
#ifndef __CV180X_REG_FMUX_GPIO_H__
#define __CV180X_REG_FMUX_GPIO_H__
#define FMUX_GPIO_REG_IOCTRL_SD0_CLK 0x0
#define FMUX_GPIO_REG_IOCTRL_SD0_CMD 0x4
#define FMUX_GPIO_REG_IOCTRL_SD0_D0 0x8
#define FMUX_GPIO_REG_IOCTRL_SD0_D1 0xc
#define FMUX_GPIO_REG_IOCTRL_SD0_D2 0x10
#define FMUX_GPIO_REG_IOCTRL_SD0_D3 0x14
#define FMUX_GPIO_REG_IOCTRL_SD0_CD 0x18
#define FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN 0x1c
#define FMUX_GPIO_REG_IOCTRL_SPK_EN 0x20
#define FMUX_GPIO_REG_IOCTRL_UART0_TX 0x24
#define FMUX_GPIO_REG_IOCTRL_UART0_RX 0x28
#define FMUX_GPIO_REG_IOCTRL_SPINOR_HOLD_X 0x2c
#define FMUX_GPIO_REG_IOCTRL_SPINOR_SCK 0x30
#define FMUX_GPIO_REG_IOCTRL_SPINOR_MOSI 0x34
#define FMUX_GPIO_REG_IOCTRL_SPINOR_WP_X 0x38
#define FMUX_GPIO_REG_IOCTRL_SPINOR_MISO 0x3c
#define FMUX_GPIO_REG_IOCTRL_SPINOR_CS_X 0x40
#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS 0x44
#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK 0x48
#define FMUX_GPIO_REG_IOCTRL_IIC0_SCL 0x4c
#define FMUX_GPIO_REG_IOCTRL_IIC0_SDA 0x50
#define FMUX_GPIO_REG_IOCTRL_AUX0 0x54
#define FMUX_GPIO_REG_IOCTRL_GPIO_ZQ 0x58
#define FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET 0x5c
#define FMUX_GPIO_REG_IOCTRL_PWR_RSTN 0x60
#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ1 0x64
#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ2 0x68
#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0 0x6c
#define FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1 0x70
#define FMUX_GPIO_REG_IOCTRL_XTAL_XIN 0x74
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO0 0x78
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO1 0x7c
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO2 0x80
#define FMUX_GPIO_REG_IOCTRL_SD1_GPIO1 0x84
#define FMUX_GPIO_REG_IOCTRL_SD1_GPIO0 0x88
#define FMUX_GPIO_REG_IOCTRL_SD1_D3 0x8c
#define FMUX_GPIO_REG_IOCTRL_SD1_D2 0x90
#define FMUX_GPIO_REG_IOCTRL_SD1_D1 0x94
#define FMUX_GPIO_REG_IOCTRL_SD1_D0 0x98
#define FMUX_GPIO_REG_IOCTRL_SD1_CMD 0x9c
#define FMUX_GPIO_REG_IOCTRL_SD1_CLK 0xa0
#define FMUX_GPIO_REG_IOCTRL_PWM0_BUCK 0xa4
#define FMUX_GPIO_REG_IOCTRL_ADC1 0xa8
#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET 0xac
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO 0xb0
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI 0xb4
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS 0xb8
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK 0xbc
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP 0xc0
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM 0xc4
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP 0xc8
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM 0xcc
#define FMUX_GPIO_REG_IOCTRL_GPIO_RTX 0xd0
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N 0xd4
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P 0xd8
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N 0xdc
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P 0xe0
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N 0xe4
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P 0xe8
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N 0xec
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P 0xf0
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N 0xf4
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P 0xf8
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2 0xfc
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2 0x100
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1 0x104
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1 0x108
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0 0x10c
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0 0x110
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE0 0x114
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE1 0x118
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE2 0x11c
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC 0x120
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC 0x124
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL 0x128
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR 0x12c
#define FMUX_GPIO_REG_DEVMATRIX_UART0_IP_SEL 0x1d4
#define FMUX_GPIO_REG_DEVMATRIX_UART1_IP_SEL 0x1d8
#define FMUX_GPIO_REG_DEVMATRIX_UART2_IP_SEL 0x1dc
#define FMUX_GPIO_REG_DEVMATRIX_UART3_IP_SEL 0x1e0
#define FMUX_GPIO_REG_DEVMATRIX_UART4_IP_SEL 0x1e4
#define FMUX_GPIO_FUNCSEL_SD0_CLK 0x0
#define FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_CMD 0x4
#define FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CMD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D0 0x8
#define FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D1 0xc
#define FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D2 0x10
#define FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D3 0x14
#define FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_CD 0x18
#define FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN 0x1c
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPK_EN 0x20
#define FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPK_EN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART0_TX 0x24
#define FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART0_TX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART0_RX 0x28
#define FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART0_RX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X 0x2c
#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_SCK 0x30
#define FMUX_GPIO_FUNCSEL_SPINOR_SCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_SCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI 0x34
#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X 0x38
#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_MISO 0x3c
#define FMUX_GPIO_FUNCSEL_SPINOR_MISO_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_MISO_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X 0x40
#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X_MASK 0x7
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS 0x44
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK 0x48
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC0_SCL 0x4c
#define FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC0_SDA 0x50
#define FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK 0x7
#define FMUX_GPIO_FUNCSEL_AUX0 0x54
#define FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_AUX0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ 0x58
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET 0x5c
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_RSTN 0x60
#define FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1 0x64
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2 0x68
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0 0x6c
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1 0x70
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_XTAL_XIN 0x74
#define FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0 0x78
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1 0x7c
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2 0x80
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_GPIO1 0x84
#define FMUX_GPIO_FUNCSEL_SD1_GPIO1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_GPIO1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_GPIO0 0x88
#define FMUX_GPIO_FUNCSEL_SD1_GPIO0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_GPIO0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D3 0x8c
#define FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D2 0x90
#define FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D1 0x94
#define FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D0 0x98
#define FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_CMD 0x9c
#define FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_CMD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_CLK 0xa0
#define FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK 0xa4
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_ADC1 0xa8
#define FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_ADC1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET 0xac
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO 0xb0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI 0xb4
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS 0xb8
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK 0xbc
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP 0xc0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM 0xc4
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP 0xc8
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM 0xcc
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK 0x7
#define FMUX_GPIO_FUNCSEL_GPIO_RTX 0xd0
#define FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N 0xd4
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P 0xd8
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N 0xdc
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P 0xe0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N 0xe4
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P 0xe8
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N 0xec
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P 0xf0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N 0xf4
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P 0xf8
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2 0xfc
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2 0x100
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1 0x104
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1 0x108
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0 0x10c
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0 0x110
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0 0x114
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1 0x118
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2 0x11c
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC 0x120
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC 0x124
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL 0x128
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR 0x12c
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK 0x7
#define FMUX_GPIO_MUX_UART0_IP_SEL 0x1d4
#define FMUX_GPIO_MUX_UART0_IP_SEL_OFFSET 0
#define FMUX_GPIO_MUX_UART0_IP_SEL_MASK 0x7
#define FMUX_GPIO_MUX_UART1_IP_SEL 0x1d8
#define FMUX_GPIO_MUX_UART1_IP_SEL_OFFSET 0
#define FMUX_GPIO_MUX_UART1_IP_SEL_MASK 0x7
#define FMUX_GPIO_MUX_UART2_IP_SEL 0x1dc
#define FMUX_GPIO_MUX_UART2_IP_SEL_OFFSET 0
#define FMUX_GPIO_MUX_UART2_IP_SEL_MASK 0x7
#define FMUX_GPIO_MUX_UART3_IP_SEL 0x1e0
#define FMUX_GPIO_MUX_UART3_IP_SEL_OFFSET 0
#define FMUX_GPIO_MUX_UART3_IP_SEL_MASK 0x7
#define FMUX_GPIO_MUX_UART4_IP_SEL 0x1e4
#define FMUX_GPIO_MUX_UART4_IP_SEL_OFFSET 0
#define FMUX_GPIO_MUX_UART4_IP_SEL_MASK 0x7
#endif /* __CV180X_REG_FMUX_GPIO_H__ */

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u-boot-2021.10/board/cvitek/cv180x/sdhci_reg.h Normal file
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#ifndef _SDHCI_REG_H
#define _SDHCI_REG_H
#include "cv180x_reg.h"
#define REG_TOP_SD_PWRSW_CTRL (0x1F4)
#define REG_SDIO0_PAD_MASK (0xFFFFFFF3)
#define REG_SDIO0_PAD_SHIFT (2)
#define REG_SDIO0_PAD_CLR_MASK (0xC)
#define REG_SDIO0_CD_PAD_REG (PINMUX_BASE + 0x900)
#define REG_SDIO0_CD_PAD_VALUE (1)
#define REG_SDIO0_CD_PAD_RESET (1)
#define REG_SDIO0_PWR_EN_PAD_REG (PINMUX_BASE + 0x904)
#define REG_SDIO0_PWR_EN_PAD_VALUE (2)
#define REG_SDIO0_PWR_EN_PAD_RESET (2)
#define REG_SDIO0_CLK_PAD_REG (PINMUX_BASE + 0xA00)
#define REG_SDIO0_CLK_PAD_VALUE (2)
#define REG_SDIO0_CLK_PAD_RESET (2)
#define REG_SDIO0_CMD_PAD_REG (PINMUX_BASE + 0xA04)
#define REG_SDIO0_CMD_PAD_VALUE (1)
#define REG_SDIO0_CMD_PAD_RESET (2)
#define REG_SDIO0_DAT0_PAD_REG (PINMUX_BASE + 0xA08)
#define REG_SDIO0_DAT0_PAD_VALUE (1)
#define REG_SDIO0_DAT0_PAD_RESET (2)
#define REG_SDIO0_DAT1_PAD_REG (PINMUX_BASE + 0xA0C)
#define REG_SDIO0_DAT1_PAD_VALUE (1)
#define REG_SDIO0_DAT1_PAD_RESET (2)
#define REG_SDIO0_DAT2_PAD_REG (PINMUX_BASE + 0xA10)
#define REG_SDIO0_DAT2_PAD_VALUE (1)
#define REG_SDIO0_DAT2_PAD_RESET (2)
#define REG_SDIO0_DAT3_PAD_REG (PINMUX_BASE + 0xA14)
#define REG_SDIO0_DAT3_PAD_VALUE (1)
#define REG_SDIO0_DAT3_PAD_RESET (2)
#define PAD_SDIO0_CD_REG (PINMUX_BASE + 0x18)
#define PAD_SDIO0_PWR_EN_REG (PINMUX_BASE + 0x1C)
#define PAD_SDIO0_CLK_REG (PINMUX_BASE + 0x0)
#define PAD_SDIO0_CMD_REG (PINMUX_BASE + 0x4)
#define PAD_SDIO0_D0_REG (PINMUX_BASE + 0x8)
#define PAD_SDIO0_D1_REG (PINMUX_BASE + 0xC)
#define PAD_SDIO0_D2_REG (PINMUX_BASE + 0x10)
#define PAD_SDIO0_D3_REG (PINMUX_BASE + 0x14)
#define REG_SDIO1_PAD_MASK (0xFFFFFFF3)
#define REG_SDIO1_PAD_SHIFT (2)
#define SDIO1_PAD_BASE 0x05027000
#define REG_SDIO1_PAD_CLR_MASK (0xC)
#define REG_SDIO1_CLK_PAD_REG (SDIO1_PAD_BASE + 0x06C)
#define REG_SDIO1_CLK_PAD_VALUE (2)
#define REG_SDIO1_CMD_PAD_REG (SDIO1_PAD_BASE + 0x068)
#define REG_SDIO1_CMD_PAD_VALUE (1)
#define REG_SDIO1_DAT0_PAD_REG (SDIO1_PAD_BASE + 0x064)
#define REG_SDIO1_DAT0_PAD_VALUE (1)
#define REG_SDIO1_DAT2_PAD_REG (SDIO1_PAD_BASE + 0x05C)
#define REG_SDIO1_DAT2_PAD_VALUE (1)
#define REG_SDIO1_DAT1_PAD_REG (SDIO1_PAD_BASE + 0x060)
#define REG_SDIO1_DAT1_PAD_VALUE (1)
#define REG_SDIO1_DAT3_PAD_REG (SDIO1_PAD_BASE + 0x058)
#define REG_SDIO1_DAT3_PAD_VALUE (1)
#define REG_EMMC_PAD_CLR_MASK (0xC)
#define REG_EMMC_PAD_SHIFT (2)
#define REG_EMMC_RSTN_PAD_REG (PINMUX_BASE + 0x914)
#define REG_EMMC_RSTN_PAD_VALUE (1)
#define REG_EMMC_CLK_PAD_REG (PINMUX_BASE + 0x91c)
#define REG_EMMC_CLK_PAD_VALUE (2)
#define REG_EMMC_CMD_PAD_REG (PINMUX_BASE + 0x928)
#define REG_EMMC_CMD_PAD_VALUE (1)
#define REG_EMMC_DAT0_PAD_REG (PINMUX_BASE + 0x920)
#define REG_EMMC_DAT0_PAD_VALUE (1)
#define REG_EMMC_DAT1_PAD_REG (PINMUX_BASE + 0x92C)
#define REG_EMMC_DAT1_PAD_VALUE (1)
#define REG_EMMC_DAT2_PAD_REG (PINMUX_BASE + 0x918)
#define REG_EMMC_DAT2_PAD_VALUE (1)
#define REG_EMMC_DAT3_PAD_REG (PINMUX_BASE + 0x924)
#define REG_EMMC_DAT3_PAD_VALUE (1)
#define CVI_SDHCI_VENDOR_OFFSET 0x200
#define CVI_SDHCI_PHY_TX_RX_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_PHY_DS_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x44)
#define CVI_SDHCI_PHY_DLY_STS (CVI_SDHCI_VENDOR_OFFSET + 0x48)
#define CVI_SDHCI_PHY_CONFIG (CVI_SDHCI_VENDOR_OFFSET + 0x4C)
#define CVI_SDHCI_BIT_CLK_FREE_EN 2
#define CVI_SDHCI_CLK_FREE_EN_VALUE 0
#define CVI_SDHCI_CLK_FREE_EN_MASK 0xFFFFFFFB
#define CVI_SDHCI_VENDOR_MSHC_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x0)
#define CVI_SDHCI_PHY_RX_DLY_SHIFT 16
// Bit 16~22
#define CVI_SDHCI_PHY_RX_DLY_MASK 0x7F0000
#define CVI_SDHCI_PHY_TX_RX_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_PHY_RX_SRC_BIT_1 24
#define CVI_SDHCI_PHY_RX_SRC_BIT_2 25
#define SDHCI_PHY_CONFIG \
(CVI_SDHCI_VENDOR_OFFSET + \
0x4C) // P_VERDOR_SPECIFIC_AREA + 0x4c0x24c( PHY_TX_BPS )
#define REG_TX_BPS_SEL_MASK 0xFFFFFFFE
#define REG_TX_BPS_SEL_CLR_MASK (0x1) // 0x24c PHY_TX_BPS
#define REG_TX_BPS_SEL_SHIFT (0) // 0x24c PHY_TX_BPS
#define REG_TX_BPS_SEL_BYPASS (1) // 0x24c PHY_TX_BPS inv
#define MMC_MAX_CLOCK (375000000)
#define MMC_MAX_CLOCK_DIV_VALUE (0x40009)
#define CLOCK_BYPASS_SELECT_REGISTER (0x3002030)
#define MAX_TUNING_CMD_RETRY_COUNT 50
#define TUNE_MAX_PHCODE 128
#define TAP_WINDOW_THLD 20
#endif

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if TARGET_CVITEK_CV181X
choice
prompt "Cvitek CV181X verification platform type select"
config TARGET_CVITEK_CV181X_ASIC
bool "ASIC"
help
This enables support for Cvitek's CV181X SoC on ASIC platform.
If unsure, say N.
config TARGET_CVITEK_CV181X_PALLADIUM
bool "Palladium"
help
This enables support for Cvitek's CV181X SoC on PALLADIUM platform.
If unsure, say N.
config TARGET_CVITEK_CV181X_FPGA
bool "FPGA"
help
This enables support for Cvitek's CV181X SoC on FPGA platform.
If unsure, say N.
endchoice
config SYS_BOARD
default "cv181x"
config SYS_VENDOR
default "cvitek"
config SYS_CPU
default "generic"
config SYS_CONFIG_NAME
default "cv181x-asic" if TARGET_CVITEK_CV181X_ASIC
default "cv181x-palladium" if TARGET_CVITEK_CV181X_PALLADIUM
default "cv181x-fpga" if TARGET_CVITEK_CV181X_FPGA
config CVITEK_SPI_FLASH
bool
prompt "Support CVITEK SPINOR"
select SPI_FLASH
select DM
select DM_SPI
select DM_SPI_FLASH
select SPI_MEM
select CMD_SF
select CVI_SPIF
config ENV_SIZE
default 0x10000 if ENV_IS_IN_SPI_FLASH
default 0x20000 if ENV_IS_IN_MMC
default 0x20000 if ENV_IS_IN_NAND
config ENV_SECT_SIZE
default 0x10000 if ENV_IS_IN_SPI_FLASH
default 0x40000 if ENV_IS_IN_MMC
default 0x20000 if ENV_IS_IN_NAND
config ENV_OFFSET
default 0x3A0000 if ENV_IS_IN_SPI_FLASH
default 0x880000 if ENV_IS_IN_MMC
default 0xae0000 if ENV_IS_IN_NAND
config ENV_OFFSET_REDUND
default 0x3B0000 if ENV_IS_IN_SPI_FLASH
default 0xb00000 if ENV_IS_IN_NAND
endif

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CV1822 BOARD
M: Myles Tsai <myles.tsai@wisecore.com.tw>
S: Maintained
F: board/armltd/vexpress64/

2
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obj-y := board.o

286
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/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
* Sharma Bhupesh <bhupesh.sharma@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <errno.h>
#include <asm/io.h>
#include <linux/compiler.h>
#if defined(__aarch64__)
#include <asm/armv8/mmu.h>
#endif
#include <usb/dwc2_udc.h>
#include <usb.h>
#include "cv181x_reg.h"
#include "mmio.h"
#include "cv181x_reg_fmux_gpio.h"
#include "cv181x_pinlist_swconfig.h"
#include <linux/delay.h>
#include <bootstage.h>
#if defined(__riscv)
#include <asm/csr.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define SD1_SDIO_PAD
#if defined(__aarch64__)
static struct mm_region cv181x_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = PHYS_SDRAM_1,
.phys = PHYS_SDRAM_1,
.size = PHYS_SDRAM_1_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = cv181x_mem_map;
#endif
// #define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) printf ("%s\n", PIN_NAME ##_ ##FUNC_NAME);
#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \
FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK << FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET, \
PIN_NAME##__##FUNC_NAME)
void pinmux_config(int io_type)
{
switch (io_type) {
case PINMUX_UART0:
PINMUX_CONFIG(UART0_RX, UART0_RX);
PINMUX_CONFIG(UART0_TX, UART0_TX);
break;
case PINMUX_SDIO0:
PINMUX_CONFIG(SD0_CD, SDIO0_CD);
PINMUX_CONFIG(SD0_PWR_EN, SDIO0_PWR_EN);
PINMUX_CONFIG(SD0_CMD, SDIO0_CMD);
PINMUX_CONFIG(SD0_CLK, SDIO0_CLK);
PINMUX_CONFIG(SD0_D0, SDIO0_D_0);
PINMUX_CONFIG(SD0_D1, SDIO0_D_1);
PINMUX_CONFIG(SD0_D2, SDIO0_D_2);
PINMUX_CONFIG(SD0_D3, SDIO0_D_3);
break;
case PINMUX_SDIO1:
#if defined(SD1_SDIO_PAD)
/*
* Name Address SD1 MIPI
* reg_sd1_phy_sel REG_0x300_0294[10] 0x0 0x1
*/
mmio_write_32(TOP_BASE + 0x294,
(mmio_read_32(TOP_BASE + 0x294) & 0xFFFFFBFF));
PINMUX_CONFIG(SD1_CMD, PWR_SD1_CMD_VO36);
PINMUX_CONFIG(SD1_CLK, PWR_SD1_CLK_VO37);
PINMUX_CONFIG(SD1_D0, PWR_SD1_D0_VO35);
PINMUX_CONFIG(SD1_D1, PWR_SD1_D1_VO34);
PINMUX_CONFIG(SD1_D2, PWR_SD1_D2_VO33);
PINMUX_CONFIG(SD1_D3, PWR_SD1_D3_VO32);
#elif defined(SD1_MIPI_PAD)
/*
* Name Address SD1 MIPI
* reg_sd1_phy_sel REG_0x300_0294[10] 0x0 0x1
*/
mmio_write_32(TOP_BASE + 0x294,
(mmio_read_32(TOP_BASE + 0x294) & 0xFFFFFBFF) | BIT(10));
PINMUX_CONFIG(PAD_MIPI_TXM4, SD1_CLK);
PINMUX_CONFIG(PAD_MIPI_TXP4, SD1_CMD);
PINMUX_CONFIG(PAD_MIPI_TXM3, SD1_D0);
PINMUX_CONFIG(PAD_MIPI_TXP3, SD1_D1);
PINMUX_CONFIG(PAD_MIPI_TXM2, SD1_D2);
PINMUX_CONFIG(PAD_MIPI_TXP2, SD1_D3);
#endif
break;
case PINMUX_EMMC:
PINMUX_CONFIG(EMMC_CLK, EMMC_CLK);
PINMUX_CONFIG(EMMC_RSTN, EMMC_RSTN);
PINMUX_CONFIG(EMMC_CMD, EMMC_CMD);
PINMUX_CONFIG(EMMC_DAT1, EMMC_DAT_1);
PINMUX_CONFIG(EMMC_DAT0, EMMC_DAT_0);
PINMUX_CONFIG(EMMC_DAT2, EMMC_DAT_2);
PINMUX_CONFIG(EMMC_DAT3, EMMC_DAT_3);
break;
case PINMUX_SPI_NAND:
PINMUX_CONFIG(EMMC_DAT2, SPINAND_HOLD);
PINMUX_CONFIG(EMMC_CLK, SPINAND_CLK);
PINMUX_CONFIG(EMMC_DAT0, SPINAND_MOSI);
PINMUX_CONFIG(EMMC_DAT3, SPINAND_WP);
PINMUX_CONFIG(EMMC_CMD, SPINAND_MISO);
PINMUX_CONFIG(EMMC_DAT1, SPINAND_CS);
break;
default:
break;
}
}
#include "../cvi_board_init.c"
#if defined(CONFIG_PHY_CVITEK_CV182XA) /* config cvitek cv182xa eth internal phy on ASIC board */
static void cv182xa_ephy_id_init(void)
{
// set rg_ephy_apb_rw_sel 0x0804@[0]=1/APB by using APB interface
mmio_write_32(0x03009804, 0x0001);
// Release 0x0800[0]=0/shutdown
mmio_write_32(0x03009800, 0x0900);
// Release 0x0800[2]=1/dig_rst_n, Let mii_reg can be accessabile
mmio_write_32(0x03009800, 0x0904);
// PHY_ID
mmio_write_32(0x03009008, 0x0043);
mmio_write_32(0x0300900c, 0x5649);
// switch to MDIO control by ETH_MAC
mmio_write_32(0x03009804, 0x0000);
}
#endif
void cpu_pwr_ctrl(void)
{
#if defined(CONFIG_RISCV)
mmio_write_32(0x01901008, 0x30001);// cortexa53_pwr_iso_en
#elif defined(CONFIG_ARM)
mmio_write_32(0x01901004, 0x30001);// c906_top_pwr_iso_en
#endif
}
int board_init(void)
{
extern volatile uint32_t BOOT0_START_TIME;
uint16_t start_time = DIV_ROUND_UP(BOOT0_START_TIME, SYS_COUNTER_FREQ_IN_SECOND / 1000);
// Save uboot start time. time is from boot0.h
mmio_write_16(TIME_RECORDS_FIELD_UBOOT_START, start_time);
cpu_pwr_ctrl();
#if defined(CONFIG_PHY_CVITEK_CV182XA) /* config cvitek cv182xa eth internal phy on ASIC board */
cv182xa_ephy_id_init();
#endif
#if defined(CONFIG_NAND_SUPPORT)
pinmux_config(PINMUX_SPI_NAND);
#elif defined(CONFIG_SPI_FLASH)
pinmux_config(PINMUX_SPI_NOR);
#elif defined(CONFIG_EMMC_SUPPORT)
pinmux_config(PINMUX_EMMC);
#endif
pinmux_config(PINMUX_SDIO1);
cvi_board_init();
return 0;
}
#if defined(__aarch64__)
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#endif
#ifdef CV_SYS_OFF
static void cv_system_off(void)
{
mmio_write_32(REG_RTC_BASE + RTC_EN_SHDN_REQ, 0x01);
while (mmio_read_32(REG_RTC_BASE + RTC_EN_SHDN_REQ) != 0x01)
;
mmio_write_32(REG_RTC_CTRL_BASE + RTC_CTRL0_UNLOCKKEY, 0xAB18);
mmio_setbits_32(REG_RTC_CTRL_BASE + RTC_CTRL0, 0xFFFF0800 | (0x1 << 0));
while (1)
;
}
#endif
void cv_system_reset(void)
{
mmio_write_32(REG_RTC_BASE + RTC_EN_WARM_RST_REQ, 0x01);
while (mmio_read_32(REG_RTC_BASE + RTC_EN_WARM_RST_REQ) != 0x01)
;
mmio_write_32(REG_RTC_CTRL_BASE + RTC_CTRL0_UNLOCKKEY, 0xAB18);
mmio_setbits_32(REG_RTC_CTRL_BASE + RTC_CTRL0, 0xFFFF0800 | (0x1 << 4));
while (1)
;
}
/*
* Board specific reset that is system reset.
*/
void reset_cpu(void)
{
cv_system_reset();
}
#ifdef CONFIG_USB_GADGET_DWC2_OTG
struct dwc2_plat_otg_data cv182x_otg_data = {
.regs_otg = USB_BASE,
.usb_gusbcfg = 0x40081400,
.rx_fifo_sz = 512,
.np_tx_fifo_sz = 512,
.tx_fifo_sz = 512,
};
int board_usb_init(int index, enum usb_init_type init)
{
uint32_t value;
value = mmio_read_32(TOP_BASE + REG_TOP_SOFT_RST) & (~BIT_TOP_SOFT_RST_USB);
mmio_write_32(TOP_BASE + REG_TOP_SOFT_RST, value);
udelay(50);
value = mmio_read_32(TOP_BASE + REG_TOP_SOFT_RST) | BIT_TOP_SOFT_RST_USB;
mmio_write_32(TOP_BASE + REG_TOP_SOFT_RST, value);
/* Set USB phy configuration */
value = mmio_read_32(REG_TOP_USB_PHY_CTRL);
mmio_write_32(REG_TOP_USB_PHY_CTRL, value | BIT_TOP_USB_PHY_CTRL_EXTVBUS
| USB_PHY_ID_OVERRIDE_ENABLE
| USB_PHY_ID_VALUE);
/* Enable ECO RXF */
mmio_write_32(REG_TOP_USB_ECO, mmio_read_32(REG_TOP_USB_ECO) | BIT_TOP_USB_ECO_RX_FLUSH);
printf("cvi_usb_hw_init done\n");
return dwc2_udc_probe(&cv182x_otg_data);
}
#endif
void board_save_time_record(uintptr_t saveaddr)
{
uint64_t boot_us = 0;
#if defined(__aarch64__)
boot_us = timer_get_boot_us();
#elif defined(__riscv)
// Read from CSR_TIME directly. RISC-V timers is initialized later.
boot_us = csr_read(CSR_TIME) / (SYS_COUNTER_FREQ_IN_SECOND / 1000000);
#else
#error "Unknown ARCH"
#endif
mmio_write_16(saveaddr, DIV_ROUND_UP(boot_us, 1000));
}

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//##==============================================================================
//##=== This script is generate by genswconfig.pl from .\00_cv181x_Pinlist_20210827.xls
//##=== Generate Time stamp is : 2021-08-27 20:43:11
//##==============================================================================
#ifndef __CV181X_PINLIST_SWCONFIG_H__
#define __CV181X_PINLIST_SWCONFIG_H__
#define CAM_MCLK0__CAM_MCLK0 0
#define CAM_MCLK0__AUX1 2
#define CAM_MCLK0__XGPIOA_0 3
#define CAM_PD0__IIS1_MCLK 1
#define CAM_PD0__XGPIOA_1 3
#define CAM_PD0__CAM_HS0 4
#define CAM_RST0__XGPIOA_2 3
#define CAM_RST0__CAM_VS0 4
#define CAM_RST0__IIC4_SCL 6
#define CAM_MCLK1__CAM_MCLK1 0
#define CAM_MCLK1__AUX2 2
#define CAM_MCLK1__XGPIOA_3 3
#define CAM_MCLK1__CAM_HS0 4
#define CAM_PD1__IIS1_MCLK 1
#define CAM_PD1__XGPIOA_4 3
#define CAM_PD1__CAM_VS0 4
#define CAM_PD1__IIC4_SDA 6
#define IIC3_SCL__IIC3_SCL 0
#define IIC3_SCL__XGPIOA_5 3
#define IIC3_SDA__IIC3_SDA 0
#define IIC3_SDA__XGPIOA_6 3
#define SD0_CLK__SDIO0_CLK 0
#define SD0_CLK__IIC1_SDA 1
#define SD0_CLK__SPI0_SCK 2
#define SD0_CLK__XGPIOA_7 3
#define SD0_CLK__PWM_15 5
#define SD0_CLK__EPHY_LNK_LED 6
#define SD0_CLK__DBG_0 7
#define SD0_CMD__SDIO0_CMD 0
#define SD0_CMD__IIC1_SCL 1
#define SD0_CMD__SPI0_SDO 2
#define SD0_CMD__XGPIOA_8 3
#define SD0_CMD__PWM_14 5
#define SD0_CMD__EPHY_SPD_LED 6
#define SD0_CMD__DBG_1 7
#define SD0_D0__SDIO0_D_0 0
#define SD0_D0__CAM_MCLK1 1
#define SD0_D0__SPI0_SDI 2
#define SD0_D0__XGPIOA_9 3
#define SD0_D0__UART3_TX 4
#define SD0_D0__PWM_13 5
#define SD0_D0__WG0_D0 6
#define SD0_D0__DBG_2 7
#define SD0_D1__SDIO0_D_1 0
#define SD0_D1__IIC1_SDA 1
#define SD0_D1__AUX0 2
#define SD0_D1__XGPIOA_10 3
#define SD0_D1__UART1_TX 4
#define SD0_D1__PWM_12 5
#define SD0_D1__WG0_D1 6
#define SD0_D1__DBG_3 7
#define SD0_D2__SDIO0_D_2 0
#define SD0_D2__IIC1_SCL 1
#define SD0_D2__AUX1 2
#define SD0_D2__XGPIOA_11 3
#define SD0_D2__UART1_RX 4
#define SD0_D2__PWM_11 5
#define SD0_D2__WG1_D0 6
#define SD0_D2__DBG_4 7
#define SD0_D3__SDIO0_D_3 0
#define SD0_D3__CAM_MCLK0 1
#define SD0_D3__SPI0_CS_X 2
#define SD0_D3__XGPIOA_12 3
#define SD0_D3__UART3_RX 4
#define SD0_D3__PWM_10 5
#define SD0_D3__WG1_D1 6
#define SD0_D3__DBG_5 7
#define SD0_CD__SDIO0_CD 0
#define SD0_CD__XGPIOA_13 3
#define SD0_PWR_EN__SDIO0_PWR_EN 0
#define SD0_PWR_EN__XGPIOA_14 3
#define SPK_EN__XGPIOA_15 3
#define UART0_TX__UART0_TX 0
#define UART0_TX__CAM_MCLK1 1
#define UART0_TX__PWM_4 2
#define UART0_TX__XGPIOA_16 3
#define UART0_TX__UART1_TX 4
#define UART0_TX__AUX1 5
#define UART0_TX__DBG_6 7
#define UART0_RX__UART0_RX 0
#define UART0_RX__CAM_MCLK0 1
#define UART0_RX__PWM_5 2
#define UART0_RX__XGPIOA_17 3
#define UART0_RX__UART1_RX 4
#define UART0_RX__AUX0 5
#define UART0_RX__DBG_7 7
#define EMMC_RSTN__EMMC_RSTN 0
#define EMMC_RSTN__XGPIOA_21 3
#define EMMC_RSTN__AUX2 4
#define EMMC_DAT2__EMMC_DAT_2 0
#define EMMC_DAT2__SPINOR_HOLD_X 1
#define EMMC_DAT2__SPINAND_HOLD 2
#define EMMC_DAT2__XGPIOA_26 3
#define EMMC_CLK__EMMC_CLK 0
#define EMMC_CLK__SPINOR_SCK 1
#define EMMC_CLK__SPINAND_CLK 2
#define EMMC_CLK__XGPIOA_22 3
#define EMMC_DAT0__EMMC_DAT_0 0
#define EMMC_DAT0__SPINOR_MOSI 1
#define EMMC_DAT0__SPINAND_MOSI 2
#define EMMC_DAT0__XGPIOA_25 3
#define EMMC_DAT3__EMMC_DAT_3 0
#define EMMC_DAT3__SPINOR_WP_X 1
#define EMMC_DAT3__SPINAND_WP 2
#define EMMC_DAT3__XGPIOA_27 3
#define EMMC_CMD__EMMC_CMD 0
#define EMMC_CMD__SPINOR_MISO 1
#define EMMC_CMD__SPINAND_MISO 2
#define EMMC_CMD__XGPIOA_23 3
#define EMMC_DAT1__EMMC_DAT_1 0
#define EMMC_DAT1__SPINOR_CS_X 1
#define EMMC_DAT1__SPINAND_CS 2
#define EMMC_DAT1__XGPIOA_24 3
#define JTAG_CPU_TMS__CV_2WTMS_CR_4WTMS 0
#define JTAG_CPU_TMS__CAM_MCLK0 1
#define JTAG_CPU_TMS__PWM_7 2
#define JTAG_CPU_TMS__XGPIOA_19 3
#define JTAG_CPU_TMS__UART1_RTS 4
#define JTAG_CPU_TMS__AUX0 5
#define JTAG_CPU_TMS__UART1_TX 6
#define JTAG_CPU_TMS__VO_D_28 7
#define JTAG_CPU_TCK__CV_2WTCK_CR_4WTCK 0
#define JTAG_CPU_TCK__CAM_MCLK1 1
#define JTAG_CPU_TCK__PWM_6 2
#define JTAG_CPU_TCK__XGPIOA_18 3
#define JTAG_CPU_TCK__UART1_CTS 4
#define JTAG_CPU_TCK__AUX1 5
#define JTAG_CPU_TCK__UART1_RX 6
#define JTAG_CPU_TCK__VO_D_29 7
#define JTAG_CPU_TRST__JTAG_CPU_TRST 0
#define JTAG_CPU_TRST__XGPIOA_20 3
#define JTAG_CPU_TRST__VO_D_30 6
#define IIC0_SCL__CV_SCL0__CR_4WTDI 0
#define IIC0_SCL__UART1_TX 1
#define IIC0_SCL__UART2_TX 2
#define IIC0_SCL__XGPIOA_28 3
#define IIC0_SCL__WG0_D0 5
#define IIC0_SCL__DBG_10 7
#define IIC0_SDA__CV_SDA0__CR_4WTDO 0
#define IIC0_SDA__UART1_RX 1
#define IIC0_SDA__UART2_RX 2
#define IIC0_SDA__XGPIOA_29 3
#define IIC0_SDA__WG0_D1 5
#define IIC0_SDA__WG1_D0 6
#define IIC0_SDA__DBG_11 7
#define AUX0__AUX0 0
#define AUX0__XGPIOA_30 3
#define AUX0__IIS1_MCLK 4
#define AUX0__VO_D_31 5
#define AUX0__WG1_D1 6
#define AUX0__DBG_12 7
#define PWR_VBAT_DET__PWR_VBAT_DET 0
#define PWR_RSTN__PWR_RSTN 0
#define PWR_SEQ1__PWR_SEQ1 0
#define PWR_SEQ1__PWR_GPIO_3 3
#define PWR_SEQ2__PWR_SEQ2 0
#define PWR_SEQ2__PWR_GPIO_4 3
#define PWR_SEQ3__PWR_SEQ3 0
#define PWR_SEQ3__PWR_GPIO_5 3
#define PTEST__PWR_PTEST 0
#define PWR_WAKEUP0__PWR_WAKEUP0 0
#define PWR_WAKEUP0__PWR_IR0 1
#define PWR_WAKEUP0__PWR_UART0_TX 2
#define PWR_WAKEUP0__PWR_GPIO_6 3
#define PWR_WAKEUP0__UART1_TX 4
#define PWR_WAKEUP0__IIC4_SCL 5
#define PWR_WAKEUP0__EPHY_LNK_LED 6
#define PWR_WAKEUP0__WG2_D0 7
#define PWR_WAKEUP1__PWR_WAKEUP1 0
#define PWR_WAKEUP1__PWR_IR1 1
#define PWR_WAKEUP1__PWR_GPIO_7 3
#define PWR_WAKEUP1__UART1_TX 4
#define PWR_WAKEUP1__IIC4_SCL 5
#define PWR_WAKEUP1__EPHY_LNK_LED 6
#define PWR_WAKEUP1__WG0_D0 7
#define PWR_BUTTON1__PWR_BUTTON1 0
#define PWR_BUTTON1__PWR_GPIO_8 3
#define PWR_BUTTON1__UART1_RX 4
#define PWR_BUTTON1__IIC4_SDA 5
#define PWR_BUTTON1__EPHY_SPD_LED 6
#define PWR_BUTTON1__WG2_D1 7
#define PWR_ON__PWR_ON 0
#define PWR_ON__PWR_GPIO_9 3
#define PWR_ON__UART1_RX 4
#define PWR_ON__IIC4_SDA 5
#define PWR_ON__EPHY_SPD_LED 6
#define PWR_ON__WG0_D1 7
#define XTAL_XIN__PWR_XTAL_CLKIN 0
#define PWR_GPIO0__PWR_GPIO_0 0
#define PWR_GPIO0__UART2_TX 1
#define PWR_GPIO0__PWR_UART0_RX 2
#define PWR_GPIO0__PWM_8 4
#define PWR_GPIO1__PWR_GPIO_1 0
#define PWR_GPIO1__UART2_RX 1
#define PWR_GPIO1__EPHY_LNK_LED 3
#define PWR_GPIO1__PWM_9 4
#define PWR_GPIO1__PWR_IIC_SCL 5
#define PWR_GPIO1__IIC2_SCL 6
#define PWR_GPIO1__CV_4WTMS_CR_SDA0 7
#define PWR_GPIO2__PWR_GPIO_2 0
#define PWR_GPIO2__PWR_SECTICK 2
#define PWR_GPIO2__EPHY_SPD_LED 3
#define PWR_GPIO2__PWM_10 4
#define PWR_GPIO2__PWR_IIC_SDA 5
#define PWR_GPIO2__IIC2_SDA 6
#define PWR_GPIO2__CV_4WTCK_CR_2WTCK 7
#define CLK32K__CLK32K 0
#define CLK32K__AUX0 1
#define CLK32K__CV_4WTDI_CR_SCL0 2
#define CLK32K__PWR_GPIO_10 3
#define CLK32K__PWM_2 4
#define CLK32K__KEY_COL0 5
#define CLK32K__CAM_MCLK0 6
#define CLK32K__DBG_0 7
#define CLK25M__CLK25M 0
#define CLK25M__AUX1 1
#define CLK25M__CV_4WTDO_CR_2WTMS 2
#define CLK25M__PWR_GPIO_11 3
#define CLK25M__PWM_3 4
#define CLK25M__KEY_COL1 5
#define CLK25M__CAM_MCLK1 6
#define CLK25M__DBG_1 7
#define IIC2_SCL__IIC2_SCL 0
#define IIC2_SCL__PWM_14 1
#define IIC2_SCL__PWR_GPIO_12 3
#define IIC2_SCL__UART2_RX 4
#define IIC2_SCL__KEY_COL2 7
#define IIC2_SDA__IIC2_SDA 0
#define IIC2_SDA__PWM_15 1
#define IIC2_SDA__PWR_GPIO_13 3
#define IIC2_SDA__UART2_TX 4
#define IIC2_SDA__IIS1_MCLK 5
#define IIC2_SDA__IIS2_MCLK 6
#define IIC2_SDA__KEY_COL3 7
#define UART2_TX__UART2_TX 0
#define UART2_TX__PWM_11 1
#define UART2_TX__PWR_UART1_TX 2
#define UART2_TX__PWR_GPIO_14 3
#define UART2_TX__KEY_ROW3 4
#define UART2_TX__UART4_TX 5
#define UART2_TX__IIS2_BCLK 6
#define UART2_TX__WG2_D0 7
#define UART2_RTS__UART2_RTS 0
#define UART2_RTS__PWM_8 1
#define UART2_RTS__PWR_GPIO_15 3
#define UART2_RTS__KEY_ROW0 4
#define UART2_RTS__UART4_RTS 5
#define UART2_RTS__IIS2_DO 6
#define UART2_RTS__WG1_D0 7
#define UART2_RX__UART2_RX 0
#define UART2_RX__PWM_10 1
#define UART2_RX__PWR_UART1_RX 2
#define UART2_RX__PWR_GPIO_16 3
#define UART2_RX__KEY_COL3 4
#define UART2_RX__UART4_RX 5
#define UART2_RX__IIS2_DI 6
#define UART2_RX__WG2_D1 7
#define UART2_CTS__UART2_CTS 0
#define UART2_CTS__PWM_9 1
#define UART2_CTS__PWR_GPIO_17 3
#define UART2_CTS__KEY_ROW1 4
#define UART2_CTS__UART4_CTS 5
#define UART2_CTS__IIS2_LRCK 6
#define UART2_CTS__WG1_D1 7
#define SD1_D3__PWR_SD1_D3_VO32 0
#define SD1_D3__SPI2_CS_X 1
#define SD1_D3__IIC1_SCL 2
#define SD1_D3__PWR_GPIO_18 3
#define SD1_D3__CAM_MCLK0 4
#define SD1_D3__UART3_CTS 5
#define SD1_D3__PWR_SPINOR1_CS_X 6
#define SD1_D3__PWM_4 7
#define SD1_D2__PWR_SD1_D2_VO33 0
#define SD1_D2__IIC1_SCL 1
#define SD1_D2__UART2_TX 2
#define SD1_D2__PWR_GPIO_19 3
#define SD1_D2__CAM_MCLK0 4
#define SD1_D2__UART3_TX 5
#define SD1_D2__PWR_SPINOR1_HOLD_X 6
#define SD1_D2__PWM_5 7
#define SD1_D1__PWR_SD1_D1_VO34 0
#define SD1_D1__IIC1_SDA 1
#define SD1_D1__UART2_RX 2
#define SD1_D1__PWR_GPIO_20 3
#define SD1_D1__CAM_MCLK1 4
#define SD1_D1__UART3_RX 5
#define SD1_D1__PWR_SPINOR1_WP_X 6
#define SD1_D1__PWM_6 7
#define SD1_D0__PWR_SD1_D0_VO35 0
#define SD1_D0__SPI2_SDI 1
#define SD1_D0__IIC1_SDA 2
#define SD1_D0__PWR_GPIO_21 3
#define SD1_D0__CAM_MCLK1 4
#define SD1_D0__UART3_RTS 5
#define SD1_D0__PWR_SPINOR1_MISO 6
#define SD1_D0__PWM_7 7
#define SD1_CMD__PWR_SD1_CMD_VO36 0
#define SD1_CMD__SPI2_SDO 1
#define SD1_CMD__IIC3_SCL 2
#define SD1_CMD__PWR_GPIO_22 3
#define SD1_CMD__CAM_VS0 4
#define SD1_CMD__EPHY_LNK_LED 5
#define SD1_CMD__PWR_SPINOR1_MOSI 6
#define SD1_CMD__PWM_8 7
#define SD1_CLK__PWR_SD1_CLK_VO37 0
#define SD1_CLK__SPI2_SCK 1
#define SD1_CLK__IIC3_SDA 2
#define SD1_CLK__PWR_GPIO_23 3
#define SD1_CLK__CAM_HS0 4
#define SD1_CLK__EPHY_SPD_LED 5
#define SD1_CLK__PWR_SPINOR1_SCK 6
#define SD1_CLK__PWM_9 7
#define RSTN__RSTN 0
#define PWM0_BUCK__PWM_0 0
#define PWM0_BUCK__XGPIOB_0 3
#define ADC3__CAM_MCLK0 1
#define ADC3__IIC4_SCL 2
#define ADC3__XGPIOB_1 3
#define ADC3__PWM_12 4
#define ADC3__EPHY_LNK_LED 5
#define ADC3__WG2_D0 6
#define ADC3__UART3_TX 7
#define ADC2__CAM_MCLK1 1
#define ADC2__IIC4_SDA 2
#define ADC2__XGPIOB_2 3
#define ADC2__PWM_13 4
#define ADC2__EPHY_SPD_LED 5
#define ADC2__WG2_D1 6
#define ADC2__UART3_RX 7
#define ADC1__XGPIOB_3 3
#define ADC1__KEY_COL2 4
#define USB_ID__USB_ID 0
#define USB_ID__XGPIOB_4 3
#define USB_VBUS_EN__USB_VBUS_EN 0
#define USB_VBUS_EN__XGPIOB_5 3
#define PKG_TYPE0__PKG_TYPE0 0
#define USB_VBUS_DET__USB_VBUS_DET 0
#define USB_VBUS_DET__XGPIOB_6 3
#define USB_VBUS_DET__CAM_MCLK0 4
#define USB_VBUS_DET__CAM_MCLK1 5
#define PKG_TYPE1__PKG_TYPE1 0
#define PKG_TYPE2__PKG_TYPE2 0
#define MUX_SPI1_MISO__UART3_RTS 1
#define MUX_SPI1_MISO__IIC1_SDA 2
#define MUX_SPI1_MISO__XGPIOB_8 3
#define MUX_SPI1_MISO__PWM_9 4
#define MUX_SPI1_MISO__KEY_COL1 5
#define MUX_SPI1_MISO__SPI1_SDI 6
#define MUX_SPI1_MISO__DBG_14 7
#define MUX_SPI1_MOSI__UART3_RX 1
#define MUX_SPI1_MOSI__IIC1_SCL 2
#define MUX_SPI1_MOSI__XGPIOB_7 3
#define MUX_SPI1_MOSI__PWM_8 4
#define MUX_SPI1_MOSI__KEY_COL0 5
#define MUX_SPI1_MOSI__SPI1_SDO 6
#define MUX_SPI1_MOSI__DBG_13 7
#define MUX_SPI1_CS__UART3_CTS 1
#define MUX_SPI1_CS__CAM_MCLK0 2
#define MUX_SPI1_CS__XGPIOB_10 3
#define MUX_SPI1_CS__PWM_11 4
#define MUX_SPI1_CS__KEY_ROW3 5
#define MUX_SPI1_CS__SPI1_CS_X 6
#define MUX_SPI1_CS__DBG_16 7
#define MUX_SPI1_SCK__UART3_TX 1
#define MUX_SPI1_SCK__CAM_MCLK1 2
#define MUX_SPI1_SCK__XGPIOB_9 3
#define MUX_SPI1_SCK__PWM_10 4
#define MUX_SPI1_SCK__KEY_ROW2 5
#define MUX_SPI1_SCK__SPI1_SCK 6
#define MUX_SPI1_SCK__DBG_15 7
#define PAD_ETH_TXP__UART3_RX 1
#define PAD_ETH_TXP__IIC1_SCL 2
#define PAD_ETH_TXP__XGPIOB_25 3
#define PAD_ETH_TXP__PWM_13 4
#define PAD_ETH_TXP__CAM_MCLK0 5
#define PAD_ETH_TXP__SPI1_SDO 6
#define PAD_ETH_TXP__IIS2_LRCK 7
#define PAD_ETH_TXM__UART3_RTS 1
#define PAD_ETH_TXM__IIC1_SDA 2
#define PAD_ETH_TXM__XGPIOB_24 3
#define PAD_ETH_TXM__PWM_12 4
#define PAD_ETH_TXM__CAM_MCLK1 5
#define PAD_ETH_TXM__SPI1_SDI 6
#define PAD_ETH_TXM__IIS2_BCLK 7
#define PAD_ETH_RXP__UART3_TX 1
#define PAD_ETH_RXP__CAM_MCLK1 2
#define PAD_ETH_RXP__XGPIOB_27 3
#define PAD_ETH_RXP__PWM_15 4
#define PAD_ETH_RXP__CAM_HS0 5
#define PAD_ETH_RXP__SPI1_SCK 6
#define PAD_ETH_RXP__IIS2_DO 7
#define PAD_ETH_RXM__UART3_CTS 1
#define PAD_ETH_RXM__CAM_MCLK0 2
#define PAD_ETH_RXM__XGPIOB_26 3
#define PAD_ETH_RXM__PWM_14 4
#define PAD_ETH_RXM__CAM_VS0 5
#define PAD_ETH_RXM__SPI1_CS_X 6
#define PAD_ETH_RXM__IIS2_DI 7
#define VIVO_D10__PWM_1 0
#define VIVO_D10__VI1_D_10 1
#define VIVO_D10__VO_D_23 2
#define VIVO_D10__XGPIOB_11 3
#define VIVO_D10__RMII0_IRQ 4
#define VIVO_D10__CAM_MCLK0 5
#define VIVO_D10__IIC1_SDA 6
#define VIVO_D10__UART2_TX 7
#define VIVO_D9__PWM_2 0
#define VIVO_D9__VI1_D_9 1
#define VIVO_D9__VO_D_22 2
#define VIVO_D9__XGPIOB_12 3
#define VIVO_D9__CAM_MCLK1 5
#define VIVO_D9__IIC1_SCL 6
#define VIVO_D9__UART2_RX 7
#define VIVO_D8__PWM_3 0
#define VIVO_D8__VI1_D_8 1
#define VIVO_D8__VO_D_21 2
#define VIVO_D8__XGPIOB_13 3
#define VIVO_D8__RMII0_MDIO 4
#define VIVO_D8__SPI3_SDO 5
#define VIVO_D8__IIC2_SCL 6
#define VIVO_D8__CAM_VS0 7
#define VIVO_D7__VI2_D_7 0
#define VIVO_D7__VI1_D_7 1
#define VIVO_D7__VO_D_20 2
#define VIVO_D7__XGPIOB_14 3
#define VIVO_D7__RMII0_RXD1 4
#define VIVO_D7__SPI3_SDI 5
#define VIVO_D7__IIC2_SDA 6
#define VIVO_D7__CAM_HS0 7
#define VIVO_D6__VI2_D_6 0
#define VIVO_D6__VI1_D_6 1
#define VIVO_D6__VO_D_19 2
#define VIVO_D6__XGPIOB_15 3
#define VIVO_D6__RMII0_REFCLKI 4
#define VIVO_D6__SPI3_SCK 5
#define VIVO_D6__UART2_TX 6
#define VIVO_D6__CAM_VS0 7
#define VIVO_D5__VI2_D_5 0
#define VIVO_D5__VI1_D_5 1
#define VIVO_D5__VO_D_18 2
#define VIVO_D5__XGPIOB_16 3
#define VIVO_D5__RMII0_RXD0 4
#define VIVO_D5__SPI3_CS_X 5
#define VIVO_D5__UART2_RX 6
#define VIVO_D5__CAM_HS0 7
#define VIVO_D4__VI2_D_4 0
#define VIVO_D4__VI1_D_4 1
#define VIVO_D4__VO_D_17 2
#define VIVO_D4__XGPIOB_17 3
#define VIVO_D4__RMII0_MDC 4
#define VIVO_D4__IIC1_SDA 5
#define VIVO_D4__UART2_CTS 6
#define VIVO_D4__CAM_VS0 7
#define VIVO_D3__VI2_D_3 0
#define VIVO_D3__VI1_D_3 1
#define VIVO_D3__VO_D_16 2
#define VIVO_D3__XGPIOB_18 3
#define VIVO_D3__RMII0_TXD0 4
#define VIVO_D3__IIC1_SCL 5
#define VIVO_D3__UART2_RTS 6
#define VIVO_D3__CAM_HS0 7
#define VIVO_D2__VI2_D_2 0
#define VIVO_D2__VI1_D_2 1
#define VIVO_D2__VO_D_15 2
#define VIVO_D2__XGPIOB_19 3
#define VIVO_D2__RMII0_TXD1 4
#define VIVO_D2__CAM_MCLK1 5
#define VIVO_D2__PWM_2 6
#define VIVO_D2__UART2_TX 7
#define VIVO_D1__VI2_D_1 0
#define VIVO_D1__VI1_D_1 1
#define VIVO_D1__VO_D_14 2
#define VIVO_D1__XGPIOB_20 3
#define VIVO_D1__RMII0_RXDV 4
#define VIVO_D1__IIC3_SDA 5
#define VIVO_D1__PWM_3 6
#define VIVO_D1__IIC4_SCL 7
#define VIVO_D0__VI2_D_0 0
#define VIVO_D0__VI1_D_0 1
#define VIVO_D0__VO_D_13 2
#define VIVO_D0__XGPIOB_21 3
#define VIVO_D0__RMII0_TXCLK 4
#define VIVO_D0__IIC3_SCL 5
#define VIVO_D0__WG1_D0 6
#define VIVO_D0__IIC4_SDA 7
#define VIVO_CLK__VI2_CLK 0
#define VIVO_CLK__VI1_CLK 1
#define VIVO_CLK__VO_CLK1 2
#define VIVO_CLK__XGPIOB_22 3
#define VIVO_CLK__RMII0_TXEN 4
#define VIVO_CLK__CAM_MCLK0 5
#define VIVO_CLK__WG1_D1 6
#define VIVO_CLK__UART2_RX 7
#define PAD_MIPIRX5N__VI1_D_11 1
#define PAD_MIPIRX5N__VO_D_12 2
#define PAD_MIPIRX5N__XGPIOC_0 3
#define PAD_MIPIRX5N__CAM_MCLK0 5
#define PAD_MIPIRX5N__WG0_D0 6
#define PAD_MIPIRX5N__DBG_0 7
#define PAD_MIPIRX5P__VI1_D_12 1
#define PAD_MIPIRX5P__VO_D_11 2
#define PAD_MIPIRX5P__XGPIOC_1 3
#define PAD_MIPIRX5P__IIS1_MCLK 4
#define PAD_MIPIRX5P__CAM_MCLK1 5
#define PAD_MIPIRX5P__WG0_D1 6
#define PAD_MIPIRX5P__DBG_1 7
#define PAD_MIPIRX4N__CV_4WTDI_CR_SCL0 0
#define PAD_MIPIRX4N__VI0_CLK 1
#define PAD_MIPIRX4N__VI1_D_13 2
#define PAD_MIPIRX4N__XGPIOC_2 3
#define PAD_MIPIRX4N__IIC1_SDA 4
#define PAD_MIPIRX4N__CAM_MCLK0 5
#define PAD_MIPIRX4N__KEY_ROW0 6
#define PAD_MIPIRX4N__MUX_SPI1_SCK 7
#define PAD_MIPIRX4P__CV_4WTMS_CR_SDA0 0
#define PAD_MIPIRX4P__VI0_D_0 1
#define PAD_MIPIRX4P__VI1_D_14 2
#define PAD_MIPIRX4P__XGPIOC_3 3
#define PAD_MIPIRX4P__IIC1_SCL 4
#define PAD_MIPIRX4P__CAM_MCLK1 5
#define PAD_MIPIRX4P__KEY_ROW1 6
#define PAD_MIPIRX4P__MUX_SPI1_CS 7
#define PAD_MIPIRX3N__CV_4WTDO_CR_2WTMS 0
#define PAD_MIPIRX3N__VI0_D_1 1
#define PAD_MIPIRX3N__VI1_D_15 2
#define PAD_MIPIRX3N__XGPIOC_4 3
#define PAD_MIPIRX3N__CAM_MCLK0 4
#define PAD_MIPIRX3N__MUX_SPI1_MISO 7
#define PAD_MIPIRX3P__CV_4WTCK_CR_2WTCK 0
#define PAD_MIPIRX3P__VI0_D_2 1
#define PAD_MIPIRX3P__VI1_D_16 2
#define PAD_MIPIRX3P__XGPIOC_5 3
#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7
#define PAD_MIPIRX2N__VI0_D_3 1
#define PAD_MIPIRX2N__VO_D_10 2
#define PAD_MIPIRX2N__XGPIOC_6 3
#define PAD_MIPIRX2N__VI1_D_17 4
#define PAD_MIPIRX2N__IIC4_SCL 5
#define PAD_MIPIRX2N__DBG_6 7
#define PAD_MIPIRX2P__VI0_D_4 1
#define PAD_MIPIRX2P__VO_D_9 2
#define PAD_MIPIRX2P__XGPIOC_7 3
#define PAD_MIPIRX2P__VI1_D_18 4
#define PAD_MIPIRX2P__IIC4_SDA 5
#define PAD_MIPIRX2P__DBG_7 7
#define PAD_MIPIRX1N__VI0_D_5 1
#define PAD_MIPIRX1N__VO_D_8 2
#define PAD_MIPIRX1N__XGPIOC_8 3
#define PAD_MIPIRX1N__KEY_ROW3 6
#define PAD_MIPIRX1N__DBG_8 7
#define PAD_MIPIRX1P__VI0_D_6 1
#define PAD_MIPIRX1P__VO_D_7 2
#define PAD_MIPIRX1P__XGPIOC_9 3
#define PAD_MIPIRX1P__IIC1_SDA 4
#define PAD_MIPIRX1P__KEY_ROW2 6
#define PAD_MIPIRX1P__DBG_9 7
#define PAD_MIPIRX0N__VI0_D_7 1
#define PAD_MIPIRX0N__VO_D_6 2
#define PAD_MIPIRX0N__XGPIOC_10 3
#define PAD_MIPIRX0N__IIC1_SCL 4
#define PAD_MIPIRX0N__CAM_MCLK1 5
#define PAD_MIPIRX0N__DBG_10 7
#define PAD_MIPIRX0P__VI0_D_8 1
#define PAD_MIPIRX0P__VO_D_5 2
#define PAD_MIPIRX0P__XGPIOC_11 3
#define PAD_MIPIRX0P__CAM_MCLK0 4
#define PAD_MIPIRX0P__DBG_11 7
#define PAD_MIPI_TXM4__VI0_D_15 0
#define PAD_MIPI_TXM4__SD1_CLK 1
#define PAD_MIPI_TXM4__VO_D_24 2
#define PAD_MIPI_TXM4__XGPIOC_18 3
#define PAD_MIPI_TXM4__CAM_MCLK1 4
#define PAD_MIPI_TXM4__PWM_12 5
#define PAD_MIPI_TXM4__IIC1_SDA 6
#define PAD_MIPI_TXM4__DBG_18 7
#define PAD_MIPI_TXP4__VI0_D_16 0
#define PAD_MIPI_TXP4__SD1_CMD 1
#define PAD_MIPI_TXP4__VO_D_25 2
#define PAD_MIPI_TXP4__XGPIOC_19 3
#define PAD_MIPI_TXP4__CAM_MCLK0 4
#define PAD_MIPI_TXP4__PWM_13 5
#define PAD_MIPI_TXP4__IIC1_SCL 6
#define PAD_MIPI_TXP4__DBG_19 7
#define PAD_MIPI_TXM3__VI0_D_17 0
#define PAD_MIPI_TXM3__SD1_D0 1
#define PAD_MIPI_TXM3__VO_D_26 2
#define PAD_MIPI_TXM3__XGPIOC_20 3
#define PAD_MIPI_TXM3__IIC2_SDA 4
#define PAD_MIPI_TXM3__PWM_14 5
#define PAD_MIPI_TXM3__IIC1_SDA 6
#define PAD_MIPI_TXM3__CAM_VS0 7
#define PAD_MIPI_TXP3__VI0_D_18 0
#define PAD_MIPI_TXP3__SD1_D1 1
#define PAD_MIPI_TXP3__VO_D_27 2
#define PAD_MIPI_TXP3__XGPIOC_21 3
#define PAD_MIPI_TXP3__IIC2_SCL 4
#define PAD_MIPI_TXP3__PWM_15 5
#define PAD_MIPI_TXP3__IIC1_SCL 6
#define PAD_MIPI_TXP3__CAM_HS0 7
#define PAD_MIPI_TXM2__CV_4WTMS_CR_SDA0 0
#define PAD_MIPI_TXM2__VI0_D_13 1
#define PAD_MIPI_TXM2__VO_D_0 2
#define PAD_MIPI_TXM2__XGPIOC_16 3
#define PAD_MIPI_TXM2__IIC1_SDA 4
#define PAD_MIPI_TXM2__PWM_8 5
#define PAD_MIPI_TXM2__SPI0_SCK 6
#define PAD_MIPI_TXM2__SD1_D2 7
#define PAD_MIPI_TXP2__CV_4WTDI_CR_SCL0 0
#define PAD_MIPI_TXP2__VI0_D_14 1
#define PAD_MIPI_TXP2__VO_CLK0 2
#define PAD_MIPI_TXP2__XGPIOC_17 3
#define PAD_MIPI_TXP2__IIC1_SCL 4
#define PAD_MIPI_TXP2__PWM_9 5
#define PAD_MIPI_TXP2__SPI0_CS_X 6
#define PAD_MIPI_TXP2__SD1_D3 7
#define PAD_MIPI_TXM1__CV_4WTDO_CR_2WTMS 0
#define PAD_MIPI_TXM1__VI0_D_11 1
#define PAD_MIPI_TXM1__VO_D_2 2
#define PAD_MIPI_TXM1__XGPIOC_14 3
#define PAD_MIPI_TXM1__IIC2_SDA 4
#define PAD_MIPI_TXM1__PWM_10 5
#define PAD_MIPI_TXM1__SPI0_SDO 6
#define PAD_MIPI_TXM1__DBG_14 7
#define PAD_MIPI_TXP1__CV_4WTCK_CR_2WTCK 0
#define PAD_MIPI_TXP1__VI0_D_12 1
#define PAD_MIPI_TXP1__VO_D_1 2
#define PAD_MIPI_TXP1__XGPIOC_15 3
#define PAD_MIPI_TXP1__IIC2_SCL 4
#define PAD_MIPI_TXP1__PWM_11 5
#define PAD_MIPI_TXP1__SPI0_SDI 6
#define PAD_MIPI_TXP1__DBG_15 7
#define PAD_MIPI_TXM0__VI0_D_9 1
#define PAD_MIPI_TXM0__VO_D_4 2
#define PAD_MIPI_TXM0__XGPIOC_12 3
#define PAD_MIPI_TXM0__CAM_MCLK1 4
#define PAD_MIPI_TXM0__PWM_14 5
#define PAD_MIPI_TXM0__CAM_VS0 6
#define PAD_MIPI_TXM0__DBG_12 7
#define PAD_MIPI_TXP0__VI0_D_10 1
#define PAD_MIPI_TXP0__VO_D_3 2
#define PAD_MIPI_TXP0__XGPIOC_13 3
#define PAD_MIPI_TXP0__CAM_MCLK0 4
#define PAD_MIPI_TXP0__PWM_15 5
#define PAD_MIPI_TXP0__CAM_HS0 6
#define PAD_MIPI_TXP0__DBG_13 7
#define PAD_AUD_AINL_MIC__XGPIOC_23 3
#define PAD_AUD_AINL_MIC__IIS1_BCLK 4
#define PAD_AUD_AINL_MIC__IIS2_BCLK 5
#define PAD_AUD_AINR_MIC__XGPIOC_22 3
#define PAD_AUD_AINR_MIC__IIS1_DO 4
#define PAD_AUD_AINR_MIC__IIS2_DI 5
#define PAD_AUD_AINR_MIC__IIS1_DI 6
#define PAD_AUD_AOUTL__XGPIOC_25 3
#define PAD_AUD_AOUTL__IIS1_LRCK 4
#define PAD_AUD_AOUTL__IIS2_LRCK 5
#define PAD_AUD_AOUTR__XGPIOC_24 3
#define PAD_AUD_AOUTR__IIS1_DI 4
#define PAD_AUD_AOUTR__IIS2_DO 5
#define PAD_AUD_AOUTR__IIS1_DO 6
#define GPIO_RTX__XGPIOB_23 3
#define GPIO_RTX__PWM_1 4
#define GPIO_RTX__CAM_MCLK0 5
#define GPIO_ZQ__PWR_GPIO_24 3
#define GPIO_ZQ__PWM_2 4
#endif /* __CV181X_PINLIST_SWCONFIG_H__ */

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#ifndef __CV181X_REG_H__
#define __CV181X_REG_H__
#define TOP_BASE 0x03000000
#define PINMUX_BASE (TOP_BASE + 0x1000)
#define WATCHDOG_BASE (TOP_BASE + 0x00010000)
#define RTC_BASE 0x05026000
/*
* RTC info registers
*/
#define RTC_INFO0 (RTC_BASE + 0x1C)
/*
* General purpose registers
*/
#define GP_REG0 (TOP_BASE + 0x80)
#define GP_REG1 (TOP_BASE + 0x84)
#define GP_REG2 (TOP_BASE + 0x88
#define GP_REG3 (TOP_BASE + 0x8C)
#define GP_REG4 (TOP_BASE + 0x90)
#define GP_REG5 (TOP_BASE + 0x94)
#define GP_REG6 (TOP_BASE + 0x98)
#define GP_REG7 (TOP_BASE + 0x9C)
#define GP_REG8 (TOP_BASE + 0xA0)
#define GP_REG9 (TOP_BASE + 0xA4)
#define GP_REG10 (TOP_BASE + 0xA8)
/*
* Pinmux definitions
*/
#define PINMUX_UART0 0
#define PINMUX_UART1 1
#define PINMUX_UART2 2
#define PINMUX_UART3 3
#define PINMUX_UART3_2 4
#define PINMUX_I2C0 5
#define PINMUX_I2C1 6
#define PINMUX_I2C2 7
#define PINMUX_I2C3 8
#define PINMUX_I2C4 9
#define PINMUX_I2C4_2 10
#define PINMUX_SPI0 11
#define PINMUX_SPI1 12
#define PINMUX_SPI2 13
#define PINMUX_SPI2_2 14
#define PINMUX_SPI3 15
#define PINMUX_SPI3_2 16
#define PINMUX_I2S0 17
#define PINMUX_I2S1 18
#define PINMUX_I2S2 19
#define PINMUX_I2S3 20
#define PINMUX_USBID 21
#define PINMUX_SDIO0 22
#define PINMUX_SDIO1 23
#define PINMUX_ND 24
#define PINMUX_EMMC 25
#define PINMUX_SPI_NOR 26
#define PINMUX_SPI_NAND 27
#define PINMUX_CAM0 28
#define PINMUX_CAM1 29
#define PINMUX_PCM0 30
#define PINMUX_PCM1 31
#define PINMUX_CSI0 32
#define PINMUX_CSI1 33
#define PINMUX_CSI2 34
#define PINMUX_DSI 35
#define PINMUX_VI0 36
#define PINMUX_VO 37
#define PINMUX_RMII1 38
#define PINMUX_EPHY_LED 39
#define PINMUX_I80 40
#define PINMUX_LVDS 41
#define PINMUX_USB_VBUS_DET (PINMUX_BASE + 0x108)
#define REG_TOP_USB_ECO (TOP_BASE + 0xB4)
#define BIT_TOP_USB_ECO_RX_FLUSH 0x80
/* rst */
#define REG_TOP_SOFT_RST 0x3000
#define BIT_TOP_SOFT_RST_USB BIT(11)
#define BIT_TOP_SOFT_RST_SDIO BIT(14)
#define BIT_TOP_SOFT_RST_NAND BIT(12)
#define REG_TOP_USB_CTRSTS (TOP_BASE + 0x38)
#define REG_TOP_CONF_INFO (TOP_BASE + 0x4)
#define BIT_TOP_CONF_INFO_VBUS BIT(9)
#define REG_TOP_USB_PHY_CTRL (TOP_BASE + 0x48)
#define BIT_TOP_USB_PHY_CTRL_EXTVBUS BIT(0)
#define USB_PHY_ID_OVERRIDE_ENABLE BIT(6)
#define USB_PHY_ID_VALUE BIT(7)
#define REG_TOP_DDR_ADDR_MODE (TOP_BASE + 0x64)
/* irq */
#define IRQ_LEVEL 0
#define IRQ_EDGE 3
/* usb */
#define USB_BASE 0x04340000
/* ethernet phy */
#define ETH_PHY_BASE 0x03009000
#define ETH_PHY_INIT_MASK 0xFFFFFFF9
#define ETH_PHY_SHUTDOWN BIT(1)
#define ETH_PHY_POWERUP 0xFFFFFFFD
#define ETH_PHY_RESET 0xFFFFFFFB
#define ETH_PHY_RESET_N BIT(2)
#define ETH_PHY_LED_LOW_ACTIVE BIT(3)
/* watchdog */
#define CONFIG_DW_WDT_BASE WATCHDOG_BASE
#define CONFIG_DW_WDT_CLOCK_KHZ 25000
#define DW_WDT_CR 0x00
#define DW_WDT_TORR 0x04
#define DW_WDT_CRR 0x0C
#define DW_WDT_CR_EN_OFFSET 0x00
#define DW_WDT_CR_RMOD_OFFSET 0x01
#define DW_WDT_CR_RMOD_VAL 0x00
#define DW_WDT_CRR_RESTART_VAL 0x76
/* SDIO Wifi */
#define WIFI_CHIP_EN_BGA BIT(18)
#define WIFI_CHIP_EN_QFN BIT(2)
/* RTC */
#define RTC_SYS_BASE 0x05000000
#define RTC_MACRO_BASE (RTC_SYS_BASE + 0x00026400)
#define RTC_MACRO_DA_SOC_READY 0x8C
#define RTC_MACRO_RO_T 0xA8
#define RTC_CORE_SRAM_BASE (RTC_SYS_BASE + 0x00026800)
#define RTC_CORE_SRAM_SIZE 0x0800 // 2KB
#define REG_RTC_CTRL_BASE (RTC_SYS_BASE + 0x00025000)
#define RTC_CTRL0_UNLOCKKEY 0x4
#define RTC_CTRL0 0x8
#define RTC_CTRL0_STATUS0 0xC
#define RTCSYS_RST_CTRL 0x18
#define REG_RTC_BASE (RTC_SYS_BASE + 0x00026000)
#define RTC_EN_PWR_WAKEUP 0xBC
#define RTC_EN_SHDN_REQ 0xC0
#define RTC_EN_PWR_CYC_REQ 0xC8
#define RTC_EN_WARM_RST_REQ 0xCC
#define RTC_EN_WDT_RST_REQ 0xE0
#define RTC_EN_SUSPEND_REQ 0xE4
#define RTC_PG_REG 0xF0
#define RTC_ST_ON_REASON 0xF8
#define REG_RTC_ST_ON_REASON (REG_RTC_BASE + RTC_ST_ON_REASON)
#define RTCSYS_F32KLESS_BASE (RTC_SYS_BASE + 0x0002A000)
#define RTC_INTERNAL_32K 0
#define RTC_EXTERNAL_32K 1
/* eFuse */
#define EFUSE_BASE (TOP_BASE + 0x00050000)
/* AXI SRAM */
#define AXI_SRAM_BASE 0x0E000000
#define AXI_SRAM_SIZE 0x40
#define EFUSE_SW_INFO_ADDR (AXI_SRAM_BASE)
#define EFUSE_SW_INFO_SIZE 4
#define BOOT_SOURCE_FLAG_ADDR (EFUSE_SW_INFO_ADDR + EFUSE_SW_INFO_SIZE)
#define BOOT_SOURCE_FLAG_SIZE 4
#define MAGIC_NUM_USB_DL 0x4D474E31 // MGN1
#define MAGIC_NUM_SD_DL 0x4D474E32 // MGN2
#define BOOT_LOG_LEN_ADDR (BOOT_SOURCE_FLAG_ADDR + BOOT_SOURCE_FLAG_SIZE) // 0x0E000008
#define BOOT_LOG_LEN_SIZE 4
#define TIME_RECORDS_ADDR (AXI_SRAM_BASE + 0x10) // 0x0E000010
/* from fsbl/plat/cv181x/include/platform_def.h struct _time_records { ... } */
#define TIME_RECORDS_FIELD_UBOOT_START (TIME_RECORDS_ADDR + 0x10)
#define TIME_RECORDS_FIELD_BOOTCMD_START (TIME_RECORDS_ADDR + 0x12)
#define TIME_RECORDS_FIELD_DECOMPRESS_KERNEL_START (TIME_RECORDS_ADDR + 0x14)
#define TIME_RECORDS_FIELD_KERNEL_START (TIME_RECORDS_ADDR + 0x16)
#endif /* __CV181X_REG_H__ */

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// $Module: fmux_gpio $
// $RegisterBank Version: V 1.0.00 $
// $Author: ghost $
// $Date: Fri, 27 Aug 2021 08:47:09 PM $
//
//GEN REG ADDR/OFFSET/MASK
#ifndef __CV181X_REG_FMUX_GPIO_H__
#define __CV181X_REG_FMUX_GPIO_H__
#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK0 0x0
#define FMUX_GPIO_REG_IOCTRL_CAM_PD0 0x4
#define FMUX_GPIO_REG_IOCTRL_CAM_RST0 0x8
#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK1 0xc
#define FMUX_GPIO_REG_IOCTRL_CAM_PD1 0x10
#define FMUX_GPIO_REG_IOCTRL_IIC3_SCL 0x14
#define FMUX_GPIO_REG_IOCTRL_IIC3_SDA 0x18
#define FMUX_GPIO_REG_IOCTRL_SD0_CLK 0x1c
#define FMUX_GPIO_REG_IOCTRL_SD0_CMD 0x20
#define FMUX_GPIO_REG_IOCTRL_SD0_D0 0x24
#define FMUX_GPIO_REG_IOCTRL_SD0_D1 0x28
#define FMUX_GPIO_REG_IOCTRL_SD0_D2 0x2c
#define FMUX_GPIO_REG_IOCTRL_SD0_D3 0x30
#define FMUX_GPIO_REG_IOCTRL_SD0_CD 0x34
#define FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN 0x38
#define FMUX_GPIO_REG_IOCTRL_SPK_EN 0x3c
#define FMUX_GPIO_REG_IOCTRL_UART0_TX 0x40
#define FMUX_GPIO_REG_IOCTRL_UART0_RX 0x44
#define FMUX_GPIO_REG_IOCTRL_EMMC_RSTN 0x48
#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT2 0x4c
#define FMUX_GPIO_REG_IOCTRL_EMMC_CLK 0x50
#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT0 0x54
#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT3 0x58
#define FMUX_GPIO_REG_IOCTRL_EMMC_CMD 0x5c
#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT1 0x60
#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS 0x64
#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK 0x68
#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TRST 0x6c
#define FMUX_GPIO_REG_IOCTRL_IIC0_SCL 0x70
#define FMUX_GPIO_REG_IOCTRL_IIC0_SDA 0x74
#define FMUX_GPIO_REG_IOCTRL_AUX0 0x78
#define FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET 0x7c
#define FMUX_GPIO_REG_IOCTRL_PWR_RSTN 0x80
#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ1 0x84
#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ2 0x88
#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ3 0x8c
#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0 0x90
#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP1 0x94
#define FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1 0x98
#define FMUX_GPIO_REG_IOCTRL_PWR_ON 0x9c
#define FMUX_GPIO_REG_IOCTRL_XTAL_XIN 0xa0
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO0 0xa4
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO1 0xa8
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO2 0xac
#define FMUX_GPIO_REG_IOCTRL_CLK32K 0xb0
#define FMUX_GPIO_REG_IOCTRL_CLK25M 0xb4
#define FMUX_GPIO_REG_IOCTRL_IIC2_SCL 0xb8
#define FMUX_GPIO_REG_IOCTRL_IIC2_SDA 0xbc
#define FMUX_GPIO_REG_IOCTRL_UART2_TX 0xc0
#define FMUX_GPIO_REG_IOCTRL_UART2_RTS 0xc4
#define FMUX_GPIO_REG_IOCTRL_UART2_RX 0xc8
#define FMUX_GPIO_REG_IOCTRL_UART2_CTS 0xcc
#define FMUX_GPIO_REG_IOCTRL_SD1_D3 0xd0
#define FMUX_GPIO_REG_IOCTRL_SD1_D2 0xd4
#define FMUX_GPIO_REG_IOCTRL_SD1_D1 0xd8
#define FMUX_GPIO_REG_IOCTRL_SD1_D0 0xdc
#define FMUX_GPIO_REG_IOCTRL_SD1_CMD 0xe0
#define FMUX_GPIO_REG_IOCTRL_SD1_CLK 0xe4
#define FMUX_GPIO_REG_IOCTRL_RSTN 0xe8
#define FMUX_GPIO_REG_IOCTRL_PWM0_BUCK 0xec
#define FMUX_GPIO_REG_IOCTRL_ADC3 0xf0
#define FMUX_GPIO_REG_IOCTRL_ADC2 0xf4
#define FMUX_GPIO_REG_IOCTRL_ADC1 0xf8
#define FMUX_GPIO_REG_IOCTRL_USB_ID 0xfc
#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_EN 0x100
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE0 0x104
#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET 0x108
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE1 0x10c
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE2 0x110
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO 0x114
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI 0x118
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS 0x11c
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK 0x120
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP 0x124
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM 0x128
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP 0x12c
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM 0x130
#define FMUX_GPIO_REG_IOCTRL_VIVO_D10 0x134
#define FMUX_GPIO_REG_IOCTRL_VIVO_D9 0x138
#define FMUX_GPIO_REG_IOCTRL_VIVO_D8 0x13c
#define FMUX_GPIO_REG_IOCTRL_VIVO_D7 0x140
#define FMUX_GPIO_REG_IOCTRL_VIVO_D6 0x144
#define FMUX_GPIO_REG_IOCTRL_VIVO_D5 0x148
#define FMUX_GPIO_REG_IOCTRL_VIVO_D4 0x14c
#define FMUX_GPIO_REG_IOCTRL_VIVO_D3 0x150
#define FMUX_GPIO_REG_IOCTRL_VIVO_D2 0x154
#define FMUX_GPIO_REG_IOCTRL_VIVO_D1 0x158
#define FMUX_GPIO_REG_IOCTRL_VIVO_D0 0x15c
#define FMUX_GPIO_REG_IOCTRL_VIVO_CLK 0x160
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5N 0x164
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5P 0x168
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N 0x16c
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P 0x170
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N 0x174
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P 0x178
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N 0x17c
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P 0x180
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N 0x184
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P 0x188
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N 0x18c
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P 0x190
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM4 0x194
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP4 0x198
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM3 0x19c
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP3 0x1a0
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2 0x1a4
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2 0x1a8
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1 0x1ac
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1 0x1b0
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0 0x1b4
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0 0x1b8
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC 0x1bc
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC 0x1c0
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL 0x1c4
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR 0x1c8
#define FMUX_GPIO_REG_IOCTRL_GPIO_RTX 0x1cc
#define FMUX_GPIO_REG_IOCTRL_GPIO_ZQ 0x1d0
#define FMUX_GPIO_FUNCSEL_CAM_MCLK0 0x0
#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CAM_PD0 0x4
#define FMUX_GPIO_FUNCSEL_CAM_PD0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CAM_PD0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CAM_RST0 0x8
#define FMUX_GPIO_FUNCSEL_CAM_RST0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CAM_RST0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CAM_MCLK1 0xc
#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CAM_PD1 0x10
#define FMUX_GPIO_FUNCSEL_CAM_PD1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CAM_PD1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC3_SCL 0x14
#define FMUX_GPIO_FUNCSEL_IIC3_SCL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC3_SCL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC3_SDA 0x18
#define FMUX_GPIO_FUNCSEL_IIC3_SDA_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC3_SDA_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_CLK 0x1c
#define FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_CMD 0x20
#define FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CMD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D0 0x24
#define FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D1 0x28
#define FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D2 0x2c
#define FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D3 0x30
#define FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_CD 0x34
#define FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN 0x38
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPK_EN 0x3c
#define FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPK_EN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART0_TX 0x40
#define FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART0_TX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART0_RX 0x44
#define FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART0_RX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_RSTN 0x48
#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_DAT2 0x4c
#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_CLK 0x50
#define FMUX_GPIO_FUNCSEL_EMMC_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_DAT0 0x54
#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_DAT3 0x58
#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_CMD 0x5c
#define FMUX_GPIO_FUNCSEL_EMMC_CMD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_CMD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_EMMC_DAT1 0x60
#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS 0x64
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK 0x68
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST 0x6c
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_OFFSET 0
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC0_SCL 0x70
#define FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC0_SDA 0x74
#define FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK 0x7
#define FMUX_GPIO_FUNCSEL_AUX0 0x78
#define FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_AUX0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET 0x7c
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_RSTN 0x80
#define FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1 0x84
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2 0x88
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_SEQ3 0x8c
#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0 0x90
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1 0x94
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1 0x98
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_ON 0x9c
#define FMUX_GPIO_FUNCSEL_PWR_ON_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_ON_MASK 0x7
#define FMUX_GPIO_FUNCSEL_XTAL_XIN 0xa0
#define FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0 0xa4
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1 0xa8
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2 0xac
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CLK32K 0xb0
#define FMUX_GPIO_FUNCSEL_CLK32K_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CLK32K_MASK 0x7
#define FMUX_GPIO_FUNCSEL_CLK25M 0xb4
#define FMUX_GPIO_FUNCSEL_CLK25M_OFFSET 0
#define FMUX_GPIO_FUNCSEL_CLK25M_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC2_SCL 0xb8
#define FMUX_GPIO_FUNCSEL_IIC2_SCL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC2_SCL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC2_SDA 0xbc
#define FMUX_GPIO_FUNCSEL_IIC2_SDA_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC2_SDA_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART2_TX 0xc0
#define FMUX_GPIO_FUNCSEL_UART2_TX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART2_TX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART2_RTS 0xc4
#define FMUX_GPIO_FUNCSEL_UART2_RTS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART2_RTS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART2_RX 0xc8
#define FMUX_GPIO_FUNCSEL_UART2_RX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART2_RX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART2_CTS 0xcc
#define FMUX_GPIO_FUNCSEL_UART2_CTS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART2_CTS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D3 0xd0
#define FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D2 0xd4
#define FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D1 0xd8
#define FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D0 0xdc
#define FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_CMD 0xe0
#define FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_CMD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_CLK 0xe4
#define FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_RSTN 0xe8
#define FMUX_GPIO_FUNCSEL_RSTN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_RSTN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK 0xec
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_ADC3 0xf0
#define FMUX_GPIO_FUNCSEL_ADC3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_ADC3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_ADC2 0xf4
#define FMUX_GPIO_FUNCSEL_ADC2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_ADC2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_ADC1 0xf8
#define FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_ADC1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_USB_ID 0xfc
#define FMUX_GPIO_FUNCSEL_USB_ID_OFFSET 0
#define FMUX_GPIO_FUNCSEL_USB_ID_MASK 0x7
#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN 0x100
#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0 0x104
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET 0x108
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1 0x10c
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2 0x110
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO 0x114
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI 0x118
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS 0x11c
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK 0x120
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP 0x124
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM 0x128
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP 0x12c
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM 0x130
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D10 0x134
#define FMUX_GPIO_FUNCSEL_VIVO_D10_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D10_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D9 0x138
#define FMUX_GPIO_FUNCSEL_VIVO_D9_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D9_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D8 0x13c
#define FMUX_GPIO_FUNCSEL_VIVO_D8_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D8_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D7 0x140
#define FMUX_GPIO_FUNCSEL_VIVO_D7_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D7_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D6 0x144
#define FMUX_GPIO_FUNCSEL_VIVO_D6_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D6_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D5 0x148
#define FMUX_GPIO_FUNCSEL_VIVO_D5_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D5_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D4 0x14c
#define FMUX_GPIO_FUNCSEL_VIVO_D4_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D4_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D3 0x150
#define FMUX_GPIO_FUNCSEL_VIVO_D3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D2 0x154
#define FMUX_GPIO_FUNCSEL_VIVO_D2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D1 0x158
#define FMUX_GPIO_FUNCSEL_VIVO_D1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_D0 0x15c
#define FMUX_GPIO_FUNCSEL_VIVO_D0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_D0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_VIVO_CLK 0x160
#define FMUX_GPIO_FUNCSEL_VIVO_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_VIVO_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N 0x164
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P 0x168
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N 0x16c
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P 0x170
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N 0x174
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P 0x178
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N 0x17c
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P 0x180
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N 0x184
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P 0x188
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N 0x18c
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P 0x190
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4 0x194
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4 0x198
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3 0x19c
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3 0x1a0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2 0x1a4
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2 0x1a8
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1 0x1ac
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1 0x1b0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0 0x1b4
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0 0x1b8
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC 0x1bc
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC 0x1c0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL 0x1c4
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR 0x1c8
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK 0x7
#define FMUX_GPIO_FUNCSEL_GPIO_RTX 0x1cc
#define FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ 0x1d0
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK 0x7
#endif /* __CV181X_REG_FMUX_GPIO_H__ */

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u-boot-2021.10/board/cvitek/cv181x/sdhci_reg.h Normal file
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#ifndef _SDHCI_REG_H
#define _SDHCI_REG_H
#include "cv181x_reg.h"
#define REG_TOP_SD_PWRSW_CTRL (0x1F4)
#define REG_SDIO0_PAD_MASK (0xFFFFFFF3)
#define REG_SDIO0_PAD_SHIFT (2)
#define REG_SDIO0_PAD_CLR_MASK (0xC)
#define REG_SDIO0_CD_PAD_REG (PINMUX_BASE + 0x900)
#define REG_SDIO0_CD_PAD_VALUE (1)
#define REG_SDIO0_CD_PAD_RESET (1)
#define REG_SDIO0_PWR_EN_PAD_REG (PINMUX_BASE + 0x904)
#define REG_SDIO0_PWR_EN_PAD_VALUE (2)
#define REG_SDIO0_PWR_EN_PAD_RESET (2)
#define REG_SDIO0_CLK_PAD_REG (PINMUX_BASE + 0xA00)
#define REG_SDIO0_CLK_PAD_VALUE (2)
#define REG_SDIO0_CLK_PAD_RESET (2)
#define REG_SDIO0_CMD_PAD_REG (PINMUX_BASE + 0xA04)
#define REG_SDIO0_CMD_PAD_VALUE (1)
#define REG_SDIO0_CMD_PAD_RESET (2)
#define REG_SDIO0_DAT0_PAD_REG (PINMUX_BASE + 0xA08)
#define REG_SDIO0_DAT0_PAD_VALUE (1)
#define REG_SDIO0_DAT0_PAD_RESET (2)
#define REG_SDIO0_DAT1_PAD_REG (PINMUX_BASE + 0xA0C)
#define REG_SDIO0_DAT1_PAD_VALUE (1)
#define REG_SDIO0_DAT1_PAD_RESET (2)
#define REG_SDIO0_DAT2_PAD_REG (PINMUX_BASE + 0xA10)
#define REG_SDIO0_DAT2_PAD_VALUE (1)
#define REG_SDIO0_DAT2_PAD_RESET (2)
#define REG_SDIO0_DAT3_PAD_REG (PINMUX_BASE + 0xA14)
#define REG_SDIO0_DAT3_PAD_VALUE (1)
#define REG_SDIO0_DAT3_PAD_RESET (2)
#define PAD_SDIO0_CD_REG (PINMUX_BASE + 0x34)
#define PAD_SDIO0_PWR_EN_REG (PINMUX_BASE + 0x38)
#define PAD_SDIO0_CLK_REG (PINMUX_BASE + 0x1C)
#define PAD_SDIO0_CMD_REG (PINMUX_BASE + 0x20)
#define PAD_SDIO0_D0_REG (PINMUX_BASE + 0x24)
#define PAD_SDIO0_D1_REG (PINMUX_BASE + 0x28)
#define PAD_SDIO0_D2_REG (PINMUX_BASE + 0x2C)
#define PAD_SDIO0_D3_REG (PINMUX_BASE + 0x30)
#define REG_SDIO1_PAD_MASK (0xFFFFFFF3)
#define REG_SDIO1_PAD_SHIFT (2)
#define SDIO1_PAD_BASE 0x05027000
#define REG_SDIO1_PAD_CLR_MASK (0xC)
#define REG_SDIO1_CLK_PAD_REG (SDIO1_PAD_BASE + 0x06C)
#define REG_SDIO1_CLK_PAD_VALUE (2)
#define REG_SDIO1_CMD_PAD_REG (SDIO1_PAD_BASE + 0x068)
#define REG_SDIO1_CMD_PAD_VALUE (1)
#define REG_SDIO1_DAT0_PAD_REG (SDIO1_PAD_BASE + 0x064)
#define REG_SDIO1_DAT0_PAD_VALUE (1)
#define REG_SDIO1_DAT2_PAD_REG (SDIO1_PAD_BASE + 0x05C)
#define REG_SDIO1_DAT2_PAD_VALUE (1)
#define REG_SDIO1_DAT1_PAD_REG (SDIO1_PAD_BASE + 0x060)
#define REG_SDIO1_DAT1_PAD_VALUE (1)
#define REG_SDIO1_DAT3_PAD_REG (SDIO1_PAD_BASE + 0x058)
#define REG_SDIO1_DAT3_PAD_VALUE (1)
#define REG_EMMC_PAD_CLR_MASK (0xC)
#define REG_EMMC_PAD_SHIFT (2)
#define REG_EMMC_RSTN_PAD_REG (PINMUX_BASE + 0x914)
#define REG_EMMC_RSTN_PAD_VALUE (1)
#define REG_EMMC_CLK_PAD_REG (PINMUX_BASE + 0x91c)
#define REG_EMMC_CLK_PAD_VALUE (2)
#define REG_EMMC_CMD_PAD_REG (PINMUX_BASE + 0x928)
#define REG_EMMC_CMD_PAD_VALUE (1)
#define REG_EMMC_DAT0_PAD_REG (PINMUX_BASE + 0x920)
#define REG_EMMC_DAT0_PAD_VALUE (1)
#define REG_EMMC_DAT1_PAD_REG (PINMUX_BASE + 0x92C)
#define REG_EMMC_DAT1_PAD_VALUE (1)
#define REG_EMMC_DAT2_PAD_REG (PINMUX_BASE + 0x918)
#define REG_EMMC_DAT2_PAD_VALUE (1)
#define REG_EMMC_DAT3_PAD_REG (PINMUX_BASE + 0x924)
#define REG_EMMC_DAT3_PAD_VALUE (1)
#define CVI_SDHCI_VENDOR_OFFSET 0x200
#define CVI_SDHCI_PHY_TX_RX_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_PHY_DS_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x44)
#define CVI_SDHCI_PHY_DLY_STS (CVI_SDHCI_VENDOR_OFFSET + 0x48)
#define CVI_SDHCI_PHY_CONFIG (CVI_SDHCI_VENDOR_OFFSET + 0x4C)
#define CVI_SDHCI_BIT_CLK_FREE_EN 2
#define CVI_SDHCI_CLK_FREE_EN_VALUE 0
#define CVI_SDHCI_CLK_FREE_EN_MASK 0xFFFFFFFB
#define CVI_SDHCI_VENDOR_MSHC_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x0)
#define CVI_SDHCI_PHY_RX_DLY_SHIFT 16
// Bit 16~22
#define CVI_SDHCI_PHY_RX_DLY_MASK 0x7F0000
#define CVI_SDHCI_PHY_TX_RX_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_PHY_RX_SRC_BIT_1 24
#define CVI_SDHCI_PHY_RX_SRC_BIT_2 25
#define SDHCI_PHY_CONFIG \
(CVI_SDHCI_VENDOR_OFFSET + \
0x4C) // P_VERDOR_SPECIFIC_AREA + 0x4c0x24c( PHY_TX_BPS )
#define REG_TX_BPS_SEL_MASK 0xFFFFFFFE
#define REG_TX_BPS_SEL_CLR_MASK (0x1) // 0x24c PHY_TX_BPS
#define REG_TX_BPS_SEL_SHIFT (0) // 0x24c PHY_TX_BPS
#define REG_TX_BPS_SEL_BYPASS (1) // 0x24c PHY_TX_BPS inv
#define MMC_MAX_CLOCK (375000000)
#define MMC_MAX_CLOCK_DIV_VALUE (0x40009)
#define CLOCK_BYPASS_SELECT_REGISTER (0x3002030)
#define MAX_TUNING_CMD_RETRY_COUNT 50
#define TUNE_MAX_PHCODE 128
#define TAP_WINDOW_THLD 20
#endif

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if TARGET_CVITEK_CV1822
choice
prompt "Cvitek CV1822 verification platform type select"
config TARGET_CVITEK_CV1822_ASIC
bool "ASIC"
help
This enables support for Cvitek's CV1822 SoC on ASIC platform.
If unsure, say N.
config TARGET_CVITEK_CV1822_PALLADIUM
bool "Palladium"
help
This enables support for Cvitek's CV1822 SoC on PALLADIUM platform.
If unsure, say N.
config TARGET_CVITEK_CV1822_FPGA
bool "FPGA"
help
This enables support for Cvitek's CV1822 SoC on FPGA platform.
If unsure, say N.
endchoice
config SYS_BOARD
default "cv1822"
config SYS_VENDOR
default "cvitek"
config SYS_CONFIG_NAME
default "cv1822-asic" if TARGET_CVITEK_CV1822_ASIC
default "cv1822-palladium" if TARGET_CVITEK_CV1822_PALLADIUM
default "cv1822-fpga" if TARGET_CVITEK_CV1822_FPGA
config SYS_BOOTMAPSZ
hex "Maximum size of memory mapped"
default "0x8000000"
endif

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CV1822 BOARD
M: Myles Tsai <myles.tsai@wisecore.com.tw>
S: Maintained
F: board/armltd/vexpress64/

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obj-y := board.o

418
u-boot-2021.10/board/cvitek/cv1822/board.c Normal file
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/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
* Sharma Bhupesh <bhupesh.sharma@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <dm/platform_data/serial_pl01x.h>
#include <asm/armv8/mmu.h>
#include <mmio.h>
#include <usb/dwc2_udc.h>
#include <usb.h>
#include "cv1822_reg.h"
#include "cvi_reboot.h"
#include "cv1822_reg_fmux_gpio.h"
#include "cv1822_pinlist_swconfig.h"
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_PL011_SERIAL
static const struct pl01x_serial_platdata serial_platdata = {
.base = V2M_UART0,
.type = TYPE_PL011,
.clock = CONFIG_PL011_CLOCK,
};
U_BOOT_DEVICE(vexpress_serials) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
};
#endif
static struct mm_region vexpress64_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = PHYS_SDRAM_1,
.phys = PHYS_SDRAM_1,
.size = PHYS_SDRAM_1_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
#ifdef BM_UPDATE_FW_START_ADDR
}, {
.virt = BM_UPDATE_FW_START_ADDR,
.phys = BM_UPDATE_FW_START_ADDR,
/*
* this area is for bmtest under uboot. -- added by Xun Li
* [0x110000000, 0x190000000] size = 2G
*/
.size = BM_UPDATE_FW_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
#else
}, {
/*
* be aware we'll need 256MB more other than PHYS_SDRAM_1_SIZE for the fake flash area
* of itb file during ram boot, and MMC's DMA buffer (BM_UPDATE_ALIGNED_BUFFER).
* so either cover it here or in video's region.
* also be carefull with BM_SPIF_BUFFER_ADDR and BM_UPDATE_FW_START_ADDR...
*/
.virt = PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE,
.phys = PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE,
.size = 0x10000000,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
#endif
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = vexpress64_mem_map;
// #define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) printf ("%s\n", PIN_NAME ##_ ##FUNC_NAME);
#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
mmio_clrsetbits_32(PINMUX_BASE + fmux_gpio_funcsel_##PIN_NAME, \
fmux_gpio_funcsel_##PIN_NAME##_MASK << fmux_gpio_funcsel_##PIN_NAME##_OFFSET, \
PIN_NAME##__##FUNC_NAME)
static void pinmux_config(int io_type)
{
switch (io_type) {
case PINMUX_UART0:
PINMUX_CONFIG(UART0_RX, UART0_RX);
PINMUX_CONFIG(UART0_TX, UART0_TX);
break;
case PINMUX_I2S1:
PINMUX_CONFIG(PAD_AUD_AOUTR, IIS1_DI);
PINMUX_CONFIG(AUX0, IIS1_MCLK);
PINMUX_CONFIG(PAD_AUD_AINR_MIC, IIS1_DO);
PINMUX_CONFIG(PAD_AUD_AINL_MIC, IIS1_BCLK);
PINMUX_CONFIG(PAD_AUD_AOUTL, IIS1_LRCK);
break;
case PINMUX_I2S2:
PINMUX_CONFIG(UART2_RX, IIS2_DI);
PINMUX_CONFIG(IIC2_SDA, IIS2_MCLK);
PINMUX_CONFIG(UART2_RTS, IIS2_DO);
PINMUX_CONFIG(UART2_TX, IIS2_BCLK);
PINMUX_CONFIG(UART2_CTS, IIS2_LRCK);
break;
case PINMUX_EMMC:
PINMUX_CONFIG(EMMC_RSTN, EMMC_RSTN);
PINMUX_CONFIG(EMMC_DAT2, EMMC_DAT_2);
PINMUX_CONFIG(EMMC_CLK, EMMC_CLK);
PINMUX_CONFIG(EMMC_DAT0, EMMC_DAT_0);
PINMUX_CONFIG(EMMC_DAT3, EMMC_DAT_3);
PINMUX_CONFIG(EMMC_CMD, EMMC_CMD);
PINMUX_CONFIG(EMMC_DAT1, EMMC_DAT_1);
break;
case PINMUX_SPI_NOR:
PINMUX_CONFIG(EMMC_CLK, SPINOR_SCK);
PINMUX_CONFIG(EMMC_CMD, SPINOR_MISO);
PINMUX_CONFIG(EMMC_DAT1, SPINOR_CS_X);
PINMUX_CONFIG(EMMC_DAT0, SPINOR_MOSI);
PINMUX_CONFIG(EMMC_DAT2, SPINOR_HOLD_X);
PINMUX_CONFIG(EMMC_DAT3, SPINOR_WP_X);
break;
case PINMUX_SPI_NAND:
PINMUX_CONFIG(EMMC_DAT2, SPINAND_HOLD);
PINMUX_CONFIG(EMMC_CLK, SPINAND_CLK);
PINMUX_CONFIG(EMMC_DAT0, SPINAND_MOSI);
PINMUX_CONFIG(EMMC_DAT3, SPINAND_WP);
PINMUX_CONFIG(EMMC_CMD, SPINAND_MISO);
PINMUX_CONFIG(EMMC_DAT1, SPINAND_CS);
break;
case PINMUX_SDIO1:
PINMUX_CONFIG(SD1_CMD, PWR_SD1_CMD);
PINMUX_CONFIG(SD1_CLK, PWR_SD1_CLK);
PINMUX_CONFIG(SD1_D0, PWR_SD1_D0);
PINMUX_CONFIG(SD1_D1, PWR_SD1_D1);
PINMUX_CONFIG(SD1_D2, PWR_SD1_D2);
PINMUX_CONFIG(SD1_D3, PWR_SD1_D3);
break;
case PINMUX_DSI:
#if (defined(CV1822_WDMB_0004A_SPINAND) || defined(CV1822_WDMB_0004B_SPINAND))
// no panel
#elif (defined(CV1822_WEVB_0005B_SPINAND) || defined(CV1822_WEVB_0005B_64MB_SPINAND))
PINMUX_CONFIG(PAD_MIPI_TXM0, XGPIOC_12);
PINMUX_CONFIG(PAD_MIPI_TXP0, XGPIOC_13);
PINMUX_CONFIG(PAD_MIPI_TXM1, XGPIOC_14);
PINMUX_CONFIG(PAD_MIPI_TXP1, XGPIOC_15);
PINMUX_CONFIG(PAD_MIPI_TXM2, XGPIOC_16);
PINMUX_CONFIG(PAD_MIPI_TXP2, XGPIOC_17);
#else
PINMUX_CONFIG(PAD_MIPI_TXM0, XGPIOC_12);
PINMUX_CONFIG(PAD_MIPI_TXP0, XGPIOC_13);
PINMUX_CONFIG(PAD_MIPI_TXM1, XGPIOC_14);
PINMUX_CONFIG(PAD_MIPI_TXP1, XGPIOC_15);
PINMUX_CONFIG(PAD_MIPI_TXM2, XGPIOC_16);
PINMUX_CONFIG(PAD_MIPI_TXP2, XGPIOC_17);
PINMUX_CONFIG(PAD_MIPI_TXM3, XGPIOC_20);
PINMUX_CONFIG(PAD_MIPI_TXP3, XGPIOC_21);
PINMUX_CONFIG(PAD_MIPI_TXM4, XGPIOC_18);
PINMUX_CONFIG(PAD_MIPI_TXP4, XGPIOC_19);
#endif
break;
default:
break;
}
}
void config_pinmux_for_low_power(void)
{
#if 0
// Board-dependent settings
mmio_write_32(0x03001090, 0x03); // Set PWR_WAKEUP0 to GPIO
mmio_write_32(0x03001094, 0x03); // Set PWR_WAKEUP1 to GPIO
mmio_write_32(0x0300109C, 0x03); // Set PWR_ON to GPIO
mmio_write_32(0x030010B0, 0x03); // Set CLK32K to GPIO
mmio_write_32(0x030010B4, 0x03); // Set CLK25M to GPIO
mmio_write_32(0x05027008, 0x40); // PWR_SEQ1: remove PD
mmio_write_32(0x0502700C, 0x40); // PWR_SEQ2: remove PD
mmio_write_32(0x05027010, 0x40); // PWR_SEQ3: remove PD
mmio_write_32(0x05027018, 0x40); // PWR_WAKEUP0: remove PD, on board PU VDDIO_RTC
mmio_write_32(0x0502701C, 0x40); // PWR_WAKEUP1: remove PD, on board PU VDDIO_RTC
mmio_write_32(0x05027024, 0x40); // PWR_ON: remove PD
mmio_write_32(0x05027034, 0x40); // PWR_GPIO[2]: remove PD, on board PU VDDIO_WIFI
mmio_write_32(0x05027038, 0x40); // CLK32K: remove PD, on board PU VDDIO_RTC
mmio_write_32(0x0502703C, 0x40); // CLK25M: remove PD, on board PU VDDIO_RTC
mmio_write_32(0x05027040, 0x40); // IIC2_SCL: remove PD, on board PU VDDIO_WIFI
mmio_write_32(0x05027044, 0x40); // IIC2_SDA: remove PD, on board PU VDDIO_WIFI
mmio_write_32(0x0502704C, 0x40); // UART2_RTS: remove PD, on board PU VDDIO_WIFI
mmio_write_32(0x05027054, 0x40); // UART2_CTS: remove PD, on board PU VDDIO_WIFI
mmio_write_32(0x05027030, 0x44); // PWR_GPIO[1]: pull up
mmio_clrbits_32(0x05021000, 0x1 << 1); // Set PWR_GPIO[1] to input
mmio_clrbits_32(0x05021004, 0x1 << 1); // Set PWR_GPIO[1] to input
#endif
}
void enable_pwr_drop_protection(void)
{
mmio_setbits_32(TOP_BASE + 0x22C, 0x3);
}
#ifdef CONFIG_CMD_CVI_SAPD
static void config_rtc_ctrl_for_low_power(void)
{
mmio_write_32(0x05025084, 0x00030003); // m51 iso_en, sd_iso_en
mmio_write_32(0x05025080, 0x00000003); // m51 power down , sd power up
mmio_write_32(0x05025084, 0x00030002); // m51 iso en and sd iso dis
mmio_write_32(0x05025098, 0x000009A6); // sd sram power up
mmio_write_32(0x05025034, 0x06450036); // sd clock en
//info("Drc_lp\n");
}
#endif
#include "../cvi_board_init.c"
// #define CV182X_RTC_EXTERNAL_32K
int board_init(void)
{
#if defined(CONFIG_TARGET_CVITEK_CV1822_ASIC) /* config eth internal phy on ASIC board */
unsigned int val;
val = readl(0x03009000) & ETH_PHY_INIT_MASK;
writel((val | ETH_PHY_SHUTDOWN) & ETH_PHY_RESET, 0x03009000);
mdelay(1);
writel(val & ETH_PHY_POWERUP & ETH_PHY_RESET, 0x03009000);
mdelay(20);
writel((val & ETH_PHY_POWERUP) | ETH_PHY_RESET_N, 0x03009000);
mdelay(1);
#endif
/* Set ethernet clock resource */
#if defined(CONFIG_TARGET_CVITEK_CV1835_FPGA)
writel(0x000000C0, 0x03000034); /* Set eth0 RGMII, eth1 RMII clk resource and interface type*/
#elif defined(CONFIG_TARGET_CVITEK_CV1835_ASIC)
writel(0x00000004, 0x03000034); /* Set eth0 RMII, eth1 RGMII clk resource and interface type*/
#elif defined(CONFIG_TARGET_CVITEK_CV1835_PALLADIUM)
writel(0x00000004, 0x03000034); /* Set eth0 RMII, eth1 RGMII clk resource and interface type*/
#endif
#ifdef CONFIG_CMD_CVI_SAPD
mmio_write_32(RTC_INFO0, CVI_SAPD_FLAG);
config_rtc_ctrl_for_low_power();
#endif
enable_pwr_drop_protection();
#if defined(CONFIG_NAND_SUPPORT)
pinmux_config(PINMUX_SPI_NAND);
#elif defined(CONFIG_SPI_FLASH)
pinmux_config(PINMUX_SPI_NOR);
#elif defined(CONFIG_EMMC_SUPPORT)
pinmux_config(PINMUX_EMMC);
#endif
#ifdef CONFIG_DISPLAY_CVITEK_MIPI
pinmux_config(PINMUX_DSI);
#endif
#if defined(CV1822_WDMB_0002A_SPINAND)
PINMUX_CONFIG(JTAG_CPU_TCK, XGPIOA_18); //IIC2_SHDN
PINMUX_CONFIG(JTAG_CPU_TMS, XGPIOA_19);//AMP_MUTE
#elif (defined(CV1822_WEVB_0005B_SPINAND) || defined(CV1822_WEVB_0005B_64MB_SPINAND))
PINMUX_CONFIG(SPK_EN, XGPIOA_15);
PINMUX_CONFIG(JTAG_CPU_TCK, XGPIOA_18);
PINMUX_CONFIG(JTAG_CPU_TMS, XGPIOA_19);//AMP_MUTE
#elif defined(CV1822_WDMB_0001A_SPINAND)
PINMUX_CONFIG(UART1_RX, UART1_RX); //UART_RX,TX,CTS
PINMUX_CONFIG(UART1_TX, UART1_TX);
PINMUX_CONFIG(UART1_CTS, UART1_CTS);
#endif
#if defined(CONFIG_MMC_SDHCI_CVITEK_WIFI)
pinmux_config(PINMUX_SDIO1);
#else
/* If not support wifi, then switch pinmux to enable LED */
PINMUX_CONFIG(SD1_CMD, EPHY_LNK_LED);
PINMUX_CONFIG(SD1_CLK, EPHY_SPD_LED);
#endif
#if (defined(CV1822_WDMB_0004A_SPINAND) || defined(CV1822_WDMB_0004B_SPINAND))
PINMUX_CONFIG(PAD_MIPI_TXP0, CAM_MCLK0);
PINMUX_CONFIG(PAD_MIPI_TXM0, XGPIOC_12);
PINMUX_CONFIG(IIC2_SCL, PWR_GPIO_12);
PINMUX_CONFIG(IIC2_SDA, PWR_GPIO_13);
PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL);
PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA);
PINMUX_CONFIG(PAD_MIPI_TXP2, XGPIOC_17);
#elif (defined(CV1821_WEVB_0005B_SPINAND) || \
defined(CV1822_WEVB_0005B_128MB_SPINAND) || \
defined(CV1822_WEVB_0005B_64MB_SPINAND) || \
defined(CV1822_WEVB_0005B_SPINAND)) || \
defined(CV1822_WEVB_0005B_SPINOR) || \
defined(CV1821_WEVB_0005B_SPINOR) || \
defined(CV1821_WEVB_0005B_64MB_SPINOR) || \
defined(CV1820_WEVB_0005B_SPINOR)
PINMUX_CONFIG(PAD_MIPI_TXP0, XGPIOC_13);
PINMUX_CONFIG(PAD_MIPI_TXM0, CAM_MCLK1);
PINMUX_CONFIG(IIC2_SCL, PWR_GPIO_12);
PINMUX_CONFIG(IIC2_SDA, PWR_GPIO_13);
PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL);
PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA);
#elif defined(CV1822_WDMB_0004C_SPINAND)
PINMUX_CONFIG(SD1_CMD, PWR_GPIO_22); //PANEL RESET
PINMUX_CONFIG(SD1_D0, IIC1_SDA); //IIC1 SDA
PINMUX_CONFIG(SD1_D3, IIC1_SCL); //IIC1 SCL
PINMUX_CONFIG(SD1_D2, CAM_MCLK0); //MCLK
PINMUX_CONFIG(SD1_D1, PWR_GPIO_20); //CAM RESET
PINMUX_CONFIG(SD1_CLK, PWR_GPIO_23); //PWDN
#else
PINMUX_CONFIG(IIC2_SCL, IIC2_SCL); //IIC2
PINMUX_CONFIG(IIC2_SDA, IIC2_SDA);
#endif
#if 0
#ifdef CONFIG_PWM_CVITEK
PINMUX_CONFIG(IIC2_SCL, PWM_14);//PWM_14
PINMUX_CONFIG(IIC2_SDA, PWM_15);//PWM_15
PINMUX_CONFIG(PWM0_BUCK, PWM_0);//PWM_0
#endif
#endif
cvi_board_init();
config_pinmux_for_low_power();
return 0;
}
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
void software_root_reset(void)
{
// clear spinand sv vec in case stuck at next boot.
mmio_setbits_32(CLKGEN_BASE, BIT(4)); // Enable clk_tpu
memset((void *)BM_IO_BUF_BASE, 0x0, BM_IO_BUF_SIZE); //8KB
mmio_write_32(REG_RTC_BASE + RTC_EN_WARM_RST_REQ, 0x01);
while (mmio_read_32(REG_RTC_BASE + RTC_EN_WARM_RST_REQ) != 0x01)
;
mmio_write_32(REG_RTC_CTRL_BASE + RTC_CTRL0_UNLOCKKEY, 0xAB18);
mmio_setbits_32(REG_RTC_CTRL_BASE + RTC_CTRL0, 0xFFFF0800 | (0x1 << 4));
while (1)
;
}
void reset_cpu(void)
{
}
/*
* Board specific ethernet initialization routine.
*/
#if 0
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}
#endif
#ifdef CONFIG_USB_GADGET_DWC2_OTG
struct dwc2_plat_otg_data cv182x_otg_data = {
.regs_otg = USB_BASE,
.usb_gusbcfg = 0x40081400,
.rx_fifo_sz = 512,
.np_tx_fifo_sz = 512,
.tx_fifo_sz = 512,
};
int board_usb_init(int index, enum usb_init_type init)
{
uint32_t value;
value = mmio_read_32(TOP_BASE + REG_TOP_SOFT_RST) & (~BIT_TOP_SOFT_RST_USB);
mmio_write_32(TOP_BASE + REG_TOP_SOFT_RST, value);
udelay(50);
value = mmio_read_32(TOP_BASE + REG_TOP_SOFT_RST) | BIT_TOP_SOFT_RST_USB;
mmio_write_32(TOP_BASE + REG_TOP_SOFT_RST, value);
/* Set USB phy configuration */
value = mmio_read_32(REG_TOP_USB_PHY_CTRL);
mmio_write_32(REG_TOP_USB_PHY_CTRL, value | BIT_TOP_USB_PHY_CTRL_EXTVBUS
| USB_PHY_ID_OVERRIDE_ENABLE
| USB_PHY_ID_VALUE);
/* Enable ECO RXF */
mmio_write_32(REG_TOP_USB_ECO, mmio_read_32(REG_TOP_USB_ECO) | BIT_TOP_USB_ECO_RX_FLUSH);
printf("cvi_usb_hw_init done\n");
return dwc2_udc_probe(&cv182x_otg_data);
}
#endif

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: cv18322_pinlist_swconfig.h
* Description:
*/
#ifndef __CV1822_PINLIST_SWCONFIG_H__
#define __CV1822_PINLIST_SWCONFIG_H__
//##==============================================================================
//##=== This script is generate by genswconfig.pl from .\00_Mercury_Pinlist_20200819_SPEPHY.xls
//##=== Generate Time stamp is : 2020-08-20 11:01:40
//##==============================================================================
#define CAM_MCLK0__CAM_MCLK0 0
#define CAM_MCLK0__AUX1 2
#define CAM_MCLK0__XGPIOA_0 3
#define CAM_PD0__IIS1_MCLK 1
#define CAM_PD0__XGPIOA_1 3
#define CAM_RST0__XGPIOA_2 3
#define CAM_RST0__IIC4_SCL 6
#define CAM_MCLK1__CAM_MCLK1 0
#define CAM_MCLK1__AUX2 2
#define CAM_MCLK1__XGPIOA_3 3
#define CAM_PD1__IIS1_MCLK 1
#define CAM_PD1__XGPIOA_4 3
#define CAM_PD1__IIC4_SDA 6
#define IIC3_SCL__IIC3_SCL 0
#define IIC3_SCL__XGPIOA_5 3
#define IIC3_SDA__IIC3_SDA 0
#define IIC3_SDA__XGPIOA_6 3
#define SD0_CLK__SDIO0_CLK 0
#define SD0_CLK__IIC1_SDA 1
#define SD0_CLK__SPI0_SCK 2
#define SD0_CLK__XGPIOA_7 3
#define SD0_CLK__PWM_15 5
#define SD0_CLK__EPHY_LNK_LED 6
#define SD0_CLK__DBG_0 7
#define SD0_CMD__SDIO0_CMD 0
#define SD0_CMD__IIC1_SCL 1
#define SD0_CMD__SPI0_SDO 2
#define SD0_CMD__XGPIOA_8 3
#define SD0_CMD__PWM_14 5
#define SD0_CMD__EPHY_SPD_LED 6
#define SD0_CMD__DBG_1 7
#define SD0_D0__SDIO0_D_0 0
#define SD0_D0__CAM_MCLK1 1
#define SD0_D0__SPI0_SDI 2
#define SD0_D0__XGPIOA_9 3
#define SD0_D0__UART3_TX 4
#define SD0_D0__PWM_13 5
#define SD0_D0__WG0_D0 6
#define SD0_D0__DBG_2 7
#define SD0_D1__SDIO0_D_1 0
#define SD0_D1__IIC1_SDA 1
#define SD0_D1__AUX0 2
#define SD0_D1__XGPIOA_10 3
#define SD0_D1__UART1_TX 4
#define SD0_D1__PWM_12 5
#define SD0_D1__WG0_D1 6
#define SD0_D1__DBG_3 7
#define SD0_D2__SDIO0_D_2 0
#define SD0_D2__IIC1_SCL 1
#define SD0_D2__AUX1 2
#define SD0_D2__XGPIOA_11 3
#define SD0_D2__UART1_RX 4
#define SD0_D2__PWM_11 5
#define SD0_D2__WG1_D0 6
#define SD0_D2__DBG_4 7
#define SD0_D3__SDIO0_D_3 0
#define SD0_D3__CAM_MCLK0 1
#define SD0_D3__SPI0_CS_X 2
#define SD0_D3__XGPIOA_12 3
#define SD0_D3__UART3_RX 4
#define SD0_D3__PWM_10 5
#define SD0_D3__WG1_D1 6
#define SD0_D3__DBG_5 7
#define SD0_CD__SDIO0_CD 0
#define SD0_CD__XGPIOA_13 3
#define SD0_PWR_EN__SDIO0_PWR_EN 0
#define SD0_PWR_EN__XGPIOA_14 3
#define SPK_EN__XGPIOA_15 3
#define UART0_TX__UART0_TX 0
#define UART0_TX__CAM_MCLK1 1
#define UART0_TX__PWM_4 2
#define UART0_TX__XGPIOA_16 3
#define UART0_TX__UART1_TX 4
#define UART0_TX__AUX1 5
#define UART0_TX__DBG_6 7
#define UART0_RX__UART0_RX 0
#define UART0_RX__CAM_MCLK0 1
#define UART0_RX__PWM_5 2
#define UART0_RX__XGPIOA_17 3
#define UART0_RX__UART1_RX 4
#define UART0_RX__AUX0 5
#define UART0_RX__DBG_7 7
#define EMMC_RSTN__EMMC_RSTN 0
#define EMMC_RSTN__XGPIOA_21 3
#define EMMC_RSTN__AUX2 4
#define EMMC_DAT2__EMMC_DAT_2 0
#define EMMC_DAT2__SPINOR_HOLD_X 1
#define EMMC_DAT2__SPINAND_HOLD 2
#define EMMC_DAT2__XGPIOA_26 3
#define EMMC_CLK__EMMC_CLK 0
#define EMMC_CLK__SPINOR_SCK 1
#define EMMC_CLK__SPINAND_CLK 2
#define EMMC_CLK__XGPIOA_22 3
#define EMMC_DAT0__EMMC_DAT_0 0
#define EMMC_DAT0__SPINOR_MOSI 1
#define EMMC_DAT0__SPINAND_MOSI 2
#define EMMC_DAT0__XGPIOA_25 3
#define EMMC_DAT3__EMMC_DAT_3 0
#define EMMC_DAT3__SPINOR_WP_X 1
#define EMMC_DAT3__SPINAND_WP 2
#define EMMC_DAT3__XGPIOA_27 3
#define EMMC_CMD__EMMC_CMD 0
#define EMMC_CMD__SPINOR_MISO 1
#define EMMC_CMD__SPINAND_MISO 2
#define EMMC_CMD__XGPIOA_23 3
#define EMMC_DAT1__EMMC_DAT_1 0
#define EMMC_DAT1__SPINOR_CS_X 1
#define EMMC_DAT1__SPINAND_CS 2
#define EMMC_DAT1__XGPIOA_24 3
#define JTAG_CPU_TMS__JTAG_CPU_TMS 0
#define JTAG_CPU_TMS__CAM_MCLK0 1
#define JTAG_CPU_TMS__PWM_7 2
#define JTAG_CPU_TMS__XGPIOA_19 3
#define JTAG_CPU_TMS__UART1_RTS 4
#define JTAG_CPU_TMS__AUX0 5
#define JTAG_CPU_TMS__UART1_TX 6
#define JTAG_CPU_TMS__DBG_9 7
#define JTAG_CPU_TCK__JTAG_CPU_TCK 0
#define JTAG_CPU_TCK__CAM_MCLK1 1
#define JTAG_CPU_TCK__PWM_6 2
#define JTAG_CPU_TCK__XGPIOA_18 3
#define JTAG_CPU_TCK__UART1_CTS 4
#define JTAG_CPU_TCK__AUX1 5
#define JTAG_CPU_TCK__UART1_RX 6
#define JTAG_CPU_TCK__DBG_8 7
#define JTAG_CPU_TRST__JTAG_CPU_TRST 0
#define JTAG_CPU_TRST__XGPIOA_20 3
#define IIC0_SCL__IIC0_SCL 0
#define IIC0_SCL__UART1_TX 1
#define IIC0_SCL__UART2_TX 2
#define IIC0_SCL__XGPIOA_28 3
#define IIC0_SCL__WG0_D0 5
#define IIC0_SCL__DBG_10 7
#define IIC0_SDA__IIC0_SDA 0
#define IIC0_SDA__UART1_RX 1
#define IIC0_SDA__UART2_RX 2
#define IIC0_SDA__XGPIOA_29 3
#define IIC0_SDA__WG0_D1 5
#define IIC0_SDA__WG1_D0 6
#define IIC0_SDA__DBG_11 7
#define AUX0__AUX0 0
#define AUX0__XGPIOA_30 3
#define AUX0__IIS1_MCLK 4
#define AUX0__WG1_D1 6
#define AUX0__DBG_12 7
#define PWR_VBAT_DET__PWR_VBAT_DET 0
#define PWR_RSTN__PWR_RSTN 0
#define PWR_SEQ1__PWR_SEQ1 0
#define PWR_SEQ1__PWR_GPIO_3 3
#define PWR_SEQ2__PWR_SEQ2 0
#define PWR_SEQ2__PWR_GPIO_4 3
#define PWR_SEQ3__PWR_SEQ3 0
#define PWR_SEQ3__PWR_GPIO_5 3
#define PTEST__PWR_PTEST 0
#define PWR_WAKEUP0__PWR_WAKEUP0 0
#define PWR_WAKEUP0__PWR_UART0_TX 2
#define PWR_WAKEUP0__PWR_GPIO_6 3
#define PWR_WAKEUP0__UART1_TX 4
#define PWR_WAKEUP0__IIC4_SCL 5
#define PWR_WAKEUP0__EPHY_LNK_LED 6
#define PWR_WAKEUP0__WG2_D0 7
#define PWR_WAKEUP1__PWR_WAKEUP1 0
#define PWR_WAKEUP1__PWR_GPIO_7 3
#define PWR_WAKEUP1__UART1_TX 4
#define PWR_WAKEUP1__IIC4_SCL 5
#define PWR_WAKEUP1__EPHY_LNK_LED 6
#define PWR_WAKEUP1__WG0_D0 7
#define PWR_BUTTON1__PWR_BUTTON1 0
#define PWR_BUTTON1__PWR_GPIO_8 3
#define PWR_BUTTON1__UART1_RX 4
#define PWR_BUTTON1__IIC4_SDA 5
#define PWR_BUTTON1__EPHY_SPD_LED 6
#define PWR_BUTTON1__WG2_D1 7
#define PWR_ON__PWR_ON 0
#define PWR_ON__PWR_GPIO_9 3
#define PWR_ON__UART1_RX 4
#define PWR_ON__IIC4_SDA 5
#define PWR_ON__EPHY_SPD_LED 6
#define PWR_ON__WG0_D1 7
#define XTAL_XIN__PWR_XTAL_CLKIN 0
#define PWR_GPIO0__PWR_GPIO_0 0
#define PWR_GPIO0__UART2_TX 1
#define PWR_GPIO0__PWR_UART0_RX 2
#define PWR_GPIO0__PWM_8 4
#define PWR_GPIO1__PWR_GPIO_1 0
#define PWR_GPIO1__UART2_RX 1
#define PWR_GPIO1__EPHY_LNK_LED 3
#define PWR_GPIO1__PWM_9 4
#define PWR_GPIO1__PWR_IIC_SCL 5
#define PWR_GPIO1__IIC2_SCL 6
#define PWR_GPIO1__PWR_MCU_JTAG_TMS 7
#define PWR_GPIO2__PWR_GPIO_2 0
#define PWR_GPIO2__PWR_SECTICK 2
#define PWR_GPIO2__EPHY_SPD_LED 3
#define PWR_GPIO2__PWM_10 4
#define PWR_GPIO2__PWR_IIC_SDA 5
#define PWR_GPIO2__IIC2_SDA 6
#define PWR_GPIO2__PWR_MCU_JTAG_TCK 7
#define CLK32K__CLK32K 0
#define CLK32K__AUX0 1
#define CLK32K__PWR_MCU_JTAG_TDI 2
#define CLK32K__PWR_GPIO_10 3
#define CLK32K__PWM_2 4
#define CLK32K__KEY_COL0 5
#define CLK32K__CAM_MCLK0 6
#define CLK32K__DBG_0 7
#define CLK25M__CLK25M 0
#define CLK25M__AUX1 1
#define CLK25M__PWR_MCU_JTAG_TDO 2
#define CLK25M__PWR_GPIO_11 3
#define CLK25M__PWM_3 4
#define CLK25M__KEY_COL1 5
#define CLK25M__CAM_MCLK1 6
#define CLK25M__DBG_1 7
#define IIC2_SCL__IIC2_SCL 0
#define IIC2_SCL__PWM_14 1
#define IIC2_SCL__PWR_GPIO_12 3
#define IIC2_SCL__UART2_RX 4
#define IIC2_SCL__KEY_COL2 7
#define IIC2_SDA__IIC2_SDA 0
#define IIC2_SDA__PWM_15 1
#define IIC2_SDA__PWR_GPIO_13 3
#define IIC2_SDA__UART2_TX 4
#define IIC2_SDA__IIS1_MCLK 5
#define IIC2_SDA__IIS2_MCLK 6
#define IIC2_SDA__KEY_COL3 7
#define UART2_TX__UART2_TX 0
#define UART2_TX__PWM_11 1
#define UART2_TX__PWR_UART1_TX 2
#define UART2_TX__PWR_GPIO_14 3
#define UART2_TX__KEY_ROW3 4
#define UART2_TX__UART4_TX 5
#define UART2_TX__IIS2_BCLK 6
#define UART2_TX__WG2_D0 7
#define UART2_RTS__UART2_RTS 0
#define UART2_RTS__PWM_8 1
#define UART2_RTS__PWR_GPIO_15 3
#define UART2_RTS__KEY_ROW0 4
#define UART2_RTS__UART4_RTS 5
#define UART2_RTS__IIS2_DO 6
#define UART2_RTS__WG1_D0 7
#define UART2_RX__UART2_RX 0
#define UART2_RX__PWM_10 1
#define UART2_RX__PWR_UART1_RX 2
#define UART2_RX__PWR_GPIO_16 3
#define UART2_RX__KEY_COL3 4
#define UART2_RX__UART4_RX 5
#define UART2_RX__IIS2_DI 6
#define UART2_RX__WG2_D1 7
#define UART2_CTS__UART2_CTS 0
#define UART2_CTS__PWM_9 1
#define UART2_CTS__PWR_GPIO_17 3
#define UART2_CTS__KEY_ROW1 4
#define UART2_CTS__UART4_CTS 5
#define UART2_CTS__IIS2_LRCK 6
#define UART2_CTS__WG1_D1 7
#define SD1_D3__PWR_SD1_D3 0
#define SD1_D3__SPI2_CS_X 1
#define SD1_D3__IIC1_SCL 2
#define SD1_D3__PWR_GPIO_18 3
#define SD1_D3__CAM_MCLK0 4
#define SD1_D3__UART3_CTS 5
#define SD1_D3__PWR_SPINOR1_CS_X 6
#define SD1_D3__PWM_4 7
#define SD1_D2__PWR_SD1_D2 0
#define SD1_D2__IIC1_SCL 1
#define SD1_D2__UART2_TX 2
#define SD1_D2__PWR_GPIO_19 3
#define SD1_D2__CAM_MCLK0 4
#define SD1_D2__UART3_TX 5
#define SD1_D2__PWR_SPINOR1_HOLD_X 6
#define SD1_D2__PWM_5 7
#define SD1_D1__PWR_SD1_D1 0
#define SD1_D1__IIC1_SDA 1
#define SD1_D1__UART2_RX 2
#define SD1_D1__PWR_GPIO_20 3
#define SD1_D1__CAM_MCLK1 4
#define SD1_D1__UART3_RX 5
#define SD1_D1__PWR_SPINOR1_WP_X 6
#define SD1_D1__PWM_6 7
#define SD1_D0__PWR_SD1_D0 0
#define SD1_D0__SPI2_SDI 1
#define SD1_D0__IIC1_SDA 2
#define SD1_D0__PWR_GPIO_21 3
#define SD1_D0__CAM_MCLK1 4
#define SD1_D0__UART3_RTS 5
#define SD1_D0__PWR_SPINOR1_MISO 6
#define SD1_D0__PWM_7 7
#define SD1_CMD__PWR_SD1_CMD 0
#define SD1_CMD__SPI2_SDO 1
#define SD1_CMD__IIC3_SCL 2
#define SD1_CMD__PWR_GPIO_22 3
#define SD1_CMD__EPHY_LNK_LED 5
#define SD1_CMD__PWR_SPINOR1_MOSI 6
#define SD1_CMD__PWM_8 7
#define SD1_CLK__PWR_SD1_CLK 0
#define SD1_CLK__SPI2_SCK 1
#define SD1_CLK__IIC3_SDA 2
#define SD1_CLK__PWR_GPIO_23 3
#define SD1_CLK__EPHY_SPD_LED 5
#define SD1_CLK__PWR_SPINOR1_SCK 6
#define SD1_CLK__PWM_9 7
#define RSTN__RSTN 0
#define PWM0_BUCK__PWM_0 0
#define PWM0_BUCK__XGPIOB_0 3
#define ADC3__CAM_MCLK0 1
#define ADC3__IIC4_SCL 2
#define ADC3__XGPIOB_1 3
#define ADC3__PWM_12 4
#define ADC3__EPHY_LNK_LED 5
#define ADC3__WG2_D0 6
#define ADC3__UART3_TX 7
#define ADC2__CAM_MCLK1 1
#define ADC2__IIC4_SDA 2
#define ADC2__XGPIOB_2 3
#define ADC2__PWM_13 4
#define ADC2__EPHY_SPD_LED 5
#define ADC2__WG2_D1 6
#define ADC2__UART3_RX 7
#define ADC1__XGPIOB_3 3
#define ADC1__KEY_COL2 4
#define USB_ID__USB_ID 0
#define USB_ID__XGPIOB_4 3
#define USB_VBUS_EN__USB_VBUS_EN 0
#define USB_VBUS_EN__XGPIOB_5 3
#define PKG_TYPE0__PKG_TYPE0 0
#define USB_VBUS_DET__USB_VBUS_DET 0
#define USB_VBUS_DET__XGPIOB_6 3
#define USB_VBUS_DET__CAM_MCLK0 4
#define USB_VBUS_DET__CAM_MCLK1 5
#define PKG_TYPE1__PKG_TYPE1 0
#define PKG_TYPE2__PKG_TYPE2 0
#define SPI1_MISO__UART3_RTS 1
#define SPI1_MISO__IIC1_SDA 2
#define SPI1_MISO__XGPIOB_8 3
#define SPI1_MISO__PWM_9 4
#define SPI1_MISO__KEY_COL1 5
#define SPI1_MISO__SPI1_SDI 6
#define SPI1_MISO__DBG_14 7
#define SPI1_MOSI__UART3_RX 1
#define SPI1_MOSI__IIC1_SCL 2
#define SPI1_MOSI__XGPIOB_7 3
#define SPI1_MOSI__PWM_8 4
#define SPI1_MOSI__KEY_COL0 5
#define SPI1_MOSI__SPI1_SDO 6
#define SPI1_MOSI__DBG_13 7
#define SPI1_CS__UART3_CTS 1
#define SPI1_CS__CAM_MCLK0 2
#define SPI1_CS__XGPIOB_10 3
#define SPI1_CS__PWM_11 4
#define SPI1_CS__KEY_ROW3 5
#define SPI1_CS__SPI1_CS_X 6
#define SPI1_CS__DBG_16 7
#define SPI1_SCK__UART3_TX 1
#define SPI1_SCK__CAM_MCLK1 2
#define SPI1_SCK__XGPIOB_9 3
#define SPI1_SCK__PWM_10 4
#define SPI1_SCK__KEY_ROW2 5
#define SPI1_SCK__SPI1_SCK 6
#define SPI1_SCK__DBG_15 7
#define VIVO_D10__PWM_1 0
#define VIVO_D10__VI1_D_10 1
#define VIVO_D10__VO_D_23 2
#define VIVO_D10__XGPIOB_11 3
#define VIVO_D10__RMII0_IRQ 4
#define VIVO_D10__CAM_MCLK0 5
#define VIVO_D10__IIC1_SDA 6
#define VIVO_D10__UART2_TX 7
#define VIVO_D9__PWM_2 0
#define VIVO_D9__VI1_D_9 1
#define VIVO_D9__VO_D_22 2
#define VIVO_D9__XGPIOB_12 3
#define VIVO_D9__CAM_MCLK1 5
#define VIVO_D9__IIC1_SCL 6
#define VIVO_D9__UART2_RX 7
#define VIVO_D8__PWM_3 0
#define VIVO_D8__VI1_D_8 1
#define VIVO_D8__VO_D_21 2
#define VIVO_D8__XGPIOB_13 3
#define VIVO_D8__RMII0_MDIO 4
#define VIVO_D8__SPI3_SDO 5
#define VIVO_D8__IIC2_SCL 6
#define VIVO_D8__DBG_17 7
#define VIVO_D7__VI2_D_7 0
#define VIVO_D7__VI1_D_7 1
#define VIVO_D7__VO_D_20 2
#define VIVO_D7__XGPIOB_14 3
#define VIVO_D7__RMII0_RXD1 4
#define VIVO_D7__SPI3_SDI 5
#define VIVO_D7__IIC2_SDA 6
#define VIVO_D7__DBG_18 7
#define VIVO_D6__VI2_D_6 0
#define VIVO_D6__VI1_D_6 1
#define VIVO_D6__VO_D_19 2
#define VIVO_D6__XGPIOB_15 3
#define VIVO_D6__RMII0_REFCLKI 4
#define VIVO_D6__SPI3_SCK 5
#define VIVO_D6__UART2_TX 6
#define VIVO_D6__DBG_19 7
#define VIVO_D5__VI2_D_5 0
#define VIVO_D5__VI1_D_5 1
#define VIVO_D5__VO_D_18 2
#define VIVO_D5__XGPIOB_16 3
#define VIVO_D5__RMII0_RXD0 4
#define VIVO_D5__SPI3_CS_X 5
#define VIVO_D5__UART2_RX 6
#define VIVO_D5__DBG_20 7
#define VIVO_D4__VI2_D_4 0
#define VIVO_D4__VI1_D_4 1
#define VIVO_D4__VO_D_17 2
#define VIVO_D4__XGPIOB_17 3
#define VIVO_D4__RMII0_MDC 4
#define VIVO_D4__IIC1_SDA 5
#define VIVO_D4__UART2_CTS 6
#define VIVO_D4__DBG_21 7
#define VIVO_D3__VI2_D_3 0
#define VIVO_D3__VI1_D_3 1
#define VIVO_D3__VO_D_16 2
#define VIVO_D3__XGPIOB_18 3
#define VIVO_D3__RMII0_TXD0 4
#define VIVO_D3__IIC1_SCL 5
#define VIVO_D3__UART2_RTS 6
#define VIVO_D3__DBG_22 7
#define VIVO_D2__VI2_D_2 0
#define VIVO_D2__VI1_D_2 1
#define VIVO_D2__VO_D_15 2
#define VIVO_D2__XGPIOB_19 3
#define VIVO_D2__RMII0_TXD1 4
#define VIVO_D2__CAM_MCLK1 5
#define VIVO_D2__PWM_2 6
#define VIVO_D2__UART2_TX 7
#define VIVO_D1__VI2_D_1 0
#define VIVO_D1__VI1_D_1 1
#define VIVO_D1__VO_D_14 2
#define VIVO_D1__XGPIOB_20 3
#define VIVO_D1__RMII0_RXDV 4
#define VIVO_D1__IIC3_SDA 5
#define VIVO_D1__PWM_3 6
#define VIVO_D1__IIC4_SCL 7
#define VIVO_D0__VI2_D_0 0
#define VIVO_D0__VI1_D_0 1
#define VIVO_D0__VO_D_13 2
#define VIVO_D0__XGPIOB_21 3
#define VIVO_D0__RMII0_TXCLK 4
#define VIVO_D0__IIC3_SCL 5
#define VIVO_D0__WG1_D0 6
#define VIVO_D0__IIC4_SDA 7
#define VIVO_CLK__VI2_CLK 0
#define VIVO_CLK__VI1_CLK 1
#define VIVO_CLK__VO_CLK1 2
#define VIVO_CLK__XGPIOB_22 3
#define VIVO_CLK__RMII0_TXEN 4
#define VIVO_CLK__CAM_MCLK0 5
#define VIVO_CLK__WG1_D1 6
#define VIVO_CLK__UART2_RX 7
#define PAD_MIPIRX5N__VI1_D_11 1
#define PAD_MIPIRX5N__VO_D_12 2
#define PAD_MIPIRX5N__XGPIOC_0 3
#define PAD_MIPIRX5N__CAM_MCLK0 5
#define PAD_MIPIRX5N__WG0_D0 6
#define PAD_MIPIRX5N__DBG_0 7
#define PAD_MIPIRX5P__VI1_D_12 1
#define PAD_MIPIRX5P__VO_D_11 2
#define PAD_MIPIRX5P__XGPIOC_1 3
#define PAD_MIPIRX5P__IIS1_MCLK 4
#define PAD_MIPIRX5P__CAM_MCLK1 5
#define PAD_MIPIRX5P__WG0_D1 6
#define PAD_MIPIRX5P__DBG_1 7
#define PAD_MIPIRX4N__VI0_CLK 1
#define PAD_MIPIRX4N__VI1_D_13 2
#define PAD_MIPIRX4N__XGPIOC_2 3
#define PAD_MIPIRX4N__IIC1_SDA 4
#define PAD_MIPIRX4N__CAM_MCLK0 5
#define PAD_MIPIRX4N__KEY_ROW0 6
#define PAD_MIPIRX4N__MUX_SPI1_SCK 7
#define PAD_MIPIRX4P__VI0_D_0 1
#define PAD_MIPIRX4P__VI1_D_14 2
#define PAD_MIPIRX4P__XGPIOC_3 3
#define PAD_MIPIRX4P__IIC1_SCL 4
#define PAD_MIPIRX4P__CAM_MCLK1 5
#define PAD_MIPIRX4P__KEY_ROW1 6
#define PAD_MIPIRX4P__MUX_SPI1_CS 7
#define PAD_MIPIRX3N__VI0_D_1 1
#define PAD_MIPIRX3N__VI1_D_15 2
#define PAD_MIPIRX3N__XGPIOC_4 3
#define PAD_MIPIRX3N__CAM_MCLK0 4
#define PAD_MIPIRX3N__MUX_SPI1_MISO 7
#define PAD_MIPIRX3P__VI0_D_2 1
#define PAD_MIPIRX3P__VI1_D_16 2
#define PAD_MIPIRX3P__XGPIOC_5 3
#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7
#define PAD_MIPIRX2N__VI0_D_3 1
#define PAD_MIPIRX2N__VO_D_10 2
#define PAD_MIPIRX2N__XGPIOC_6 3
#define PAD_MIPIRX2N__VI1_D_17 4
#define PAD_MIPIRX2N__IIC4_SCL 5
#define PAD_MIPIRX2N__DBG_6 7
#define PAD_MIPIRX2P__VI0_D_4 1
#define PAD_MIPIRX2P__VO_D_9 2
#define PAD_MIPIRX2P__XGPIOC_7 3
#define PAD_MIPIRX2P__VI1_D_18 4
#define PAD_MIPIRX2P__IIC4_SDA 5
#define PAD_MIPIRX2P__DBG_7 7
#define PAD_MIPIRX1N__VI0_D_5 1
#define PAD_MIPIRX1N__VO_D_8 2
#define PAD_MIPIRX1N__XGPIOC_8 3
#define PAD_MIPIRX1N__KEY_ROW3 6
#define PAD_MIPIRX1N__DBG_8 7
#define PAD_MIPIRX1P__VI0_D_6 1
#define PAD_MIPIRX1P__VO_D_7 2
#define PAD_MIPIRX1P__XGPIOC_9 3
#define PAD_MIPIRX1P__IIC1_SDA 4
#define PAD_MIPIRX1P__KEY_ROW2 6
#define PAD_MIPIRX1P__DBG_9 7
#define PAD_MIPIRX0N__VI0_D_7 1
#define PAD_MIPIRX0N__VO_D_6 2
#define PAD_MIPIRX0N__XGPIOC_10 3
#define PAD_MIPIRX0N__IIC1_SCL 4
#define PAD_MIPIRX0N__CAM_MCLK1 5
#define PAD_MIPIRX0N__DBG_10 7
#define PAD_MIPIRX0P__VI0_D_8 1
#define PAD_MIPIRX0P__VO_D_5 2
#define PAD_MIPIRX0P__XGPIOC_11 3
#define PAD_MIPIRX0P__CAM_MCLK0 4
#define PAD_MIPIRX0P__DBG_11 7
#define PAD_MIPI_TXM4__VO_D_24 2
#define PAD_MIPI_TXM4__XGPIOC_18 3
#define PAD_MIPI_TXM4__CAM_MCLK1 4
#define PAD_MIPI_TXM4__PWM_12 5
#define PAD_MIPI_TXM4__IIC1_SDA 6
#define PAD_MIPI_TXM4__DBG_18 7
#define PAD_MIPI_TXP4__VO_D_25 2
#define PAD_MIPI_TXP4__XGPIOC_19 3
#define PAD_MIPI_TXP4__CAM_MCLK0 4
#define PAD_MIPI_TXP4__PWM_13 5
#define PAD_MIPI_TXP4__IIC1_SCL 6
#define PAD_MIPI_TXP4__DBG_19 7
#define PAD_MIPI_TXM3__VO_D_26 2
#define PAD_MIPI_TXM3__XGPIOC_20 3
#define PAD_MIPI_TXM3__IIC2_SDA 4
#define PAD_MIPI_TXM3__PWM_14 5
#define PAD_MIPI_TXM3__IIC1_SDA 6
#define PAD_MIPI_TXM3__DBG_20 7
#define PAD_MIPI_TXP3__VO_D_27 2
#define PAD_MIPI_TXP3__XGPIOC_21 3
#define PAD_MIPI_TXP3__IIC2_SCL 4
#define PAD_MIPI_TXP3__PWM_15 5
#define PAD_MIPI_TXP3__IIC1_SCL 6
#define PAD_MIPI_TXP3__DBG_21 7
#define PAD_MIPI_TXM2__VI0_D_13 1
#define PAD_MIPI_TXM2__VO_D_0 2
#define PAD_MIPI_TXM2__XGPIOC_16 3
#define PAD_MIPI_TXM2__IIC1_SDA 4
#define PAD_MIPI_TXM2__PWM_8 5
#define PAD_MIPI_TXM2__SPI0_SCK 6
#define PAD_MIPI_TXM2__DBG_16 7
#define PAD_MIPI_TXP2__VI0_D_14 1
#define PAD_MIPI_TXP2__VO_CLK0 2
#define PAD_MIPI_TXP2__XGPIOC_17 3
#define PAD_MIPI_TXP2__IIC1_SCL 4
#define PAD_MIPI_TXP2__PWM_9 5
#define PAD_MIPI_TXP2__SPI0_CS_X 6
#define PAD_MIPI_TXP2__DBG_17 7
#define PAD_MIPI_TXM1__VI0_D_11 1
#define PAD_MIPI_TXM1__VO_D_2 2
#define PAD_MIPI_TXM1__XGPIOC_14 3
#define PAD_MIPI_TXM1__IIC2_SDA 4
#define PAD_MIPI_TXM1__PWM_10 5
#define PAD_MIPI_TXM1__SPI0_SDO 6
#define PAD_MIPI_TXM1__DBG_14 7
#define PAD_MIPI_TXP1__VI0_D_12 1
#define PAD_MIPI_TXP1__VO_D_1 2
#define PAD_MIPI_TXP1__XGPIOC_15 3
#define PAD_MIPI_TXP1__IIC2_SCL 4
#define PAD_MIPI_TXP1__PWM_11 5
#define PAD_MIPI_TXP1__SPI0_SDI 6
#define PAD_MIPI_TXP1__DBG_15 7
#define PAD_MIPI_TXM0__VI0_D_9 1
#define PAD_MIPI_TXM0__VO_D_4 2
#define PAD_MIPI_TXM0__XGPIOC_12 3
#define PAD_MIPI_TXM0__CAM_MCLK1 4
#define PAD_MIPI_TXM0__PWM_14 5
#define PAD_MIPI_TXM0__DBG_12 7
#define PAD_MIPI_TXP0__VI0_D_10 1
#define PAD_MIPI_TXP0__VO_D_3 2
#define PAD_MIPI_TXP0__XGPIOC_13 3
#define PAD_MIPI_TXP0__CAM_MCLK0 4
#define PAD_MIPI_TXP0__PWM_15 5
#define PAD_MIPI_TXP0__DBG_13 7
#define PAD_AUD_AINL_MIC__XGPIOC_23 3
#define PAD_AUD_AINL_MIC__IIS1_BCLK 4
#define PAD_AUD_AINR_MIC__XGPIOC_22 3
#define PAD_AUD_AINR_MIC__IIS1_DO 4
#define PAD_AUD_AOUTL__XGPIOC_25 3
#define PAD_AUD_AOUTL__IIS1_LRCK 4
#define PAD_AUD_AOUTR__XGPIOC_24 3
#define PAD_AUD_AOUTR__IIS1_DI 4
#endif /* __CV1822_PINLIST_SWCONFIG_H__ */

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#ifndef __CV1822_REG_H
#define __CV1822_REG_H
#define TOP_BASE 0x03000000
#define PINMUX_BASE (TOP_BASE + 0x1000)
#define CLKGEN_BASE (TOP_BASE + 0x2000)
#define WATCHDOG_BASE (TOP_BASE + 0x00010000)
#define RTC_BASE 0x05026000
#define BM_IO_BUF_BASE 0x0C000000
#define BM_IO_BUF_SIZE 0x2000
/*
* RTC info registers
*/
#define RTC_INFO0 (RTC_BASE + 0x1C)
/*
* General purpose registers
*/
#define GP_REG0 (TOP_BASE + 0x80)
#define GP_REG1 (TOP_BASE + 0x84)
#define GP_REG2 (TOP_BASE + 0x88
#define GP_REG3 (TOP_BASE + 0x8C)
#define GP_REG4 (TOP_BASE + 0x90)
#define GP_REG5 (TOP_BASE + 0x94)
#define GP_REG6 (TOP_BASE + 0x98)
#define GP_REG7 (TOP_BASE + 0x9C)
#define GP_REG8 (TOP_BASE + 0xA0)
#define GP_REG9 (TOP_BASE + 0xA4)
#define GP_REG10 (TOP_BASE + 0xA8)
/*
* Pinmux definitions
*/
#define PINMUX_UART0 0
#define PINMUX_UART1 1
#define PINMUX_UART2 2
#define PINMUX_UART3 3
#define PINMUX_UART3_2 4
#define PINMUX_I2C0 5
#define PINMUX_I2C1 6
#define PINMUX_I2C2 7
#define PINMUX_I2C3 8
#define PINMUX_I2C4 9
#define PINMUX_I2C4_2 10
#define PINMUX_SPI0 11
#define PINMUX_SPI1 12
#define PINMUX_SPI2 13
#define PINMUX_SPI2_2 14
#define PINMUX_SPI3 15
#define PINMUX_SPI3_2 16
#define PINMUX_I2S0 17
#define PINMUX_I2S1 18
#define PINMUX_I2S2 19
#define PINMUX_I2S3 20
#define PINMUX_USBID 21
#define PINMUX_SDIO0 22
#define PINMUX_SDIO1 23
#define PINMUX_ND 24
#define PINMUX_EMMC 25
#define PINMUX_SPI_NOR 26
#define PINMUX_SPI_NAND 27
#define PINMUX_CAM0 28
#define PINMUX_CAM1 29
#define PINMUX_PCM0 30
#define PINMUX_PCM1 31
#define PINMUX_CSI0 32
#define PINMUX_CSI1 33
#define PINMUX_CSI2 34
#define PINMUX_DSI 35
#define PINMUX_VI0 36
#define PINMUX_VO 37
#define PINMUX_RMII1 38
#define PINMUX_EPHY_LED 39
#define PINMUX_I80 40
#define PINMUX_LVDS 41
#define REG_TOP_USB_ECO (TOP_BASE + 0xB4)
#define BIT_TOP_USB_ECO_RX_FLUSH 0x80
/* rst */
#define REG_TOP_SOFT_RST 0x3000
#define BIT_TOP_SOFT_RST_USB BIT(11)
#define BIT_TOP_SOFT_RST_SDIO BIT(14)
#define BIT_TOP_SOFT_RST_NAND BIT(12)
#define REG_TOP_USB_CTRSTS (TOP_BASE + 0x38)
#define REG_TOP_CONF_INFO (TOP_BASE + 0x4)
#define BIT_TOP_CONF_INFO_VBUS BIT(9)
#define REG_TOP_USB_PHY_CTRL (TOP_BASE + 0x48)
#define BIT_TOP_USB_PHY_CTRL_EXTVBUS BIT(0)
#define USB_PHY_ID_OVERRIDE_ENABLE BIT(6)
#define USB_PHY_ID_VALUE BIT(7)
#define REG_TOP_DDR_ADDR_MODE (TOP_BASE + 0x64)
/* irq */
#define IRQ_LEVEL 0
#define IRQ_EDGE 3
/* usb */
#define USB_BASE 0x04340000
/* ethernet phy */
#define ETH_PHY_BASE 0x03009000
#define ETH_PHY_INIT_MASK 0xFFFFFFF9
#define ETH_PHY_SHUTDOWN BIT(1)
#define ETH_PHY_POWERUP 0xFFFFFFFD
#define ETH_PHY_RESET 0xFFFFFFFB
#define ETH_PHY_RESET_N BIT(2)
#define ETH_PHY_LED_LOW_ACTIVE BIT(3)
/* watchdog */
#define DW_WDT_CR 0x00
#define DW_WDT_TORR 0x04
#define DW_WDT_CRR 0x0C
#define DW_WDT_CR_EN_OFFSET 0x00
#define DW_WDT_CR_RMOD_OFFSET 0x01
#define DW_WDT_CR_RMOD_VAL 0x00
#define DW_WDT_CRR_RESTART_VAL 0x76
/* SDIO Wifi */
#define WIFI_CHIP_EN_BGA BIT(18)
#define WIFI_CHIP_EN_QFN BIT(2)
/* RTC */
#define RTC_SYS_BASE 0x05000000
#define RTC_MACRO_BASE (RTC_SYS_BASE + 0x00026400)
#define RTC_MACRO_DA_SOC_READY 0x8C
#define RTC_MACRO_RO_T 0xA8
#define RTC_CORE_SRAM_BASE (RTC_SYS_BASE + 0x00026800)
#define RTC_CORE_SRAM_SIZE 0x0800 // 2KB
#define REG_RTC_CTRL_BASE (RTC_SYS_BASE + 0x00025000)
#define RTC_CTRL0_UNLOCKKEY 0x4
#define RTC_CTRL0 0x8
#define RTC_CTRL0_STATUS0 0xC
#define RTCSYS_RST_CTRL 0x18
#define REG_RTC_BASE (RTC_SYS_BASE + 0x00026000)
#define RTC_EN_PWR_WAKEUP 0xBC
#define RTC_EN_SHDN_REQ 0xC0
#define RTC_EN_PWR_CYC_REQ 0xC8
#define RTC_EN_WARM_RST_REQ 0xCC
#define RTC_EN_WDT_RST_REQ 0xE0
#define RTC_EN_SUSPEND_REQ 0xE4
#define RTC_PG_REG 0xF0
#define RTC_ST_ON_REASON 0xF8
#define REG_RTC_ST_ON_REASON (REG_RTC_BASE + RTC_ST_ON_REASON)
#define RTCSYS_F32KLESS_BASE (RTC_SYS_BASE + 0x0002A000)
#define RTC_INTERNAL_32K 0
#define RTC_EXTERNAL_32K 1
#define CONFIG_DW_WDT_BASE WATCHDOG_BASE
#define CONFIG_DW_WDT_CLOCK_KHZ 25000
#endif /* __CV1822_REG_H */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: cv1822_reg_fmux_gpio.h
* Description:
*/
#ifndef __CV1822_REG_FMUX_GPIO_H__
#define __CV1822_REG_FMUX_GPIO_H__
//GEN REG ADDR/OFFSET/MASK
#define fmux_gpio_REG_IOCTRL_CAM_MCLK0 0x0
#define fmux_gpio_REG_IOCTRL_CAM_PD0 0x4
#define fmux_gpio_REG_IOCTRL_CAM_RST0 0x8
#define fmux_gpio_REG_IOCTRL_CAM_MCLK1 0xc
#define fmux_gpio_REG_IOCTRL_CAM_PD1 0x10
#define fmux_gpio_REG_IOCTRL_IIC3_SCL 0x14
#define fmux_gpio_REG_IOCTRL_IIC3_SDA 0x18
#define fmux_gpio_REG_IOCTRL_SD0_CLK 0x1c
#define fmux_gpio_REG_IOCTRL_SD0_CMD 0x20
#define fmux_gpio_REG_IOCTRL_SD0_D0 0x24
#define fmux_gpio_REG_IOCTRL_SD0_D1 0x28
#define fmux_gpio_REG_IOCTRL_SD0_D2 0x2c
#define fmux_gpio_REG_IOCTRL_SD0_D3 0x30
#define fmux_gpio_REG_IOCTRL_SD0_CD 0x34
#define fmux_gpio_REG_IOCTRL_SD0_PWR_EN 0x38
#define fmux_gpio_REG_IOCTRL_SPK_EN 0x3c
#define fmux_gpio_REG_IOCTRL_UART0_TX 0x40
#define fmux_gpio_REG_IOCTRL_UART0_RX 0x44
#define fmux_gpio_REG_IOCTRL_EMMC_RSTN 0x48
#define fmux_gpio_REG_IOCTRL_EMMC_DAT2 0x4c
#define fmux_gpio_REG_IOCTRL_EMMC_CLK 0x50
#define fmux_gpio_REG_IOCTRL_EMMC_DAT0 0x54
#define fmux_gpio_REG_IOCTRL_EMMC_DAT3 0x58
#define fmux_gpio_REG_IOCTRL_EMMC_CMD 0x5c
#define fmux_gpio_REG_IOCTRL_EMMC_DAT1 0x60
#define fmux_gpio_REG_IOCTRL_JTAG_CPU_TMS 0x64
#define fmux_gpio_REG_IOCTRL_JTAG_CPU_TCK 0x68
#define fmux_gpio_REG_IOCTRL_JTAG_CPU_TRST 0x6c
#define fmux_gpio_REG_IOCTRL_IIC0_SCL 0x70
#define fmux_gpio_REG_IOCTRL_IIC0_SDA 0x74
#define fmux_gpio_REG_IOCTRL_AUX0 0x78
#define fmux_gpio_REG_IOCTRL_PWR_VBAT_DET 0x7c
#define fmux_gpio_REG_IOCTRL_PWR_RSTN 0x80
#define fmux_gpio_REG_IOCTRL_PWR_SEQ1 0x84
#define fmux_gpio_REG_IOCTRL_PWR_SEQ2 0x88
#define fmux_gpio_REG_IOCTRL_PWR_SEQ3 0x8c
#define fmux_gpio_REG_IOCTRL_PWR_WAKEUP0 0x90
#define fmux_gpio_REG_IOCTRL_PWR_WAKEUP1 0x94
#define fmux_gpio_REG_IOCTRL_PWR_BUTTON1 0x98
#define fmux_gpio_REG_IOCTRL_PWR_ON 0x9c
#define fmux_gpio_REG_IOCTRL_XTAL_XIN 0xa0
#define fmux_gpio_REG_IOCTRL_PWR_GPIO0 0xa4
#define fmux_gpio_REG_IOCTRL_PWR_GPIO1 0xa8
#define fmux_gpio_REG_IOCTRL_PWR_GPIO2 0xac
#define fmux_gpio_REG_IOCTRL_CLK32K 0xb0
#define fmux_gpio_REG_IOCTRL_CLK25M 0xb4
#define fmux_gpio_REG_IOCTRL_IIC2_SCL 0xb8
#define fmux_gpio_REG_IOCTRL_IIC2_SDA 0xbc
#define fmux_gpio_REG_IOCTRL_UART2_TX 0xc0
#define fmux_gpio_REG_IOCTRL_UART2_RTS 0xc4
#define fmux_gpio_REG_IOCTRL_UART2_RX 0xc8
#define fmux_gpio_REG_IOCTRL_UART2_CTS 0xcc
#define fmux_gpio_REG_IOCTRL_SD1_D3 0xd0
#define fmux_gpio_REG_IOCTRL_SD1_D2 0xd4
#define fmux_gpio_REG_IOCTRL_SD1_D1 0xd8
#define fmux_gpio_REG_IOCTRL_SD1_D0 0xdc
#define fmux_gpio_REG_IOCTRL_SD1_CMD 0xe0
#define fmux_gpio_REG_IOCTRL_SD1_CLK 0xe4
#define fmux_gpio_REG_IOCTRL_RSTN 0xe8
#define fmux_gpio_REG_IOCTRL_PWM0_BUCK 0xec
#define fmux_gpio_REG_IOCTRL_ADC3 0xf0
#define fmux_gpio_REG_IOCTRL_ADC2 0xf4
#define fmux_gpio_REG_IOCTRL_ADC1 0xf8
#define fmux_gpio_REG_IOCTRL_USB_ID 0xfc
#define fmux_gpio_REG_IOCTRL_USB_VBUS_EN 0x100
#define fmux_gpio_REG_IOCTRL_PKG_TYPE0 0x104
#define fmux_gpio_REG_IOCTRL_USB_VBUS_DET 0x108
#define fmux_gpio_REG_IOCTRL_PKG_TYPE1 0x10c
#define fmux_gpio_REG_IOCTRL_PKG_TYPE2 0x110
#define fmux_gpio_REG_IOCTRL_SPI1_MISO 0x114
#define fmux_gpio_REG_IOCTRL_SPI1_MOSI 0x118
#define fmux_gpio_REG_IOCTRL_SPI1_CS 0x11c
#define fmux_gpio_REG_IOCTRL_SPI1_SCK 0x120
#define fmux_gpio_REG_IOCTRL_VIVO_D10 0x124
#define fmux_gpio_REG_IOCTRL_VIVO_D9 0x128
#define fmux_gpio_REG_IOCTRL_VIVO_D8 0x12c
#define fmux_gpio_REG_IOCTRL_VIVO_D7 0x130
#define fmux_gpio_REG_IOCTRL_VIVO_D6 0x134
#define fmux_gpio_REG_IOCTRL_VIVO_D5 0x138
#define fmux_gpio_REG_IOCTRL_VIVO_D4 0x13c
#define fmux_gpio_REG_IOCTRL_VIVO_D3 0x140
#define fmux_gpio_REG_IOCTRL_VIVO_D2 0x144
#define fmux_gpio_REG_IOCTRL_VIVO_D1 0x148
#define fmux_gpio_REG_IOCTRL_VIVO_D0 0x14c
#define fmux_gpio_REG_IOCTRL_VIVO_CLK 0x150
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX5N 0x154
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX5P 0x158
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX4N 0x15c
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX4P 0x160
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX3N 0x164
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX3P 0x168
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX2N 0x16c
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX2P 0x170
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX1N 0x174
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX1P 0x178
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX0N 0x17c
#define fmux_gpio_REG_IOCTRL_PAD_MIPIRX0P 0x180
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXM4 0x184
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXP4 0x188
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXM3 0x18c
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXP3 0x190
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXM2 0x194
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXP2 0x198
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXM1 0x19c
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXP1 0x1a0
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXM0 0x1a4
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXP0 0x1a8
#define fmux_gpio_REG_IOCTRL_PAD_AUD_AINL_MIC 0x1ac
#define fmux_gpio_REG_IOCTRL_PAD_AUD_AINR_MIC 0x1b0
#define fmux_gpio_REG_IOCTRL_PAD_AUD_AOUTL 0x1b4
#define fmux_gpio_REG_IOCTRL_PAD_AUD_AOUTR 0x1b8
#define fmux_gpio_funcsel_CAM_MCLK0 0x0
#define fmux_gpio_funcsel_CAM_MCLK0_OFFSET 0
#define fmux_gpio_funcsel_CAM_MCLK0_MASK 0x7
#define fmux_gpio_funcsel_CAM_PD0 0x4
#define fmux_gpio_funcsel_CAM_PD0_OFFSET 0
#define fmux_gpio_funcsel_CAM_PD0_MASK 0x7
#define fmux_gpio_funcsel_CAM_RST0 0x8
#define fmux_gpio_funcsel_CAM_RST0_OFFSET 0
#define fmux_gpio_funcsel_CAM_RST0_MASK 0x7
#define fmux_gpio_funcsel_CAM_MCLK1 0xc
#define fmux_gpio_funcsel_CAM_MCLK1_OFFSET 0
#define fmux_gpio_funcsel_CAM_MCLK1_MASK 0x7
#define fmux_gpio_funcsel_CAM_PD1 0x10
#define fmux_gpio_funcsel_CAM_PD1_OFFSET 0
#define fmux_gpio_funcsel_CAM_PD1_MASK 0x7
#define fmux_gpio_funcsel_IIC3_SCL 0x14
#define fmux_gpio_funcsel_IIC3_SCL_OFFSET 0
#define fmux_gpio_funcsel_IIC3_SCL_MASK 0x7
#define fmux_gpio_funcsel_IIC3_SDA 0x18
#define fmux_gpio_funcsel_IIC3_SDA_OFFSET 0
#define fmux_gpio_funcsel_IIC3_SDA_MASK 0x7
#define fmux_gpio_funcsel_SD0_CLK 0x1c
#define fmux_gpio_funcsel_SD0_CLK_OFFSET 0
#define fmux_gpio_funcsel_SD0_CLK_MASK 0x7
#define fmux_gpio_funcsel_SD0_CMD 0x20
#define fmux_gpio_funcsel_SD0_CMD_OFFSET 0
#define fmux_gpio_funcsel_SD0_CMD_MASK 0x7
#define fmux_gpio_funcsel_SD0_D0 0x24
#define fmux_gpio_funcsel_SD0_D0_OFFSET 0
#define fmux_gpio_funcsel_SD0_D0_MASK 0x7
#define fmux_gpio_funcsel_SD0_D1 0x28
#define fmux_gpio_funcsel_SD0_D1_OFFSET 0
#define fmux_gpio_funcsel_SD0_D1_MASK 0x7
#define fmux_gpio_funcsel_SD0_D2 0x2c
#define fmux_gpio_funcsel_SD0_D2_OFFSET 0
#define fmux_gpio_funcsel_SD0_D2_MASK 0x7
#define fmux_gpio_funcsel_SD0_D3 0x30
#define fmux_gpio_funcsel_SD0_D3_OFFSET 0
#define fmux_gpio_funcsel_SD0_D3_MASK 0x7
#define fmux_gpio_funcsel_SD0_CD 0x34
#define fmux_gpio_funcsel_SD0_CD_OFFSET 0
#define fmux_gpio_funcsel_SD0_CD_MASK 0x7
#define fmux_gpio_funcsel_SD0_PWR_EN 0x38
#define fmux_gpio_funcsel_SD0_PWR_EN_OFFSET 0
#define fmux_gpio_funcsel_SD0_PWR_EN_MASK 0x7
#define fmux_gpio_funcsel_SPK_EN 0x3c
#define fmux_gpio_funcsel_SPK_EN_OFFSET 0
#define fmux_gpio_funcsel_SPK_EN_MASK 0x7
#define fmux_gpio_funcsel_UART0_TX 0x40
#define fmux_gpio_funcsel_UART0_TX_OFFSET 0
#define fmux_gpio_funcsel_UART0_TX_MASK 0x7
#define fmux_gpio_funcsel_UART0_RX 0x44
#define fmux_gpio_funcsel_UART0_RX_OFFSET 0
#define fmux_gpio_funcsel_UART0_RX_MASK 0x7
#define fmux_gpio_funcsel_EMMC_RSTN 0x48
#define fmux_gpio_funcsel_EMMC_RSTN_OFFSET 0
#define fmux_gpio_funcsel_EMMC_RSTN_MASK 0x7
#define fmux_gpio_funcsel_EMMC_DAT2 0x4c
#define fmux_gpio_funcsel_EMMC_DAT2_OFFSET 0
#define fmux_gpio_funcsel_EMMC_DAT2_MASK 0x7
#define fmux_gpio_funcsel_EMMC_CLK 0x50
#define fmux_gpio_funcsel_EMMC_CLK_OFFSET 0
#define fmux_gpio_funcsel_EMMC_CLK_MASK 0x7
#define fmux_gpio_funcsel_EMMC_DAT0 0x54
#define fmux_gpio_funcsel_EMMC_DAT0_OFFSET 0
#define fmux_gpio_funcsel_EMMC_DAT0_MASK 0x7
#define fmux_gpio_funcsel_EMMC_DAT3 0x58
#define fmux_gpio_funcsel_EMMC_DAT3_OFFSET 0
#define fmux_gpio_funcsel_EMMC_DAT3_MASK 0x7
#define fmux_gpio_funcsel_EMMC_CMD 0x5c
#define fmux_gpio_funcsel_EMMC_CMD_OFFSET 0
#define fmux_gpio_funcsel_EMMC_CMD_MASK 0x7
#define fmux_gpio_funcsel_EMMC_DAT1 0x60
#define fmux_gpio_funcsel_EMMC_DAT1_OFFSET 0
#define fmux_gpio_funcsel_EMMC_DAT1_MASK 0x7
#define fmux_gpio_funcsel_JTAG_CPU_TMS 0x64
#define fmux_gpio_funcsel_JTAG_CPU_TMS_OFFSET 0
#define fmux_gpio_funcsel_JTAG_CPU_TMS_MASK 0x7
#define fmux_gpio_funcsel_JTAG_CPU_TCK 0x68
#define fmux_gpio_funcsel_JTAG_CPU_TCK_OFFSET 0
#define fmux_gpio_funcsel_JTAG_CPU_TCK_MASK 0x7
#define fmux_gpio_funcsel_JTAG_CPU_TRST 0x6c
#define fmux_gpio_funcsel_JTAG_CPU_TRST_OFFSET 0
#define fmux_gpio_funcsel_JTAG_CPU_TRST_MASK 0x7
#define fmux_gpio_funcsel_IIC0_SCL 0x70
#define fmux_gpio_funcsel_IIC0_SCL_OFFSET 0
#define fmux_gpio_funcsel_IIC0_SCL_MASK 0x7
#define fmux_gpio_funcsel_IIC0_SDA 0x74
#define fmux_gpio_funcsel_IIC0_SDA_OFFSET 0
#define fmux_gpio_funcsel_IIC0_SDA_MASK 0x7
#define fmux_gpio_funcsel_AUX0 0x78
#define fmux_gpio_funcsel_AUX0_OFFSET 0
#define fmux_gpio_funcsel_AUX0_MASK 0x7
#define fmux_gpio_funcsel_PWR_VBAT_DET 0x7c
#define fmux_gpio_funcsel_PWR_VBAT_DET_OFFSET 0
#define fmux_gpio_funcsel_PWR_VBAT_DET_MASK 0x7
#define fmux_gpio_funcsel_PWR_RSTN 0x80
#define fmux_gpio_funcsel_PWR_RSTN_OFFSET 0
#define fmux_gpio_funcsel_PWR_RSTN_MASK 0x7
#define fmux_gpio_funcsel_PWR_SEQ1 0x84
#define fmux_gpio_funcsel_PWR_SEQ1_OFFSET 0
#define fmux_gpio_funcsel_PWR_SEQ1_MASK 0x7
#define fmux_gpio_funcsel_PWR_SEQ2 0x88
#define fmux_gpio_funcsel_PWR_SEQ2_OFFSET 0
#define fmux_gpio_funcsel_PWR_SEQ2_MASK 0x7
#define fmux_gpio_funcsel_PWR_SEQ3 0x8c
#define fmux_gpio_funcsel_PWR_SEQ3_OFFSET 0
#define fmux_gpio_funcsel_PWR_SEQ3_MASK 0x7
#define fmux_gpio_funcsel_PWR_WAKEUP0 0x90
#define fmux_gpio_funcsel_PWR_WAKEUP0_OFFSET 0
#define fmux_gpio_funcsel_PWR_WAKEUP0_MASK 0x7
#define fmux_gpio_funcsel_PWR_WAKEUP1 0x94
#define fmux_gpio_funcsel_PWR_WAKEUP1_OFFSET 0
#define fmux_gpio_funcsel_PWR_WAKEUP1_MASK 0x7
#define fmux_gpio_funcsel_PWR_BUTTON1 0x98
#define fmux_gpio_funcsel_PWR_BUTTON1_OFFSET 0
#define fmux_gpio_funcsel_PWR_BUTTON1_MASK 0x7
#define fmux_gpio_funcsel_PWR_ON 0x9c
#define fmux_gpio_funcsel_PWR_ON_OFFSET 0
#define fmux_gpio_funcsel_PWR_ON_MASK 0x7
#define fmux_gpio_funcsel_XTAL_XIN 0xa0
#define fmux_gpio_funcsel_XTAL_XIN_OFFSET 0
#define fmux_gpio_funcsel_XTAL_XIN_MASK 0x7
#define fmux_gpio_funcsel_PWR_GPIO0 0xa4
#define fmux_gpio_funcsel_PWR_GPIO0_OFFSET 0
#define fmux_gpio_funcsel_PWR_GPIO0_MASK 0x7
#define fmux_gpio_funcsel_PWR_GPIO1 0xa8
#define fmux_gpio_funcsel_PWR_GPIO1_OFFSET 0
#define fmux_gpio_funcsel_PWR_GPIO1_MASK 0x7
#define fmux_gpio_funcsel_PWR_GPIO2 0xac
#define fmux_gpio_funcsel_PWR_GPIO2_OFFSET 0
#define fmux_gpio_funcsel_PWR_GPIO2_MASK 0x7
#define fmux_gpio_funcsel_CLK32K 0xb0
#define fmux_gpio_funcsel_CLK32K_OFFSET 0
#define fmux_gpio_funcsel_CLK32K_MASK 0x7
#define fmux_gpio_funcsel_CLK25M 0xb4
#define fmux_gpio_funcsel_CLK25M_OFFSET 0
#define fmux_gpio_funcsel_CLK25M_MASK 0x7
#define fmux_gpio_funcsel_IIC2_SCL 0xb8
#define fmux_gpio_funcsel_IIC2_SCL_OFFSET 0
#define fmux_gpio_funcsel_IIC2_SCL_MASK 0x7
#define fmux_gpio_funcsel_IIC2_SDA 0xbc
#define fmux_gpio_funcsel_IIC2_SDA_OFFSET 0
#define fmux_gpio_funcsel_IIC2_SDA_MASK 0x7
#define fmux_gpio_funcsel_UART2_TX 0xc0
#define fmux_gpio_funcsel_UART2_TX_OFFSET 0
#define fmux_gpio_funcsel_UART2_TX_MASK 0x7
#define fmux_gpio_funcsel_UART2_RTS 0xc4
#define fmux_gpio_funcsel_UART2_RTS_OFFSET 0
#define fmux_gpio_funcsel_UART2_RTS_MASK 0x7
#define fmux_gpio_funcsel_UART2_RX 0xc8
#define fmux_gpio_funcsel_UART2_RX_OFFSET 0
#define fmux_gpio_funcsel_UART2_RX_MASK 0x7
#define fmux_gpio_funcsel_UART2_CTS 0xcc
#define fmux_gpio_funcsel_UART2_CTS_OFFSET 0
#define fmux_gpio_funcsel_UART2_CTS_MASK 0x7
#define fmux_gpio_funcsel_SD1_D3 0xd0
#define fmux_gpio_funcsel_SD1_D3_OFFSET 0
#define fmux_gpio_funcsel_SD1_D3_MASK 0x7
#define fmux_gpio_funcsel_SD1_D2 0xd4
#define fmux_gpio_funcsel_SD1_D2_OFFSET 0
#define fmux_gpio_funcsel_SD1_D2_MASK 0x7
#define fmux_gpio_funcsel_SD1_D1 0xd8
#define fmux_gpio_funcsel_SD1_D1_OFFSET 0
#define fmux_gpio_funcsel_SD1_D1_MASK 0x7
#define fmux_gpio_funcsel_SD1_D0 0xdc
#define fmux_gpio_funcsel_SD1_D0_OFFSET 0
#define fmux_gpio_funcsel_SD1_D0_MASK 0x7
#define fmux_gpio_funcsel_SD1_CMD 0xe0
#define fmux_gpio_funcsel_SD1_CMD_OFFSET 0
#define fmux_gpio_funcsel_SD1_CMD_MASK 0x7
#define fmux_gpio_funcsel_SD1_CLK 0xe4
#define fmux_gpio_funcsel_SD1_CLK_OFFSET 0
#define fmux_gpio_funcsel_SD1_CLK_MASK 0x7
#define fmux_gpio_funcsel_RSTN 0xe8
#define fmux_gpio_funcsel_RSTN_OFFSET 0
#define fmux_gpio_funcsel_RSTN_MASK 0x7
#define fmux_gpio_funcsel_PWM0_BUCK 0xec
#define fmux_gpio_funcsel_PWM0_BUCK_OFFSET 0
#define fmux_gpio_funcsel_PWM0_BUCK_MASK 0x7
#define fmux_gpio_funcsel_ADC3 0xf0
#define fmux_gpio_funcsel_ADC3_OFFSET 0
#define fmux_gpio_funcsel_ADC3_MASK 0x7
#define fmux_gpio_funcsel_ADC2 0xf4
#define fmux_gpio_funcsel_ADC2_OFFSET 0
#define fmux_gpio_funcsel_ADC2_MASK 0x7
#define fmux_gpio_funcsel_ADC1 0xf8
#define fmux_gpio_funcsel_ADC1_OFFSET 0
#define fmux_gpio_funcsel_ADC1_MASK 0x7
#define fmux_gpio_funcsel_USB_ID 0xfc
#define fmux_gpio_funcsel_USB_ID_OFFSET 0
#define fmux_gpio_funcsel_USB_ID_MASK 0x7
#define fmux_gpio_funcsel_USB_VBUS_EN 0x100
#define fmux_gpio_funcsel_USB_VBUS_EN_OFFSET 0
#define fmux_gpio_funcsel_USB_VBUS_EN_MASK 0x7
#define fmux_gpio_funcsel_PKG_TYPE0 0x104
#define fmux_gpio_funcsel_PKG_TYPE0_OFFSET 0
#define fmux_gpio_funcsel_PKG_TYPE0_MASK 0x7
#define fmux_gpio_funcsel_USB_VBUS_DET 0x108
#define fmux_gpio_funcsel_USB_VBUS_DET_OFFSET 0
#define fmux_gpio_funcsel_USB_VBUS_DET_MASK 0x7
#define fmux_gpio_funcsel_PKG_TYPE1 0x10c
#define fmux_gpio_funcsel_PKG_TYPE1_OFFSET 0
#define fmux_gpio_funcsel_PKG_TYPE1_MASK 0x7
#define fmux_gpio_funcsel_PKG_TYPE2 0x110
#define fmux_gpio_funcsel_PKG_TYPE2_OFFSET 0
#define fmux_gpio_funcsel_PKG_TYPE2_MASK 0x7
#define fmux_gpio_funcsel_SPI1_MISO 0x114
#define fmux_gpio_funcsel_SPI1_MISO_OFFSET 0
#define fmux_gpio_funcsel_SPI1_MISO_MASK 0x7
#define fmux_gpio_funcsel_SPI1_MOSI 0x118
#define fmux_gpio_funcsel_SPI1_MOSI_OFFSET 0
#define fmux_gpio_funcsel_SPI1_MOSI_MASK 0x7
#define fmux_gpio_funcsel_SPI1_CS 0x11c
#define fmux_gpio_funcsel_SPI1_CS_OFFSET 0
#define fmux_gpio_funcsel_SPI1_CS_MASK 0x7
#define fmux_gpio_funcsel_SPI1_SCK 0x120
#define fmux_gpio_funcsel_SPI1_SCK_OFFSET 0
#define fmux_gpio_funcsel_SPI1_SCK_MASK 0x7
#define fmux_gpio_funcsel_VIVO_D10 0x124
#define fmux_gpio_funcsel_VIVO_D10_OFFSET 0
#define fmux_gpio_funcsel_VIVO_D10_MASK 0x7
#define fmux_gpio_funcsel_VIVO_D9 0x128
#define fmux_gpio_funcsel_VIVO_D9_OFFSET 0
#define fmux_gpio_funcsel_VIVO_D9_MASK 0x7
#define fmux_gpio_funcsel_VIVO_D8 0x12c
#define fmux_gpio_funcsel_VIVO_D8_OFFSET 0
#define fmux_gpio_funcsel_VIVO_D8_MASK 0x7
#define fmux_gpio_funcsel_VIVO_D7 0x130
#define fmux_gpio_funcsel_VIVO_D7_OFFSET 0
#define fmux_gpio_funcsel_VIVO_D7_MASK 0x7
#define fmux_gpio_funcsel_VIVO_D6 0x134
#define fmux_gpio_funcsel_VIVO_D6_OFFSET 0
#define fmux_gpio_funcsel_VIVO_D6_MASK 0x7
#define fmux_gpio_funcsel_VIVO_D5 0x138
#define fmux_gpio_funcsel_VIVO_D5_OFFSET 0
#define fmux_gpio_funcsel_VIVO_D5_MASK 0x7
#define fmux_gpio_funcsel_VIVO_D4 0x13c
#define fmux_gpio_funcsel_VIVO_D4_OFFSET 0
#define fmux_gpio_funcsel_VIVO_D4_MASK 0x7
#define fmux_gpio_funcsel_VIVO_D3 0x140
#define fmux_gpio_funcsel_VIVO_D3_OFFSET 0
#define fmux_gpio_funcsel_VIVO_D3_MASK 0x7
#define fmux_gpio_funcsel_VIVO_D2 0x144
#define fmux_gpio_funcsel_VIVO_D2_OFFSET 0
#define fmux_gpio_funcsel_VIVO_D2_MASK 0x7
#define fmux_gpio_funcsel_VIVO_D1 0x148
#define fmux_gpio_funcsel_VIVO_D1_OFFSET 0
#define fmux_gpio_funcsel_VIVO_D1_MASK 0x7
#define fmux_gpio_funcsel_VIVO_D0 0x14c
#define fmux_gpio_funcsel_VIVO_D0_OFFSET 0
#define fmux_gpio_funcsel_VIVO_D0_MASK 0x7
#define fmux_gpio_funcsel_VIVO_CLK 0x150
#define fmux_gpio_funcsel_VIVO_CLK_OFFSET 0
#define fmux_gpio_funcsel_VIVO_CLK_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX5N 0x154
#define fmux_gpio_funcsel_PAD_MIPIRX5N_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX5N_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX5P 0x158
#define fmux_gpio_funcsel_PAD_MIPIRX5P_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX5P_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX4N 0x15c
#define fmux_gpio_funcsel_PAD_MIPIRX4N_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX4N_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX4P 0x160
#define fmux_gpio_funcsel_PAD_MIPIRX4P_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX4P_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX3N 0x164
#define fmux_gpio_funcsel_PAD_MIPIRX3N_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX3N_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX3P 0x168
#define fmux_gpio_funcsel_PAD_MIPIRX3P_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX3P_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX2N 0x16c
#define fmux_gpio_funcsel_PAD_MIPIRX2N_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX2N_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX2P 0x170
#define fmux_gpio_funcsel_PAD_MIPIRX2P_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX2P_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX1N 0x174
#define fmux_gpio_funcsel_PAD_MIPIRX1N_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX1N_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX1P 0x178
#define fmux_gpio_funcsel_PAD_MIPIRX1P_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX1P_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX0N 0x17c
#define fmux_gpio_funcsel_PAD_MIPIRX0N_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX0N_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPIRX0P 0x180
#define fmux_gpio_funcsel_PAD_MIPIRX0P_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPIRX0P_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXM4 0x184
#define fmux_gpio_funcsel_PAD_MIPI_TXM4_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXM4_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXP4 0x188
#define fmux_gpio_funcsel_PAD_MIPI_TXP4_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXP4_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXM3 0x18c
#define fmux_gpio_funcsel_PAD_MIPI_TXM3_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXM3_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXP3 0x190
#define fmux_gpio_funcsel_PAD_MIPI_TXP3_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXP3_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXM2 0x194
#define fmux_gpio_funcsel_PAD_MIPI_TXM2_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXM2_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXP2 0x198
#define fmux_gpio_funcsel_PAD_MIPI_TXP2_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXP2_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXM1 0x19c
#define fmux_gpio_funcsel_PAD_MIPI_TXM1_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXM1_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXP1 0x1a0
#define fmux_gpio_funcsel_PAD_MIPI_TXP1_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXP1_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXM0 0x1a4
#define fmux_gpio_funcsel_PAD_MIPI_TXM0_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXM0_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXP0 0x1a8
#define fmux_gpio_funcsel_PAD_MIPI_TXP0_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXP0_MASK 0x7
#define fmux_gpio_funcsel_PAD_AUD_AINL_MIC 0x1ac
#define fmux_gpio_funcsel_PAD_AUD_AINL_MIC_OFFSET 0
#define fmux_gpio_funcsel_PAD_AUD_AINL_MIC_MASK 0x7
#define fmux_gpio_funcsel_PAD_AUD_AINR_MIC 0x1b0
#define fmux_gpio_funcsel_PAD_AUD_AINR_MIC_OFFSET 0
#define fmux_gpio_funcsel_PAD_AUD_AINR_MIC_MASK 0x7
#define fmux_gpio_funcsel_PAD_AUD_AOUTL 0x1b4
#define fmux_gpio_funcsel_PAD_AUD_AOUTL_OFFSET 0
#define fmux_gpio_funcsel_PAD_AUD_AOUTL_MASK 0x7
#define fmux_gpio_funcsel_PAD_AUD_AOUTR 0x1b8
#define fmux_gpio_funcsel_PAD_AUD_AOUTR_OFFSET 0
#define fmux_gpio_funcsel_PAD_AUD_AOUTR_MASK 0x7
#endif /* __CV1822_REG_FMUX_GPIO_H__ */

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#ifndef _SDHCI_REG_H
#define _SDHCI_REG_H
#include "cv1822_reg.h"
#define REG_TOP_SD_PWRSW_CTRL (0x1F4)
#define REG_SDIO0_PAD_MASK (0xFFFFFFF3)
#define REG_SDIO0_PAD_SHIFT (2)
#define REG_SDIO0_PAD_CLR_MASK (0xC)
#define REG_SDIO0_CD_PAD_REG (PINMUX_BASE + 0x900)
#define REG_SDIO0_CD_PAD_VALUE (1)
#define REG_SDIO0_CD_PAD_RESET (1)
#define REG_SDIO0_PWR_EN_PAD_REG (PINMUX_BASE + 0x904)
#define REG_SDIO0_PWR_EN_PAD_VALUE (2)
#define REG_SDIO0_PWR_EN_PAD_RESET (2)
#define REG_SDIO0_CLK_PAD_REG (PINMUX_BASE + 0xA00)
#define REG_SDIO0_CLK_PAD_VALUE (2)
#define REG_SDIO0_CLK_PAD_RESET (2)
#define REG_SDIO0_CMD_PAD_REG (PINMUX_BASE + 0xA04)
#define REG_SDIO0_CMD_PAD_VALUE (1)
#define REG_SDIO0_CMD_PAD_RESET (2)
#define REG_SDIO0_DAT0_PAD_REG (PINMUX_BASE + 0xA08)
#define REG_SDIO0_DAT0_PAD_VALUE (1)
#define REG_SDIO0_DAT0_PAD_RESET (2)
#define REG_SDIO0_DAT1_PAD_REG (PINMUX_BASE + 0xA0C)
#define REG_SDIO0_DAT1_PAD_VALUE (1)
#define REG_SDIO0_DAT1_PAD_RESET (2)
#define REG_SDIO0_DAT2_PAD_REG (PINMUX_BASE + 0xA10)
#define REG_SDIO0_DAT2_PAD_VALUE (1)
#define REG_SDIO0_DAT2_PAD_RESET (2)
#define REG_SDIO0_DAT3_PAD_REG (PINMUX_BASE + 0xA14)
#define REG_SDIO0_DAT3_PAD_VALUE (1)
#define REG_SDIO0_DAT3_PAD_RESET (2)
#define PAD_SDIO0_CD_REG (PINMUX_BASE + 0x34)
#define PAD_SDIO0_PWR_EN_REG (PINMUX_BASE + 0x38)
#define PAD_SDIO0_CLK_REG (PINMUX_BASE + 0x1C)
#define PAD_SDIO0_CMD_REG (PINMUX_BASE + 0x20)
#define PAD_SDIO0_D0_REG (PINMUX_BASE + 0x24)
#define PAD_SDIO0_D1_REG (PINMUX_BASE + 0x28)
#define PAD_SDIO0_D2_REG (PINMUX_BASE + 0x2C)
#define PAD_SDIO0_D3_REG (PINMUX_BASE + 0x30)
#define REG_SDIO1_PAD_MASK (0xFFFFFFF3)
#define REG_SDIO1_PAD_SHIFT (2)
#define SDIO1_PAD_BASE 0x05027000
#define REG_SDIO1_PAD_CLR_MASK (0xC)
#define REG_SDIO1_CLK_PAD_REG (SDIO1_PAD_BASE + 0x06C)
#define REG_SDIO1_CLK_PAD_VALUE (2)
#define REG_SDIO1_CMD_PAD_REG (SDIO1_PAD_BASE + 0x068)
#define REG_SDIO1_CMD_PAD_VALUE (1)
#define REG_SDIO1_DAT0_PAD_REG (SDIO1_PAD_BASE + 0x064)
#define REG_SDIO1_DAT0_PAD_VALUE (1)
#define REG_SDIO1_DAT2_PAD_REG (SDIO1_PAD_BASE + 0x05C)
#define REG_SDIO1_DAT2_PAD_VALUE (1)
#define REG_SDIO1_DAT1_PAD_REG (SDIO1_PAD_BASE + 0x060)
#define REG_SDIO1_DAT1_PAD_VALUE (1)
#define REG_SDIO1_DAT3_PAD_REG (SDIO1_PAD_BASE + 0x058)
#define REG_SDIO1_DAT3_PAD_VALUE (1)
#define REG_EMMC_PAD_CLR_MASK (0xC)
#define REG_EMMC_PAD_SHIFT (2)
#define REG_EMMC_RSTN_PAD_REG (PINMUX_BASE + 0x914)
#define REG_EMMC_RSTN_PAD_VALUE (1)
#define REG_EMMC_CLK_PAD_REG (PINMUX_BASE + 0x91c)
#define REG_EMMC_CLK_PAD_VALUE (2)
#define REG_EMMC_CMD_PAD_REG (PINMUX_BASE + 0x928)
#define REG_EMMC_CMD_PAD_VALUE (1)
#define REG_EMMC_DAT0_PAD_REG (PINMUX_BASE + 0x920)
#define REG_EMMC_DAT0_PAD_VALUE (1)
#define REG_EMMC_DAT1_PAD_REG (PINMUX_BASE + 0x92C)
#define REG_EMMC_DAT1_PAD_VALUE (1)
#define REG_EMMC_DAT2_PAD_REG (PINMUX_BASE + 0x918)
#define REG_EMMC_DAT2_PAD_VALUE (1)
#define REG_EMMC_DAT3_PAD_REG (PINMUX_BASE + 0x924)
#define REG_EMMC_DAT3_PAD_VALUE (1)
#define CVI_SDHCI_VENDOR_OFFSET 0x200
#define CVI_SDHCI_PHY_TX_RX_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_PHY_DS_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x44)
#define CVI_SDHCI_PHY_DLY_STS (CVI_SDHCI_VENDOR_OFFSET + 0x48)
#define CVI_SDHCI_PHY_CONFIG (CVI_SDHCI_VENDOR_OFFSET + 0x4C)
#define CVI_SDHCI_BIT_CLK_FREE_EN 2
#define CVI_SDHCI_CLK_FREE_EN_VALUE 0
#define CVI_SDHCI_CLK_FREE_EN_MASK 0xFFFFFFFB
#define CVI_SDHCI_VENDOR_MSHC_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x0)
#define CVI_SDHCI_PHY_RX_DLY_SHIFT 16
// Bit 16~22
#define CVI_SDHCI_PHY_RX_DLY_MASK 0x7F0000
#define CVI_SDHCI_PHY_TX_RX_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_PHY_RX_SRC_BIT_1 24
#define CVI_SDHCI_PHY_RX_SRC_BIT_2 25
#define SDHCI_PHY_CONFIG \
(CVI_SDHCI_VENDOR_OFFSET + \
0x4C) // P_VERDOR_SPECIFIC_AREA + 0x4c0x24c( PHY_TX_BPS )
#define REG_TX_BPS_SEL_MASK 0xFFFFFFFE
#define REG_TX_BPS_SEL_CLR_MASK (0x1) // 0x24c PHY_TX_BPS
#define REG_TX_BPS_SEL_SHIFT (0) // 0x24c PHY_TX_BPS
#define REG_TX_BPS_SEL_BYPASS (1) // 0x24c PHY_TX_BPS inv
#define MMC_MAX_CLOCK (375000000)
#define MMC_MAX_CLOCK_DIV_VALUE (0x40009)
#define CLOCK_BYPASS_SELECT_REGISTER (0x3002030)
#define MAX_TUNING_CMD_RETRY_COUNT 50
#define TUNE_MAX_PHCODE 128
#define TAP_WINDOW_THLD 20
#endif

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u-boot-2021.10/board/cvitek/cv1835/Kconfig Normal file
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if TARGET_CVITEK_CV1835
choice
prompt "Cvitek CV1835 verification platform type select"
config TARGET_CVITEK_CV1835_ASIC
bool "ASIC"
help
This enables support for Cvitek's CV1835 SoC on ASIC platform.
If unsure, say N.
config TARGET_CVITEK_CV1835_PALLADIUM
bool "Palladium"
help
This enables support for Cvitek's CV1835 SoC on PALLADIUM platform.
If unsure, say N.
config TARGET_CVITEK_CV1835_FPGA
bool "FPGA"
help
This enables support for Cvitek's CV1835 SoC on FPGA platform.
If unsure, say N.
endchoice
config SYS_BOARD
default "cv1835"
config SYS_VENDOR
default "cvitek"
config SYS_CONFIG_NAME
default "cv1835-asic" if TARGET_CVITEK_CV1835_ASIC
default "cv1835-palladium" if TARGET_CVITEK_CV1835_PALLADIUM
default "cv1835-fpga" if TARGET_CVITEK_CV1835_FPGA
config SYS_BOOTMAPSZ
hex "Maximum size of memory mapped"
default "0x10000000"
endif

4
u-boot-2021.10/board/cvitek/cv1835/MAINTAINERS Normal file
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CV1835 BOARD
M: Myles Tsai <myles.tsai@wisecore.com.tw>
S: Maintained
F: board/armltd/vexpress64/

2
u-boot-2021.10/board/cvitek/cv1835/Makefile Normal file
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obj-y := board.o

492
u-boot-2021.10/board/cvitek/cv1835/board.c Normal file
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/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
* Sharma Bhupesh <bhupesh.sharma@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <dm/platform_data/serial_pl01x.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-armv8/mmio.h>
#include "cv1835_reg.h"
#include "cv1835_reg_fmux_gpio.h"
#include "cv1835_pinlist_swconfig.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_PL011_SERIAL
static const struct pl01x_serial_platdata serial_platdata = {
.base = V2M_UART0,
.type = TYPE_PL011,
.clock = CONFIG_PL011_CLOCK,
};
U_BOOT_DEVICE(vexpress_serials) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
};
#endif
static struct mm_region vexpress64_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = PHYS_SDRAM_1,
.phys = PHYS_SDRAM_1,
.size = PHYS_SDRAM_1_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
#ifdef BM_UPDATE_FW_START_ADDR
}, {
.virt = BM_UPDATE_FW_START_ADDR,
.phys = BM_UPDATE_FW_START_ADDR,
/*
* this area is for bmtest under uboot. -- added by Xun Li
* [0x110000000, 0x190000000] size = 2G
*/
.size = BM_UPDATE_FW_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
#else
}, {
/*
* be aware we'll need 256MB more other than PHYS_SDRAM_1_SIZE for the fake flash area
* of itb file during ram boot, and MMC's DMA buffer (BM_UPDATE_ALIGNED_BUFFER).
* so either cover it here or in video's region.
* also be carefull with BM_SPIF_BUFFER_ADDR and BM_UPDATE_FW_START_ADDR...
*/
.virt = PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE,
.phys = PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE,
.size = 0x10000000,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
#endif
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = vexpress64_mem_map;
static void pinmux_config(int io_type)
{
switch (io_type) {
case PINMUX_UART0:
PINMUX_CONFIG(UART0_RX, UART0_RX);
PINMUX_CONFIG(UART0_TX, UART0_TX);
break;
case PINMUX_UART1:
PINMUX_CONFIG(UART1_RX, UART1_RX);
PINMUX_CONFIG(UART1_TX, UART1_TX);
break;
case PINMUX_UART2:
PINMUX_CONFIG(UART2_RX, UART2_RX);
PINMUX_CONFIG(UART2_TX, UART2_TX);
break;
case PINMUX_UART3:
PINMUX_CONFIG(PWM2, UART3_RX);
PINMUX_CONFIG(PWM3, UART3_TX);
break;
case PINMUX_I2C0:
PINMUX_CONFIG(IIC0_SCL, IIC0_SCL);
PINMUX_CONFIG(IIC0_SDA, IIC0_SDA);
break;
case PINMUX_I2C1:
PINMUX_CONFIG(IIC1_SCL, IIC1_SCL);
PINMUX_CONFIG(IIC1_SDA, IIC1_SDA);
break;
case PINMUX_I2C2:
PINMUX_CONFIG(IIC2_SCL, IIC2_SCL);
PINMUX_CONFIG(IIC2_SDA, IIC2_SDA);
break;
case PINMUX_I2C3:
PINMUX_CONFIG(IIC3_SCL, IIC3_SCL);
PINMUX_CONFIG(IIC3_SDA, IIC3_SDA);
break;
case PINMUX_SPI0:
PINMUX_CONFIG(SPI0_SCK, SPI0_SCK);
PINMUX_CONFIG(SPI0_CS_X, SPI0_CS_X);
PINMUX_CONFIG(SPI0_SDI, SPI0_SDI);
PINMUX_CONFIG(SPI0_SDO, SPI0_SDO);
break;
case PINMUX_SPI1:
PINMUX_CONFIG(XGPIO_A_25, SPI1_SCK);
PINMUX_CONFIG(XGPIO_A_29, SPI1_CS_X);
PINMUX_CONFIG(XGPIO_A_23, SPI1_SDI);
PINMUX_CONFIG(XGPIO_A_24, SPI1_SDO);
break;
case PINMUX_SPI2:
PINMUX_CONFIG(IIC3_SCL, SPI2_SCK);
PINMUX_CONFIG(IIC3_SDA, SPI2_CS_X);
PINMUX_CONFIG(IIC0_SCL, SPI2_SDI);
PINMUX_CONFIG(IIC0_SDA, SPI2_SDO);
break;
case PINMUX_SPI3:
printf("fix me: PINMUX_SPI3\n");
break;
case PINMUX_I2S1:
PINMUX_CONFIG(UART1_RTS, IIS1_DI);
PINMUX_CONFIG(UART2_RTS, IIS1_MCLK);
PINMUX_CONFIG(UART1_CTS, IIS1_DO);
PINMUX_CONFIG(UART1_TX, IIS1_BCLK);
PINMUX_CONFIG(UART1_RX, IIS1_LRCK);
break;
case PINMUX_I2S2:
PINMUX_CONFIG(XGPIO_A_20, IIS2_DI);
PINMUX_CONFIG(EMMC_RSTN, IIS2_MCLK);
PINMUX_CONFIG(XGPIO_A_21, IIS2_DO);
PINMUX_CONFIG(XGPIO_A_26, IIS2_BCLK);
PINMUX_CONFIG(XGPIO_A_22, IIS2_LRCK);
break;
case PINMUX_SDIO0:
PINMUX_CONFIG(SDIO0_CD, SDIO0_CD);
PINMUX_CONFIG(SDIO0_PWR_EN, SDIO0_PWR_EN);
PINMUX_CONFIG(SDIO0_CMD, SDIO0_CMD);
PINMUX_CONFIG(SDIO0_CLK, SDIO0_CLK);
PINMUX_CONFIG(SDIO0_D0, SDIO0_D_0);
PINMUX_CONFIG(SDIO0_D1, SDIO0_D_1);
PINMUX_CONFIG(SDIO0_D2, SDIO0_D_2);
PINMUX_CONFIG(SDIO0_D3, SDIO0_D_3);
break;
case PINMUX_SDIO1:
PINMUX_CONFIG(XGPIO_A_24, SDIO1_CMD);
PINMUX_CONFIG(XGPIO_A_25, SDIO1_CLK);
PINMUX_CONFIG(XGPIO_A_23, SDIO1_D_0);
PINMUX_CONFIG(XGPIO_A_28, SDIO1_D_1);
PINMUX_CONFIG(XGPIO_A_27, SDIO1_D_2);
PINMUX_CONFIG(XGPIO_A_29, SDIO1_D_3);
PINMUX_CONFIG(XGPIO_A_22, XGPIOA_22);
break;
case PINMUX_EMMC:
PINMUX_CONFIG(EMMC_CLK, EMMC_CLK);
PINMUX_CONFIG(EMMC_RSTN, EMMC_RSTN);
PINMUX_CONFIG(EMMC_CMD, EMMC_CMD);
PINMUX_CONFIG(EMMC_DAT1, EMMC_DAT_1);
PINMUX_CONFIG(EMMC_DAT0, EMMC_DAT_0);
PINMUX_CONFIG(EMMC_DAT2, EMMC_DAT_2);
PINMUX_CONFIG(EMMC_DAT3, EMMC_DAT_3);
break;
case PINMUX_SPI_NOR:
PINMUX_CONFIG(EMMC_CLK, SPINOR_SCK);
PINMUX_CONFIG(EMMC_CMD, SPINOR_SDI);
PINMUX_CONFIG(EMMC_DAT1, SPINOR_CS_X);
PINMUX_CONFIG(EMMC_DAT0, SPINOR_SDO);
PINMUX_CONFIG(EMMC_DAT2, SPINOR_HOLD_X);
PINMUX_CONFIG(EMMC_DAT3, SPINOR_WP_X);
break;
case PINMUX_SPI_NAND:
PINMUX_CONFIG(EMMC_CLK, SPINAND_CLK);
PINMUX_CONFIG(EMMC_CMD, SPINAND_DI);
PINMUX_CONFIG(EMMC_DAT1, SPINAND_CS);
PINMUX_CONFIG(EMMC_DAT0, SPINAND_DO);
PINMUX_CONFIG(EMMC_DAT2, SPINAND_HOLD);
PINMUX_CONFIG(EMMC_DAT3, SPINAND_WP);
break;
case PINMUX_CAM0:
PINMUX_CONFIG(CAM_PD0, CAM_MCLK1);
PINMUX_CONFIG(CAM_MCLK0, CAM_MCLK0);
break;
case PINMUX_VI0:
printf("fix me: PINMUX_VI0\n");
break;
case PINMUX_VO:
printf("fix me: PINMUX_VO\n");
break;
case PINMUX_DSI:
PINMUX_CONFIG(PWM1, XGPIOB_4);
PINMUX_CONFIG(PWM2, XGPIOB_3);
PINMUX_CONFIG(PWM3, XGPIOB_5);
PINMUX_CONFIG(PAD_MIPI_TXM4, MIPI_TXM4);
PINMUX_CONFIG(PAD_MIPI_TXP4, MIPI_TXP4);
PINMUX_CONFIG(PAD_MIPI_TXM3, MIPI_TXM3);
PINMUX_CONFIG(PAD_MIPI_TXP3, MIPI_TXP3);
PINMUX_CONFIG(PAD_MIPI_TXM2, MIPI_TXM2);
PINMUX_CONFIG(PAD_MIPI_TXP2, MIPI_TXP2);
PINMUX_CONFIG(PAD_MIPI_TXM1, MIPI_TXM1);
PINMUX_CONFIG(PAD_MIPI_TXP1, MIPI_TXP1);
PINMUX_CONFIG(PAD_MIPI_TXM0, MIPI_TXM0);
PINMUX_CONFIG(PAD_MIPI_TXP0, MIPI_TXP0);
break;
case PINMUX_RMII1:
PINMUX_CONFIG(SPI0_SDI, RMII1_TXD3);
PINMUX_CONFIG(SPI0_SDO, RMII1_RXD3);
PINMUX_CONFIG(SPI0_SCK, RMII1_TXD2);
PINMUX_CONFIG(SPI0_CS_X, RMII1_RXD2);
PINMUX_CONFIG(IIC2_SCL, RMII1_MDIO);
PINMUX_CONFIG(IIC1_SCL, RMII1_RXD1);
PINMUX_CONFIG(IIC1_SDA, RMII1_REFCLKI);
PINMUX_CONFIG(UART2_TX, RMII1_RXD0);
PINMUX_CONFIG(IIC2_SDA, RMII1_MDC);
PINMUX_CONFIG(UART1_RTS, RMII1_TXD0);
PINMUX_CONFIG(UART2_RTS, RMII1_TXD1);
PINMUX_CONFIG(UART2_RX, RMII1_RXDV);
PINMUX_CONFIG(UART1_TX, RMII1_TXCLK);
PINMUX_CONFIG(UART1_CTS, XGPIOB_20);
PINMUX_CONFIG(UART2_CTS, RMII1_TXEN);
break;
case PINMUX_EPHY_LED:
PINMUX_CONFIG(XGPIO_A_26, EPHY_LNK_LED);
PINMUX_CONFIG(XGPIO_A_22, EPHY_SPD_LED);
break;
case PINMUX_I80:
PINMUX_CONFIG(VO_DATA1, VO_DATA_1);
PINMUX_CONFIG(VO_DATA0, VO_DATA_0);
PINMUX_CONFIG(PAD_MIPI_TXM4, VO_DATA_10);
PINMUX_CONFIG(PAD_MIPI_TXP4, VO_DATA_9);
PINMUX_CONFIG(PAD_MIPI_TXM3, VO_DATA_8);
PINMUX_CONFIG(PAD_MIPI_TXP3, VO_DATA_7);
PINMUX_CONFIG(PAD_MIPI_TXM2, VO_DATA_6);
PINMUX_CONFIG(PAD_MIPI_TXP2, VO_DATA_5);
PINMUX_CONFIG(PAD_MIPI_TXM1, VO_DATA_4);
PINMUX_CONFIG(PAD_MIPI_TXP1, VO_DATA_3);
PINMUX_CONFIG(PAD_MIPI_TXM0, VO_DATA_2);
PINMUX_CONFIG(PAD_MIPI_TXP0, VO_CLK);
break;
default:
break;
}
}
#define _reg_read(addr) readl((void __iomem *)addr)
#define _reg_write(addr, data) writel(data, (void __iomem *)addr)
static void cvsnfc_setup_internal_clk(void)
{
/*
* Set clk_spi_nand to 150Mhz
* write(0x3002088) = read(0x3002088)|0x10
* write(0x3002088) = 0x000A0019
* write(0x3002088) = 0x000A0009
*/
#define TOP_CLK_REG_BASE 0x3002000
#define REG_SPI_NAND_CLK_SETTING (TOP_CLK_REG_BASE + 0x88)
_reg_write(REG_SPI_NAND_CLK_SETTING, _reg_read(REG_SPI_NAND_CLK_SETTING) | 0x10);
mdelay(1);
_reg_write(REG_SPI_NAND_CLK_SETTING, 0x000A0019);
mdelay(1);
_reg_write(REG_SPI_NAND_CLK_SETTING, 0x000A0009);
}
#include "../cvi_board_init.c"
int board_init(void)
{
#if defined(CONFIG_TARGET_CVITEK_CV1835_ASIC) /* config eth internal phy on ASIC board */
unsigned int val;
//writel(0x00000000, 0x03002030);
//writel(0x00000000, 0x03002034);
val = readl(0x03009000) & ETH_PHY_INIT_MASK;
writel((val | ETH_PHY_SHUTDOWN) & ETH_PHY_RESET, 0x03009000);
mdelay(1);
writel(val & ETH_PHY_POWERUP & ETH_PHY_RESET, 0x03009000);
mdelay(20);
writel((val & ETH_PHY_POWERUP) | ETH_PHY_RESET_N, 0x03009000);
mdelay(1);
val = readl(0x03009000);
writel(readl(0x03009000) | ETH_PHY_LED_LOW_ACTIVE, 0x03009000);
#endif
/* Set ethernet clock resource */
#if defined(CONFIG_TARGET_CVITEK_CV1835_FPGA)
writel(0x000000C1, 0x03000034); /* Set eth0 RGMII, eth1 RMII clk resource and interface type*/
#elif defined(CONFIG_TARGET_CVITEK_CV1835_ASIC)
writel(0x0000001C, 0x03000034); /* Set eth0 RMII, eth1 RGMII clk resource and interface type*/
writel(0x00000020, 0x03001940); /* set TX driving strength of ASIC EVB RGMII interface */
writel(0x00000020, 0x03001918);
writel(0x00000020, 0x03001934);
writel(0x00000020, 0x03001938);
writel(0x00000020, 0x0300194c);
writel(0x00000020, 0x03001910);
writel(0x00000020, 0x03001928); /* Remove RX pull down */
writel(0x00000020, 0x0300193c);
writel(0x00000020, 0x0300192c);
writel(0x00000020, 0x03001924);
writel(0x00000020, 0x0300191c);
writel(0x00000020, 0x03001914);
writel(0x01070000, 0x030001CC); /* RGMII TX/RX delayline select config */
#elif defined(CONFIG_TARGET_CVITEK_CV1835_PALLADIUM)
writel(0x0000001C, 0x03000034); /* Set eth0 RMII, eth1 RGMII clk resource and interface type*/
#endif
#if defined(CONFIG_NAND_SUPPORT)
pinmux_config(PINMUX_SPI_NAND); // TODO, use gpio to decide storage pinmux
#elif defined(CONFIG_SPI_FLASH)
pinmux_config(PINMUX_SPI_NOR);
#elif defined(CONFIG_EMMC_SUPPORT)
pinmux_config(PINMUX_EMMC);
#endif
#ifdef CONFIG_DISPLAY_CVITEK_MIPI
pinmux_config(PINMUX_DSI);
#elif defined(CONFIG_DISPLAY_CVITEK_I80)
pinmux_config(PINMUX_I80);
#endif
#if defined(CV1835_WDMB_0001A_SPINAND)
PINMUX_CONFIG(UART1_RX, UART1_RX); //UART_RX,TX,CTS
PINMUX_CONFIG(UART1_TX, UART1_TX);
PINMUX_CONFIG(UART1_CTS, UART1_CTS);
#elif defined(CV1835_WDMB_0002A_SPINAND)
PINMUX_CONFIG(JTAG_CPU_TCK, XGPIOA_0); //IIC2_SHDN
PINMUX_CONFIG(IIC2_SCL, IIC2_SCL); //IIC2
PINMUX_CONFIG(IIC2_SDA, IIC2_SDA);
PINMUX_CONFIG(JTAG_CPU_TMS, XGPIOA_6);//AMP_MUTE
#elif defined(CV1832_WDMB_0002B_SPINAND)
PINMUX_CONFIG(PWM3, XGPIOB_5); //LED_PWM
PINMUX_CONFIG(UART1_CTS, XGPIOB_20); //ALARM_OUT
PINMUX_CONFIG(ADC1, XGPIOB_24); //IR_IN
PINMUX_CONFIG(VI_DATA19, XGPIOD_2); //ALARM_IN
PINMUX_CONFIG(VI_DATA20, XGPIOC_31); //KEY_SET
PINMUX_CONFIG(VI_DATA21, XGPIOD_0); //IR_CUT1
PINMUX_CONFIG(VI_DATA22, XGPIOC_30); //IR_CUT2
#elif defined(CV1835_WDMB_0003A)
pinmux_config(PINMUX_SDIO1);//wifi
PINMUX_CONFIG(ADC1, XGPIOB_24); //Light_INT
PINMUX_CONFIG(UART1_CTS, XGPIOB_20); //REMOVE_BUT
PINMUX_CONFIG(UART1_RTS, XGPIOB_16); //RELAY_C
PINMUX_CONFIG(JTAG_CPU_TCK, XGPIOA_0); //CAM1_PWDN
PINMUX_CONFIG(JTAG_CPU_TMS, XGPIOA_6); //CAM0_PWDN
PINMUX_CONFIG(SDIO0_D1, XGPIOA_17); //VO_IN
PINMUX_CONFIG(SDIO0_D2, XGPIOA_18); //NFC_IRQ
PINMUX_CONFIG(SPI0_SCK, SPI0_SCK); //NFC_SCK
PINMUX_CONFIG(SPI0_CS_X, XGPIOB_9); //NFC_CS_X
PINMUX_CONFIG(SPI0_SDI, SPI0_SDI); //NFC_SDI
PINMUX_CONFIG(SPI0_SDO, SPI0_SDO); //NFC_SDO
PINMUX_CONFIG(IIC1_SCL, IIC1_SCL); //RTC
PINMUX_CONFIG(IIC1_SDA, IIC1_SDA); //RTC
PINMUX_CONFIG(UART1_TX, UART1_TX); //RS485_A
PINMUX_CONFIG(UART1_RX, UART1_RX); //RS485_B
PINMUX_CONFIG(SDIO0_D3, XGPIOA_19); //RS485_RE_DE
PINMUX_CONFIG(XGPIO_A_26, EPHY_LNK_LED); //EPHY_SPD_LED
PINMUX_CONFIG(XGPIO_A_22, EPHY_SPD_LED); //EPHY_LNK_LED
PINMUX_CONFIG(PWM3, PWM_3); //white_led
#elif defined(CV9520_WEVB_0002A_V02_NVR)
#elif defined(CV9520_WDMB_0004A_V02_NVR)
pinmux_config(PINMUX_SDIO1); //WIFI
PINMUX_CONFIG(XGPIO_A_26, EPHY_LNK_LED); //EPHY_SPD_LED
PINMUX_CONFIG(XGPIO_A_22, EPHY_SPD_LED); //EPHY_LNK_LED
pinmux_config(PINMUX_RMII1); //ETH1
PINMUX_CONFIG(USB_VBUS_DET, USB_VBUS_DET); //USB_VBUS_DET
PINMUX_CONFIG(PWM1, PWM_1); //LCD Brightness PWM
PINMUX_CONFIG(MIPIRX0_PAD0N, XGPIOC_28); //TOUCHPAD
PINMUX_CONFIG(MIPIRX0_PAD0P, XGPIOC_29); //TOUCHPAD
#elif defined(CV9520_WEVB_0002A_V02_NVR_SPINAND)
#elif defined(CV9520_WDMB_0004A_V02_NVR_SPINAND)
pinmux_config(PINMUX_SDIO1); //WIFI
PINMUX_CONFIG(XGPIO_A_26, EPHY_LNK_LED); //EPHY_SPD_LED
PINMUX_CONFIG(XGPIO_A_22, EPHY_SPD_LED); //EPHY_LNK_LED
pinmux_config(PINMUX_RMII1); //ETH1
PINMUX_CONFIG(USB_VBUS_DET, USB_VBUS_DET); //USB_VBUS_DET
PINMUX_CONFIG(PWM1, PWM_1); //LCD Brightness PWM
PINMUX_CONFIG(MIPIRX0_PAD0N, XGPIOC_28); //TOUCHPAD
PINMUX_CONFIG(MIPIRX0_PAD0P, XGPIOC_29); //TOUCHPAD
#elif defined(CV1835_WEVB_0002A_I80)
pinmux_config(PINMUX_SDIO1);
pinmux_config(PINMUX_I2C1);
pinmux_config(PINMUX_I2C2);
pinmux_config(PINMUX_I2C3);
pinmux_config(PINMUX_UART1);
pinmux_config(PINMUX_UART2);
PINMUX_CONFIG(UART2_RTS, UART2_RTS);
PINMUX_CONFIG(UART2_CTS, UART2_CTS);
PINMUX_CONFIG(VI_DATA21, UART3_RX);//uart3
PINMUX_CONFIG(VI_DATA22, UART3_TX);
PINMUX_CONFIG(UART1_CTS, UART4_RX);//uart4
PINMUX_CONFIG(UART1_RTS, UART4_TX);
PINMUX_CONFIG(SPI0_SDI, SPI0_SDI);//spi0
PINMUX_CONFIG(SPI0_SDO, SPI0_SDO);
PINMUX_CONFIG(SPI0_SCK, SPI0_SCK);
PINMUX_CONFIG(SPI0_CS_X, XGPIOB_9);
PINMUX_CONFIG(SDIO0_PWR_EN, XGPIOA_4);//gpio
PINMUX_CONFIG(SDIO0_CMD, XGPIOA_14);
PINMUX_CONFIG(SDIO0_CLK, XGPIOA_15);
PINMUX_CONFIG(SDIO0_D0, XGPIOA_16);
PINMUX_CONFIG(SDIO0_D1, XGPIOA_17);
PINMUX_CONFIG(SDIO0_D2, XGPIOA_18);
PINMUX_CONFIG(SDIO0_D3, XGPIOA_19);
PINMUX_CONFIG(CAM_PD0, CAM_MCLK1); //cam_pd
PINMUX_CONFIG(JTAG_CPU_TRST, XGPIOA_2);
PINMUX_CONFIG(JTAG_CPU_TMS, XGPIOA_6);
#endif
cvsnfc_setup_internal_clk();
return cvi_board_init();
}
int dram_init(void)
{
unsigned int ddr_size;
ddr_size = readl(GP_REG8);
gd->ram_size = ddr_size ? ddr_size : PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init_banksize(void)
{
unsigned int ddr_size;
ddr_size = readl(GP_REG8);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = ddr_size ? ddr_size : PHYS_SDRAM_1_SIZE;
return 0;
}
/*
* Board specific reset that is system reset.
*/
void reset_cpu(ulong addr)
{
}
void software_root_reset(void)
{
unsigned int val;
writel(0x4, (RTC_BASE + RTC_DB_REQ_WARM_RST));
writel(0x1, (RTC_BASE + RTC_EN_WARM_RST_REQ));
writel(0xAB18, (RTCFC_BASE + RTC_CTRL0_UNLOCKKEY));
val = readl((RTCFC_BASE + RTC_CTRL0)) | 0xFFFF0000 | (0x1 << 4);
writel(val, (RTCFC_BASE + RTC_CTRL0));
}
/*
* Board specific ethernet initialization routine.
*/
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

521
u-boot-2021.10/board/cvitek/cv1835/cv1835_pinlist_swconfig.h Normal file
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@ -0,0 +1,521 @@
/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: cv1835_pinlist_swconfig.h
* Description:
*/
#ifndef __CV1835_PINLIST_SWCONFIG_H__
#define __CV1835_PINLIST_SWCONFIG_H__
//##==============================================================================
//##=== Generate Time stamp is : 2019-11-27 20:20:28
//##==============================================================================
#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
mmio_clrsetbits_32(PINMUX_BASE + fmux_gpio_funcsel_##PIN_NAME, \
fmux_gpio_funcsel_##PIN_NAME##_MASK << fmux_gpio_funcsel_##PIN_NAME##_OFFSET, \
PIN_NAME##__##FUNC_NAME)
#define JTAG_CPU_TCK__JTAG_CPU_TCK 0
#define JTAG_CPU_TCK__DBG_1 1
#define JTAG_CPU_TCK__XGPIOA_0 3
#define SDIO0_CD__SDIO0_CD 0
#define SDIO0_CD__DBG_6 1
#define SDIO0_CD__XGPIOA_1 3
#define RSTN__RSTN 0
#define JTAG_CPU_TRST__JTAG_CPU_TRST 0
#define JTAG_CPU_TRST__DBG_0 1
#define JTAG_CPU_TRST__XGPIOA_2 3
#define UART0_RX__UART0_RX 0
#define UART0_RX__DBG_4 1
#define UART0_RX__AUX0 2
#define UART0_RX__XGPIOA_3 3
#define UART0_RX__H265_UART_RX 4
#define UART0_RX__H264_UART_RX 5
#define SDIO0_PWR_EN__SDIO0_PWR_EN 0
#define SDIO0_PWR_EN__DBG_5 1
#define SDIO0_PWR_EN__XGPIOA_4 3
#define UART0_TX__UART0_TX 0
#define UART0_TX__DBG_3 1
#define UART0_TX__AUX1 2
#define UART0_TX__XGPIOA_5 3
#define UART0_TX__H265_UART_TX 4
#define UART0_TX__H264_UART_TX 5
#define JTAG_CPU_TMS__JTAG_CPU_TMS 0
#define JTAG_CPU_TMS__DBG_2 1
#define JTAG_CPU_TMS__XGPIOA_6 3
#define JTAG_CPU_TMS__JTAG_CPU_5W_TMS 4
#define EMMC_CLK__EMMC_CLK 0
#define EMMC_CLK__SPINOR_SCK 1
#define EMMC_CLK__SPINAND_CLK 2
#define EMMC_CLK__XGPIOA_7 3
#define EMMC_RSTN__EMMC_RSTN 0
#define EMMC_RSTN__XGPIOA_8 3
#define EMMC_RSTN__AUX2 4
#define EMMC_RSTN__IIS2_MCLK 5
#define EMMC_CMD__EMMC_CMD 0
#define EMMC_CMD__SPINOR_SDI 1
#define EMMC_CMD__SPINAND_DI 2
#define EMMC_CMD__XGPIOA_9 3
#define EMMC_DAT1__EMMC_DAT_1 0
#define EMMC_DAT1__SPINOR_CS_X 1
#define EMMC_DAT1__SPINAND_CS 2
#define EMMC_DAT1__XGPIOA_10 3
#define EMMC_DAT0__EMMC_DAT_0 0
#define EMMC_DAT0__SPINOR_SDO 1
#define EMMC_DAT0__SPINAND_DO 2
#define EMMC_DAT0__XGPIOA_11 3
#define EMMC_DAT2__EMMC_DAT_2 0
#define EMMC_DAT2__SPINOR_HOLD_X 1
#define EMMC_DAT2__SPINAND_HOLD 2
#define EMMC_DAT2__XGPIOA_12 3
#define EMMC_DAT3__EMMC_DAT_3 0
#define EMMC_DAT3__SPINOR_WP_X 1
#define EMMC_DAT3__SPINAND_WP 2
#define EMMC_DAT3__XGPIOA_13 3
#define SDIO0_CMD__SDIO0_CMD 0
#define SDIO0_CMD__DBG_11 1
#define SDIO0_CMD__XGPIOA_14 3
#define SDIO0_CLK__SDIO0_CLK 0
#define SDIO0_CLK__DBG_12 1
#define SDIO0_CLK__XGPIOA_15 3
#define SDIO0_D0__SDIO0_D_0 0
#define SDIO0_D0__DBG_10 1
#define SDIO0_D0__XGPIOA_16 3
#define SDIO0_D1__SDIO0_D_1 0
#define SDIO0_D1__DBG_9 1
#define SDIO0_D1__XGPIOA_17 3
#define SDIO0_D2__SDIO0_D_2 0
#define SDIO0_D2__DBG_8 1
#define SDIO0_D2__AUX0 2
#define SDIO0_D2__XGPIOA_18 3
#define SDIO0_D3__SDIO0_D_3 0
#define SDIO0_D3__DBG_7 1
#define SDIO0_D3__AUX1 2
#define SDIO0_D3__XGPIOA_19 3
#define XGPIO_A_20__UART1_TX 1
#define XGPIO_A_20__UART2_TX 2
#define XGPIO_A_20__XGPIOA_20 3
#define XGPIO_A_20__H265_UART_TX 4
#define XGPIO_A_20__IIS2_DI 5
#define XGPIO_A_20__H264_UART_TX 6
#define XGPIO_A_20__WG1_D0 7
#define XGPIO_A_21__UART1_RX 1
#define XGPIO_A_21__UART2_RX 2
#define XGPIO_A_21__XGPIOA_21 3
#define XGPIO_A_21__H265_UART_RX 4
#define XGPIO_A_21__IIS2_DO 5
#define XGPIO_A_21__H264_UART_RX 6
#define XGPIO_A_21__WG1_D1 7
#define XGPIO_A_22__UART1_CTS 1
#define XGPIO_A_22__UART2_CTS 2
#define XGPIO_A_22__XGPIOA_22 3
#define XGPIO_A_22__IIS2_LRCK 5
#define XGPIO_A_22__UART4_TX 6
#define XGPIO_A_22__EPHY_SPD_LED 7
#define XGPIO_A_23__SDIO1_D_0 1
#define XGPIO_A_23__SPI1_SDI 2
#define XGPIO_A_23__XGPIOA_23 3
#define XGPIO_A_23__EPHY_DPX_LED 6
#define XGPIO_A_24__SDIO1_CMD 1
#define XGPIO_A_24__SPI1_SDO 2
#define XGPIO_A_24__XGPIOA_24 3
#define XGPIO_A_24__EPHY_SPD_LED 6
#define XGPIO_A_25__SDIO1_CLK 1
#define XGPIO_A_25__SPI1_SCK 2
#define XGPIO_A_25__XGPIOA_25 3
#define XGPIO_A_25__EPHY_LNK_LED 6
#define XGPIO_A_26__UART1_RTS 1
#define XGPIO_A_26__UART2_RTS 2
#define XGPIO_A_26__XGPIOA_26 3
#define XGPIO_A_26__RMII0_IRQ 4
#define XGPIO_A_26__IIS2_BCLK 5
#define XGPIO_A_26__UART4_RX 6
#define XGPIO_A_26__EPHY_LNK_LED 7
#define XGPIO_A_27__SDIO1_D_2 1
#define XGPIO_A_27__XGPIOA_27 3
#define XGPIO_A_27__H265_UART_TX 4
#define XGPIO_A_27__EPHY_DPX_LED 6
#define XGPIO_A_27__H264_UART_TX 7
#define XGPIO_A_28__SDIO1_D_1 1
#define XGPIO_A_28__XGPIOA_28 3
#define XGPIO_A_28__H265_UART_RX 4
#define XGPIO_A_28__EPHY_SPD_LED 6
#define XGPIO_A_28__H264_UART_RX 7
#define XGPIO_A_29__SDIO1_D_3 1
#define XGPIO_A_29__SPI1_CS_X 2
#define XGPIO_A_29__XGPIOA_29 3
#define XGPIO_A_29__EPHY_LNK_LED 6
#define RTC_MODE__RTC_MODE 0
#define RTC_MODE__XGPIOA_30 3
#define PWR_WAKEUP0__PWR_WAKEUP0 0
#define PWR_WAKEUP0__XGPIOA_31 3
#define PWR_BUTTON1__PWR_BUTTON1 0
#define PWR_BUTTON1__XGPIOB_0 3
#define PWR_WAKEUP1__PWR_WAKEUP1 0
#define PWR_WAKEUP1__XGPIOB_1 3
#define PWR_BUTTON0__PWR_BUTTON0 0
#define PWR_BUTTON0__XGPIOD_11 3
#define PWR_VBAT_DET__PWR_VBAT_DET 0
#define PWR_ON__PWR_ON 0
#define PWR_ON__XGPIOB_2 3
#define PTEST__PTEST 0
#define PWM2__PWM_2 0
#define PWM2__IIC1_SCL 1
#define PWM2__KEY_COL2 2
#define PWM2__XGPIOB_3 3
#define PWM2__JTAG_CPU_5W_TDI 4
#define PWM2__UART3_RX 5
#define PWM2__WG2_D0 7
#define PWM0_BUCK__PWM_0 0
#define PWM0_BUCK__XGPIOB_6 3
#define PWM3__PWM_3 0
#define PWM3__IIC1_SDA 1
#define PWM3__KEY_COL3 2
#define PWM3__XGPIOB_5 3
#define PWM3__UART3_TX 5
#define PWM3__WG2_D1 7
#define PWM1__PWM_1 0
#define PWM1__XGPIOB_4 3
#define PWM1__JTAG_CPU_5W_TDO 4
#define SPI0_SDI__SPI0_SDI 0
#define SPI0_SDI__IIC2_SDA 1
#define SPI0_SDI__PWM_15 2
#define SPI0_SDI__XGPIOB_8 3
#define SPI0_SDI__UART3_CTS 4
#define SPI0_SDI__RMII1_TXD3 5
#define SPI0_SDI__SPINOR1_SDI 6
#define SPI0_SDO__SPI0_SDO 0
#define SPI0_SDO__IIC2_SCL 1
#define SPI0_SDO__PWM_14 2
#define SPI0_SDO__XGPIOB_10 3
#define SPI0_SDO__UART3_RTS 4
#define SPI0_SDO__RMII1_RXD3 5
#define SPI0_SDO__SPINOR1_SDO 6
#define SPI0_SCK__SPI0_SCK 0
#define SPI0_SCK__IIC4_SCL 1
#define SPI0_SCK__PWM_12 2
#define SPI0_SCK__XGPIOB_7 3
#define SPI0_SCK__UART3_RX 4
#define SPI0_SCK__RMII1_TXD2 5
#define SPI0_SCK__SPINOR1_SCK 6
#define SPI0_CS_X__SPI0_CS_X 0
#define SPI0_CS_X__IIC4_SDA 1
#define SPI0_CS_X__PWM_13 2
#define SPI0_CS_X__XGPIOB_9 3
#define SPI0_CS_X__UART3_TX 4
#define SPI0_CS_X__RMII1_RXD2 5
#define SPI0_CS_X__SPINOR1_CS_X 6
#define IIC2_SCL__IIC2_SCL 0
#define IIC2_SCL__PWM_14 1
#define IIC2_SCL__UART2_RX 2
#define IIC2_SCL__XGPIOB_11 3
#define IIC2_SCL__RMII1_MDIO 4
#define IIC1_SCL__IIC1_SCL 0
#define IIC1_SCL__PWM_12 1
#define IIC1_SCL__XGPIOB_12 3
#define IIC1_SCL__RMII1_RXD1 4
#define IIC1_SCL__SPINOR1_HOLD_X 6
#define IIC1_SDA__IIC1_SDA 0
#define IIC1_SDA__PWM_13 1
#define IIC1_SDA__XGPIOB_14 3
#define IIC1_SDA__RMII1_REFCLKI 4
#define IIC1_SDA__SPINOR1_WP_X 6
#define UART2_TX__UART2_TX 0
#define UART2_TX__PWM_11 1
#define UART2_TX__KEY_ROW3 2
#define UART2_TX__XGPIOB_15 3
#define UART2_TX__RMII1_RXD0 4
#define UART2_TX__WG2_D0 7
#define IIC2_SDA__IIC2_SDA 0
#define IIC2_SDA__PWM_15 1
#define IIC2_SDA__UART2_TX 2
#define IIC2_SDA__XGPIOB_13 3
#define IIC2_SDA__RMII1_MDC 4
#define UART1_RTS__UART1_RTS 0
#define UART1_RTS__PWM_7 1
#define UART1_RTS__KEY_COL1 2
#define UART1_RTS__XGPIOB_16 3
#define UART1_RTS__RMII1_TXD0 4
#define UART1_RTS__IIS1_DI 5
#define UART1_RTS__UART4_TX 7
#define UART2_RTS__UART2_RTS 0
#define UART2_RTS__PWM_8 1
#define UART2_RTS__KEY_ROW0 2
#define UART2_RTS__XGPIOB_18 3
#define UART2_RTS__RMII1_TXD1 4
#define UART2_RTS__IIS1_MCLK 5
#define UART2_RTS__WG1_D0 7
#define UART2_RX__UART2_RX 0
#define UART2_RX__PWM_10 1
#define UART2_RX__KEY_COL3 2
#define UART2_RX__XGPIOB_17 3
#define UART2_RX__RMII1_RXDV 4
#define UART2_RX__WG2_D1 7
#define UART1_TX__UART1_TX 0
#define UART1_TX__PWM_4 1
#define UART1_TX__KEY_COL2 2
#define UART1_TX__XGPIOB_21 3
#define UART1_TX__RMII1_TXCLK 4
#define UART1_TX__IIS1_BCLK 5
#define UART1_TX__EPHY_LNK_LED 7
#define UART1_CTS__UART1_CTS 0
#define UART1_CTS__PWM_6 1
#define UART1_CTS__KEY_COL0 2
#define UART1_CTS__XGPIOB_20 3
#define UART1_CTS__IIS1_DO 5
#define UART1_CTS__RMII1_IRQ 6
#define UART1_CTS__UART4_RX 7
#define BOOT_MS__BOOT_MS 0
#define BOOT_MS__XGPIOB_22 3
#define UART2_CTS__UART2_CTS 0
#define UART2_CTS__PWM_9 1
#define UART2_CTS__KEY_ROW1 2
#define UART2_CTS__XGPIOB_19 3
#define UART2_CTS__RMII1_TXEN 4
#define UART2_CTS__WG1_D1 7
#define ADC1__XGPIOB_24 3
#define UART1_RX__UART1_RX 0
#define UART1_RX__PWM_5 1
#define UART1_RX__KEY_ROW2 2
#define UART1_RX__XGPIOB_23 3
#define UART1_RX__IIS1_LRCK 5
#define UART1_RX__EPHY_SPD_LED 7
#define USB_ID__USB_ID 0
#define USB_ID__XGPIOB_26 3
#define USB_VBUS_DET__USB_VBUS_DET 0
#define USB_VBUS_DET__XGPIOB_25 3
#define USB_VBUS_EN__USB_VBUS_EN 0
#define USB_VBUS_EN__XGPIOB_27 3
#define CLK32K__CLK32K 0
#define CLK32K__AUX0 1
#define CLK32K__DBG_1 2
#define CLK32K__XGPIOB_29 3
#define CLK25M__CLK25M 0
#define CLK25M__AUX1 1
#define CLK25M__DBG_0 2
#define CLK25M__XGPIOB_28 3
#define XTAL_XIN_XI__XTAL_CLKIN 0
#define VO_DATA1__VO_DATA_1 1
#define VO_DATA1__XGPIOC_8 3
#define VO_DATA1__VO_BUS_1 6
#define VO_DATA0__VO_DATA_0 1
#define VO_DATA0__XGPIOC_9 3
#define VO_DATA0__VO_BUS_0 6
#define PAD_MIPI_TXM4__MIPI_TXM4 0
#define PAD_MIPI_TXM4__VO_DATA_10 1
#define PAD_MIPI_TXM4__DBG_13 2
#define PAD_MIPI_TXM4__XGPIOB_30 3
#define PAD_MIPI_TXM4__SPI3_SCK 4
#define PAD_MIPI_TXM4__PWM_12 5
#define PAD_MIPI_TXM4__VO_BUS_10 6
#define PAD_MIPI_TXP4__MIPI_TXP4 0
#define PAD_MIPI_TXP4__VO_DATA_9 1
#define PAD_MIPI_TXP4__DBG_14 2
#define PAD_MIPI_TXP4__XGPIOB_31 3
#define PAD_MIPI_TXP4__SPI3_CS_X 4
#define PAD_MIPI_TXP4__PWM_13 5
#define PAD_MIPI_TXP4__VO_BUS_9 6
#define PAD_MIPI_TXM3__MIPI_TXM3 0
#define PAD_MIPI_TXM3__VO_DATA_8 1
#define PAD_MIPI_TXM3__DBG_15 2
#define PAD_MIPI_TXM3__XGPIOC_0 3
#define PAD_MIPI_TXM3__SPI3_SDO 4
#define PAD_MIPI_TXM3__PWM_6 5
#define PAD_MIPI_TXM3__VO_BUS_8 6
#define PAD_MIPI_TXP3__MIPI_TXP3 0
#define PAD_MIPI_TXP3__VO_DATA_7 1
#define PAD_MIPI_TXP3__DBG_16 2
#define PAD_MIPI_TXP3__XGPIOC_1 3
#define PAD_MIPI_TXP3__SPI3_SDI 4
#define PAD_MIPI_TXP3__PWM_7 5
#define PAD_MIPI_TXP3__VO_BUS_7 6
#define PAD_MIPI_TXM2__MIPI_TXM2 0
#define PAD_MIPI_TXM2__VO_DATA_6 1
#define PAD_MIPI_TXM2__DBG_17 2
#define PAD_MIPI_TXM2__XGPIOC_2 3
#define PAD_MIPI_TXM2__KEY_ROW0 4
#define PAD_MIPI_TXM2__PWM_8 5
#define PAD_MIPI_TXM2__VO_BUS_6 6
#define PAD_MIPI_TXP2__MIPI_TXP2 0
#define PAD_MIPI_TXP2__VO_DATA_5 1
#define PAD_MIPI_TXP2__DBG_18 2
#define PAD_MIPI_TXP2__XGPIOC_3 3
#define PAD_MIPI_TXP2__KEY_ROW1 4
#define PAD_MIPI_TXP2__PWM_9 5
#define PAD_MIPI_TXP2__VO_BUS_5 6
#define PAD_MIPI_TXM1__MIPI_TXM1 0
#define PAD_MIPI_TXM1__VO_DATA_4 1
#define PAD_MIPI_TXM1__DBG_19 2
#define PAD_MIPI_TXM1__XGPIOC_4 3
#define PAD_MIPI_TXM1__KEY_ROW2 4
#define PAD_MIPI_TXM1__PWM_10 5
#define PAD_MIPI_TXM1__VO_BUS_4 6
#define PAD_MIPI_TXP1__MIPI_TXP1 0
#define PAD_MIPI_TXP1__VO_DATA_3 1
#define PAD_MIPI_TXP1__DBG_20 2
#define PAD_MIPI_TXP1__XGPIOC_5 3
#define PAD_MIPI_TXP1__KEY_ROW3 4
#define PAD_MIPI_TXP1__PWM_11 5
#define PAD_MIPI_TXP1__VO_BUS_3 6
#define PAD_MIPI_TXM0__MIPI_TXM0 0
#define PAD_MIPI_TXM0__VO_DATA_2 1
#define PAD_MIPI_TXM0__DBG_21 2
#define PAD_MIPI_TXM0__XGPIOC_6 3
#define PAD_MIPI_TXM0__KEY_COL0 4
#define PAD_MIPI_TXM0__PWM_14 5
#define PAD_MIPI_TXM0__VO_BUS_2 6
#define PAD_MIPI_TXP0__MIPI_TXP0 0
#define PAD_MIPI_TXP0__VO_CLK 1
#define PAD_MIPI_TXP0__DBG_22 2
#define PAD_MIPI_TXP0__XGPIOC_7 3
#define PAD_MIPI_TXP0__KEY_COL1 4
#define PAD_MIPI_TXP0__PWM_15 5
#define PAD_MIPI_TXP0__VO_BUS_11 6
#define MIPIRX1_PAD0P__VI_DATA_0 1
#define MIPIRX1_PAD0P__DBG_0 2
#define MIPIRX1_PAD0P__XGPIOC_10 3
#define MIPIRX1_PAD0P__VO_DATA_11 4
#define MIPIRX1_PAD0P__VI1_DATA_8 5
#define MIPIRX1_PAD0P__VO_BUS_12 6
#define MIPIRX1_PAD0N__VI_DATA_1 1
#define MIPIRX1_PAD0N__DBG_31 2
#define MIPIRX1_PAD0N__XGPIOC_11 3
#define MIPIRX1_PAD0N__VO_DATA_12 4
#define MIPIRX1_PAD0N__VI1_DATA_7 5
#define MIPIRX1_PAD0N__VO_BUS_13 6
#define MIPIRX1_PAD1P__VI_DATA_2 1
#define MIPIRX1_PAD1P__DBG_30 2
#define MIPIRX1_PAD1P__XGPIOC_12 3
#define MIPIRX1_PAD1P__VO_DATA_13 4
#define MIPIRX1_PAD1P__VI1_DATA_6 5
#define MIPIRX1_PAD1P__VO_BUS_14 6
#define MIPIRX1_PAD1N__VI_DATA_3 1
#define MIPIRX1_PAD1N__DBG_29 2
#define MIPIRX1_PAD1N__XGPIOC_13 3
#define MIPIRX1_PAD1N__VO_DATA_14 4
#define MIPIRX1_PAD1N__VI1_DATA_5 5
#define MIPIRX1_PAD1N__VO_BUS_15 6
#define MIPIRX1_PAD2P__VI_DATA_4 1
#define MIPIRX1_PAD2P__DBG_28 2
#define MIPIRX1_PAD2P__XGPIOC_14 3
#define MIPIRX1_PAD2P__VO_DATA_15 4
#define MIPIRX1_PAD2P__VI1_DATA_4 5
#define MIPIRX1_PAD2P__VO_BUS_16 6
#define MIPIRX1_PAD2N__VI_DATA_5 1
#define MIPIRX1_PAD2N__DBG_27 2
#define MIPIRX1_PAD2N__XGPIOC_15 3
#define MIPIRX1_PAD2N__VO_DATA_16 4
#define MIPIRX1_PAD2N__VI1_DATA_3 5
#define MIPIRX1_PAD2N__VO_BUS_17 6
#define MIPIRX1_PAD3P__VI_DATA_6 1
#define MIPIRX1_PAD3P__DBG_26 2
#define MIPIRX1_PAD3P__XGPIOC_16 3
#define MIPIRX1_PAD3P__VO_DATA_17 4
#define MIPIRX1_PAD3P__VI1_DATA_2 5
#define MIPIRX1_PAD3P__VO_BUS_18 6
#define MIPIRX1_PAD3N__VI_DATA_7 1
#define MIPIRX1_PAD3N__DBG_25 2
#define MIPIRX1_PAD3N__XGPIOC_17 3
#define MIPIRX1_PAD3N__VI1_DATA_1 5
#define MIPIRX1_PAD4P__VI_DATA_8 1
#define MIPIRX1_PAD4P__DBG_24 2
#define MIPIRX1_PAD4P__XGPIOC_18 3
#define MIPIRX1_PAD4P__VI1_DATA_0 5
#define MIPIRX1_PAD4N__VI_DATA_9 1
#define MIPIRX1_PAD4N__DBG_23 2
#define MIPIRX1_PAD4N__XGPIOC_19 3
#define MIPIRX1_PAD4N__VI1_CLK 5
#define MIPIRX0_PAD4N__VI_DATA_10 1
#define MIPIRX0_PAD4N__DBG_1 2
#define MIPIRX0_PAD4N__XGPIOC_20 3
#define MIPIRX0_PAD4N__VI1_DATA_9 5
#define MIPIRX0_PAD4P__VI_DATA_11 1
#define MIPIRX0_PAD4P__DBG_2 2
#define MIPIRX0_PAD4P__XGPIOC_21 3
#define MIPIRX0_PAD3N__VI_DATA_12 1
#define MIPIRX0_PAD3N__DBG_4 2
#define MIPIRX0_PAD3N__XGPIOC_23 3
#define MIPIRX0_PAD3P__VI_CLK 1
#define MIPIRX0_PAD3P__DBG_3 2
#define MIPIRX0_PAD3P__XGPIOC_22 3
#define MIPIRX0_PAD2N__VI_DATA_13 1
#define MIPIRX0_PAD2N__DBG_5 2
#define MIPIRX0_PAD2N__XGPIOC_24 3
#define MIPIRX0_PAD2N__IIC4_SCL 4
#define MIPIRX0_PAD2P__VI_DATA_14 1
#define MIPIRX0_PAD2P__DBG_6 2
#define MIPIRX0_PAD2P__XGPIOC_25 3
#define MIPIRX0_PAD2P__IIC4_SDA 4
#define MIPIRX0_PAD1N__VI_DATA_15 1
#define MIPIRX0_PAD1N__DBG_7 2
#define MIPIRX0_PAD1N__XGPIOC_26 3
#define MIPIRX0_PAD1N__KEY_ROW3 4
#define MIPIRX0_PAD1P__VI_DATA_16 1
#define MIPIRX0_PAD1P__DBG_8 2
#define MIPIRX0_PAD1P__XGPIOC_27 3
#define MIPIRX0_PAD1P__KEY_ROW2 4
#define MIPIRX0_PAD0N__VI_DATA_17 1
#define MIPIRX0_PAD0N__DBG_9 2
#define MIPIRX0_PAD0N__XGPIOC_28 3
#define MIPIRX0_PAD0P__VI_DATA_18 1
#define MIPIRX0_PAD0P__DBG_10 2
#define MIPIRX0_PAD0P__XGPIOC_29 3
#define VI_DATA22__VI_DATA_22 1
#define VI_DATA22__DBG_14 2
#define VI_DATA22__XGPIOC_30 3
#define VI_DATA22__KEY_COL1 4
#define VI_DATA22__UART3_TX 5
#define VI_DATA22__H265_UART_TX 6
#define VI_DATA22__H264_UART_TX 7
#define VI_DATA20__VI_DATA_20 1
#define VI_DATA20__DBG_12 2
#define VI_DATA20__XGPIOC_31 3
#define VI_DATA20__KEY_ROW0 4
#define VI_DATA21__VI_DATA_21 1
#define VI_DATA21__DBG_13 2
#define VI_DATA21__XGPIOD_0 3
#define VI_DATA21__KEY_COL0 4
#define VI_DATA21__UART3_RX 5
#define VI_DATA21__H265_UART_RX 6
#define VI_DATA21__H264_UART_RX 7
#define CAM_PD0__CAM_MCLK1 0
#define CAM_PD0__AUX2 2
#define CAM_PD0__XGPIOD_1 3
#define VI_DATA19__VI_DATA_19 1
#define VI_DATA19__DBG_11 2
#define VI_DATA19__XGPIOD_2 3
#define VI_DATA19__KEY_ROW1 4
#define IIC0_SDA__IIC0_SDA 0
#define IIC0_SDA__SPI2_SDO 1
#define IIC0_SDA__XGPIOD_3 3
#define CAM_MCLK0__CAM_MCLK0 0
#define CAM_MCLK0__AUX3 2
#define CAM_MCLK0__XGPIOD_4 3
#define IIC3_SCL__IIC3_SCL 0
#define IIC3_SCL__SPI2_SCK 1
#define IIC3_SCL__DBG_17 2
#define IIC3_SCL__XGPIOD_5 3
#define IIC3_SCL__IIC4_SCL 4
#define VI_DATA24__VI_DATA_24 1
#define VI_DATA24__DBG_16 2
#define VI_DATA24__XGPIOD_6 3
#define VI_DATA24__KEY_COL3 4
#define VI_DATA24__UART3_CTS 5
#define CAM_RST0__XGPIOD_7 3
#define VI_DATA23__VI_DATA_23 1
#define VI_DATA23__DBG_15 2
#define VI_DATA23__XGPIOD_8 3
#define VI_DATA23__KEY_COL2 4
#define VI_DATA23__UART3_RTS 5
#define IIC3_SDA__IIC3_SDA 0
#define IIC3_SDA__SPI2_CS_X 1
#define IIC3_SDA__DBG_18 2
#define IIC3_SDA__XGPIOD_9 3
#define IIC3_SDA__IIC4_SDA 4
#define IIC0_SCL__IIC0_SCL 0
#define IIC0_SCL__SPI2_SDI 1
#define IIC0_SCL__XGPIOD_10 3
#endif /* __CV1835_PINLIST_SWCONFIG_H__ */

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#ifndef __CV1835_REG_H
#define __CV1835_REG_H
#define TOP_BASE 0x03000000
#define PINMUX_BASE (TOP_BASE + 0x1000)
#define WATCHDOG_BASE (TOP_BASE + 0x00010000)
/*
* Pinmux definitions
*/
#define PINMUX_UART0 0
#define PINMUX_UART1 1
#define PINMUX_UART2 2
#define PINMUX_UART3 3
#define PINMUX_UART3_2 4
#define PINMUX_I2C0 5
#define PINMUX_I2C1 6
#define PINMUX_I2C2 7
#define PINMUX_I2C3 8
#define PINMUX_I2C4 9
#define PINMUX_I2C4_2 10
#define PINMUX_SPI0 11
#define PINMUX_SPI1 12
#define PINMUX_SPI2 13
#define PINMUX_SPI2_2 14
#define PINMUX_SPI3 15
#define PINMUX_SPI3_2 16
#define PINMUX_I2S0 17
#define PINMUX_I2S1 18
#define PINMUX_I2S2 19
#define PINMUX_I2S3 20
#define PINMUX_USBID 21
#define PINMUX_SDIO0 22
#define PINMUX_SDIO1 23
#define PINMUX_ND 24
#define PINMUX_EMMC 25
#define PINMUX_SPI_NOR 26
#define PINMUX_SPI_NAND 27
#define PINMUX_CAM0 28
#define PINMUX_CAM1 29
#define PINMUX_PCM0 30
#define PINMUX_PCM1 31
#define PINMUX_CSI0 32
#define PINMUX_CSI1 33
#define PINMUX_CSI2 34
#define PINMUX_DSI 35
#define PINMUX_VI0 36
#define PINMUX_VO 37
#define PINMUX_RMII1 38
#define PINMUX_EPHY_LED 39
#define PINMUX_I80 40
#define PINMUX_LVDS 41
/* rst */
#define REG_TOP_SOFT_RST 0x3000
#define BIT_TOP_SOFT_RST_USB BIT(11)
#define BIT_TOP_SOFT_RST_SDIO BIT(14)
#define BIT_TOP_SOFT_RST_NAND BIT(12)
#define REG_TOP_USB_CTRSTS (TOP_BASE + 0x38)
#define REG_TOP_CONF_INFO (TOP_BASE + 0x4)
#define BIT_TOP_CONF_INFO_VBUS BIT(9)
#define REG_TOP_USB_PHY_CTRL (TOP_BASE + 0x48)
#define BIT_TOP_USB_PHY_CTRL_EXTVBUS BIT(0)
#define REG_TOP_DDR_ADDR_MODE (TOP_BASE + 0x64)
/* irq */
#define IRQ_LEVEL 0
#define IRQ_EDGE 3
/* usb */
#define USB_BASE 0x040C0000
#define USB_HOST_BASE 0x040D0000
#define USB_DEV_BASE 0x040E0000
/* ethernet phy */
#define ETH_PHY_BASE 0x03009000
#define ETH_PHY_INIT_MASK 0xFFFFFFF9
#define ETH_PHY_SHUTDOWN BIT(1)
#define ETH_PHY_POWERUP 0xFFFFFFFD
#define ETH_PHY_RESET 0xFFFFFFFB
#define ETH_PHY_RESET_N BIT(2)
#define ETH_PHY_LED_LOW_ACTIVE BIT(3)
/* watchdog */
#define WDT_BASE 0x03010000
#define DW_WDT_CR 0x00
#define DW_WDT_TORR 0x04
#define DW_WDT_CRR 0x0C
#define DW_WDT_CR_EN_OFFSET 0x00
#define DW_WDT_CR_RMOD_OFFSET 0x01
#define DW_WDT_CR_RMOD_VAL 0x00
#define DW_WDT_CRR_RESTART_VAL 0x76
/* rtc */
#define RTC_BASE 0x03005000
#define RTC_DB_REQ_WARM_RST 0x60
#define RTC_EN_WARM_RST_REQ 0xcc
#define RTCFC_BASE 0x03004000
#define RTC_CTRL0_UNLOCKKEY 0x4
#define RTC_CTRL0 0x8
/* rst */
#define CV183X_SOFT_RST_REG0 0x03003000
#define CV183X_SOFT_RST_REG1 0x03003004
/* gp_reg */
#define GP_REG2 0x03000088
#define GP_REG3 0x0300008C
#define GP_REG4 0x03000090
#define GP_REG5 0x03000094
#define GP_REG8 0x030000A0
#endif /* __CV1835_REG_H */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: cv1835_reg_fmux_gpio.h
* Description:
*/
// $Module: fmux_gpio $
// $RegisterBank Version: V 1.0.00 $
// $Author: ghost $
// $Date: Wed, 27 Nov 2019 08:24:45 PM $
//
#ifndef __CV1835_REG_FMUX_GPIO_H__
#define __CV1835_REG_FMUX_GPIO_H__
//GEN REG ADDR/OFFSET/MASK
#define fmux_gpio_REG_IOCTRL_JTAG_CPU_TCK 0x0
#define fmux_gpio_REG_IOCTRL_SDIO0_CD 0x4
#define fmux_gpio_REG_IOCTRL_RSTN 0x8
#define fmux_gpio_REG_IOCTRL_JTAG_CPU_TRST 0xc
#define fmux_gpio_REG_IOCTRL_UART0_RX 0x10
#define fmux_gpio_REG_IOCTRL_SDIO0_PWR_EN 0x14
#define fmux_gpio_REG_IOCTRL_UART0_TX 0x18
#define fmux_gpio_REG_IOCTRL_JTAG_CPU_TMS 0x1c
#define fmux_gpio_REG_IOCTRL_EMMC_CLK 0x20
#define fmux_gpio_REG_IOCTRL_EMMC_RSTN 0x24
#define fmux_gpio_REG_IOCTRL_EMMC_CMD 0x28
#define fmux_gpio_REG_IOCTRL_EMMC_DAT1 0x2c
#define fmux_gpio_REG_IOCTRL_EMMC_DAT0 0x30
#define fmux_gpio_REG_IOCTRL_EMMC_DAT2 0x34
#define fmux_gpio_REG_IOCTRL_EMMC_DAT3 0x38
#define fmux_gpio_REG_IOCTRL_SDIO0_CMD 0x3c
#define fmux_gpio_REG_IOCTRL_SDIO0_CLK 0x40
#define fmux_gpio_REG_IOCTRL_SDIO0_D0 0x44
#define fmux_gpio_REG_IOCTRL_SDIO0_D1 0x48
#define fmux_gpio_REG_IOCTRL_SDIO0_D2 0x4c
#define fmux_gpio_REG_IOCTRL_SDIO0_D3 0x50
#define fmux_gpio_REG_IOCTRL_XGPIO_A_20 0x54
#define fmux_gpio_REG_IOCTRL_XGPIO_A_21 0x58
#define fmux_gpio_REG_IOCTRL_XGPIO_A_22 0x5c
#define fmux_gpio_REG_IOCTRL_XGPIO_A_23 0x60
#define fmux_gpio_REG_IOCTRL_XGPIO_A_24 0x64
#define fmux_gpio_REG_IOCTRL_XGPIO_A_25 0x68
#define fmux_gpio_REG_IOCTRL_XGPIO_A_26 0x6c
#define fmux_gpio_REG_IOCTRL_XGPIO_A_27 0x70
#define fmux_gpio_REG_IOCTRL_XGPIO_A_28 0x74
#define fmux_gpio_REG_IOCTRL_XGPIO_A_29 0x78
#define fmux_gpio_REG_IOCTRL_RTC_MODE 0x7c
#define fmux_gpio_REG_IOCTRL_PWR_WAKEUP0 0x80
#define fmux_gpio_REG_IOCTRL_PWR_BUTTON1 0x84
#define fmux_gpio_REG_IOCTRL_PWR_WAKEUP1 0x88
#define fmux_gpio_REG_IOCTRL_PWR_BUTTON0 0x8c
#define fmux_gpio_REG_IOCTRL_PWR_VBAT_DET 0x90
#define fmux_gpio_REG_IOCTRL_PWR_ON 0x94
#define fmux_gpio_REG_IOCTRL_PWM2 0x98
#define fmux_gpio_REG_IOCTRL_PWM0_BUCK 0x9c
#define fmux_gpio_REG_IOCTRL_PWM3 0xa0
#define fmux_gpio_REG_IOCTRL_PWM1 0xa4
#define fmux_gpio_REG_IOCTRL_SPI0_SDI 0xa8
#define fmux_gpio_REG_IOCTRL_SPI0_SDO 0xac
#define fmux_gpio_REG_IOCTRL_SPI0_SCK 0xb0
#define fmux_gpio_REG_IOCTRL_SPI0_CS_X 0xb4
#define fmux_gpio_REG_IOCTRL_IIC2_SCL 0xb8
#define fmux_gpio_REG_IOCTRL_IIC1_SCL 0xbc
#define fmux_gpio_REG_IOCTRL_IIC1_SDA 0xc0
#define fmux_gpio_REG_IOCTRL_UART2_TX 0xc4
#define fmux_gpio_REG_IOCTRL_IIC2_SDA 0xc8
#define fmux_gpio_REG_IOCTRL_UART1_RTS 0xcc
#define fmux_gpio_REG_IOCTRL_UART2_RTS 0xd0
#define fmux_gpio_REG_IOCTRL_UART2_RX 0xd4
#define fmux_gpio_REG_IOCTRL_UART1_TX 0xd8
#define fmux_gpio_REG_IOCTRL_UART1_CTS 0xdc
#define fmux_gpio_REG_IOCTRL_BOOT_MS 0xe0
#define fmux_gpio_REG_IOCTRL_UART2_CTS 0xe4
#define fmux_gpio_REG_IOCTRL_ADC1 0xe8
#define fmux_gpio_REG_IOCTRL_UART1_RX 0xec
#define fmux_gpio_REG_IOCTRL_USB_ID 0xf0
#define fmux_gpio_REG_IOCTRL_USB_VBUS_DET 0xf4
#define fmux_gpio_REG_IOCTRL_USB_VBUS_EN 0xf8
#define fmux_gpio_REG_IOCTRL_CLK32K 0xfc
#define fmux_gpio_REG_IOCTRL_CLK25M 0x100
#define fmux_gpio_REG_IOCTRL_XTAL_XIN_XI 0x104
#define fmux_gpio_REG_IOCTRL_VO_DATA1 0x108
#define fmux_gpio_REG_IOCTRL_VO_DATA0 0x10c
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXM4 0x110
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXP4 0x114
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXM3 0x118
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXP3 0x11c
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXM2 0x120
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXP2 0x124
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXM1 0x128
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXP1 0x12c
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXM0 0x130
#define fmux_gpio_REG_IOCTRL_PAD_MIPI_TXP0 0x134
#define fmux_gpio_REG_IOCTRL_MIPIRX1_PAD0P 0x138
#define fmux_gpio_REG_IOCTRL_MIPIRX1_PAD0N 0x13c
#define fmux_gpio_REG_IOCTRL_MIPIRX1_PAD1P 0x140
#define fmux_gpio_REG_IOCTRL_MIPIRX1_PAD1N 0x144
#define fmux_gpio_REG_IOCTRL_MIPIRX1_PAD2P 0x148
#define fmux_gpio_REG_IOCTRL_MIPIRX1_PAD2N 0x14c
#define fmux_gpio_REG_IOCTRL_MIPIRX1_PAD3P 0x150
#define fmux_gpio_REG_IOCTRL_MIPIRX1_PAD3N 0x154
#define fmux_gpio_REG_IOCTRL_MIPIRX1_PAD4P 0x158
#define fmux_gpio_REG_IOCTRL_MIPIRX1_PAD4N 0x15c
#define fmux_gpio_REG_IOCTRL_MIPIRX0_PAD4N 0x160
#define fmux_gpio_REG_IOCTRL_MIPIRX0_PAD4P 0x164
#define fmux_gpio_REG_IOCTRL_MIPIRX0_PAD3N 0x168
#define fmux_gpio_REG_IOCTRL_MIPIRX0_PAD3P 0x16c
#define fmux_gpio_REG_IOCTRL_MIPIRX0_PAD2N 0x170
#define fmux_gpio_REG_IOCTRL_MIPIRX0_PAD2P 0x174
#define fmux_gpio_REG_IOCTRL_MIPIRX0_PAD1N 0x178
#define fmux_gpio_REG_IOCTRL_MIPIRX0_PAD1P 0x17c
#define fmux_gpio_REG_IOCTRL_MIPIRX0_PAD0N 0x180
#define fmux_gpio_REG_IOCTRL_MIPIRX0_PAD0P 0x184
#define fmux_gpio_REG_IOCTRL_VI_DATA22 0x188
#define fmux_gpio_REG_IOCTRL_VI_DATA20 0x18c
#define fmux_gpio_REG_IOCTRL_VI_DATA21 0x190
#define fmux_gpio_REG_IOCTRL_CAM_PD0 0x194
#define fmux_gpio_REG_IOCTRL_VI_DATA19 0x198
#define fmux_gpio_REG_IOCTRL_IIC0_SDA 0x19c
#define fmux_gpio_REG_IOCTRL_CAM_MCLK0 0x1a0
#define fmux_gpio_REG_IOCTRL_IIC3_SCL 0x1a4
#define fmux_gpio_REG_IOCTRL_VI_DATA24 0x1a8
#define fmux_gpio_REG_IOCTRL_CAM_RST0 0x1ac
#define fmux_gpio_REG_IOCTRL_VI_DATA23 0x1b0
#define fmux_gpio_REG_IOCTRL_IIC3_SDA 0x1b4
#define fmux_gpio_REG_IOCTRL_IIC0_SCL 0x1b8
#define fmux_gpio_funcsel_JTAG_CPU_TCK 0x0
#define fmux_gpio_funcsel_JTAG_CPU_TCK_OFFSET 0
#define fmux_gpio_funcsel_JTAG_CPU_TCK_MASK 0x7
#define fmux_gpio_funcsel_SDIO0_CD 0x4
#define fmux_gpio_funcsel_SDIO0_CD_OFFSET 0
#define fmux_gpio_funcsel_SDIO0_CD_MASK 0x7
#define fmux_gpio_funcsel_RSTN 0x8
#define fmux_gpio_funcsel_RSTN_OFFSET 0
#define fmux_gpio_funcsel_RSTN_MASK 0x7
#define fmux_gpio_funcsel_JTAG_CPU_TRST 0xc
#define fmux_gpio_funcsel_JTAG_CPU_TRST_OFFSET 0
#define fmux_gpio_funcsel_JTAG_CPU_TRST_MASK 0x7
#define fmux_gpio_funcsel_UART0_RX 0x10
#define fmux_gpio_funcsel_UART0_RX_OFFSET 0
#define fmux_gpio_funcsel_UART0_RX_MASK 0x7
#define fmux_gpio_funcsel_SDIO0_PWR_EN 0x14
#define fmux_gpio_funcsel_SDIO0_PWR_EN_OFFSET 0
#define fmux_gpio_funcsel_SDIO0_PWR_EN_MASK 0x7
#define fmux_gpio_funcsel_UART0_TX 0x18
#define fmux_gpio_funcsel_UART0_TX_OFFSET 0
#define fmux_gpio_funcsel_UART0_TX_MASK 0x7
#define fmux_gpio_funcsel_JTAG_CPU_TMS 0x1c
#define fmux_gpio_funcsel_JTAG_CPU_TMS_OFFSET 0
#define fmux_gpio_funcsel_JTAG_CPU_TMS_MASK 0x7
#define fmux_gpio_funcsel_EMMC_CLK 0x20
#define fmux_gpio_funcsel_EMMC_CLK_OFFSET 0
#define fmux_gpio_funcsel_EMMC_CLK_MASK 0x7
#define fmux_gpio_funcsel_EMMC_RSTN 0x24
#define fmux_gpio_funcsel_EMMC_RSTN_OFFSET 0
#define fmux_gpio_funcsel_EMMC_RSTN_MASK 0x7
#define fmux_gpio_funcsel_EMMC_CMD 0x28
#define fmux_gpio_funcsel_EMMC_CMD_OFFSET 0
#define fmux_gpio_funcsel_EMMC_CMD_MASK 0x7
#define fmux_gpio_funcsel_EMMC_DAT1 0x2c
#define fmux_gpio_funcsel_EMMC_DAT1_OFFSET 0
#define fmux_gpio_funcsel_EMMC_DAT1_MASK 0x7
#define fmux_gpio_funcsel_EMMC_DAT0 0x30
#define fmux_gpio_funcsel_EMMC_DAT0_OFFSET 0
#define fmux_gpio_funcsel_EMMC_DAT0_MASK 0x7
#define fmux_gpio_funcsel_EMMC_DAT2 0x34
#define fmux_gpio_funcsel_EMMC_DAT2_OFFSET 0
#define fmux_gpio_funcsel_EMMC_DAT2_MASK 0x7
#define fmux_gpio_funcsel_EMMC_DAT3 0x38
#define fmux_gpio_funcsel_EMMC_DAT3_OFFSET 0
#define fmux_gpio_funcsel_EMMC_DAT3_MASK 0x7
#define fmux_gpio_funcsel_SDIO0_CMD 0x3c
#define fmux_gpio_funcsel_SDIO0_CMD_OFFSET 0
#define fmux_gpio_funcsel_SDIO0_CMD_MASK 0x7
#define fmux_gpio_funcsel_SDIO0_CLK 0x40
#define fmux_gpio_funcsel_SDIO0_CLK_OFFSET 0
#define fmux_gpio_funcsel_SDIO0_CLK_MASK 0x7
#define fmux_gpio_funcsel_SDIO0_D0 0x44
#define fmux_gpio_funcsel_SDIO0_D0_OFFSET 0
#define fmux_gpio_funcsel_SDIO0_D0_MASK 0x7
#define fmux_gpio_funcsel_SDIO0_D1 0x48
#define fmux_gpio_funcsel_SDIO0_D1_OFFSET 0
#define fmux_gpio_funcsel_SDIO0_D1_MASK 0x7
#define fmux_gpio_funcsel_SDIO0_D2 0x4c
#define fmux_gpio_funcsel_SDIO0_D2_OFFSET 0
#define fmux_gpio_funcsel_SDIO0_D2_MASK 0x7
#define fmux_gpio_funcsel_SDIO0_D3 0x50
#define fmux_gpio_funcsel_SDIO0_D3_OFFSET 0
#define fmux_gpio_funcsel_SDIO0_D3_MASK 0x7
#define fmux_gpio_funcsel_XGPIO_A_20 0x54
#define fmux_gpio_funcsel_XGPIO_A_20_OFFSET 0
#define fmux_gpio_funcsel_XGPIO_A_20_MASK 0x7
#define fmux_gpio_funcsel_XGPIO_A_21 0x58
#define fmux_gpio_funcsel_XGPIO_A_21_OFFSET 0
#define fmux_gpio_funcsel_XGPIO_A_21_MASK 0x7
#define fmux_gpio_funcsel_XGPIO_A_22 0x5c
#define fmux_gpio_funcsel_XGPIO_A_22_OFFSET 0
#define fmux_gpio_funcsel_XGPIO_A_22_MASK 0x7
#define fmux_gpio_funcsel_XGPIO_A_23 0x60
#define fmux_gpio_funcsel_XGPIO_A_23_OFFSET 0
#define fmux_gpio_funcsel_XGPIO_A_23_MASK 0x7
#define fmux_gpio_funcsel_XGPIO_A_24 0x64
#define fmux_gpio_funcsel_XGPIO_A_24_OFFSET 0
#define fmux_gpio_funcsel_XGPIO_A_24_MASK 0x7
#define fmux_gpio_funcsel_XGPIO_A_25 0x68
#define fmux_gpio_funcsel_XGPIO_A_25_OFFSET 0
#define fmux_gpio_funcsel_XGPIO_A_25_MASK 0x7
#define fmux_gpio_funcsel_XGPIO_A_26 0x6c
#define fmux_gpio_funcsel_XGPIO_A_26_OFFSET 0
#define fmux_gpio_funcsel_XGPIO_A_26_MASK 0x7
#define fmux_gpio_funcsel_XGPIO_A_27 0x70
#define fmux_gpio_funcsel_XGPIO_A_27_OFFSET 0
#define fmux_gpio_funcsel_XGPIO_A_27_MASK 0x7
#define fmux_gpio_funcsel_XGPIO_A_28 0x74
#define fmux_gpio_funcsel_XGPIO_A_28_OFFSET 0
#define fmux_gpio_funcsel_XGPIO_A_28_MASK 0x7
#define fmux_gpio_funcsel_XGPIO_A_29 0x78
#define fmux_gpio_funcsel_XGPIO_A_29_OFFSET 0
#define fmux_gpio_funcsel_XGPIO_A_29_MASK 0x7
#define fmux_gpio_funcsel_RTC_MODE 0x7c
#define fmux_gpio_funcsel_RTC_MODE_OFFSET 0
#define fmux_gpio_funcsel_RTC_MODE_MASK 0x7
#define fmux_gpio_funcsel_PWR_WAKEUP0 0x80
#define fmux_gpio_funcsel_PWR_WAKEUP0_OFFSET 0
#define fmux_gpio_funcsel_PWR_WAKEUP0_MASK 0x7
#define fmux_gpio_funcsel_PWR_BUTTON1 0x84
#define fmux_gpio_funcsel_PWR_BUTTON1_OFFSET 0
#define fmux_gpio_funcsel_PWR_BUTTON1_MASK 0x7
#define fmux_gpio_funcsel_PWR_WAKEUP1 0x88
#define fmux_gpio_funcsel_PWR_WAKEUP1_OFFSET 0
#define fmux_gpio_funcsel_PWR_WAKEUP1_MASK 0x7
#define fmux_gpio_funcsel_PWR_BUTTON0 0x8c
#define fmux_gpio_funcsel_PWR_BUTTON0_OFFSET 0
#define fmux_gpio_funcsel_PWR_BUTTON0_MASK 0x7
#define fmux_gpio_funcsel_PWR_VBAT_DET 0x90
#define fmux_gpio_funcsel_PWR_VBAT_DET_OFFSET 0
#define fmux_gpio_funcsel_PWR_VBAT_DET_MASK 0x7
#define fmux_gpio_funcsel_PWR_ON 0x94
#define fmux_gpio_funcsel_PWR_ON_OFFSET 0
#define fmux_gpio_funcsel_PWR_ON_MASK 0x7
#define fmux_gpio_funcsel_PWM2 0x98
#define fmux_gpio_funcsel_PWM2_OFFSET 0
#define fmux_gpio_funcsel_PWM2_MASK 0x7
#define fmux_gpio_funcsel_PWM0_BUCK 0x9c
#define fmux_gpio_funcsel_PWM0_BUCK_OFFSET 0
#define fmux_gpio_funcsel_PWM0_BUCK_MASK 0x7
#define fmux_gpio_funcsel_PWM3 0xa0
#define fmux_gpio_funcsel_PWM3_OFFSET 0
#define fmux_gpio_funcsel_PWM3_MASK 0x7
#define fmux_gpio_funcsel_PWM1 0xa4
#define fmux_gpio_funcsel_PWM1_OFFSET 0
#define fmux_gpio_funcsel_PWM1_MASK 0x7
#define fmux_gpio_funcsel_SPI0_SDI 0xa8
#define fmux_gpio_funcsel_SPI0_SDI_OFFSET 0
#define fmux_gpio_funcsel_SPI0_SDI_MASK 0x7
#define fmux_gpio_funcsel_SPI0_SDO 0xac
#define fmux_gpio_funcsel_SPI0_SDO_OFFSET 0
#define fmux_gpio_funcsel_SPI0_SDO_MASK 0x7
#define fmux_gpio_funcsel_SPI0_SCK 0xb0
#define fmux_gpio_funcsel_SPI0_SCK_OFFSET 0
#define fmux_gpio_funcsel_SPI0_SCK_MASK 0x7
#define fmux_gpio_funcsel_SPI0_CS_X 0xb4
#define fmux_gpio_funcsel_SPI0_CS_X_OFFSET 0
#define fmux_gpio_funcsel_SPI0_CS_X_MASK 0x7
#define fmux_gpio_funcsel_IIC2_SCL 0xb8
#define fmux_gpio_funcsel_IIC2_SCL_OFFSET 0
#define fmux_gpio_funcsel_IIC2_SCL_MASK 0x7
#define fmux_gpio_funcsel_IIC1_SCL 0xbc
#define fmux_gpio_funcsel_IIC1_SCL_OFFSET 0
#define fmux_gpio_funcsel_IIC1_SCL_MASK 0x7
#define fmux_gpio_funcsel_IIC1_SDA 0xc0
#define fmux_gpio_funcsel_IIC1_SDA_OFFSET 0
#define fmux_gpio_funcsel_IIC1_SDA_MASK 0x7
#define fmux_gpio_funcsel_UART2_TX 0xc4
#define fmux_gpio_funcsel_UART2_TX_OFFSET 0
#define fmux_gpio_funcsel_UART2_TX_MASK 0x7
#define fmux_gpio_funcsel_IIC2_SDA 0xc8
#define fmux_gpio_funcsel_IIC2_SDA_OFFSET 0
#define fmux_gpio_funcsel_IIC2_SDA_MASK 0x7
#define fmux_gpio_funcsel_UART1_RTS 0xcc
#define fmux_gpio_funcsel_UART1_RTS_OFFSET 0
#define fmux_gpio_funcsel_UART1_RTS_MASK 0x7
#define fmux_gpio_funcsel_UART2_RTS 0xd0
#define fmux_gpio_funcsel_UART2_RTS_OFFSET 0
#define fmux_gpio_funcsel_UART2_RTS_MASK 0x7
#define fmux_gpio_funcsel_UART2_RX 0xd4
#define fmux_gpio_funcsel_UART2_RX_OFFSET 0
#define fmux_gpio_funcsel_UART2_RX_MASK 0x7
#define fmux_gpio_funcsel_UART1_TX 0xd8
#define fmux_gpio_funcsel_UART1_TX_OFFSET 0
#define fmux_gpio_funcsel_UART1_TX_MASK 0x7
#define fmux_gpio_funcsel_UART1_CTS 0xdc
#define fmux_gpio_funcsel_UART1_CTS_OFFSET 0
#define fmux_gpio_funcsel_UART1_CTS_MASK 0x7
#define fmux_gpio_funcsel_BOOT_MS 0xe0
#define fmux_gpio_funcsel_BOOT_MS_OFFSET 0
#define fmux_gpio_funcsel_BOOT_MS_MASK 0x7
#define fmux_gpio_funcsel_UART2_CTS 0xe4
#define fmux_gpio_funcsel_UART2_CTS_OFFSET 0
#define fmux_gpio_funcsel_UART2_CTS_MASK 0x7
#define fmux_gpio_funcsel_ADC1 0xe8
#define fmux_gpio_funcsel_ADC1_OFFSET 0
#define fmux_gpio_funcsel_ADC1_MASK 0x7
#define fmux_gpio_funcsel_UART1_RX 0xec
#define fmux_gpio_funcsel_UART1_RX_OFFSET 0
#define fmux_gpio_funcsel_UART1_RX_MASK 0x7
#define fmux_gpio_funcsel_USB_ID 0xf0
#define fmux_gpio_funcsel_USB_ID_OFFSET 0
#define fmux_gpio_funcsel_USB_ID_MASK 0x7
#define fmux_gpio_funcsel_USB_VBUS_DET 0xf4
#define fmux_gpio_funcsel_USB_VBUS_DET_OFFSET 0
#define fmux_gpio_funcsel_USB_VBUS_DET_MASK 0x7
#define fmux_gpio_funcsel_USB_VBUS_EN 0xf8
#define fmux_gpio_funcsel_USB_VBUS_EN_OFFSET 0
#define fmux_gpio_funcsel_USB_VBUS_EN_MASK 0x7
#define fmux_gpio_funcsel_CLK32K 0xfc
#define fmux_gpio_funcsel_CLK32K_OFFSET 0
#define fmux_gpio_funcsel_CLK32K_MASK 0x7
#define fmux_gpio_funcsel_CLK25M 0x100
#define fmux_gpio_funcsel_CLK25M_OFFSET 0
#define fmux_gpio_funcsel_CLK25M_MASK 0x7
#define fmux_gpio_funcsel_XTAL_XIN_XI 0x104
#define fmux_gpio_funcsel_XTAL_XIN_XI_OFFSET 0
#define fmux_gpio_funcsel_XTAL_XIN_XI_MASK 0x7
#define fmux_gpio_funcsel_VO_DATA1 0x108
#define fmux_gpio_funcsel_VO_DATA1_OFFSET 0
#define fmux_gpio_funcsel_VO_DATA1_MASK 0x7
#define fmux_gpio_funcsel_VO_DATA0 0x10c
#define fmux_gpio_funcsel_VO_DATA0_OFFSET 0
#define fmux_gpio_funcsel_VO_DATA0_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXM4 0x110
#define fmux_gpio_funcsel_PAD_MIPI_TXM4_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXM4_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXP4 0x114
#define fmux_gpio_funcsel_PAD_MIPI_TXP4_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXP4_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXM3 0x118
#define fmux_gpio_funcsel_PAD_MIPI_TXM3_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXM3_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXP3 0x11c
#define fmux_gpio_funcsel_PAD_MIPI_TXP3_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXP3_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXM2 0x120
#define fmux_gpio_funcsel_PAD_MIPI_TXM2_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXM2_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXP2 0x124
#define fmux_gpio_funcsel_PAD_MIPI_TXP2_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXP2_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXM1 0x128
#define fmux_gpio_funcsel_PAD_MIPI_TXM1_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXM1_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXP1 0x12c
#define fmux_gpio_funcsel_PAD_MIPI_TXP1_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXP1_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXM0 0x130
#define fmux_gpio_funcsel_PAD_MIPI_TXM0_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXM0_MASK 0x7
#define fmux_gpio_funcsel_PAD_MIPI_TXP0 0x134
#define fmux_gpio_funcsel_PAD_MIPI_TXP0_OFFSET 0
#define fmux_gpio_funcsel_PAD_MIPI_TXP0_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX1_PAD0P 0x138
#define fmux_gpio_funcsel_MIPIRX1_PAD0P_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX1_PAD0P_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX1_PAD0N 0x13c
#define fmux_gpio_funcsel_MIPIRX1_PAD0N_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX1_PAD0N_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX1_PAD1P 0x140
#define fmux_gpio_funcsel_MIPIRX1_PAD1P_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX1_PAD1P_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX1_PAD1N 0x144
#define fmux_gpio_funcsel_MIPIRX1_PAD1N_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX1_PAD1N_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX1_PAD2P 0x148
#define fmux_gpio_funcsel_MIPIRX1_PAD2P_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX1_PAD2P_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX1_PAD2N 0x14c
#define fmux_gpio_funcsel_MIPIRX1_PAD2N_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX1_PAD2N_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX1_PAD3P 0x150
#define fmux_gpio_funcsel_MIPIRX1_PAD3P_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX1_PAD3P_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX1_PAD3N 0x154
#define fmux_gpio_funcsel_MIPIRX1_PAD3N_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX1_PAD3N_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX1_PAD4P 0x158
#define fmux_gpio_funcsel_MIPIRX1_PAD4P_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX1_PAD4P_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX1_PAD4N 0x15c
#define fmux_gpio_funcsel_MIPIRX1_PAD4N_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX1_PAD4N_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX0_PAD4N 0x160
#define fmux_gpio_funcsel_MIPIRX0_PAD4N_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX0_PAD4N_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX0_PAD4P 0x164
#define fmux_gpio_funcsel_MIPIRX0_PAD4P_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX0_PAD4P_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX0_PAD3N 0x168
#define fmux_gpio_funcsel_MIPIRX0_PAD3N_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX0_PAD3N_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX0_PAD3P 0x16c
#define fmux_gpio_funcsel_MIPIRX0_PAD3P_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX0_PAD3P_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX0_PAD2N 0x170
#define fmux_gpio_funcsel_MIPIRX0_PAD2N_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX0_PAD2N_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX0_PAD2P 0x174
#define fmux_gpio_funcsel_MIPIRX0_PAD2P_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX0_PAD2P_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX0_PAD1N 0x178
#define fmux_gpio_funcsel_MIPIRX0_PAD1N_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX0_PAD1N_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX0_PAD1P 0x17c
#define fmux_gpio_funcsel_MIPIRX0_PAD1P_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX0_PAD1P_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX0_PAD0N 0x180
#define fmux_gpio_funcsel_MIPIRX0_PAD0N_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX0_PAD0N_MASK 0x7
#define fmux_gpio_funcsel_MIPIRX0_PAD0P 0x184
#define fmux_gpio_funcsel_MIPIRX0_PAD0P_OFFSET 0
#define fmux_gpio_funcsel_MIPIRX0_PAD0P_MASK 0x7
#define fmux_gpio_funcsel_VI_DATA22 0x188
#define fmux_gpio_funcsel_VI_DATA22_OFFSET 0
#define fmux_gpio_funcsel_VI_DATA22_MASK 0x7
#define fmux_gpio_funcsel_VI_DATA20 0x18c
#define fmux_gpio_funcsel_VI_DATA20_OFFSET 0
#define fmux_gpio_funcsel_VI_DATA20_MASK 0x7
#define fmux_gpio_funcsel_VI_DATA21 0x190
#define fmux_gpio_funcsel_VI_DATA21_OFFSET 0
#define fmux_gpio_funcsel_VI_DATA21_MASK 0x7
#define fmux_gpio_funcsel_CAM_PD0 0x194
#define fmux_gpio_funcsel_CAM_PD0_OFFSET 0
#define fmux_gpio_funcsel_CAM_PD0_MASK 0x7
#define fmux_gpio_funcsel_VI_DATA19 0x198
#define fmux_gpio_funcsel_VI_DATA19_OFFSET 0
#define fmux_gpio_funcsel_VI_DATA19_MASK 0x7
#define fmux_gpio_funcsel_IIC0_SDA 0x19c
#define fmux_gpio_funcsel_IIC0_SDA_OFFSET 0
#define fmux_gpio_funcsel_IIC0_SDA_MASK 0x7
#define fmux_gpio_funcsel_CAM_MCLK0 0x1a0
#define fmux_gpio_funcsel_CAM_MCLK0_OFFSET 0
#define fmux_gpio_funcsel_CAM_MCLK0_MASK 0x7
#define fmux_gpio_funcsel_IIC3_SCL 0x1a4
#define fmux_gpio_funcsel_IIC3_SCL_OFFSET 0
#define fmux_gpio_funcsel_IIC3_SCL_MASK 0x7
#define fmux_gpio_funcsel_VI_DATA24 0x1a8
#define fmux_gpio_funcsel_VI_DATA24_OFFSET 0
#define fmux_gpio_funcsel_VI_DATA24_MASK 0x7
#define fmux_gpio_funcsel_CAM_RST0 0x1ac
#define fmux_gpio_funcsel_CAM_RST0_OFFSET 0
#define fmux_gpio_funcsel_CAM_RST0_MASK 0x7
#define fmux_gpio_funcsel_VI_DATA23 0x1b0
#define fmux_gpio_funcsel_VI_DATA23_OFFSET 0
#define fmux_gpio_funcsel_VI_DATA23_MASK 0x7
#define fmux_gpio_funcsel_IIC3_SDA 0x1b4
#define fmux_gpio_funcsel_IIC3_SDA_OFFSET 0
#define fmux_gpio_funcsel_IIC3_SDA_MASK 0x7
#define fmux_gpio_funcsel_IIC0_SCL 0x1b8
#define fmux_gpio_funcsel_IIC0_SCL_OFFSET 0
#define fmux_gpio_funcsel_IIC0_SCL_MASK 0x7
#endif /* __CV1835_REG_FMUX_GPIO_H__ */

122
u-boot-2021.10/board/cvitek/cv1835/sdhci_reg.h Normal file
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@ -0,0 +1,122 @@
#ifndef _SDHCI_REG_H
#define _SDHCI_REG_H
#include "cv1835_reg.h"
#define REG_TOP_SD_PWRSW_CTRL (0x1F4)
#define REG_SDIO0_PAD_MASK (0xFFFFFFF3)
#define REG_SDIO0_PAD_SHIFT (2)
#define REG_SDIO0_PAD_CLR_MASK (0xC)
#define REG_SDIO0_CD_PAD_REG (PINMUX_BASE + 0xC04)
#define REG_SDIO0_CD_PAD_VALUE (1)
#define REG_SDIO0_CD_PAD_RESET (1)
#define REG_SDIO0_CLK_PAD_REG (PINMUX_BASE + 0xB04)
#define REG_SDIO0_CLK_PAD_VALUE (2)
#define REG_SDIO0_CLK_PAD_RESET (2)
#define REG_SDIO0_CMD_PAD_REG (PINMUX_BASE + 0xB00)
#define REG_SDIO0_CMD_PAD_VALUE (1)
#define REG_SDIO0_CMD_PAD_RESET (2)
#define REG_SDIO0_DAT0_PAD_REG (PINMUX_BASE + 0xB08)
#define REG_SDIO0_DAT0_PAD_VALUE (1)
#define REG_SDIO0_DAT0_PAD_RESET (2)
#define REG_SDIO0_DAT1_PAD_REG (PINMUX_BASE + 0xB0C)
#define REG_SDIO0_DAT1_PAD_VALUE (1)
#define REG_SDIO0_DAT1_PAD_RESET (2)
#define REG_SDIO0_DAT2_PAD_REG (PINMUX_BASE + 0xB10)
#define REG_SDIO0_DAT2_PAD_VALUE (1)
#define REG_SDIO0_DAT2_PAD_RESET (2)
#define REG_SDIO0_DAT3_PAD_REG (PINMUX_BASE + 0xB14)
#define REG_SDIO0_DAT3_PAD_VALUE (1)
#define REG_SDIO0_DAT3_PAD_RESET (2)
#define PAD_SDIO0_CD_REG (PINMUX_BASE + 0x04)
#define PAD_SDIO0_PWR_EN_REG (PINMUX_BASE + 0x14)
#define PAD_SDIO0_CLK_REG (PINMUX_BASE + 0x40)
#define PAD_SDIO0_CMD_REG (PINMUX_BASE + 0x3C)
#define PAD_SDIO0_D0_REG (PINMUX_BASE + 0x44)
#define PAD_SDIO0_D1_REG (PINMUX_BASE + 0x48)
#define PAD_SDIO0_D2_REG (PINMUX_BASE + 0x4C)
#define PAD_SDIO0_D3_REG (PINMUX_BASE + 0x50)
#define REG_SDIO1_PAD_MASK (0xFFFFFFF3)
#define REG_SDIO1_PAD_SHIFT (2)
#define REG_SDIO1_PAD_CLR_MASK (0xC)
#define REG_SDIO1_CLK_PAD_REG (PINMUX_BASE + 0xA14)
#define REG_SDIO1_CLK_PAD_VALUE (2)
#define REG_SDIO1_CMD_PAD_REG (PINMUX_BASE + 0xA10)
#define REG_SDIO1_CMD_PAD_VALUE (1)
#define REG_SDIO1_DAT0_PAD_REG (PINMUX_BASE + 0xA0C)
#define REG_SDIO1_DAT0_PAD_VALUE (1)
#define REG_SDIO1_DAT2_PAD_REG (PINMUX_BASE + 0xA1C)
#define REG_SDIO1_DAT2_PAD_VALUE (1)
#define REG_SDIO1_DAT1_PAD_REG (PINMUX_BASE + 0xA20)
#define REG_SDIO1_DAT1_PAD_VALUE (1)
#define REG_SDIO1_DAT3_PAD_REG (PINMUX_BASE + 0xA24)
#define REG_SDIO1_DAT3_PAD_VALUE (1)
#define REG_EMMC_PAD_CLR_MASK (0xC)
#define REG_EMMC_PAD_SHIFT (2)
#define REG_EMMC_RSTN_PAD_REG (PINMUX_BASE + 0xC24)
#define REG_EMMC_RSTN_PAD_VALUE (1)
#define REG_EMMC_CLK_PAD_REG (PINMUX_BASE + 0xC20)
#define REG_EMMC_CLK_PAD_VALUE (2)
#define REG_EMMC_CMD_PAD_REG (PINMUX_BASE + 0xC28)
#define REG_EMMC_CMD_PAD_VALUE (1)
#define REG_EMMC_DAT0_PAD_REG (PINMUX_BASE + 0xC30)
#define REG_EMMC_DAT0_PAD_VALUE (1)
#define REG_EMMC_DAT1_PAD_REG (PINMUX_BASE + 0xC2C)
#define REG_EMMC_DAT1_PAD_VALUE (1)
#define REG_EMMC_DAT2_PAD_REG (PINMUX_BASE + 0xC34)
#define REG_EMMC_DAT2_PAD_VALUE (1)
#define REG_EMMC_DAT3_PAD_REG (PINMUX_BASE + 0xC38)
#define REG_EMMC_DAT3_PAD_VALUE (1)
#define SDHCI_RX_DELAY_LINE (SDHCI_PHY_R_OFFSET + 0x0C)
#define REG_RX_SRC_SEL_MASK (0xFFCFFFFF) // 0x30c reg_rx_src_sel [21:20]
#define REG_RX_SRC_SEL_CLK_TX_INV (0) // clk_tx_inv
#define REG_RX_SRC_SEL_PAD_CLK (1) // pad_clk
#define REG_RX_SRC_SEL_RES (2) // resvd
#define REG_RX_SRC_SEL_CLK_TX (3) // clk_tx
#define REG_RX_SRC_SEL_SHIFT (20) // 0x30c reg_rx_src_sel [21:20]
#define SDHCI_TX_DELAY_LINE (SDHCI_PHY_R_OFFSET + 0x1C)
#define REG_TX_SRC_SEL_MASK (0xFFFFF3FF) // 0x31c reg_tx_src_sel [11:10]
#define REG_TX_SRC_SEL_CLK_TX_INV (0) // clk_tx_inv
#define REG_TX_SRC_SEL_PAD_CLK (1) // pad_clk
#define REG_TX_SRC_SEL_RES (2) // resvd
#define REG_TX_SRC_SEL_CLK_TX (3) // clk_tx
#define REG_TX_SRC_SEL_SHIFT (10) // 0x31c reg_tx_src_sel [11:10]
#define MMC_MAX_CLOCK (375000000)
#define MMC_MAX_CLOCK_DIV_VALUE (0x40009)
#define CLOCK_BYPASS_SELECT_REGISTER (0x3002030)
#define CVI_SDHCI_VENDOR_OFFSET 0x500
#define CVI_SDHCI_VENDOR_MSHC_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x8)
#define CVI_SDHCI_VENDOR_EMMC_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x2C)
#define CVI_SDHCI_VENDOR_A_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_VENDOR_A_STAT_R (CVI_SDHCI_VENDOR_OFFSET + 0x44)
#define MAX_TUNING_CMD_RETRY_COUNT 50
#define TUNE_MAX_PHCODE 128
#define TAP_WINDOW_THLD 20
#endif

7
u-boot-2021.10/cmd/Kconfig
View File

@ -2389,6 +2389,13 @@ config CMD_UBIFS
help help
UBIFS is a file system for flash devices which works on top of UBI. UBIFS is a file system for flash devices which works on top of UBI.
config CMD_CVI_UPDATE
bool "cvitek update command"
default y
help
uboot will check flag in SRAM and thendecide if it's sd,usb,usb drive or Ethernet upgrade.
User can run cvi_update [usb/sd/eth] for force update without check flag.
config MMC_SPEED_MODE_SET config MMC_SPEED_MODE_SET
bool "set speed mode using mmc command" bool "set speed mode using mmc command"
depends on CMD_MMC depends on CMD_MMC

5
u-boot-2021.10/cmd/Makefile
View File

@ -68,6 +68,9 @@ obj-$(CONFIG_CMD_FAT) += fat.o
obj-$(CONFIG_CMD_FDT) += fdt.o obj-$(CONFIG_CMD_FDT) += fdt.o
obj-$(CONFIG_CMD_SQUASHFS) += sqfs.o obj-$(CONFIG_CMD_SQUASHFS) += sqfs.o
obj-$(CONFIG_CMD_FLASH) += flash.o obj-$(CONFIG_CMD_FLASH) += flash.o
obj-$(CONFIG_CMD_CVI_UPDATE) += cvi_update.o
obj-$(CONFIG_CMD_CVI_UPDATE) += cvi_utask.o
obj-$(CONFIG_NAND_SUPPORT) += cvi_sd_update.o cvi_sd_update_spinand_v3.o
obj-$(CONFIG_CMD_FPGA) += fpga.o obj-$(CONFIG_CMD_FPGA) += fpga.o
obj-$(CONFIG_CMD_FPGAD) += fpgad.o obj-$(CONFIG_CMD_FPGAD) += fpgad.o
obj-$(CONFIG_CMD_FS_GENERIC) += fs.o obj-$(CONFIG_CMD_FS_GENERIC) += fs.o
@ -200,6 +203,8 @@ obj-$(CONFIG_CMD_AVB) += avb.o
# Foundries.IO SCP03 # Foundries.IO SCP03
obj-$(CONFIG_CMD_SCP03) += scp03.o obj-$(CONFIG_CMD_SCP03) += scp03.o
obj-y += efuse.o
obj-$(CONFIG_ARM) += arm/ obj-$(CONFIG_ARM) += arm/
obj-$(CONFIG_RISCV) += riscv/ obj-$(CONFIG_RISCV) += riscv/
obj-$(CONFIG_SANDBOX) += sandbox/ obj-$(CONFIG_SANDBOX) += sandbox/

68
u-boot-2021.10/cmd/cvi_sd_update.c Normal file
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@ -0,0 +1,68 @@
#include <stdlib.h>
#include <common.h>
#include <config.h>
#include <command.h>
#include <cvsnfc.h>
#define BIT_WRITE_FIP_BIN BIT(0)
#define BIT_WRITE_ROM_PATCH BIT(1)
#define BIT_WRITE_BLD BIT(2)
#define COMPARE_STRING_LEN 6
//------------------------------------------------------------------------------
// data type definitions: typedef, struct or class
//------------------------------------------------------------------------------
#define PTR_INC(base, offset) (void *)((uint8_t *)(base) + (offset))
static int do_cvi_sd_update(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
{
char *addr;
uint32_t component = 0;
if (argc != 4) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
addr = (char *)simple_strtol(argv[1], NULL, 16);
if (!addr) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
printf("addr %p\n", addr);
if (!strncmp(argv[3], "fip", COMPARE_STRING_LEN)) {
printf("fip.bin\n");
component |= BIT_WRITE_FIP_BIN;
} else if (!strncmp(argv[3], "patch", COMPARE_STRING_LEN)) {
printf("patch\n");
component |= BIT_WRITE_ROM_PATCH;
} else if (!strncmp(argv[3], "all", COMPARE_STRING_LEN)) {
printf("all\n");
component |= BIT_WRITE_FIP_BIN | BIT_WRITE_ROM_PATCH | BIT_WRITE_BLD;
} else {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (!strncmp(argv[2], "spinand", COMPARE_STRING_LEN)) {
do_cvi_update_spinand(component, addr);
} else {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
return 0;
}
U_BOOT_CMD(cvi_sd_update, 4, 0, do_cvi_sd_update,
"cvi_sd_update - write images to SPI NAND\n",
"cvi_sd_update addr dev_type img_type - Print a report\n"
"addr : data memory address\n"
"dev_type : spinand\n"
"img_type : fip/patch/all\n"
);

981
u-boot-2021.10/cmd/cvi_sd_update_spinand_v3.c Normal file
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@ -0,0 +1,981 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include <stdlib.h>
#include <common.h>
#include <config.h>
#include <command.h>
#include <fs.h>
#include <part.h>
#include <vsprintf.h>
#include <u-boot/md5.h>
#include <image-sparse.h>
#include <div64.h>
#include <linux/math64.h>
#include <linux/log2.h>
#include <u-boot/crc.h>
#include <time.h>
#include <rand.h>
#include <env.h>
#define cvi_assert(expr) do {\
if (!(expr)) {\
printf("%s:%d[%s]\n", __FILE__, __LINE__, __func__);\
while \
(1);\
} \
} while (0)
#include <cvsnfc.h>
//#define CVI_SD_UPDATE_DEBUG
#ifdef CVI_SD_UPDATE_DEBUG
#define DEBUG_WRITE 1
#define DEBUG_READ 1
#define DEBUG_ERASE 1
#define DEBUG_CMD_FLOW 1
#define DEBUG_DUMP_FIP 1
#else
#define DEBUG_WRITE 0
#define DEBUG_READ 0
#define DEBUG_ERASE 0
#define DEBUG_CMD_FLOW 0
#define DEBUG_DUMP_FIP 1
#endif
#define FORCE_ROM_USE_2K_PAGE
#define PLAT_BM_FIP_MAX_SIZE 0xA0000 // 640KB, Fixed, don't change unless you know it
#define PLAT_BM_FIP_MAX_CHECK_SIZE 0xA0000 // 640KB, Fixed, don't change unless you know it
//------------------------------------------------------------------------------
// data type definitions: typedef, struct or class
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// constant definitions:
//------------------------------------------------------------------------------
#define FIP_IMAGE_HEAD "FIPH" /* FIP Image Header 1 */
#define FIP_IMAGE_BODY "FIPB" /* FIP Image body */
#define FIP_MAGIC_NUMBER "CVBL01\n\0"
#define SPI_NAND_VERSION (0x1823a001)
/* system vector related definitions */
#define SPI_NAND_BASE_DATA_BACKUP_COPY (2)
#define MAX_BLOCK_CNT (20)
/* system vector relocated definitions end here */
#define SPI_NAND_FIP_RSVD_BLOCK_COUNT MAX_BLOCK_CNT // Reserved blocks for FIP.
#define BACKUP_FIP_START_POSITION 9
#define BIT(nr) (1UL << (nr))
#define PTR_INC(base, offset) (void *)((uint8_t *)(base) + (offset))
#define GET_PG_IDX_IN_BLK(x, y) ((x) % (y))
#define GET_BLK_IDX(x, y) ((x) / (y))
#define FIP_STOP_RECOVERY 2
#define FIP_CHECKNUM_ERROR 1
#define FIP_HEADER_NO_ISSUE 0
#define FIP_PAGE_ERROR 1
#define FIP_PAGE_NO_ISSUE 0
#define FIP_NO_AVAILABLE_BLOCK 1
struct _spi_nand_info_t {
uint32_t version;
uint32_t id;
uint32_t page_size;
uint32_t spare_size;
uint32_t block_size;
uint32_t pages_per_block;
uint32_t fip_block_cnt;
uint8_t pages_per_block_shift;
uint8_t badblock_pos;
uint8_t dummy_data1[2];
uint32_t flags;
uint8_t ecc_en_feature_offset;
uint8_t ecc_en_mask;
uint8_t ecc_status_offset;
uint8_t ecc_status_mask;
uint8_t ecc_status_shift;
uint8_t ecc_status_uncorr_val;
uint8_t dummy_data2[2];
uint32_t erase_count; // erase count for sys base block
uint8_t sck_l;
uint8_t sck_h;
uint16_t max_freq;
uint32_t sample_param;
uint8_t xtal_switch;
uint8_t dummy_data3[71];
};
#define FIP_BK_TAG_SIZE 4
/* the header should start with FIH1, FIB1+sequence number */
struct block_header_t {
uint8_t tag[FIP_BK_TAG_SIZE];
uint32_t bk_cnt_or_seq; /* for first block, it is block count. Otherwise, it is sequence number */
uint32_t checknum; /* the check number to make sure all fip header and body are consistent */
uint32_t dummy;
};
struct _fip_param1_t {
uint64_t magic1;
uint32_t magic2;
uint32_t param_cksum;
struct _spi_nand_info_t nand_info;
};
struct _fip_info_t {
uint8_t bk_position[SPI_NAND_FIP_RSVD_BLOCK_COUNT / 2];
uint32_t checknum[SPI_NAND_FIP_RSVD_BLOCK_COUNT / 2];
uint8_t total_count;
uint16_t current_bk_mask;
};
struct _spi_nand_info_t *g_spi_nand_info;
struct _fip_param1_t *g_fip_param;
struct _spi_nand_info_t spinand_info;
static char spi_nand_defect_bk_list[(MAX_BLOCK_CNT / 8) + 1];
static char spi_nand_bk_usage_list[(MAX_BLOCK_CNT / 8) + 1];
static uint8_t spi_nand_g_param_init = 0xff;
uint8_t *pg_buf;
uint32_t g_virgin_start;
//int spi_nand_flush_vec(void);
//void spi_nand_dump_vec(void);
static inline u32 DESC_CONV(char *x)
{
return ((((((x[0] << 8) | x[1]) << 8) | x[2]) << 8) | x[3]);
}
static inline u32 CHECK_MASK_BIT(void *_mask, u32 bit)
{
u32 w = bit / 8;
u32 off = bit % 8;
return ((u8 *)_mask)[w] & (1 << off);
}
static inline void SET_MASK_BIT(void *_mask, u32 bit)
{
u32 byte = bit / 8;
u32 offset = bit % 8;
((u8 *)_mask)[byte] |= (1 << offset);
}
static void get_spi_nand_info(void)
{
struct cvsnfc_host *host = cvsnfc_get_host();
spinand_info.version = SPI_NAND_VERSION;
spinand_info.id = host->nand_chip_info->id[0]
| host->nand_chip_info->id[1] << 8
| host->nand_chip_info->id[2] << 16;
spinand_info.page_size = host->nand_chip_info->pagesize;
spinand_info.spare_size = host->nand_chip_info->oobsize;
spinand_info.block_size = host->nand_chip_info->erasesize;
spinand_info.pages_per_block = (host->nand_chip_info->erasesize /
host->nand_chip_info->pagesize);
spinand_info.badblock_pos = host->nand_chip_info->badblock_pos;
spinand_info.fip_block_cnt = SPI_NAND_FIP_RSVD_BLOCK_COUNT;
spinand_info.pages_per_block_shift = ilog2(spinand_info.pages_per_block);
spinand_info.flags = host->nand_chip_info->flags;
if (DEBUG_WRITE) {
printf("NAND_DEBUG: %s NAND id=0x%x, page size=%d, page per block=%d, block_size=%d, fip_block_cnt=%d\n",
__func__,
spinand_info.id,
spinand_info.page_size,
spinand_info.pages_per_block,
spinand_info.block_size,
spinand_info.fip_block_cnt);
}
// TODO: get ecc info form nand_chip_info
spinand_info.ecc_en_feature_offset = host->nand_chip_info->ecc_en_feature_offset;
spinand_info.ecc_en_mask = host->nand_chip_info->ecc_en_mask;
spinand_info.ecc_status_offset = host->nand_chip_info->ecc_status_offset;
spinand_info.ecc_status_mask = host->nand_chip_info->ecc_status_mask;
spinand_info.ecc_status_shift = host->nand_chip_info->ecc_status_shift;
spinand_info.ecc_status_uncorr_val = host->nand_chip_info->ecc_status_uncorr_val;
spinand_info.sck_l = host->nand_chip_info->sck_l;
spinand_info.sck_h = host->nand_chip_info->sck_h;
spinand_info.max_freq = host->nand_chip_info->max_freq;
spinand_info.sample_param = host->nand_chip_info->sample_param;
spinand_info.xtal_switch = host->nand_chip_info->xtal_switch;
if (DEBUG_WRITE) {
printf("NAND_DEBUG: %s, ecc_en_feature_offset = 0x%x, ecc_status_offset = 0x%x\n", __func__,
spinand_info.ecc_en_feature_offset, spinand_info.ecc_status_offset);
printf("NAND_DEBUG: %s, sck_l = 0x%x, sck_h = 0x%x, max_freq = %d, sample_param=0x%x\n", __func__,
spinand_info.sck_l, spinand_info.sck_h, spinand_info.max_freq, spinand_info.sample_param);
printf("NAND_DEBUG: %s, xtal_switch = %d\n", __func__, spinand_info.xtal_switch);
}
}
static void spi_nand_global_param_init(void)
{
struct _spi_nand_info_t *info = &spinand_info;
if (spi_nand_g_param_init == 1) /* global parameters is initialized */
return;
g_fip_param = (struct _fip_param1_t *)malloc(sizeof(struct _fip_param1_t));
memset(g_fip_param, 0, sizeof(struct _fip_param1_t));
g_spi_nand_info = &g_fip_param->nand_info;
get_spi_nand_info();
pg_buf = (uint8_t *)malloc(info->page_size + info->spare_size);
spi_nand_g_param_init = 1;
}
/*
* Erase all block and scan defect block
*/
static int spi_nand_scan_defect(void)
{
int status;
struct _spi_nand_info_t *info = &spinand_info;
struct cvsnfc_host *host = cvsnfc_get_host();
u32 ttl_pg_sz = info->page_size + info->spare_size;
printf("Scan and erase first %d blocks\n", info->fip_block_cnt);
// printf("%s info =%p, page_size %d, block size=%d, spare_size=%d\n", __func__, info,
// info->page_size, info->block_size, info->spare_size);
memset(spi_nand_defect_bk_list, 0, (MAX_BLOCK_CNT / 8) + 1);
memset(spi_nand_bk_usage_list, 0, (MAX_BLOCK_CNT / 8) + 1);
for (u32 blk_id = 0; blk_id < info->fip_block_cnt; blk_id++) {
uint32_t pg = blk_id << info->pages_per_block_shift;
host->addr_value[1] = pg;
cvsnfc_send_cmd_erase(host);
memset(pg_buf, 0xff, ttl_pg_sz);
status = cvsnfc_read_page_raw(host->mtd, host->chip, pg_buf, 0, pg);
if (status) {
printf("read status %d, ", status);
cvi_assert(0);
}
u8 *mark = (u8 *)pg_buf;
/* Should we check spare data at 800H of this page instead of byte 0 */
//printf("NAND_DEBUG: block[%d] spare byte[0] at 0x800 = %x\n", blk_id, *(mark + info->page_size));
if ((*mark != 0xff) || (*(mark + info->page_size) != 0xff)) {
printf("\n\nFound bad block %d, ", blk_id);
//printf("bad ");
//printf(" mark : 0x%x\n\n", *mark);
//bbt_dump_buf("data:", pg_buf, 16);
SET_MASK_BIT(spi_nand_defect_bk_list, blk_id);
}
}
return 0;
}
static int spi_nand_blk_allocator(int fip_idx)
{
struct _spi_nand_info_t *info = &spinand_info;
int blk_idx;
u8 start_blk = 0;
if (fip_idx == 1) {
start_blk = BACKUP_FIP_START_POSITION;
for (blk_idx = start_blk; blk_idx < info->fip_block_cnt; blk_idx++)
if ((CHECK_MASK_BIT(spi_nand_defect_bk_list, blk_idx) == 0) &&
(CHECK_MASK_BIT(spi_nand_bk_usage_list, blk_idx) == 0))
break;
if (blk_idx >= info->fip_block_cnt) {
printf("no available block can be allocated for fip[1]\n");
return -FIP_NO_AVAILABLE_BLOCK;
}
} else {
for (blk_idx = start_blk; blk_idx < BACKUP_FIP_START_POSITION; blk_idx++)
if ((CHECK_MASK_BIT(spi_nand_defect_bk_list, blk_idx) == 0) &&
(CHECK_MASK_BIT(spi_nand_bk_usage_list, blk_idx) == 0))
break;
if (blk_idx >= BACKUP_FIP_START_POSITION) {
printf("no available block can be allocated for fip[0]\n");
return -FIP_NO_AVAILABLE_BLOCK;
}
}
SET_MASK_BIT(spi_nand_bk_usage_list, blk_idx);
return blk_idx;
}
int check_fip_checknum(struct _fip_info_t *fip_info)
{
int i;
if (fip_info->total_count != 0xff) {
for (i = 1; i < fip_info->total_count; i++) {
if (fip_info->checknum[0] == fip_info->checknum[i])
continue; /* checknum is consistent with fip header */
else
return 1; /* checknum is not consistent, it means fip is corrupted */
}
return 0; /* all checknums are consistence */
}
return 1; /* no valid total_count, it means fip is corrupted */
}
int fip_reallocate_and_recovery(struct _fip_info_t *fip, int fip_idx, int bk_idx)
{
struct _spi_nand_info_t *info = &spinand_info;
struct cvsnfc_host *host = cvsnfc_get_host();
int status;
void *temp_buf;
uint8_t bk_shift;
int bk_page_id;
int target_page_id;
int blk_id;
bk_shift = info->pages_per_block_shift;
temp_buf = (uint8_t *)malloc(info->page_size);
/* erase original block first */
host->addr_value[1] = (fip + fip_idx)->bk_position[bk_idx] << bk_shift;
cvsnfc_send_cmd_erase(host);
retry:
blk_id = spi_nand_blk_allocator(fip_idx);
if (blk_id < 0)
return -1;
(fip + fip_idx)->bk_position[bk_idx] = blk_id;
for (int pg_idx = 0; pg_idx < info->pages_per_block; pg_idx++) {
if (fip_idx == 0) {
bk_page_id = ((fip + 1)->bk_position[bk_idx] << info->pages_per_block_shift) + pg_idx;
target_page_id = (fip->bk_position[bk_idx] << info->pages_per_block_shift) + pg_idx;
} else {
bk_page_id = (fip->bk_position[bk_idx] << info->pages_per_block_shift) + pg_idx;
target_page_id = ((fip + 1)->bk_position[bk_idx] << info->pages_per_block_shift) + pg_idx;
}
status = cvsnfc_read_page(host->mtd, host->chip, (void *)pg_buf,
info->page_size, bk_page_id);
if (status < 0) {
printf("%s, ECC UNCORR detect on backup bk %d page %d, stop recovery\n", __func__,
(fip + fip_idx)->bk_position[bk_idx], pg_idx);
goto retry;
}
cvsnfc_write_page(host->mtd, host->chip, (void *)pg_buf, 0,
target_page_id);
status = cvsnfc_read_page(host->mtd, host->chip, (void *)temp_buf, info->page_size,
target_page_id);
if (status < 0) {
printf("%s, ECC UNCORR detect on bk %d page %d after recovery\n", __func__,
(fip + fip_idx)->bk_position[bk_idx], pg_idx);
}
if (memcmp(temp_buf, pg_buf, info->page_size)) {
printf("%s, fip 0 read back compare error at bk %d!\n", __func__,
(fip + fip_idx)->bk_position[bk_idx]);
}
}
free(temp_buf);
return 0;
}
int fip_block_recover(struct _fip_info_t *fip, int bk_idx, int backup_fip, int target_fip)
{
struct cvsnfc_host *host = cvsnfc_get_host();
struct _spi_nand_info_t *info = &spinand_info;
int status;
void *temp_buf;
int backup_page_id;
int target_page_id;
temp_buf = (uint8_t *)malloc(info->page_size);
for (int pg_idx = 0; pg_idx < info->pages_per_block; pg_idx++) {
backup_page_id = ((fip + backup_fip)->bk_position[bk_idx] << info->pages_per_block_shift) + pg_idx;
target_page_id = ((fip + target_fip)->bk_position[bk_idx] << info->pages_per_block_shift) + pg_idx;
status = cvsnfc_read_page(host->mtd, host->chip, (void *)pg_buf,
info->page_size, backup_page_id);
if (status < 0) {
printf("%s, ECC UNCORR detect on backup bk %d page %d, stop recovery\n",
__func__, (fip + backup_fip)->bk_position[bk_idx], pg_idx);
goto recover_fail;
}
cvsnfc_write_page(host->mtd, host->chip, (void *)pg_buf, 0,
target_page_id);
status = cvsnfc_read_page(host->mtd, host->chip, (void *)temp_buf, info->page_size,
target_page_id);
if (status < 0) {
printf("%s, ECC UNCORR detect on bk %d page %d after recovery\n",
__func__, (fip + target_fip)->bk_position[bk_idx], pg_idx);
if (fip_reallocate_and_recovery(fip, target_fip, bk_idx) < 0)
goto recover_fail;
}
if (memcmp(temp_buf, pg_buf, info->page_size)) {
printf("%s, fip 0 read back compare error at bk %d!\n", __func__,
fip->bk_position[bk_idx]);
if (fip_reallocate_and_recovery(fip, target_fip, bk_idx) < 0)
goto recover_fail;
}
}
free(temp_buf);
return FIP_PAGE_NO_ISSUE;
recover_fail:
free(temp_buf);
return FIP_STOP_RECOVERY;
}
int fip_check_checknum_and_recovery(struct _fip_info_t *fip)
{
struct cvsnfc_host *host = cvsnfc_get_host();
struct _spi_nand_info_t *info = &spinand_info;
int status;
int bk_id;
if (check_fip_checknum(fip) && !check_fip_checknum(fip + 1)) {
/* checknums within fip_info[0] are not consistnece, but fip_info[1] is OK. recovery fip0 from fip1 */
if (fip->current_bk_mask != (fip + 1)->current_bk_mask) {
for (int i = 0; i < (fip + 1)->total_count; i++) {
if (!((fip->current_bk_mask >> i) & 0x1)) {
printf("fip[0] bk idx %d is corrupted, recover from fip[1]\n", i);
bk_id = spi_nand_blk_allocator(0);
fip->bk_position[i] = bk_id;
host->addr_value[1] = fip->bk_position[i] << info->pages_per_block_shift;
cvsnfc_send_cmd_erase(host);
status = fip_block_recover(fip, i, 1, 0);
if (status)
return status;
}
}
fip->total_count = (fip + 1)->total_count;
fip->current_bk_mask = (fip + 1)->current_bk_mask;
} else {
printf("Checknums of fip[0] are not consistence\n");
for (int i = 0; i < fip->total_count; i++) {
/* Erase original blocks first */
host->addr_value[1] = fip->bk_position[i] << info->pages_per_block_shift;
cvsnfc_send_cmd_erase(host);
/* Read pages from backup fip then write to target pages */
status = fip_block_recover(fip, i, 1, 0);
if (status)
return status;
}
}
} else if (!check_fip_checknum(fip) && check_fip_checknum(fip + 1)) {
/* checknums within fip_info[1] are not consistnece, but fip_info[0] is OK. recovery fip1 from fip0 */
if (fip->current_bk_mask != (fip + 1)->current_bk_mask) {
for (int i = 0; i < fip->total_count; i++) {
if (!(((fip + 1)->current_bk_mask >> i) & 0x1)) {
printf("fip[1] bk idx %d is corrupted, recover from fip[0]\n", i);
bk_id = spi_nand_blk_allocator(1);
(fip + 1)->bk_position[i] = bk_id;
host->addr_value[1] = (fip + 1)->bk_position[i] << info->pages_per_block_shift;
cvsnfc_send_cmd_erase(host);
status = fip_block_recover(fip, i, 0, 1);
if (status)
return status;
}
}
(fip + 1)->total_count = fip->total_count;
(fip + 1)->current_bk_mask = fip->current_bk_mask;
} else {
printf("Checknums of fip[1] are not consistence\n");
for (int i = 0; i < (fip + 1)->total_count; i++) {
/* Erase original blocks first */
host->addr_value[1] = (fip + 1)->bk_position[i] << info->pages_per_block_shift;
cvsnfc_send_cmd_erase(host);
/* Read pages from backup fip then write to target pages */
status = fip_block_recover(fip, i, 0, 1);
if (status)
return status;
}
}
} else if (check_fip_checknum(fip) && check_fip_checknum(fip + 1)) {
printf("Both fip[0] and fip[1] are corrupted, please do re-download again!!\n");
return FIP_STOP_RECOVERY;
} else if (fip->checknum[0] != (fip + 1)->checknum[0]) {
/* checknums of fip0 and fip1 are not the same, it means fip download is not complete*/
/* recovery fip0 from fip1 */
printf("Checknum of fip[0] is not the same with fip[1]\n");
for (int i = 0; i < (fip + 1)->total_count; i++) {
/* Erase original blocks first */
host->addr_value[1] = fip->bk_position[i] << info->pages_per_block_shift;
cvsnfc_send_cmd_erase(host);
/* Read pages from backup fip then write to target pages */
status = fip_block_recover(fip, i, 1, 0);
if (status)
return status;
}
fip->total_count = (fip + 1)->total_count;
fip->current_bk_mask = (fip + 1)->current_bk_mask;
} else {
printf("All Header check PASS\n");
return FIP_HEADER_NO_ISSUE;
}
return FIP_CHECKNUM_ERROR;
}
int fip_check_page_and_recovery(struct _fip_info_t *fip)
{
struct _spi_nand_info_t *info = &spinand_info;
struct cvsnfc_host *host = cvsnfc_get_host();
int status;
uint8_t erase_and_recover = 0;
uint8_t fip_idx = 0;
uint8_t bk_shift;
bk_shift = info->pages_per_block_shift;
for (fip_idx = 0; fip_idx < SPI_NAND_BASE_DATA_BACKUP_COPY; fip_idx++) {
for (int i = 0; i < fip->total_count; i++) {
for (int pg_idx = 0; pg_idx < info->pages_per_block; pg_idx++) {
int page_id;
page_id = ((fip + fip_idx)->bk_position[i] << bk_shift) + pg_idx;
status = cvsnfc_read_page(host->mtd, host->chip, (void *)pg_buf,
info->page_size, page_id);
if (status < 0) {
printf("ECC UNCORR detect on bk %d page %d\n",
(fip + fip_idx)->bk_position[i], pg_idx);
erase_and_recover = 1;
break; /* need to erase a whole block and then re-write again */
}
}
if (erase_and_recover == 1) {
printf("Recover bk %d due to page error\n", (fip + fip_idx)->bk_position[i]);
host->addr_value[1] = (fip + fip_idx)->bk_position[i] << bk_shift;
cvsnfc_send_cmd_erase(host);
if (fip_idx == 0)
status = fip_block_recover(fip, i, 1, 0);
else
status = fip_block_recover(fip, i, 0, 1);
if (status)
return status;
erase_and_recover = 0;
}
}
}
printf("All Page check PASS\n");
return 0;
}
/*
* This function is entry point of normal bootup of u-boot
* check each block status and recovery it if ECC ERROR occur
*/
int check_and_update_fip_bin(void)
{
struct _spi_nand_info_t *info;
struct cvsnfc_host *host = cvsnfc_get_host();
u32 blk_id = 0;
struct _fip_info_t fip_info[SPI_NAND_BASE_DATA_BACKUP_COPY];
struct block_header_t *bk_header;
u32 pg_sz, bk_sz;
int status;
u8 fip_header_count = 0;
u32 boot_src;
spi_nand_global_param_init();
info = &spinand_info;
pg_sz = info->page_size;
bk_sz = info->block_size;
memset(pg_buf, 0, sizeof(pg_sz));
memset(&fip_info, 0xff, sizeof(struct _fip_info_t) * SPI_NAND_BASE_DATA_BACKUP_COPY);
for (int i = 0; i < SPI_NAND_BASE_DATA_BACKUP_COPY; i++) {
fip_info[i].current_bk_mask = 0x0;
}
memset(spi_nand_defect_bk_list, 0, (MAX_BLOCK_CNT / 8) + 1);
memset(spi_nand_bk_usage_list, 0, (MAX_BLOCK_CNT / 8) + 1);
for (blk_id = 0; blk_id < SPI_NAND_FIP_RSVD_BLOCK_COUNT; blk_id++) {
status = cvsnfc_read_page(host->mtd, host->chip, (void *)pg_buf, pg_sz,
(blk_id << info->pages_per_block_shift) + 0);
/* Read first page of each block */
if (status < 0) {
printf("%s, find ECC UNCORR on bk %d\n", __func__, blk_id);
SET_MASK_BIT(spi_nand_defect_bk_list, blk_id);
continue;
}
bk_header = (struct block_header_t *)pg_buf;
if (!memcmp(bk_header->tag, FIP_IMAGE_HEAD, FIP_BK_TAG_SIZE)) {
fip_header_count++;
if (fip_header_count == 1 && blk_id >= BACKUP_FIP_START_POSITION)
printf("WARNING!! First fip header position exceed backup start position\n");
if (fip_header_count == 1)
spi_nand_adjust_max_freq(host, (u32 *)bk_header->tag, &bk_header->checknum);
if (blk_id < BACKUP_FIP_START_POSITION) {
if (fip_info[0].bk_position[0] == 0xff) {
fip_info[0].bk_position[0] = blk_id;
fip_info[0].checknum[0] = bk_header->checknum;
fip_info[0].total_count = bk_header->bk_cnt_or_seq;
fip_info[0].current_bk_mask |= 0x1 << 0;
SET_MASK_BIT(spi_nand_bk_usage_list, blk_id);
continue;
} else
printf("fip info[0] header is not initialized before\n");
} else {
if (fip_info[1].bk_position[0] == 0xff) {
fip_info[1].bk_position[0] = blk_id;
fip_info[1].checknum[0] = bk_header->checknum;
fip_info[1].total_count = bk_header->bk_cnt_or_seq;
fip_info[1].current_bk_mask |= 0x1 << 0;
SET_MASK_BIT(spi_nand_bk_usage_list, blk_id);
continue;
} else
printf("fip info[1] header is not initialized before\n");
}
if (fip_header_count > SPI_NAND_BASE_DATA_BACKUP_COPY)
printf("%s, WARNING!! find unexpected fip_header at bk %d\n", __func__, blk_id);
} else if (!memcmp(bk_header->tag, FIP_IMAGE_BODY, FIP_BK_TAG_SIZE)) {
if (blk_id < BACKUP_FIP_START_POSITION) {
if (fip_info[0].bk_position[bk_header->bk_cnt_or_seq] == 0xff) {
fip_info[0].bk_position[bk_header->bk_cnt_or_seq] = blk_id;
fip_info[0].checknum[bk_header->bk_cnt_or_seq] = bk_header->checknum;
fip_info[0].current_bk_mask |= 0x1 << bk_header->bk_cnt_or_seq;
SET_MASK_BIT(spi_nand_bk_usage_list, blk_id);
continue;
} else
printf("fip info[0] body %d is not initialized before\n",
bk_header->bk_cnt_or_seq);
} else {
if (fip_info[1].bk_position[bk_header->bk_cnt_or_seq] == 0xff) {
fip_info[1].bk_position[bk_header->bk_cnt_or_seq] = blk_id;
fip_info[1].checknum[bk_header->bk_cnt_or_seq] = bk_header->checknum;
fip_info[1].current_bk_mask |= 0x1 << bk_header->bk_cnt_or_seq;
SET_MASK_BIT(spi_nand_bk_usage_list, blk_id);
continue;
} else
printf("fip info[1] body %d is not initialized before\n",
bk_header->bk_cnt_or_seq);
}
}
}
if (DEBUG_DUMP_FIP) {
for (int i = 0; i < SPI_NAND_BASE_DATA_BACKUP_COPY; i++) {
printf("fip_info[%d] total count=%d\n", i, fip_info[i].total_count);
for (int j = 0; j < (SPI_NAND_FIP_RSVD_BLOCK_COUNT / 2); j++)
printf("fip_info[%d].bk_position[%d]= 0x%x, fip_info[%d].checknum[%d] = 0x%x\n",
i, j, fip_info[i].bk_position[j], i, j, fip_info[i].checknum[j]);
printf("fip_info[%d].current mask=0x%x\n", i, fip_info[i].current_bk_mask);
}
printf("defect list = %02x%02x%02x\n", spi_nand_defect_bk_list[2],
spi_nand_defect_bk_list[1], spi_nand_defect_bk_list[0]);
printf("usage list = %02x%02x%02x\n", spi_nand_bk_usage_list[2],
spi_nand_bk_usage_list[1], spi_nand_bk_usage_list[0]);
}
boot_src = readl((unsigned int *)BOOT_SOURCE_FLAG_ADDR);
if (boot_src == MAGIC_NUM_SD_DL || boot_src == MAGIC_NUM_USB_DL)
return 0; /* No need to check and update spinand */
if (fip_header_count <= SPI_NAND_BASE_DATA_BACKUP_COPY) {
if (!fip_check_checknum_and_recovery(fip_info)) {
/* check page ecc and do revoery if necessary */
fip_check_page_and_recovery(fip_info);
}
// } else if (fip_header_count == 1) {
// printf("Only detect 1 fip header\n");
} else if (fip_header_count > SPI_NAND_BASE_DATA_BACKUP_COPY) {
printf("WARNING!! find unexpected fip_header\n");
} else {
printf("WARNING!! cannot find fip_header\n");
}
return 0;
}
static uint32_t spi_nand_crc16_ccitt_with_tag(unsigned char *buf, int len)
{
uint32_t crc = 0;
crc = crc16_ccitt(0, buf, len);
crc |= 0xCAFE0000;
return crc;
}
static void spi_nand_check_size_error(u32 target_len, u32 curr_offset, u32 pg_size)
{
if ((target_len - curr_offset) >= pg_size)
printf("## WARNING 1 ## data size %d to be wrote is wrong!!\n", (target_len - curr_offset));
}
static int spi_nand_flush_fip_bin(void *buf)
{
int status = 0;
void *buffer = (void *)buf;
void *src_buf_addr = 0;
struct cvsnfc_host *host = cvsnfc_get_host();
struct _spi_nand_info_t *info = &spinand_info;
u32 pg_sz, pg_per_blk, bk_sz;
u32 total_len, ttl_block_cnt_to_write, ttl_pg_cnt_to_write;
struct block_header_t bk_header;
u32 bk_overhead; /* used to calculate total block header size in page 0 of each block */
u32 blk_idx = 0;
u32 blk_id = 0;
u32 src_len;
uint8_t *temp_buf;
unsigned int checknum;
srand(get_timer(0));
checknum = rand();
printf("Generated checknum=0x%x\n", checknum);
pg_sz = info->page_size;
bk_sz = info->block_size;
src_len = env_get_ulong("filesize", 16, 0);
printf("fip size=%d bytes\n", src_len);
ttl_block_cnt_to_write = src_len / bk_sz;
if ((src_len % bk_sz) != 0)
ttl_block_cnt_to_write += 1;
bk_overhead = sizeof(struct block_header_t);
memset(&bk_header, 0, sizeof(struct block_header_t));
total_len = (src_len + (ttl_block_cnt_to_write * bk_overhead));
ttl_pg_cnt_to_write = total_len / pg_sz;
if (total_len % pg_sz != 0)
ttl_pg_cnt_to_write += 1; /* add 1 page to write remaining data */
ttl_block_cnt_to_write = total_len / bk_sz; /* re-calculate new block count */
if (total_len % bk_sz != 0)
ttl_block_cnt_to_write += 1;
if (DEBUG_WRITE)
printf("Write totol_len=%d, bk_overhead=%d, ttl_page_cnt_to_write=%d, ttl_block_cnt_to_write=%d\n",
total_len, bk_overhead, ttl_pg_cnt_to_write, ttl_block_cnt_to_write);
pg_per_blk = info->pages_per_block;
temp_buf = (uint8_t *)malloc(info->page_size);
for (u32 i = 0; i < SPI_NAND_BASE_DATA_BACKUP_COPY; i++) {
u32 offset_in_buf = 0;
uint8_t wrote_bk_cnt = 0;
printf("write %d copy of fip\n", i + 1);
for (u32 pg_idx_in_buf = 0; pg_idx_in_buf < ttl_pg_cnt_to_write; pg_idx_in_buf++) {
u32 pg_idx_in_blk;
uint8_t block_damage = 0;
pg_idx_in_blk = GET_PG_IDX_IN_BLK(pg_idx_in_buf, pg_per_blk);
blk_idx = GET_BLK_IDX(pg_idx_in_buf, pg_per_blk);
src_buf_addr = PTR_INC(buffer, offset_in_buf);
if (pg_idx_in_blk == 0) {
if (wrote_bk_cnt == 0) { /* Fill FIP image first block header */
struct _fip_param1_t *temp_fip_param;
uint32_t crc = 0;
int param_crc_size;
memcpy(bk_header.tag, FIP_IMAGE_HEAD, 4);
bk_header.bk_cnt_or_seq = (uint32_t)ttl_block_cnt_to_write;
bk_header.checknum = checknum;
memcpy(temp_buf, &bk_header, bk_overhead);
temp_fip_param = src_buf_addr;
memcpy(&temp_fip_param->nand_info, info, sizeof(struct _spi_nand_info_t));
param_crc_size = 0x800 - offsetof(struct _fip_param1_t, nand_info);
crc = spi_nand_crc16_ccitt_with_tag((unsigned char *)&temp_fip_param->nand_info
, param_crc_size);
//printf("%s, get crc=0x%08x, param_crc_size=%d\n", __func__,
// crc, param_crc_size);
temp_fip_param->param_cksum = crc;
memcpy((temp_buf + bk_overhead), src_buf_addr, (pg_sz - bk_overhead));
} else { /* Fill remaining FIP image body */
memcpy(bk_header.tag, FIP_IMAGE_BODY, 4);
bk_header.bk_cnt_or_seq = (uint32_t)wrote_bk_cnt;
bk_header.checknum = checknum;
memcpy(temp_buf, &bk_header, bk_overhead);
if (pg_idx_in_buf == (ttl_pg_cnt_to_write - 1)) { /* last page */
spi_nand_check_size_error(src_len, offset_in_buf, pg_sz);
memcpy((temp_buf + bk_overhead), src_buf_addr,
(src_len - offset_in_buf));
} else
memcpy((temp_buf + bk_overhead), src_buf_addr, (pg_sz - bk_overhead));
}
wrote_bk_cnt++;
offset_in_buf = offset_in_buf + (pg_sz - bk_overhead); /* Insert fip header in page 0 */
} else {
if (pg_idx_in_buf == (ttl_pg_cnt_to_write - 1)) { /* last page */
spi_nand_check_size_error(src_len, offset_in_buf, pg_sz);
memcpy(temp_buf, src_buf_addr, (src_len - offset_in_buf));
} else
memcpy(temp_buf, src_buf_addr, pg_sz);
offset_in_buf = offset_in_buf + pg_sz;
}
if (DEBUG_WRITE)
printf("flush fip.bin with next offset = 0x%x\n",
offset_in_buf);
retry:
if (pg_idx_in_blk == 0 || block_damage == 1) {
/* pg_idx_in_blk == 0 means need a new block */
/* damage == 1 means need to find next block*/
blk_id = spi_nand_blk_allocator(i);
if (DEBUG_WRITE)
printf("NAND_DEBUG: %s, allocate blk_id=%d for page %d (%x)\n",
__func__, blk_id, pg_idx_in_buf, pg_idx_in_buf);
if (blk_id == -1) {
cvi_assert(0);
return -1;
}
block_damage = 0;
}
/* should we supplyment remain data of last page if remaining data is less then 1 page ?*/
cvsnfc_write_page(host->mtd, host->chip, (void *)temp_buf, 0,
(blk_id << info->pages_per_block_shift) + pg_idx_in_blk);
/* read page again to check data consistent */
memset(pg_buf, 0, sizeof(pg_sz));
status = cvsnfc_read_page(host->mtd, host->chip, (void *)pg_buf, pg_sz,
(blk_id << info->pages_per_block_shift) + pg_idx_in_blk);
if (status < 0) {
printf("##WARNING## %s update failed at block %d page %d, please check...\n",
__func__, blk_id, pg_idx_in_blk);
//cvi_assert(0);
block_damage = 1;
host->addr_value[1] = blk_id << info->pages_per_block_shift;
cvsnfc_send_cmd_erase(host);
SET_MASK_BIT(spi_nand_defect_bk_list, blk_id);
goto retry;
} else if (status > 0) {
printf("NAND_DEBUG: Read ecc corr page idx %d, blk_id %d\n", pg_idx_in_blk, blk_id);
}
if (memcmp(temp_buf, pg_buf, pg_sz)) {
printf("fip read back compare error!\n");
bbt_dump_buf((void *)"temp_buf", temp_buf, pg_sz >> 4);
bbt_dump_buf((void *)"pg_buf", pg_buf, pg_sz >> 4);
cvi_assert(0);
}
}
}
free(temp_buf);
return 0;
}
int spi_nand_fip_download(void *buf)
{
int status;
/* always erase fip partition first and then download re-assemble fip */
status = spi_nand_scan_defect();
if (status) {
printf("scan factory error\n");
return -1;
}
status = spi_nand_flush_fip_bin(buf);
if (status)
printf("flush fip error\n");
return 0;
}
/*
* This function is entry point of u-boot download process
*/
int do_cvi_update_spinand(uint32_t component, void *addr)
{
printf("%s with version 0x%x\n", __func__, SPI_NAND_VERSION);
if (DEBUG_WRITE)
bbt_dump_buf("source fip", addr, 0x40);
spi_nand_fip_download(addr);
return 0;
}

319
u-boot-2021.10/cmd/cvi_update.c Normal file
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#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <imgs.h>
#include <ubifs_uboot.h>
#ifdef CONFIG_NAND_SUPPORT
#include <nand.h>
#endif
#include "cvi_update.h"
#define COMPARE_STRING_LEN 3
#define SD_UPDATE_MAGIC 0x4D474E32
#define ETH_UPDATE_MAGIC 0x4D474E35
#define USB_DRIVE_UPGRADE_MAGIC 0x55425355
#define FIP_UPDATE_MAGIC 0x55464950
#define UPDATE_DONE_MAGIC 0x50524F47
#define OTA_MAGIC 0x5245434F
//#define ALWAYS_USB_DRVIVE_UPGRATE
#define HEADER_SIZE 64
#define SECTOR_SIZE 0x200
#define HEADER_MAGIC "CIMG"
#define MAX_LOADSIZE (16 * 1024 * 1024)
#ifdef CONFIG_CMD_SAVEENV
#define SET_DL_COMPLETE() \
do { \
env_set("dl_flag", "prog"); \
run_command("saveenv", 0); \
} while (0)
#else
#define SET_DL_COMPLETE() writel(0x50524F47, (unsigned int *)UPGRADE_SRAM_ADDR)
#endif /* CONFIG_CMD_SAVEENV */
#ifdef CONFIG_NAND_SUPPORT
static uint32_t lastend;
#endif
uint32_t update_magic;
enum chunk_type_e { dont_care = 0, check_crc };
enum storage_type_e { sd_dl = 0, usb_dl };
static uint32_t bcd2hex4(uint32_t bcd)
{
return ((bcd) & 0x0f) + (((bcd) >> 4) & 0xf0) + (((bcd) >> 8) & 0xf00) + (((bcd) >> 12) & 0xf000);
}
static int _storage_update(enum storage_type_e type);
int _prgImage(char *file, uint32_t chunk_header_size, char *file_name)
{
uint32_t size = *(uint32_t *)((uintptr_t)file + 4);
uint32_t offset = *(uint32_t *)((uintptr_t)file + 8);
#if (defined CONFIG_SPI_FLASH)/* || (defined CONFIG_NAND_SUPPORT)*/
uint32_t part_size = *(uint32_t *)((uintptr_t)file + 12);
#endif
//uint32_t header_crc = *(uint32_t *)((uintptr_t)file + 16);
char cmd[255] = { '\0' };
int ret = 0;
//if (chunk_type == check_crc) {
// uint32_t crc = crc32(
// 0, (unsigned char *)file + chunk_header_size, size);
// if (crc != header_crc) {
// printf("Crc check failed header(0x%08x) img(0x%08x), skip it\n",
// header_crc, crc);
// return 0;
// } else {
// /* Invalidate crc to avoid program garbage */
// *(uint32_t *)((uintptr_t)file + 12) = 0;
// }
//}
#ifdef CONFIG_NAND_SUPPORT
int dev = nand_curr_device;
struct mtd_info *mtd = nand_info[dev];
uint32_t goodblocks = 0, blocks = 0;
// Calculate real offset when programming chunk.
if (offset < lastend)
offset = lastend;
else
lastend = offset;
blocks = (size & (mtd->erasesize - 1)) ? ALIGN(size, mtd->erasesize) : size;
blocks /= mtd->erasesize;
for (; goodblocks < blocks; lastend += mtd->erasesize) {
if (!nand_block_isbad(mtd, lastend))
goodblocks++;
}
//pr_debug("offset:0x%x lastoffset:0x%x, end:0x%x\n", offset, lastend, part_size + offset);
snprintf(cmd, 255, "nand write %p 0x%x 0x%x",
(void *)file + chunk_header_size, offset, size);
#elif defined(CONFIG_SPI_FLASH)
if (update_magic == SD_UPDATE_MAGIC && (!strcmp(file_name, "fip.bin") ||
!strcmp(file_name, "boot.spinor"))) {
snprintf(cmd, 255, "sf update %p 0x%x 0x%x",
(void *)file + chunk_header_size, offset, size);
} else {
snprintf(cmd, 255, "sf erase %#x %#x;", offset, part_size);
pr_debug("%s\n", cmd);
run_command(cmd, 0);
snprintf(cmd, 255, "sf write %p 0x%x 0x%x",
(void *)file + chunk_header_size, offset, size);
}
#else
if (size & (SECTOR_SIZE - 1))
size = ALIGN(size, SECTOR_SIZE);
size = size / SECTOR_SIZE;
offset = offset / SECTOR_SIZE;
snprintf(cmd, 255, "mmc write %p 0x%x 0x%x",
(void *)file + chunk_header_size, offset, size);
#endif
pr_debug("%s\n", cmd);
ret = run_command(cmd, 0);
if (ret)
return 0;
return size;
}
static int _checkHeader(char *file, char strStorage[10])
{
char *magic = (void *)HEADER_ADDR;
uint32_t version = *(uint32_t *)((uintptr_t)HEADER_ADDR + 4);
uint32_t chunk_sz = *(uint32_t *)((uintptr_t)HEADER_ADDR + 8);
uint32_t total_chunk = *(uint32_t *)((uintptr_t)HEADER_ADDR + 12);
uint32_t file_sz = *(uint32_t *)((uintptr_t)HEADER_ADDR + 16);
#ifdef CONFIG_NAND_SUPPORT
char *extra = (void *)((uintptr_t)HEADER_ADDR + 20);
static char prevExtra[EXTRA_FLAG_SIZE + 1] = { '\0' };
#endif
int ret = strncmp(magic, HEADER_MAGIC, 4);
if (ret) {
printf("File:%s Magic number is wrong, skip it\n", file);
return ret;
}
printf("Header Version:%d\n", version);
char cmd[255] = { '\0' };
uint32_t pos = HEADER_SIZE;
#ifdef CONFIG_NAND_SUPPORT
// Erase partition first
if (strncmp(extra, prevExtra, EXTRA_FLAG_SIZE)) {
strncpy(prevExtra, extra, EXTRA_FLAG_SIZE);
snprintf(cmd, 255, "nand erase.part -y %s", prevExtra);
pr_debug("%s\n", cmd);
run_command(cmd, 0);
}
#endif
for (int i = 0; i < total_chunk; i++) {
uint32_t load_size = file_sz > (MAX_LOADSIZE + chunk_sz) ?
MAX_LOADSIZE + chunk_sz :
file_sz;
snprintf(cmd, 255, "fatload %s %p %s 0x%x 0x%x;", strStorage,
(void *)UPDATE_ADDR, file, load_size, pos);
pr_debug("%s\n", cmd);
ret = run_command(cmd, 0);
if (ret)
return ret;
ret = _prgImage((void *)UPDATE_ADDR, chunk_sz, file);
if (ret == 0) {
printf("program file:%s failed\n", file);
break;
}
pos += load_size;
file_sz -= load_size;
}
return 0;
}
static int _storage_update(enum storage_type_e type)
{
int ret = 0;
char cmd[255] = { '\0' };
char strStorage[10] = { '\0' };
if (type == sd_dl) {
printf("Start SD downloading...\n");
// Consider SD card with MBR as default
#if defined(CONFIG_NAND_SUPPORT) || defined(CONFIG_SPI_FLASH)
strlcpy(strStorage, "mmc 0:1", 9);
#elif defined(CONFIG_EMMC_SUPPORT)
strlcpy(strStorage, "mmc 1:1", 9);
#endif
snprintf(cmd, 255, "fatload %s %p fip.bin;", strStorage,
(void *)HEADER_ADDR);
ret = run_command(cmd, 0);
if (ret) {
// Consider SD card without MBR
printf("** Trying use partition 0 (without MBR) **\n");
#if defined(CONFIG_NAND_SUPPORT) || defined(CONFIG_SPI_FLASH)
strlcpy(strStorage, "mmc 0:0", 9);
#elif defined(CONFIG_EMMC_SUPPORT)
strlcpy(strStorage, "mmc 1:0", 9);
#endif
snprintf(cmd, 255, "fatload %s %p fip.bin;", strStorage,
(void *)HEADER_ADDR);
ret = run_command(cmd, 0);
if (ret)
return ret;
}
#if defined(CONFIG_NAND_SUPPORT)
snprintf(cmd, 255, "cvi_sd_update %p spinand fip",
(void *)HEADER_ADDR);
ret = run_command(cmd, 0);
#elif defined(CONFIG_SPI_FLASH)
run_command("sf probe", 0);
snprintf(cmd, 255,
"sf update %p ${fip_PART_OFFSET} ${filesize};",
(void *)HEADER_ADDR);
ret = run_command(cmd, 0);
#elif defined(CONFIG_EMMC_SUPPORT)
// Switch to boot partition
run_command("mmc dev 0 1", 0);
snprintf(cmd, 255, "mmc write %p 0 0x800;",
(void *)HEADER_ADDR);
run_command(cmd, 0);
snprintf(cmd, 255, "mmc write %p 0x800 0x800;;",
(void *)HEADER_ADDR);
run_command(cmd, 0);
printf("Program fip.bin done\n");
// Switch to user partition
run_command("mmc dev 0 0", 0);
#endif
}
for (int i = 1; i < ARRAY_SIZE(imgs); i++) {
snprintf(cmd, 255, "fatload %s %p %s 0x%x 0;", strStorage,
(void *)HEADER_ADDR, imgs[i], HEADER_SIZE);
pr_debug("%s\n", cmd);
ret = run_command(cmd, 0);
if (ret) {
printf("load %s failed, skip it!\n", imgs[i]);
continue;
}
if (_checkHeader(imgs[i], strStorage))
continue;
}
if (ret == 0)
SET_DL_COMPLETE();
return 0;
}
static int _usb_update(uint32_t usb_pid)
{
int ret = 0;
char cmd[255] = { '\0' };
char utask_cmd[255] = { '\0' };
printf("Start USB downloading...\n");
// Clean download flags
writel(0x0, (unsigned int *)BOOT_SOURCE_FLAG_ADDR); //mw.l 0xe00fc00 0x0;
// Always download Fip first
snprintf(utask_cmd, 255, "cvi_utask vid 0x3346 pid 0x%x", usb_pid);
ret = run_command(utask_cmd, 0);
#ifdef CONFIG_NAND_SUPPORT
snprintf(cmd, 255, "cvi_sd_update %p spinand fip", (void *)UPDATE_ADDR);
pr_debug("%s\n", cmd);
ret = run_command(cmd, 0);
#elif defined(CONFIG_SPI_FLASH)
ret = run_command("sf probe", 0);
snprintf(cmd, 255, "sf update %p ${fip_PART_OFFSET} ${fip_PART_SIZE};", (void *)UPDATE_ADDR)
pr_debug("%s\n", cmd);
ret = run_command(cmd, 0);
#else
// Switch to boot partition
run_command("mmc dev 0 1", 0);
snprintf(cmd, 255, "mmc write %p 0 0x800;", (void *)UPDATE_ADDR);
pr_debug("%s\n", cmd);
run_command(cmd, 0);
snprintf(cmd, 255, "mmc write %p 0x800 0x800;", (void *)UPDATE_ADDR);
pr_debug("%s\n", cmd);
run_command(cmd, 0);
printf("Program fip.bin done\n");
// Switch to user partition
run_command("mmc dev 0 0", 0);
#endif
// Since device will reset by host tool, set flag first
SET_DL_COMPLETE();
while (1) {
ret = run_command(utask_cmd, 0);
if (ret) {
pr_debug("cvi_utask failed(%d)\n", ret);
return ret;
}
//_prgImage((void *)UPDATE_ADDR, readl(HEADER_ADDR + 8));
};
return 0;
}
static int do_cvi_update(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int ret = 1;
uint32_t usb_pid = 0;
if (argc == 1) {
update_magic = readl((unsigned int *)BOOT_SOURCE_FLAG_ADDR);
if (update_magic == SD_UPDATE_MAGIC) {
run_command("env default -a", 0);
ret = _storage_update(sd_dl);
} else if (update_magic == USB_UPDATE_MAGIC) {
run_command("env default -a", 0);
usb_pid = in_be32(UBOOT_PID_SRAM_ADDR);
usb_pid = bcd2hex4(usb_pid);
ret = _usb_update(usb_pid);
}
} else {
printf("Usage:\n%s\n", cmdtp->usage);
}
return ret;
}
U_BOOT_CMD(
cvi_update, 2, 0, do_cvi_update,
"cvi_update [eth, sd, usb]- check boot status and update if necessary\n",
"run cvi_update without parameter will check the boot status and try to update");

39
u-boot-2021.10/cmd/cvi_utask.c Normal file
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#include <stdlib.h>
#include <common.h>
#include <command.h>
#include <cvi_utask.h>
__weak int cvi_usb_polling(void)
{
return 0;
}
__weak void acm_patch_id(unsigned short vid, unsigned short pid)
{
}
static int do_cvi_utask(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
{
printf("\nstart usb task!\n");
if (argc == 3 && strncmp(argv[1], "pid", 3) == 0) {
int pid = (int)simple_strtoul(argv[2], NULL, 10);
acm_patch_id(0, pid);
} else if (argc == 5 && (strncmp(argv[1], "vid", 3) == 0) && (strncmp(argv[3], "pid", 3) == 0)) {
int vid = (int)simple_strtoul(argv[2], NULL, 10);
int pid = (int)simple_strtoul(argv[4], NULL, 10);
acm_patch_id(vid, pid);
}
cvi_usb_polling();
return CMD_RET_SUCCESS;
}
U_BOOT_CMD(cvi_utask, 5, 0, do_cvi_utask,
"bootloader control block command",
"cvi_bcb <interface> <dev> <varname>\n"
);

711
u-boot-2021.10/cmd/efuse.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <command.h>
#include <stdlib.h>
#include <stdarg.h>
#include <malloc.h>
#include <mmio.h>
#include <cvi_efuse.h>
#define EFUSE_DEBUG 0
#define _cc_trace(fmt, ...) __trace("", __FILE__, __func__, __LINE__, fmt, ##__VA_ARGS__)
#define _cc_error(fmt, ...) __trace("ERROR:", __FILE__, __func__, __LINE__, fmt, ##__VA_ARGS__)
#define ERROR(fmt, ...) __trace("ERROR:", __FILE__, __func__, __LINE__, fmt, ##__VA_ARGS__)
#if EFUSE_DEBUG
#define VERBOSE(fmt, ...) __trace("VERBOSE:", __FILE__, __func__, __LINE__, fmt, ##__VA_ARGS__)
static int __trace(const char *prefix, const char *path, const char *func, int lineno, const char *fmt, ...)
{
va_list ap;
int ret;
printf("[%s%s:%s:%d] ", prefix, path, func, lineno);
if (!fmt || fmt[0] == '\0') {
ret = printf("\n");
} else {
va_start(ap, fmt);
ret = vprintf(fmt, ap);
va_end(ap);
}
return ret;
}
#else
#define VERBOSE(fmt, ...)
static int __trace(const char *prefix, const char *path, const char *func, int lineno, const char *fmt, ...)
{
return 0;
}
#endif
static int hex2bytes(const char *hex, unsigned char *buf, int buf_size)
{
int i, total = 0;
char tmp[3];
memset(buf, 0, buf_size);
for (i = 0; i < buf_size; i++) {
if (!hex[0] || !hex[1])
break;
tmp[0] = hex[0];
tmp[1] = hex[1];
tmp[2] = '\0';
buf[i] = simple_strtoul(tmp, NULL, 16);
hex += 2;
total += 1;
}
return total;
}
// ===========================================================================
// EFUSE implementation
// ===========================================================================
#define EFUSE_SHADOW_REG (EFUSE_BASE + 0x100)
#define EFUSE_SIZE 0x100
#define EFUSE_MODE (EFUSE_BASE + 0x0)
#define EFUSE_ADR (EFUSE_BASE + 0x4)
#define EFUSE_DIR_CMD (EFUSE_BASE + 0x8)
#define EFUSE_RD_DATA (EFUSE_BASE + 0xC)
#define EFUSE_STATUS (EFUSE_BASE + 0x10)
#define EFUSE_ONE_WAY (EFUSE_BASE + 0x14)
#define EFUSE_BIT_AREAD BIT(0)
#define EFUSE_BIT_MREAD BIT(1)
#define EFUSE_BIT_PRG BIT(2)
#define EFUSE_BIT_PWR_DN BIT(3)
#define EFUSE_BIT_CMD BIT(4)
#define EFUSE_BIT_BUSY BIT(0)
#define EFUSE_CMD_REFRESH (0x30)
enum EFUSE_READ_TYPE { EFUSE_AREAD, EFUSE_MREAD };
static void cvi_efuse_wait_for_ready(void)
{
while (mmio_read_32(EFUSE_STATUS) & EFUSE_BIT_BUSY)
;
}
static void cvi_efuse_power_on(uint32_t on)
{
if (on)
mmio_setbits_32(EFUSE_MODE, EFUSE_BIT_CMD);
else
mmio_setbits_32(EFUSE_MODE, EFUSE_BIT_PWR_DN | EFUSE_BIT_CMD);
}
static void cvi_efuse_refresh(void)
{
mmio_write_32(EFUSE_MODE, EFUSE_CMD_REFRESH);
}
static void cvi_efuse_prog_bit(uint32_t word_addr, uint32_t bit_addr, uint32_t high_row)
{
uint32_t phy_addr;
// word_addr: virtual addr, take "lower 6-bits" from 7-bits (0-127)
// bit_addr: virtual addr, 5-bits (0-31)
// composite physical addr[11:0] = [11:7]bit_addr + [6:0]word_addr
phy_addr = ((bit_addr & 0x1F) << 7) | ((word_addr & 0x3F) << 1) | high_row;
cvi_efuse_wait_for_ready();
// send efuse program cmd
mmio_write_32(EFUSE_ADR, phy_addr);
mmio_write_32(EFUSE_MODE, EFUSE_BIT_PRG | EFUSE_BIT_CMD);
}
static uint32_t cvi_efuse_read_from_phy(uint32_t phy_word_addr, enum EFUSE_READ_TYPE type)
{
// power on efuse macro
cvi_efuse_power_on(1);
cvi_efuse_wait_for_ready();
mmio_write_32(EFUSE_ADR, phy_word_addr);
if (type == EFUSE_AREAD) // array read
mmio_write_32(EFUSE_MODE, EFUSE_BIT_AREAD | EFUSE_BIT_CMD);
else if (type == EFUSE_MREAD) // margin read
mmio_write_32(EFUSE_MODE, EFUSE_BIT_MREAD | EFUSE_BIT_CMD);
else {
ERROR("EFUSE: Unsupported read type!");
return (uint32_t)-1;
}
cvi_efuse_wait_for_ready();
return mmio_read_32(EFUSE_RD_DATA);
}
static int cvi_efuse_write_word(uint32_t vir_word_addr, uint32_t val)
{
uint32_t i, j, row_val, zero_bit;
uint32_t new_value;
int err_cnt = 0;
for (j = 0; j < 2; j++) {
VERBOSE("EFUSE: Program physical word addr #%d\n", (vir_word_addr << 1) | j);
// array read by word address
row_val = cvi_efuse_read_from_phy((vir_word_addr << 1) | j,
EFUSE_AREAD); // read low word of word_addr
zero_bit = val & (~row_val); // only program zero bit
// program row which bit is zero
for (i = 0; i < 32; i++) {
if ((zero_bit >> i) & 1)
cvi_efuse_prog_bit(vir_word_addr, i, j);
}
// check by margin read
new_value = cvi_efuse_read_from_phy((vir_word_addr << 1) | j, EFUSE_MREAD);
VERBOSE("%s(): val=0x%x new_value=0x%x\n", __func__, val, new_value);
if ((val & new_value) != val) {
err_cnt += 1;
ERROR("EFUSE: Program bits check failed (%d)!\n", err_cnt);
}
}
cvi_efuse_refresh();
return err_cnt >= 2 ? -EIO : 0;
}
static void cvi_efuse_init(void)
{
// power on efuse macro
cvi_efuse_power_on(1);
// send refresh cmd to reload all eFuse values to shadow registers
cvi_efuse_refresh();
// efuse macro will be auto powered off after refresh cmd, so don't
// need to turn it off manually
}
void cvi_efuse_dump(uint32_t vir_word_addr)
{
uint32_t j, val;
for (j = 0; j < 2; j++) {
// check by margin read
val = cvi_efuse_read_from_phy((vir_word_addr << 1) | j, EFUSE_MREAD);
printf("EFUSE EFUSE_MREAD: Program bits %d check 0x%x\n", j, val);
val = cvi_efuse_read_from_phy((vir_word_addr << 1) | j, EFUSE_AREAD);
printf("EFUSE EFUSE_AREAD: Program bits %d check 0x%x\n", j, val);
}
}
int64_t cvi_efuse_read_from_shadow(uint32_t addr)
{
if (addr >= EFUSE_SIZE)
return -EFAULT;
if (addr % 4 != 0)
return -EFAULT;
return mmio_read_32(EFUSE_SHADOW_REG + addr);
}
int cvi_efuse_write(uint32_t addr, uint32_t value)
{
int ret;
VERBOSE("%s(): 0x%x = 0x%x\n", __func__, addr, value);
if (addr >= EFUSE_SIZE)
return -EFAULT;
if (addr % 4 != 0)
return -EFAULT;
ret = cvi_efuse_write_word(addr / 4, value);
VERBOSE("%s(): ret=%d\n", __func__, ret);
cvi_efuse_init();
cvi_efuse_wait_for_ready();
return ret;
}
// ===========================================================================
// EFUSE API
// ===========================================================================
enum CVI_EFUSE_LOCK_WRITE_E {
CVI_EFUSE_LOCK_WRITE_HASH0_PUBLIC = CVI_EFUSE_OTHERS + 1,
CVI_EFUSE_LOCK_WRITE_LOADER_EK,
CVI_EFUSE_LOCK_WRITE_DEVICE_EK,
CVI_EFUSE_LOCK_WRITE_LAST
};
static struct _CVI_EFUSE_AREA_S {
CVI_U32 addr;
CVI_U32 size;
} cvi_efuse_area[] = { [CVI_EFUSE_AREA_USER] = { 0x40, 40 },
[CVI_EFUSE_AREA_DEVICE_ID] = { 0x8c, 8 },
[CVI_EFUSE_AREA_HASH0_PUBLIC] = { 0xA8, 32 },
[CVI_EFUSE_AREA_LOADER_EK] = { 0xD8, 16 },
[CVI_EFUSE_AREA_DEVICE_EK] = { 0xE8, 16 } };
static struct _CVI_EFUSE_LOCK_S {
CVI_S32 wlock_shift;
CVI_S32 rlock_shift;
} cvi_efuse_lock[] = { [CVI_EFUSE_LOCK_HASH0_PUBLIC] = { 0, 8 }, [CVI_EFUSE_LOCK_LOADER_EK] = { 4, 12 },
[CVI_EFUSE_LOCK_DEVICE_EK] = { 6, 14 }, [CVI_EFUSE_LOCK_WRITE_HASH0_PUBLIC] = { 0, -1 },
[CVI_EFUSE_LOCK_WRITE_LOADER_EK] = { 4, -1 }, [CVI_EFUSE_LOCK_WRITE_DEVICE_EK] = { 6, -1 } };
static struct _CVI_EFUSE_USER_S {
CVI_U32 addr;
CVI_U32 size;
} cvi_efuse_user[] = {
{ 0x40, 4 }, { 0x48, 4 }, { 0x50, 4 }, { 0x58, 4 }, { 0x60, 4 },
{ 0x68, 4 }, { 0x70, 4 }, { 0x78, 4 }, { 0x80, 4 }, { 0x88, 4 },
};
#define CVI_EFUSE_TOTAL_SIZE 0x100
#define CVI_EFUSE_LOCK_ADDR 0xF8
#define CVI_EFUSE_SECURE_CONF_ADDR 0xA0
#define CVI_EFUSE_SCS_ENABLE_SHIFT 0
CVI_S32 CVI_EFUSE_GetSize(enum CVI_EFUSE_AREA_E area, CVI_U32 *size)
{
if (area >= ARRAY_SIZE(cvi_efuse_area) || cvi_efuse_area[area].size == 0) {
_cc_error("area (%d) is not found\n", area);
return CVI_ERR_EFUSE_INVALID_AREA;
}
if (size)
*size = cvi_efuse_area[area].size;
return 0;
}
CVI_S32 _CVI_EFUSE_Read(CVI_U32 addr, void *buf, CVI_U32 buf_size)
{
int64_t ret = -1;
int i;
VERBOSE("%s(): 0x%x(%u) to %p\n", __func__, addr, buf_size, buf);
if (!buf)
return CVI_ERR_EFUSE_INVALID_PARA;
if (buf_size > EFUSE_SIZE)
buf_size = EFUSE_SIZE;
for (i = 0; i < buf_size; i += 4) {
ret = cvi_efuse_read_from_shadow(addr + i);
VERBOSE("%s(): i=%x ret=%lx\n", __func__, i, ret);
if (ret < 0)
return ret;
*(uint32_t *)(buf + i) = (ret >= 0) ? ret : 0;
}
return 0;
}
static CVI_S32 _CVI_EFUSE_Write(CVI_U32 addr, const void *buf, CVI_U32 buf_size)
{
_cc_trace("addr=0x%02x\n", addr);
int ret = -1;
CVI_U32 value;
int i;
if (!buf)
return CVI_ERR_EFUSE_INVALID_PARA;
for (i = 0; i < buf_size; i += 4) {
memcpy(&value, buf + i, sizeof(value));
_cc_trace("smc call: 0x%02x=0x%08x\n", addr + i, value);
ret = cvi_efuse_write(addr + i, value);
if (ret < 0) {
printf("%s: error (%d)\n", __func__, ret);
return ret;
}
}
return 0;
}
CVI_S32 CVI_EFUSE_Read(enum CVI_EFUSE_AREA_E area, CVI_U8 *buf, CVI_U32 buf_size)
{
CVI_U32 user_size = cvi_efuse_area[CVI_EFUSE_AREA_USER].size;
CVI_U8 user[user_size], *p;
CVI_S32 ret;
int i;
if (area >= ARRAY_SIZE(cvi_efuse_area) || cvi_efuse_area[area].size == 0) {
_cc_error("area (%d) is not found\n", area);
return CVI_ERR_EFUSE_INVALID_AREA;
}
if (!buf)
return CVI_ERR_EFUSE_INVALID_PARA;
memset(buf, 0, buf_size);
if (buf_size > cvi_efuse_area[area].size)
buf_size = cvi_efuse_area[area].size;
if (area != CVI_EFUSE_AREA_USER)
return _CVI_EFUSE_Read(cvi_efuse_area[area].addr, buf, buf_size);
memset(user, 0, user_size);
p = user;
for (i = 0; i < ARRAY_SIZE(cvi_efuse_user); i++) {
ret = _CVI_EFUSE_Read(cvi_efuse_user[i].addr, p, cvi_efuse_user[i].size);
if (ret < 0)
return ret;
p += cvi_efuse_user[i].size;
}
memcpy(buf, user, buf_size);
return CVI_SUCCESS;
}
CVI_S32 CVI_EFUSE_Write(enum CVI_EFUSE_AREA_E area, const CVI_U8 *buf, CVI_U32 buf_size)
{
CVI_U32 user_size = cvi_efuse_area[CVI_EFUSE_AREA_USER].size;
CVI_U8 user[user_size], *p;
CVI_S32 ret;
int i;
if (area >= ARRAY_SIZE(cvi_efuse_area) || cvi_efuse_area[area].size == 0) {
_cc_error("area (%d) is not found\n", area);
return CVI_ERR_EFUSE_INVALID_AREA;
}
if (!buf)
return CVI_ERR_EFUSE_INVALID_PARA;
if (buf_size > cvi_efuse_area[area].size)
buf_size = cvi_efuse_area[area].size;
if (area != CVI_EFUSE_AREA_USER)
return _CVI_EFUSE_Write(cvi_efuse_area[area].addr, buf, buf_size);
memset(user, 0, user_size);
memcpy(user, buf, buf_size);
p = user;
for (i = 0; i < ARRAY_SIZE(cvi_efuse_user); i++) {
ret = _CVI_EFUSE_Write(cvi_efuse_user[i].addr, p, cvi_efuse_user[i].size);
if (ret < 0)
return ret;
p += cvi_efuse_user[i].size;
}
return CVI_SUCCESS;
}
CVI_S32 CVI_EFUSE_EnableSecureBoot(void)
{
CVI_U32 value = 0x3 << CVI_EFUSE_SCS_ENABLE_SHIFT;
return _CVI_EFUSE_Write(CVI_EFUSE_SECURE_CONF_ADDR, &value, sizeof(value));
}
CVI_S32 CVI_EFUSE_IsSecureBootEnabled(void)
{
CVI_U32 value = 0;
CVI_S32 ret = 0;
ret = _CVI_EFUSE_Read(CVI_EFUSE_SECURE_CONF_ADDR, &value, sizeof(value));
_cc_trace("ret=%d value=%u\n", ret, value);
if (ret < 0)
return ret;
value &= 0x3 << CVI_EFUSE_SCS_ENABLE_SHIFT;
return !!value;
}
CVI_S32 CVI_EFUSE_Lock(enum CVI_EFUSE_LOCK_E lock)
{
CVI_U32 value = 0;
CVI_U32 ret = 0;
if (lock >= ARRAY_SIZE(cvi_efuse_lock)) {
_cc_error("lock (%d) is not found\n", lock);
return CVI_ERR_EFUSE_INVALID_AREA;
}
value = 0x3 << cvi_efuse_lock[lock].wlock_shift;
ret = _CVI_EFUSE_Write(CVI_EFUSE_LOCK_ADDR, &value, sizeof(value));
if (ret < 0)
return ret;
if (cvi_efuse_lock[lock].rlock_shift >= 0) {
value = 0x3 << cvi_efuse_lock[lock].rlock_shift;
ret = _CVI_EFUSE_Write(CVI_EFUSE_LOCK_ADDR, &value, sizeof(value));
}
return ret;
}
CVI_S32 CVI_EFUSE_IsLocked(enum CVI_EFUSE_LOCK_E lock)
{
CVI_S32 ret = 0;
CVI_U32 value = 0;
if (lock >= ARRAY_SIZE(cvi_efuse_lock)) {
_cc_error("lock (%d) is not found\n", lock);
return CVI_ERR_EFUSE_INVALID_AREA;
}
ret = _CVI_EFUSE_Read(CVI_EFUSE_LOCK_ADDR, &value, sizeof(value));
_cc_trace("ret=%d value=%u\n", ret, value);
if (ret < 0)
return ret;
value &= 0x3 << cvi_efuse_lock[lock].wlock_shift;
return !!value;
}
CVI_S32 CVI_EFUSE_LockWrite(enum CVI_EFUSE_LOCK_E lock)
{
CVI_U32 value = 0;
CVI_S32 ret = 0;
if (lock >= ARRAY_SIZE(cvi_efuse_lock)) {
_cc_error("lock (%d) is not found\n", lock);
return CVI_ERR_EFUSE_INVALID_AREA;
}
value = 0x3 << cvi_efuse_lock[lock].wlock_shift;
ret = _CVI_EFUSE_Write(CVI_EFUSE_LOCK_ADDR, &value, sizeof(value));
return ret;
}
CVI_S32 CVI_EFUSE_IsWriteLocked(enum CVI_EFUSE_LOCK_E lock)
{
CVI_S32 ret = 0;
CVI_U32 value = 0;
if (lock >= ARRAY_SIZE(cvi_efuse_lock)) {
_cc_error("lock (%d) is not found\n", lock);
return CVI_ERR_EFUSE_INVALID_AREA;
}
ret = _CVI_EFUSE_Read(CVI_EFUSE_LOCK_ADDR, &value, sizeof(value));
_cc_trace("ret=%d value=%u\n", ret, value);
if (ret < 0)
return ret;
value &= 0x3 << cvi_efuse_lock[lock].wlock_shift;
return !!value;
}
static const char *const efuse_index[] = {
[CVI_EFUSE_AREA_USER] = "USER",
[CVI_EFUSE_AREA_DEVICE_ID] = "DEVICE_ID",
[CVI_EFUSE_AREA_HASH0_PUBLIC] = "HASH0_PUBLIC",
[CVI_EFUSE_AREA_LOADER_EK] = "LOADER_EK",
[CVI_EFUSE_AREA_DEVICE_EK] = "DEVICE_EK",
[CVI_EFUSE_LOCK_HASH0_PUBLIC] = "LOCK_HASH0_PUBLIC",
[CVI_EFUSE_LOCK_LOADER_EK] = "LOCK_LOADER_EK",
[CVI_EFUSE_LOCK_DEVICE_EK] = "LOCK_DEVICE_EK",
[CVI_EFUSE_LOCK_WRITE_HASH0_PUBLIC] = "LOCK_WRITE_HASH0_PUBLIC",
[CVI_EFUSE_LOCK_WRITE_LOADER_EK] = "LOCK_WRITE_LOADER_EK",
[CVI_EFUSE_LOCK_WRITE_DEVICE_EK] = "LOCK_WRITE_DEVICE_EK",
[CVI_EFUSE_SECUREBOOT] = "SECUREBOOT",
};
static int find_efuse_by_name(const char *name)
{
int i;
for (i = 0; i < ARRAY_SIZE(efuse_index); i++) {
if (!efuse_index[i])
continue;
if (!strcmp(name, efuse_index[i]))
return i;
}
return -1;
}
static int do_efuser(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
int idx;
int ret;
unsigned int size;
unsigned char buf[128];
if (argc != 2)
return CMD_RET_USAGE;
_cc_trace("Read eFuse: %s\n", argv[1]);
idx = find_efuse_by_name(argv[1]);
if (idx < 0)
return CMD_RET_USAGE;
_cc_trace("idx=%d %s\n", idx, efuse_index[idx]);
if (idx < CVI_EFUSE_AREA_LAST) {
if (CVI_EFUSE_GetSize(idx, &size) < 0)
return CMD_RET_FAILURE;
_cc_trace("size=%d\n", size);
if (CVI_EFUSE_Read(idx, buf, size) < 0)
return CMD_RET_FAILURE;
print_buffer(0, buf, 1, size, 0);
return 0;
} else if (idx < CVI_EFUSE_LOCK_LAST) {
ret = CVI_EFUSE_IsLocked(idx);
printf("%s is %s locked\n", efuse_index[idx], ret ? "" : "not");
return 0;
} else if (idx < CVI_EFUSE_LOCK_WRITE_LAST) {
ret = CVI_EFUSE_IsWriteLocked(idx);
printf("%s is %s write_locked\n", efuse_index[idx], ret ? "" : "not");
return 0;
} else if (idx == CVI_EFUSE_SECUREBOOT) {
ret = CVI_EFUSE_IsSecureBootEnabled();
printf("Secure Boot is %s\n", ret ? "enabled" : "disabled");
return 0;
}
return CMD_RET_FAILURE;
}
static int do_efusew(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
int idx;
int ret;
unsigned int size;
unsigned char buf[128] = { 0 };
_cc_trace("argc=%d\n", argc);
if (argc != 2 && argc != 3)
return CMD_RET_USAGE;
_cc_trace("Write eFuse: %s=%s\n", argv[1], argv[2]);
idx = find_efuse_by_name(argv[1]);
if (idx < 0)
return CMD_RET_USAGE;
_cc_trace("idx=%d %s\n", idx, efuse_index[idx]);
printf("Write eFuse %s(%d) with:\n", efuse_index[idx], idx);
if (idx < CVI_EFUSE_AREA_LAST) {
if (argc != 3)
return CMD_RET_USAGE;
size = hex2bytes(argv[2], buf, sizeof(buf));
if (size <= 0)
return CMD_RET_USAGE;
print_buffer(0, buf, 1, size, 0);
if (CVI_EFUSE_GetSize(idx, &size) < 0)
return CMD_RET_FAILURE;
_cc_trace("size=%d\n", size);
ret = CVI_EFUSE_Write(idx, buf, size);
if (ret < 0) {
printf("Failed to write %s\n", efuse_index[idx]);
return CMD_RET_FAILURE;
}
return 0;
} else if (idx < CVI_EFUSE_LOCK_LAST) {
if (CVI_EFUSE_Lock(idx) < 0) {
printf("Failed to lock %s\n", efuse_index[idx]);
return CMD_RET_FAILURE;
}
printf("%s is locked\n", efuse_index[idx]);
return 0;
} else if (idx < CVI_EFUSE_LOCK_WRITE_LAST) {
if (CVI_EFUSE_LockWrite(idx) < 0) {
printf("Failed to lock write %s\n", efuse_index[idx]);
return CMD_RET_FAILURE;
}
printf("%s is locked\n", efuse_index[idx]);
return 0;
} else if (idx == CVI_EFUSE_SECUREBOOT) {
ret = CVI_EFUSE_EnableSecureBoot();
printf("Enabled Secure Boot is %s\n", ret >= 0 ? "success" : "failed");
return 0;
}
return CMD_RET_FAILURE;
}
static int do_efusew_word(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
uint32_t addr, value;
int ret = -1;
if (argc != 3)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 0);
value = simple_strtoul(argv[2], NULL, 0);
printf("Write eFuse: 0x%04x=0x%08x\n", addr, value);
ret = cvi_efuse_write(addr, value);
if (ret < 0) {
printf("ERROR: ret=%d\n", ret);
return CMD_RET_FAILURE;
}
return 0;
}
static int do_efuser_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
int i;
uint32_t buf[EFUSE_SIZE / sizeof(uint32_t)];
for (i = 0; i < ARRAY_SIZE(buf); i++)
buf[i] = cvi_efuse_read_from_shadow(i * sizeof(uint32_t));
print_buffer(0, buf, 1, sizeof(buf), 16);
return 0;
}
U_BOOT_CMD(efuser, 9, 1, do_efuser, "Read efuse",
"[args..]\n"
" - args ...");
U_BOOT_CMD(efusew, 9, 1, do_efusew, "Write efuse",
"[args..]\n"
" - args ...");
U_BOOT_CMD(efusew_word, 9, 1, do_efusew_word, "Write word to efuse",
"efusew_word addr value\n"
" - args ...");
U_BOOT_CMD(efuser_dump, 9, 1, do_efuser_dump, "Read/Dump efuse",
"do_efuser_dump\n"
" - args ...");

62
u-boot-2021.10/cmd/mmc.c
View File

@ -13,6 +13,8 @@
#include <part.h> #include <part.h>
#include <sparse_format.h> #include <sparse_format.h>
#include <image-sparse.h> #include <image-sparse.h>
#include <div64.h>
#include <linux/math64.h>
static int curr_device = -1; static int curr_device = -1;
@ -341,6 +343,7 @@ static int do_mmc_read(struct cmd_tbl *cmdtp, int flag,
struct mmc *mmc; struct mmc *mmc;
u32 blk, cnt, n; u32 blk, cnt, n;
void *addr; void *addr;
ulong start_time, delta;
if (argc != 4) if (argc != 4)
return CMD_RET_USAGE; return CMD_RET_USAGE;
@ -355,9 +358,17 @@ static int do_mmc_read(struct cmd_tbl *cmdtp, int flag,
printf("\nMMC read: dev # %d, block # %d, count %d ... ", printf("\nMMC read: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt); curr_device, blk, cnt);
start_time = get_timer(0);
n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR"); delta = get_timer(start_time);
printf("%d blocks read: %s in %lu ms", n, (n == cnt) ? "OK" : "ERROR", delta);
if (delta > 0) {
puts(" (");
print_size(div_u64(n * 512, delta) * 1000, "/s");
puts(")");
}
puts("\n");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
} }
@ -434,6 +445,7 @@ static int do_mmc_write(struct cmd_tbl *cmdtp, int flag,
struct mmc *mmc; struct mmc *mmc;
u32 blk, cnt, n; u32 blk, cnt, n;
void *addr; void *addr;
ulong start_time, delta;
if (argc != 4) if (argc != 4)
return CMD_RET_USAGE; return CMD_RET_USAGE;
@ -453,8 +465,16 @@ static int do_mmc_write(struct cmd_tbl *cmdtp, int flag,
printf("Error: card is write protected!\n"); printf("Error: card is write protected!\n");
return CMD_RET_FAILURE; return CMD_RET_FAILURE;
} }
start_time = get_timer(0);
n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR"); delta = get_timer(start_time);
printf("%d blocks written: %s in %lu ms", n, (n == cnt) ? "OK" : "ERROR", delta);
if (delta > 0) {
puts(" (");
print_size(div_u64(n * 512, delta) * 1000, "/s");
puts(")");
}
puts("\n");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
} }
@ -464,6 +484,7 @@ static int do_mmc_erase(struct cmd_tbl *cmdtp, int flag,
{ {
struct mmc *mmc; struct mmc *mmc;
u32 blk, cnt, n; u32 blk, cnt, n;
ulong start_time, delta;
if (argc != 3) if (argc != 3)
return CMD_RET_USAGE; return CMD_RET_USAGE;
@ -482,8 +503,16 @@ static int do_mmc_erase(struct cmd_tbl *cmdtp, int flag,
printf("Error: card is write protected!\n"); printf("Error: card is write protected!\n");
return CMD_RET_FAILURE; return CMD_RET_FAILURE;
} }
start_time = get_timer(0);
n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt); n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt);
printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR"); delta = get_timer(start_time);
printf("%d blocks erased: %s in %lu ms ", n, (n == cnt) ? "OK" : "ERROR", delta);
if (delta > 0) {
puts(" (");
print_size(div_u64(n * 512, delta) * 1000, "/s");
puts(")");
}
puts("\n");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
} }
@ -585,6 +614,30 @@ static int do_mmc_dev(struct cmd_tbl *cmdtp, int flag,
return CMD_RET_SUCCESS; return CMD_RET_SUCCESS;
} }
static int do_mmc_fuse_rstn(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
int dev, ret;
struct mmc *mmc;
if (argc == 2) {
dev = (int)dectoul(argv[1], NULL);
mmc = init_mmc_device(dev, true);
} else {
return CMD_RET_USAGE;
}
if (!mmc)
return CMD_RET_FAILURE;
ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, 0x1);
printf("Set RST_N = 0x1 ret: %d\n", ret);
if (ret)
return 1;
return CMD_RET_SUCCESS;
}
static int do_mmc_list(struct cmd_tbl *cmdtp, int flag, static int do_mmc_list(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[]) int argc, char *const argv[])
{ {
@ -1019,6 +1072,7 @@ static struct cmd_tbl cmd_mmc[] = {
U_BOOT_CMD_MKENT(rescan, 2, 1, do_mmc_rescan, "", ""), U_BOOT_CMD_MKENT(rescan, 2, 1, do_mmc_rescan, "", ""),
U_BOOT_CMD_MKENT(part, 1, 1, do_mmc_part, "", ""), U_BOOT_CMD_MKENT(part, 1, 1, do_mmc_part, "", ""),
U_BOOT_CMD_MKENT(dev, 4, 0, do_mmc_dev, "", ""), U_BOOT_CMD_MKENT(dev, 4, 0, do_mmc_dev, "", ""),
U_BOOT_CMD_MKENT(fuse_rstn, 2, 0, do_mmc_fuse_rstn, "", ""),
U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""), U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""),
#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
U_BOOT_CMD_MKENT(hwpartition, 28, 0, do_mmc_hwpartition, "", ""), U_BOOT_CMD_MKENT(hwpartition, 28, 0, do_mmc_hwpartition, "", ""),

10
u-boot-2021.10/cmd/nand.c
View File

@ -393,6 +393,11 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc,
int dev = nand_curr_device; int dev = nand_curr_device;
int repeat = flag & CMD_FLAG_REPEAT; int repeat = flag & CMD_FLAG_REPEAT;
ulong start;
int temp;
start = get_timer(0);
/* at least two arguments please */ /* at least two arguments please */
if (argc < 2) if (argc < 2)
goto usage; goto usage;
@ -621,7 +626,7 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc,
ret = nand_write_skip_bad(mtd, off, &rwsize, ret = nand_write_skip_bad(mtd, off, &rwsize,
NULL, maxsize, NULL, maxsize,
(u_char *)addr, (u_char *)addr,
WITH_WR_VERIFY); 0);
#ifdef CONFIG_CMD_NAND_TRIMFFS #ifdef CONFIG_CMD_NAND_TRIMFFS
} else if (!strcmp(s, ".trimffs")) { } else if (!strcmp(s, ".trimffs")) {
if (read) { if (read) {
@ -655,6 +660,9 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc,
printf(" %zu bytes %s: %s\n", rwsize, printf(" %zu bytes %s: %s\n", rwsize,
read ? "read" : "written", ret ? "ERROR" : "OK"); read ? "read" : "written", ret ? "ERROR" : "OK");
temp = rwsize / get_timer(start);
printf("nand %s speed %d.%d MB/s\n", argv[0], temp / 1000, (temp - (temp / 1000) * 1000));
return ret == 0 ? 0 : 1; return ret == 0 ? 0 : 1;
} }

9
u-boot-2021.10/cmd/net.c
View File

@ -17,7 +17,9 @@
#include <net/udp.h> #include <net/udp.h>
#include <net/sntp.h> #include <net/sntp.h>
static int netboot_common(enum proto_t, struct cmd_tbl *, int, char * const []); static int __attribute__((unused)) netboot_common(enum proto_t,
struct cmd_tbl *,
int, char * const []);
#ifdef CONFIG_CMD_BOOTP #ifdef CONFIG_CMD_BOOTP
static int do_bootp(struct cmd_tbl *cmdtp, int flag, int argc, static int do_bootp(struct cmd_tbl *cmdtp, int flag, int argc,
@ -191,8 +193,9 @@ static void netboot_update_env(void)
#endif #endif
} }
static int netboot_common(enum proto_t proto, struct cmd_tbl *cmdtp, int argc, static int __attribute__((unused)) netboot_common(enum proto_t proto,
char *const argv[]) struct cmd_tbl *cmdtp,
int argc, char *const argv[])
{ {
char *s; char *s;
char *end; char *end;

12
u-boot-2021.10/cmd/sf.c
View File

@ -172,6 +172,7 @@ static const char *spi_flash_update_block(struct spi_flash *flash, u32 offset,
size_t len, const char *buf, char *cmp_buf, size_t *skipped) size_t len, const char *buf, char *cmp_buf, size_t *skipped)
{ {
char *ptr = (char *)buf; char *ptr = (char *)buf;
u8 *tmp = NULL;
debug("offset=%#x, sector_size=%#x, len=%#zx\n", debug("offset=%#x, sector_size=%#x, len=%#zx\n",
offset, flash->sector_size, len); offset, flash->sector_size, len);
@ -190,6 +191,10 @@ static const char *spi_flash_update_block(struct spi_flash *flash, u32 offset,
return "erase"; return "erase";
/* If it's a partial sector, copy the data into the temp-buffer */ /* If it's a partial sector, copy the data into the temp-buffer */
if (len != flash->sector_size) { if (len != flash->sector_size) {
for (int i = 0; i < flash->sector_size; i++) {
tmp = (u8 *)cmp_buf;
tmp[i] = 0xff;
}
memcpy(cmp_buf, buf, len); memcpy(cmp_buf, buf, len);
ptr = cmp_buf; ptr = cmp_buf;
} }
@ -268,6 +273,10 @@ static int do_spi_flash_read_write(int argc, char *const argv[])
int ret = 1; int ret = 1;
int dev = 0; int dev = 0;
loff_t offset, len, maxsize; loff_t offset, len, maxsize;
ulong start;
int temp = 0;
start = get_timer(0);
if (argc < 3) if (argc < 3)
return -1; return -1;
@ -313,6 +322,9 @@ static int do_spi_flash_read_write(int argc, char *const argv[])
printf("OK\n"); printf("OK\n");
} }
temp = len / get_timer(start);
printf("sf %s speed %d.%d MB/s\n", argv[0], temp / 1000, (temp - (temp / 1000) * 1000));
unmap_physmem(buf, len); unmap_physmem(buf, len);
return ret == 0 ? 0 : 1; return ret == 0 ? 0 : 1;

2
u-boot-2021.10/common/Kconfig.boot
View File

@ -329,7 +329,7 @@ config HAVE_SYS_TEXT_BASE
bool bool
depends on !NIOS2 && !XTENSA depends on !NIOS2 && !XTENSA
depends on !EFI_APP depends on !EFI_APP
default y default n
config SYS_TEXT_BASE config SYS_TEXT_BASE
depends on HAVE_SYS_TEXT_BASE depends on HAVE_SYS_TEXT_BASE

1
u-boot-2021.10/common/autoboot.c
View File

@ -486,6 +486,7 @@ void autoboot_command(const char *s)
if (lock) if (lock)
prev = disable_ctrlc(1); /* disable Ctrl-C checking */ prev = disable_ctrlc(1); /* disable Ctrl-C checking */
board_save_time_record(TIME_RECORDS_FIELD_BOOTCMD_START);
run_command_list(s, -1, 0); run_command_list(s, -1, 0);
if (lock) if (lock)

18
u-boot-2021.10/common/board_f.c
View File

@ -359,6 +359,15 @@ static int setup_dest_addr(void)
return 0; return 0;
} }
#if (CONFIG_SYS_RESVIONSZ != 0)
static int reserve_ion(void)
{
gd->relocaddr -= CONFIG_SYS_RESVIONSZ;
debug("Reserving %dk for ion buffer at %08lx\n", (CONFIG_SYS_RESVIONSZ >> 16), gd->relocaddr);
return 0;
}
#endif
#ifdef CONFIG_PRAM #ifdef CONFIG_PRAM
/* reserve protected RAM */ /* reserve protected RAM */
static int reserve_pram(void) static int reserve_pram(void)
@ -472,8 +481,8 @@ static int reserve_noncached(void)
MMU_SECTION_SIZE; MMU_SECTION_SIZE;
gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY, gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
MMU_SECTION_SIZE); MMU_SECTION_SIZE);
debug("Reserving %dM for noncached_alloc() at: %08lx\n", debug("Reserving %lldM for noncached_alloc() at: %08lx\n",
CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp); (long long)(CONFIG_SYS_NONCACHED_MEMORY >> 20), gd->start_addr_sp);
return 0; return 0;
} }
@ -734,6 +743,7 @@ static int jump_to_copy(void)
arch_setup_gd(gd->new_gd); arch_setup_gd(gd->new_gd);
board_init_f_r_trampoline(gd->start_addr_sp); board_init_f_r_trampoline(gd->start_addr_sp);
#else #else
printf("gd->relocaddr=0x%lx. offset=0x%lx\n", gd->relocaddr, gd->relocaddr - CONFIG_SYS_TEXT_BASE);
relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
#endif #endif
@ -905,6 +915,10 @@ static const init_fnc_t init_sequence_f[] = {
* - board info struct * - board info struct
*/ */
setup_dest_addr, setup_dest_addr,
#if (CONFIG_SYS_RESVIONSZ != 0)
reserve_ion,
#endif
#ifdef CONFIG_OF_BOARD_FIXUP #ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt, fix_fdt,
#endif #endif

6
u-boot-2021.10/common/board_r.c
View File

@ -661,9 +661,6 @@ static init_fnc_t init_sequence_r[] = {
stdio_init_tables, stdio_init_tables,
serial_initialize, serial_initialize,
initr_announce, initr_announce,
#if CONFIG_IS_ENABLED(WDT)
initr_watchdog,
#endif
INIT_FUNC_WATCHDOG_RESET INIT_FUNC_WATCHDOG_RESET
#if defined(CONFIG_NEEDS_MANUAL_RELOC) && defined(CONFIG_BLOCK_CACHE) #if defined(CONFIG_NEEDS_MANUAL_RELOC) && defined(CONFIG_BLOCK_CACHE)
blkcache_init, blkcache_init,
@ -689,6 +686,9 @@ static init_fnc_t init_sequence_r[] = {
#endif #endif
#ifdef CONFIG_ARCH_EARLY_INIT_R #ifdef CONFIG_ARCH_EARLY_INIT_R
arch_early_init_r, arch_early_init_r,
#endif
#if CONFIG_IS_ENABLED(WDT)
initr_watchdog,
#endif #endif
power_init_board, power_init_board,
#ifdef CONFIG_MTD_NOR_FLASH #ifdef CONFIG_MTD_NOR_FLASH

14
u-boot-2021.10/common/image.c
View File

@ -17,6 +17,7 @@
#include <asm/cache.h> #include <asm/cache.h>
#include <u-boot/crc.h> #include <u-boot/crc.h>
#include <watchdog.h> #include <watchdog.h>
#include <time.h>
#ifdef CONFIG_SHOW_BOOT_PROGRESS #ifdef CONFIG_SHOW_BOOT_PROGRESS
#include <status_led.h> #include <status_led.h>
@ -444,10 +445,19 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
uint unc_len, ulong *load_end) uint unc_len, ulong *load_end)
{ {
int ret = 0; int ret = 0;
#ifndef USE_HOSTCC
ulong start;
#endif
*load_end = load; *load_end = load;
print_decomp_msg(comp, type, load == image_start); print_decomp_msg(comp, type, load == image_start);
#ifndef USE_HOSTCC
// Save decompression start time
board_save_time_record(TIME_RECORDS_FIELD_DECOMPRESS_KERNEL_START);
start = get_timer(0);
#endif
/* /*
* Load the image to the right place, decompressing if needed. After * Load the image to the right place, decompressing if needed. After
* this, image_len will be set to the number of uncompressed bytes * this, image_len will be set to the number of uncompressed bytes
@ -581,6 +591,10 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
*load_end = load + image_len; *load_end = load + image_len;
#ifndef USE_HOSTCC
printf(" Decompressing %lu bytes used %lums\n", image_len, get_timer(start));
#endif
return ret; return ret;
} }

51
u-boot-2021.10/cvitek.mk Normal file
View File

@ -0,0 +1,51 @@
ifeq (${UBOOT_VBOOT}, 1)
KBUILD_CPPFLAGS += -DUBOOT_VBOOT
endif
ifeq (${CONFIG_SKIP_RAMDISK},y)
KBUILD_CPPFLAGS += -DCONFIG_SKIP_RAMDISK=${CONFIG_SKIP_RAMDISK}
endif
ifeq (${CONFIG_USE_DEFAULT_ENV},y)
KBUILD_CPPFLAGS += -DCONFIG_USE_DEFAULT_ENV=${CONFIG_USE_DEFAULT_ENV}
endif
ifeq (${STORAGE_TYPE}, spinand)
KBUILD_CFLAGS += -DCONFIG_NAND_SUPPORT
KBUILD_CFLAGS += -DSPINAND_SQSH
endif
ifeq (${STORAGE_TYPE}, emmc)
KBUILD_CFLAGS += -DCONFIG_EMMC_SUPPORT
endif
ifeq (${STORAGE_TYPE}, sd)
KBUILD_CFLAGS += -DCONFIG_SD_BOOT
endif
ifeq (${RELEASE}, 1)
KBUILD_CPPFLAGS += -DRELEASE
endif
cvichip = $(shell echo $(CHIP) | tr a-z A-Z)
cviboard = $(shell echo $(CVIBOARD) | tr a-z A-Z)
KBUILD_CPPFLAGS += -DCVICHIP=${CHIP}
KBUILD_CPPFLAGS += -DCVIBOARD=${CVIBOARD} -D${cvichip}_${cviboard}
ifneq (${PANEL_TUNING_PARAM},)
cvi_panel = $(shell echo $(PANEL_TUNING_PARAM) | tr a-z A-Z)
KBUILD_CPPFLAGS += -D${cvi_panel}
KBUILD_CPPFLAGS += $(if $(findstring I80,$(cvi_panel)),-D${cvichip}_${cviboard}_I80,)
endif
ifneq (${PANEL_LANE_NUM_TUNING_PARAM},)
KBUILD_CPPFLAGS += -D$(shell echo $(PANEL_LANE_NUM_TUNING_PARAM) | tr a-z A-Z)
endif
ifneq (${PANEL_LANE_SWAP_TUNING_PARAM},)
KBUILD_CPPFLAGS += -D$(shell echo $(PANEL_LANE_SWAP_TUNING_PARAM) | tr a-z A-Z)
endif
KBUILD_CPPFLAGS += $(if $(findstring CV183X,$(CHIP_ARCH)),-DBOOTLOGO_ISP_RESET,)
KBUILD_CFLAGS += -I$(srctree)/include/cvitek

9
u-boot-2021.10/drivers/adc/Kconfig
View File

@ -11,6 +11,15 @@ config ADC
- support supply's phandle with auto-enable - support supply's phandle with auto-enable
- supply polarity setting in fdt - supply polarity setting in fdt
config ADC_CVITEK
bool "Enable cvitek ADC driver"
help
This enables basic driver for cvitek ADC compatible with cvitek soc.
It provides:
- 3 analog input channels
- 12-bit resolution
- 320 KSPS of sample rate
config ADC_EXYNOS config ADC_EXYNOS
bool "Enable Exynos 54xx ADC driver" bool "Enable Exynos 54xx ADC driver"
help help

1
u-boot-2021.10/drivers/adc/Makefile
View File

@ -5,6 +5,7 @@
# #
obj-$(CONFIG_ADC) += adc-uclass.o obj-$(CONFIG_ADC) += adc-uclass.o
obj-$(CONFIG_ADC_CVITEK) += cvitek-adc.o
obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o
obj-$(CONFIG_ADC_SANDBOX) += sandbox.o obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o

2
u-boot-2021.10/drivers/adc/adc-uclass.c
View File

@ -22,7 +22,7 @@
#define CHECK_MASK (!CHECK_NUMBER) #define CHECK_MASK (!CHECK_NUMBER)
/* TODO: add support for timer uclass (for early calls) */ /* TODO: add support for timer uclass (for early calls) */
#ifdef CONFIG_SANDBOX_ARCH #if defined(CONFIG_SANDBOX_ARCH) || defined(CONFIG_ADC_CVITEK)
#define sdelay(x) udelay(x) #define sdelay(x) udelay(x)
#else #else
extern void sdelay(unsigned long loops); extern void sdelay(unsigned long loops);

219
u-boot-2021.10/drivers/adc/cvitek-adc.c Normal file
View File

@ -0,0 +1,219 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 cvitek All rights reserved.
* Author: jinyu zhao <jinyu.zhaok@cvitek.com>
*
* cvitek SARADC driver for U-Boot
*/
#include <common.h>
#include <errno.h>
#include <dm.h>
#include <adc.h>
#include <asm/io.h>
#define CVITEK_ADC_MAX_CHANNELS 6
#define CVITEK_ADC_DATA_BITS 12
enum channel {
/* Top domain ADC ch1, ch2, ch3 */
ADC1 = 1,
ADC2,
ADC3,
/* no die domain ADC ch1, ch2, ch3 */
PWR_ADC1,/* ADC4 <== PWR_GPIO2 */
PWR_ADC2,/* ADC5 <== PWR_GPIO1 */
PWR_ADC3,/* ADC6 <== PWR_VBAT_DET */
};
struct cvitek_adc_regs {
unsigned int reserved_1[1];
unsigned int ctrl;/* 0x04 */
unsigned int status;/* 0x08 */
unsigned int cyc_set;/* 0x0c */
unsigned int reserved_2[1];
unsigned int ch1_result;/* 0x14 */
unsigned int ch2_result;/* 0x18 */
unsigned int ch3_result;/* 0x1c */
unsigned int intr_en;/* 0x20 */
unsigned int intr_clr;/* 0x24 */
unsigned int intr_sta;/* 0x28 */
unsigned int intr_raw;/* 0x2c */
};
struct cvitek_adc_priv {
struct udevice *dev; /* Device, NULL for invalid adc */
void __iomem *top_domain_base;
void __iomem *rtc_domain_base;
int active_channel;
};
static void cvitek_adc_cyc_setting(struct cvitek_adc_regs *regs)
{
uint32_t value;
value = readl(&regs->cyc_set);
value &= ~(0xf << 12);
value |= (0xf << 12);//set saradc clock cycle=840ns
writel(value, &regs->cyc_set);
}
int cvitek_adc_channel_data(struct udevice *dev, int channel,
unsigned int *data)
{
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct cvitek_adc_priv *priv = dev_get_priv(dev);
struct cvitek_adc_regs *regs;
unsigned int value;
if (channel != priv->active_channel) {
pr_err("Requested channel is not active!");
return -EINVAL;
}
switch (channel) {
case ADC1:
case ADC2:
case ADC3:
regs = (struct cvitek_adc_regs *)priv->top_domain_base;
break;
case PWR_ADC1:
case PWR_ADC2:
case PWR_ADC3:
regs = (struct cvitek_adc_regs *)priv->rtc_domain_base;
break;
}
// Trigger measurement
value = readl(&regs->ctrl);
writel(value | 0x1, &regs->ctrl);
// Check busy status
while (readl(&regs->status) & 0x1)
;
switch (channel) {
case PWR_ADC1:
case ADC1:
value = readl(&regs->ch1_result) & uc_pdata->data_mask;
break;
case PWR_ADC2:
case ADC2:
value = readl(&regs->ch2_result) & uc_pdata->data_mask;
break;
case PWR_ADC3:
case ADC3:
value = readl(&regs->ch3_result) & uc_pdata->data_mask;
break;
}
*data = value;
return 0;
}
int cvitek_adc_start_channel(struct udevice *dev, int channel)
{
struct cvitek_adc_priv *priv = dev_get_priv(dev);
struct cvitek_adc_regs *regs;
unsigned int value;
priv->active_channel = channel;
switch (channel) {
case ADC1:
case ADC2:
case ADC3:
regs = (struct cvitek_adc_regs *)priv->top_domain_base;
break;
case PWR_ADC1:
case PWR_ADC2:
case PWR_ADC3:
channel -= 3;
regs = (struct cvitek_adc_regs *)priv->rtc_domain_base;
break;
}
// Disable saradc interrupt
writel(0x0, &regs->intr_en);
// Set saradc cycle
cvitek_adc_cyc_setting(regs);
// Set channel
value = readl(&regs->ctrl);
writel(value | (1 << (4 + channel)),
&regs->ctrl);
return 0;
}
int cvitek_adc_stop(struct udevice *dev)
{
struct cvitek_adc_priv *priv = dev_get_priv(dev);
struct cvitek_adc_regs *top_regs, *rtcsyc_regs;
unsigned int value;
top_regs = (struct cvitek_adc_regs *)priv->top_domain_base;
rtcsyc_regs = (struct cvitek_adc_regs *)priv->rtc_domain_base;
// disable measurement
value = readl(&top_regs->ctrl);
writel(value & ~0x1, &top_regs->ctrl);
value = readl(&rtcsyc_regs->ctrl);
writel(value & ~0x1, &rtcsyc_regs->ctrl);
priv->active_channel = -1;
return 0;
}
int cvitek_adc_probe(struct udevice *dev)
{
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct cvitek_adc_priv *priv = dev_get_priv(dev);
fdt_addr_t base;
base = dev_read_addr_index(dev, 0);
if (base == FDT_ADDR_T_NONE) {
pr_err("Can't get the top SARADC register base address\n");
return -ENXIO;
}
priv->top_domain_base = (void *)base;
base = dev_read_addr_index(dev, 1);
if (base == FDT_ADDR_T_NONE) {
pr_err("Can't get the rtcsys SARADC register base address\n");
return -ENXIO;
}
priv->rtc_domain_base = (void *)base;
priv->dev = dev;
priv->active_channel = -1;
uc_pdata->data_mask = (1 << CVITEK_ADC_DATA_BITS) - 1;
uc_pdata->data_format = 0;
uc_pdata->data_timeout_us = 15;
/* Mask available channel bits: [1:5] */
uc_pdata->channel_mask = (2 << CVITEK_ADC_MAX_CHANNELS) - 2;
return 0;
}
static const struct adc_ops cvitek_adc_ops = {
.start_channel = cvitek_adc_start_channel,
.channel_data = cvitek_adc_channel_data,
.stop = cvitek_adc_stop,
};
static const struct udevice_id cvitek_adc_ids[] = {
{ .compatible = "cvitek,saradc" },
{ }
};
U_BOOT_DRIVER(cvitek_adc) = {
.name = "cvitek-adc",
.id = UCLASS_ADC,
.of_match = cvitek_adc_ids,
.ops = &cvitek_adc_ops,
.probe = cvitek_adc_probe,
.priv_auto = sizeof(struct cvitek_adc_priv),
};

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u-boot-2021.10/drivers/cvi_usb/Makefile Normal file
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obj-y := utask/cv181x/cvi_usb.o
obj-y += utask/cv181x/cps_cvi.o
obj-y += utask/cv181x/cvi_udc_otg.o
obj-y += utask/cv181x/cvi_udc_otg_xfer_dma.o
obj-y += utask/cv181x/usb_tty.o

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u-boot-2021.10/drivers/cvi_usb/utask/cv181x/cps_cvi.c Normal file
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#include <common.h>
#include <linux/types.h>
#include <stdlib.h>
#include <cpu_func.h>
/* see dps.h */
uint32_t cvi_uncached_read32(uint32_t *address)
{
return *address;
}
/* see dps.h */
void cvi_uncached_write32(uint32_t value, uint32_t *address)
{
*address = value;
}
/* see dps.h */
void cvi_buffer_copy(uint8_t *dst, uint8_t *src, uint32_t size)
{
memcpy((void *)dst, (void *)src, size);
}
/* Since this is a bare-metal system, with no MMU in place, we expect that there will be no cache enabled */
void cvi_cache_invalidate(uintptr_t address, size_t size)
{
#ifdef TENSILICA
xthal_dcache_region_invalidate(address, size);
#else
invalidate_dcache_range(address, address + ROUND(size, CONFIG_SYS_CACHELINE_SIZE));
#endif
}
void cvi_cache_flush(uintptr_t address, size_t size)
{
#ifdef TENSILICA
xthal_dcache_region_writeback(address, size);
#else
flush_dcache_range(address, address + ROUND(size, CONFIG_SYS_CACHELINE_SIZE));
#endif
}
void cvi_delay_ns(uint32_t ns)
{
}

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u-boot-2021.10/drivers/cvi_usb/utask/cv181x/cvi_udc_otg.c Normal file
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47
u-boot-2021.10/drivers/cvi_usb/utask/cv181x/cvi_usb.c Normal file
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/**********************************************************************
* main.c
*
* USB Core Driver
* main component function
***********************************************************************/
#include "include/debug.h"
#include "include/cvi_usb.h"
#include "include/platform_def.h"
#include <common.h>
#include <linux/delay.h>
#include <mmio.h>
#include <cpu_func.h>
extern int acm_app(void);
static void cvi_usb_hw_init(void)
{
uint32_t value;
value = mmio_read_32(TOP_BASE + REG_TOP_SOFT_RST) & (~BIT_TOP_SOFT_RST_USB);
mmio_write_32(TOP_BASE + REG_TOP_SOFT_RST, value);
udelay(50);
value = mmio_read_32(TOP_BASE + REG_TOP_SOFT_RST) | BIT_TOP_SOFT_RST_USB;
mmio_write_32(TOP_BASE + REG_TOP_SOFT_RST, value);
/* Set USB phy configuration */
value = mmio_read_32(REG_TOP_USB_PHY_CTRL);
mmio_write_32(REG_TOP_USB_PHY_CTRL, value | BIT_TOP_USB_PHY_CTRL_EXTVBUS
| USB_PHY_ID_OVERRIDE_ENABLE
| USB_PHY_ID_VALUE);
/* Enable ECO RXF */
// mmio_write_32(REG_TOP_USB_ECO, mmio_read_32(REG_TOP_USB_ECO) | BIT_TOP_USB_ECO_RX_FLUSH);
NOTICE("%s\n", __func__);
}
/* program starts here */
int cvi_usb_polling(void)
{
cvi_usb_hw_init();
acm_app();
return 0;
}

24
u-boot-2021.10/drivers/cvi_usb/utask/cv181x/include/big_endian.h Normal file
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#ifndef BYTEORDER_BENDIAN_H
#define BYTEORDER_BENDIAN_H
#include "swap.h"
#define cpuToLe32(x) ((uint32_t)swap32(x))
#define le32ToCpu(x) ((uint32_t)swap32(x))
#define cpuToLe16(x) ((uint16_t)swap16(x))
#define le16ToCpu(x) ((uint16_t)swap16(x))
#define cpuToBe32(x) (x)
#define be32ToCpu(x) (x)
#define cpuToBe16(x) (x)
#define be16ToCpu(x) (x)
/**
* Macros used for reading 16-bits and 32-bits data from memory which
* starting address could be unaligned.
*/
#define ptrToWord(ptr) ((*(uint8_t *)ptr) | (*((uint8_t *)(ptr + 1)) << 8))
#define ptrToDword(ptr) ((*(uint8_t *)ptr) | (*((uint8_t *)(ptr + 1)) << 8) | \
(*((uint8_t *)(ptr + 2)) << 16) | (*((uint8_t *)(ptr + 3)) << 24))
#endif /* BYTEORDER_BENDIAN_H */

12
u-boot-2021.10/drivers/cvi_usb/utask/cv181x/include/byteorder.h Normal file
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#ifndef BYTEORDER_H
#define BYTEORDER_H
#define CPU_LITTLE_ENDIAN
#ifdef CPU_LITTLE_ENDIAN
#include "little_endian.h"
#else
#include "big_endian.h"
#endif
#endif /* BYTEORDER_H */

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#ifndef CVI_CH9_H
#define CVI_CH9_H
#include "cvi_stdtypes.h"
#include "linux/bitops.h"
/** @defgroup ConfigInfo Configuration and Hardware Operation Information
* The following definitions specify the driver operation environment that
* is defined by hardware configuration or client code. These defines are
* located in the header file of the core driver.
* @{
*/
/**********************************************************************
* Defines
**********************************************************************
*/
/** Data transfer direction */
#define CH9_USB_DIR_HOST_TO_DEVICE 0
#define CH9_USB_DIR_DEVICE_TO_HOST BIT(7)
/** Type of request */
#define CH9_USB_REQ_TYPE_MASK (3 << 5)
#define CH9_USB_REQ_TYPE_STANDARD (0 << 5)
#define CH9_USB_REQ_TYPE_CLASS BIT(5)
#define CH9_USB_REQ_TYPE_VENDOR (2 << 5)
#define CH9_USB_REQ_TYPE_OTHER (3 << 5)
/** Recipient of request */
#define CH9_REQ_RECIPIENT_MASK 0x0f
#define CH9_USB_REQ_RECIPIENT_DEVICE 0
#define CH9_USB_REQ_RECIPIENT_INTERFACE 1
#define CH9_USB_REQ_RECIPIENT_ENDPOINT 2
#define CH9_USB_REQ_RECIPIENT_OTHER 3
/** Standard Request Code (chapter 9.4, Table 9-5 of USB Spec.) */
#define CH9_USB_REQ_GET_STATUS 0
#define CH9_USB_REQ_CLEAR_FEATURE 1
#define CH9_USB_REQ_SET_FEATURE 3
#define CH9_USB_REQ_SET_ADDRESS 5
#define CH9_USB_REQ_GET_DESCRIPTOR 6
#define CH9_USB_REQ_SET_DESCRIPTOR 7
#define CH9_USB_REQ_GET_CONFIGURATION 8
#define CH9_USB_REQ_SET_CONFIGURATION 9
#define CH9_USB_REQ_GET_INTERFACE 10
#define CH9_USB_REQ_SET_INTERFACE 11
#define CH9_USB_REQ_SYNCH_FRAME 12
#define CH9_USB_REQ_SET_ENCRYPTION 13
#define CH9_USB_REQ_GET_ENCRYPTION 14
#define CH9_USB_REQ_SET_HANDSHAKE 15
#define CH9_USB_REQ_GET_HANDSHAKE 16
#define CH9_USB_REQ_SET_CONNECTION 17
#define CH9_USB_REQ_SET_SCURITY_DATA 18
#define CH9_USB_REQ_GET_SCURITY_DATA 19
#define CH9_USB_REQ_SET_WUSB_DATA 20
#define CH9_USB_REQ_LOOPBACK_DATA_WRITE 21
#define CH9_USB_REQ_LOOPBACK_DATA_READ 22
#define CH9_USB_REQ_SET_INTERFACE_DS 23
#define CH9_USB_REQ_CVI_ENTER_DL 66
#define CH9_USB_REQ_SET_SEL 48
#define CH9_USB_REQ_ISOCH_DELAY 49
/** Standard Descriptor Types (chapter 9.4 - Table 9-6 of USB Spec.) */
#define CH9_USB_DT_DEVICE 1
#define CH9_USB_DT_CONFIGURATION 2
#define CH9_USB_DT_STRING 3
#define CH9_USB_DT_INTERFACE 4
#define CH9_USB_DT_ENDPOINT 5
#define CH9_USB_DT_DEVICE_QUALIFIER 6
/** USB 2 */
#define CH9_USB_DT_OTHER_SPEED_CONFIGURATION 7
/** USB 2 */
#define CH9_USB_DT_INTERFACE_POWER 8
#define CH9_USB_DT_OTG 9
#define CH9_USB_DT_DEBUG 10
#define CH9_USB_DT_INTERFACE_ASSOCIATION 11
#define CH9_USB_DT_BOS 15
#define CH9_USB_DT_DEVICE_CAPABILITY 16
#define CH9_USB_DT_SS_USB_ENDPOINT_COMPANION 48
#define CH9_USB_DT_SS_PLUS_ISOCHRONOUS_ENDPOINT_COMPANION 49
#define CH9_USB_DT_OTG 9
/** Descriptor size */
#define CH9_USB_DS_DEVICE 18
#define CH9_USB_DS_BOS 5
#define CH9_USB_DS_DEVICE_ACM 12
/** Capability type: USB 2.0 EXTENSION */
#define CH9_USB_DS_DEVICE_CAPABILITY_20 7
/** Capability type: SUPERSPEED_USB */
#define CH9_USB_DS_DEVICE_CAPABILITY_30 10
/** Capability type: CONTAINER_ID */
#define CH9_USB_DS_DEVICE_CAPABILITY_CONTAINER_ID 21
/** Capability type: Capability type: PRECISION_TIME_MEASUREMENT */
#define CH9_USB_DS_DEVICE_CAPABILITY_PRECISION_TIME_MEASUREMENT 4
#define CH9_USB_DS_CONFIGURATION 9
#define CH9_USB_DS_INTERFACE_ASSOCIATION 8
#define CH9_USB_DS_SS_USB_ENDPOINT_COMPANION 6
#define CH9_USB_DS_SS_PLUS_ISOCHRONOUS_ENDPOINT_COMPANION 8
#define CH9_USB_DS_INTERFACE 9
#define CH9_USB_DS_ENDPOINT 7
#define CH9_USB_DS_STRING 3
#define CH9_USB_DS_OTG 5
/** USB2 */
#define CH9_USB_DS_DEVICE_QUALIFIER 10
/** USB2 */
#define CH9_USB_DS_OTHER_SPEED_CONFIGURATION 7
#define CH9_USB_DS_INTERFACE_POWER 8
/** Standard Feature Selectors (chapter 9.4, Table 9-7 of USB Spec) */
#define CH9_USB_FS_ENDPOINT_HALT 0
#define CH9_USB_FS_FUNCTION_SUSPEND 0
#define CH9_USB_FS_DEVICE_REMOTE_WAKEUP 1
#define CH9_USB_FS_TEST_MODE 2
#define CH9_USB_FS_B_HNP_ENABLE 3
#define CH9_USB_FS_A_HNP_SUPPORT 4
#define CH9_USB_FS_A_ALT_HNP_SUPPORT 5
#define CH9_USB_FS_WUSB_DEVICE 6
#define CH9_USB_FS_U1_ENABLE 48
#define CH9_USB_FS_U2_ENABLE 49
#define CH9_USB_FS_LTM_ENABLE 50
#define CH9_USB_FS_B3_NTF_HOST_REL 51
#define CH9_USB_FS_B3_RESP_ENABLE 52
#define CH9_USB_FS_LDM_ENABLE 53
/** Recipient Device (Figure 9-4 of USB Spec) */
#define CH9_USB_STATUS_DEV_SELF_POWERED BIT(0)
#define CH9_USB_STATUS_DEV_REMOTE_WAKEUP BIT(1)
#define CH9_USB_STATUS_DEV_U1_ENABLE BIT(2)
#define CH9_USB_STATUS_DEV_U2_ENABLE BIT(3)
#define CH9_USB_STATUS_DEV_LTM_ENABLE BIT(4)
/** Recipient Interface (Figure 9-5 of USB Spec) */
#define CH9_USB_STATUS_INT_REMOTE_WAKE_CAPABLE BIT(0)
#define CH9_USB_STATUS_INT_REMOTE_WAKEUP BIT(1)
/** Recipient Endpoint (Figure 9-6 of USB Spec) */
#define CH9_USB_STATUS_EP_HALT BIT(1)
/** Recipient Endpoint - PTM GetStatus Request(Figure 9-7 of USB Spec) */
#define CH9_USB_STATUS_EP_PTM_ENABLE BIT(0)
#define CH9_USB_STATUS_EP_PTM_VALID BIT(1)
#define CH9_USB_STATUS_EP_PTM_LINK_DELAY_OFFSET (16)
#define CH9_USB_STATUS_EP_PTM_LINK_DELAY_MASK (0xFFFF << 16)
/**
* Macros describing information for SetFeauture Request and FUNCTION_SUSPEND selector
* (chapter 9.4.9, Table 9-9 of USB Spec)
*/
#define CH9_USB_SF_LOW_POWER_SUSPEND_STATE 0x1
#define CH9_USB_SF_REMOTE_WAKE_ENABLED 0x2
/**
* Standard Class Code defined by usb.org
* (link: http://www.usb.org/developers/defined_class)
*/
#define CH9_USB_CLASS_INTERFACE 0x0
#define CH9_USB_CLASS_AUDIO 0x01
#define CH9_USB_CLASS_CDC 0x02
#define CH9_USB_CLASS_COMMUNICATION 0x01
#define CH9_USB_CLASS_HID 0x03
#define CH9_USB_CLASS_PHYSICAL 0x05
#define CH9_USB_CLASS_IMAGE 0x06
#define CH9_USB_CLASS_PRINTER 0x07
#define CH9_USB_CLASS_MASS_STORAGE 0x08
#define CH9_USB_CLASS_HUB 0x09
#define CH9_USB_CLASS_CDC_DATA 0x0A
#define CH9_USB_CLASS_SMART_CARD 0x0B
#define CH9_USB_CLASS_CONTENT_SEECURITY 0x0D
#define CH9_USB_CLASS_VIDEO 0x0E
#define CH9_USB_CLASS_HEALTHCARE 0x0F
#define CH9_USB_CLASS_AUDIO_VIDEO 0x10
#define CH9_USB_CLASS_DIAGNOSTIC 0xDC
#define CH9_USB_CLASS_WIRELESS 0xE0
#define CH9_USB_CLASS_MISCELLANEOUS 0xEF
#define CH9_USB_CLASS_APPLICATION 0xFE
#define CH9_USB_CLASS_VENDOR 0xFF
/** Device Capability Types Codes (see Table 9-14 of USB Spec 3.1 */
#define CH9_USB_DCT_WIRELESS_USB 0x01
#define CH9_USB_DCT_USB20_EXTENSION 0x02
#define CH9_USB_DCT_SS_USB 0x03
#define CH9_USB_DCT_CONTAINER_ID 0x04
#define CH9_USB_DCT_PLATFORM 0x05
#define CH9_USB_DCT_POWER_DELIVERY_CAPABILITY 0x06
#define CH9_USB_DCT_BATTERY_INFO_CAPABILITY 0x07
#define CH9_USB_DCT_PD_CONSUMER_PORT_CAPABILITY 0x08
#define CH9_USB_DCT_PD_PROVIDER_PORT_CAPABILITY 0x09
#define CH9_USB_DCT_SS_PLUS 0x0A
#define CH9_USB_DCT_PRECISION_TIME_MEASUREMENT 0x0B
#define CH9_USB_DCT_WIRELESS_USB_EXT 0x0C
/** Describe supports LPM defined in bmAttribues field of CUSBD_Usb20ExtensionDescriptor */
#define CH9_USB_USB20_EXT_LPM_SUPPORT BIT(1)
#define CH9_USB_USB20_EXT_BESL_AND_ALTERNATE_HIRD BIT(2)
/**
* Describe supports LTM defined in bmAttribues field
* of CUSBD_UsbSuperSpeedDeviceCapabilityDescriptor
*/
#define CH9_USB_SS_CAP_LTM BIT(1)
/**
* Describe speed supported defined in wSpeedSupported field
* of CUSBD_UsbSuperSpeedDeviceCapabilityDescriptor
*/
#define CH9_USB_SS_CAP_SUPPORT_LS BIT(0)
#define CH9_USB_SS_CAP_SUPPORT_FS BIT(1)
#define CH9_USB_SS_CAP_SUPPORT_HS BIT(2)
#define CH9_USB_SS_CAP_SUPPORT_SS BIT(3)
/** Describe encoding of bmSublinkSpeedAttr0 filed from CUSBD_UsbSuperSpeedPlusDescriptor */
#define CH9_USB_SSP_SID_OFFSET 0
#define CH9_USB_SSP_SID_MASK 0 0x0000000f
#define CH9_USB_SSP_LSE_OFFSET 4
#define CH9_USB_SSP_LSE_MASK (0x00000003 << CUSBD_USB_SSP_LSE_OFFSET)
#define CH9_USB_SSP_ST_OFFSET 6
#define CH9_USB_SSP_ST_MASK (0x00000003 << CUSBD_USB_SSP_ST_OFFSET)
#define CH9_USB_SSP_LP_OFFSET 14
#define CH9_USB_SSP_LP_MASK (0x00000003 << CUSBD_USB_SSP_LP_OFFSET)
#define CH9_USB_SSP_LSM_OFFSET 16
#define CH9_USB_SSP_LSM_MASK (0x0000FFFF << CUSBD_USB_SSP_LSM_OFFSET)
/** Description of bmAttributes field from Configuration Description */
#define CH9_USB_CONFIG_RESERVED BIT(7)
/** Self Powered */
#define CH9_USB_CONFIG_SELF_POWERED BIT(6)
#define CH9_USB_CONFIG_BUS_POWERED BIT(7)
/** Remote Wakeup */
#define CH9_USB_CONFIG_REMOTE_WAKEUP BIT(5)
/** Definitions for bEndpointAddress field from Endpoint descriptor */
#define CH9_USB_EP_DIR_MASK 0x80
#define CH9_USB_EP_DIR_IN 0x80
#define CH9_USB_EP_NUMBER_MASK 0x0f
/** Endpoint attributes from Endpoint descriptor - bmAttributes field */
#define CH9_USB_EP_TRANSFER_MASK 0x03
#define CH9_USB_EP_CONTROL 0x0
#define CH9_USB_EP_ISOCHRONOUS 0x01
#define CH9_USB_EP_BULK 0x02
#define CH9_USB_EP_INTERRUPT 0x03
/** Synchronization types for ISOCHRONOUS endpoints */
#define CH9_USB_EP_SYNC_MASK 0xC
#define CH9_USB_EP_SYNC_NO (0x00 >> 2)
#define CH9_USB_EP_SYNC_ASYNCHRONOUS (0x1 >> 2)
#define CH9_USB_EP_SYNC_ADAPTIVE (0x02 >> 2)
#define CH9_USB_EP_SYNC_SYNCHRONOUS (0x03 >> 2)
#define CH9_USB_EP_USAGE_MASK (0x3 >> 4)
/** Usage types for ISOCHRONOUS endpoints */
#define CH9_USB_EP_USAGE_DATA (00 >> 4)
#define CH9_USB_EP_USAGE_FEEDBACK (0x01 >> 4)
#define CH9_USB_EP_USAGE_IMPLICIT_FEEDBACK (0x02 >> 4)
/** Usage types for INTERRUPTS endpoints */
#define CH9_USB_EP_USAGE_PERIODIC (00 >> 4)
#define CH9_USB_EP_USAGE_NOTIFICATION (0x01 >> 4)
/** Description of fields bmAttributes from OTG descriptor */
#define CH9_USB_OTG_ADP_MASK 0x4
#define CH9_USB_OTG_HNP_MASK 0x2
#define CH9_USB_OTG_SRP_MASK 0x1
/**
* Test Mode Selectors
* See USB 2.0 spec Table 9-7
*/
#define CH9_TEST_J 1
#define CH9_TEST_K 2
#define CH9_TEST_SE0_NAK 3
#define CH9_TEST_PACKET 4
#define CH9_TEST_FORCE_EN 5
#define CH9_MAX_PACKET_SIZE_MASK 0x7ff
#define CH9_PACKET_PER_FRAME_SHIFT 11
/**
* OTG status selector
* See USB_OTG_AND_EH_2-0 spec Table 6-4
*/
#define CH9_OTG_STATUS_SELECTOR 0xF000
/**
* @}
*/
/* Conventional codes for class-specific descriptors. The convention is
* defined in the USB "Common Class" Spec (3.11). Individual class specs
* are authoritative for their usage, not the "common class" writeup.
*/
#define USB_DT_CS_DEVICE (CH9_USB_REQ_TYPE_CLASS | CH9_USB_DT_DEVICE)
#define USB_DT_CS_CONFIG (CH9_USB_REQ_TYPE_CLASS | CH9_USB_DT_CONFIG)
#define USB_DT_CS_STRING (CH9_USB_REQ_TYPE_CLASS | CH9_USB_DT_STRING)
#define USB_DT_CS_INTERFACE (CH9_USB_REQ_TYPE_CLASS | CH9_USB_DT_INTERFACE)
#define USB_DT_CS_ENDPOINT (CH9_USB_REQ_TYPE_CLASS | CH9_USB_DT_ENDPOINT)
/** @defgroup DataStructure Dynamic Data Structures
* This section defines the data structures used by the driver to provide
* hardware information, modification and dynamic operation of the driver.
* These data structures are defined in the header file of the core driver
* and utilized by the API.
* @{
*/
/**********************************************************************
* Forward declarations
**********************************************************************/
struct CH9_UsbSetup;
struct CH9_UsbDeviceDescriptor;
struct CH9_UsbBosDescriptor;
struct CH9_UsbCapabilityDescriptor;
struct CH9_Usb20ExtensionDescriptor;
struct CH9_UsbSSDeviceCapabilityDescriptor;
struct CH9_UsbContainerIdDescriptor;
struct CH9_UsbPlatformDescriptor;
struct CH9_UsbSSPlusDescriptor;
struct CH9_UsbPTMCapabilityDescriptor;
struct CH9_UsbConfigurationDescriptor;
struct CH9_UsbInterfaceAssociationDescriptor;
struct CH9_UsbInterfaceDescriptor;
struct CH9_UsbEndpointDescriptor;
struct CH9_UsbSSEndpointCompanionDescriptor;
struct CH9_UsbSSPlusIsocEndpointCompanionDescriptor;
struct CH9_UsbStringDescriptor;
struct CH9_UsbDeviceQualifierDescriptor;
struct CH9_UsbOtherSpeedConfigurationDescriptor;
struct CH9_UsbHeaderDescriptor;
struct CH9_UsbOtgDescriptor;
struct CH9_ConfigParams;
/**********************************************************************
* Enumerations
**********************************************************************/
/** USB States defined in USB Specification */
typedef enum {
/** Device not attached yet */
CH9_USB_STATE_NONE = 0,
/** see Figure 9-1 of USB Spec */
CH9_USB_STATE_ATTACHED = 1,
CH9_USB_STATE_POWERED = 2,
CH9_USB_STATE_DEFAULT = 3,
CH9_USB_STATE_ADDRESS = 4,
CH9_USB_STATE_CONFIGURED = 5,
CH9_USB_STATE_SUSPENDED = 6,
CH9_USB_STATE_ERROR = 7,
} CH9_UsbState;
/** Speeds defined in USB Specification */
typedef enum {
/** unknown speed - before enumeration */
CH9_USB_SPEED_UNKNOWN = 0,
/** (1,5Mb/s) */
CH9_USB_SPEED_LOW = 1,
/** usb 1.1 (12Mb/s) */
CH9_USB_SPEED_FULL = 2,
/** usb 2.0 (480Mb/s) */
CH9_USB_SPEED_HIGH = 3,
/** usb 2.5 wireless */
CH9_USB_SPEED_WIRELESS = 4,
/** usb 3.0 GEN 1 (5Gb/s) */
CH9_USB_SPEED_SUPER = 5,
/** usb 3.1 GEN2 (10Gb/s) */
CH9_USB_SPEED_SUPER_PLUS = 6,
} CH9_UsbSpeed;
/**********************************************************************
* Structures and unions
*********************************************************************
*/
/** Structure describes USB request (SETUP packet). See USB Specification (chapter 9.3) */
typedef struct CH9_UsbSetup {
/** Characteristics of request */
uint8_t bmRequestType;
/** Specific request */
uint8_t bRequest;
/** Field that varies according to request */
uint16_t wValue;
/** typically used to pass an index or offset. */
uint16_t wIndex;
/** Number of bytes to transfer if there is a data stage */
uint16_t wLength;
} __packed CH9_UsbSetup;
/** Standard Device Descriptor (see Table 9-11 of USB Spec 3.1) */
typedef struct CH9_UsbDeviceDescriptor {
/** Size of descriptor */
uint8_t bLength;
/** Device descriptor type */
uint8_t bDescriptorType;
/** USB Specification Release Number */
uint16_t bcdUSB;
/** Class code (assigned by the USB-IF) */
uint8_t bDeviceClass;
/** Subclass code (assigned by the USB-IF */
uint8_t bDeviceSubClass;
/** Protocol code (assigned by the USB-IF */
uint8_t bDeviceProtocol;
/** Maximum packet size for endpoint zero */
uint8_t bMaxPacketSize0;
/** Vendor ID (assigned by the USB-IF */
uint16_t idVendor;
/** Product ID (assigned by manufacturer) */
uint16_t idProduct;
/** Device release number */
uint16_t bcdDevice;
/** Index of string descriptor describing manufacturer */
uint8_t iManufacturer;
/** Index of string descriptor describing product */
uint8_t iProduct;
/** Index of string descriptor for serial number */
uint8_t iSerialNumber;
/** Number of possible configurations */
uint8_t bNumConfigurations;
} __packed CH9_UsbDeviceDescriptor;
/** Binary Device Object Store descriptor (see Table 9-12 of USB Spec 3.1) */
typedef struct CH9_UsbBosDescriptor {
/** Size of this descriptor */
uint8_t bLength;
/** Descriptor type: BOS */
uint8_t bDescriptorType;
/** Length of this descriptor and all of its sub descriptors */
uint16_t wTotalLength;
/** The number of separate device capability descriptors in the BOS */
uint8_t bNumDeviceCaps;
} __packed CH9_UsbBosDescriptor;
/** Device Capability Descriptor (see Table 9-12 of USB Spec 3.1) */
typedef struct CH9_UsbCapabilityDescriptor {
/** Size of this descriptor */
uint8_t bLength;
/** Descriptor type: DEVICE CAPABILITY type */
uint8_t bDescriptorType;
/** Capability type: USB 2.0 EXTENSION (002h) */
uint8_t bDevCapabilityType;
/** Capability specific format */
uint32_t bmAttributes;
} __packed CH9_UsbCapabilityDescriptor;
/** USB 2.0 Extension Descriptor (see Table 9-15 of USB Spec 3.1) */
typedef struct CH9_Usb20ExtensionDescriptor {
/** Size of this descriptor */
uint8_t bLength;
/** Descriptor type: DEVICE CAPABILITY type */
uint8_t bDescriptorType;
/** Capability type: USB 2.0 EXTENSION (002h) */
uint8_t bDevCapabilityType;
/** Capability specific format */
uint32_t bmAttributes;
} __packed CH9_Usb20ExtensionDescriptor;
/** SuperSpeed USB Device Capability Descriptor (see Table 9-16 of USB Spec 3.1) */
typedef struct CH9_UsbSSDeviceCapabilityDescriptor {
/** Size of this descriptor */
uint8_t bLength;
/** DEVICE CAPABILITY Descriptor type */
uint8_t bDescriptorType;
/** Capability type: SUPERSPEED_USB */
uint8_t bDevCapabilityType;
/** Bitmap encoding of supported device level features */
uint8_t bmAttributes;
/** Bitmap encoding of the speed supported by device */
uint16_t wSpeedSupported;
/**
* The lowest speed at which all the functionality
* supported by the device is available to the user
*/
uint8_t vFunctionalitySupport;
/** U1 Device Exit Latency */
uint8_t bU1DevExitLat;
/** U2 Device Exit Latency */
uint16_t bU2DevExitLat;
} __packed CH9_UsbSSDeviceCapabilityDescriptor;
/** Container ID Descriptor (see Table 9-17 of USB Spec 3.1) */
typedef struct CH9_UsbContainerIdDescriptor {
/** Size of this descriptor */
uint8_t bLength;
/** DEVICE CAPABILITY Descriptor type */
uint8_t bDescriptorType;
/** Capability type: CONTAINER_ID */
uint8_t bDevCapabilityType;
/** Field reserved and shall be set to zero */
uint8_t bReserved;
/** unique number to device instance */
uint8_t ContainerId[16];
} __packed CH9_UsbContainerIdDescriptor;
typedef struct CH9_UsbPlatformDescriptor {
/** Size of this descriptor */
uint8_t bLength;
/** DEVICE CAPABILITY Descriptor type */
uint8_t bDescriptorType;
/** Capability type: PLATFORM */
uint8_t bDevCapabilityType;
/** Field reserved and shall be set to zero */
uint8_t bReserved;
/** unique number to identifies a platform */
uint8_t PlatformCapabilityUUID[16];
/** variable length */
uint8_t CapabilityData[0];
} __packed CH9_UsbPlatformDescriptor;
/** SuperSpeedPlus USB Device Capability (see Table 9-19 of USB Spec 3.1) */
typedef struct CH9_UsbSSPlusDescriptor {
/** Size of this descriptor */
uint8_t bLength;
/** DEVICE CAPABILITY Descriptor type */
uint8_t bDescriptorType;
/** Capability type: SUPERSPEED_PLUS */
uint8_t bDevCapabilityType;
/** Field reserved and shall be set to zero */
uint8_t bReserved;
/** Bitmap encoding of supported SuperSpeedPlus features */
uint32_t bmAttributes;
/** supported functionality */
uint16_t wFunctionalitySupport;
/** Reserved. Shall be set to zero */
uint16_t wReserved;
/** Sublink Speed Attribute */
uint32_t bmSublinkSpeedAttr0;
/** Additional Lane Speed Attributes */
uint32_t bmSublinkSpeedAttrSSAC;
} __packed CH9_UsbSSPlusDescriptor;
/** SuperSpeedPlus USB Device Capability (see Table 9-19 of USB Spec 3.1) */
typedef struct CH9_UsbPTMCapabilityDescriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bDevCapabilityType;
} __packed CH9_UsbPTMCapabilityDescriptor;
/** Standard Configuration Descriptor (see Table 9-21 of USB Spec 3.1) */
typedef struct CH9_UsbConfigurationDescriptor {
/** Size of descriptor */
uint8_t bLength;
/** Configuration descriptor type */
uint8_t bDescriptorType;
/** Total length of configuration */
uint16_t wTotalLength;
/** Number of interfaces supported by configuration */
uint8_t bNumInterfaces;
/** Value use as an argument to SetConfiguration() request */
uint8_t bConfigurationValue;
/** Index of string descriptor describing this configuration */
uint8_t iConfiguration;
/** Configuration attributes */
uint8_t bmAttributes;
/** Maximum power consumption of the USB device */
uint8_t bMaxPower;
} __packed CH9_UsbConfigurationDescriptor;
/** Standard Interface Association Descriptor (see Table 9-22 of USB Spec 3.1) */
typedef struct CH9_UsbInterfaceAssociationDescriptor {
/** Size of descriptor */
uint8_t bLength;
/** Interface Association Descriptor Type */
uint8_t bDescriptorType;
/** interface number of this interface that is associated with this function */
uint8_t bFirstInterface;
/** Number of contiguous interfaces that are associated with this function */
uint8_t bInterfaceCount;
/** Class code assigned by USB-IF */
uint8_t bFunctionClass;
/** Subclass code */
uint8_t bFunctionSubClass;
/** Protocol code */
uint8_t bFunctionProtocol;
/** Index of string descriptor describing this function */
uint8_t iFunction;
} __packed CH9_UsbInterfaceAssociationDescriptor;
/** Standard Interface Descriptor (see Table 9-23 of USB Spec 3.1) */
typedef struct CH9_UsbInterfaceDescriptor {
/** Size of descriptor */
uint8_t bLength;
/** Interface Descriptor Type */
uint8_t bDescriptorType;
/** Number of this interface */
uint8_t bInterfaceNumber;
/** Value used to select this alternate setting */
uint8_t bAlternateSetting;
/** Class code */
uint8_t bNumEndpoints;
/** Subclass code */
uint8_t bInterfaceClass;
/** Subclass code */
uint8_t bInterfaceSubClass;
/** Protocol code */
uint8_t bInterfaceProtocol;
/** Index of string */
uint8_t iInterface;
} __packed CH9_UsbInterfaceDescriptor;
#define USB_DT_INTERFACE_SIZE 9
#define USB_DIR_OUT 0 /* to device */
#define USB_DIR_IN 0x80 /* to host */
/** Standard Endpoint Descriptor */
typedef struct CH9_UsbEndpointDescriptor {
/** Size of descriptor */
uint8_t bLength;
/** Endpoint Descriptor Type */
uint8_t bDescriptorType;
/** The address of the endpoint */
uint8_t bEndpointAddress;
/** Endpoint attribute */
uint8_t bmAttributes;
/** Maximum packet size for this endpoint */
uint16_t wMaxPacketSize;
/** interval for polling endpoint data transfer */
uint8_t bInterval;
} __packed CH9_UsbEndpointDescriptor;
#define USB_DT_ENDPOINT_SIZE 7
#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */
/** Standard SuperSpeed Endpoint Companion Descriptor (see Table 9-26 of USB Spec 3.1) */
typedef struct CH9_UsbSSEndpointCompanionDescriptor {
/** Size of descriptor in bytes */
uint8_t bLength;
/** SUPERSPEED_USB_ENDPOINT_COMPANION Descriptor types */
uint8_t bDescriptorType;
/** Number of packets that endpoint can transmit as part of burst */
uint8_t bMaxBurst;
uint8_t bmAttributes;
/** The total number of bytes for every service interval */
uint16_t wBytesPerInterval;
} __packed CH9_UsbSSEndpointCompanionDescriptor;
/**
* Standard SuperSpeedPlus Isochronous Endpoint
* Companion Descriptor (see Table 9-27 of USB Spec 3.1)
*/
typedef struct CH9_UsbSSPlusIsocEndpointCompanionDescriptor {
/** Size of descriptor in bytes */
uint8_t bLength;
/** SUPERSPEEDPLUS_ISOCHRONOUS_ENDPOINT_COMPANION Descriptor types */
uint8_t bDescriptorType;
/** Reserved. Shall be set to zero */
uint16_t wReserved;
/** The total number of bytes for every service interval */
uint32_t dwBytesPerInterval;
} __packed CH9_UsbSSPlusIsocEndpointCompanionDescriptor;
/** Standard String Descriptor */
typedef struct CH9_UsbStringDescriptor {
/** Size of descriptor */
uint8_t bLength;
/** STRING Descriptor Type */
uint8_t bDescriptorType;
/** UNICODE encoded string */
uint8_t *bString;
} __packed CH9_UsbStringDescriptor;
/** Standard Device Qualifier Descriptor (see Table 9-9 of USB Spec 2.0) */
typedef struct CH9_UsbDeviceQualifierDescriptor {
/** Size of descriptor */
uint8_t bLength;
/** Device Qualifier type */
uint8_t bDescriptorType;
/** USB Specification version number */
uint16_t bcdUSB;
/** Class code */
uint8_t bDeviceClass;
/** Subclass code */
uint8_t bDeviceSubClass;
/** Protocol code */
uint8_t bDeviceProtocol;
/** Maximum packet size for other speed */
uint8_t bMaxPacketSize0;
/** Number of other speed configuration */
uint8_t bNumConfigurations;
/** Reserved for future use */
uint8_t bReserved;
} __packed CH9_UsbDeviceQualifierDescriptor;
/** Standard Other_Speed_Configuration descriptor (see Table 9-11 of USB Spec 2.0) */
typedef struct CH9_UsbOtherSpeedConfigurationDescriptor {
/** Size of descriptor */
uint8_t bLength;
/** Configuration descriptor type */
uint8_t bDescriptorType;
/** Total length of configuration */
uint16_t wTotalLength;
/** Number of interfaces supported by this speed configuration */
uint8_t bNumInterfaces;
/** Value to use to select configuration */
uint8_t bConfigurationValue;
/** Index of string descriptor describing this configuration */
uint8_t iConfiguration;
/** Configuration attributes */
uint8_t bmAttributes;
/** Maximum power consumption of the USB device */
uint8_t bMaxPower;
} __packed CH9_UsbOtherSpeedConfigurationDescriptor;
/**
* Header descriptor. All descriptor have the same header that
* consist of bLength and bDescriptorType fields
*/
typedef struct CH9_UsbHeaderDescriptor {
/** Size of descriptor */
uint8_t bLength;
/** descriptor Type */
uint8_t bDescriptorType;
} __packed CH9_UsbHeaderDescriptor;
/** OTG descriptor (see OTG spec. Table 6.1) */
typedef struct CH9_UsbOtgDescriptor {
/** Size of descriptor */
uint8_t bLength;
/** OTG Descriptor Type */
uint8_t bDescriptorType;
/** Attribute field */
uint8_t bmAttributes;
/** OTG and EH supplement release number */
uint16_t bcdOTG;
} __packed CH9_UsbOtgDescriptor;
typedef struct CH9_ConfigParams {
/** U1 Device exit Latency */
uint8_t bU1devExitLat;
/** U2 Device exit Latency */
uint16_t bU2DevExitLat;
} __packed CH9_ConfigParams;
/**
* @}
*/
#endif /* CVI_CH9_H */

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