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build: version release v4.1.5

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[coredump]: add coredump config for cv180x/cv181x
[sensor]: add sensor sc035hgs&sc035hgs_1l
[feat](build): del cv182x/cv183x/athena2 dir
[sensor] add sc2336_slave [sensor] add sc2331_slave
[feat] add cvi_update_rtos tool
[feat](Sensor): Add support for sensor SC2336P_1L.
[board] add cv1810c_wevb_0006a_spinand board
[sensor] add new sensor sc223a config

Change-Id: I320322d4cb91a586de6ba2f65c7319f109312aca
This commit is contained in:
forum_service
2023-12-18 13:46:46 +08:00
committed by carbon
parent 213c880673
commit c313eb2192
807 changed files with 433 additions and 90109 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
build/Kconfig
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@ -559,18 +559,47 @@ config FAST_IMAGE_TYPE
E_FAST_H264 : 2
E_FAST_H265 : 3
config ENABLE_ALIOS
bool "Enable ALIOS"
default n
choice
prompt "Alios source selection"
default DISABLE_ALIOS
config DISABLE_ALIOS
bool "disable alios"
help
Disable alios update tool
We usually choose this configuration
This configuration is required to compile the boot kernel uboot
This configuration does not support alios upgrades
config ENABLE_ALIOS_UPDATE
bool "mars/phobos alios update"
help
Enable alios update tool
We don't usually choose this configuration
This configuration is required to compile the tools that update mars/phobos alios
This configuration does not support booting the kernel
config ENABLE_ALIOS
bool "mercury alios"
help
Enable mercury alios update tool
We don't usually choose this configuration
This configuration is required to compile the tools that update mercury alios
This configuration does not support booting the kernel
endchoice
config ALIOS_SOURCE
string
default "mars_alios" if ENABLE_ALIOS_UPDATE
default "alios" if ENABLE_ALIOS
default "" if DISABLE_ALIOS
help
Enable alios.
Select build alios source.
config ALIOS_SOLUTION
string "Select alios solution"
default "cv182x_helloworld"
depends on ENABLE_ALIOS
string
default "helloworld" if ENABLE_ALIOS_UPDATE
default "cv182x_helloworld" if ENABLE_ALIOS
default "" if DISABLE_ALIOS
help
Select solution to build alios.
Select solution to build alios.
endmenu

15
build/boards/chip_list.json
View File

@ -1,20 +1,9 @@
{
"cv183x": {
"cv183x": ["cv1829", "cv1832", "cv1835", "cv1838"],
"cv952x": ["cv9520"],
"cv75x1": ["cv7581"]
},
"cv182x": {
"cv182x": ["cv1820", "cv1821", "cv1822", "cv1823", "cv1825", "cv1826"],
"cv73x7": ["cv7327", "cv7357"]
},
"cv181x": {
"cv181x": ["cv181x", "cv1823a", "cv1821a", "cv1820a", "cv1811h", "cv1811c", "cv1810c", "cv1810h", "cv1812cp", "cv1812h", "cv1813h"]
"cv181x": ["cv181x", "cv1811h", "cv1811c", "cv1810c", "cv1810h", "cv1812cp", "cv1812h", "cv1813h"]
},
"cv180x": {
"cv180x": ["cv180x", "cv1800b", "cv1800c", "cv1801b", "cv1801c", "cv180zb"]
}
}
}

3
build/boards/cv180x/cv1800b_sophpi_duo_sd/linux/cvitek_cv1800b_sophpi_duo_sd_defconfig
View File

@ -260,3 +260,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv180x/cv1800b_wdmb_0008a_spinor/linux/cvitek_cv1800b_wdmb_0008a_spinor_defconfig
View File

@ -225,3 +225,6 @@ CONFIG_DEBUG_FS=y
# CONFIG_RCU_TRACE is not set
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv180x/cv1800b_wevb_0008a_spinor/linux/cvitek_cv1800b_wevb_0008a_spinor_defconfig
View File

@ -217,3 +217,6 @@ CONFIG_DEBUG_FS=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_USB_STORAGE=y
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv180x/cv1800c_wevb_0009a_spinor/linux/cvitek_cv1800c_wevb_0009a_spinor_defconfig
View File

@ -211,3 +211,6 @@ CONFIG_DEBUG_FS=y
# CONFIG_RCU_TRACE is not set
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv180x/cv1801b_wevb_0008a_spinor/linux/cvitek_cv1801b_wevb_0008a_spinor_defconfig
View File

@ -371,3 +371,6 @@ CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv180x/cv1801c_wdmb_0009a_spinor/linux/cvitek_cv1801c_wdmb_0009a_spinor_defconfig
View File

@ -387,3 +387,6 @@ CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv180x/cv1801c_wevb_0009a_spinand/linux/cvitek_cv1801c_wevb_0009a_spinand_defconfig
View File

@ -458,3 +458,6 @@ CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv180x/cv1801c_wevb_0009a_spinor/linux/cvitek_cv1801c_wevb_0009a_spinor_defconfig
View File

@ -372,3 +372,6 @@ CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

6
build/boards/cv180x/cv180x_fpga/config.json
View File

@ -1,6 +0,0 @@
{
"ddr_cfg_list": [
""
],
"board_information": "FPGA"
}

21
build/boards/cv180x/cv180x_fpga/cv180x_fpga_defconfig
View File

@ -1,21 +0,0 @@
CONFIG_CHIP_cv180x=y
CONFIG_ARCH="riscv"
CONFIG_CROSS_COMPILE="riscv64-unknown-linux-gnu-"
CONFIG_KERNEL_ENTRY_HACK=y
CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80200000"
CONFIG_TOOLCHAIN_GLIBC_RISCV64=y
CONFIG_BOOT_IMAGE_SINGLE_DTB=y
CONFIG_SENSOR_SONY_IMX327_FPGA=y
CONFIG_MIPI_PANEL_ILI9881C=y
CONFIG_UBOOT_2021_10=y
CONFIG_KERNEL_SRC_5.10=y
# CONFIG_ROOTFS_OVERLAYFS is not set
# CONFIG_TARGET_PACKAGE_CVITRACER is not set
# CONFIG_TARGET_PACKAGE_GDBSERVER is not set
# CONFIG_TARGET_PACKAGE_LIBCRYPTO is not set
# CONFIG_TARGET_PACKAGE_LIBZ is not set
# CONFIG_TARGET_PACKAGE_OTASERVER is not set
# CONFIG_TARGET_PACKAGE_RSYSLOG is not set
# CONFIG_TARGET_PACKAGE_CRONTABS is not set
# CONFIG_TARGET_PACKAGE_GATORD is not set
# CONFIG_ENABLE_FREERTOS is not set

16
build/boards/cv180x/cv180x_fpga/dts_riscv/cv180x_fpga.dts
View File

@ -1,16 +0,0 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_bga.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
/ {
};
&sd {
no-1-8-v;
src-frequency = <25000000>;
min-frequency = <400000>;
max-frequency = <12000000>;
};

407
build/boards/cv180x/cv180x_fpga/linux/cvitek_cv180x_fpga_defconfig
View File

@ -1,407 +0,0 @@
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=15
CONFIG_BLK_DEV_INITRD=y
# CONFIG_SYSFS_SYSCALL is not set
# CONFIG_FHANDLE is not set
# CONFIG_BASE_FULL is not set
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
# CONFIG_SLUB_DEBUG is not set
CONFIG_FORCE_MAX_ZONEORDER=10
CONFIG_ARCH_CVITEK=y
CONFIG_SOC_THEAD=y
# CONFIG_RISCV_SWIOTLB is not set
CONFIG_VECTOR=y
CONFIG_VECTOR_0_7=y
# CONFIG_COMPAT is not set
CONFIG_ARCH_CV180X=y
CONFIG_ARCH_CVITEK_CHIP="cv180x"
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_MQ_IOSCHED_DEADLINE is not set
# CONFIG_MQ_IOSCHED_KYBER is not set
# CONFIG_COREDUMP is not set
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_CFG80211=m
CONFIG_RFKILL=y
CONFIG_UEVENT_HELPER=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_OF_PARTS is not set
CONFIG_MTD_BLOCK=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_CVSNFC=y
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
CONFIG_SPI_CVI_SPIF=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_AURORA is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_DWMAC_GENERIC is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_CVITEK_PHY is not set
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
# CONFIG_WLAN_VENDOR_BROADCOM is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
# CONFIG_WLAN_VENDOR_MARVELL is not set
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_PINCTRL=y
CONFIG_CVITEK_PINCTRL_CV1835=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
CONFIG_THERMAL=n
CONFIG_THERMAL_WRITABLE_TRIPS=n
CONFIG_THERMAL_EMULATION=n
CONFIG_WATCHDOG=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_DVB_NET is not set
# CONFIG_DVB_DYNAMIC_MINORS is not set
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
CONFIG_VIDEO_CVITEK_CIF=m
CONFIG_VIDEO_CVITEK_SNS_I2C=m
# CONFIG_CXD2880_SPI_DRV is not set
# CONFIG_MEDIA_TUNER_SIMPLE is not set
# CONFIG_MEDIA_TUNER_TDA18250 is not set
# CONFIG_MEDIA_TUNER_TDA8290 is not set
# CONFIG_MEDIA_TUNER_TDA827X is not set
# CONFIG_MEDIA_TUNER_TDA18271 is not set
# CONFIG_MEDIA_TUNER_TDA9887 is not set
# CONFIG_MEDIA_TUNER_TEA5761 is not set
# CONFIG_MEDIA_TUNER_TEA5767 is not set
# CONFIG_MEDIA_TUNER_MSI001 is not set
# CONFIG_MEDIA_TUNER_MT20XX is not set
# CONFIG_MEDIA_TUNER_MT2060 is not set
# CONFIG_MEDIA_TUNER_MT2063 is not set
# CONFIG_MEDIA_TUNER_MT2266 is not set
# CONFIG_MEDIA_TUNER_MT2131 is not set
# CONFIG_MEDIA_TUNER_QT1010 is not set
# CONFIG_MEDIA_TUNER_XC2028 is not set
# CONFIG_MEDIA_TUNER_XC5000 is not set
# CONFIG_MEDIA_TUNER_XC4000 is not set
# CONFIG_MEDIA_TUNER_MXL5005S is not set
# CONFIG_MEDIA_TUNER_MXL5007T is not set
# CONFIG_MEDIA_TUNER_MC44S803 is not set
# CONFIG_MEDIA_TUNER_MAX2165 is not set
# CONFIG_MEDIA_TUNER_TDA18218 is not set
# CONFIG_MEDIA_TUNER_FC0011 is not set
# CONFIG_MEDIA_TUNER_FC0012 is not set
# CONFIG_MEDIA_TUNER_FC0013 is not set
# CONFIG_MEDIA_TUNER_TDA18212 is not set
# CONFIG_MEDIA_TUNER_E4000 is not set
# CONFIG_MEDIA_TUNER_FC2580 is not set
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
# CONFIG_MEDIA_TUNER_TUA9001 is not set
# CONFIG_MEDIA_TUNER_SI2157 is not set
# CONFIG_MEDIA_TUNER_IT913X is not set
# CONFIG_MEDIA_TUNER_R820T is not set
# CONFIG_MEDIA_TUNER_MXL301RF is not set
# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
# CONFIG_DVB_STB0899 is not set
# CONFIG_DVB_STB6100 is not set
# CONFIG_DVB_STV090x is not set
# CONFIG_DVB_STV0910 is not set
# CONFIG_DVB_STV6110x is not set
# CONFIG_DVB_STV6111 is not set
# CONFIG_DVB_MXL5XX is not set
# CONFIG_DVB_M88DS3103 is not set
# CONFIG_DVB_DRXK is not set
# CONFIG_DVB_TDA18271C2DD is not set
# CONFIG_DVB_SI2165 is not set
# CONFIG_DVB_MN88472 is not set
# CONFIG_DVB_MN88473 is not set
# CONFIG_DVB_CX24110 is not set
# CONFIG_DVB_CX24123 is not set
# CONFIG_DVB_MT312 is not set
# CONFIG_DVB_ZL10036 is not set
# CONFIG_DVB_ZL10039 is not set
# CONFIG_DVB_S5H1420 is not set
# CONFIG_DVB_STV0288 is not set
# CONFIG_DVB_STB6000 is not set
# CONFIG_DVB_STV0299 is not set
# CONFIG_DVB_STV6110 is not set
# CONFIG_DVB_STV0900 is not set
# CONFIG_DVB_TDA8083 is not set
# CONFIG_DVB_TDA10086 is not set
# CONFIG_DVB_TDA8261 is not set
# CONFIG_DVB_VES1X93 is not set
# CONFIG_DVB_TUNER_ITD1000 is not set
# CONFIG_DVB_TUNER_CX24113 is not set
# CONFIG_DVB_TDA826X is not set
# CONFIG_DVB_TUA6100 is not set
# CONFIG_DVB_CX24116 is not set
# CONFIG_DVB_CX24117 is not set
# CONFIG_DVB_CX24120 is not set
# CONFIG_DVB_SI21XX is not set
# CONFIG_DVB_TS2020 is not set
# CONFIG_DVB_DS3000 is not set
# CONFIG_DVB_MB86A16 is not set
# CONFIG_DVB_TDA10071 is not set
# CONFIG_DVB_SP8870 is not set
# CONFIG_DVB_SP887X is not set
# CONFIG_DVB_CX22700 is not set
# CONFIG_DVB_CX22702 is not set
# CONFIG_DVB_S5H1432 is not set
# CONFIG_DVB_DRXD is not set
# CONFIG_DVB_L64781 is not set
# CONFIG_DVB_TDA1004X is not set
# CONFIG_DVB_NXT6000 is not set
# CONFIG_DVB_MT352 is not set
# CONFIG_DVB_ZL10353 is not set
# CONFIG_DVB_DIB3000MB is not set
# CONFIG_DVB_DIB3000MC is not set
# CONFIG_DVB_DIB7000M is not set
# CONFIG_DVB_DIB7000P is not set
# CONFIG_DVB_DIB9000 is not set
# CONFIG_DVB_TDA10048 is not set
# CONFIG_DVB_AF9013 is not set
# CONFIG_DVB_EC100 is not set
# CONFIG_DVB_STV0367 is not set
# CONFIG_DVB_CXD2820R is not set
# CONFIG_DVB_CXD2841ER is not set
# CONFIG_DVB_RTL2830 is not set
# CONFIG_DVB_RTL2832 is not set
# CONFIG_DVB_RTL2832_SDR is not set
# CONFIG_DVB_SI2168 is not set
# CONFIG_DVB_ZD1301_DEMOD is not set
# CONFIG_DVB_CXD2880 is not set
# CONFIG_DVB_VES1820 is not set
# CONFIG_DVB_TDA10021 is not set
# CONFIG_DVB_TDA10023 is not set
# CONFIG_DVB_STV0297 is not set
# CONFIG_DVB_NXT200X is not set
# CONFIG_DVB_OR51211 is not set
# CONFIG_DVB_OR51132 is not set
# CONFIG_DVB_BCM3510 is not set
# CONFIG_DVB_LGDT330X is not set
# CONFIG_DVB_LGDT3305 is not set
# CONFIG_DVB_LGDT3306A is not set
# CONFIG_DVB_LG2160 is not set
# CONFIG_DVB_S5H1409 is not set
# CONFIG_DVB_AU8522_DTV is not set
# CONFIG_DVB_AU8522_V4L is not set
# CONFIG_DVB_S5H1411 is not set
# CONFIG_DVB_S921 is not set
# CONFIG_DVB_DIB8000 is not set
# CONFIG_DVB_MB86A20S is not set
# CONFIG_DVB_TC90522 is not set
# CONFIG_DVB_MN88443X is not set
# CONFIG_DVB_PLL is not set
# CONFIG_DVB_TUNER_DIB0070 is not set
# CONFIG_DVB_TUNER_DIB0090 is not set
# CONFIG_DVB_DRX39XYJ is not set
# CONFIG_DVB_LNBH25 is not set
# CONFIG_DVB_LNBH29 is not set
# CONFIG_DVB_LNBP21 is not set
# CONFIG_DVB_LNBP22 is not set
# CONFIG_DVB_ISL6405 is not set
# CONFIG_DVB_ISL6421 is not set
# CONFIG_DVB_ISL6423 is not set
# CONFIG_DVB_A8293 is not set
# CONFIG_DVB_LGS8GL5 is not set
# CONFIG_DVB_LGS8GXX is not set
# CONFIG_DVB_ATBM8830 is not set
# CONFIG_DVB_TDA665x is not set
# CONFIG_DVB_IX2505V is not set
# CONFIG_DVB_M88RS2000 is not set
# CONFIG_DVB_AF9033 is not set
# CONFIG_DVB_HORUS3A is not set
# CONFIG_DVB_ASCOT2E is not set
# CONFIG_DVB_HELENE is not set
# CONFIG_DVB_CXD2099 is not set
# CONFIG_DVB_SP2 is not set
CONFIG_FB=y
CONFIG_FB_CVITEK=m
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_PROC_FS is not set
# CONFIG_SND_DRIVERS is not set
CONFIG_SND_HDA_PREALLOC_SIZE=1
# CONFIG_SND_SPI is not set
# CONFIG_SND_USB is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_CV182XA_CV182XAADC=y
CONFIG_SND_SOC_CV182XA_CV182XADAC=y
CONFIG_SND_CV1835_I2S=y
CONFIG_SND_SOC_CV182XAADC=y
CONFIG_SND_SOC_CV182XADAC=y
CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
CONFIG_CV1835_I2S_SUBSYS=y
CONFIG_USB=m
CONFIG_USB_DWC2=m
CONFIG_USB_GADGET=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_CVI=y
CONFIG_RTC_CLASS=y
# CONFIG_VIRTIO_MENU is not set
CONFIG_STAGING=y
CONFIG_ION=y
CONFIG_ION_SYSTEM_HEAP=y
CONFIG_ION_CARVEOUT_HEAP=y
CONFIG_ION_CMA_HEAP=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PWM=y
CONFIG_SIFIVE_PLIC=y
CONFIG_ANDROID=y
# CONFIG_MANDATORY_FILE_LOCKING is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_WBUF_VERIFY=y
CONFIG_UBIFS_FS=y
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_ZLIB is not set
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_XZ=y
CONFIG_NFS_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_3=y
CONFIG_CRYPTO_SHA256=y
# CONFIG_CRYPTO_HW is not set
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
# CONFIG_XZ_DEC_ARMTHUMB is not set
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=0
CONFIG_PRINTK_TIME=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_INFO_DWARF4=y
CONFIG_GDB_SCRIPTS=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_FS=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
#
# Network configurations
#
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_HAVE_NET_DSA=y
CONFIG_PAGE_POOL=y
CONFIG_REGMAP_MMIO=y
CONFIG_OF_NET=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_CVITEK=y
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
# CONFIG_FIXED_PHY is not set
CONFIG_SMSC_PHY=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_OF_MDIO=y
CONFIG_MDIO_DEVRES=y
#
# sysDMA Configurations
#
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC_CVITEK=y
CONFIG_CV1835_SYSDMA_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_HAS_DMA=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y

1
build/boards/cv180x/cv180x_fpga/memmap.py
View File

@ -1 +0,0 @@
../../default/memmap/cv180x/memmap_ddr_4g.py

1
build/boards/cv180x/cv180x_fpga/partition/partition_none.xml
View File

@ -1 +0,0 @@
../../../default/partition/partition_none.xml

1
build/boards/cv180x/cv180x_fpga/partition/partition_spinor.xml
View File

@ -1 +0,0 @@
../../../default/partition/partition_spinor.xml

7
build/boards/cv180x/cv180x_fpga/u-boot/cvi_board_init.c
View File

@ -1,7 +0,0 @@
int cvi_board_init(void)
{
PINMUX_CONFIG(SD1_CMD, IIC3_SCL);
PINMUX_CONFIG(SD1_CLK, IIC3_SDA);
return 0;
}

1
build/boards/cv180x/cv180x_fpga/u-boot/cvitek.h
View File

@ -1 +0,0 @@
../../../default/u-boot/cvitek_cv180x.h

44
build/boards/cv180x/cv180x_fpga/u-boot/cvitek_cv180x_fpga_defconfig
View File

@ -1,44 +0,0 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="cv180x_fpga"
CONFIG_IDENT_STRING=" cvitek_cv180x"
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_TARGET_CVITEK_CV180X=y
CONFIG_TARGET_CVITEK_CV180X_FPGA=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="cv180x_c906# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_CVI_SD_UPDATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CVITEK=y
CONFIG_MTD=y
CONFIG_PHY_SMSC=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
# CONFIG_PHY_CVITEK is not set
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LZ4=y
CONFIG_LZMA=y
# CONFIG_TOOLS_LIBCRYPTO is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set

6
build/boards/cv180x/cv180x_palladium/config.json
View File

@ -1,6 +0,0 @@
{
"ddr_cfg_list": [
""
],
"board_information": "PALLADIUM"
}

23
build/boards/cv180x/cv180x_palladium/cv180x_palladium_defconfig
View File

@ -1,23 +0,0 @@
CONFIG_CHIP_cv180x=y
CONFIG_ARCH="riscv"
CONFIG_BOARD_palladium=y
CONFIG_DDR_CFG_none=y
CONFIG_CROSS_COMPILE="riscv64-unknown-linux-gnu-"
CONFIG_KERNEL_ENTRY_HACK=y
CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80200000"
CONFIG_TOOLCHAIN_GLIBC_RISCV64=y
CONFIG_BOOT_IMAGE_SINGLE_DTB=y
CONFIG_SENSOR_SONY_IMX327_FPGA=y
CONFIG_MIPI_PANEL_ILI9881C=y
CONFIG_UBOOT_2021_10=y
CONFIG_KERNEL_SRC_5.10=y
# CONFIG_ROOTFS_OVERLAYFS is not set
# CONFIG_TARGET_PACKAGE_CVITRACER is not set
# CONFIG_TARGET_PACKAGE_GDBSERVER is not set
# CONFIG_TARGET_PACKAGE_LIBCRYPTO is not set
# CONFIG_TARGET_PACKAGE_LIBZ is not set
# CONFIG_TARGET_PACKAGE_OTASERVER is not set
# CONFIG_TARGET_PACKAGE_RSYSLOG is not set
# CONFIG_TARGET_PACKAGE_CRONTABS is not set
# CONFIG_TARGET_PACKAGE_GATORD is not set
# CONFIG_ENABLE_FREERTOS is not set

22
build/boards/cv180x/cv180x_palladium/dts_riscv/cv180x_palladium.dts
View File

@ -1,22 +0,0 @@
/dts-v1/;
#include "cv180x_base_riscv.dtsi"
#include "cv180x_asic_bga.dtsi"
#include "cv180x_asic_spinor.dtsi"
#include "cv180x_default_memmap.dtsi"
/ {
};
&c906_cpus {
timebase-frequency = <1000000000>;
cpu@0 {
clock-frequency = <850000000>;
};
};
&uart0 {
clock-frequency = <307200>;
current-speed = <19200>;
};

61
build/boards/cv180x/cv180x_palladium/memmap.py
View File

@ -1,61 +0,0 @@
SIZE_1M = 0x100000
SIZE_1K = 1024
# Only attributes in class MemoryMap are generated to .h
class MemoryMap:
# No prefix "CVIMMAP_" for the items in _no_prefix[]
_no_prefix = [
"CONFIG_SYS_TEXT_BASE" # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
]
DRAM_BASE = 0x80000000
DRAM_SIZE = 256 * SIZE_1M
# Bootlogo
BOOTLOGO_ADDR = DRAM_BASE + 24 * SIZE_1M
BOOTLOGO_SIZE = 1.5 * SIZE_1M
# C906L freertos
FREERTOS_SIZE = 2 * SIZE_1M
FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
# psu_ddr_0_MEM_0 : ORIGIN = FREERTOS_ADDR, LENGTH = FREERTOS_SIZE
# OpenSBI | arm-trusted-firmware
MONITOR_ADDR = DRAM_BASE
ATF_SIZE = 512 * SIZE_1K
OPENSBI_SIZE = 512 * SIZE_1K
OPENSBI_FDT_ADDR = DRAM_BASE + SIZE_1M
# FSBL
FSBL_UNZIP_ADDR = DRAM_BASE + 16 * SIZE_1M
FSBL_UNZIP_SIZE = DRAM_BASE + 4 * SIZE_1M
FSBL_C906L_START_ADDR = FREERTOS_ADDR
# uboot-2021 defconfig
CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
CONFIG_SYS_INIT_SP_ADDR = DRAM_BASE + 63 * SIZE_1M
UIMAG_ADDR = DRAM_BASE + 18 * SIZE_1M
CVI_UPDATE_HEADER_SIZE = SIZE_1K
CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR + CVI_UPDATE_HEADER_SIZE
# memory@DRAM_BASE
KERNEL_MEMORY_ADDR = DRAM_BASE
KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
ION_ADDR = DRAM_BASE + 0x3C80000
ION_SIZE = 65.5 * SIZE_1M
# Fast image buffer
H26X_BITSTREAM_ADDR = DRAM_BASE + 39 * SIZE_1M
H26X_BITSTREAM_SIZE = 2 * SIZE_1M
H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
H26X_ENC_BUFF_SIZE = 0
ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
ISP_MEM_BASE_SIZE = 10 * SIZE_1M
FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE

1
build/boards/cv180x/cv180x_palladium/partition/partition_none.xml
View File

@ -1 +0,0 @@
../../../default/partition/partition_none.xml

1
build/boards/cv180x/cv180x_palladium/partition/partition_spinor.xml
View File

@ -1 +0,0 @@
../../../default/partition/partition_spinor.xml

4
build/boards/cv180x/cv180x_palladium/u-boot/cvi_board_init.c
View File

@ -1,4 +0,0 @@
int cvi_board_init(void)
{
return 0;
}

1
build/boards/cv180x/cv180x_palladium/u-boot/cvitek.h
View File

@ -1 +0,0 @@
../../../default/u-boot/cvitek_cv180x.h

45
build/boards/cv180x/cv180x_palladium/u-boot/cvitek_cv180x_palladium_defconfig
View File

@ -1,45 +0,0 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="cv180x_palladium"
CONFIG_IDENT_STRING=" cvitek_cv180x"
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_TARGET_CVITEK_CV180X=y
CONFIG_TARGET_CVITEK_CV180X_PALLADIUM=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BAUDRATE=19200
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="cv180x_c906# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_CVI_SD_UPDATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CVITEK=y
CONFIG_MTD=y
CONFIG_PHY_SMSC=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
# CONFIG_PHY_CVITEK is not set
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LZ4=y
CONFIG_LZMA=y
# CONFIG_TOOLS_LIBCRYPTO is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set

3
build/boards/cv180x/cv180zb_wdmb_0008a_spinor/linux/cvitek_cv180zb_wdmb_0008a_spinor_defconfig
View File

@ -224,3 +224,6 @@ CONFIG_DEBUG_FS=y
# CONFIG_RCU_TRACE is not set
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv180x/cv180zb_wevb_0008a_spinor/linux/cvitek_cv180zb_wevb_0008a_spinor_defconfig
View File

@ -229,3 +229,6 @@ CONFIG_DEBUG_FS=y
# CONFIG_RCU_TRACE is not set
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1810c_wdmb_0006a_spinor/linux/cvitek_cv1810c_wdmb_0006a_spinor_defconfig
View File

@ -466,3 +466,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

2
build/boards/cv181x/cv1820a_wevb_0006a_spinor/config.json → build/boards/cv181x/cv1810c_wevb_0006a_spinand/config.json
View File

@ -3,5 +3,5 @@
"ddr2_1333_x16",
"ddr_auto_x16"
],
"board_information": "CA53 + SPINOR 16MB + QFN SIP 64MB"
"board_information": "C906B + SPINAND 256MB + BGA SIP 128MB"
}

34
build/boards/cv181x/cv1820a_wevb_0006a_spinor/cv1820a_wevb_0006a_spinor_defconfig → build/boards/cv181x/cv1810c_wevb_0006a_spinand/cv1810c_wevb_0006a_spinand_defconfig
View File

@ -1,15 +1,19 @@
CONFIG_CHIP_cv1820a=y
CONFIG_BOARD_wevb_0006a_spinor=y
CONFIG_CHIP_cv1810c=y
CONFIG_BOARD_wevb_0006a_spinand=y
CONFIG_DDR_CFG_ddr2_1333_x16=y
CONFIG_ARCH="arm"
CONFIG_ARCH="riscv"
CONFIG_CROSS_COMPILE="riscv64-unknown-linux-musl-"
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KERNEL_ENTRY_HACK=y
CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80108000"
CONFIG_TOOLCHAIN_GLIBC_ARM=y
CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80200000"
CONFIG_TOOLCHAIN_MUSL_RISCV64=y
CONFIG_FLASH_SIZE_SHRINK=y
CONFIG_NO_FB=y
CONFIG_NO_TP=y
CONFIG_DDR_64MB_SIZE=y
CONFIG_BOOT_IMAGE_SINGLE_DTB=y
CONFIG_STORAGE_TYPE_spinor=y
CONFIG_STORAGE_TYPE_spinand=y
CONFIG_SENSOR_TUNING_PARAM_cv181x_src_gcore_gc4653=y
CONFIG_SENSOR_GCORE_GC4653=y
CONFIG_SENSOR_SMS_SC3335=y
CONFIG_SENSOR_SMS_SC500AI=y
@ -21,12 +25,22 @@ CONFIG_SENSOR_SONY_IMX327_2L=y
CONFIG_SENSOR_SONY_IMX327_SLAVE=y
CONFIG_SENSOR_OV_OS04C10=y
CONFIG_UBOOT_2021_10=y
CONFIG_KERNEL_SRC_5.10=y
CONFIG_KERNEL_LZMA=y
CONFIG_SKIP_RAMDISK=y
CONFIG_SENSOR_TUNING_PARAM_cv181x_src_gcore_gc4653=y
CONFIG_USE_4K_ERASE_SIZE_FOR_JFFS2=y
# CONFIG_ROOTFS_OVERLAYFS is not set
CONFIG_TARGET_PACKAGE_DROPBEAR=y
CONFIG_TARGET_PACKAGE_MTD-UTILS=y
# CONFIG_TARGET_PACKAGE_CVITRACER is not set
# CONFIG_TARGET_PACKAGE_GDBSERVER is not set
# CONFIG_TARGET_PACKAGE_LIBCRYPTO is not set
# CONFIG_TARGET_PACKAGE_LIBZ is not set
# CONFIG_TARGET_PACKAGE_OTASERVER is not set
# CONFIG_TARGET_PACKAGE_RSYSLOG is not set
CONFIG_TARGET_PACKAGE_BUSYBOX_SYSLOGD_SCRIPT=y
CONFIG_TARGET_PACKAGE_CRONTABS=y
# CONFIG_TARGET_PACKAGE_GATORD is not set
CONFIG_TARGET_PACKAGE_WIFI=y
CONFIG_TARGET_PACKAGE_DROPBEAR=y
CONFIG_TARGET_PACKAGE_NTP=y
CONFIG_ENABLE_FREERTOS=y
CONFIG_ENABLE_RTOS_DUMP_PRINT=y
CONFIG_DUMP_PRINT_SZ_IDX=17

4
build/boards/cv181x/cv1823a_wevb_0007a_spinand/dts_arm/cv1823a_wevb_0007a_spinand.dts → build/boards/cv181x/cv1810c_wevb_0006a_spinand/dts_riscv/cv1810c_wevb_0006a_spinand.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
#include "cv181x_base_arm.dtsi"
#include "cv181x_asic_bga.dtsi"
#include "cv181x_base_riscv.dtsi"
#include "cv181x_asic_qfn.dtsi"
#include "cv181x_asic_spinand.dtsi"
#include "cv181x_default_memmap.dtsi"

157
build/boards/cv180x/cv180x_palladium/linux/cvitek_cv180x_palladium_defconfig → build/boards/cv181x/cv1810c_wevb_0006a_spinand/linux/cvitek_cv1810c_wevb_0006a_spinand_defconfig
View File

@ -1,3 +1,4 @@
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
@ -21,10 +22,11 @@ CONFIG_SOC_THEAD=y
CONFIG_VECTOR=y
CONFIG_VECTOR_0_7=y
# CONFIG_COMPAT is not set
CONFIG_ARCH_CV180X=y
CONFIG_ARCH_CVITEK_CHIP="cv180x"
CONFIG_ARCH_CV180X_PALLADIUM=y
CONFIG_ARCH_CVITEK_CHIP="cv181x"
CONFIG_ARCH_CV181X_ASIC=y
CONFIG_POWER_RESET=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_STRICT_KERNEL_RWX=n
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
@ -39,7 +41,7 @@ CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_CFG80211=m
CONFIG_CFG80211=y
CONFIG_RFKILL=y
CONFIG_UEVENT_HELPER=y
CONFIG_DEVTMPFS=y
@ -53,11 +55,11 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_CVSNFC=y
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
CONFIG_SPI_CVI_SPIF=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_NETDEVICES=y
# CONFIG_NET_CORE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
@ -89,7 +91,8 @@ CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_SMSC_PHY=y
CONFIG_CVITEK_PHY=y
CONFIG_CVITEK_PHY_UAPS=y
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
@ -101,10 +104,15 @@ CONFIG_SMSC_PHY=y
# CONFIG_WLAN_VENDOR_MARVELL is not set
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
CONFIG_RTL8188FU=n
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
CONFIG_WLAN_VENDOR_MICROCHIP=n
CONFIG_WLAN_VENDOR_QUANTENNA=n
CONFIG_INPUT=n
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
@ -126,19 +134,27 @@ CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
CONFIG_THERMAL=y
CONFIG_THERMAL_NETLINK=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_DVB_NET is not set
# CONFIG_DVB_DYNAMIC_MINORS is not set
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
CONFIG_MEDIA_SUPPORT=n
CONFIG_VIDEO_V4L2_SUBDEV_API=n
CONFIG_V4L_PLATFORM_DRIVERS=n
CONFIG_V4L_MEM2MEM_DRIVERS=n
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=n
CONFIG_VIDEO_CVITEK=m
CONFIG_VIDEO_CVITEK_CIF=m
CONFIG_VIDEO_CVITEK_SNS_I2C=m
CONFIG_VIDEO_CVITEK_MIPI_TX=m
#
# Media SPI Adapters
#
# CONFIG_CXD2880_SPI_DRV is not set
# end of Media SPI Adapters
#
# Customize TV tuners
#
# CONFIG_MEDIA_TUNER_SIMPLE is not set
# CONFIG_MEDIA_TUNER_TDA18250 is not set
# CONFIG_MEDIA_TUNER_TDA8290 is not set
@ -176,6 +192,14 @@ CONFIG_VIDEO_CVITEK_SNS_I2C=m
# CONFIG_MEDIA_TUNER_MXL301RF is not set
# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
# end of Customize TV tuners
#
# Customise DVB Frontends
#
#
# Multistandard (satellite) frontends
#
# CONFIG_DVB_STB0899 is not set
# CONFIG_DVB_STB6100 is not set
# CONFIG_DVB_STV090x is not set
@ -184,11 +208,19 @@ CONFIG_VIDEO_CVITEK_SNS_I2C=m
# CONFIG_DVB_STV6111 is not set
# CONFIG_DVB_MXL5XX is not set
# CONFIG_DVB_M88DS3103 is not set
#
# Multistandard (cable + terrestrial) frontends
#
# CONFIG_DVB_DRXK is not set
# CONFIG_DVB_TDA18271C2DD is not set
# CONFIG_DVB_SI2165 is not set
# CONFIG_DVB_MN88472 is not set
# CONFIG_DVB_MN88473 is not set
#
# DVB-S (satellite) frontends
#
# CONFIG_DVB_CX24110 is not set
# CONFIG_DVB_CX24123 is not set
# CONFIG_DVB_MT312 is not set
@ -216,6 +248,10 @@ CONFIG_VIDEO_CVITEK_SNS_I2C=m
# CONFIG_DVB_DS3000 is not set
# CONFIG_DVB_MB86A16 is not set
# CONFIG_DVB_TDA10071 is not set
#
# DVB-T (terrestrial) frontends
#
# CONFIG_DVB_SP8870 is not set
# CONFIG_DVB_SP887X is not set
# CONFIG_DVB_CX22700 is not set
@ -244,10 +280,18 @@ CONFIG_VIDEO_CVITEK_SNS_I2C=m
# CONFIG_DVB_SI2168 is not set
# CONFIG_DVB_ZD1301_DEMOD is not set
# CONFIG_DVB_CXD2880 is not set
#
# DVB-C (cable) frontends
#
# CONFIG_DVB_VES1820 is not set
# CONFIG_DVB_TDA10021 is not set
# CONFIG_DVB_TDA10023 is not set
# CONFIG_DVB_STV0297 is not set
#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
# CONFIG_DVB_NXT200X is not set
# CONFIG_DVB_OR51211 is not set
# CONFIG_DVB_OR51132 is not set
@ -260,14 +304,29 @@ CONFIG_VIDEO_CVITEK_SNS_I2C=m
# CONFIG_DVB_AU8522_DTV is not set
# CONFIG_DVB_AU8522_V4L is not set
# CONFIG_DVB_S5H1411 is not set
#
# ISDB-T (terrestrial) frontends
#
# CONFIG_DVB_S921 is not set
# CONFIG_DVB_DIB8000 is not set
# CONFIG_DVB_MB86A20S is not set
#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
# CONFIG_DVB_TC90522 is not set
# CONFIG_DVB_MN88443X is not set
#
# Digital terrestrial only tuners/PLL
#
# CONFIG_DVB_PLL is not set
# CONFIG_DVB_TUNER_DIB0070 is not set
# CONFIG_DVB_TUNER_DIB0090 is not set
#
# SEC control devices for DVB-S
#
# CONFIG_DVB_DRX39XYJ is not set
# CONFIG_DVB_LNBH25 is not set
# CONFIG_DVB_LNBH29 is not set
@ -287,10 +346,20 @@ CONFIG_VIDEO_CVITEK_SNS_I2C=m
# CONFIG_DVB_HORUS3A is not set
# CONFIG_DVB_ASCOT2E is not set
# CONFIG_DVB_HELENE is not set
#
# Common Interface (EN50221) controller drivers
#
# CONFIG_DVB_CXD2099 is not set
# CONFIG_DVB_SP2 is not set
CONFIG_FB=y
CONFIG_FB_CVITEK=m
# end of Customise DVB Frontends
#
# Digital TV options
#
# CONFIG_DVB_NET is not set
# CONFIG_DVB_DYNAMIC_MINORS is not set
# end of Digital TV options
CONFIG_FB=n
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
@ -306,20 +375,18 @@ CONFIG_SND_CV1835_I2S=y
CONFIG_SND_SOC_CV182XAADC=y
CONFIG_SND_SOC_CV182XADAC=y
CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
CONFIG_SND_PCM_TIMER=n
CONFIG_CV1835_I2S_SUBSYS=y
CONFIG_USB=m
CONFIG_USB_DWC2=m
CONFIG_USB_GADGET=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_CVI=y
CONFIG_RTC_CLASS=y
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC_CVITEK=y
CONFIG_RTC_CLASS=y
# CONFIG_VIRTIO_MENU is not set
CONFIG_STAGING=y
CONFIG_ION=y
@ -332,22 +399,25 @@ CONFIG_PWM=y
CONFIG_SIFIVE_PLIC=y
CONFIG_ANDROID=y
# CONFIG_MANDATORY_FILE_LOCKING is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_WBUF_VERIFY=y
CONFIG_UBIFS_FS=y
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_ZLIB is not set
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZ4=n
CONFIG_SQUASHFS_XZ=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_3=y
CONFIG_EFIVAR_FS=n
CONFIG_CRYPTO_SHA256=y
# CONFIG_CRYPTO_HW is not set
# CONFIG_XZ_DEC_X86 is not set
@ -358,13 +428,44 @@ CONFIG_CRYPTO_SHA256=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=0
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_INFO_DWARF4=y
CONFIG_DEBUG_INFO=n
CONFIG_DEBUG_INFO_DWARF4=n
CONFIG_GDB_SCRIPTS=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_FS=y
CONFIG_BLK_DEV_INITRD=n
CONFIG_KALLSYMS=n
CONFIG_FRAME_POINTER=n
CONFIG_DEBUG_MISC=n
CONFIG_RCU_TRACE=n
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_U_AUDIO=y
CONFIG_USB_F_SERIAL=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_EEM=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_F_FS=y
CONFIG_USB_F_UAC1=y
CONFIG_USB_F_UVC=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_BUG=n
CONFIG_IO_URING=n
CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

85
build/boards/cv181x/cv1810c_wevb_0006a_spinand/memmap.py Normal file
View File

@ -0,0 +1,85 @@
SIZE_1M = 0x100000
SIZE_1K = 1024
# Only attributes in class MemoryMap are generated to .h
class MemoryMap:
# No prefix "CVIMMAP_" for the items in _no_prefix[]
_no_prefix = [
"CONFIG_SYS_TEXT_BASE" # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
]
DRAM_BASE = 0x80000000
DRAM_SIZE = 64 * SIZE_1M
# ==============
# C906L FreeRTOS
# ==============
FREERTOS_SIZE = 768 * SIZE_1K
# FreeRTOS is at the end of DRAM
FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
FSBL_C906L_START_ADDR = FREERTOS_ADDR
# ==============================
# OpenSBI | arm-trusted-firmware
# ==============================
# Monitor is at the begining of DRAM
MONITOR_ADDR = DRAM_BASE
ATF_SIZE = 256 * SIZE_1K
OPENSBI_SIZE = 256 * SIZE_1K
OPENSBI_FDT_ADDR = MONITOR_ADDR + OPENSBI_SIZE
# =========================
# memory@DRAM_BASE in .dts.
# =========================
# Ignore the area of FreeRTOS in u-boot and kernel
KERNEL_MEMORY_ADDR = DRAM_BASE
KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
# =================
# Multimedia buffer. Used by u-boot/kernel/FreeRTOS
# =================
ION_SIZE = 26.5 * SIZE_1M
H26X_BITSTREAM_SIZE = 0 * SIZE_1M
H26X_ENC_BUFF_SIZE = 0
ISP_MEM_BASE_SIZE = 0 * SIZE_1M
FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE
# ION after FreeRTOS
ION_ADDR = FREERTOS_ADDR - ION_SIZE
# Buffers of the fast image are inside the ION buffer
H26X_BITSTREAM_ADDR = ION_ADDR
H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
assert ISP_MEM_BASE_ADDR + ISP_MEM_BASE_SIZE <= ION_ADDR + ION_SIZE
# Boot logo is after the ION buffer
# Framebuffer uses boot logo's reserved memory
BOOTLOGO_SIZE = 0 * SIZE_1K
BOOTLOGO_ADDR = ION_ADDR - BOOTLOGO_SIZE
FRAMEBUFFER_SIZE = BOOTLOGO_SIZE
FRAMEBUFFER_ADDR = BOOTLOGO_ADDR
# ===================
# FSBL and u-boot-2021
# ===================
CVI_UPDATE_HEADER_SIZE = SIZE_1K
UIMAG_SIZE = 15 * SIZE_1M
# kernel image loading buffer
UIMAG_ADDR = DRAM_BASE + 20 * SIZE_1M
CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR - CVI_UPDATE_HEADER_SIZE
# FSBL decompress buffer
FSBL_UNZIP_ADDR = UIMAG_ADDR
FSBL_UNZIP_SIZE = UIMAG_SIZE
assert UIMAG_ADDR + UIMAG_SIZE <= BOOTLOGO_ADDR
# u-boot's run address and entry point
CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
# u-boot's init stack point is only used before board_init_f()
CONFIG_SYS_INIT_SP_ADDR = UIMAG_ADDR + UIMAG_SIZE

0
build/boards/cv181x/cv1823a_wevb_0007a_spinand/partition/partition_spinand.xml → build/boards/cv181x/cv1810c_wevb_0006a_spinand/partition/partition_spinand.xml
View File

30
build/boards/cv181x/cv1810c_wevb_0006a_spinand/rootfs_script/clean_rootfs.sh Executable file
View File

@ -0,0 +1,30 @@
#!/bin/bash
SYSTEM_DIR=$1
rm -rf $SYSTEM_DIR/mnt/system/usr
rm -rf $SYSTEM_DIR/mnt/system/lib
rm -rf $SYSTEM_DIR/etc/init.d/S01syslogd
rm -rf $SYSTEM_DIR/etc/init.d/S02klogd
rm -rf $SYSTEM_DIR/etc/init.d/S02sysctl
rm -rf $SYSTEM_DIR/etc/init.d/S20urandom
rm -rf $SYSTEM_DIR/etc/init.d/S40network
rm -rf $SYSTEM_DIR/etc/init.d/S23ntp
rm -rf $SYSTEM_DIR/bin/ntpd
rm -rf $SYSTEM_DIR/mnt/cfg/secure.img
#del cv181x_mipi_tx.ko
rm -rf $SYSTEM_DIR/mnt/system/ko/cv181x_mipi_tx.ko
sed -i "/cv181x_mipi_tx.ko/d" $SYSTEM_DIR/mnt/system/ko/loadsystemko.sh
if [ $BUILD_FOR_DEBUG != "y" ]
then
#del dmesg cmd if CONFIG_PRINTK=n
#sed -i "/dmesg/d" $SYSTEM_DIR/mnt/system/ko/loadsystemko.sh
#del debugfs node
sed -i "/debugfs/d" $SYSTEM_DIR/etc/fstab
fi
du -sh $SYSTEM_DIR/* |sort -rh

12
build/boards/cv181x/cv1810c_wevb_0006a_spinand/u-boot/cvi_board_init.c Normal file
View File

@ -0,0 +1,12 @@
int cvi_board_init(void)
{
PINMUX_CONFIG(IIC0_SCL, CV_SCL0__CR_4WTDI);
PINMUX_CONFIG(IIC0_SDA, CV_SDA0__CR_4WTDO);
PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL);
PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA);
PINMUX_CONFIG(PAD_MIPI_TXP0, XGPIOC_13);
PINMUX_CONFIG(PAD_MIPI_TXM0, CAM_MCLK1);
return 0;
}

0
build/boards/default/u-boot/cvitek_183x.h → build/boards/cv181x/cv1810c_wevb_0006a_spinand/u-boot/cvitek.h
View File

24
build/boards/cv181x/cv181x_fpga_c906/u-boot/cvitek_cv181x_fpga_c906_defconfig → build/boards/cv181x/cv1810c_wevb_0006a_spinand/u-boot/cvitek_cv1810c_wevb_0006a_spinand_defconfig
View File

@ -1,17 +1,15 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_BOOTMAPSZ=0x40000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="cv181x_fpga"
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
CONFIG_IDENT_STRING=" cvitek_cv181x"
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_TARGET_CVITEK_CV181X=y
CONFIG_TARGET_CVITEK_CV181X_FPGA=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=1
CONFIG_BOOTDELAY=0
CONFIG_SYS_PROMPT="cv181x_c906# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
@ -24,26 +22,24 @@ CONFIG_SYS_PROMPT="cv181x_c906# "
CONFIG_CMD_MMC=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_CVI_SD_UPDATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_PHYLIB=y
# CONFIG_PHY_BROADCOM is not set
CONFIG_PHY_SMSC=y
# CONFIG_PHY_FIXED is not set
CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CVITEK=y
CONFIG_MTD=y
# CONFIG_SPI_FLASH is not set
CONFIG_PHY_CVITEK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LZ4=y
CONFIG_LZMA=y
# CONFIG_TOOLS_LIBCRYPTO is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FLASH_CVSNFC_V3=y
CONFIG_ENV_IS_IN_NAND=y

3
build/boards/cv181x/cv1810c_wevb_0006a_spinor/linux/cvitek_cv1810c_wevb_0006a_spinor_defconfig
View File

@ -466,3 +466,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1810h_wevb_0007a_spinor/linux/cvitek_cv1810h_wevb_0007a_spinor_defconfig
View File

@ -466,3 +466,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1811c_wdmb_0006a_spinor/linux/cvitek_cv1811c_wdmb_0006a_spinor_defconfig
View File

@ -454,3 +454,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1811c_wevb_0006a_emmc/linux/cvitek_cv1811c_wevb_0006a_emmc_defconfig
View File

@ -462,3 +462,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1811c_wevb_0006a_spinand/linux/cvitek_cv1811c_wevb_0006a_spinand_defconfig
View File

@ -450,3 +450,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1811h_wevb_0007a_spinor/linux/cvitek_cv1811h_wevb_0007a_spinor_defconfig
View File

@ -486,3 +486,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1812cp_wevb_0006a_emmc/linux/cvitek_cv1812cp_wevb_0006a_emmc_defconfig
View File

@ -488,3 +488,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1812cp_wevb_0006a_spinand/linux/cvitek_cv1812cp_wevb_0006a_spinand_defconfig
View File

@ -486,3 +486,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1812h_wevb_0007a_emmc/linux/cvitek_cv1812h_wevb_0007a_emmc_defconfig
View File

@ -463,3 +463,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1812h_wevb_0007a_emmc_huashan/linux/cvitek_cv1812h_wevb_0007a_emmc_huashan_defconfig
View File

@ -661,3 +661,6 @@ CONFIG_BT_HCIUART_SERDEV=n
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8821CS=m
CONFIG_RTL8723DS=m
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

6
build/boards/cv181x/cv1812h_wevb_0007a_spinand/linux/cvitek_cv1812h_wevb_0007a_spinand_defconfig
View File

@ -91,7 +91,8 @@ CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_CV182XCONFIG_CVITEK_PHYA_PHY=y
CONFIG_CVITEK_PHY=y
CONFIG_CVITEK_PHY_UAPS=y
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
@ -486,3 +487,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1812h_wevb_0007a_spinand_huashan/linux/cvitek_cv1812h_wevb_0007a_spinand_huashan_defconfig
View File

@ -494,3 +494,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1812h_wevb_0007a_spinor/linux/cvitek_cv1812h_wevb_0007a_spinor_defconfig
View File

@ -487,3 +487,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1812h_wevb_0007a_spinor_huashan/linux/cvitek_cv1812h_wevb_0007a_spinor_huashan_defconfig
View File

@ -495,3 +495,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1813h_wevb_0007a_emmc/linux/cvitek_cv1813h_wevb_0007a_emmc_defconfig
View File

@ -463,3 +463,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1813h_wevb_0007a_spinand/linux/cvitek_cv1813h_wevb_0007a_spinand_defconfig
View File

@ -486,3 +486,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

3
build/boards/cv181x/cv1813h_wevb_0007a_spinor/linux/cvitek_cv1813h_wevb_0007a_spinor_defconfig
View File

@ -486,3 +486,6 @@ CONFIG_ADVISE_SYSCALLS=n
CONFIG_SIGNALFD=n
CONFIG_TIMERFD=n
CONFIG_EPOLL=n
CONFIG_ELF_CORE=y
CONFIG_COREDUMP=y
CONFIG_PROC_SYSCTL=y

6
build/boards/cv181x/cv181x_fpga/config.json
View File

@ -1,6 +0,0 @@
{
"ddr_cfg_list": [
""
],
"board_information": "FPGA"
}

34
build/boards/cv181x/cv181x_fpga/cv181x_fpga_defconfig
View File

@ -1,34 +0,0 @@
CONFIG_CHIP_cv181x=y
CONFIG_ARCH="arm"
CONFIG_BOARD_fpga=y
CONFIG_DDR_CFG_none=y
CONFIG_TOOLCHAIN_GLIBC_ARM=y
CONFIG_STORAGE_TYPE_spinor=y
CONFIG_CROSS_COMPILE_KERNEL="arm-linux-gnueabihf-"
CONFIG_KERNEL_ENTRY_HACK=y
CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80108000"
CONFIG_BOOT_IMAGE_SINGLE_DTB=y
# CONFIG_ROOTFS_OVERLAYFS is not set
# CONFIG_TARGET_PACKAGE_GDBSERVER is not set
# CONFIG_TARGET_PACKAGE_NANOMSG is not set
# CONFIG_TARGET_PACKAGE_OTASERVER is not set
# CONFIG_TARGET_PACKAGE_RSYSLOG is not set
#
# Sensor settings
#
#
# Sensor support list
#
CONFIG_SENSOR_SONY_IMX327_FPGA=y
#
# Panel settings
#
#
# Panel support list
#
CONFIG_MIPI_PANEL_ILI9881C=y

688
build/boards/cv181x/cv181x_fpga/linux/cv181x_fpga.dts
View File

@ -1,688 +0,0 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/cv181x-resets.h>
#include <dt-bindings/clock/cv181x-clock.h>
#include <dt-bindings/sound/cv1835-audio.h>
#include <dt-bindings/dma/cv181x-dmamap.h>
/dts-v1/;
/memreserve/ 0x80000000 0x0000000000080000; // ATF BL31 + BL32
/ {
compatible = "linux,dummy-virt";
#size-cells = <0x2>;
#address-cells = <0x2>;
interrupt-parent = <&gic>;
rst: reset-controller {
#reset-cells = <1>;
compatible = "cvitek,reset";
reg = <0x0 0x03003000 0x0 0x10>;
};
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "osc";
};
clk: clock-controller {
compatible = "cvitek,cv181x-clk";
reg = <0x0 0x03002000 0x0 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
gic: interrupt-controller {
compatible = "arm,cortex-a15-gic";
ranges;
#size-cells = <0x2>;
#address-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0x0 0x01F01000 0x0 0x1000>,
<0x0 0x01F02000 0x0 0x2000>;
};
psci {
migrate = <0xc4000005>;
cpu_on = <0xc4000003>;
cpu_off = <0x84000002>;
cpu_suspend = <0xc4000001>;
sys_poweroff = <0x84000008>;
sys_reset = <0x84000009>;
method = "smc";
compatible = "arm,psci-0.2", "arm,psci";
};
cpus {
#size-cells = <0x0>;
#address-cells = <0x1>;
A53_0: cpu@0 {
reg = <0x0>;
enable-method = "psci";
compatible = "arm,cortex-a53";
device_type = "cpu";
};
};
tpu {
compatible = "cvitek,tpu";
reg-names = "tdma", "tiu";
reg = <0x0 0x0C100000 0x0 0x1000>,
<0x0 0x0C101000 0x0 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
};
mon {
compatible = "cvitek,mon";
reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
reg = <0x0 0x01040000 0x0 0x1000>,
<0x0 0x08004000 0x0 0x1000>,
<0x0 0x08006000 0x0 0x1000>,
<0x0 0x08008000 0x0 0x1000>,
<0x0 0x0800A000 0x0 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
};
cvitek-ion {
compatible = "cvitek,cvitek-ion";
heap_carveout@0 {
compatible = "cvitek,carveout";
memory-region = <&ion_reserved>;
};
};
cviaudio_core {
compatible = "cvitek,audio";
};
reserved-memory {
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
cma_reserved: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x1000000>; // 16MB
alignment = <0x0 0x2000>; // 8KB
linux,cma-default;
};
ion_reserved: ion {
compatible = "ion-region";
size = <0x0 0x06000000>; // 96MB
};
};
timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
always-on;
clock-frequency = <25000000>;
compatible = "arm,armv8-timer";
};
sysdma_remap {
compatible = "cvitek,sysdma_remap";
reg = <0x0 0x03000154 0x0 0x10>;
ch-remap = <CVI_I2S0_RX CVI_I2S2_TX CVI_I2S1_RX CVI_I2S1_TX
CVI_SPI_NAND CVI_SPI_NAND CVI_I2S2_RX CVI_I2S3_TX>;
int_mux_base = <0x03000298>;
int_mux = <0x1FF>; /* enable bit [0..8] for CPU0(CA53) */
};
dmac: dma@0x4330000 {
compatible = "snps,dmac-bm";
reg = <0x0 0x04330000 0x0 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_sdma_axi";
clocks = <&clk CV181X_CLK_SDMA_AXI>;
dma-channels = /bits/ 8 <8>;
#dma-cells = <3>;
dma-requests = /bits/ 8 <16>;
chan_allocation_order = /bits/ 8 <0>;
chan_priority = /bits/ 8 <1>;
block_size = <1024>;
dma-masters = /bits/ 8 <2>;
data-width = <4 4>; /* bytes */
axi_tr_width = <4>; /* bytes */
block-ts = <15>;
};
watchdog0: cv-wd@0x3010000 {
compatible = "snps,dw-wdt";
reg = <0x0 0x03010000 0x0 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_WDT>;
clocks = <&pclk>;
};
pclk: pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
uart0: serial@04140000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x04140000 0x0 0x1000>;
clock-frequency = <25000000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
usb: usb@04340000 {
compatible = "cvitek,cv182x-usb";
reg = <0x0 0x04340000 0x0 0x10000>, <0x0 0x03006000 0x0 0x58>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "otg";
g-use-dma;
g-rx-fifo-size = <536>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <768 512 512 384 128 128>;
#if 0
clocks = <&clk CV181X_CLK_AXI4_USB>,
<&clk CV181X_CLK_APB_USB>,
<&clk CV181X_CLK_125M_USB>,
<&clk CV181X_CLK_33K_USB>,
<&clk CV181X_CLK_12M_USB>;
clock-names = "clk_axi", "clk_apb", "clk_125m", "clk_33k", "clk_12m";
vbus-gpio = <&portb 6 0>;
#endif
status = "okay";
};
memory {
reg = <0x0 0x80000000 0x0 0x80000000>;
device_type = "memory";
};
eth_csrclk: eth_csrclk {
clock-output-names = "eth_csrclk";
clock-frequency = <25000000>;
#clock-cells = <0x0>;
compatible = "fixed-clock";
};
eth_ptpclk: eth_ptpclk {
clock-output-names = "eth_ptpclk";
clock-frequency = <50000000>;
#clock-cells = <0x0>;
compatible = "fixed-clock";
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <1>;
snps,rd_osr_lmt = <2>;
snps,blen = <4 8 16 0 0 0 0>;
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
ethernet0: ethernet@4070000 {
compatible = "cvitek,ethernet";
reg = <0x0 0x04070000 0x0 0x10000>;
interrupt-names = "macirq";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "stmmaceth", "ptp_ref";
clocks = <&eth_csrclk>, <&eth_ptpclk>;
//phy-reset-gpios = <&porta 26 0>;
/* no hash filter and perfect filter support */
snps,multicast-filter-bins = <0>;
snps,perfect-filter-entries = <1>;
snps,txpbl = <8>;
snps,rxpbl = <8>;
snps,aal;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
};
gpio0: gpio@03020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x03020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
bank-name = "porta";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio3: gpio@03023000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x03023000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
portd: gpio-controller@2 {
compatible = "snps,dw-apb-gpio-port";
bank-name = "portd";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <12>;
reg = <0>;
interrupt-controller;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
};
i2c_srcclk: clk25mhz {
clock-output-names = "clk25mhz";
clock-frequency = <25000000>;
#clock-cells = <0x0>;
compatible = "fixed-clock";
};
audio_clock: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
#if 0
clock-frequency = <12288000>;
#else
clock-frequency = <24576000>;
#endif
};
#if 0
emmc:cv-emmc@4300000 {
compatible = "cvitek,cv181x-fpga-emmc";
reg = <0x0 0x4300000 0x0 0x1000>;
reg-names = "core_mem";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <4>;
non-removable;
max-frequency = <12000000>;
no-sdio;
no-sd;
};
#endif
sd:cv-sd@4310000 {
compatible = "cvitek,cv181x-fpga-sd";
reg = <0x0 0x4310000 0x0 0x1000>;
reg-names = "core_mem";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <4>;
max-frequency = <12000000>;
no-sdio;
no-mmc;
};
i2c0: i2c@04000000 {
compatible = "snps,designware-i2c";
clocks = <&i2c_srcclk>;
reg = <0x0 0x04000000 0x0 0x1000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
#size-cells = <0x0>;
#address-cells = <0x1>;
resets = <&rst RST_I2C0>;
reset-names = "i2c0";
};
i2c1: i2c@04010000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV181X_CLK_I2C>;
reg = <0x0 0x04010000 0x0 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
#size-cells = <0x0>;
#address-cells = <0x1>;
resets = <&rst RST_I2C1>;
reset-names = "i2c1";
};
i2c2: i2c@04020000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV181X_CLK_I2C>;
reg = <0x0 0x04020000 0x0 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
resets = <&rst RST_I2C2>;
reset-names = "i2c2";
};
i2c3: i2c@04030000 {
compatible = "snps,designware-i2c";
clocks = <&i2c_srcclk>;
reg = <0x0 0x04030000 0x0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
#size-cells = <0x0>;
#address-cells = <0x1>;
resets = <&rst RST_I2C3>;
reset-names = "i2c3";
};
i2c4: i2c@04040000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV181X_CLK_I2C>;
reg = <0x0 0x04040000 0x0 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
resets = <&rst RST_I2C4>;
reset-names = "i2c4";
};
spi0:spi0@04180000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x04180000 0x0 0x10000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CV181X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
};
spi1:spi1@04190000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x04190000 0x0 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CV181X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
};
spi2:spi2@041A0000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x041A0000 0x0 0x10000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CV181X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
};
spi3:spi3@041B0000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x041B0000 0x0 0x10000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CV181X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
#if 0
dmas = <&dmac 2 1 1
&dmac 3 1 1>;
dma-names = "rx", "tx";
capability = "txrx";
#endif
};
i2s_mclk: i2s_mclk {
clock-output-names = "i2s_mclk";
clock-frequency = <24576000>;
#clock-cells = <0x0>;
compatible = "fixed-clock";
};
i2s_subsys {
compatible = "cvitek,i2s_tdm_subsys";
reg = <0x0 0x04108000 0x0 0x100>;
clocks = <&i2s_mclk>, <&clk CV181X_CLK_A0PLL>,
<&clk CV181X_CLK_SDMA_AUD0>, <&clk CV181X_CLK_SDMA_AUD1>,
<&clk CV181X_CLK_SDMA_AUD2>, <&clk CV181X_CLK_SDMA_AUD3>;
clock-names = "i2sclk", "clk_a0pll",
"clk_sdma_aud0", "clk_sdma_aud1",
"clk_sdma_aud2", "clk_sdma_aud3";
master_base = <0x04110000>; /* I2S1 is master, only useful while using multi I2S IPs work on same IO */
};
i2s0: i2s@04100000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04100000 0x0 0x2000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <0>;
#sound-dai-cells = <0>;
dmas = <&dmac 0 1 1>; /* read channel */
dma-names = "rx";
capability = "rx"; /* I2S0 connect to internal ADC as RX */
mclk_out = "false";
};
i2s1: i2s@04110000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04110000 0x0 0x2000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <1>;
#sound-dai-cells = <0>;
dmas = <&dmac 2 1 1 /* read channel */
&dmac 3 1 1>; /* write channel */
dma-names = "rx", "tx";
capability = "txrx";
mclk_out = "false";
};
i2s2: i2s@04120000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04120000 0x0 0x2000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <2>;
#sound-dai-cells = <0>;
dmas = <&dmac 6 1 1 /* read channel */
&dmac 1 1 1>; /* write channel */
dma-names = "rx", "tx";
capability = "txrx";
mclk_out = "false";
};
i2s3: i2s@04130000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04130000 0x0 0x2000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <3>;
#sound-dai-cells = <0>;
dmas = <&dmac 7 1 1>; /* write channel */
dma-names = "tx";
capability = "tx"; /* I2S3 connect to internal DAC as TX */
mclk_out = "true";
};
adc: adc@0300A100 {
compatible = "cvitek,cv182xadc";
reg = <0x0 0x0300A100 0x0 0x100>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
clk_source = <0x04130000>; /* MCLK source is I2S3 */
};
dac: dac@0300A000 {
compatible = "cvitek,cv182xdac";
reg = <0x0 0x0300A000 0x0 0x100>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
};
pdm: pdm@0x041D0C00 {
compatible = "cvitek,cv1835pdm";
reg = <0x0 0x041D0C00 0x0 0x100>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
};
sound_adc {
compatible = "cvitek,cv182x-adc";
cvi,model = "CV182X";
cvi,card_name = "cv182x_adc";
};
sound_dac {
compatible = "cvitek,cv182x-dac";
cvi,model = "CV182X";
cvi,card_name = "cv182x_dac";
};
sound_PDM {
compatible = "cvitek,cv182x-pdm";
cvi,model = "CV182X";
cvi,card_name = "cv182x_internal_PDM";
};
mipi_rx: cif {
compatible = "cvitek,cif";
reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
<0x0 0x0a0c4000 0x0 0x2000>;
reg-names = "csi_mac0", "csi_wrap0", "csi_mac1";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "csi0", "csi1";
snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>;
resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
};
mipi_tx {
compatible = "cvitek,mipi_tx";
};
sys {
compatible = "cvitek,sys";
};
base {
compatible = "cvitek,base";
reg = <0x0 0x0a0c8000 0x0 0x20>;
reg-names = "vip_sys";
};
vi {
compatible = "cvitek,vi";
reg = <0x0 0x0a000000 0x0 0x80000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "isp";
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_AXI_VIP>,
<&clk CV181X_CLK_CSI_BE_VIP>, <&clk CV181X_CLK_ISP_TOP_VIP>,
<&clk CV181X_CLK_CSI_MAC0_VIP>, <&clk CV181X_CLK_CSI_MAC1_VIP>;
clock-names = "clk_sys_0", "clk_sys_1", "clk_sys_2",
"clk_axi", "clk_csi_be", "clk_isp_top",
"clk_csi_mac0", "clk_csi_mac1";
clock-freq-vip-sys1 = <300000000>;
};
ive {
compatible = "cvitek,ive";
reg-names = "ive_base";
reg = <0x0 0x0A0A0000 0x0 0x3100>;
interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
};
vpss {
compatible = "cvitek,vpss";
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
reg-names = "sc","dphy";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sc";
clock-freq-vip-sys1 = <300000000>;
};
vo {
compatible = "cvitek,vo";
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
reg-names = "sc","dphy";
};
dwa {
compatible = "cvitek,dwa";
reg = <0x0 0x0a0c0000 0x0 0x1000>;
reg-names = "dwa";
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dwa";
clock-names = "clk_dwa";
clock-freq-vip-sys1 = <300000000>;
};
rgn {
compatible = "cvitek,rgn";
};
vcodec {
compatible = "cvitek,fpga-vcodec";
reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>,
<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
reg-names = "h265","h264","vc_ctrl","vc_sbm","vc_addr_remap";
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "h265","h264";
};
jpu {
compatible = "cvitek,fpga-jpeg";
reg = <0x0 0x0B000000 0x0 0x300>,<0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>;
reg-names = "jpeg","vc_ctrl","vc_sbm";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "jpeg";
reset = <&rst RST_JPEG>;
reset-names = "jpeg";
};
cvi_vc_drv {
compatible = "cvitek,cvi_vc_drv";
reg = <0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
reg-names = "vc_ctrl","vc_sbm","vc_addr_remap";
};
aliases {
serial0 = &uart0;
ethernet0 = &ethernet0;
};
chosen {
stdout-path = "serial0"; // "serial0:115200n8", no arguments means no re-initialization
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A53_0>;
};
rtos_cmdqu {
compatible = "cvitek,rtos_cmdqu";
reg = <0x0 0x01900000 0x0 0x1000>;
reg-names = "mailbox";
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mailbox";
};
};

327
build/boards/cv181x/cv181x_fpga/linux/cvitek_cv181x_fpga_defconfig
View File

@ -1,327 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_TASKSTATS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
CONFIG_PROFILING=y
CONFIG_ARM_LPAE=y
# CONFIG_VDSO is not set
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_OABI_COMPAT=y
CONFIG_FORCE_MAX_ZONEORDER=10
# CONFIG_ATAGS is not set
CONFIG_KEXEC=y
CONFIG_CRASH_DUMP=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_PM_TEST_SUSPEND=y
CONFIG_ARCH_CVITEK=y
CONFIG_ARCH_CV181X=y
CONFIG_ARCH_CVITEK_CHIP="cv181x"
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_NET_SCHED=y
CONFIG_CFG80211=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=2
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_CVSNFC=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_DWMAC_GENERIC is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_CVITEK_PHY=y
CONFIG_CVITEK_PHY_UAPS=y
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
# CONFIG_WLAN_VENDOR_BROADCOM is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
# CONFIG_WLAN_VENDOR_MARVELL is not set
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
# CONFIG_WLAN_VENDOR_REALTEK is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_DW=y
CONFIG_HW_RANDOM=y
CONFIG_CVITEK_PINCTRL_CV1835=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
CONFIG_THERMAL=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
CONFIG_VIDEO_CVITEK=m
CONFIG_VIDEO_CVITEK_CIF=m
CONFIG_VIDEO_CVITEK_SNS_I2C=m
CONFIG_VIDEO_CVITEK_MIPI_TX=m
CONFIG_FB=y
CONFIG_FB_CVITEK=m
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_CV182X_CV182XADC=y
CONFIG_SND_SOC_CV182X_CV182XDAC=y
CONFIG_SND_CV1835_I2S=y
CONFIG_SND_SOC_CV182XADC=y
CONFIG_SND_SOC_CV182XDAC=y
CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
CONFIG_CV1835_I2S_SUBSYS=y
CONFIG_USB=y
CONFIG_USB_OTG=y
CONFIG_USB_OTG_FSM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_REALTEK=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_ISD200=y
CONFIG_USB_STORAGE_USBAT=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_STORAGE_JUMPSHOT=y
CONFIG_USB_STORAGE_ALAUDA=y
CONFIG_USB_STORAGE_ONETOUCH=y
CONFIG_USB_STORAGE_KARMA=y
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
CONFIG_USB_STORAGE_ENE_UB6250=y
CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_U_AUDIO=y
CONFIG_USB_F_SERIAL=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_EEM=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_F_UAC1=y
CONFIG_USB_F_UVC=y
CONFIG_USB_UAS=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_GADGET=y
CONFIG_U_SERIAL_CONSOLE=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_INPUT_EVDEV=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_CVI=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_STAGING=y
CONFIG_ION=y
CONFIG_ION_SYSTEM_HEAP=y
CONFIG_ION_CARVEOUT_HEAP=y
CONFIG_ION_CMA_HEAP=y
CONFIG_CVI_WIFI_PIN=y
CONFIG_PWM=y
CONFIG_ANDROID=y
# CONFIG_GATOR is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_ENCRYPTION=y
CONFIG_OVERLAY_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_UBIFS_FS=y
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_ZLIB is not set
CONFIG_SQUASHFS_XZ=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_3=y
CONFIG_NLS_UTF8=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
# CONFIG_CRYPTO_ECHAINIV is not set
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_ARC4=y
# CONFIG_CRYPTO_HW is not set
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_SCHEDSTATS=y
CONFIG_SCHED_STACK_END_CHECK=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
CONFIG_DEBUG_LIST=y
CONFIG_IRQSOFF_TRACER=y
CONFIG_SCHED_TRACER=y
CONFIG_HWLAT_TRACER=y
CONFIG_FTRACE_SYSCALLS=y
CONFIG_STACK_TRACER=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_FUNCTION_PROFILER=y
#
# Network configurations
#
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_HAVE_NET_DSA=y
CONFIG_PAGE_POOL=y
CONFIG_REGMAP_MMIO=y
CONFIG_OF_NET=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_CVITEK=y
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_FIXED_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_OF_MDIO=y
CONFIG_MDIO_DEVRES=y
#
# sysDMA Configurations
#
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC_CVITEK=y
CONFIG_CV1835_SYSDMA_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_HAS_DMA=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
#
# SPI
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_DW_MMIO is not set
# CONFIG_SPI_SPIDEV is not set

1
build/boards/cv181x/cv181x_fpga/memmap.py
View File

@ -1 +0,0 @@
../../default/memmap/cv181x/memmap_ddr_4g.py

11
build/boards/cv181x/cv181x_fpga/partition/partition_emmc.xml
View File

@ -1,11 +0,0 @@
<physical_partition type="emmc">
<partition label="BOOT" size_in_kb="8192" file="boot.emmc" />
<partition label="MISC" size_in_kb="512" file="logo.jpg" />
<!-- Beware that in emmc u-boot environment should be 0x40000 alignment -->
<partition label="ENV" size_in_kb="128" file="" />
<partition label="ROOTFS" size_in_kb="70656" file="rootfs.emmc" />
<partition label="SYSTEM" size_in_kb="40960" file="system.emmc" type="ext4" />
<partition label="CFG" size_in_kb="15240" file="cfg.emmc" mountpoint="/mnt/cfg" type="ext4" />
<partition label="DATA" size_in_kb="3145728" file="" mountpoint="/mnt/data" type="ext4"/>
</physical_partition>

1
build/boards/cv181x/cv181x_fpga/partition/partition_none.xml
View File

@ -1 +0,0 @@
../../../default/partition/partition_none.xml

1
build/boards/cv181x/cv181x_fpga/partition/partition_spinor.xml
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@ -1 +0,0 @@
../../../default/partition/partition_spinor_16mb_cv181x.xml

4
build/boards/cv181x/cv181x_fpga/u-boot/cvi_board_init.c
View File

@ -1,4 +0,0 @@
int cvi_board_init(void)
{
return 0;
}

1
build/boards/cv181x/cv181x_fpga/u-boot/cvitek.h
View File

@ -1 +0,0 @@
../../../default/u-boot/cvitek_cv181x.h

60
build/boards/cv181x/cv181x_fpga/u-boot/cvitek_cv181x_fpga_defconfig
View File

@ -1,60 +0,0 @@
CONFIG_ARM=y
CONFIG_TARGET_CVITEK=y
CONFIG_TARGET_CVITEK_CV181X=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_BOOTMAPSZ=0x40000000
CONFIG_IDENT_STRING=" cvitek_cv181x"
CONFIG_ARMV8_SET_SMPEN=y
CONFIG_TARGET_CVITEK_CV181X_FPGA=y
CONFIG_DEFAULT_DEVICE_TREE="cv181x_fpga"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="cv181x# "
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_PHYLIB=y
# CONFIG_PHY_BROADCOM is not set
CONFIG_PHY_SMSC=y
# CONFIG_PHY_FIXED is not set
CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CVITEK=y
CONFIG_SYS_NS16550=y
CONFIG_LZ4=y
CONFIG_LZMA=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_CVI_UPDATE=y
CONFIG_CMD_CVI_SD_UPDATE=y
CONFIG_CMD_CVI_REBOOT=y
CONFIG_CMD_NFS=y
CONFIG_CMD_PART=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_MISC is not set
CONFIG_MTD=y
CONFIG_SPI=y
CONFIG_SPI_FLASH=y

6
build/boards/cv181x/cv181x_fpga_c906/config.json
View File

@ -1,6 +0,0 @@
{
"ddr_cfg_list": [
""
],
"board_information": "FPGA"
}

35
build/boards/cv181x/cv181x_fpga_c906/cv181x_fpga_c906_defconfig
View File

@ -1,35 +0,0 @@
CONFIG_CHIP_cv181x=y
CONFIG_ARCH="riscv"
CONFIG_BOARD_fpga_c906=y
CONFIG_DDR_CFG_none=y
CONFIG_CROSS_COMPILE="riscv64-unknown-linux-gnu-"
CONFIG_KERNEL_SRC_5.10=y
CONFIG_CROSS_COMPILE_KERNEL="riscv64-unknown-linux-gnu-"
CONFIG_KERNEL_ENTRY_HACK=y
CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80200000"
CONFIG_TOOLCHAIN_GLIBC_RISCV64=y
CONFIG_STORAGE_TYPE_none=y
CONFIG_BOOT_IMAGE_SINGLE_DTB=y
CONFIG_UBOOT_2021_10=y
CONFIG_SENSOR_SONY_IMX327_FPGA=y
# CONFIG_ROOTFS_OVERLAYFS is not set
# CONFIG_TARGET_PACKAGE_CVITRACER is not set
# CONFIG_TARGET_PACKAGE_GDBSERVER is not set
# CONFIG_TARGET_PACKAGE_LIBCRYPTO is not set
# CONFIG_TARGET_PACKAGE_LIBZ is not set
# CONFIG_TARGET_PACKAGE_OTASERVER is not set
# CONFIG_TARGET_PACKAGE_RSYSLOG is not set
# CONFIG_TARGET_PACKAGE_CRONTABS is not set
# CONFIG_TARGET_PACKAGE_GATORD is not set
#
# Panel settings
#
#
# Panel support list
#
CONFIG_MIPI_PANEL_ILI9881C=y

696
build/boards/cv181x/cv181x_fpga_c906/linux/cv181x_fpga_c906.dts
View File

@ -1,696 +0,0 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/cv181x-resets.h>
#include <dt-bindings/clock/cv181x-clock.h>
#include <dt-bindings/dma/cv181x-dmamap.h>
#include <dt-bindings/gpio/gpio.h>
/dts-v1/;
/ {
compatible = "cvitek,cv181x";
model = "riscv-c906,fpga";
#address-cells = <0x02>;
#size-cells = <0x02>;
rst: reset-controller {
#reset-cells = <1>;
compatible = "cvitek,reset";
reg = <0x0 0x03003000 0x0 0x10>;
};
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "osc";
};
clk: clock-controller {
compatible = "cvitek,cv181x-clk";
reg = <0x0 0x03002000 0x0 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
reserved-memory {
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
cma_reserved: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x1000000>; // 2MB
alignment = <0x0 0x2000>; // 2MB
linux,cma-default;
};
ion_reserved: ion {
compatible = "ion-region";
size = <0x0 0x04000000>; // 71MB
};
vip_reserved: vip {
/* <start, length> pair
* and restrict to 4G address range
*/
size = <0x0 0x02000000>; // 32MB
no-map;
};
vcodec_reserved: vcodec {
/* <start, length> pair
* and restrict to 512M address range
*/
alloc-ranges = <0x0 0x80000000 0 0x20000000>;
size = <0x0 0x200000>; // 2MB
alignment = <0x0 0x1000>; // 4KB
no-map;
};
};
mon {
compatible = "cvitek,mon";
reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
reg = <0x0 0x01040000 0x0 0x1000>,
<0x0 0x08004000 0x0 0x1000>,
<0x0 0x08006000 0x0 0x1000>,
<0x0 0x08008000 0x0 0x1000>,
<0x0 0x0800A000 0x0 0x1000>;
interrupt-names = "mon_irq";
interrupt-parent = <&plic0>;
interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
};
tpu {
compatible = "cvitek,tpu";
reg-names = "tdma", "tiu";
reg = <0x0 0x0C100000 0x0 0x1000>,
<0x0 0x0C101000 0x0 0x1000>;
interrupt-names = "tiu_irq", "tdma_irq";
interrupt-parent = <&plic0>;
interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
<76 IRQ_TYPE_LEVEL_HIGH>;
};
cvitek-ion {
compatible = "cvitek,cvitek-ion";
heap_carveout@0 {
compatible = "cvitek,carveout";
memory-region = <&ion_reserved>;
};
};
chosen {
bootargs = "console=ttyS0,115200n8 debug loglevel=8,initcall_debug=8 root=/dev/ init=/sbin/init earlycon=sbi";
stdout-path = "serial0";
};
uart0: serial@4140000 {
interrupt-parent = <&plic0>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <25000000>;
current-speed = <115200>;
reg = <0x00 0x4140000 0x00 0x100>;
compatible = "snps,dw-apb-uart";
reg-shift = <2>;
reg-io-width = <4>;
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
timebase-frequency = <25000000>;
cpu-map {
cluster0 {
core0 {
cpu = <0x01>;
};
};
};
cpu@0 {
device_type = "cpu";
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdvcsu";
mmu-type = "riscv,sv39";
clock-frequency = <25000000>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <0x01>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00 0x80000000 0x00 0x40000000>;
};
soc {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "simple-bus";
ranges;
plic0: interrupt-controller@70000000 {
riscv,ndev = <101>;
riscv,max-priority = <0x07>;
reg-names = "control";
reg = <0x00 0x70000000 0x00 0x4000000>;
interrupts-extended = <&cpu0_intc 0xffffffff &cpu0_intc 0x09>;
interrupt-controller;
compatible = "riscv,plic0";
#interrupt-cells = <0x02>;
#address-cells = <0x00>;
};
clint@74000000 {
interrupts-extended = <&cpu0_intc 0x03 &cpu0_intc 0x07>;
reg = <0x00 0x74000000 0x00 0x10000>;
compatible = "riscv,clint0";
clint,has-no-64bit-mmio;
};
};
sysdma_remap {
compatible = "cvitek,sysdma_remap";
reg = <0x0 0x03000154 0x0 0x10>;
ch-remap = <CVI_I2S0_RX CVI_I2S2_TX CVI_I2S1_RX CVI_I2S1_TX
CVI_SPI_NAND CVI_SPI_NAND CVI_I2S2_RX CVI_I2S3_TX>;
int_mux_base = <0x03000298>;
int_mux = <0x7FC00>; /* enable bit [10..18] for CPU1(906B) */
};
dmac: dma@0x4330000 {
compatible = "snps,dmac-bm";
reg = <0x0 0x04330000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_sdma_axi";
clocks = <&clk CV181X_CLK_SDMA_AXI>;
dma-channels = /bits/ 8 <8>;
#dma-cells = <3>;
dma-requests = /bits/ 8 <16>;
chan_allocation_order = /bits/ 8 <0>;
chan_priority = /bits/ 8 <1>;
block_size = <1024>;
dma-masters = /bits/ 8 <2>;
data-width = <4 4>; /* bytes */
axi_tr_width = <4>; /* bytes */
block-ts = <15>;
};
usb: usb@04340000 {
compatible = "cvitek,cv182x-usb";
reg = <0x0 0x04340000 0x0 0x10000>, <0x0 0x03006000 0x0 0x58>;
interrupt-parent = <&plic0>;
interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "otg";
g-use-dma;
g-rx-fifo-size = <536>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <768 512 512 384 128 128>;
#if 0
clocks = <&clk CV182X_CLK_AXI4_USB>,
<&clk CV182X_CLK_APB_USB>,
<&clk CV182X_CLK_125M_USB>,
<&clk CV182X_CLK_33K_USB>,
<&clk CV182X_CLK_12M_USB>;
clock-names = "clk_axi", "clk_apb", "clk_125m", "clk_33k", "clk_12m";
vbus-gpio = <&portb 6 0>;
#endif
status = "okay";
};
spinand:cv-spinf@4060000 {
compatible = "cvitek,cv1835-spinf";
reg = <0x0 0x4060000 0x0 0x1000>;
reg-names = "core_mem";
interrupt-parent = <&plic0>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <4>;
dmas = <&dmac 4 1 1
&dmac 5 1 1>;
dma-names = "rx","tx";
};
i2c0: i2c@04000000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV181X_CLK_I2C>;
reg = <0x0 0x04000000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
#size-cells = <0x0>;
#address-cells = <0x1>;
resets = <&rst RST_I2C0>;
reset-names = "i2c0";
};
i2c1: i2c@04010000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV181X_CLK_I2C>;
reg = <0x0 0x04010000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
#size-cells = <0x0>;
#address-cells = <0x1>;
resets = <&rst RST_I2C1>;
reset-names = "i2c1";
};
i2c2: i2c@04020000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV181X_CLK_I2C>;
reg = <0x0 0x04020000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <100000>;
resets = <&rst RST_I2C2>;
reset-names = "i2c2";
};
i2c3: i2c@04030000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV181X_CLK_I2C>;
reg = <0x0 0x04030000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
resets = <&rst RST_I2C3>;
reset-names = "i2c3";
};
i2c4: i2c@04040000 {
compatible = "snps,designware-i2c";
clocks = <&clk CV181X_CLK_I2C>;
reg = <0x0 0x04040000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
resets = <&rst RST_I2C4>;
reset-names = "i2c4";
};
spi0:spi0@04180000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x04180000 0x0 0x10000>;
interrupt-parent = <&plic0>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CV181X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
};
spi1:spi1@04190000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x04190000 0x0 0x10000>;
interrupt-parent = <&plic0>;
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CV181X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
};
spi2:spi2@041A0000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x041A0000 0x0 0x10000>;
interrupt-parent = <&plic0>;
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CV181X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
};
spi3:spi3@041B0000 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x041B0000 0x0 0x10000>;
interrupt-parent = <&plic0>;
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CV181X_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
#if 0
dmas = <&dmac 2 1 1
&dmac 3 1 1>;
dma-names = "rx", "tx";
capability = "txrx";
#endif
};
eth_csrclk: eth_csrclk {
clock-output-names = "eth_csrclk";
clock-frequency = <25000000>;
#clock-cells = <0x0>;
compatible = "fixed-clock";
};
eth_ptpclk: eth_ptpclk {
clock-output-names = "eth_ptpclk";
clock-frequency = <50000000>;
#clock-cells = <0x0>;
compatible = "fixed-clock";
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <1>;
snps,rd_osr_lmt = <2>;
snps,blen = <4 8 16 0 0 0 0>;
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
ethernet0: ethernet@4070000 {
compatible = "cvitek,ethernet";
reg = <0x0 0x04070000 0x0 0x10000>;
interrupt-names = "macirq";
interrupt-parent = <&plic0>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "stmmaceth", "ptp_ref";
clocks = <&eth_csrclk>, <&eth_ptpclk>;
//phy-reset-gpios = <&porta 26 0>;
/* no hash filter and perfect filter support */
snps,multicast-filter-bins = <0>;
snps,perfect-filter-entries = <1>;
snps,txpbl = <8>;
snps,rxpbl = <8>;
snps,aal;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
};
gpio0: gpio@03020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x03020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
bank-name = "porta";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
interrupt-parent = <&plic0>;
interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
};
};
#if 0
emmc:cv-emmc@4300000 {
compatible = "cvitek,cv181x-fpga-emmc";
reg = <0x0 0x04300000 0x0 0x1000>;
reg-names = "core_mem";
interrupt-parent = <&plic0>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <4>;
non-removable;
no-sdio;
no-sd;
src-frequency = <25000000>;
min-frequency = <200000>;
max-frequency = <20000000>;
64_addressing;
reset_tx_rx_phy;
};
#endif
sd:cv-sd@4310000 {
compatible = "cvitek,cv181x-fpga-sd";
reg = <0x0 0x04310000 0x0 0x1000>;
reg-names = "core_mem";
interrupt-parent = <&plic0>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <4>;
no-sdio;
no-mmc;
src-frequency = <25000000>;
min-frequency = <200000>;
max-frequency = <20000000>;
64_addressing;
reset_tx_rx_phy;
reset-names = "sdhci";
};
i2s_mclk: i2s_mclk {
clock-output-names = "i2s_mclk";
clock-frequency = <24576000>;
#clock-cells = <0x0>;
compatible = "fixed-clock";
};
i2s_subsys {
compatible = "cvitek,i2s_tdm_subsys";
reg = <0x0 0x04108000 0x0 0x100>;
clocks = <&i2s_mclk>, <&clk CV181X_CLK_A0PLL>,
<&clk CV181X_CLK_SDMA_AUD0>, <&clk CV181X_CLK_SDMA_AUD1>,
<&clk CV181X_CLK_SDMA_AUD2>, <&clk CV181X_CLK_SDMA_AUD3>;
clock-names = "i2sclk", "clk_a0pll",
"clk_sdma_aud0", "clk_sdma_aud1",
"clk_sdma_aud2", "clk_sdma_aud3";
master_base = <0x04110000>; /* I2S1 is master, only useful while using multi I2S IPs work on same IO */
};
i2s0: i2s@04100000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04100000 0x0 0x2000>;
interrupt-parent = <&plic0>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <0>;
#sound-dai-cells = <0>;
dmas = <&dmac 0 1 1>; /* read channel */
dma-names = "rx";
capability = "rx"; /* I2S0 connect to internal ADC as RX */
mclk_out = "false";
};
i2s1: i2s@04110000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04110000 0x0 0x2000>;
interrupt-parent = <&plic0>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <1>;
#sound-dai-cells = <0>;
dmas = <&dmac 2 1 1 /* read channel */
&dmac 3 1 1>; /* write channel */
dma-names = "rx", "tx";
capability = "txrx";
mclk_out = "false";
};
i2s2: i2s@04120000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04120000 0x0 0x2000>;
interrupt-parent = <&plic0>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <2>;
#sound-dai-cells = <0>;
dmas = <&dmac 6 1 1 /* read channel */
&dmac 1 1 1>; /* write channel */
dma-names = "rx", "tx";
capability = "txrx";
mclk_out = "false";
};
i2s3: i2s@04130000 {
compatible = "cvitek,cv1835-i2s";
reg = <0x0 0x04130000 0x0 0x2000>;
interrupt-parent = <&plic0>;
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
dev-id = <3>;
#sound-dai-cells = <0>;
dmas = <&dmac 7 1 1>; /* write channel */
dma-names = "tx";
capability = "tx"; /* I2S3 connect to internal DAC as TX */
mclk_out = "true";
};
adc: adc@0300A100 {
compatible = "cvitek,cv182xadc";
reg = <0x0 0x0300A100 0x0 0x100>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
clk_source = <0x04130000>; /* MCLK source is I2S3 */
};
dac: dac@0300A000 {
compatible = "cvitek,cv182xdac";
reg = <0x0 0x0300A000 0x0 0x100>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
};
pdm: pdm@0x041D0C00 {
compatible = "cvitek,cv1835pdm";
reg = <0x0 0x041D0C00 0x0 0x100>;
clocks = <&i2s_mclk 0>;
clock-names = "i2sclk";
};
sound_adc {
compatible = "cvitek,cv182x-adc";
cvi,model = "CV182X";
cvi,card_name = "cv182x_adc";
};
sound_dac {
compatible = "cvitek,cv182x-dac";
cvi,model = "CV182X";
cvi,card_name = "cv182x_dac";
};
sound_PDM {
compatible = "cvitek,cv182x-pdm";
cvi,model = "CV182X";
cvi,card_name = "cv182x_internal_PDM";
};
rtos_cmdqu {
compatible = "cvitek,rtos_cmdqu";
reg = <0x0 0x01900000 0x0 0x1000>;
reg-names = "mailbox";
interrupt-parent = <&plic0>;
interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mailbox";
};
vcodec {
compatible = "cvitek,fpga-vcodec";
memory-region = <&vcodec_reserved>;
reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>,
<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
reg-names = "h265","h264","vc_ctrl","vc_sbm","vc_addr_remap";
interrupt-parent = <&plic0>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>,
<21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "h265","h264";
};
jpu {
compatible = "cvitek,fpga-jpeg";
reg = <0x0 0x0B000000 0x0 0x300>,<0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>;
reg-names = "jpeg","vc_ctrl","vc_sbm";
interrupt-parent = <&plic0>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "jpeg";
};
mipi_rx: cif {
compatible = "cvitek,cif";
reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
<0x0 0x0a0c4000 0x0 0x2000>;
reg-names = "csi_mac0", "csi_wrap0", "csi_mac1";
interrupt-parent = <&plic0>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "csi0", "csi1";
snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>;
resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
};
mipi_tx {
compatible = "cvitek,mipi_tx";
};
sys {
compatible = "cvitek,sys";
};
base {
compatible = "cvitek,base";
reg = <0x0 0x0a0c8000 0x0 0x20>;
reg-names = "vip_sys";
};
vi {
compatible = "cvitek,vi";
reg = <0x0 0x0a000000 0x0 0x80000>;
interrupt-parent = <&plic0>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "isp";
};
vpss {
compatible = "cvitek,vpss";
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
interrupt-parent = <&plic0>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
reg-names = "sc","dphy";
interrupt-names = "sc";
};
ive {
compatible = "cvitek,ive";
reg-names = "ive_base";
reg = <0x0 0x0A0A0000 0x0 0x3100>;
interrupt-names = "ive_irq";
interrupt-parent = <&plic0>;
interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
};
vo {
compatible = "cvitek,vo";
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
reg-names = "sc","dphy";
};
dwa {
compatible = "cvitek,dwa";
reg = <0x0 0x0a0c0000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
reg-names = "dwa";
interrupt-names = "dwa";
};
rgn {
compatible = "cvitek,rgn";
};
aliases {
serial0 = &uart0;
ethernet0 = &ethernet0;
};
};

315
build/boards/cv181x/cv181x_fpga_c906/linux/cvitek_cv181x_fpga_c906_defconfig
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@ -1,315 +0,0 @@
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_WATCH_QUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_DEBUG=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_GZIP=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
# CONFIG_INITRAMFS_COMPRESSION_XZ is not set
# CONFIG_INITRAMFS_COMPRESSION_LZO is not set
# CONFIG_INITRAMFS_COMPRESSION_LZ4 is not set
# CONFIG_INITRAMFS_COMPRESSION_ZSTD is not set
# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
CONFIG_BOOT_CONFIG=y
CONFIG_EXPERT=y
CONFIG_BPF_SYSCALL=y
CONFIG_PERF_EVENTS=y
CONFIG_PROFILING=y
CONFIG_ARCH_CVITEK=y
CONFIG_SOC_THEAD=y
# CONFIG_RISCV_SWIOTLB is not set
CONFIG_VECTOR=y
CONFIG_VECTOR_0_7=y
# CONFIG_COMPAT is not set
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HZ_100=y
# CONFIG_EFI is not set
CONFIG_PM=y
CONFIG_ARCH_CVITEK_CHIP="cv181x"
CONFIG_KPROBES=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_NET_SCHED=y
CONFIG_CFG80211=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DEBUG_DRIVER=y
CONFIG_DEBUG_DEVRES=y
CONFIG_TEST_ASYNC_DRIVER_PROBE=m
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_OF_OVERLAY=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_VIRTIO_BLK=m
CONFIG_INPUT_MOUSEDEV=n
CONFIG_INPUT_EVDEV=n
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO_LIBPS2=n
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_TTY_PRINTK=y
CONFIG_VIRTIO_CONSOLE=m
CONFIG_HW_RANDOM=y
CONFIG_PINCTRL=y
CONFIG_CVITEK_PINCTRL_CV1835=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
# CONFIG_GPIO_CDEV is not set
CONFIG_GPIO_DWAPB=y
# CONFIG_HWMON is not set
CONFIG_THERMAL=n
CONFIG_THERMAL_STATISTICS=n
CONFIG_THERMAL_WRITABLE_TRIPS=n
CONFIG_THERMAL_EMULATION=n
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_ICE_WDT is not set
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_FB=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
CONFIG_USB=y
CONFIG_USB_OTG=y
CONFIG_USB_OTG_FSM=y
CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y
CONFIG_U_SERIAL_CONSOLE=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_CVI=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
# CONFIG_RTC_INTF_SYSFS is not set
# CONFIG_RTC_INTF_PROC is not set
# CONFIG_RTC_INTF_DEV is not set
CONFIG_SYNC_FILE=y
# CONFIG_VIRTIO_MENU is not set
# CONFIG_VHOST_MENU is not set
CONFIG_STAGING=y
CONFIG_ION=y
CONFIG_ION_SYSTEM_HEAP=y
CONFIG_ION_CARVEOUT_HEAP=y
CONFIG_ION_CMA_HEAP=y
CONFIG_PWM=y
CONFIG_SIFIVE_PLIC=y
CONFIG_RESET_CONTROLLER=y
CONFIG_ANDROID=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_OVERLAY_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_UBIFS_FS=y
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_ZLIB is not set
CONFIG_SQUASHFS_XZ=y
CONFIG_NFS_FS=y
# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
CONFIG_CRYPTO_GHASH=n
CONFIG_CRYPTO_MD5=n
CONFIG_CRYPTO_SHA1=n
CONFIG_CRYPTO_AES=n
CONFIG_CRYPTO_DES=n
CONFIG_CRYPTO_DRBG_MENU=n
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=m
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=n
CONFIG_DMA_CMA=y
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
# CONFIG_SYMBOLIC_ERRNAME is not set
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_PAGE_REF=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_SCHED_STACK_END_CHECK=y
CONFIG_DEBUG_VM=y
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_DEBUG_VIRTUAL=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_SCHEDSTATS=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_CVITEK_PINCTRL_CV1835=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
CONFIG_VIDEO_CVITEK=m
CONFIG_VIDEO_CVITEK_CIF=m
CONFIG_VIDEO_CVITEK_SNS_I2C=m
CONFIG_VIDEO_CVITEK_MIPI_TX=m
CONFIG_FB_CVITEK=m
CONFIG_HID=n
CONFIG_HID_GENERIC=n
CONFIG_USB_HID=n
CONFIG_USB_OTG=n
CONFIG_STRICT_KERNEL_RWX=n
CONFIG_IPV6=n
#
# Network configurations
#
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_HAVE_NET_DSA=y
CONFIG_PAGE_POOL=y
CONFIG_REGMAP_MMIO=y
CONFIG_OF_NET=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_CVITEK=y
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_FIXED_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_OF_MDIO=y
CONFIG_MDIO_DEVRES=y
#
# sysDMA Configurations
#
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC_CVITEK=y
CONFIG_CV1835_SYSDMA_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_HAS_DMA=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
#
# SPI
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_DW_MMIO is not set
# CONFIG_SPI_SPIDEV is not set
#
# NAND driver
#
# CONFIG_MTD_NAND_ECC is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_NAND_CVSNFC is not set
# CONFIG_MTD_RAW_NAND is not set
#
# AUDIO
#
CONFIG_SND_CV1835_I2S=y
CONFIG_CV1835_I2S_SUBSYS=y
# CONFIG_SND_SOC_CV1835_CONCURRENT_I2S is not set
CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
#
# AUDIO - INTERNAL ADC AND DAC
#
CONFIG_SND_SOC_CV182X_CV182XADC=y
CONFIG_SND_SOC_CV182XADC=y
CONFIG_SND_SOC_CV182X_CV182XDAC=y
CONFIG_SND_SOC_CV182XDAC=y
# Ftrace
CONFIG_FUNCTION_TRACER=y
CONFIG_FUNCTION_GRAPH_TRACER=y
CONFIG_STACK_TRACER=y
CONFIG_DYNAMIC_FTRACE=y
CONFIG_DEBUG_KMEMLEAK=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y

1
build/boards/cv181x/cv181x_fpga_c906/memmap.py
View File

@ -1 +0,0 @@
../../default/memmap/cv181x/memmap_ddr_4g.py

11
build/boards/cv181x/cv181x_fpga_c906/partition/partition_emmc.xml
View File

@ -1,11 +0,0 @@
<physical_partition type="emmc">
<partition label="BOOT" size_in_kb="8192" file="boot.emmc" />
<partition label="MISC" size_in_kb="512" file="logo.jpg" />
<!-- Beware that in emmc u-boot environment should be 0x40000 alignment -->
<partition label="ENV" size_in_kb="128" file="" />
<partition label="ROOTFS" size_in_kb="70656" file="rootfs.emmc" />
<partition label="SYSTEM" size_in_kb="40960" file="system.emmc" type="ext4" />
<partition label="CFG" size_in_kb="15240" file="cfg.emmc" mountpoint="/mnt/cfg" type="ext4" />
<partition label="DATA" size_in_kb="3145728" file="" mountpoint="/mnt/data" type="ext4"/>
</physical_partition>

1
build/boards/cv181x/cv181x_fpga_c906/partition/partition_none.xml
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@ -1 +0,0 @@
../../../default/partition/partition_none.xml

1
build/boards/cv181x/cv181x_fpga_c906/partition/partition_spinor.xml
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@ -1 +0,0 @@
../../../default/partition/partition_spinor_16mb_cv181x.xml

4
build/boards/cv181x/cv181x_fpga_c906/u-boot/cvi_board_init.c
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@ -1,4 +0,0 @@
int cvi_board_init(void)
{
return 0;
}

1
build/boards/cv181x/cv181x_fpga_c906/u-boot/cvitek.h
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@ -1 +0,0 @@
../../../default/u-boot/cvitek_cv181x.h

6
build/boards/cv181x/cv181x_palladium/config.json
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@ -1,6 +0,0 @@
{
"ddr_cfg_list": [
""
],
"board_information": "PALLADIUM"
}

16
build/boards/cv181x/cv181x_palladium/cv181x_palladium_defconfig
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@ -1,16 +0,0 @@
CONFIG_CHIP_cv181x=y
CONFIG_ARCH="arm"
CONFIG_BOARD_palladium=y
CONFIG_DDR_CFG_none=y
CONFIG_TOOLCHAIN_GLIBC_ARM=y
CONFIG_STORAGE_TYPE_spinor=y
CONFIG_CROSS_COMPILE_KERNEL="arm-linux-gnueabihf-"
CONFIG_KERNEL_ENTRY_HACK=y
CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80108000"
CONFIG_BOOT_IMAGE_SINGLE_DTB=y
# CONFIG_ROOTFS_OVERLAYFS is not set
# CONFIG_TARGET_PACKAGE_GDBSERVER is not set
# CONFIG_TARGET_PACKAGE_NANOMSG is not set
# CONFIG_TARGET_PACKAGE_OTASERVER is not set
# CONFIG_TARGET_PACKAGE_RSYSLOG is not set

270
build/boards/cv181x/cv181x_palladium/linux/cv181x_palladium.dts
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@ -1,270 +0,0 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/cv1835-resets.h>
#include <dt-bindings/sound/cv1835-audio.h>
/dts-v1/;
/memreserve/ 0x80000000 0x0000000000080000; // ATF BL31 + BL32
/ {
compatible = "linux,dummy-virt";
#size-cells = <0x2>;
#address-cells = <0x2>;
interrupt-parent = <&gic>;
rst: reset-controller {
#reset-cells = <1>;
compatible = "cvitek,reset";
reg = <0x0 0x03003000 0x0 0x10>;
};
gic: interrupt-controller {
compatible = "arm,cortex-a15-gic";
ranges;
#size-cells = <0x2>;
#address-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0x0 0x01F01000 0x0 0x1000>,
<0x0 0x01F02000 0x0 0x2000>;
};
psci {
migrate = <0xc4000005>;
cpu_on = <0xc4000003>;
cpu_off = <0x84000002>;
cpu_suspend = <0xc4000001>;
sys_poweroff = <0x84000008>;
sys_reset = <0x84000009>;
method = "smc";
compatible = "arm,psci-0.2", "arm,psci";
};
cpus {
#size-cells = <0x0>;
#address-cells = <0x1>;
A53_0: cpu@0 {
reg = <0x0>;
enable-method = "psci";
compatible = "arm,cortex-a53";
device_type = "cpu";
};
};
tpu {
compatible = "cvitek,tpu";
reg-names = "tdma", "tiu";
reg = <0x0 0x0C100000 0x0 0x1000>,
<0x0 0x0C101000 0x0 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
};
mon {
compatible = "cvitek,mon";
reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
reg = <0x0 0x01040000 0x0 0x1000>,
<0x0 0x08004000 0x0 0x1000>,
<0x0 0x08006000 0x0 0x1000>,
<0x0 0x08008000 0x0 0x1000>,
<0x0 0x0800A000 0x0 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
};
cvitek-ion {
compatible = "cvitek,cvitek-ion";
heap_carveout@0 {
compatible = "cvitek,carveout";
memory-region = <&ion_reserved>;
};
};
reserved-memory {
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
cma_reserved: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x1000000>; // 16MB
alignment = <0x0 0x2000>; // 8KB
linux,cma-default;
};
ion_reserved: ion {
compatible = "ion-region";
size = <0x0 0x06000000>; // 96MB
};
vip_reserved: vip {
/* <start, length> pair
* and restrict to 4G address range
*/
size = <0x0 0x02000000>; // 32MB
no-map;
};
vcodec_reserved: vcodec {
/* <start, length> pair
* and restrict to 4G address range
*/
alloc-ranges = <0x0 0x80000000 0 0xC0000000>;
size = <0x0 0x06000000>; // 96MB
alignment = <0x0 0x1000>; // 4KB
no-map;
};
jpu_reserved: jpu {
/* <start, length> pair
* and restrict to 4G address range
*/
alloc-ranges = <0x0 0x80000000 0 0xC0000000>;
size = <0x0 0x01000000>; // 16MB
alignment = <0x0 0x1000>; // 4KB
no-map;
};
};
timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
always-on;
clock-frequency = <1000000000>;
compatible = "arm,armv8-timer";
};
watchdog0: cv-wd@0x3010000 {
compatible = "snps,dw-wdt";
reg = <0x0 0x03010000 0x0 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_WDT>;
clocks = <&pclk>;
};
pclk: pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
uart0: serial@04140000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x04140000 0x0 0x1000>;
clock-frequency = <307200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
memory {
reg = <0x0 0x80000000 0x0 0x80000000>;
device_type = "memory";
};
gpio0: gpio@03020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x03020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
bank-name = "porta";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
};
};
mipi_rx: cif {
compatible = "cvitek,cif";
reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
<0x0 0x0a0c4000 0x0 0x2000>;
reg-names = "csi_mac0", "csi_wrap0", "csi_mac1";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "csi0", "csi1";
snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>;
resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
};
mipi_tx {
compatible = "cvitek,mipi_tx";
};
base {
compatible = "cvitek,base";
};
vip {
compatible = "cvitek,vip";
memory-region = <&vip_reserved>;
reg = <0x0 0x0a080000 0x0 0x10000>,<0x0 0x0a0c0000 0x0 0x1000>,
<0x0 0x0a0c8000 0x0 0x20>,<0x0 0x0a000000 0x0 0x80000>,
<0x0 0x0a0d1000 0x0 0x100>;
reg-names = "sc","dwa","vip_sys","isp","dphy";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sc","dwa","isp";
cvitek,cif-modules = <&mipi_rx>;
snsr-num = <1>;
clock-freq-vip-sys1 = <300000000>;
};
vcodec {
compatible = "cvitek,cv1822-fpga-vcodec";
memory-region = <&vcodec_reserved>;
reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>;
reg-names = "h265", "h264","vc_ctrl";
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "h265","h264";
};
jpu {
compatible = "cvitek,cv1822-fpga-jpeg";
memory-region = <&jpu_reserved>;
reg = <0x0 0x0B000000 0x0 0x300>;
reg-names = "jpeg";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "jpeg";
reset = <&rst RST_JPEG>;
reset-names = "jpeg";
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0"; // "serial0:115200n8", no arguments means no re-initialization
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A53_0>;
};
rtos_cmdqu {
compatible = "cvitek,rtos_cmdqu";
reg = <0x0 0x01900000 0x0 0x1000>;
reg-names = "mailbox";
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mailbox";
};
};

108
build/boards/cv181x/cv181x_palladium/linux/cv181x_riscv64_fpga.dts
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@ -1,108 +0,0 @@
/dts-v1/;
/ {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "riscv-virtio";
model = "riscv-virtio,qemu";
reserved-memory {
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
mmode_resv0@80000000 {
reg = <0x00 0x80000000 0x00 0x20000>;
};
};
chosen {
bootargs = "console=ttyS0,115200n8 debug loglevel=8,initcall_debug=8 root=/dev/ init=/sbin/init earlycon=sbi";
stdout-path = "serial0";
};
uart0: serial@4140000 {
interrupts = <44>;
interrupt-parent = <0x03>;
clock-frequency = <25000000>;
reg = <0x00 0x4140000 0x00 0x100>;
compatible = "snps,dw-apb-uart";
reg-shift = <2>;
reg-io-width = <4>;
status = "okay";
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
timebase-frequency = <25000000>;
cpu-map {
cluster0 {
core0 {
cpu = <0x01>;
};
};
};
cpu@0 {
linux,phandle = <0x01>;
phandle = <0x01>;
device_type = "cpu";
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
mmu-type = "riscv,sv39";
clock-frequency = <25000000>;
interrupt-controller {
#interrupt-cells = <0x01>;
interrupt-controller;
compatible = "riscv,cpu-intc";
linux,phandle = <0x02>;
phandle = <0x02>;
};
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00 0x80000000 0x00 0x8000000>;
};
soc {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "simple-bus";
ranges;
interrupt-controller@70000000 {
linux,phandle = <0x03>;
phandle = <0x03>;
riscv,ndev = <0x50>;
riscv,max-priority = <0x07>;
reg-names = "control";
reg = <0x00 0x70000000 0x00 0x4000000>;
interrupts-extended = <0x02 11 0x02 0x09>;
//interrupts-extended = <0x02 0xffffffff 0x02 0x09>;
interrupt-controller;
compatible = "riscv,plic0";
#interrupt-cells = <0x01>;
#address-cells = <0x00>;
};
clint@74000000 {
interrupts-extended = <0x02 0x03 0x02 0x07>;
reg = <0x00 0x74000000 0x00 0x10000>;
compatible = "riscv,clint0";
clint,has-no-64bit-mmio;
};
};
aliases {
serial0 = &uart0;
};
};

270
build/boards/cv181x/cv181x_palladium/linux/cvitek_cv181x_palladium_defconfig
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@ -1,270 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_TASKSTATS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
CONFIG_PROFILING=y
CONFIG_ARM_LPAE=y
# CONFIG_VDSO is not set
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_OABI_COMPAT=y
CONFIG_FORCE_MAX_ZONEORDER=10
# CONFIG_ATAGS is not set
CONFIG_KEXEC=y
CONFIG_CRASH_DUMP=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_PM_TEST_SUSPEND=y
CONFIG_ARCH_CVITEK=y
CONFIG_ARCH_CV181X=y
CONFIG_ARCH_CVITEK_CHIP="cv181x"
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_NET_SCHED=y
CONFIG_CFG80211=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=2
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_CVSNFC=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
# CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_STMMAC_ETH=y
# CONFIG_DWMAC_GENERIC is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_CVITEK_PHY=y
CONFIG_CVITEK_PHY_UAPS=y
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
# CONFIG_WLAN_VENDOR_BROADCOM is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
# CONFIG_WLAN_VENDOR_MARVELL is not set
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
# CONFIG_WLAN_VENDOR_REALTEK is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_DW=y
CONFIG_HW_RANDOM=y
# CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_CVITEK_PINCTRL_CV1835=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
CONFIG_THERMAL=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
# CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_CONTROLLER=y
# CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_MEDIA_USB_SUPPORT=y
# CONFIG_USB_VIDEO_CLASS=y
# CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_SOC_CAMERA=y
# CONFIG_V4L_MEM2MEM_DRIVERS=y
# CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
# CONFIG_VIDEO_CVITEK=m
# CONFIG_VIDEO_CVITEK_CIF=m
# CONFIG_VIDEO_CVITEK_SNS_I2C=m
# CONFIG_VIDEO_CVITEK_MIPI_TX=m
# CONFIG_FB=y
# CONFIG_FB_CVITEK=m
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_CV182X_CV182XADC=y
CONFIG_SND_SOC_CV182X_CV182XDAC=y
CONFIG_SND_CV1835_I2S=y
CONFIG_SND_SOC_CV182XADC=y
CONFIG_SND_SOC_CV182XDAC=y
CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
CONFIG_CV1835_I2S_SUBSYS=y
CONFIG_USB=y
CONFIG_USB_OTG=y
CONFIG_USB_OTG_FSM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_REALTEK=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_ISD200=y
CONFIG_USB_STORAGE_USBAT=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_STORAGE_JUMPSHOT=y
CONFIG_USB_STORAGE_ALAUDA=y
CONFIG_USB_STORAGE_ONETOUCH=y
CONFIG_USB_STORAGE_KARMA=y
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
CONFIG_USB_STORAGE_ENE_UB6250=y
CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_U_AUDIO=y
CONFIG_USB_F_SERIAL=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_EEM=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_F_UAC1=y
CONFIG_USB_F_UVC=y
CONFIG_USB_UAS=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_GADGET=y
CONFIG_U_SERIAL_CONSOLE=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_INPUT_EVDEV=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_CVI=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC_CVITEK=y
CONFIG_STAGING=y
CONFIG_ION=y
CONFIG_ION_SYSTEM_HEAP=y
CONFIG_ION_CARVEOUT_HEAP=y
CONFIG_ION_CMA_HEAP=y
CONFIG_CV1835_SYSDMA_REMAP=y
CONFIG_CVI_WIFI_PIN=y
CONFIG_PWM=y
CONFIG_ANDROID=y
# CONFIG_GATOR is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_ENCRYPTION=y
CONFIG_OVERLAY_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_UBIFS_FS=y
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_ZLIB is not set
CONFIG_SQUASHFS_XZ=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_3=y
CONFIG_NLS_UTF8=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
# CONFIG_CRYPTO_ECHAINIV is not set
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_ARC4=y
# CONFIG_CRYPTO_HW is not set
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_SCHEDSTATS=y
CONFIG_SCHED_STACK_END_CHECK=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
CONFIG_DEBUG_LIST=y
CONFIG_IRQSOFF_TRACER=y
CONFIG_SCHED_TRACER=y
CONFIG_HWLAT_TRACER=y
CONFIG_FTRACE_SYSCALLS=y
CONFIG_STACK_TRACER=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_FUNCTION_PROFILER=y

2215
build/boards/cv181x/cv181x_palladium/linux/cvitek_cv181x_riscv64_fpga_defconfig
View File

File diff suppressed because it is too large Load Diff

1
build/boards/cv181x/cv181x_palladium/memmap.py
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@ -1 +0,0 @@
../../default/memmap/cv181x/memmap_ddr_4g.py

1
build/boards/cv181x/cv181x_palladium/partition/partition_none.xml
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@ -1 +0,0 @@
../../../default/partition/partition_none.xml

1
build/boards/cv181x/cv181x_palladium/partition/partition_spinor.xml
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@ -1 +0,0 @@
../../../default/partition/partition_spinor_16mb_cv181x.xml

4
build/boards/cv181x/cv181x_palladium/u-boot/cvi_board_init.c
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@ -1,4 +0,0 @@
int cvi_board_init(void)
{
return 0;
}

1
build/boards/cv181x/cv181x_palladium/u-boot/cvitek.h
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@ -1 +0,0 @@
../../../default/u-boot/cvitek_cv181x.h

47
build/boards/cv181x/cv181x_palladium/u-boot/cvitek_cv181x_palladium_defconfig
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@ -1,47 +0,0 @@
CONFIG_ARM=y
CONFIG_TARGET_CVITEK=y
CONFIG_TARGET_CVITEK_CV181X=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" cvitek_cv181x"
CONFIG_ARMV8_SET_SMPEN=y
CONFIG_TARGET_CVITEK_CV181X_PALLADIUM=y
CONFIG_DEFAULT_DEVICE_TREE="cv181x_palladium"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="cv181x# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
# CONFIG_CMD_CVI_UPDATE is not set
CONFIG_CMD_CVI_REBOOT=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_CMD_NFS=y
CONFIG_PHYLIB=y
# CONFIG_PHY_BROADCOM is not set
# CONFIG_PHY_SMSC is not set
# CONFIG_PHY_FIXED is not set
CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_BAUDRATE=19200
CONFIG_LZ4=y
CONFIG_LZMA=y

10
build/boards/cv181x/cv1820a_wevb_0006a_spinor/dts_arm/cv1820a_wevb_0006a_spinor.dts
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@ -1,10 +0,0 @@
/dts-v1/;
#include "cv181x_base_arm.dtsi"
#include "cv181x_asic_qfn.dtsi"
#include "cv181x_asic_spinor.dtsi"
#include "cv181x_default_memmap.dtsi"
/ {
};

1
build/boards/cv181x/cv1820a_wevb_0006a_spinor/linux/cvitek_cv1820a_wevb_0006a_spinor_defconfig
View File

@ -1 +0,0 @@
../../../default/linux/cv181x_wevb_spinor_spinand_arm_defconfig

1
build/boards/cv181x/cv1820a_wevb_0006a_spinor/memmap.py
View File

@ -1 +0,0 @@
../../default/memmap/cv181x/memmap_ddr_64mb.py

1
build/boards/cv181x/cv1820a_wevb_0006a_spinor/partition/partition_spinor.xml
View File

@ -1 +0,0 @@
../../../default/partition/partition_spinor_16mb_cv181x.xml

7
build/boards/cv181x/cv1820a_wevb_0006a_spinor/rootfs_script/clean_rootfs.sh
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@ -1,7 +0,0 @@
#!/bin/bash
SYSTEM_DIR=$1
rm -rf $SYSTEM_DIR/mnt/system/usr
rm -rf $SYSTEM_DIR/mnt/system/lib
du -sh $SYSTEM_DIR/* |sort -rh

1
build/boards/cv181x/cv1820a_wevb_0006a_spinor/u-boot/cvi_board_init.c
View File

@ -1 +0,0 @@
../../../default/u-boot/cv181x_qfn_cvi_board_init.c

1
build/boards/cv181x/cv1820a_wevb_0006a_spinor/u-boot/cvitek.h
View File

@ -1 +0,0 @@
../../../default/u-boot/cvitek_cv181x.h

1
build/boards/cv181x/cv1820a_wevb_0006a_spinor/u-boot/cvitek_cv1820a_wevb_0006a_spinor_defconfig
View File

@ -1 +0,0 @@
../../../default/u-boot/cv181x_wevb_arm_spinor_defconfig

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