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freertos: release the generic version source code

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freertos runs on the second core (small one) of the CPU
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carbon
2023-10-19 14:31:43 +08:00
parent e266c53351
commit ca03037500
2166 changed files with 694154 additions and 58149 deletions
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12
freertos/.gitignore vendored
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@ -1,11 +1,5 @@
build/
install/
*.bin
cvitek/task/isp/isp
cvitek/build/
cvitek/install/bin
cvitek/install/lib
cvitek/install/lib/libaudio.a
cvitek/install/lib/libcomm.a
cvitek/install/lib/librgn.a
.vscode/

192
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/FreeRTOSConfig.h Normal file
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/*
* FreeRTOS Kernel V10.3.0
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include "xparameters.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html
*----------------------------------------------------------*/
/*
* The FreeRTOS Cortex-A port implements a full interrupt nesting model.
*
* Interrupts that are assigned a priority at or below
* configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM
* generic interrupt controller [GIC] means a priority that has a numerical
* value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API
* functions and will nest.
*
* Interrupts that are assigned a priority above
* configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical
* value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS
* API functions, will nest, and will not be masked by FreeRTOS critical
* sections (although it is necessary for interrupts to be globally disabled
* extremely briefly as the interrupt mask is updated in the GIC).
*
* FreeRTOS functions that can be called from an interrupt are those that end in
* "FromISR". FreeRTOS maintains a separate interrupt safe API to enable
* interrupt entry to be shorter, faster, simpler and smaller.
*
* For the purpose of setting configMAX_API_CALL_INTERRUPT_PRIORITY 255
* represents the lowest priority.
*/
#define configMAX_API_CALL_INTERRUPT_PRIORITY 9
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configUSE_TICKLESS_IDLE 0
#define configTICK_RATE_HZ ( ( TickType_t ) 250 )
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configMAX_PRIORITIES ( 8 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 )
#define configTOTAL_HEAP_SIZE ( 256 * 1024 )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 14
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_QUEUE_SETS 1
/* This demo creates RTOS objects using both static and dynamic allocation. */
#define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 1 /* Defaults to 1 anyway. */
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTimerPendFunctionCall 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTaskAbortDelay 1
#define INCLUDE_xTaskGetHandle 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
/* This demo makes use of one or more example stats formatting functions. These
format the raw data provided by the uxTaskGetSystemState() function in to human
readable ASCII form. See the notes in the implementation of vTaskList() within
FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
/* Run time stats are not generated. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS and
portGET_RUN_TIME_COUNTER_VALUE must be defined if configGENERATE_RUN_TIME_STATS
is set to 1. */
#define configGENERATE_RUN_TIME_STATS 0
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
#define portGET_RUN_TIME_COUNTER_VALUE()
/* The size of the global output buffer that is available for use when there
are multiple command interpreters running at once (for example, one on a UART
and one on TCP/IP). This is done to prevent an output buffer being defined by
each implementation - which would waste RAM. In this case, there is only one
command interpreter running. */
#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber );
#define configASSERT( x ) if( ( x ) == 0 ) { vMainAssertCalled( __FILE__, __LINE__ ); }
/* If configTASK_RETURN_ADDRESS is not defined then a task that attempts to
return from its implementing function will end up in a "task exit error"
function - which contains a call to configASSERT(). However this can give GCC
some problems when it tries to unwind the stack, as the exit error function has
nothing to return to. To avoid this define configTASK_RETURN_ADDRESS to 0. */
#define configTASK_RETURN_ADDRESS NULL
/* Bump up the priority of recmuCONTROLLING_TASK_PRIORITY to prevent false
positive errors being reported considering the priority of other tasks in the
system. */
#define recmuCONTROLLING_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
/****** Hardware specific settings. *******************************************/
/*
* The application must provide a function that configures a peripheral to
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
* in FreeRTOSConfig.h to call the function. This file contains a function
* that is suitable for use on the Zynq MPU. FreeRTOS_Tick_Handler() must
* be installed as the peripheral's interrupt handler.
*/
void vConfigureTickInterrupt( void );
#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()
void vClearTickInterrupt( void );
#define configCLEAR_TICK_INTERRUPT() vClearTickInterrupt()
/* The following constant describe the hardware, and are correct for the
Zynq MPU. */
#define configINTERRUPT_CONTROLLER_BASE_ADDRESS ( XPAR_PSU_ACPU_GIC_DIST_BASEADDR )
#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ( XPAR_PSU_ACPU_GIC_BASEADDR - XPAR_PSU_ACPU_GIC_DIST_BASEADDR )
#define configUNIQUE_INTERRUPT_PRIORITIES 16
#define fabs( x ) __builtin_fabs( x )
#define configUSE_TRACE_FACILITY 1
/* FreeRTOS+POSIX
* Portable Operating System Interface (POSIX threading wrapper) for FreeRTOS
*
* Dependencies
* Both configUSE_POSIX_ERRNO and configUSE_APPLICATION_TASK_TAG must be set to 1 in FreeRTOSConfig.h.
*/
#define configUSE_POSIX_ERRNO 1
#define configUSE_APPLICATION_TASK_TAG 1
#endif /* FREERTOS_CONFIG_H */

0
freertos/cvitek/task/vi/include/vi_task_main.h → freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/Makefile
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110
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject Normal file
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freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.project Normal file
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<arguments>1.0-name-matches-false-false-GCC</arguments>
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320
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c Normal file
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/*
* FreeRTOS Kernel V10.3.0
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky
* style project, and a more comprehensive test and demo application. The
* mainSELECTED_APPLICATION setting in main.c is used to select between the
* two. See the notes on using mainSELECTED_APPLICATION in main.c. This file
* implements the simply blinky style version.
*
* NOTE 2: This file only contains the source code that is specific to the
* simple demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 200 milliseconds...and so on.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, outputs a message to the
* UART. The 'block time' parameter passed to the queue receive function
* specifies that the task should be held in the Blocked state indefinitely to
* wait for data to be available on the queue. The queue receive task will only
* leave the Blocked state when the queue send task writes to the queue. As the
* queue send task writes to the queue every 200 milliseconds, the queue receive
* task leaves the Blocked state every 200 milliseconds, and therefore outputs
* a message every 200 milliseconds.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Xilinx includes. */
#include "xil_printf.h"
#include "cmdqueue.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 200ms value is converted
to ticks using the portTICK_PERIOD_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 5000 )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/*-----------------------------------------------------------*/
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
static void prvISPRunTask( void *pvParameters );
static void prvVcodecRunTask( void *pvParameters );
static void prvVpssRunTask( void *pvParameters );
static void prvCmdQuRunTask( void *pvParameters );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static QueueHandle_t xQueue = NULL;
static QueueHandle_t xQueueIsp = NULL;
static QueueHandle_t xQueueVcodec = NULL;
static QueueHandle_t xQueueVpss = NULL;
static QueueHandle_t xQueueCmdqu = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
xQueueIsp = xQueueCreate( mainQUEUE_LENGTH, sizeof( cmdqu_t ) );
xQueueVcodec = xQueueCreate( mainQUEUE_LENGTH, sizeof( cmdqu_t ) );
xQueueVpss = xQueueCreate( mainQUEUE_LENGTH, sizeof( cmdqu_t ) );
xQueueCmdqu = xQueueCreate( mainQUEUE_LENGTH, sizeof( cmdqu_t ) );
if( xQueue != NULL && xQueueIsp != NULL && xQueueVcodec != NULL && xQueueVpss != NULL)
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
"Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
NULL, /* The parameter passed to the task - not used in this case. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
xTaskCreate( prvISPRunTask, "ISP", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
xTaskCreate( prvVcodecRunTask, "Vcodec", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
xTaskCreate( prvVpssRunTask, "Vpss", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
xTaskCreate( prvCmdQuRunTask, "Vpss", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was either insufficient FreeRTOS heap memory available for the idle
and/or timer tasks to be created, or vTaskStartScheduler() was called from
User mode. See the memory management section on the FreeRTOS web site for
more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The
mode from which main() is called is set in the C start up code and must be
a privileged mode (not user mode). */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCmdQuRunTask( void *pvParameters )
{
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
cmdqu_t rtos_cmdq;
struct shm_para_t *shm_para = 0x120000040;
xil_printf("prvCmdQuRunTask run\n");
for( ;; )
{
xQueueReceive( xQueueCmdqu, &rtos_cmdq, portMAX_DELAY );
/* send command to linux*/
queue_enqueue(&shm_para->rtos_cmd_queue, &rtos_cmdq);
volatile int * addr=0x1F01F00;
*addr=0x10008;
asm volatile("dsb sy;");
asm volatile("isb sy;");
}
}
static void prvISPRunTask( void *pvParameters )
{
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
cmdqu_t rtos_cmdq;
xil_printf("prvISPRunTask run\n");
for( ;; )
{
xQueueReceive( xQueueIsp, &rtos_cmdq, portMAX_DELAY );
xil_printf("prvISPRunTask id=%d cmd=%d para=%lx\n", rtos_cmdq.ip_id, rtos_cmdq.cmd_id, rtos_cmdq.param_ptr);
if(rtos_cmdq.ip_id ==0) {
xQueueSend( xQueueCmdqu, &rtos_cmdq, 0U );
}
rtos_cmdq.ip_id = -1;
}
}
static void prvVcodecRunTask( void *pvParameters )
{
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
xil_printf("prvVcodecRunTask run\n");
cmdqu_t rtos_cmdq;
for( ;; )
{
xQueueReceive( xQueueVcodec, &rtos_cmdq, portMAX_DELAY );
xil_printf("prvVcodecRunTask id=%d cmd=%d para=%lx\n", rtos_cmdq.ip_id, rtos_cmdq.cmd_id, rtos_cmdq.param_ptr);
if(rtos_cmdq.ip_id == 1) {
xQueueSend( xQueueCmdqu, &rtos_cmdq, 0U );
}
rtos_cmdq.ip_id = -1;
}
}
static void prvVpssRunTask( void *pvParameters )
{
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
xil_printf("prvVpssRunTask run\n");
cmdqu_t rtos_cmdq;
for( ;; )
{
xQueueReceive( xQueueVpss, &rtos_cmdq, portMAX_DELAY );
xil_printf("prvVpssRunTask id=%d cmd=%d para=%lx\n", rtos_cmdq.ip_id, rtos_cmdq.cmd_id, rtos_cmdq.param_ptr);
if(rtos_cmdq.ip_id == 2) {
xQueueSend( xQueueCmdqu, &rtos_cmdq, 0U );
}
rtos_cmdq.ip_id = -1;
}
}
static void prvQueueSendTask( void *pvParameters )
{
TickType_t xNextWakeTime;
const uint32_t ulValueToSend = 100UL;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0U );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
uint32_t ulReceivedValue;
const uint32_t ulExpectedValue = 100UL;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but is
it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == ulExpectedValue )
{
xil_printf( "100 received\r\n" );
ulReceivedValue = 0U;
}
}
}
enum IP_TYPE{
IP_ISP,
IP_VCODEC,
IP_VPSS,
};
/*-----------------------------------------------------------*/
void prvQueueISR(void)
{
xil_printf("prvQueueISR\n");
struct shm_para_t *shm_para = 0x120000040;
queue_t *linux_cmd_queue = &shm_para->linux_cmd_queue;
xil_printf("buffer =%lx\n",((unsigned long)shm_para->linux_cmd_queue.queue_buffer));
xil_printf("offset =%lx\n", shm_para->virt_phys_offset);
xil_printf("queue =%lx\n", linux_cmd_queue);
while(!queue_is_empty(linux_cmd_queue))
{
/* receive command from linux*/
cmdqu_t * cmdq;
cmdqu_t rtos_cmdq;
cmdq = queue_peek(linux_cmd_queue);
xil_printf("cmdq id = %lx\n", cmdq->ip_id);
xil_printf("cmdq cmd = %lx\n", cmdq->cmd_id);
xil_printf("cmdq param = %lx\n", cmdq->param_ptr);
rtos_cmdq.ip_id = cmdq->ip_id;
rtos_cmdq.cmd_id = cmdq->cmd_id;
rtos_cmdq.param_ptr = cmdq->param_ptr;
queue_dequeue(linux_cmd_queue);
switch (rtos_cmdq.ip_id) {
case IP_ISP:
// if(!xQueueIsQueueFullFromISR(xQueueIsp))
xQueueSendFromISR( xQueueIsp, &rtos_cmdq, 0U );
// else
// xil_printf("ISP Queue is full\n");
break;
case IP_VCODEC:
xQueueSendFromISR( xQueueVcodec, &rtos_cmdq, 0U );
break;
case IP_VPSS:
xQueueSendFromISR( xQueueVpss, &rtos_cmdq, 0U );
break;
default:
break;
}
}
}

308
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_asm_vectors.S Normal file
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@ -0,0 +1,308 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file asm_vectors.s
*
* This file contains the initial vector table for the Cortex A53 processor
* Currently NEON registers are not saved on stack if interrupt is taken.
* It will be implemented.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 5.00 pkp 5/21/14 Initial version
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
.org 0
.text
.globl _boot
.globl _vector_table
.globl _freertos_vector_table
.globl FIQInterrupt
.globl IRQInterrupt
.globl SErrorInterrupt
.globl SynchronousInterrupt
.org 0
.section .vectors, "a"
_vector_table:
.set VBAR, _vector_table
.org VBAR
b _boot
.org (VBAR + 0x80)
b .
.org (VBAR + 0x100)
b .
.org (VBAR + 0x180)
b .
.org (VBAR + 0x200)
b .
.org (VBAR + 0x280)
b .
.org (VBAR + 0x300)
b .
.org (VBAR + 0x380)
b .
.org (VBAR + 0x400)
b .
.org (VBAR + 0x480)
b .
.org (VBAR + 0x500)
b .
.org (VBAR + 0x580)
b .
.org (VBAR + 0x600)
b .
.org (VBAR + 0x680)
b .
.org (VBAR + 0x700)
b .
.org (VBAR + 0x780)
b .
/******************************************************************************
* Vector table to use when FreeRTOS is running.
*****************************************************************************/
.set FREERTOS_VBAR, (VBAR+0x1000)
.org(FREERTOS_VBAR)
_freertos_vector_table:
b FreeRTOS_SWI_Handler
.org (FREERTOS_VBAR + 0x80)
b FreeRTOS_IRQ_Handler
.org (FREERTOS_VBAR + 0x100)
b .
.org (FREERTOS_VBAR + 0x180)
b .
.org (FREERTOS_VBAR + 0x200)
b FreeRTOS_SWI_Handler
.org (FREERTOS_VBAR + 0x280)
b FreeRTOS_IRQ_Handler
.org (FREERTOS_VBAR + 0x300)
b .
.org (FREERTOS_VBAR + 0x380)
b .
.org (FREERTOS_VBAR + 0x400)
b .
.org (FREERTOS_VBAR + 0x480)
b .
.org (FREERTOS_VBAR + 0x500)
b .
.org (FREERTOS_VBAR + 0x580)
b .
.org (FREERTOS_VBAR + 0x600)
b .
.org (FREERTOS_VBAR + 0x680)
b .
.org (FREERTOS_VBAR + 0x700)
b .
.org (FREERTOS_VBAR + 0x780)
b .
.org (FREERTOS_VBAR + 0x800)
#if 0
SynchronousInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl SynchronousInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
IRQInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl IRQInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
FIQInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl FIQInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
SErrorInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl SErrorInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
#endif
.end

134
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_tick_config.c Executable file
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@ -0,0 +1,134 @@
/*
* FreeRTOS Kernel V10.3.0
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Xilinx includes. */
#include "platform.h"
#include "xttcps.h"
#include "xscugic.h"
/* Timer used to generate the tick interrupt. */
static XTtcPs xRTOSTickTimerInstance;
/*-----------------------------------------------------------*/
void vConfigureTickInterrupt( void )
{
BaseType_t xStatus;
XTtcPs_Config *pxTimerConfiguration;
XInterval usInterval;
uint8_t ucPrescale;
const uint8_t ucLevelSensitive = 1;
extern XScuGic xInterruptController;
pxTimerConfiguration = XTtcPs_LookupConfig( XPAR_XTTCPS_0_DEVICE_ID );
configASSERT( pxTimerConfiguration );
#if 0
/* Initialise the device. */
xStatus = XTtcPs_CfgInitialize( &xRTOSTickTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
if( xStatus != XST_SUCCESS )
{
/* Not sure how to do this before XTtcPs_CfgInitialize is called as
*xRTOSTickTimerInstance is set within XTtcPs_CfgInitialize(). */
XTtcPs_Stop( &xRTOSTickTimerInstance );
xStatus = XTtcPs_CfgInitialize( &xRTOSTickTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
configASSERT( xStatus == XST_SUCCESS );
}
/* Set the options. */
XTtcPs_SetOptions( &xRTOSTickTimerInstance, ( XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE ) );
/* Derive values from the tick rate. */
XTtcPs_CalcIntervalFromFreq( &xRTOSTickTimerInstance, configTICK_RATE_HZ, &( usInterval ), &( ucPrescale ) );
/* Set the interval and prescale. */
XTtcPs_SetInterval( &xRTOSTickTimerInstance, usInterval );
XTtcPs_SetPrescaler( &xRTOSTickTimerInstance, ucPrescale );
#endif
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, CNTP_TIMER_0_INT_ID, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive );
/* Connect to the interrupt controller. */
xStatus = XScuGic_Connect( &xInterruptController, CNTP_TIMER_0_INT_ID, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, ( void * ) &xRTOSTickTimerInstance );
configASSERT( xStatus == XST_SUCCESS);
/* Enable the interrupt in the GIC. */
XScuGic_Enable( &xInterruptController, CNTP_TIMER_0_INT_ID );
/* Enable the interrupts in the timer and sart the timer. */
XTime_StartTimer();
}
/*-----------------------------------------------------------*/
void vClearTickInterrupt( void )
{
volatile uint32_t ulInterruptStatus;
/* Read the interrupt status, then write it back to clear the interrupt. */
//ulInterruptStatus = XTtcPs_GetInterruptStatus( &xRTOSTickTimerInstance );
//XTtcPs_ClearInterruptStatus( &xRTOSTickTimerInstance, ulInterruptStatus );
/* hardcore now, need to implement later*/
int* gicd_icpend_addr = 0x1F01280;
int* gicc_eoir_addr = 0x1F02010;
*gicc_eoir_addr = 30;
*gicd_icpend_addr=0x40000000;
__asm volatile( "DSB SY" );
__asm volatile( "ISB SY" );
// reset tick
XTime_ResetTimer();
}
/*-----------------------------------------------------------*/
void vApplicationIRQHandler( uint32_t ulICCIAR )
{
extern const XScuGic_Config XScuGic_ConfigTable[];
static const XScuGic_VectorTableEntry *pxVectorTable = XScuGic_ConfigTable[ XPAR_SCUGIC_SINGLE_DEVICE_ID ].HandlerTable;
uint32_t ulInterruptID;
const XScuGic_VectorTableEntry *pxVectorEntry;
/* Interrupts cannot be re-enabled until the source of the interrupt is
cleared. The ID of the interrupt is obtained by bitwise ANDing the ICCIAR
value with 0x3FF. */
ulInterruptID = ulICCIAR & 0x3FFUL;
if( ulInterruptID < XSCUGIC_MAX_NUM_INTR_INPUTS )
{
/* Call the function installed in the array of installed handler
functions. */
pxVectorEntry = &( pxVectorTable[ ulInterruptID ] );
configASSERT( pxVectorEntry );
pxVectorEntry->Handler( pxVectorEntry->CallBackRef );
}
}

234
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.c Normal file
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@ -0,0 +1,234 @@
/*
* FreeRTOS Kernel V10.3.0
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
* NOTE: Currently only timer 1 and timer 2 are used -
*
* This file initialises two timers as follows:
*
* Timer 0 and Timer 1 provide the interrupts that are used with the IntQ
* standard demo tasks, which test interrupt nesting and using queues from
* interrupts. Both these interrupts operate below the maximum syscall
* interrupt priority.
*
* Timer 2 is a much higher frequency timer that tests the nesting of interrupts
* that execute above the maximum syscall interrupt priority.
*
* All the timers can nest with the tick interrupt - creating a maximum
* interrupt nesting depth of 4.
*
* For convenience, the high frequency timer is also used to provide the time
* base for the run time stats.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
/* Demo includes. */
#include "IntQueueTimer.h"
#include "IntQueue.h"
/* Xilinx includes. */
#include "xttcps.h"
#include "xscugic.h"
/* The frequencies at which the first two timers expire are slightly offset to
ensure they don't remain synchronised. The frequency of the interrupt that
operates above the max syscall interrupt priority is 10 times faster so really
hammers the interrupt entry and exit code. */
#define tmrTIMERS_USED 3
#define tmrTIMER_0_FREQUENCY ( 100UL )
#define tmrTIMER_1_FREQUENCY ( 111UL )
#define tmrTIMER_2_FREQUENCY ( 20000UL )
/*-----------------------------------------------------------*/
/*
* The single interrupt service routines that is used to service all three
* timers.
*/
static void prvTimerHandler( void *CallBackRef );
/*-----------------------------------------------------------*/
/* Hardware constants. */
static const BaseType_t xDeviceIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_DEVICE_ID, XPAR_XTTCPS_1_DEVICE_ID, XPAR_XTTCPS_2_DEVICE_ID };
static const BaseType_t xInterruptIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_INTR, XPAR_XTTCPS_1_INTR, XPAR_XTTCPS_2_INTR };
/* Timer configuration settings. */
typedef struct
{
uint32_t OutputHz; /* Output frequency. */
uint16_t Interval; /* Interval value. */
uint8_t Prescaler; /* Prescaler value. */
uint16_t Options; /* Option settings. */
} TmrCntrSetup;
static TmrCntrSetup xTimerSettings[ tmrTIMERS_USED ] =
{
{ tmrTIMER_0_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },
{ tmrTIMER_1_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },
{ tmrTIMER_2_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }
};
/* Lower priority number means higher logical priority, so
configMAX_API_CALL_INTERRUPT_PRIORITY - 1 is above the maximum system call
interrupt priority. */
static const UBaseType_t uxInterruptPriorities[ tmrTIMERS_USED ] =
{
configMAX_API_CALL_INTERRUPT_PRIORITY + 1,
configMAX_API_CALL_INTERRUPT_PRIORITY,
configMAX_API_CALL_INTERRUPT_PRIORITY - 1
};
static XTtcPs xTimerInstances[ tmrTIMERS_USED ];
/* Used to provide a means of ensuring the intended interrupt nesting depth is
actually being reached. */
extern uint64_t ullPortInterruptNesting;
static volatile uint32_t ulMaxRecordedNesting = 1;
/* Used to ensure the high frequency timer is running at the expected
frequency. */
static volatile uint32_t ulHighFrequencyTimerCounts = 0;
/*-----------------------------------------------------------*/
void vInitialiseTimerForIntQueueTest( void )
{
BaseType_t xStatus;
TmrCntrSetup *pxTimerSettings;
extern XScuGic xInterruptController;
BaseType_t xTimer;
XTtcPs *pxTimerInstance;
XTtcPs_Config *pxTimerConfiguration;
const uint8_t ucRisingEdge = 3;
/*_RB_ Currently only timer 1 and timer 2 are used. */
for( xTimer = 0; xTimer < ( tmrTIMERS_USED - 1 ); xTimer++ )
{
/* Look up the timer's configuration. */
pxTimerInstance = &( xTimerInstances[ xTimer ] );
pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] );
configASSERT( pxTimerConfiguration );
#if 0
pxTimerSettings = &( xTimerSettings[ xTimer ] );
/* Initialise the device. */
xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
if( xStatus != XST_SUCCESS )
{
/* Not sure how to do this before XTtcPs_CfgInitialize is called
as pxTimerInstance is set within XTtcPs_CfgInitialize(). */
XTtcPs_Stop( pxTimerInstance );
xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
configASSERT( xStatus == XST_SUCCESS );
}
/* Set the options. */
XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options );
/* The timer frequency is preset in the pxTimerSettings structure.
Derive the values for the other structure members. */
XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) );
/* Set the interval and prescale. */
XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval );
XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler );
#endif
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucRisingEdge );
/* Connect to the interrupt controller. */
xStatus = XScuGic_Connect( &xInterruptController, xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance );
configASSERT( xStatus == XST_SUCCESS);
/* Enable the interrupt in the GIC. */
XScuGic_Enable( &xInterruptController, xInterruptIDs[ xTimer ] );
/* Enable the interrupts in the timer. */
XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
/* Start the timer. */
XTtcPs_Start( pxTimerInstance );
}
}
/*-----------------------------------------------------------*/
static void prvTimerHandler( void *pvCallBackRef )
{
uint32_t ulInterruptStatus;
XTtcPs *pxTimer = ( XTtcPs * ) pvCallBackRef;
BaseType_t xYieldRequired;
/* Read the interrupt status, then write it back to clear the interrupt. */
ulInterruptStatus = XTtcPs_GetInterruptStatus( pxTimer );
XTtcPs_ClearInterruptStatus( pxTimer, ulInterruptStatus );
__asm volatile( "DSB SY" );
__asm volatile( "ISB SY" );
/* Now the interrupt has been cleared, interrupts can be re-enabled. */
portENABLE_INTERRUPTS();
/* Only one interrupt event type is expected. */
configASSERT( ( XTTCPS_IXR_INTERVAL_MASK & ulInterruptStatus ) != 0 );
/* Check the device ID to know which IntQueue demo to call. */
if( pxTimer->Config.DeviceId == xDeviceIDs[ 0 ] )
{
xYieldRequired = xFirstTimerHandler();
}
else if( pxTimer->Config.DeviceId == xDeviceIDs[ 1 ] )
{
xYieldRequired = xSecondTimerHandler();
}
else
{
/* Used to check the timer is running at the expected frequency. */
ulHighFrequencyTimerCounts++;
xYieldRequired = pdFALSE;
}
/* Latch the highest interrupt nesting count detected. */
if( ullPortInterruptNesting > ulMaxRecordedNesting )
{
ulMaxRecordedNesting = ullPortInterruptNesting;
}
/* If xYieldRequired is not pdFALSE then calling either xFirstTimerHandler()
or xSecondTimerHandler() resulted in a task leaving the blocked state and
the task that left the blocked state had a priority higher than the currently
running task (the task this interrupt interrupted) - so a context switch
should be performed so the interrupt returns directly to the higher priority
task. xYieldRequired is tested inside the following macro. */
portYIELD_FROM_ISR( xYieldRequired );
}

36
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.h Normal file
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@ -0,0 +1,36 @@
/*
* FreeRTOS Kernel V10.3.0
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef INT_QUEUE_TIMER_H
#define INT_QUEUE_TIMER_H
void vInitialiseTimerForIntQueueTest( void );
BaseType_t xTimer0Handler( void );
BaseType_t xTimer1Handler( void );
#endif

237
freertos/cvitek/task/demo/Full_Demo/main_full.c → freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c
View File

@ -28,18 +28,20 @@
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky
* style project, and a more comprehensive test and demo application. The
* RUN_TYPE in build.sh setting in main.c is used to select between the two.
* See the notes on using RUN_TYPE in build.sh where it is defined below.
* mainSELECTED_APPLICATION setting in main.c is used to select between the two.
* See the notes on using mainSELECTED_APPLICATION in main.c. This file
* implements the comprehensive version.
*
* NOTE 2: This file only contains the source code that is not specific to
* either the simply blinky or full demos - this includes initialisation code
* and callback functions.
* NOTE 2: This file only contains the source code that is specific to the
* full demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
*
* NOTE 3: The full demo includes a test that checks the floating point context
* is maintained correctly across task switches. The standard GCC libraries can
* use floating point registers and made this test fail (unless the tasks that
* use the library are given a floating point context as described on the
* documentation page for this demo).
*
* NOTE 3: This project builds the FreeRTOS source code, so is expecting the
* BSP project to be configured as a 'standalone' bsp project rather than a
* 'FreeRTOS' bsp project. However the BSP project MUST still be build with
* the FREERTOS_BSP symbol defined (-DFREERTOS_BSP must be added to the
* command line in the BSP configuration).
******************************************************************************
*
* main_full() creates all the demo application tasks and software timers, then
@ -80,6 +82,7 @@
#include "countsem.h"
#include "GenQTest.h"
#include "recmutex.h"
#include "IntQueue.h"
#include "EventGroupsDemo.h"
#include "TaskNotify.h"
#include "IntSemTest.h"
@ -89,39 +92,39 @@
#include "TimerDemo.h"
/* Xilinx includes. */
#include "printf.h"
#include "xil_printf.h"
/* Priorities for the demo application tasks. */
#define mainSEM_TEST_PRIORITY (tskIDLE_PRIORITY + (UBaseType_t)1)
#define mainBLOCK_Q_PRIORITY (tskIDLE_PRIORITY + (UBaseType_t)2)
#define mainCREATOR_TASK_PRIORITY (tskIDLE_PRIORITY + (UBaseType_t)3)
#define mainFLOP_TASK_PRIORITY (tskIDLE_PRIORITY)
#define mainUART_COMMAND_CONSOLE_STACK_SIZE \
(configMINIMAL_STACK_SIZE * (UBaseType_t)3)
#define mainCOM_TEST_TASK_PRIORITY (tskIDLE_PRIORITY + (UBaseType_t)2)
#define mainCHECK_TASK_PRIORITY (configMAX_PRIORITIES - (UBaseType_t)1)
#define mainQUEUE_OVERWRITE_PRIORITY (tskIDLE_PRIORITY)
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 2 )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 3 )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * ( UBaseType_t ) 3 )
#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 2 )
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - ( UBaseType_t ) 1 )
#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )
/* A block time of zero simply means "don't block". */
#define mainDONT_BLOCK ((TickType_t)0)
#define mainDONT_BLOCK ( ( TickType_t ) 0 )
/* The period of the check task, in ms. */
#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS((TickType_t)20000)
#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( ( TickType_t ) 20000 )
/* Parameters that are passed into the register check tasks solely for the
purpose of ensuring parameters are passed into tasks correctly. */
#define mainREG_TEST_TASK_1_PARAMETER ((void *)0x12345678)
#define mainREG_TEST_TASK_2_PARAMETER ((void *)0x87654321)
#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )
#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )
/* The base period used by the timer test tasks. */
#define mainTIMER_TEST_PERIOD (50)
#define mainTIMER_TEST_PERIOD ( 50 )
/*-----------------------------------------------------------*/
/*
* The check task, as described at the top of this file.
*/
static void prvCheckTask(void *pvParameters);
static void prvCheckTask( void *pvParameters );
/*
* Register check tasks, and the tasks used to write over and check the contents
@ -130,36 +133,35 @@ static void prvCheckTask(void *pvParameters);
* entry points are kept in the C file for the convenience of checking the task
* parameter.
*/
static void prvRegTestTaskEntry1(void *pvParameters);
extern void vRegTest1Implementation(void);
static void prvRegTestTaskEntry2(void *pvParameters);
extern void vRegTest2Implementation(void);
static void prvRegTestTaskEntry1( void *pvParameters );
extern void vRegTest1Implementation( void );
static void prvRegTestTaskEntry2( void *pvParameters );
extern void vRegTest2Implementation( void );
/*
* Register commands that can be used with FreeRTOS+CLI. The commands are
* defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.
*/
extern void vRegisterSampleCLICommands(void);
extern void vRegisterSampleCLICommands( void );
/*
* The task that manages the FreeRTOS+CLI input and output.
*/
extern void vUARTCommandConsoleStart(uint16_t usStackSize,
UBaseType_t uxPriority);
extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );
/*
* A high priority task that does nothing other than execute at a pseudo random
* time to ensure the other test tasks don't just execute in a repeating
* pattern.
*/
static void prvPseudoRandomiser(void *pvParameters);
static void prvPseudoRandomiser( void *pvParameters );
/*
* The full demo uses the tick hook function to include test code in the tick
* interrupt. vFullDemoTickHook() is called by vApplicationTickHook(), which
* is defined in main.c.
*/
void vFullDemoTickHook(void);
void vFullDemoTickHook( void );
/*-----------------------------------------------------------*/
@ -171,40 +173,39 @@ volatile uint64_t ullRegTest1LoopCounter = 0ULL, ullRegTest2LoopCounter = 0ULL;
/*-----------------------------------------------------------*/
void main_full(void)
void main_full( void )
{
/* Start all the other standard demo/test tasks. They have no particular
/* Start all the other standard demo/test tasks. They have no particular
functionality, but do demonstrate how to use the FreeRTOS API and test the
kernel port. */
#if 0 //There are not 3 timers to trigger interrupt
vStartInterruptQueueTasks();
#endif
vStartDynamicPriorityTasks();
vCreateBlockTimeTasks();
vStartCountingSemaphoreTasks();
vStartGenericQueueTasks(tskIDLE_PRIORITY);
vStartGenericQueueTasks( tskIDLE_PRIORITY );
vStartRecursiveMutexTasks();
vStartSemaphoreTasks(mainSEM_TEST_PRIORITY);
vStartMathTasks(mainFLOP_TASK_PRIORITY);
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartMathTasks( mainFLOP_TASK_PRIORITY );
vStartEventGroupTasks();
vStartTaskNotifyTask();
vStartInterruptSemaphoreTasks();
vStartStaticallyAllocatedTasks();
vCreateAbortDelayTasks();
vStartQueueOverwriteTask(mainQUEUE_OVERWRITE_PRIORITY);
vStartTimerDemoTask(mainTIMER_TEST_PERIOD);
vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );
vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
/* Create the register check tasks, as described at the top of this file */
xTaskCreate(prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE,
mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL);
xTaskCreate(prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE,
mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL);
xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );
xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
/* Create the task that just adds a little random behaviour. */
xTaskCreate(prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL,
configMAX_PRIORITIES - 1, NULL);
xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
/* Create the task that performs the 'check' functionality, as described at
the top of this file. */
xTaskCreate(prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL,
mainCHECK_TASK_PRIORITY, NULL);
xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Start the scheduler. */
vTaskStartScheduler();
@ -217,21 +218,20 @@ void main_full(void)
more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The
mode from which main() is called is set in the C start up code and must be
a privileged mode (not user mode). */
for (;;)
;
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTask(void *pvParameters)
static void prvCheckTask( void *pvParameters )
{
TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
TickType_t xLastExecutionTime;
static uint64_t ullLastRegTest1Value = 0, ullLastRegTest2Value = 0;
uint64_t ullErrorFound = pdFALSE;
const char *pcStatusString = "Pass";
TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
TickType_t xLastExecutionTime;
static uint64_t ullLastRegTest1Value = 0, ullLastRegTest2Value = 0;
uint64_t ullErrorFound = pdFALSE;
const char *pcStatusString = "Pass";
/* Just to stop compiler warnings. */
(void)pvParameters;
( void ) pvParameters;
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
@ -240,126 +240,140 @@ static void prvCheckTask(void *pvParameters)
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. The system status is written to the UART on each
iteration. */
for (;;) {
for( ;; )
{
/* Delay until it is time to execute again. */
vTaskDelayUntil(&xLastExecutionTime, xDelayPeriod);
vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
/* Check all the demo tasks (other than the flash tasks) to ensure
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none have detected an error. */
#if 0 //There are not 3 timers to trigger interrupt
#if 0 //There are not 3 timers to trigger interrupt
if( xAreIntQueueTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 0ULL;
pcStatusString = "Error: IntQ";
}
#endif
#endif
if (xAreMathsTaskStillRunning() != pdTRUE) {
if( xAreMathsTaskStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 1ULL;
pcStatusString = "Error: Math";
}
if (xAreDynamicPriorityTasksStillRunning() != pdTRUE) {
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 2ULL;
pcStatusString = "Error: Dynamic";
}
if (xAreBlockTimeTestTasksStillRunning() != pdTRUE) {
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 4ULL;
pcStatusString = "Error: Block Time";
}
if (xAreGenericQueueTasksStillRunning() != pdTRUE) {
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 5ULL;
pcStatusString = "Error: Generic Queue";
}
if (xAreRecursiveMutexTasksStillRunning() != pdTRUE) {
if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 6ULL;
pcStatusString = "Error: Recursive Mutex";
}
if (xAreSemaphoreTasksStillRunning() != pdTRUE) {
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 8ULL;
pcStatusString = "Error: Semaphore";
}
if (xAreCountingSemaphoreTasksStillRunning() != pdTRUE) {
if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 10ULL;
pcStatusString = "Error: Counting Semaphore";
}
if (xAreEventGroupTasksStillRunning() != pdPASS) {
if( xAreEventGroupTasksStillRunning() != pdPASS )
{
ullErrorFound |= 1ULL << 12ULL;
pcStatusString = "Error: Event Group";
}
if (xAreTaskNotificationTasksStillRunning() != pdTRUE) {
if( xAreTaskNotificationTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 13ULL;
pcStatusString = "Error: Task Notifications";
}
if (xAreInterruptSemaphoreTasksStillRunning() != pdTRUE) {
if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 14ULL;
pcStatusString = "Error: Interrupt Semaphore";
}
if (xAreStaticAllocationTasksStillRunning() != pdTRUE) {
if( xAreStaticAllocationTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 15ULL;
pcStatusString = "Error: Static Allocation";
}
if (xAreAbortDelayTestTasksStillRunning() != pdTRUE) {
if( xAreAbortDelayTestTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 16ULL;
pcStatusString = "Error: Abort Delay";
}
if (xIsQueueOverwriteTaskStillRunning() != pdTRUE) {
if( xIsQueueOverwriteTaskStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 17ULL;
pcStatusString = "Error: Queue Overwrite";
}
if (xAreTimerDemoTasksStillRunning(xDelayPeriod) != pdTRUE) {
if( xAreTimerDemoTasksStillRunning( xDelayPeriod ) != pdTRUE )
{
ullErrorFound |= 1ULL << 18ULL;
pcStatusString = "Error: Timer Demo";
}
/* Check that the register test 1 task is still running. */
if (ullLastRegTest1Value == ullRegTest1LoopCounter) {
if( ullLastRegTest1Value == ullRegTest1LoopCounter )
{
ullErrorFound |= 1ULL << 17ULL;
pcStatusString = "Error: Reg Test 1";
}
ullLastRegTest1Value = ullRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if (ullLastRegTest2Value == ullRegTest2LoopCounter) {
if( ullLastRegTest2Value == ullRegTest2LoopCounter )
{
ullErrorFound |= 1ULL << 18ULL;
pcStatusString = "Error: Reg Test 2";
}
ullLastRegTest2Value = ullRegTest2LoopCounter;
/* Output the system status string. */
printf("%s, status code = %lx, tick count = %ld\r\n",
pcStatusString, ullErrorFound, xTaskGetTickCount());
xil_printf( "%s, status code = %lu, tick count = %lu\r\n", pcStatusString, ullErrorFound, xTaskGetTickCount() );
configASSERT(ullErrorFound == pdFALSE);
configASSERT( ullErrorFound == pdFALSE );
}
}
/*-----------------------------------------------------------*/
static void prvRegTestTaskEntry1(void *pvParameters)
static void prvRegTestTaskEntry1( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
written in C for convenience of checking the task parameter is being passed
in correctly. */
if (pvParameters == mainREG_TEST_TASK_1_PARAMETER) {
if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
{
/* The reg test task also tests the floating point registers. Tasks
that use the floating point unit must call vPortTaskUsesFPU() before
any floating point instructions are executed. */
/* riscv64 enable fpu in start.S*/
#if defined(__aarch64__)
vPortTaskUsesFPU();
#endif
/* Start the part of the test that is written in assembler. */
vRegTest1Implementation();
@ -368,23 +382,21 @@ static void prvRegTestTaskEntry1(void *pvParameters)
/* The following line will only execute if the task parameter is found to
be incorrect. The check task will detect that the regtest loop counter is
not being incremented and flag an error. */
vTaskDelete(NULL);
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvRegTestTaskEntry2(void *pvParameters)
static void prvRegTestTaskEntry2( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
written in C for convenience of checking the task parameter is being passed
in correctly. */
if (pvParameters == mainREG_TEST_TASK_2_PARAMETER) {
if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
{
/* The reg test task also tests the floating point registers. Tasks
that use the floating point unit must call vPortTaskUsesFPU() before
any floating point instructions are executed. */
/* riscv64 enable fpu in start.S*/
#if defined(__aarch64__)
vPortTaskUsesFPU();
#endif
/* Start the part of the test that is written in assembler. */
vRegTest2Implementation();
@ -393,41 +405,43 @@ static void prvRegTestTaskEntry2(void *pvParameters)
/* The following line will only execute if the task parameter is found to
be incorrect. The check task will detect that the regtest loop counter is
not being incremented and flag an error. */
vTaskDelete(NULL);
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvPseudoRandomiser(void *pvParameters)
static void prvPseudoRandomiser( void *pvParameters )
{
const uint64_t ullMultiplier = 0x015a4e35ULL, ullIncrement = 1ULL,
ullMinDelay = pdMS_TO_TICKS(95);
volatile uint64_t ullNextRand = (uint64_t)&pvParameters, ullValue;
const uint64_t ullMultiplier = 0x015a4e35ULL, ullIncrement = 1ULL, ullMinDelay = pdMS_TO_TICKS( 95 );
volatile uint64_t ullNextRand = ( uint64_t ) &pvParameters, ullValue;
/* This task does nothing other than ensure there is a little bit of
disruption in the scheduling pattern of the other tasks. Normally this is
done by generating interrupts at pseudo random times. */
for (;;) {
ullNextRand = (ullMultiplier * ullNextRand) + ullIncrement;
ullValue = (ullNextRand >> 16ULL) & 0xffULL;
for( ;; )
{
ullNextRand = ( ullMultiplier * ullNextRand ) + ullIncrement;
ullValue = ( ullNextRand >> 16ULL ) & 0xffULL;
if (ullValue < ullMinDelay) {
if( ullValue < ullMinDelay )
{
ullValue = ullMinDelay;
}
vTaskDelay(ullValue);
vTaskDelay( ullValue );
while (ullValue > 0) {
__asm volatile("NOP");
__asm volatile("NOP");
__asm volatile("NOP");
__asm volatile("NOP");
while( ullValue > 0 )
{
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
ullValue--;
}
}
}
/*-----------------------------------------------------------*/
void vFullDemoTickHook(void)
void vFullDemoTickHook( void )
{
/* The full demo includes a software timer demo/test that requires
prodding periodically from the tick interrupt. */
@ -445,3 +459,6 @@ void vFullDemoTickHook(void)
/* Call the code that 'gives' a task notification from an ISR. */
xNotifyTaskFromISR();
}

0
freertos/cvitek/task/demo/Full_Demo/reg_test.S → freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/reg_test.S
View File

87
freertos/cvitek/task/demo/POSIX_Demo/main_posix.c → freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/POSIX_Demo/main_posix.c Normal file → Executable file
View File

@ -40,15 +40,13 @@
*
* Documentation for this demo can be found on:
* http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_POSIX/demo/posix_demo.html
*/
/* FreeRTOS includes. */
******************************************************************************
*
*
* /* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
/* FreeRTOS+POSIX. */
#include "FreeRTOS_POSIX/unistd.h"
/* System headers */
#include <stdio.h>
@ -56,66 +54,73 @@
#include "posix_demo.h"
/* Demo task priority */
#define mainPOSIX_DEMO_PRIORITY (tskIDLE_PRIORITY + 4)
#define mainPOSIX_DEMO_PRIORITY ( tskIDLE_PRIORITY + 4 )
/*-----------------------------------------------------------*/
int main_posix(void)
int main_posix( void )
{
TickType_t xLastExecutionTime;
TickType_t xLastExecutionTime;
configASSERT((mainPOSIX_DEMO_PRIORITY < configMAX_PRIORITIES));
configASSERT( ( mainPOSIX_DEMO_PRIORITY < configMAX_PRIORITIES ) );
const uint32_t ulLongTime_ms = pdMS_TO_TICKS(1000UL);
const uint32_t ulLongTime_ms = pdMS_TO_TICKS( 1000UL );
printf("FreeRTOS POSIX demo\n");
xil_printf( "FreeRTOS POSIX demo\n" );
/* Start the task to run POSIX demo */
xTaskCreate(vStartPOSIXDemo, "posix", configMINIMAL_STACK_SIZE, NULL,
mainPOSIX_DEMO_PRIORITY, NULL);
/* Start the task to run POSIX demo */
xTaskCreate( vStartPOSIXDemo,
"posix",
configMINIMAL_STACK_SIZE,
NULL,
mainPOSIX_DEMO_PRIORITY,
NULL );
vTaskStartScheduler();
vTaskStartScheduler();
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
xLastExecutionTime = xTaskGetTickCount();
xLastExecutionTime = xTaskGetTickCount();
/* If all is well, the scheduler will now be running, and the following
/* If all is well, the scheduler will now be running, and the following
* line will never be reached. If the following line does execute, then
* there was insufficient FreeRTOS heap memory available for the idle and/or
* timer tasks to be created. See the memory management section on the
* FreeRTOS web site for more details (this is standard text that is not
* really applicable to the Win32 simulator port). */
for (;;) {
/* Delay until it is time to execute again. */
vTaskDelayUntil(&xLastExecutionTime, ulLongTime_ms);
}
for( ; ; )
{
/* Delay until it is time to execute again. */
vTaskDelayUntil( &xLastExecutionTime, ulLongTime_ms );
}
return 0;
return 0;
}
/*-----------------------------------------------------------*/
void vAssertCalled(const char *pcFile, uint32_t ulLine)
void vAssertCalled( const char * pcFile,
uint32_t ulLine )
{
const uint32_t ulLongSleep = 1000UL;
volatile uint32_t ulBlockVariable = 0UL;
volatile char *pcFileName = (volatile char *)pcFile;
volatile uint32_t ulLineNumber = ulLine;
const uint32_t ulLongSleep = 1000UL;
volatile uint32_t ulBlockVariable = 0UL;
volatile char * pcFileName = ( volatile char * ) pcFile;
volatile uint32_t ulLineNumber = ulLine;
(void)pcFileName;
(void)ulLineNumber;
( void ) pcFileName;
( void ) ulLineNumber;
printf("vAssertCalled %s, %ld\n", pcFile, (long)ulLine);
fflush(stdout);
xil_printf( "vAssertCalled %s, %ld\n", pcFile, ( long ) ulLine );
fflush( stdout );
/* Setting ulBlockVariable to a non-zero value in the debugger will allow
/* Setting ulBlockVariable to a non-zero value in the debugger will allow
* this function to be exited. */
taskDISABLE_INTERRUPTS();
{
while (ulBlockVariable == 0UL) {
sleep(ulLongSleep);
}
}
taskENABLE_INTERRUPTS();
taskDISABLE_INTERRUPTS();
{
while( ulBlockVariable == 0UL )
{
sleep( ulLongSleep );
}
}
taskENABLE_INTERRUPTS();
}

375
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/POSIX_Demo/posix_demo.c Executable file
View File

@ -0,0 +1,375 @@
/*
* Amazon FreeRTOS POSIX Demo V1.4.2
* Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://aws.amazon.com/freertos
* http://www.FreeRTOS.org
*/
/**
* @brief Demo intro: job distribution with actor model.
*
* This demo simulates job distribution with actor model.
* https://en.wikipedia.org/wiki/Actor_model
*
* In this demo, vStartPOSIXDemo() first creates all mailboxes
* which will be used by actors to send and receive messages.
* Then it spins up two types of actors -- Dispatcher and Workers.
*
* Dispatcher -- Distributing sub-tasks to workers.
* Distribution is done by putting messages into each worker's inbox,
* which is essentially an mqueue. Dispatcher keeps distributing tasks
* until all intended tasks are distributed.
*
* Workers -- Take sub-tasks and perform predefined routine for each type of tasks.
*
* Upon finishing distributing all tasks, Dispatcher will send a "terminate" message to
* each worker. vStartPOSIXDemo() will then join all actor threads and clean up mailboxes.
*
* @note A few assumptions are made in this demo, which a user might have to alter
* if to adopt this model in a new application:
*
* - The upper limit for MQUEUE_NUMBER_OF_WORKERS is set to 10.
* This is not due to physical constraint (e.g. memory), rather to make queue
* names end with a single digit number.
*
* - Message enum is cast to char/uint8_t directly, with the assumption that
* the system is not going to have more than 254 messages, which is often true
* in practice. Could extend bits used in a message to either have more messages
* or include additional arguments for a message. Proper typecasting is needed
* in that case.
*
* - The philosophy is "failure is expected". It is shown in both the way dispatcher
* delivers messages (i.e. messages can be dropped by worker(s)), and also the
* way workers process messages (i.e. workers do not inform dispatcher success or
* failure).
*
* - Following the philosophy, dispatcher shall never use blocking calls to distribute
* tasks. The only exception made here is that dispatcher needs to make sure the
* successful delivery of "terminate" messages. So that, main thread could join
* all actor threads and finish the demo.
*/
/* FreeRTOS includes. */
#include "FreeRTOS.h"
/* System headers */
#include <stdbool.h>
#include <string.h>
#include <stdio.h>
/* Demo includes. */
#include "posix_demo.h"
/* FreeRTOS+POSIX. */
#include "FreeRTOS_POSIX/pthread.h"
#include "FreeRTOS_POSIX/mqueue.h"
#include "FreeRTOS_POSIX/time.h"
#include "FreeRTOS_POSIX/fcntl.h"
#include "FreeRTOS_POSIX/errno.h"
/* Constants */
#define LINE_BREAK "\r\n"
/**
* @brief Control messages.
*
* uint8_t is sufficient for this enum, that we are going to cast to char directly.
* If ever needed, implement a function to properly typecast.
*/
/**@{ */
typedef enum ControlMessage
{
eMSG_LOWER_INAVLID = 0x00, /**< Guard, let's not use 0x00 for messages. */
eWORKER_CTRL_MSG_CONTINUE = 0x01, /**< Dispatcher to worker, distributing another job. */
eWORKER_CTRL_MSG_EXIT = 0x02, /**< Dispatcher to worker, all jobs are finished and the worker receiving such can exit. */
/* define additional messages here */
eMSG_UPPER_INVALID = 0xFF /**< Guard, additional tasks shall be defined above. */
} eControlMessage;
/**@} */
/**
* @defgroup Configuration constants for the dispatcher-worker demo.
*/
/**@{ */
#define MQUEUE_NUMBER_OF_WORKERS ( 4 ) /**< The number of worker threads, each thread has one queue which is used as income box. */
#if ( MQUEUE_NUMBER_OF_WORKERS > 10 )
#error "Please keep MQUEUE_NUMBER_OF_WORKERS < 10."
#endif
#define MQUEUE_WORKER_QNAME_BASE "/qNode0" /**< Queue name base. */
#define MQUEUE_WORKER_QNAME_BASE_LEN ( 6 ) /** Queue name base length. */
#define MQUEUE_TIMEOUT_SECONDS ( 1 ) /**< Relative timeout for mqueue functions. */
#define MQUEUE_MAX_NUMBER_OF_MESSAGES_WORKER ( 1 ) /**< Maximum number of messages in a queue. */
#define MQUEUE_MSG_WORKER_CTRL_MSG_SIZE sizeof( uint8_t ) /**< Control message size. */
#define DEMO_ERROR ( -1 ) /**< Any non-zero value would work. */
/**@} */
/**
* @brief Structure used by Worker thread.
*/
/**@{ */
typedef struct WorkerThreadResources
{
pthread_t pxID; /**< thread ID. */
mqd_t xInboxID; /**< mqueue inbox ID. */
} WorkerThreadResources_t;
/**@} */
/**
* @brief Structure used by Dispatcher thread.
*/
/**@{ */
typedef struct DispatcherThreadResources
{
pthread_t pxID; /**< thread ID. */
mqd_t * pOutboxID; /**< a list of mqueue outbox ID. */
} DispatcherThreadResources_t;
/**@} */
/*-----------------------------------------------------------*/
static void * prvWorkerThread( void * pvArgs )
{
WorkerThreadResources_t pArgList = *( WorkerThreadResources_t * ) pvArgs;
xil_printf( "Worker thread #[%d] - start %s", ( int ) pArgList.pxID, LINE_BREAK );
struct timespec xReceiveTimeout = { 0 };
ssize_t xMessageSize = 0;
char pcReceiveBuffer[ MQUEUE_MSG_WORKER_CTRL_MSG_SIZE ] = { 0 };
/* This is a worker thread that reacts based on what is sent to its inbox (mqueue). */
while( true )
{
clock_gettime( CLOCK_REALTIME, &xReceiveTimeout );
xReceiveTimeout.tv_sec += MQUEUE_TIMEOUT_SECONDS;
xMessageSize = mq_receive( pArgList.xInboxID,
pcReceiveBuffer,
MQUEUE_MSG_WORKER_CTRL_MSG_SIZE,
0 );
/* Parse messages */
if( xMessageSize == MQUEUE_MSG_WORKER_CTRL_MSG_SIZE )
{
switch( ( int ) pcReceiveBuffer[ 0 ] )
{
case eWORKER_CTRL_MSG_CONTINUE:
/* Task branch, currently only prints message to screen. */
/* Could perform tasks here. Could also notify dispatcher upon completion, if desired. */
xil_printf( "Worker thread #[%d] -- Received eWORKER_CTRL_MSG_CONTINUE %s", ( int ) pArgList.pxID, LINE_BREAK );
break;
case eWORKER_CTRL_MSG_EXIT:
xil_printf( "Worker thread #[%d] -- Finished. Exit now. %s", ( int ) pArgList.pxID, LINE_BREAK );
return NULL;
default:
/* Received a message that we don't care or not defined. */
break;
}
}
else
{
/* Invalid message. Error handling can be done here, if desired. */
}
}
/* You should never hit here. */
/* return NULL; */
}
/*-----------------------------------------------------------*/
static void * prvDispatcherThread( void * pvArgs )
{
DispatcherThreadResources_t pArgList = *( DispatcherThreadResources_t * ) pvArgs;
xil_printf( "Dispatcher thread - start %s", LINE_BREAK );
struct timespec xSendTimeout = { 0 };
ssize_t xMessageSize = 0;
char pcSendBuffer[ MQUEUE_MSG_WORKER_CTRL_MSG_SIZE ] = { 0 };
/* Just for fun, let threads do a total of 100 independent tasks. */
int i = 0;
const int totalNumOfJobsPerThread = 100;
/* Distribute 1000 independent tasks to workers, in round-robin fashion. */
pcSendBuffer[ 0 ] = ( char ) eWORKER_CTRL_MSG_CONTINUE;
for( i = 0; i < totalNumOfJobsPerThread; i++ )
{
clock_gettime( CLOCK_REALTIME, &xSendTimeout );
xSendTimeout.tv_sec += MQUEUE_TIMEOUT_SECONDS;
xil_printf( "Dispatcher iteration #[%d] -- Sending msg to worker thread #[%d]. %s", i, ( int ) pArgList.pOutboxID[ i % MQUEUE_NUMBER_OF_WORKERS ], LINE_BREAK );
xMessageSize = mq_timedsend( pArgList.pOutboxID[ i % MQUEUE_NUMBER_OF_WORKERS ],
pcSendBuffer,
MQUEUE_MSG_WORKER_CTRL_MSG_SIZE,
0,
&xSendTimeout );
if( xMessageSize != 0 )
{
/* This error is acceptable in our setup.
* Since inbox for each thread fits only one message.
* In reality, balance inbox size, message arrival rate, and message drop rate. */
xil_printf( "An acceptable failure -- dispatcher failed to send eWORKER_CTRL_MSG_CONTINUE to outbox ID: %x. errno %d %s",
( int ) pArgList.pOutboxID[ i % MQUEUE_NUMBER_OF_WORKERS ], errno, LINE_BREAK );
}
}
/* Control thread is now done with distributing jobs. Tell workers they are done. */
pcSendBuffer[ 0 ] = ( char ) eWORKER_CTRL_MSG_EXIT;
for( i = 0; i < MQUEUE_NUMBER_OF_WORKERS; i++ )
{
xil_printf( "Dispatcher [%d] -- Sending eWORKER_CTRL_MSG_EXIT to worker thread #[%d]. %s", i, ( int ) pArgList.pOutboxID[ i % MQUEUE_NUMBER_OF_WORKERS ], LINE_BREAK );
/* This is a blocking call, to guarantee worker thread exits. */
xMessageSize = mq_send( pArgList.pOutboxID[ i % MQUEUE_NUMBER_OF_WORKERS ],
pcSendBuffer,
MQUEUE_MSG_WORKER_CTRL_MSG_SIZE,
0 );
}
return NULL;
}
/*-----------------------------------------------------------*/
/**
* @brief Job distribution with actor model.
*
* See the top of this file for detailed description.
*/
void vStartPOSIXDemo( void *pvParameters )
{
int i = 0;
int iStatus = 0;
xil_printf( "Run Task:vStartPOSIXDemo\n" );
/* Remove warnings about unused parameters. */
( void ) pvParameters;
/* Handles of the threads and related resources. */
DispatcherThreadResources_t pxDispatcher = { 0 };
WorkerThreadResources_t pxWorkers[ MQUEUE_NUMBER_OF_WORKERS ] = { { 0 } };
mqd_t workerMqueues[ MQUEUE_NUMBER_OF_WORKERS ] = { 0 };
struct mq_attr xQueueAttributesWorker =
{
.mq_flags = 0,
.mq_maxmsg = MQUEUE_MAX_NUMBER_OF_MESSAGES_WORKER,
.mq_msgsize = MQUEUE_MSG_WORKER_CTRL_MSG_SIZE,
.mq_curmsgs = 0
};
pxDispatcher.pOutboxID = workerMqueues;
/* Create message queues for each worker thread. */
for( i = 0; i < MQUEUE_NUMBER_OF_WORKERS; i++ )
{
/* Prepare a unique queue name for each worker. */
char qName[] = MQUEUE_WORKER_QNAME_BASE;
qName[ MQUEUE_WORKER_QNAME_BASE_LEN - 1 ] = qName[ MQUEUE_WORKER_QNAME_BASE_LEN - 1 ] + i;
/* Open a queue with --
* O_CREAT -- create a message queue.
* O_RDWR -- both receiving and sending messages.
*/
pxWorkers[ i ].xInboxID = mq_open( qName,
O_CREAT | O_RDWR,
( mode_t ) 0,
&xQueueAttributesWorker );
if( pxWorkers[ i ].xInboxID == ( mqd_t ) -1 )
{
xil_printf( "Invalid inbox (mqueue) for worker. %s", LINE_BREAK );
iStatus = DEMO_ERROR;
break;
}
/* Outboxes of dispatcher thread is the inboxes of all worker threads. */
pxDispatcher.pOutboxID[ i ] = pxWorkers[ i ].xInboxID;
}
/* Create and start Worker threads. */
if( iStatus == 0 )
{
for( i = 0; i < MQUEUE_NUMBER_OF_WORKERS; i++ )
{
( void ) pthread_create( &( pxWorkers[ i ].pxID ), NULL, prvWorkerThread, &pxWorkers[ i ] );
}
/* Create and start dispatcher thread. */
( void ) pthread_create( &( pxDispatcher.pxID ), NULL, prvDispatcherThread, &pxDispatcher );
/* Actors will do predefined tasks in threads. Current implementation is that
* dispatcher actor notifies worker actors to terminate upon finishing distributing tasks. */
/* Wait for worker threads to join. */
for( i = 0; i < MQUEUE_NUMBER_OF_WORKERS; i++ )
{
( void ) pthread_join( pxWorkers[ i ].pxID, NULL );
}
/* Wait for dispatcher thread to join. */
( void ) pthread_join( pxDispatcher.pxID, NULL );
}
/* Close and unlink worker message queues. */
for( i = 0; i < MQUEUE_NUMBER_OF_WORKERS; i++ )
{
char qName[] = MQUEUE_WORKER_QNAME_BASE;
qName[ MQUEUE_WORKER_QNAME_BASE_LEN - 1 ] = qName[ MQUEUE_WORKER_QNAME_BASE_LEN - 1 ] + i;
if( pxWorkers[ i ].xInboxID != 0 )
{
( void ) mq_close( pxWorkers[ i ].xInboxID );
( void ) mq_unlink( qName );
}
}
/* Have something on console. */
if( iStatus == 0 )
{
xil_printf( "All threads finished. %s", LINE_BREAK );
}
else
{
xil_printf( "Queues did not get initialized properly. Did not run demo. %s", LINE_BREAK );
}
/* This task was created with the native xTaskCreate() API function, so
must not run off the end of its implementing thread. */
vTaskDelete( NULL );
}

2
freertos/cvitek/task/demo/POSIX_Demo/posix_demo.h → freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/POSIX_Demo/posix_demo.h Normal file → Executable file
View File

@ -27,6 +27,6 @@
#ifndef _POSIX_DEMO_H_
#define _POSIX_DEMO_H_
void vStartPOSIXDemo(void *pvParameters);
void vStartPOSIXDemo( void * pvParameters );
#endif /* _POSIX_DEMO_H_ */

27
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/bm1882_common.h Executable file
View File

@ -0,0 +1,27 @@
#ifndef _BM1882_COMMON_H_
#define _BM1882_COMMON_H_
#define SEC_BASE 0x02000000
#define TOP_BASE 0x03000000
#define SPACC_BASE (SEC_BASE + 0x00060000)
#define TRNG_BASE (SEC_BASE + 0x00070000)
#define SEC_DBG_I2C_BASE (SEC_BASE + 0x00080000)
#define FAB_FIREWALL_BASE (SEC_BASE + 0x00090000)
#define DDR_FIREWALL_BASE (SEC_BASE + 0x000A0000)
#define PINMUX_BASE (TOP_BASE + 0x1000)
#define TEMPSEN_BASE (TOP_BASE + 0xE0000)
#define CLKGEN_BASE (TOP_BASE + 0x00002000)
#define UART0_BASE 0x04140000
#define SRAM_BASE 0x0E000000
#define REG_CLK_ENABLE_REG0 (CLKGEN_BASE)
#define REG_CLK_ENABLE_REG1 (CLKGEN_BASE + 0x4)
#define REG_CLK_BYPASS_SEL_REG (CLKGEN_BASE + 0x30)
#define REG_CLK_BYPASS_SEL_REG2 (CLKGEN_BASE + 0x34)
#define REG_CLK_DIV0_CTL_CA53_REG (CLKGEN_BASE + 0x40)
#define REG_CLK_DIV0_CTL_CPU_AXI0_REG (CLKGEN_BASE + 0x48)
#define REG_CLK_DIV0_CTL_TPU_AXI_REG (CLKGEN_BASE + 0x54)
#define REG_CLK_DIV0_CTL_TPU_FAB_REG (CLKGEN_BASE + 0x5C)
#endif

320
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld Normal file
View File

@ -0,0 +1,320 @@
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: */
/* */
/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A53 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000;
_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
psu_ddr_0_MEM_0 : ORIGIN = 0x110000000, LENGTH = 0x2000000
psu_ddr_1_MEM_0 : ORIGIN = 0x800000000, LENGTH = 0x80000000
psu_ocm_ram_0_MEM_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000
psu_qspi_linear_0_MEM_0 : ORIGIN = 0xC0000000, LENGTH = 0x20000000
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > psu_ddr_0_MEM_0
.init (ALIGN(64)) : {
KEEP (*(.init))
} > psu_ddr_0_MEM_0
.fini (ALIGN(64)) : {
KEEP (*(.fini))
} > psu_ddr_0_MEM_0
.interp : {
KEEP (*(.interp))
} > psu_ddr_0_MEM_0
.note-ABI-tag : {
KEEP (*(.note-ABI-tag))
} > psu_ddr_0_MEM_0
.rodata : {
. = ALIGN(64);
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > psu_ddr_0_MEM_0
.rodata1 : {
. = ALIGN(64);
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > psu_ddr_0_MEM_0
.sdata2 : {
. = ALIGN(64);
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > psu_ddr_0_MEM_0
.sbss2 : {
. = ALIGN(64);
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > psu_ddr_0_MEM_0
.data : {
. = ALIGN(64);
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > psu_ddr_0_MEM_0
.data1 : {
. = ALIGN(64);
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > psu_ddr_0_MEM_0
.got : {
*(.got)
} > psu_ddr_0_MEM_0
.got1 : {
*(.got1)
} > psu_ddr_0_MEM_0
.got2 : {
*(.got2)
} > psu_ddr_0_MEM_0
.ctors : {
. = ALIGN(64);
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > psu_ddr_0_MEM_0
.dtors : {
. = ALIGN(64);
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > psu_ddr_0_MEM_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > psu_ddr_0_MEM_0
.eh_frame : {
*(.eh_frame)
} > psu_ddr_0_MEM_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > psu_ddr_0_MEM_0
.gcc_except_table : {
*(.gcc_except_table)
} > psu_ddr_0_MEM_0
.mmu_tbl0 (ALIGN(4096)) : {
__mmu_tbl0_start = .;
*(.mmu_tbl0)
__mmu_tbl0_end = .;
} > psu_ddr_0_MEM_0
.mmu_tbl1 (ALIGN(4096)) : {
__mmu_tbl1_start = .;
*(.mmu_tbl1)
__mmu_tbl1_end = .;
} > psu_ddr_0_MEM_0
.mmu_tbl2 (ALIGN(4096)) : {
__mmu_tbl2_start = .;
*(.mmu_tbl2)
__mmu_tbl2_end = .;
} > psu_ddr_0_MEM_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > psu_ddr_0_MEM_0
.preinit_array : {
. = ALIGN(64);
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > psu_ddr_0_MEM_0
.init_array : {
. = ALIGN(64);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > psu_ddr_0_MEM_0
.fini_array : {
. = ALIGN(64);
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > psu_ddr_0_MEM_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > psu_ddr_0_MEM_0
.sdata : {
. = ALIGN(64);
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > psu_ddr_0_MEM_0
.sbss (NOLOAD) : {
. = ALIGN(64);
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
. = ALIGN(64);
__sbss_end = .;
} > psu_ddr_0_MEM_0
.tdata : {
. = ALIGN(64);
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > psu_ddr_0_MEM_0
.tbss : {
. = ALIGN(64);
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > psu_ddr_0_MEM_0
.bss (NOLOAD) : {
. = ALIGN(64);
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(64);
__bss_end__ = .;
} > psu_ddr_0_MEM_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(64);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > psu_ddr_0_MEM_0
.stack (NOLOAD) : {
. = ALIGN(64);
_el3_stack_end = .;
. += _STACK_SIZE;
__el3_stack = .;
_el2_stack_end = .;
. += _EL2_STACK_SIZE;
. = ALIGN(64);
__el2_stack = .;
_el1_stack_end = .;
. += _EL1_STACK_SIZE;
. = ALIGN(64);
__el1_stack = .;
_el0_stack_end = .;
. += _EL0_STACK_SIZE;
. = ALIGN(64);
__el0_stack = .;
} > psu_ddr_0_MEM_0
_end = .;
}

293
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c Executable file
View File

@ -0,0 +1,293 @@
/*
* FreeRTOS Kernel V10.3.0
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/******************************************************************************
*
* See http://www.FreeRTOS.org/RTOS-Xilinx-UltraScale_MPSoC_64-bit.html for
* additional information on this demo.
*
* NOTE 1: This project provides two demo applications. A simple blinky
* style project, and a more comprehensive test and demo application. The
* mainSELECTED_APPLICATION setting in main.c is used to select between the two.
* See the notes on using mainSELECTED_APPLICATION where it is defined below.
*
* NOTE 2: This file only contains the source code that is not specific to
* either the simply blinky or full demos - this includes initialisation code
* and callback functions.
*
* NOTE 3: This project builds the FreeRTOS source code, so is expecting the
* BSP project to be configured as a 'standalone' bsp project rather than a
* 'FreeRTOS' bsp project. However the BSP project MUST still be build with
* the FREERTOS_BSP symbol defined (-DFREERTOS_BSP must be added to the
* command line in the BSP configuration).
*/
/* Standard includes. */
#include <stdio.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Xilinx includes. */
#include "platform.h"
#include "xttcps.h"
#include "xscugic.h"
/* mainSELECTED_APPLICATION is used to select between two demo applications,
* as described at the top of this file.
*
* When mainSELECTED_APPLICATION is set to 0 the simple blinky example will
* be run.
*
* When mainSELECTED_APPLICATION is set to 1 the comprehensive test and demo
* application will be run.
*
* When mainSELECTED_APPLICATION is set to 2 the posix application will be run.
*/
#define mainSELECTED_APPLICATION 1
/*-----------------------------------------------------------*/
/*
* Configure the hardware as necessary to run this demo.
*/
static void prvSetupHardware( void );
/*
* See the comments at the top of this file and above the
* mainSELECTED_APPLICATION definition.
*/
#if ( mainSELECTED_APPLICATION == 0 )
extern void main_blinky( void );
#elif ( mainSELECTED_APPLICATION == 1 )
extern void main_full( void );
#elif ( mainSELECTED_APPLICATION == 2 )
extern void main_posix( void );
#else
#error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition.
#endif
/* Prototypes for the standard FreeRTOS callback/hook functions implemented
within this file. */
void vApplicationMallocFailedHook( void );
void vApplicationIdleHook( void );
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
void vApplicationTickHook( void );
/*-----------------------------------------------------------*/
/* The interrupt controller is initialised in this file, and made available to
other modules. */
XScuGic xInterruptController;
/*-----------------------------------------------------------*/
int main( void )
{
/* See http://www.FreeRTOS.org/RTOS-Xilinx-UltraScale_MPSoC_64-bit.html for
additional information on this demo. */
system_init();
xil_printf("Build Date:%s (Time :%s) \n", __DATE__ , __TIME__);
xil_printf("enable I/D cache & MMU\n");
enable_caches();
xil_printf("enable I/D cache & MMU done\n");
/* Configure the hardware ready to run the demo. */
prvSetupHardware();
/* The mainSELECTED_APPLICATION setting is described at the top
of this file. */
#if( mainSELECTED_APPLICATION == 0 )
{
main_blinky();
}
#elif( mainSELECTED_APPLICATION == 1 )
{
main_full();
}
#elif ( mainSELECTED_APPLICATION == 2 )
{
main_posix();
}
#endif
/* Don't expect to reach here. */
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
BaseType_t xStatus;
XScuGic_Config *pxGICConfig;
/* Ensure no interrupts execute while the scheduler is in an inconsistent
state. Interrupts are automatically enabled when the scheduler is
started. */
portDISABLE_INTERRUPTS();
/* Obtain the configuration of the GIC. */
pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID );
/* Sanity check the FreeRTOSConfig.h settings are correct for the
hardware. */
configASSERT( pxGICConfig );
configASSERT( pxGICConfig->CpuBaseAddress == ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) );
configASSERT( pxGICConfig->DistBaseAddress == configINTERRUPT_CONTROLLER_BASE_ADDRESS );
/* Install a default handler for each GIC interrupt. */
xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* Called if a call to pvPortMalloc() fails because there is insufficient
free memory available in the FreeRTOS heap. pvPortMalloc() is called
internally by FreeRTOS API functions that create tasks, queues, software
timers, and semaphores. The size of the FreeRTOS heap is set by the
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
volatile size_t xFreeHeapSpace;
/* This is just a trivial example of an idle hook. It is called on each
cycle of the idle task. It must *NOT* attempt to block. In this case the
idle task just queries the amount of FreeRTOS heap that remains. See the
memory management section on the http://www.FreeRTOS.org web site for memory
management options. If there is a lot of heap memory free then the
configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up
RAM. */
xFreeHeapSpace = xPortGetFreeHeapSize();
/* Remove compiler warning about xFreeHeapSpace being set but never used. */
( void ) xFreeHeapSpace;
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
#if( mainSELECTED_APPLICATION == 1 )
{
/* Only the comprehensive demo actually uses the tick hook. */
extern void vFullDemoTickHook( void );
vFullDemoTickHook();
}
#endif
}
/*-----------------------------------------------------------*/
/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an
implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
used by the Idle task. */
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
{
/* If the buffers to be provided to the Idle task are declared inside this
function then they must be declared static - otherwise they will be allocated on
the stack and so not exists after this function exits. */
static StaticTask_t xIdleTaskTCB;
static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
/* Pass out a pointer to the StaticTask_t structure in which the Idle task's
state will be stored. */
*ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
/* Pass out the array that will be used as the Idle task's stack. */
*ppxIdleTaskStackBuffer = uxIdleTaskStack;
/* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
Note that, as the array is necessarily of type StackType_t,
configMINIMAL_STACK_SIZE is specified in words, not bytes. */
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
}
/*-----------------------------------------------------------*/
/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
application must provide an implementation of vApplicationGetTimerTaskMemory()
to provide the memory that is used by the Timer service task. */
void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
{
/* If the buffers to be provided to the Timer task are declared inside this
function then they must be declared static - otherwise they will be allocated on
the stack and so not exists after this function exits. */
static StaticTask_t xTimerTaskTCB;
static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
/* Pass out a pointer to the StaticTask_t structure in which the Timer
task's state will be stored. */
*ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
/* Pass out the array that will be used as the Timer task's stack. */
*ppxTimerTaskStackBuffer = uxTimerTaskStack;
/* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
Note that, as the array is necessarily of type StackType_t,
configMINIMAL_STACK_SIZE is specified in words, not bytes. */
*pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
}
/*-----------------------------------------------------------*/
void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber )
{
xil_printf( "ASSERT! Line %lu of file %s\r\n", ulLineNumber, pcFileName );
taskENTER_CRITICAL();
for( ;; );
}
void *____memset(void *str, int c, size_t n)
{
size_t x;
uint8_t *puc = ( uint8_t * ) str;
for( x = 0; x < c; x++ )
{
puc[ x ] = ( uint8_t ) c;
}
return str;
}

72
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/mmio.h Executable file
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@ -0,0 +1,72 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __MMIO_H__
#define __MMIO_H__
#include <stdint.h>
#define mmio_wr32 mmio_write_32
#define mmio_rd32 mmio_read_32
static inline void mmio_write_8(uintptr_t addr, uint8_t value)
{
*(volatile uint8_t*)addr = value;
}
static inline uint8_t mmio_read_8(uintptr_t addr)
{
return *(volatile uint8_t*)addr;
}
static inline void mmio_write_16(uintptr_t addr, uint16_t value)
{
*(volatile uint16_t*)addr = value;
}
static inline uint16_t mmio_read_16(uintptr_t addr)
{
return *(volatile uint16_t*)addr;
}
static inline void mmio_write_32(uintptr_t addr, uint32_t value)
{
*(volatile uint32_t*)addr = value;
}
static inline uint32_t mmio_read_32(uintptr_t addr)
{
return *(volatile uint32_t*)addr;
}
static inline void mmio_write_64(uintptr_t addr, uint64_t value)
{
*(volatile uint64_t*)addr = value;
}
static inline uint64_t mmio_read_64(uintptr_t addr)
{
return *(volatile uint64_t*)addr;
}
static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear)
{
mmio_write_32(addr, mmio_read_32(addr) & ~clear);
}
static inline void mmio_setbits_32(uintptr_t addr, uint32_t set)
{
mmio_write_32(addr, mmio_read_32(addr) | set);
}
static inline void mmio_clrsetbits_32(uintptr_t addr,
uint32_t clear,
uint32_t set)
{
mmio_write_32(addr, (mmio_read_32(addr) & ~clear) | set);
}
#endif /* __MMIO_H__ */

84
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform.c Normal file
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@ -0,0 +1,84 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "xparameters.h"
#include "xil_cache.h"
#include "platform_config.h"
#include "uart_dw.h"
/*
* Uncomment one of the following two lines, depending on the target,
* if ps7/psu init source files are added in the source directory for
* compiling example outside of SDK.
*/
/*#include "ps7_init.h"*/
/*#include "psu_init.h"*/
#ifdef STDOUT_IS_16550
#include "xuartns550_l.h"
#define UART_BAUD 9600
#endif
void
init_uart()
{
uart_init();
#ifdef STDOUT_IS_16550
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
/* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
}
void
init_platform()
{
/*
* If you want to run this example outside of SDK,
* uncomment one of the following two lines and also #include "ps7_init.h"
* or #include "ps7_init.h" at the top, depending on the target.
* Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
* along with this example source files for compilation.
*/
/* ps7_init();*/
/* psu_init();*/
enable_caches();
init_uart();
}
void
cleanup_platform()
{
disable_caches();
}

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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef __PLATFORM_H_
#define __PLATFORM_H_
#include "platform_config.h"
void init_platform();
void cleanup_platform();
#endif

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#ifndef __PLATFORM_CONFIG_H_
#define __PLATFORM_CONFIG_H_
#define STDOUT_IS_PSU_UART
#define UART_DEVICE_ID 0
#endif

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#include <stdint.h>
#include <string.h>
#include "system_common.h"
#include "uart.h"
#include "mmio.h"
//#include "bm1880v2_reg_fmux_gpio.h"
//#include "bm1880v2_pinlist_swconfig.h"
void system_init(void)
{
uart_init();
//irq_init();
xil_printf("system init done\n");
}
struct irq_action {
irq_handler_t handler;
unsigned long flags;
unsigned int irqn;
void *priv;
char name[32];
};
static struct irq_action g_irq_action[32];
__weak void invalidate_dcache_range(unsigned long start, unsigned long size) {}
__weak void flush_dcache_range(unsigned long start, unsigned long size) {}
__weak void invalidate_icache_all(void) {}
__weak void invalidate_dcache_all(void) {}
/*
* GIC driver
*/
#define REG_BASE_GICD 0x01F01000
#define REG_BASE_GICC 0x01F02000
#define GIC_CPU_CTRL 0x00
#define GIC_CPU_PRIMASK 0x04
#define GIC_CPU_BINPOINT 0x08
#define GIC_CPU_INTACK 0x0c
#define GIC_CPU_EOI 0x10
#define GIC_CPU_RUNNINGPRI 0x14
#define GIC_CPU_HIGHPRI 0x18
#define GIC_DIST_CTRL 0x000
#define GIC_DIST_CTR 0x004
#define GIC_DIST_IGROUP 0x080
#define GIC_DIST_ENABLE_SET 0x100
#define GIC_DIST_ENABLE_CLEAR 0x180
#define GIC_DIST_PENDING_SET 0x200
#define GIC_DIST_PENDING_CLEAR 0x280
#define GIC_DIST_ACTIVE_SET 0x300
#define GIC_DIST_ACTIVE_CLEAR 0x380
#define GIC_DIST_PRI 0x400
#define GIC_DIST_TARGET 0x800
#define GIC_DIST_CONFIG 0xc00
#define GIC_DIST_SOFTINT 0xf00
#define GICC_DIS_BYPASS_MASK 0x1e0
static inline uint32_t read_reg(uint64_t addr)
{
return *((volatile uint32_t *)addr);
}
static inline void write_reg(uint64_t addr, uint32_t value)
{
*((volatile uint32_t *)addr) = value;
}
struct gic_data {
uint64_t dist_base;
uint64_t cpu_base;
int gic_irqs;
int hwirq_base;
void *chip;
};
struct irq_chip {
const char *name;
void (*irq_mask)(struct gic_data *data, int irq_num);
void (*irq_unmask)(struct gic_data *data, int irq_num);
int (*irq_ack)(struct gic_data *data);
void (*irq_set_priority)(struct gic_data *data, int irq_num, int priority);
void (*irq_eoi)(struct gic_data *data, int irq_num);
void (*irq_set_type)(struct gic_data *data, uint32_t flow_type);
};
static void gicd_init(void);
static void gicc_init(void);
static struct irq_chip gic_chip;
static struct gic_data gic_data = {
.dist_base = REG_BASE_GICD,
.cpu_base = REG_BASE_GICC,
.chip = &gic_chip
};
static inline uint32_t gic_data_dist_base(struct gic_data *gic)
{
return gic->dist_base;
}
static inline uint32_t gic_data_cpu_base(struct gic_data *gic)
{
return gic->cpu_base;
}
static void irq_trigger_mode(int irqn, int mode)
{
uint32_t reg_addr, off_in_reg, data;
reg_addr = gic_data_dist_base(&gic_data) + GIC_DIST_CONFIG + (irqn / 16) * 4;
off_in_reg = (irqn % 16) * 2;
data = read_reg(reg_addr);
data &= ~(3 << off_in_reg);
data |= mode << off_in_reg;
write_reg(reg_addr, data);
}
void irq_trigger(int irqn)
{
irqn += gic_data.hwirq_base;
write_reg(gic_data_dist_base(&gic_data) + GIC_DIST_PENDING_SET + (irqn / 32) * 4, 1 << (irqn % 32));
}
void irq_clear(int irqn)
{
irqn += gic_data.hwirq_base;
write_reg(gic_data_dist_base(&gic_data) + GIC_DIST_PENDING_CLEAR + (irqn / 32) * 4, 1 << (irqn % 32));
}
int irq_get_nums(void)
{
return gic_data.gic_irqs - gic_data.hwirq_base;
}
static void gic_mask_irq(struct gic_data *d, int irq_num)
{
uint32_t mask = 1 << (irq_num % 32);
write_reg(gic_data_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (irq_num / 32) * 4, mask);
}
static void gic_unmask_irq(struct gic_data *d, int irq_num)
{
uint32_t mask = 1 << (irq_num % 32);
write_reg(gic_data_dist_base(d) + GIC_DIST_ENABLE_SET + (irq_num / 32) * 4, mask);
}
static void gic_eoi_irq(struct gic_data *d, int irq_num)
{
write_reg(gic_data_cpu_base(d) + GIC_CPU_EOI, irq_num);
}
static int gic_ack_irq(struct gic_data *d)
{
return read_reg(gic_data_cpu_base(d) + GIC_CPU_INTACK);
}
static void gic_set_priority_irq(struct gic_data *d, int irq_num, int priority)
{
uint32_t reg;
uint32_t spi_pri_base = gic_data_dist_base(d) + GIC_DIST_PRI;
int bit;
reg = read_reg(spi_pri_base + (irq_num / 4 * 4));
bit = (irq_num % 4) * 8;
reg &= ~(0xF0UL << bit);
reg |= (0xF0UL & (priority << 4)) << bit;
write_reg(spi_pri_base + (irq_num / 4 * 4), reg);
}
static void gic_set_type(struct gic_data *d, uint32_t type)
{
return;
}
static struct irq_chip gic_chip = {
.name = "GIC",
.irq_mask = gic_mask_irq,
.irq_unmask = gic_unmask_irq,
.irq_ack = gic_ack_irq,
.irq_set_priority = gic_set_priority_irq,
.irq_eoi = gic_eoi_irq,
.irq_set_type = gic_set_type,
};
static uint8_t gic_get_cpumask(struct gic_data *data)
{
uint32_t base = gic_data_dist_base(&gic_data);
uint32_t mask, i;
for (i = mask = 0; i < 32; i += 4) {
mask = read_reg(base + GIC_DIST_TARGET + i);
mask |= mask >> 16;
mask |= mask >> 8;
if (mask)
break;
}
#ifndef CONFIG_CHIP_BM1882
if (!mask)
xil_printf("GIC CPU mask not found - will fail to boot.\n");
#endif
return mask;
}
static void gicd_init(void)
{
int hwirq_base = 32;
int gic_irqs;
uint32_t base = gic_data_dist_base(&gic_data);
uint32_t cpumask;
int i;
gic_irqs = read_reg(base + GIC_DIST_CTR) & 0x1f;
gic_irqs = (gic_irqs + 1) * 32;
if (gic_irqs > 1020)
gic_irqs = 1020;
gic_data.gic_irqs = gic_irqs;
gic_data.hwirq_base = hwirq_base;
write_reg(base + GIC_DIST_CTRL, 0);
cpumask = gic_get_cpumask(&gic_data);
cpumask |= cpumask << 8;
cpumask |= cpumask << 16;
for (i = 32; i < gic_irqs; i += 4)
write_reg(base + GIC_DIST_TARGET + i * 4 / 4, cpumask);
/* Set all global interrupts to be level triggered, active low. */
for (i = 32; i < gic_irqs; i += 16)
write_reg(base + GIC_DIST_CONFIG + i / 4, 0);
/* Set priority on all global interrupts. */
for (i = 32; i < gic_irqs; i += 4)
write_reg(base + GIC_DIST_PRI + i, 0xa0a0a0a0);
/* Disable all global interrupts. */
for (i = 32; i < gic_irqs; i += 32) {
write_reg(base + GIC_DIST_ACTIVE_CLEAR + i / 8, 0xffffffff);
write_reg(base + GIC_DIST_ENABLE_CLEAR + i / 8, 0xffffffff);
}
write_reg(base + GIC_DIST_CTRL, 1);
}
static void gicc_init(void)
{
int i;
uint32_t base, bypass;
base = gic_data_dist_base(&gic_data);
write_reg(base + GIC_DIST_ACTIVE_CLEAR, 0xffffffff);
write_reg(base + GIC_DIST_ENABLE_CLEAR, 0xffff0000);
write_reg(base + GIC_DIST_ENABLE_SET, 0x0000ffff);
for (i = 0; i < 32; i += 4)
write_reg(base + GIC_DIST_PRI + i * 4 / 4, 0xa0a0a0a0);
base = gic_data_cpu_base(&gic_data);
write_reg(base + GIC_CPU_PRIMASK, 0xf0);
bypass = read_reg(base + GIC_CPU_CTRL);
bypass &= GICC_DIS_BYPASS_MASK;
/* Enable CPU interrupt */
write_reg(base + GIC_CPU_CTRL, bypass | 1);
}
static void cpu_route_irqs_el2(void)
{
int get_arm_current_el(void);
uint64_t el;
uint64_t hcr_el2 = 0x0038; // set AMO, IMO, and FMO
asm volatile(
"mrs %0, currentel\n"
"lsr %0, %0, #2\n"
"and %0, %0, #3\n"
: "=r" (el) : );
if (el == 2) {
asm volatile("mrs x0, hcr_el2\n"
"bic x0, x0, #0x08000000\n" // clear TGE
"orr x0, x0, %0\n"
"msr hcr_el2, x0\n"
:
: "r"(hcr_el2)
: "x0");
}
}
void cpu_enable_irqs(void)
{
cpu_route_irqs_el2();
//Need to fix it with SError Exception
// asm volatile ( \
// "msr daifclr, #6 " \
// : \
// : \
// : "memory"); \
//
}
void cpu_disable_irqs(void)
{
asm volatile ( \
"msr daifset, #6 " \
: \
: \
: "memory"); \
}
void irq_init(void)
{
cpu_enable_irqs();
gicd_init();
gicc_init();
}
int request_irq(unsigned int irqn, irq_handler_t handler, unsigned long flags,
const char *name, void *priv)
{
if ((irqn < 0) || (irqn >= NUM_IRQ))
return -1;
irqn += gic_data.hwirq_base;
if (flags & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING))
irq_trigger_mode(irqn, IRQ_EDGE);
else
irq_trigger_mode(irqn, IRQ_LEVEL);
g_irq_action[irqn].handler = handler;
if (name) {
memcpy(g_irq_action[irqn].name, name, sizeof(g_irq_action[irqn].name));
g_irq_action[irqn].name[sizeof(g_irq_action[irqn].name) - 1] = 0;
}
g_irq_action[irqn].irqn = irqn - gic_data.hwirq_base;
g_irq_action[irqn].flags = flags;
g_irq_action[irqn].priv = priv;
gic_chip.irq_set_priority(&gic_data, irqn, 10);
gic_chip.irq_unmask(&gic_data, irqn);
return 0;
}
void printf_once(char *string, int irq)
{
static uint8_t __print_once = FALSE;
static int id = 0;
if (!__print_once || (id != irq)) {
__print_once = TRUE;
id =(int) irq;
xil_printf("%s %d\n",string, irq);
}
}
void do_irq(void)
{
int irqn;
irqn = gic_chip.irq_ack(&gic_data);
printf_once("do_irq", irqn - 32);
g_irq_action[irqn].handler(g_irq_action[irqn].irqn, g_irq_action[irqn].priv);
gic_chip.irq_eoi(&gic_data, irqn);
}
void disable_irq(unsigned int irqn)
{
irqn += gic_data.hwirq_base;
gic_chip.irq_mask(&gic_data, irqn);
}
void enable_irq(unsigned int irqn)
{
irqn += gic_data.hwirq_base;
gic_chip.irq_unmask(&gic_data, irqn);
}

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#ifndef _SYSTEM_COMMON_H_
#define _SYSTEM_COMMON_H_
#include <stdio.h>
#include "xil_types.h"
#include "bm1882_common.h"
static inline u32 float_to_u32(float x)
{
union {
int ival;
float fval;
} v = { .fval = x };
return v.ival;
}
static inline float u32_to_float(u32 x)
{
union {
int ival;
float fval;
} v = { .ival = x };
return v.fval;
}
#define array_len(a) (sizeof(a) / sizeof(a[0]))
#define ALIGNMENT(x, a) __ALIGNMENT_MASK((x), (typeof(x))(a)-1)
#define __ALIGNMENT_MASK(x, mask) (((x)+(mask))&~(mask))
#define PTR_ALIGNMENT(p, a) ((typeof(p))ALIGNMENT((unsigned long)(p), (a)))
#define IS_ALIGNMENT(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
#define __raw_readb(a) (*(volatile unsigned char *)(a))
#define __raw_readw(a) (*(volatile unsigned short *)(a))
#define __raw_readl(a) (*(volatile unsigned int *)(a))
#define __raw_readq(a) (*(volatile unsigned long long *)(a))
#define __raw_writeb(a,v) (*(volatile unsigned char *)(a) = (v))
#define __raw_writew(a,v) (*(volatile unsigned short *)(a) = (v))
#define __raw_writel(a,v) (*(volatile unsigned int *)(a) = (v))
#define __raw_writeq(a,v) (*(volatile unsigned long long *)(a) = (v))
#define readb(a) __raw_readb(a)
#define readw(a) __raw_readw(a)
#define readl(a) __raw_readl(a)
#define readq(a) __raw_readq(a)
#define writeb(a, v) __raw_writeb(a,v)
#define writew(a, v) __raw_writew(a,v)
#define writel(a, v) __raw_writel(a,v)
#define writeq(a, v) __raw_writeq(a,v)
#define cpu_write8(a, v) writeb(a, v)
#define cpu_write16(a, v) writew(a, v)
#define cpu_write32(a, v) writel(a, v)
#define cpu_read8(a) readb(a)
#define cpu_read16(a) readw(a)
#define cpu_read32(a) readl(a)
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifdef ENABLE_DEBUG
#define debug(fmt, args...) printf(fmt, ##args)
#else
#define debug(...)
#endif
#ifdef ENABLE_PRINT
#define uartlog(fmt, args...) printf(fmt, ##args)
#else
#define uartlog(...)
#endif
#if 0
extern u32 debug_level;
#define debug_out(flag, fmt, args...) \
do { \
if (flag <= debug_level) \
printf(fmt, ##args); \
} while (0)
#endif
static inline void opdelay(unsigned int times)
{
while (times--)
__asm__ volatile("nop");
}
#ifdef USE_BMTAP
#define call_atomic(nodechip_idx, atomic_func, p_command, eng_id) \
emit_task_descriptor(p_command, eng_id)
#endif
#define TOP_USB_PHY_CTRSTS_REG (TOP_BASE + 0x48)
#define UPCR_EXTERNAL_VBUS_VALID_OFFSET 0
#define TOP_DDR_ADDR_MODE_REG (TOP_BASE + 0x64)
#define DAMR_REG_USB_REMAP_ADDR_39_32_OFFSET 16
#define DAMR_REG_USB_REMAP_ADDR_39_32_MSK (0xff)
#define DAMR_REG_VD_REMAP_ADDR_39_32_OFFSET 24
#define DAMR_REG_VD_REMAP_ADDR_39_32_MSK (0xff)
#define SW_RESET (TOP_BASE + 0x3000)
#define JPEG_RESET 4
#define TOP_USB_CTRSTS_REG (TOP_BASE + 0x38)
#define UCR_MODE_STRAP_OFFSET 0
#define UCR_MODE_STRAP_NON 0x0
#define UCR_MODE_STRAP_HOST 0x2
#define UCR_MODE_STRAP_DEVICE 0x4
#define UCR_MODE_STRAP_MSK (0x7)
#define UCR_PORT_OVER_CURRENT_ACTIVE_OFFSET 10
#define UCR_PORT_OVER_CURRENT_ACTIVE_MSK 1
#define PINMUX_UART0 0
#define PINMUX_UART1 1
#define PINMUX_UART2 2
#define PINMUX_UART3 3
#define PINMUX_UART3_2 4
#define PINMUX_I2C0 5
#define PINMUX_I2C1 6
#define PINMUX_I2C2 7
#define PINMUX_I2C3 8
#define PINMUX_I2C4 9
#define PINMUX_I2C4_2 10
#define PINMUX_SPI0 11
#define PINMUX_SPI1 12
#define PINMUX_SPI2 13
#define PINMUX_SPI2_2 14
#define PINMUX_SPI3 15
#define PINMUX_SPI3_2 16
#define PINMUX_I2S0 17
#define PINMUX_I2S1 18
#define PINMUX_I2S2 19
#define PINMUX_I2S3 20
#define PINMUX_USBID 21
#define PINMUX_SDIO0 22
#define PINMUX_SDIO1 23
#define PINMUX_ND 24
#define PINMUX_EMMC 25
#define PINMUX_SPI_NOR 26
#define PINMUX_SPI_NAND 27
#define PINMUX_CAM0 28
#define PINMUX_CAM1 29
#define PINMUX_PCM0 30
#define PINMUX_PCM1 31
#define PINMUX_CSI0 32
#define PINMUX_CSI1 33
#define PINMUX_CSI2 34
#define PINMUX_DSI 35
#define PINMUX_VI0 36
#define PINMUX_VO 37
#define PINMUX_PWM1 38
/* addr remap */
#define REG_TOP_ADDR_REMAP 0x0064
#define ADDR_REMAP_USB(a) ((a&0xFF)<<16)
/* rst */
#define REG_TOP_SOFT_RST 0x3000
#define BIT_TOP_SOFT_RST_AP (1 << 1)
#define BIT_TOP_SOFT_RST_USB (1 << 11)
#define BIT_TOP_SOFT_RST_SDIO (1 << 14)
/* irq */
#define IRQ_LEVEL 0
#define IRQ_EDGE 3
#define SDMA_INTR 0
#define I2S0_TX_EMP_INTR 1
#define I2S0_TX_OR_INTR 2
#define I2S0_RX_DA_INTR 3
#define I2S0_RX_OR_INTR 4
#define I2S1_TX_EMP_INTR 5
#define I2S1_TX_OR_INTR 6
#define I2S1_RX_DA_INTR 7
#define I2S1_RX_OR_INTR 8
#define UART_INTR_UART0 9
#define UART_DMA_TX_REQ_UART0 10
#define UART_DMA_RX_REQ_UART0 11
#define UART_INTR_UART1 12
#define UART_DMA_TX_REQ_UART1 13
#define UART_DMA_RX_REQ_UART1 14
#define UART_INTR_UART2 15
#define UART_DMA_TX_REQ_UART2 16
#define UART_DMA_RX_REQ_UART2 17
#define UART_INTR_UART3 18
#define UART_DMA_TX_REQ_UART3 19
#define UART_DMA_RX_REQ_UART3 20
#define RTC_ALARM_O 21
#define SD1_WAKEUP_INTR 22
#define SD1_INTR 23
#define ETH1_SBD_PERCH_RX_INTR_O_0 24
#define ETH1_SBD_PERCH_RX_INTR_O_1 25
#define ETH1_SBD_PERCH_RX_INTR_O_2 26
#define ETH1_SBD_PERCH_RX_INTR_O_3 27
#define ETH1_SBD_PERCH_RX_INTR_O_4 28
#define ETH1_SBD_PERCH_RX_INTR_O_5 29
#define ETH1_SBD_PERCH_RX_INTR_O_6 30
#define ETH1_SBD_PERCH_RX_INTR_O_7 31
#define ETH1_SBD_PERCH_TX_INTR_O_0 32
#define ETH1_SBD_PERCH_TX_INTR_O_1 33
#define ETH1_SBD_PERCH_TX_INTR_O_2 34
#define ETH1_SBD_PERCH_TX_INTR_O_3 35
#define ETH1_SBD_PERCH_TX_INTR_O_4 36
#define ETH1_SBD_PERCH_TX_INTR_O_5 37
#define ETH1_SBD_PERCH_TX_INTR_O_6 38
#define ETH1_SBD_PERCH_TX_INTR_O_7 39
#define ETH0_SBD_PERCH_RX_INTR_O_0 40
#define ETH0_SBD_PERCH_RX_INTR_O_1 41
#define ETH0_SBD_PERCH_RX_INTR_O_2 42
#define ETH0_SBD_PERCH_RX_INTR_O_3 43
#define ETH0_SBD_PERCH_RX_INTR_O_4 44
#define ETH0_SBD_PERCH_RX_INTR_O_5 45
#define ETH0_SBD_PERCH_RX_INTR_O_6 46
#define ETH0_SBD_PERCH_RX_INTR_O_7 47
#define ETH0_SBD_PERCH_TX_INTR_O_0 48
#define ETH0_SBD_PERCH_TX_INTR_O_1 49
#define ETH0_SBD_PERCH_TX_INTR_O_2 50
#define ETH0_SBD_PERCH_TX_INTR_O_3 51
#define ETH0_SBD_PERCH_TX_INTR_O_4 52
#define ETH0_SBD_PERCH_TX_INTR_O_5 53
#define ETH0_SBD_PERCH_TX_INTR_O_6 54
#define ETH0_SBD_PERCH_TX_INTR_O_7 55
#define ETH1_SBD_INTR_O 56
#define ETH0_SBD_INTR_O 57
#define SD0_WAKEUP_INTR 58
#define SD0_INTR 59
#define EMMC_WAKEUP_INTR 60
#define EMMC_INTR 61
// #define NA 62
#define DDR_PI_PHY_INTR 63
#define SF_SPI_INT 64
#define SPI_0_SSI_INTR 65
#define GPIO2_INTR_FLAG 66
#define GPIO1_INTR_FLAG 67
#define GPIO0_INTR_FLAG 68
#define WDT_INTR 69
#define IC4_INTR 70
#define IC3_INTR 71
#define IC2_INTR 72
#define IC1_INTR 73
#define IC0_INTR 74
#define JPEG_INTRPT_REQ 75
#define H264C_INTERRUPT 76
#define H265C_INTERRUPT 77
// #define NA 78
#define TPU_INTR 79
#define TDMA_INTERRUPT 80
// #define NA 81
#define USB_OTGIRQ 82
#define USB_IRQS_0 83
#define USB_IRQS_1 84
#define USB_INTERRUPT_REQ_0 85
#define USB_INTERRUPT_REQ_1 86
#define USB_INTERRUPT_REQ_2 87
#define USB_INTERRUPT_REQ_3 88
#define USB_INTERRUPT_REQ_4 89
#define USB_INTERRUPT_REQ_5 90
#define USB_INTERRUPT_REQ_6 91
#define USB_INTERRUPT_REQ_7 92
// #define NA 93
// #define NA 94
// #define NA 95
#define NPMUIRQ_0 96
#define NPMUIRQ_1 97
#define NPMUIRQ_2 98
#define NPMUIRQ_3 99
#define CTIIRQ_0 100
#define CTIIRQ_1 101
#define CTIIRQ_2 102
#define CTIIRQ_3 103
#define NEXTERRIRQ 104
// #define NA 105
// #define NA 106
// #define NA 107
#define GP_REG15_0 108
#define GP_REG15_1 109
#define GP_REG15_2 110
#define GP_REG15_3 111
#define GP_REG15_4 112
#define GP_REG15_5 113
#define GP_REG15_6 114
#define GP_REG15_7 115
#define GP_REG15_8 116
#define GP_REG15_9 117
#define GP_REG15_10 118
#define GP_REG15_11 119
#define GP_REG15_12 120
#define GP_REG15_13 121
#define GP_REG15_14 122
#define GP_REG15_15 123
#define SPI_1_SSI_INTR 124
#define SPI_2_SSI_INTR 125
#define SPI_3_SSI_INTR 126
#define I2S2_TX_EMP_INTR 127
#define I2S2_TX_OR_INTR 128
#define I2S2_RX_DA_INTR 129
#define I2S2_RX_OR_INTR 130
#define I2S3_TX_EMP_INTR 131
#define I2S3_TX_OR_INTR 132
#define I2S3_RX_DA_INTR 133
#define I2S3_RX_OR_INTR 134
// #define NA 135
// #define NA 136
// #define NA 137
#define VIP_INT_ISP_TOP 138
#define VIP_INT_SC_TOP_0 139
#define VIP_INT_SC_TOP_1 140
#define VIP_INT_SC_TOP_2 141
#define VIP_INT_SC_TOP_3 142
#define VIP_INT_SC_TOP_4 143
#define VIP_INT_SC_TOP_5 144
#define VIP_INT_SC_TOP_6 145
#define VIP_INT_SC_TOP_7 146
#define VIP_INT_SC_TOP_8 147
#define VIP_INT_SC_TOP_9 148
#define VIP_INT_SC_TOP_10 149
#define VIP_INT_SC_TOP_11 150
#define VIP_INT_SC_TOP_12 151
#define VIP_INT_SC_TOP_13 152
#define VIP_INT_SC_TOP_14 153
#define VIP_INT_SC_TOP_15 154
#define VIP_INT_CSI_MAC0 155
#define VIP_INT_CSI_MAC1 156
#define VIP_INT_DWA_WRAP 157
// #define NA 158
#define PERI_FIREWALL_IRQ 159
#define HSPERI_FIREWALL_IRQ 160
#define SPACC_IRQ 161
#define TRNG_IRQ 162
// #define NA 163
#define TEMPSEN_IRQ_O 164
#define INTR_SARADC 165
// #define NA 166
// #define NA 167
// #define NA 168
#define DDR_FW_INTR 169
#define ROM_FIREWALL_IRQ 170
#define SRAM_FIREWALL_IRQ 171
#define DDR_AXI_MON_INTR 172
// #define NA 173
// #define NA 174
// #define NA 175
// #define NA 176
// #define NA 177
// #define NA 178
// #define NA 179
#define TIMER_INTR_FLAG 180
#define SPI_NAND_INTR 181
#define DBGSYS_APBUSMON_HANG_INT 182
#define IRQF_TRIGGER_NONE 0x00000000
#define IRQF_TRIGGER_RISING 0x00000001
#define IRQF_TRIGGER_FALLING 0x00000002
#define IRQF_TRIGGER_HIGH 0x00000004
#define IRQF_TRIGGER_LOW 0x00000008
#define IRQF_TRIGGER_MASK (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW | \
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)
typedef int (*irq_handler_t)(int irqn, void *priv);
extern int request_irq(unsigned int irqn, irq_handler_t handler, unsigned long flags,
const char *name, void *priv);
void disable_irq(unsigned int irqn);
void enable_irq(unsigned int irqn);
void cpu_enable_irqs(void);
void cpu_disable_irqs(void);
extern void irq_trigger(int irqn);
extern void irq_clear(int irqn);
extern int irq_get_nums(void);
void pinmux_config(int io_type);
/*FIXME
* NUM_IRQ may be different accross
* different platform, we should review it when porting
*/
#define NUM_IRQ (256)
#define SPI_SECTOR_SIZE 256
#define SPI_DMMR_TEST_SIZE 1024
#endif

40
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/timer_dw.c Executable file
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#include <stddef.h>
#include <string.h>
#include <stdint.h>
#include "debug.h"
#include "mmio.h"
#include "timer_dw.h"
#define DBG_DW_TIMER
void dw_timer_start(uint32_t timer_id)
{
// disable timer
mmio_write_32(REG_TIMER1_CONTROL + timer_id * 0x14, 0x0);
// set timer load count
mmio_write_32(REG_TIMER1_LOADCNT + timer_id * 0x14, PRELOAD_CNT);
// enable timer
mmio_write_32(REG_TIMER1_CONTROL + timer_id * 0x14, 0x1);
INFO("dw_timer_start\n");
}
void dw_timer_stop(uint32_t timer_id, uint32_t *write_addr)
{
uint32_t time_end;
uint32_t timer_interval_ms;
time_end = mmio_read_32(REG_TIMER1_CURRENT_VALUE + timer_id * 0x14);
INFO("BLD: time_end=0x%x\n", time_end);
// disable timer
mmio_write_32(REG_TIMER1_CONTROL + timer_id * 0x14, 0x0);
timer_interval_ms = (PRELOAD_CNT - time_end) * NS_PER_TICK / 1000000;
INFO("timer ms = %d\n", timer_interval_ms);
*write_addr = timer_interval_ms;
}

38
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/timer_dw.h Executable file
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#ifndef __DW_TIMER_H
#define __DW_TIMER_H
#include <stdint.h>
#include <platform_def.h>
#define NS_PER_TICK (1000000000UL / PLAT_DW_TIMER_CLK_HZ)
#define PRELOAD_CNT 0xFFFFFFFF
#define TIMER_ID1 0x0
#define TIMER_ID2 0x1
#define TIMER_ID3 0x2
#define TIMER_ID4 0x3
#define TIMER_ID5 0x4
#define TIMER_ID6 0x5
#define TIMER_ID7 0x6
#define TIMER_ID8 0x7
#define REG_TIMER_BASE 0x030A0000
#define REG_TIMER1_BASE (REG_TIMER_BASE + 0x00)
#define REG_TIMERS_INTSTATUS (REG_TIMER_BASE + 0xA0)
#define REG_TIMERS_EOI (REG_TIMER_BASE + 0xA4)
#define REG_TIMERS_RAW_INTSTATUS (REG_TIMER_BASE + 0xA8)
#define REG_TIMERS_COMP_VERSION (REG_TIMER_BASE + 0xAC)
#define REG_TIMERN_LOADCNT2_BASE (REG_TIMER_BASE + 0xB0)
#define REG_TIMER1_LOADCNT REG_TIMER1_BASE
#define REG_TIMER1_LOADCNT2 (REG_TIMERN_LOADCNT2_BASE + 0x00)
#define REG_TIMER1_CURRENT_VALUE (REG_TIMER1_BASE + 0x04)
#define REG_TIMER1_CONTROL (REG_TIMER1_BASE + 0x08)
#define REG_TIMER1_EOI (REG_TIMER1_BASE + 0x0C)
#define REG_TIMER1_INTSTATUS (REG_TIMER1_BASE + 0x10)
void dw_timer_start(uint32_t timer_id);
void dw_timer_stop(uint32_t timer_id, uint32_t *write_addr);
#endif /* __DW_TIMER_H */

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freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/uart.h Executable file
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#ifndef _UART_H_
#define _UART_H_
#include <stdint.h>
void uart_init(void);
int uart_getc(void);
int uart_tstc(void);
void uart_putc(uint8_t ch);
void uart_puts(char *str);
#endif

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freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/uart_dw.c Executable file
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#include <stdint.h>
#define thr rbr
#define iir fcr
#define dll rbr
#define dlm ier
struct dw_regs {
volatile uint32_t rbr; /* 0x00 Data register */
volatile uint32_t ier; /* 0x04 Interrupt Enable Register */
volatile uint32_t fcr; /* 0x08 FIFO Control Register */
volatile uint32_t lcr; /* 0x0C Line control register */
volatile uint32_t mcr; /* 0x10 Line control register */
volatile uint32_t lsr; /* 0x14 Line Status Register */
volatile uint32_t msr; /* 0x18 Modem Status Register */
volatile uint32_t spr; /* 0x20 Scratch Register */
};
#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
#define UART_LCR_PEN 0x08 /* Parity eneble */
#define UART_LCR_EPS 0x10 /* Even Parity Select */
#define UART_LCR_STKP 0x20 /* Stick Parity */
#define UART_LCR_SBRK 0x40 /* Set Break */
#define UART_LCR_BKSE 0x80 /* Bank select enable */
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
#define UART_MCR_DTR 0x01 /* DTR */
#define UART_MCR_RTS 0x02 /* RTS */
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
#define UART_LSR_DR 0x01 /* Receiver data ready */
#define UART_LSR_TEMT 0x40 /* Xmitter empty */
#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */
#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR)
#define UART_LCR_8N1 0x03
static struct dw_regs *uart = (struct dw_regs *)0x04140000;
void uart_init(void)
{
int baudrate = 115200;
int uart_clock = 25 * 1000 * 1000;
int divisor = uart_clock / (16 * baudrate);
uart->lcr = uart->lcr | UART_LCR_DLAB | UART_LCR_8N1;
uart->dll = divisor & 0xff;
uart->dlm = (divisor >> 8) & 0xff;
uart->lcr = uart->lcr & (~UART_LCR_DLAB);
uart->ier = 0;
uart->mcr = UART_MCRVAL;
uart->fcr = UART_FCR_DEFVAL;
uart->lcr = 3;
}
void _uart_putc(uint8_t ch)
{
while (!(uart->lsr & UART_LSR_THRE))
;
uart->rbr= ch;
}
void uart_putc(uint8_t ch)
{
if (ch == '\n') {
_uart_putc('\r');
}
_uart_putc(ch);
}
void uart_puts(char *str)
{
if (!str)
return;
while (*str) {
uart_putc(*str++);
}
}
int uart_getc(void)
{
while (!(uart->lsr & UART_LSR_DR))
;
return (int)uart->rbr;
}
int uart_tstc(void)
{
return (!!(uart->lsr & UART_LSR_DR));
}

12
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/uart_dw.h Normal file
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#ifndef _UART_H_
#define _UART_H_
#include <stdint.h>
void uart_init(void);
int uart_getc(void);
int uart_tstc(void);
void uart_putc(uint8_t ch);
void uart_puts(char *str);
#endif

13
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.cproject Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.200132248">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.200132248" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
</cproject>

75
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RTOSDemo_A53_bsp</name>
<comment>Created by SDK v2018.1</comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.make.core.makeBuilder</name>
<arguments>
<dictionary>
<key>org.eclipse.cdt.core.errorOutputParser</key>
<value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.arguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.command</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.auto</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.clean</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.inc</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.environment</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdk.sw.SwProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.make.core.makeNature</nature>
</natures>
</projectDescription>

4
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.sdkproject Normal file
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THIRPARTY=false
HW_PROJECT_REFERENCE=ZynqMP_ZCU102_hw_platform
PROCESSOR=psu_cortexa53_0
MSS_FILE=system.mss

35
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/Makefile Normal file
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# Makefile generated by Xilinx.
PROCESSOR = psu_cortexa53_0
LIBRARIES = ${PROCESSOR}/lib/libxil.a
BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
ifneq (,$(findstring win,$(RDI_PLATFORM)))
SHELL = CMD
endif
all: libs
@echo 'Finished building libraries'
include: $(addsuffix /make.include,$(SUBDIRS))
libs: $(addsuffix /make.libs,$(SUBDIRS))
clean: $(addsuffix /make.clean,$(SUBDIRS))
$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
cp -f $< $@
%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
@echo "Running Make include in $(subst /make.include,,$@)"
$(MAKE) -C $(subst /make.include,,$@) include "SHELL=$(SHELL)" "COMPILER=aarch64-elf-gcc" "ARCHIVER=aarch64-elf-ar" "COMPILER_FLAGS= -O2 -c -ffunction-sections -fdata-sections" "EXTRA_COMPILER_FLAGS=-g -Wall -Wextra -DFREERTOS_BSP"
%/make.libs: include
@echo "Running Make libs in $(subst /make.libs,,$@)"
$(MAKE) -C $(subst /make.libs,,$@) libs "SHELL=$(SHELL)" "COMPILER=aarch64-elf-gcc" "ARCHIVER=aarch64-elf-ar" "COMPILER_FLAGS= -O2 -c -ffunction-sections -fdata-sections" "EXTRA_COMPILER_FLAGS=-g -Wall -Wextra -DFREERTOS_BSP"
%/make.clean:
$(MAKE) -C $(subst /make.clean,,$@) -s clean
clean:
rm -f ${PROCESSOR}/lib/libxil.a

48
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/bspconfig.h Executable file
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Configurations for Standalone BSP
*
*******************************************************************/
#ifndef BSPCONFIG_H /* prevent circular inclusions */
#define BSPCONFIG_H /* by using protection macros */
#define MICROBLAZE_PVR_NONE
#define EL3 0
#define EL1_NONSECURE 1
#define HYP_GUEST 0
#endif /*end of __BSPCONFIG_H_*/

70
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/linkage.h Normal file
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/*
* U-Boot - linkage.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _LINUX_LINKAGE_H
#define _LINUX_LINKAGE_H
/* Some toolchains use other characters (e.g. '`') to mark new line in macro */
#ifndef ASM_NL
#define ASM_NL ;
#endif
#ifdef __cplusplus
#define CPP_ASMLINKAGE extern "C"
#else
#define CPP_ASMLINKAGE
#endif
#ifndef asmlinkage
#define asmlinkage CPP_ASMLINKAGE
#endif
#define SYMBOL_NAME_STR(X) #X
#define SYMBOL_NAME(X) X
#ifdef __STDC__
#define SYMBOL_NAME_LABEL(X) X##:
#else
#define SYMBOL_NAME_LABEL(X) X:
#endif
#ifndef __ALIGN
#define __ALIGN .align 4
#endif
#ifndef __ALIGN_STR
#define __ALIGN_STR ".align 4"
#endif
#define ALIGN __ALIGN
#define ALIGN_STR __ALIGN_STR
#define LENTRY(name) \
ALIGN ASM_NL \
SYMBOL_NAME_LABEL(name)
#define ENTRY(name) \
.globl SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#define WEAK(name) \
.weak SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#ifndef END
#define END(name) \
.size name, .-name
#endif
#ifndef ENDPROC
#define ENDPROC(name) \
.type name STT_FUNC ASM_NL \
END(name)
#endif
#endif

329
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/macro.h Normal file
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/*
* include/asm-arm/macro.h
*
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARM_MACRO_H__
#define __ASM_ARM_MACRO_H__
#ifdef CONFIG_ARM64
#include <asm/system.h>
#endif
/*
* These macros provide a convenient way to write 8, 16 and 32 bit data
* to any address.
* Registers r4 and r5 are used, any data in these registers are
* overwritten by the macros.
* The macros are valid for any ARM architecture, they do not implement
* any memory barriers so caution is recommended when using these when the
* caches are enabled or on a multi-core system.
*/
.macro write32, addr, data
ldr r4, =\addr
ldr r5, =\data
str r5, [r4]
.endm
.macro write16, addr, data
ldr r4, =\addr
ldrh r5, =\data
strh r5, [r4]
.endm
.macro write8, addr, data
ldr r4, =\addr
ldrb r5, =\data
strb r5, [r4]
.endm
/*
* This macro generates a loop that can be used for delays in the code.
* Register r4 is used, any data in this register is overwritten by the
* macro.
* The macro is valid for any ARM architeture. The actual time spent in the
* loop will vary from CPU to CPU though.
*/
.macro wait_timer, time
ldr r4, =\time
1:
nop
subs r4, r4, #1
bcs 1b
.endm
/*
* Register aliases.
*/
lr .req x30
/*
* Branch according to exception level
*/
.macro switch_el, xreg, el3_label, el2_label, el1_label
mrs \xreg, CurrentEL
cmp \xreg, 0xc
b.eq \el3_label
cmp \xreg, 0x8
b.eq \el2_label
cmp \xreg, 0x4
b.eq \el1_label
.endm
/*
* Branch if current processor is a Cortex-A57 core.
*/
.macro branch_if_a57_core, xreg, a57_label
mrs \xreg, midr_el1
lsr \xreg, \xreg, #4
and \xreg, \xreg, #0x00000FFF
cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
b.eq \a57_label
.endm
/*
* Branch if current processor is a Cortex-A53 core.
*/
.macro branch_if_a53_core, xreg, a53_label
mrs \xreg, midr_el1
lsr \xreg, \xreg, #4
and \xreg, \xreg, #0x00000FFF
cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
b.eq \a53_label
.endm
/*
* Branch if current processor is a slave,
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_slave, xreg, slave_label
#ifdef CONFIG_ARMV8_MULTIENTRY
/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
mrs \xreg, mpidr_el1
tst \xreg, #0xff /* Test Affinity 0 */
b.ne \slave_label
lsr \xreg, \xreg, #8
tst \xreg, #0xff /* Test Affinity 1 */
b.ne \slave_label
lsr \xreg, \xreg, #8
tst \xreg, #0xff /* Test Affinity 2 */
b.ne \slave_label
lsr \xreg, \xreg, #16
tst \xreg, #0xff /* Test Affinity 3 */
b.ne \slave_label
#endif
.endm
/*
* Branch if current processor is a master,
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_master, xreg1, xreg2, master_label
#ifdef CONFIG_ARMV8_MULTIENTRY
/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
mrs \xreg1, mpidr_el1
lsr \xreg2, \xreg1, #32
lsl \xreg1, \xreg1, #40
lsr \xreg1, \xreg1, #40
orr \xreg1, \xreg1, \xreg2
cbz \xreg1, \master_label
#else
b \master_label
#endif
.endm
/*
* Switch from EL3 to EL2 for ARMv8
* @ep: kernel entry point
* @flag: The execution state flag for lower exception
* level, ES_TO_AARCH64 or ES_TO_AARCH32
* @tmp: temporary register
*
* For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
* For loading 64-bit OS, x0 is physical address to the FDT blob.
* They will be passed to the guest.
*/
.macro armv8_switch_to_el2_m, ep, flag, tmp
msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
mov \tmp, #CPTR_EL2_RES1
msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
/* Initialize Generic Timers */
msr cntvoff_el2, xzr
/* Initialize SCTLR_EL2
*
* setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
* and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
* EE,WXN,I,SA,C,A,M to 0
*/
ldr \tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\
SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\
SCTLR_EL2_SA_DIS | SCTLR_EL2_DCACHE_DIS |\
SCTLR_EL2_ALIGN_DIS | SCTLR_EL2_MMU_DIS)
msr sctlr_el2, \tmp
mov \tmp, sp
msr sp_el2, \tmp /* Migrate SP */
mrs \tmp, vbar_el3
msr vbar_el2, \tmp /* Migrate VBAR */
/* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */
cmp \flag, #ES_TO_AARCH32
b.eq 1f
/*
* The next lower exception level is AArch64, 64bit EL2 | HCE |
* RES1 (Bits[5:4]) | Non-secure EL0/EL1.
* and the SMD depends on requirements.
*/
#ifdef CONFIG_ARMV8_PSCI
ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
SCR_EL3_RES1 | SCR_EL3_NS_EN)
#else
ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
SCR_EL3_NS_EN)
#endif
msr scr_el3, \tmp
/* Return to the EL2_SP2 mode from EL3 */
ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
SPSR_EL_M_AARCH64 | SPSR_EL_M_EL2H)
msr spsr_el3, \tmp
msr elr_el3, \ep
eret
1:
/*
* The next lower exception level is AArch32, 32bit EL2 | HCE |
* SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
*/
ldr \tmp, =(SCR_EL3_RW_AARCH32 | SCR_EL3_HCE_EN |\
SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
SCR_EL3_NS_EN)
msr scr_el3, \tmp
/* Return to AArch32 Hypervisor mode */
ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
SPSR_EL_M_HYP)
msr spsr_el3, \tmp
msr elr_el3, \ep
eret
.endm
/*
* Switch from EL2 to EL1 for ARMv8
* @ep: kernel entry point
* @flag: The execution state flag for lower exception
* level, ES_TO_AARCH64 or ES_TO_AARCH32
* @tmp: temporary register
*
* For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
* For loading 64-bit OS, x0 is physical address to the FDT blob.
* They will be passed to the guest.
*/
.macro armv8_switch_to_el1_m, ep, flag, tmp
/* Initialize Generic Timers */
mrs \tmp, cnthctl_el2
/* Enable EL1 access to timers */
orr \tmp, \tmp, #(CNTHCTL_EL2_EL1PCEN_EN |\
CNTHCTL_EL2_EL1PCTEN_EN)
msr cnthctl_el2, \tmp
msr cntvoff_el2, xzr
/* Initilize MPID/MPIDR registers */
mrs \tmp, midr_el1
msr vpidr_el2, \tmp
mrs \tmp, mpidr_el1
msr vmpidr_el2, \tmp
/* Disable coprocessor traps */
mov \tmp, #CPTR_EL2_RES1
msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
mov \tmp, #CPACR_EL1_FPEN_EN
msr cpacr_el1, \tmp /* Enable FP/SIMD at EL1 */
/* SCTLR_EL1 initialization
*
* setting RES1 bits (29,28,23,22,20,11) to 1
* and RES0 bits (31,30,27,21,17,13,10,6) +
* UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
* CP15BEN,SA0,SA,C,A,M to 0
*/
ldr \tmp, =(SCTLR_EL1_RES1 | SCTLR_EL1_UCI_DIS |\
SCTLR_EL1_EE_LE | SCTLR_EL1_WXN_DIS |\
SCTLR_EL1_NTWE_DIS | SCTLR_EL1_NTWI_DIS |\
SCTLR_EL1_UCT_DIS | SCTLR_EL1_DZE_DIS |\
SCTLR_EL1_ICACHE_DIS | SCTLR_EL1_UMA_DIS |\
SCTLR_EL1_SED_EN | SCTLR_EL1_ITD_EN |\
SCTLR_EL1_CP15BEN_DIS | SCTLR_EL1_SA0_DIS |\
SCTLR_EL1_SA_DIS | SCTLR_EL1_DCACHE_DIS |\
SCTLR_EL1_ALIGN_DIS | SCTLR_EL1_MMU_DIS)
msr sctlr_el1, \tmp
mov \tmp, sp
msr sp_el1, \tmp /* Migrate SP */
mrs \tmp, vbar_el2
msr vbar_el1, \tmp /* Migrate VBAR */
/* Check switch to AArch64 EL1 or AArch32 Supervisor mode */
cmp \flag, #ES_TO_AARCH32
b.eq 1f
/* Initialize HCR_EL2 */
ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
msr hcr_el2, \tmp
/* Return to the EL1_SP1 mode from EL2 */
ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
SPSR_EL_M_AARCH64 | SPSR_EL_M_EL1H)
msr spsr_el2, \tmp
msr elr_el2, \ep
eret
1:
/* Initialize HCR_EL2 */
ldr \tmp, =(HCR_EL2_RW_AARCH32 | HCR_EL2_HCD_DIS)
msr hcr_el2, \tmp
/* Return to AArch32 Supervisor mode from EL2 */
ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
SPSR_EL_M_SVC)
msr spsr_el2, \tmp
msr elr_el2, \ep
eret
.endm
#if defined(CONFIG_GICV3)
.macro gic_wait_for_interrupt_m xreg1
0 : wfi
mrs \xreg1, ICC_IAR1_EL1
msr ICC_EOIR1_EL1, \xreg1
cbnz \xreg1, 0b
.endm
#elif defined(CONFIG_GICV2)
.macro gic_wait_for_interrupt_m xreg1, wreg2
0 : wfi
ldr \wreg2, [\xreg1, GICC_AIAR]
str \wreg2, [\xreg1, GICC_AEOIR]
and \wreg2, \wreg2, #0x3ff
cbnz \wreg2, 0b
.endm
#endif
#endif /* __ASM_ARM_MACRO_H__ */

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/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARMV8_MMU_H_
#define _ASM_ARMV8_MMU_H_
/***************************************************************/
/*
* The following definitions are related each other, shoud be
* calculated specifically.
*/
#define VA_BITS CONFIG_SYS_VA_BITS
#define PTE_BLOCK_BITS CONFIG_SYS_PTL2_BITS
/*
* block/section address mask and size definitions.
*/
#define UL(_v) (unsigned long)(_v)
/* PAGE_SHIFT determines the page size */
#undef PAGE_SIZE
#define PAGE_SHIFT 12
#define PAGE_SIZE (1 << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
/***************************************************************/
/*
* Memory types
*/
#define MT_DEVICE_NGNRNE 0
#define MT_DEVICE_NGNRE 1
#define MT_DEVICE_GRE 2
#define MT_NORMAL_NC 3
#define MT_NORMAL 4
#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
(0x04 << (MT_DEVICE_NGNRE * 8)) | \
(0x0c << (MT_DEVICE_GRE * 8)) | \
(0x44 << (MT_NORMAL_NC * 8)) | \
(UL(0xff) << (MT_NORMAL * 8)))
/*
* Hardware page table definitions.
*
*/
#define PTE_TYPE_MASK (3 << 0)
#define PTE_TYPE_FAULT (0 << 0)
#define PTE_TYPE_TABLE (3 << 0)
#define PTE_TYPE_BLOCK (1 << 0)
#define PTE_TYPE_VALID (1 << 0)
#define PTE_TABLE_PXN (1UL << 59)
#define PTE_TABLE_XN (1UL << 60)
#define PTE_TABLE_AP (1UL << 61)
#define PTE_TABLE_NS (1UL << 63)
/*
* Block
*/
#define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
#define PTE_BLOCK_NS (1 << 5)
#define PTE_BLOCK_NON_SHARE (0 << 8)
#define PTE_BLOCK_AP (2 << 6)
#define PTE_BLOCK_OUTER_SHARE (2 << 8)
#define PTE_BLOCK_INNER_SHARE (3 << 8)
#define PTE_BLOCK_AF (1 << 10)
#define PTE_BLOCK_NG (1 << 11)
#define PTE_BLOCK_PXN (UL(1) << 53)
#define PTE_BLOCK_UXN (UL(1) << 54)
/*
* AttrIndx[2:0]
*/
#define PMD_ATTRINDX(t) ((t) << 2)
#define PMD_ATTRINDX_MASK (7 << 2)
#define PMD_ATTRMASK (PTE_BLOCK_PXN | \
PTE_BLOCK_UXN | \
PMD_ATTRINDX_MASK | \
PTE_TYPE_VALID)
/*
* TCR flags.
*/
#define TCR_T0SZ(x) ((64 - (x)) << 0)
#define TCR_IRGN_NC (0 << 8)
#define TCR_IRGN_WBWA (1 << 8)
#define TCR_IRGN_WT (2 << 8)
#define TCR_IRGN_WBNWA (3 << 8)
#define TCR_IRGN_MASK (3 << 8)
#define TCR_ORGN_NC (0 << 10)
#define TCR_ORGN_WBWA (1 << 10)
#define TCR_ORGN_WT (2 << 10)
#define TCR_ORGN_WBNWA (3 << 10)
#define TCR_ORGN_MASK (3 << 10)
#define TCR_SHARED_NON (0 << 12)
#define TCR_SHARED_OUTER (2 << 12)
#define TCR_SHARED_INNER (3 << 12)
#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG0_16K (2 << 14)
#define TCR_EPD1_DISABLE (1 << 23)
#define TCR_EL1_RSVD (1 << 31)
#define TCR_EL2_RSVD (1 << 31 | 1 << 23)
#define TCR_EL3_RSVD (1 << 31 | 1 << 23)
#ifndef __ASSEMBLY__
static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint64_t attr)
{
#if 1
asm volatile("dsb sy");
if (el == 1) {
asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
} else if (el == 2) {
asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
} else if (el == 3) {
asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
} else {
while(1);
}
asm volatile("isb");
#endif
}
struct mm_region {
uint64_t virt;
uint64_t phys;
uint64_t size;
uint64_t attrs;
};
void enable_caches();
extern struct mm_region *mem_map;
void setup_pgtables(void);
uint64_t get_tcr(int el, uint64_t *pips, uint64_t *pva_bits);
#endif
#endif /* _ASM_ARMV8_MMU_H_ */

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#ifndef RTOS_QUEUE_H
#define RTOS_QUEUE_H
//#include <linux/kernel.h>
//#include <linux/slab.h>
#include <stddef.h>
#include <stdbool.h>
#define QUEUE_NUM 0x20
//typedef size_t unsigned long;
//typedef bool unsigned char;
typedef struct queue_t queue_t;
typedef struct cmdqu_t cmdqu_t;
struct cmdqu_t {
size_t ip_id;
size_t cmd_id;
size_t *param_ptr;
}__attribute__ ((aligned (0x20)));
struct queue_t {
unsigned int head;
unsigned int tail;
char *linux_queue_buffer;
union {
char *queue_buffer;
char *rtos_queue_buffer;
};
};
struct shm_para_t {
unsigned long virt_phy_offset;
union {
// unsigned long linux_cmd_queue_addr;
queue_t linux_cmd_queue;
};
union {
// unsigned long rtos_cmd_queue_addr;
queue_t rtos_cmd_queue;
};
// spinlock_t rtos_memory_lock;
// spinlock_t rtos_queue_lock;
} shm_para_t;
void queue_new(queue_t *self);
bool queue_is_empty(queue_t *self);
bool queue_enqueue(queue_t *self, cmdqu_t *data);
cmdqu_t *queue_peek(queue_t *self);
cmdqu_t *queue_dequeue(queue_t *self);
#endif //RTOS_QUEUE_H

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/******************************************************************************
*
* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file sleep.h
*
* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
* related APIs.
*
* <pre>
* MODIFICATION HISTORY :
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 6.6 srm 11/02/17 Added processor specific sleep rountines
* function prototypes.
*
* </pre>
*
******************************************************************************/
#ifndef SLEEP_H
#define SLEEP_H
#include "xil_types.h"
#include "xil_io.h"
#ifdef __cplusplus
extern "C" {
#endif
/*****************************************************************************/
/**
*
* This macro polls an address periodically until a condition is met or till the
* timeout occurs.
* The minimum timeout for calling this macro is 100us. If the timeout is less
* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
* If the timeout is not a multiple of 100us, it waits for a timeout of
* the next usec value which is a multiple of 100us.
*
* @param IO_func - accessor function to read the register contents.
* Depends on the register width.
* @param ADDR - Address to be polled
* @param VALUE - variable to read the value
* @param COND - Condition to checked (usually involves VALUE)
* @param TIMEOUT_US - timeout in micro seconds
*
* @return 0 - when the condition is met
* -1 - when the condition is not met till the timeout period
*
* @note none
*
*****************************************************************************/
#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
( { \
u64 timeout = TIMEOUT_US/100; \
if(TIMEOUT_US%100!=0) \
timeout++; \
for(;;) { \
VALUE = IO_func(ADDR); \
if(COND) \
break; \
else { \
usleep(100); \
timeout--; \
if(timeout==0) \
break; \
} \
} \
(timeout>0) ? 0 : -1; \
} )
void usleep(unsigned long useconds);
void sleep(unsigned int seconds);
int usleep_R5(unsigned long useconds);
unsigned sleep_R5(unsigned int seconds);
int usleep_MB(unsigned long useconds);
unsigned sleep_MB(unsigned int seconds);
int usleep_A53(unsigned long useconds);
unsigned sleep_A53(unsigned int seconds);
int usleep_A9(unsigned long useconds);
unsigned sleep_A9(unsigned int seconds);
#ifdef __cplusplus
}
#endif
#endif

15
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#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H
/*
* SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
*/
#define CR_M (1 << 0) /* MMU enable */
#define CR_A (1 << 1) /* Alignment abort enable */
#define CR_C (1 << 2) /* Dcache enable */
#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
#define CR_I (1 << 12) /* Icache enable */
#define CR_WXN (1 << 19) /* Write Permision Imply XN */
#define CR_EE (1 << 25) /* Exception (Big) Endian */
#endif

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/******************************************************************************
*
* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file vectors.h
*
* This file contains the C level vector prototypes for the ARM Cortex A9 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _VECTORS_H_
#define _VECTORS_H_
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Function Prototypes ******************************/
void FIQInterrupt(void);
void IRQInterrupt(void);
#if !defined (__aarch64__)
void SWInterrupt(void);
void DataAbortInterrupt(void);
void PrefetchAbortInterrupt(void);
void UndefinedException(void);
#else
void SynchronousInterrupt(void);
void SErrorInterrupt(void);
#endif
#ifdef __cplusplus
}
#endif
#endif /* protection macro */

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/*******************************************************************************
*
* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xavbuf.h
*
* This file implements all the functions related to the Video Pipeline of the
* DisplayPort Subsystem.
*
* Features supported by this driver
* - Live Video and Graphics input.
* - Non-Live Video Graphics input.
* - Output Formats Supported - RGB, YUV444, YUV4222.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 aad 06/24/17 Initial release.
* 2.0 aad 10/07/17 Added Enums for Video and Audio sources.
* </pre>
*
*******************************************************************************/
#ifndef XAVBUF_H_
/* Prevent circular inclusions by using protection macros. */
#define XAVBUF_H_
/******************************* Include Files ********************************/
#include "xavbuf_hw.h"
#include "sleep.h"
/****************************** Type Definitions ******************************/
/**
* This typedef describes all the Video Formats supported by the driver
*/
typedef enum {
//Non-Live Video Formats
CbY0CrY1,
CrY0CbY1,
Y0CrY1Cb,
Y0CbY1Cr,
YV16,
YV24,
YV16Ci,
MONOCHROME,
YV16Ci2,
YUV444,
RGB888,
RGBA8880,
RGB888_10BPC,
YUV444_10BPC,
YV16Ci2_10BPC,
YV16Ci_10BPC,
YV16_10BPC,
YV24_10BPC,
MONOCHROME_10BPC,
YV16_420,
YV16Ci_420,
YV16Ci2_420,
YV16_420_10BPC,
YV16Ci_420_10BPC,
YV16Ci2_420_10BPC,
// Non-Live Graphics formats
RGBA8888,
ABGR8888,
RGB888_GFX,
BGR888,
RGBA5551,
RGBA4444,
RGB565,
BPP8,
BPP4,
BPP2,
BPP1,
YUV422,
YOnly,
//Live Input/Output Video/Graphics Formats
RGB_6BPC,
RGB_8BPC,
RGB_10BPC,
RGB_12BPC,
YCbCr444_6BPC,
YCbCr444_8BPC,
YCbCr444_10BPC,
YCbCr444_12BPC,
YCbCr422_8BPC,
YCbCr422_10BPC,
YCbCr422_12BPC,
YOnly_8BPC,
YOnly_10BPC,
YOnly_12BPC,
} XAVBuf_VideoFormat;
/**
* This data structure describes video planes.
*/
typedef enum {
Interleaved,
SemiPlanar,
Planar
} XAVBuf_VideoModes;
/**
* This typedef describes the video source list
*/
typedef enum {
XAVBUF_VIDSTREAM1_LIVE,
XAVBUF_VIDSTREAM1_NONLIVE,
XAVBUF_VIDSTREAM1_TPG,
XAVBUF_VIDSTREAM1_NONE,
} XAVBuf_VideoStream;
/**
* This typedef describes the graphics source list
*/
typedef enum {
XAVBUF_VIDSTREAM2_DISABLEGFX = 0x0,
XAVBUF_VIDSTREAM2_NONLIVE_GFX = 0x4,
XAVBUF_VIDSTREAM2_LIVE_GFX = 0x8,
XAVBUF_VIDSTREAM2_NONE = 0xC0,
} XAVBuf_GfxStream;
/**
* This typedef describes the audio stream 1 source list
*/
typedef enum {
XAVBUF_AUDSTREAM1_LIVE = 0x00,
XAVBUF_AUDSTREAM1_NONLIVE = 0x10,
XAVBUF_AUDSTREAM1_TPG = 0x20,
XAVBUF_AUDSTREAM1_NO_AUDIO = 0x30,
} XAVBuf_AudioStream1;
/**
* This typedef describes the audio stream 2 source list
*/
typedef enum {
XAVBUF_AUDSTREAM2_NO_AUDIO = 0X00,
XAVBUF_AUDSTREAM2_AUDIOGFX = 0X40,
} XAVBuf_AudioStream2;
/**
* This typedef describes the attributes associated with the video formats.
*/
typedef struct {
XAVBuf_VideoFormat VideoFormat;
u8 Value;
XAVBuf_VideoModes Mode;
u32 SF[3];
u8 SamplingEn;
u8 IsRGB;
u8 Swap;
u8 BPP;
} XAVBuf_VideoAttribute;
/**
* This typedef stores the attributes of an audio stream
*/
typedef struct {
u32 Volume;
u8 SwapLR;
} XAVBuf_AudioAttribute;
/**
* This typedef stores the data associated with the Audio Video input modes.
*/
typedef struct {
XAVBuf_VideoAttribute *NonLiveVideo, *NonLiveGraphics;
XAVBuf_VideoAttribute *LiveVideo, *LiveGraphics;
XAVBuf_AudioAttribute *Audio, *GraphicsAudio;
XAVBuf_VideoStream VideoSrc;
XAVBuf_GfxStream GraphicsSrc;
XAVBuf_AudioStream1 AudioSrc1;
XAVBuf_AudioStream2 AudioSrc2;
u8 AudioClk, VideoClk;
} XAVBuf_AVModes;
/**
* This structure stores the background color information.
*/
typedef struct {
u16 RCr;
u16 GY;
u16 BCb;
} XAVBuf_BlenderBgClr;
/**
* This typedef stores the AVBuf Configuration information.
*/
typedef struct {
u16 DeviceId;
u32 BaseAddr;
} XAVBuf_Config;
/**
* This typedef stores all the attributes associated to the Blender block of the
* DisplayPort Subsystem
*/
typedef struct {
u8 GlobalAlphaEn;
u8 Alpha;
XAVBuf_VideoAttribute *OutputVideo;
} XAVBuf_Blender;
/**
* The XAVBuf driver instance data. The user is required to allocate a variable
* of this type for every XAVBUF instance in the system. A pointer to this type
* is then passed to the driver API functions
*/
typedef struct {
XAVBuf_Config Config;
XAVBuf_AVModes AVMode;
XAVBuf_Blender Blender;
} XAVBuf;
/**************************** Function Prototypes *****************************/
/* xavbuf.c: Setup and initialization functions. */
void XAVBuf_CfgInitialize(XAVBuf *InstancePtr, u32 BaseAddr, u16 DeviceId);
/* xavbuf.c: Functions to setup the Input Video and Audio sources */
void XAVBuf_InputVideoSelect(XAVBuf *InstancePtr, XAVBuf_VideoStream VidStream,
XAVBuf_GfxStream GfxStream);
void XAVBuf_InputAudioSelect(XAVBuf *InstancePtr, XAVBuf_AudioStream1 AudStream,
XAVBuf_AudioStream2 AudioStream2);
/* xavbuf.c: Functions to setup the Video Format attributes */
int XAVBuf_SetInputNonLiveVideoFormat(XAVBuf *InstancePtr,
XAVBuf_VideoFormat Format);
int XAVBuf_SetInputNonLiveGraphicsFormat(XAVBuf *InstancePtr,
XAVBuf_VideoFormat Format);
int XAVBuf_SetInputLiveVideoFormat(XAVBuf *InstancePtr,
XAVBuf_VideoFormat Format);
int XAVBuf_SetInputLiveGraphicsFormat(XAVBuf *InstancePtr,
XAVBuf_VideoFormat Format);
int XAVBuf_SetOutputVideoFormat(XAVBuf *InstancePtr, XAVBuf_VideoFormat Format);
XAVBuf_VideoAttribute *XAVBuf_GetLiveVideoAttribute(XAVBuf_VideoFormat Format);
XAVBuf_VideoAttribute *XAVBuf_GetNLiveVideoAttribute(XAVBuf_VideoFormat Format);
XAVBuf_VideoAttribute *XAVBuf_GetNLGraphicsAttribute(XAVBuf_VideoFormat Format);
/* xavbuf.c: Functions to setup the clock sources for video and audio */
void XAVBuf_SetAudioVideoClkSrc(XAVBuf *InstancePtr, u8 VideoClk, u8 AudioClk);
/* xavbuf.c: Functions that setup Video and Graphics pipeline depending on the
* sources and format selected.
*/
void XAVBuf_ConfigureVideoPipeline(XAVBuf *InstancePtr);
void XAVBuf_ConfigureGraphicsPipeline(XAVBuf *InstancePtr);
/* Functions to setup Blender Properties */
void XAVBuf_BlendSetBgColor(XAVBuf *InstancePtr, XAVBuf_BlenderBgClr *Color);
void XAVBuf_SetBlenderAlpha(XAVBuf *InstancePtr, u8 Alpha, u8 Enable);
void XAVBuf_SoftReset(XAVBuf *InstancePtr);
void XABuf_LineResetDisable(XAVBuf *InstancePtr, u8 Disable);
void XAVBuf_ConfigureOutputVideo(XAVBuf *InstancePtr);
/* Audio Configuration functions */
void XAVBuf_AudioSoftReset(XAVBuf *InstancePtr);
void XAVBuf_AudioMixerVolumeControl(XAVBuf *InstancePtr, u8 Channel0Volume,
u8 Channel1Volume);
/* DPDMA Interface functions */
void XAVBuf_EnableGraphicsBuffers(XAVBuf *InstancePtr, u8 Enable);
void XAVBuf_EnableVideoBuffers(XAVBuf *InstancePtr, u8 Enable);
void XAVBuf_EnableAudio0Buffers(XAVBuf *InstancePtr, u8 Enable);
void XAVBuf_EnableAudio1Buffers(XAVBuf *InstancePtr, u8 Enable);
#endif //XAVBUF_H_

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************/
/**
*
* @file xavbuf_clk.h
*
* This header file contains the identifiers and low-level driver functions (or
* macros) that can be used to configure PLL to generate required frequency.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 mh 06/24/17 Initial release.
* 2.1 tu 12/29/17 LPD and FPD offsets adjusted
* </pre>
*
*******************************************************************************/
#ifndef XAVBUF_CLK_H_
#define XAVBUF_CLK_H_
/******************************* Include Files ********************************/
#include "xavbuf_hw.h"
#include "xstatus.h"
#include "sleep.h"
/****************************** Type Definitions ******************************/
/**
* This enum enumerates various PLL
*/
enum PLL{
APLL = 0,
DPLL = 1,
VPLL = 2,
IOPLL = 3,
RPLL = 4
};
/**
* This typedef enumerates various variables used to configure Pll
*/
typedef struct {
u64 BaseAddress;
u64 Fractional;
u64 RefClkFreqhz;
u32 Divider;
u8 Offset;
u8 ClkDividBy2;
u8 ExtDivider0;
u8 ExtDivider1;
u8 ExtDividerCnt;
u8 DomainSwitchDiv;
u8 FracIntegerFBDIV;
u8 IntegerFBDIV;
u8 InputRefClk;
u8 Fpd;
u8 Pll;
}XAVBuf_Pll;
/**************************** Function Prototypes *****************************/
int XAVBuf_SetPixelClock(u64 FreqHz);
int XAVBuf_SetAudioClock(u64 FreqHz);
#endif /* XAVBUF_CLK_H_ */

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/******************************************************************************
*
* Copyright (C) 2007 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xaxipmon.h
* @addtogroup axipmon_v6_6
* @{
* @details
*
* The XAxiPmon driver supports the Xilinx AXI Performance Monitor device.
*
* The AXI Performance Monitor device provides following features:
*
* Configurable number of Metric Counters and Incrementers
* Computes performance metrics for Agents connected to
* monitor slots (Up to 8 slots)
*
* The following Metrics can be computed:
*
* Metrics computed for an AXI4 MM agent:
* Write Request Count: Total number of write requests by/to the agent.
* Read Request Count: Total number of read requests given by/to the
* agent.
* Read Latency: It is defined as the time from the start of read address
* transaction to the beginning of the read data service.
* Write Latency: It is defined as the period needed a master completes
* write data transaction, i.e. from write address
* transaction to write response from slave.
* Write Byte Count: Total number of bytes written by/to the agent.
* This metric is helpful when calculating the
* throughput of the system.
* Read Byte Count: Total number of bytes read from/by the agent.
* Average Write Latency: Average write latency seen by the agent.
* It can be derived from total write latency
* and the write request count.
* Average Read Latency: Average read latency seen by the agent. It can be
* derived from total read latency and the read
* request count.
* Master Write Idle Cycle Count: Number of idle cycles caused by the
* masters during write transactions to
* the slave.
* Slave Write Idle Cycle Count: Number of idle cycles caused by this slave
* during write transactions to the slave.
* Master Read Idle Cycle Count: Number of idle cycles caused by the
* master during read transactions to the
* slave.
* Slave Read Idle Cycle Count: Number of idle cycles caused by this slave
* during read transactions to the slave.
*
* Metrics computed for an AXI4-Stream agent:
*
* Transfer Cycle Count: Total number of writes by/to the agent.
* Data Byte Count: Total number of data bytes written by/to the agent.
* This metric helps in calculating the throughput
* of the system.
* Position Byte Count: Total number of position bytes transferred.
* Null Byte Count: Total number of null bytes transferred.
* Packet Count: Total number of packets transferred.
*
* There are three modes : Advanced, Profile and Trace.
* - Advanced mode has 10 Mertic Counters, Sampled Metric Counters, Incrementors
* and Sampled Incrementors.
* - Profile mode has only 47 Metric Counters and Sampled Metric Counters.
* - Trace mode has no Counters.
* User should refer to the hardware device specification for detailed
* information about the device.
*
* This header file contains the prototypes of driver functions that can
* be used to access the AXI Performance Monitor device.
*
*
* <b> Initialization and Configuration </b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the AXI Performance Monitor device.
*
* XAxiPmon_CfgInitialize() API is used to initialize the AXI Performance Monitor
* device. The user needs to first call the XAxiPmon_LookupConfig() API which
* returns the Configuration structure pointer which is passed as a parameter to
* the XAxiPmon_CfgInitialize() API.
*
*
* <b>Interrupts</b>
*
* The AXI Performance Monitor does not support Interrupts
*
*
* <b> Virtual Memory </b>
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
*
* <b> Threads </b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b> Asserts </b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
*
* <b> Building the driver </b>
*
* The XAxiPmon driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* <b> Limitations of the driver </b>
*
*
* <br><br>
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 02/27/12 First release
* 2.00a bss 06/23/12 Updated to support v2_00a version of IP.
* 3.00a bss 09/03/12 To support v2_01_a version of IP:
* Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
* added XAPM_FLAG_EVENT, XAPM_FLAG_EVNTSTAR,
* XAPM_FLAG_EVNTSTOP.
* Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
* modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
* in xaxipmon.c
* Deleted XAPM_AGENT_OFFSET Macro in xaxipmon_hw.h
* 3.01a bss 10/25/12 To support new version of IP:
* Added XAPM_MCXLOGEN_OFFSET macros in xaxipmon_hw.h.
* Added XAxiPmon_SetMetricCounterCutOff,
* XAxiPmon_GetMetricCounterCutOff,
* XAxiPmon_EnableExternalTrigger and
* XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
* Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
* (CR #683746) in xaxipmon.c
* Added XAxiPmon_EnableEventLog,
* XAxiPmon_DisableMetricsCounter,
* XAxiPmon_EnableMetricsCounter APIs in xaxipmon.c to
* replace macros in this file.
* Added XAPM_FLAG_XXX macros.
* Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
* APIs (CR #683799).
* Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
* APIs (CR #683801).
* Added XAxiPmon_GetMetricName API (CR #683803).
* Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent
* declarations (CR #677337)
* 4.00a bss 01/17/13 To support new version of IP:
* Added XAPM_METRIC_SET_12 to XAPM_METRIC_SET_15 macros.
* Added XAxiPmon_SetLogEnableRanges,
* XAxiPmon_GetLogEnableRanges,
* XAxiPmon_EnableMetricCounterTrigger,
* XAxiPmon_DisableMetricCounterTrigger,
* XAxiPmon_EnableEventLogTrigger,
* XAxiPmon_DisableEventLogTrigger,
* XAxiPmon_SetWriteLatencyId,
* XAxiPmon_SetReadLatencyId,
* XAxiPmon_GetWriteLatencyId,
* XAxiPmon_GetReadLatencyId APIs and removed
* XAxiPmon_SetMetricCounterCutOff,
* XAxiPmon_GetMetricCounterCutOff,
* XAxiPmon_EnableExternalTrigger and
* XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
* Added XAPM_LATENCYID_OFFSET,
* XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
* XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK in
* xaxipmon_hw.h
* 5.00a bss 08/26/13 To support new version of IP:
* XAxiPmon_SampleMetrics Macro.
* Modified XAxiPmon_CfgInitialize, Assert functions
* Added XAxiPmon_GetMetricCounter,
* XAxiPmon_SetSampleInterval, XAxiPmon_GetSampleInterval,
* XAxiPmon_SetWrLatencyStart, XAxiPmon_SetWrLatencyEnd,
* XAxiPmon_SetRdLatencyStart, XAxiPmon_SetRdLatencyEnd,
* XAxiPmon_GetWrLatencyStart, XAxiPmon_GetWrLatencyEnd,
* XAxiPmon_GetRdLatencyStart, XAxiPmon_GetRdLatencyEnd,
* XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
* XAxiPmon_GetWriteIdMask and XAxiPmon_GetReadIdMask APIs
* Renamed :
* XAxiPmon_SetWriteLatencyId to
* XAxiPmon_SetWriteId, XAxiPmon_SetReadLatencyId to
* XAxiPmon_SetReadId, XAxiPmon_GetWriteLatencyId to
* XAxiPmon_GetWriteId and XAxiPmon_SetReadLatencyId to
* XAxiPmon_GetReadId. in xaxipmon.c
* Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
* XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET,
* XAPM_IDMASK_OFFSET, XAPM_CR_IDFILTER_ENABLE_MASK,
* XAPM_CR_WRLATENCY_START_MASK,
* XAPM_CR_WRLATENCY_END_MASK,
* XAPM_CR_RDLATENCY_START_MASK,
* XAPM_CR_RDLATENCY_END_MASK and
* XAPM_MAX_COUNTERS_PROFILE.
* Renamed:
* XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
* XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
* XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
* in xaxipmon_hw.h.
* Modified driver tcl to generate new parameters
* ScaleFactor, ModeProfile, ModeTrace and ModeAdvanced
* in Config structure.
* 6.0 adk 19/12/13 Updated as per the New Tcl API's
* 6.1 adk 16/04/14 Updated the driver tcl for the newly added parameters in
* The Axi pmon IP.
* 6.2 bss 04/21/14 Updated XAxiPmon_CfgInitialize in xaxipmon.c to Reset
* counters and FIFOs based on Modes(CR#782671). And if
* both profile and trace modes are present set mode as
* Advanced.
* 6.2 bss 03/02/15 To support Zynq MP APM:
* Added Is32BitFiltering in XAxiPmon_Config structure.
* Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
* XAxiPmon_GetWriteId, XAxiPmon_GetReadId
* XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask
* XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
* functions in xaxipmon.c.
* Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET in
* xaxipmon_hw.h
*
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* 6.4 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototype of XAxiPmon_CfgInitialize API.
* 6.5 ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 6.6 ms 04/18/17 Modified tcl file to add suffix U for all macro
* definitions of axipmon in xparameters.h
* </pre>
*
*****************************************************************************/
#ifndef XAXIPMON_H /* Prevent circular inclusions */
#define XAXIPMON_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xaxipmon_hw.h"
/************************** Constant Definitions ****************************/
/**
* @name Macro for Maximum number of Counters
*
* @{
*/
#define XAPM_MAX_COUNTERS 10U /**< Maximum number of Counters */
#define XAPM_MAX_COUNTERS_PROFILE 48U /**< Maximum number of Counters */
/*@}*/
/**
* @name Indices for Metric Counters and Sampled Metric Coounters used with
* XAxiPmon_GetMetricCounter and XAxiPmon_GetSampledMetricCounter APIs
* @{
*/
#define XAPM_METRIC_COUNTER_0 0U /**< Metric Counter 0 Register Index */
#define XAPM_METRIC_COUNTER_1 1U /**< Metric Counter 1 Register Index */
#define XAPM_METRIC_COUNTER_2 2U /**< Metric Counter 2 Register Index */
#define XAPM_METRIC_COUNTER_3 3U /**< Metric Counter 3 Register Index */
#define XAPM_METRIC_COUNTER_4 4U /**< Metric Counter 4 Register Index */
#define XAPM_METRIC_COUNTER_5 5U /**< Metric Counter 5 Register Index */
#define XAPM_METRIC_COUNTER_6 6U /**< Metric Counter 6 Register Index */
#define XAPM_METRIC_COUNTER_7 7U /**< Metric Counter 7 Register Index */
#define XAPM_METRIC_COUNTER_8 8U /**< Metric Counter 8 Register Index */
#define XAPM_METRIC_COUNTER_9 9U /**< Metric Counter 9 Register Index */
/*@}*/
/**
* @name Indices for Incrementers and Sampled Incrementers used with
* XAxiPmon_GetIncrementer and XAxiPmon_GetSampledIncrementer APIs
* @{
*/
#define XAPM_INCREMENTER_0 0U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_1 1U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_2 2U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_3 3U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_4 4U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_5 5U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_6 6U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_7 7U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_8 8U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_9 9U /**< Metric Counter 0 Register Index */
/*@}*/
/**
* @name Macros for Metric Selector Settings
* @{
*/
#define XAPM_METRIC_SET_0 0U /**< Write Transaction Count */
#define XAPM_METRIC_SET_1 1U /**< Read Transaction Count */
#define XAPM_METRIC_SET_2 2U /**< Write Byte Count */
#define XAPM_METRIC_SET_3 3U /**< Read Byte Count */
#define XAPM_METRIC_SET_4 4U /**< Write Beat Count */
#define XAPM_METRIC_SET_5 5U /**< Total Read Latency */
#define XAPM_METRIC_SET_6 6U /**< Total Write Latency */
#define XAPM_METRIC_SET_7 7U /**< Slv_Wr_Idle_Cnt */
#define XAPM_METRIC_SET_8 8U /**< Mst_Rd_Idle_Cnt */
#define XAPM_METRIC_SET_9 9U /**< Num_BValids */
#define XAPM_METRIC_SET_10 10U /**< Num_WLasts */
#define XAPM_METRIC_SET_11 11U /**< Num_RLasts */
#define XAPM_METRIC_SET_12 12U /**< Minimum Write Latency */
#define XAPM_METRIC_SET_13 13U /**< Maximum Write Latency */
#define XAPM_METRIC_SET_14 14U /**< Minimum Read Latency */
#define XAPM_METRIC_SET_15 15U /**< Maximum Read Latency */
#define XAPM_METRIC_SET_16 16U /**< Transfer Cycle Count */
#define XAPM_METRIC_SET_17 17U /**< Packet Count */
#define XAPM_METRIC_SET_18 18U /**< Data Byte Count */
#define XAPM_METRIC_SET_19 19U /**< Position Byte Count */
#define XAPM_METRIC_SET_20 20U /**< Null Byte Count */
#define XAPM_METRIC_SET_21 21U /**< Slv_Idle_Cnt */
#define XAPM_METRIC_SET_22 22U /**< Mst_Idle_Cnt */
#define XAPM_METRIC_SET_30 30U /**< External event count */
/*@}*/
/**
* @name Macros for Maximum number of Agents
* @{
*/
#define XAPM_MAX_AGENTS 8U /**< Maximum number of Agents */
/*@}*/
/**
* @name Macros for Flags in Flag Enable Control Register
* @{
*/
#define XAPM_FLAG_WRADDR 0x00000001 /**< Write Address Flag */
#define XAPM_FLAG_FIRSTWR 0x00000002 /**< First Write Flag */
#define XAPM_FLAG_LASTWR 0x00000004 /**< Last Write Flag */
#define XAPM_FLAG_RESPONSE 0x00000008 /**< Response Flag */
#define XAPM_FLAG_RDADDR 0x00000010 /**< Read Address Flag */
#define XAPM_FLAG_FIRSTRD 0x00000020 /**< First Read Flag */
#define XAPM_FLAG_LASTRD 0x00000040 /**< Last Read Flag */
#define XAPM_FLAG_SWDATA 0x00010000 /**< Software-written Data Flag */
#define XAPM_FLAG_EVENT 0x00020000 /**< Last Read Flag */
#define XAPM_FLAG_EVNTSTOP 0x00040000 /**< Last Read Flag */
#define XAPM_FLAG_EVNTSTART 0x00080000 /**< Last Read Flag */
#define XAPM_FLAG_GCCOVF 0x00100000 /**< Global Clock Counter Overflow
* Flag */
#define XAPM_FLAG_SCLAPSE 0x00200000 /**< Sample Counter Lapse Flag */
#define XAPM_FLAG_MC0 0x00400000U /**< Metric Counter 0 Flag */
#define XAPM_FLAG_MC1 0x00800000U /**< Metric Counter 1 Flag */
#define XAPM_FLAG_MC2 0x01000000U /**< Metric Counter 2 Flag */
#define XAPM_FLAG_MC3 0x02000000U /**< Metric Counter 3 Flag */
#define XAPM_FLAG_MC4 0x04000000U /**< Metric Counter 4 Flag */
#define XAPM_FLAG_MC5 0x08000000U /**< Metric Counter 5 Flag */
#define XAPM_FLAG_MC6 0x10000000U /**< Metric Counter 6 Flag */
#define XAPM_FLAG_MC7 0x20000000U /**< Metric Counter 7 Flag */
#define XAPM_FLAG_MC8 0x40000000U /**< Metric Counter 8 Flag */
#define XAPM_FLAG_MC9 0x80000000U /**< Metric Counter 9 Flag */
/*@}*/
/**
* @name Macros for Read/Write Latency Start and End points
* @{
*/
#define XAPM_LATENCY_ADDR_ISSUE 0U /**< Address Issue as start
point for Latency calculation*/
#define XAPM_LATENCY_ADDR_ACCEPT 1U /**< Address Acceptance as start
point for Latency calculation*/
#define XAPM_LATENCY_LASTRD 0U /**< Last Read as end point for
Latency calculation */
#define XAPM_LATENCY_LASTWR 0U /**< Last Write as end point for
Latency calculation */
#define XAPM_LATENCY_FIRSTRD 1U /**< First Read as end point for
Latency calculation */
#define XAPM_LATENCY_FIRSTWR 1U /**< First Write as end point for
Latency calculation */
/*@}*/
/**
* @name Macros for Modes of APM
* @{
*/
#define XAPM_MODE_TRACE 2U /**< APM in Trace mode */
#define XAPM_MODE_PROFILE 1U /**< APM in Profile mode */
#define XAPM_MODE_ADVANCED 0U /**< APM in Advanced mode */
/*@}*/
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for the AXI Performance
* Monitor device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
UINTPTR BaseAddress; /**< Device base address */
s32 GlobalClkCounterWidth; /**< Global Clock Counter Width */
s32 MetricSampleCounterWidth ; /**< Metric Sample Counters Width */
u8 IsEventCount; /**< Event Count Enabled 1 - enabled
0 - not enabled */
u8 NumberofSlots; /**< Number of Monitor Slots */
u8 NumberofCounters; /**< Number of Counters */
u8 HaveSampledCounters; /**< Have Sampled Counters 1 - present
0 - Not present */
u8 IsEventLog; /**< Event Logging Enabled 1 - enabled
0 - Not enabled */
u32 FifoDepth; /**< Event Log FIFO Depth */
u32 FifoWidth; /**< Event Log FIFO Width */
u32 TidWidth; /**< Streaming Interface TID Width */
u8 ScaleFactor; /**< Event Count Scaling factor */
u8 ModeAdvanced; /**< Advanced Mode */
u8 ModeProfile; /**< Profile Mode */
u8 ModeTrace; /**< Trace Mode */
u8 Is32BitFiltering; /**< 32 bit filtering enabled */
} XAxiPmon_Config;
/**
* The driver's instance data. The user is required to allocate a variable
* of this type for every AXI Performance Monitor device in system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XAxiPmon_Config Config; /**< XAxiPmon_Config of current device */
u32 IsReady; /**< Device is initialized and ready */
u8 Mode; /**< APM Mode */
} XAxiPmon;
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
*
* This routine enables the Global Interrupt.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrGlobalEnable(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_IntrGlobalEnable(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \
XAPM_GIE_OFFSET, 1)
/****************************************************************************/
/**
*
* This routine disables the Global Interrupt.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrGlobalDisable(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_IntrGlobalDisable(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \
XAPM_GIE_OFFSET, 0)
/****************************************************************************/
/**
*
* This routine enables interrupt(s). Use the XAPM_IXR_* constants defined in
* xaxipmon_hw.h to create the bit-mask to enable interrupts.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Mask is the mask to enable. Bit positions of 1 will be enabled.
* Bit positions of 0 will keep the previous setting. This mask is
* formed by OR'ing XAPM_IXR__* bits defined in xaxipmon_hw.h.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XAxiPmon_IntrEnable(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IE_OFFSET) | (Mask));
/****************************************************************************/
/**
*
* This routine disable interrupt(s). Use the XAPM_IXR_* constants defined in
* xaxipmon_hw.h to create the bit-mask to disable interrupts.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Mask is the mask to disable. Bit positions of 1 will be
* disabled. Bit positions of 0 will keep the previous setting.
* This mask is formed by OR'ing XAPM_IXR_* bits defined in
* xaxipmon_hw.h.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XAxiPmon_IntrDisable(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IE_OFFSET) | (Mask));
/****************************************************************************/
/**
*
* This routine clears the specified interrupt(s).
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Mask is the mask to clear. Bit positions of 1 will be cleared.
* This mask is formed by OR'ing XAPM_IXR_* bits defined in
* xaxipmon_hw.h.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XAxiPmon_IntrClear(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IS_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IS_OFFSET) | (Mask));
/****************************************************************************/
/**
*
* This routine returns the Interrupt Status Register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return Interrupt Status Register contents
*
* @note C-Style signature:
* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_IntrGetStatus(InstancePtr) \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IS_OFFSET);
/****************************************************************************/
/**
*
* This function enables the Global Clock Counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableGlobalClkCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableGlobalClkCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) | XAPM_CR_GCC_ENABLE_MASK);
/****************************************************************************/
/**
*
* This function disbles the Global Clock Counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableGlobalClkCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableGlobalClkCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) & ~(XAPM_CR_GCC_ENABLE_MASK));
/****************************************************************************/
/**
*
* This function enables the specified flag in Flag Control Register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableFlag(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableFlag(InstancePtr, Flag) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_FEC_OFFSET) | (Flag));
/****************************************************************************/
/**
*
* This function disables the specified flag in Flag Control Register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableFlag(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableFlag(InstancePtr, Flag) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_FEC_OFFSET) & ~(Flag));
/****************************************************************************/
/**
*
* This function loads the sample interval register value into the sample
* interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_LoadSampleIntervalCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_LoadSampleIntervalCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
XAPM_SICR_LOAD_MASK);
/****************************************************************************/
/**
*
* This enables the down count of the sample interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableSampleIntervalCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableSampleIntervalCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\
XAPM_SICR_ENABLE_MASK);
/****************************************************************************/
/**
*
* This disables the down count of the sample interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableSampleIntervalCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableSampleIntervalCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_SICR_OFFSET) & ~(XAPM_SICR_ENABLE_MASK));
/****************************************************************************/
/**
*
* This enables Reset of Metric Counters when Sample Interval Counter lapses.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableMetricCounterReset(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableMetricCounterReset(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\
XAPM_SICR_MCNTR_RST_MASK);
/****************************************************************************/
/**
*
* This disables the down count of the sample interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableMetricCounterReset(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableMetricCounterReset(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_SICR_OFFSET) & ~(XAPM_SICR_MCNTR_RST_MASK));
/****************************************************************************/
/**
*
* This function enables the ID Filter Masking.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableIDFilter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableIDFilter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) | XAPM_CR_IDFILTER_ENABLE_MASK);
/****************************************************************************/
/**
*
* This function disbles the ID Filter masking.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableIDFilter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableIDFilter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) & ~(XAPM_CR_IDFILTER_ENABLE_MASK));
/****************************************************************************/
/**
*
* This function samples Metric Counters to Sampled Metric Counters by
* reading Sample Register and also returns interval. i.e. the number of
* clocks in between previous read to the current read of sample register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return Interval. i.e. the number of clocks in between previous
* read to the current read of sample register.
*
* @note C-Style signature:
* u32 XAxiPmon_SampleMetrics(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_SampleMetrics(InstancePtr) \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, XAPM_SR_OFFSET);
/************************** Function Prototypes *****************************/
/**
* Functions in xaxipmon_sinit.c
*/
XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId);
/**
* Functions in xaxipmon.c
*/
s32 XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr,
XAxiPmon_Config *ConfigPtr, UINTPTR EffectiveAddr);
s32 XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr);
void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr);
s32 XAxiPmon_ResetFifo(XAxiPmon *InstancePtr);
void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
u16 RangeUpper, u16 RangeLower);
void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
u16 *RangeUpper, u16 *RangeLower);
void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval);
void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval);
s32 XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
u8 CounterNum);
s32 XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
u8 *Slot);
void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue,
u32 *CntLowValue);
u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum);
u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum);
u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum);
u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum);
void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData);
u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr);
s32 XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables);
s32 XAxiPmon_StopEventLog(XAxiPmon *InstancePtr);
s32 XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval);
s32 XAxiPmon_StopCounters(XAxiPmon *InstancePtr);
void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr);
void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr);
void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
u16 RangeUpper, u16 RangeLower);
void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
u16 *RangeUpper, u16 *RangeLower);
void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr);
void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr);
void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr);
void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr);
void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr);
const char * XAxiPmon_GetMetricName(u8 Metrics);
void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId);
void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId);
u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr);
u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr);
void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param);
void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param);
void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param);
void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param);
u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr);
u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr);
u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr);
u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr);
void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask);
void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask);
u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr);
u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr);
/**
* Functions in xaxipmon_selftest.c
*/
s32 XAxiPmon_SelfTest(XAxiPmon *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xaxipmon_hw.h
* @addtogroup axipmon_v6_6
* @{
*
* This header file contains identifiers and basic driver functions (or
* macros) that can be used to access the AXI Performance Monitor.
*
* Refer to the device specification for more information about this driver.
*
* @note None.
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 02/27/12 First release
* 2.00a bss 06/23/12 Updated to support v2_00a version of IP.
* 3.00a bss 09/03/12 Deleted XAPM_AGENT_OFFSET Macro to support
* v2_01a version of IP.
* 3.01a bss 10/25/12 To support new version of IP:
* Added XAPM_MCXLOGEN_OFFSET and
* XAPM_CR_EXTERNAL_TRIGGER_MASK macros.
* 4.00a bss 01/17/13 To support new version of IP:
* Added XAPM_LATENCYID_OFFSET,
* XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
* XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK
* 5.00a bss 08/26/13 To support new version of IP:
* Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
* XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET.
* Added macro XAPM_IDMASK_OFFSET, XAPM_SR_OFFSET.
* Added XAPM_CR_IDFILTER_ENABLE_MASK,
* XAPM_CR_WRLATENCY_START_MASK,
* XAPM_CR_WRLATENCY_END_MASK,
* XAPM_CR_RDLATENCY_START_MASK,
* XAPM_CR_RDLATENCY_END_MASK, XAPM_MASKID_RID_MASK
* and XAPM_MASKID_WID_MASK macros.
* Renamed:
* XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
* XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
* XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
*
* 6.2 bss 03/02/15 Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET to support
* Zynq MP APM.
*
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* </pre>
*
*****************************************************************************/
#ifndef XAXIPMON_HW_H /* Prevent circular inclusions */
#define XAXIPMON_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions ****************************/
/**@name Register offsets of AXIMONITOR in the Device Config
*
* The following constants provide access to each of the registers of the
* AXI PERFORMANCE MONITOR device.
* @{
*/
#define XAPM_GCC_HIGH_OFFSET 0x00000000U /**< Global Clock Counter
32 to 63 bits */
#define XAPM_GCC_LOW_OFFSET 0x00000004U /**< Global Clock Counter Lower
0-31 bits */
#define XAPM_SI_HIGH_OFFSET 0x00000020U /**< Sample Interval MSB */
#define XAPM_SI_LOW_OFFSET 0x00000024U /**< Sample Interval LSB */
#define XAPM_SICR_OFFSET 0x00000028U /**< Sample Interval Control
Register */
#define XAPM_SR_OFFSET 0x0000002CU /**< Sample Register */
#define XAPM_GIE_OFFSET 0x00000030U /**< Global Interrupt Enable
Register */
#define XAPM_IE_OFFSET 0x00000034U /**< Interrupt Enable Register */
#define XAPM_IS_OFFSET 0x00000038U /**< Interrupt Status Register */
#define XAPM_MSR0_OFFSET 0x00000044U /**< Metric Selector 0 Register */
#define XAPM_MSR1_OFFSET 0x00000048U /**< Metric Selector 1 Register */
#define XAPM_MSR2_OFFSET 0x0000004CU /**< Metric Selector 2 Register */
#define XAPM_MC0_OFFSET 0x00000100U /**< Metric Counter 0 Register */
#define XAPM_INC0_OFFSET 0x00000104U /**< Incrementer 0 Register */
#define XAPM_RANGE0_OFFSET 0x00000108U /**< Range 0 Register */
#define XAPM_MC0LOGEN_OFFSET 0x0000010CU /**< Metric Counter 0
Log Enable Register */
#define XAPM_MC1_OFFSET 0x00000110U /**< Metric Counter 1 Register */
#define XAPM_INC1_OFFSET 0x00000114U /**< Incrementer 1 Register */
#define XAPM_RANGE1_OFFSET 0x00000118U /**< Range 1 Register */
#define XAPM_MC1LOGEN_OFFSET 0x0000011CU /**< Metric Counter 1
Log Enable Register */
#define XAPM_MC2_OFFSET 0x00000120U /**< Metric Counter 2 Register */
#define XAPM_INC2_OFFSET 0x00000124U /**< Incrementer 2 Register */
#define XAPM_RANGE2_OFFSET 0x00000128U /**< Range 2 Register */
#define XAPM_MC2LOGEN_OFFSET 0x0000012CU /**< Metric Counter 2
Log Enable Register */
#define XAPM_MC3_OFFSET 0x00000130U /**< Metric Counter 3 Register */
#define XAPM_INC3_OFFSET 0x00000134U /**< Incrementer 3 Register */
#define XAPM_RANGE3_OFFSET 0x00000138U /**< Range 3 Register */
#define XAPM_MC3LOGEN_OFFSET 0x0000013CU /**< Metric Counter 3
Log Enable Register */
#define XAPM_MC4_OFFSET 0x00000140U /**< Metric Counter 4 Register */
#define XAPM_INC4_OFFSET 0x00000144U /**< Incrementer 4 Register */
#define XAPM_RANGE4_OFFSET 0x00000148U /**< Range 4 Register */
#define XAPM_MC4LOGEN_OFFSET 0x0000014CU /**< Metric Counter 4
Log Enable Register */
#define XAPM_MC5_OFFSET 0x00000150U /**< Metric Counter 5
Register */
#define XAPM_INC5_OFFSET 0x00000154U /**< Incrementer 5 Register */
#define XAPM_RANGE5_OFFSET 0x00000158U /**< Range 5 Register */
#define XAPM_MC5LOGEN_OFFSET 0x0000015CU /**< Metric Counter 5
Log Enable Register */
#define XAPM_MC6_OFFSET 0x00000160U /**< Metric Counter 6
Register */
#define XAPM_INC6_OFFSET 0x00000164U /**< Incrementer 6 Register */
#define XAPM_RANGE6_OFFSET 0x00000168U /**< Range 6 Register */
#define XAPM_MC6LOGEN_OFFSET 0x0000016CU /**< Metric Counter 6
Log Enable Register */
#define XAPM_MC7_OFFSET 0x00000170U /**< Metric Counter 7
Register */
#define XAPM_INC7_OFFSET 0x00000174U /**< Incrementer 7 Register */
#define XAPM_RANGE7_OFFSET 0x00000178U /**< Range 7 Register */
#define XAPM_MC7LOGEN_OFFSET 0x0000017CU /**< Metric Counter 7
Log Enable Register */
#define XAPM_MC8_OFFSET 0x00000180U /**< Metric Counter 8
Register */
#define XAPM_INC8_OFFSET 0x00000184U /**< Incrementer 8 Register */
#define XAPM_RANGE8_OFFSET 0x00000188U /**< Range 8 Register */
#define XAPM_MC8LOGEN_OFFSET 0x0000018CU /**< Metric Counter 8
Log Enable Register */
#define XAPM_MC9_OFFSET 0x00000190U /**< Metric Counter 9
Register */
#define XAPM_INC9_OFFSET 0x00000194U /**< Incrementer 9 Register */
#define XAPM_RANGE9_OFFSET 0x00000198U /**< Range 9 Register */
#define XAPM_MC9LOGEN_OFFSET 0x0000019CU /**< Metric Counter 9
Log Enable Register */
#define XAPM_SMC0_OFFSET 0x00000200U /**< Sampled Metric Counter
0 Register */
#define XAPM_SINC0_OFFSET 0x00000204U /**< Sampled Incrementer
0 Register */
#define XAPM_SMC1_OFFSET 0x00000210U /**< Sampled Metric Counter
1 Register */
#define XAPM_SINC1_OFFSET 0x00000214U /**< Sampled Incrementer
1 Register */
#define XAPM_SMC2_OFFSET 0x00000220U /**< Sampled Metric Counter
2 Register */
#define XAPM_SINC2_OFFSET 0x00000224U /**< Sampled Incrementer
2 Register */
#define XAPM_SMC3_OFFSET 0x00000230U /**< Sampled Metric Counter
3 Register */
#define XAPM_SINC3_OFFSET 0x00000234U /**< Sampled Incrementer
3 Register */
#define XAPM_SMC4_OFFSET 0x00000240U /**< Sampled Metric Counter
4 Register */
#define XAPM_SINC4_OFFSET 0x00000244U /**< Sampled Incrementer
4 Register */
#define XAPM_SMC5_OFFSET 0x00000250U /**< Sampled Metric Counter
5 Register */
#define XAPM_SINC5_OFFSET 0x00000254U /**< Sampled Incrementer
5 Register */
#define XAPM_SMC6_OFFSET 0x00000260U /**< Sampled Metric Counter
6 Register */
#define XAPM_SINC6_OFFSET 0x00000264U /**< Sampled Incrementer
6 Register */
#define XAPM_SMC7_OFFSET 0x00000270U /**< Sampled Metric Counter
7 Register */
#define XAPM_SINC7_OFFSET 0x00000274U /**< Sampled Incrementer
7 Register */
#define XAPM_SMC8_OFFSET 0x00000280U /**< Sampled Metric Counter
8 Register */
#define XAPM_SINC8_OFFSET 0x00000284U /**< Sampled Incrementer
8 Register */
#define XAPM_SMC9_OFFSET 0x00000290U /**< Sampled Metric Counter
9 Register */
#define XAPM_SINC9_OFFSET 0x00000294U /**< Sampled Incrementer
9 Register */
#define XAPM_MC10_OFFSET 0x000001A0U /**< Metric Counter 10
Register */
#define XAPM_MC11_OFFSET 0x000001B0U /**< Metric Counter 11
Register */
#define XAPM_MC12_OFFSET 0x00000500U /**< Metric Counter 12
Register */
#define XAPM_MC13_OFFSET 0x00000510U /**< Metric Counter 13
Register */
#define XAPM_MC14_OFFSET 0x00000520U /**< Metric Counter 14
Register */
#define XAPM_MC15_OFFSET 0x00000530U /**< Metric Counter 15
Register */
#define XAPM_MC16_OFFSET 0x00000540U /**< Metric Counter 16
Register */
#define XAPM_MC17_OFFSET 0x00000550U /**< Metric Counter 17
Register */
#define XAPM_MC18_OFFSET 0x00000560U /**< Metric Counter 18
Register */
#define XAPM_MC19_OFFSET 0x00000570U /**< Metric Counter 19
Register */
#define XAPM_MC20_OFFSET 0x00000580U /**< Metric Counter 20
Register */
#define XAPM_MC21_OFFSET 0x00000590U /**< Metric Counter 21
Register */
#define XAPM_MC22_OFFSET 0x000005A0U /**< Metric Counter 22
Register */
#define XAPM_MC23_OFFSET 0x000005B0U /**< Metric Counter 23
Register */
#define XAPM_MC24_OFFSET 0x00000700U /**< Metric Counter 24
Register */
#define XAPM_MC25_OFFSET 0x00000710U /**< Metric Counter 25
Register */
#define XAPM_MC26_OFFSET 0x00000720U /**< Metric Counter 26
Register */
#define XAPM_MC27_OFFSET 0x00000730U /**< Metric Counter 27
Register */
#define XAPM_MC28_OFFSET 0x00000740U /**< Metric Counter 28
Register */
#define XAPM_MC29_OFFSET 0x00000750U /**< Metric Counter 29
Register */
#define XAPM_MC30_OFFSET 0x00000760U /**< Metric Counter 30
Register */
#define XAPM_MC31_OFFSET 0x00000770U /**< Metric Counter 31
Register */
#define XAPM_MC32_OFFSET 0x00000780U /**< Metric Counter 32
Register */
#define XAPM_MC33_OFFSET 0x00000790U /**< Metric Counter 33
Register */
#define XAPM_MC34_OFFSET 0x000007A0U /**< Metric Counter 34
Register */
#define XAPM_MC35_OFFSET 0x000007B0U /**< Metric Counter 35
Register */
#define XAPM_MC36_OFFSET 0x00000900U /**< Metric Counter 36
Register */
#define XAPM_MC37_OFFSET 0x00000910U /**< Metric Counter 37
Register */
#define XAPM_MC38_OFFSET 0x00000920U /**< Metric Counter 38
Register */
#define XAPM_MC39_OFFSET 0x00000930U /**< Metric Counter 39
Register */
#define XAPM_MC40_OFFSET 0x00000940U /**< Metric Counter 40
Register */
#define XAPM_MC41_OFFSET 0x00000950U /**< Metric Counter 41
Register */
#define XAPM_MC42_OFFSET 0x00000960U /**< Metric Counter 42
Register */
#define XAPM_MC43_OFFSET 0x00000970U /**< Metric Counter 43
Register */
#define XAPM_MC44_OFFSET 0x00000980U /**< Metric Counter 44
Register */
#define XAPM_MC45_OFFSET 0x00000990U /**< Metric Counter 45
Register */
#define XAPM_MC46_OFFSET 0x000009A0U /**< Metric Counter 46
Register */
#define XAPM_MC47_OFFSET 0x000009B0U /**< Metric Counter 47
Register */
#define XAPM_SMC10_OFFSET 0x000002A0U /**< Sampled Metric Counter
10 Register */
#define XAPM_SMC11_OFFSET 0x000002B0U /**< Sampled Metric Counter
11 Register */
#define XAPM_SMC12_OFFSET 0x00000600U /**< Sampled Metric Counter
12 Register */
#define XAPM_SMC13_OFFSET 0x00000610U /**< Sampled Metric Counter
13 Register */
#define XAPM_SMC14_OFFSET 0x00000620U /**< Sampled Metric Counter
14 Register */
#define XAPM_SMC15_OFFSET 0x00000630U /**< Sampled Metric Counter
15 Register */
#define XAPM_SMC16_OFFSET 0x00000640U /**< Sampled Metric Counter
16 Register */
#define XAPM_SMC17_OFFSET 0x00000650U /**< Sampled Metric Counter
17 Register */
#define XAPM_SMC18_OFFSET 0x00000660U /**< Sampled Metric Counter
18 Register */
#define XAPM_SMC19_OFFSET 0x00000670U /**< Sampled Metric Counter
19 Register */
#define XAPM_SMC20_OFFSET 0x00000680U /**< Sampled Metric Counter
20 Register */
#define XAPM_SMC21_OFFSET 0x00000690U /**< Sampled Metric Counter
21 Register */
#define XAPM_SMC22_OFFSET 0x000006A0U /**< Sampled Metric Counter
22 Register */
#define XAPM_SMC23_OFFSET 0x000006B0U /**< Sampled Metric Counter
23 Register */
#define XAPM_SMC24_OFFSET 0x00000800U /**< Sampled Metric Counter
24 Register */
#define XAPM_SMC25_OFFSET 0x00000810U /**< Sampled Metric Counter
25 Register */
#define XAPM_SMC26_OFFSET 0x00000820U /**< Sampled Metric Counter
26 Register */
#define XAPM_SMC27_OFFSET 0x00000830U /**< Sampled Metric Counter
27 Register */
#define XAPM_SMC28_OFFSET 0x00000840U /**< Sampled Metric Counter
28 Register */
#define XAPM_SMC29_OFFSET 0x00000850U /**< Sampled Metric Counter
29 Register */
#define XAPM_SMC30_OFFSET 0x00000860U /**< Sampled Metric Counter
30 Register */
#define XAPM_SMC31_OFFSET 0x00000870U /**< Sampled Metric Counter
31 Register */
#define XAPM_SMC32_OFFSET 0x00000880U /**< Sampled Metric Counter
32 Register */
#define XAPM_SMC33_OFFSET 0x00000890U /**< Sampled Metric Counter
33 Register */
#define XAPM_SMC34_OFFSET 0x000008A0U /**< Sampled Metric Counter
34 Register */
#define XAPM_SMC35_OFFSET 0x000008B0U /**< Sampled Metric Counter
35 Register */
#define XAPM_SMC36_OFFSET 0x00000A00U /**< Sampled Metric Counter
36 Register */
#define XAPM_SMC37_OFFSET 0x00000A10U /**< Sampled Metric Counter
37 Register */
#define XAPM_SMC38_OFFSET 0x00000A20U /**< Sampled Metric Counter
38 Register */
#define XAPM_SMC39_OFFSET 0x00000A30U /**< Sampled Metric Counter
39 Register */
#define XAPM_SMC40_OFFSET 0x00000A40U /**< Sampled Metric Counter
40 Register */
#define XAPM_SMC41_OFFSET 0x00000A50U /**< Sampled Metric Counter
41 Register */
#define XAPM_SMC42_OFFSET 0x00000A60U /**< Sampled Metric Counter
42 Register */
#define XAPM_SMC43_OFFSET 0x00000A70U /**< Sampled Metric Counter
43 Register */
#define XAPM_SMC44_OFFSET 0x00000A80U /**< Sampled Metric Counter
44 Register */
#define XAPM_SMC45_OFFSET 0x00000A90U /**< Sampled Metric Counter
45 Register */
#define XAPM_SMC46_OFFSET 0x00000AA0U /**< Sampled Metric Counter
46 Register */
#define XAPM_SMC47_OFFSET 0x00000AB0U /**< Sampled Metric Counter
47 Register */
#define XAPM_CTL_OFFSET 0x00000300U /**< Control Register */
#define XAPM_ID_OFFSET 0x00000304U /**< Latency ID Register */
#define XAPM_IDMASK_OFFSET 0x00000308U /**< ID Mask Register */
#define XAPM_RID_OFFSET 0x0000030CU /**< Latency Write ID Register */
#define XAPM_RIDMASK_OFFSET 0x00000310U /**< Read ID Mask Register */
#define XAPM_FEC_OFFSET 0x00000400U /**< Flag Enable
Control Register */
#define XAPM_SWD_OFFSET 0x00000404U /**< Software-written
Data Register */
/* @} */
/**
* @name AXI Monitor Sample Interval Control Register mask(s)
* @{
*/
#define XAPM_SICR_MCNTR_RST_MASK 0x00000100U /**< Enable the Metric
Counter Reset */
#define XAPM_SICR_LOAD_MASK 0x00000002U /**< Load the Sample Interval
* Register Value into the
* counter */
#define XAPM_SICR_ENABLE_MASK 0x00000001U /**< Enable the downcounter */
/*@}*/
/** @name Interrupt Status/Enable Register Bit Definitions and Masks
* @{
*/
#define XAPM_IXR_MC9_OVERFLOW_MASK 0x00001000U /**< Metric Counter 9
* Overflow> */
#define XAPM_IXR_MC8_OVERFLOW_MASK 0x00000800U /**< Metric Counter 8
* Overflow> */
#define XAPM_IXR_MC7_OVERFLOW_MASK 0x00000400U /**< Metric Counter 7
* Overflow> */
#define XAPM_IXR_MC6_OVERFLOW_MASK 0x00000200U /**< Metric Counter 6
* Overflow> */
#define XAPM_IXR_MC5_OVERFLOW_MASK 0x00000100U /**< Metric Counter 5
* Overflow> */
#define XAPM_IXR_MC4_OVERFLOW_MASK 0x00000080U /**< Metric Counter 4
* Overflow> */
#define XAPM_IXR_MC3_OVERFLOW_MASK 0x00000040U /**< Metric Counter 3
* Overflow> */
#define XAPM_IXR_MC2_OVERFLOW_MASK 0x00000020U /**< Metric Counter 2
* Overflow> */
#define XAPM_IXR_MC1_OVERFLOW_MASK 0x00000010U /**< Metric Counter 1
* Overflow> */
#define XAPM_IXR_MC0_OVERFLOW_MASK 0x00000008U /**< Metric Counter 0
* Overflow> */
#define XAPM_IXR_FIFO_FULL_MASK 0x00000004U /**< Event Log FIFO
* full> */
#define XAPM_IXR_SIC_OVERFLOW_MASK 0x00000002U /**< Sample Interval
* Counter Overflow> */
#define XAPM_IXR_GCC_OVERFLOW_MASK 0x00000001U /**< Global Clock Counter
* Overflow> */
#define XAPM_IXR_ALL_MASK (XAPM_IXR_SIC_OVERFLOW_MASK | \
XAPM_IXR_GCC_OVERFLOW_MASK | \
XAPM_IXR_FIFO_FULL_MASK | \
XAPM_IXR_MC0_OVERFLOW_MASK | \
XAPM_IXR_MC1_OVERFLOW_MASK | \
XAPM_IXR_MC2_OVERFLOW_MASK | \
XAPM_IXR_MC3_OVERFLOW_MASK | \
XAPM_IXR_MC4_OVERFLOW_MASK | \
XAPM_IXR_MC5_OVERFLOW_MASK | \
XAPM_IXR_MC6_OVERFLOW_MASK | \
XAPM_IXR_MC7_OVERFLOW_MASK | \
XAPM_IXR_MC8_OVERFLOW_MASK | \
XAPM_IXR_MC9_OVERFLOW_MASK)
/* @} */
/**
* @name AXI Monitor Control Register mask(s)
* @{
*/
#define XAPM_CR_FIFO_RESET_MASK 0x02000000U
/**< FIFO Reset */
#define XAPM_CR_GCC_RESET_MASK 0x00020000U
/**< Global Clk
Counter Reset */
#define XAPM_CR_GCC_ENABLE_MASK 0x00010000U
/**< Global Clk
Counter Enable */
#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK 0x00000200U
/**< Enable External trigger
to start event Log */
#define XAPM_CR_EVENTLOG_ENABLE_MASK 0x00000100U
/**< Event Log Enable */
#define XAPM_CR_RDLATENCY_END_MASK 0x00000080U
/**< Write Latency
End point */
#define XAPM_CR_RDLATENCY_START_MASK 0x00000040U
/**< Read Latency
Start point */
#define XAPM_CR_WRLATENCY_END_MASK 0x00000020U
/**< Write Latency
End point */
#define XAPM_CR_WRLATENCY_START_MASK 0x00000010U
/**< Write Latency
Start point */
#define XAPM_CR_IDFILTER_ENABLE_MASK 0x00000008U
/**< ID Filter Enable */
#define XAPM_CR_MCNTR_EXTTRIGGER_MASK 0x00000004U
/**< Enable External
trigger to start
Metric Counters */
#define XAPM_CR_MCNTR_RESET_MASK 0x00000002U
/**< Metrics Counter
Reset */
#define XAPM_CR_MCNTR_ENABLE_MASK 0x00000001U
/**< Metrics Counter
Enable */
/*@}*/
/**
* @name AXI Monitor ID Register mask(s)
* @{
*/
#define XAPM_ID_RID_MASK 0xFFFF0000U /**< Read ID */
#define XAPM_ID_WID_MASK 0x0000FFFFU /**< Write ID */
/*@}*/
/**
* @name AXI Monitor ID Mask Register mask(s)
* @{
*/
#define XAPM_MASKID_RID_MASK 0xFFFF0000U /**< Read ID Mask */
#define XAPM_MASKID_WID_MASK 0x0000FFFFU /**< Write ID Mask*/
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* Read a register of the AXI Performance Monitor device. This macro provides
* register access to all registers using the register offsets defined above.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset is the offset of the register to read.
*
* @return The contents of the register.
*
* @note C-style Signature:
* u32 XAxiPmon_ReadReg(u32 BaseAddress, u32 RegOffset);
*
******************************************************************************/
#define XAxiPmon_ReadReg(BaseAddress, RegOffset) \
(Xil_In32((BaseAddress) + (RegOffset)))
/*****************************************************************************/
/**
*
* Write a register of the AXI Performance Monitor device. This macro provides
* register access to all registers using the register offsets defined above.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset is the offset of the register to write.
* @param Data is the value to write to the register.
*
* @return None.
*
* @note C-style Signature:
* void XAxiPmon_WriteReg(u32 BaseAddress,
* u32 RegOffset,u32 Data)
*
******************************************************************************/
#define XAxiPmon_WriteReg(BaseAddress, RegOffset, Data) \
(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */
/** @} */

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@ -0,0 +1,119 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.h
*
*
* @note Dummy File for backwards compatibility
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
* </pre>
*
******************************************************************************/
#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
#define XBASIC_TYPES_H /* by using protection macros */
/** @name Legacy types
* Deprecated legacy types.
* @{
*/
typedef unsigned char Xuint8; /**< unsigned 8-bit */
typedef char Xint8; /**< signed 8-bit */
typedef unsigned short Xuint16; /**< unsigned 16-bit */
typedef short Xint16; /**< signed 16-bit */
typedef unsigned long Xuint32; /**< unsigned 32-bit */
typedef long Xint32; /**< signed 32-bit */
typedef float Xfloat32; /**< 32-bit floating point */
typedef double Xfloat64; /**< 64-bit double precision FP */
typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
#if !defined __XUINT64__
typedef struct
{
Xuint32 Upper;
Xuint32 Lower;
} Xuint64;
#endif
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XIL_TYPES_H
typedef Xuint32 u32;
typedef Xuint16 u16;
typedef Xuint8 u8;
#endif
#else
#include <linux/types.h>
#endif
#ifndef TRUE
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
/*
* Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
* Please use NULL, TRUE and FALSE
*/
#define XNULL NULL
#define XTRUE TRUE
#define XFALSE FALSE
/*
* This file is deprecated and users
* should use xil_types.h and xil_assert.h\n\r
*/
#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
#warning Please refer the Standalone BSP UG647 for further details
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcanps.h
* @addtogroup canps_v3_2
* @{
* @details
*
* The Xilinx CAN driver component. This component supports the Xilinx
* CAN Controller.
*
* The CAN Controller supports the following features:
* - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards.
* - Supports both Standard (11 bit Identifier) and Extended (29 bit
* Identifier) frames.
* - Supports Bit Rates up to 1 Mbps.
* - Transmit message object FIFO with a user configurable depth of
* up to 64 message objects.
* - Transmit prioritization through one TX High Priority Buffer.
* - Receive message object FIFO with a user configurable depth of
* up to 64 message objects.
* - Watermark interrupts for Rx FIFO with configurable Watermark.
* - Acceptance filtering with 4 acceptance filters.
* - Sleep mode with automatic wake up.
* - Loop Back mode for diagnostic applications.
* - Snoop mode for diagnostic applications.
* - Maskable Error and Status Interrupts.
* - Readable Error Counters.
* - External PHY chip required.
* - Receive Timestamp.
*
* The device driver supports all the features listed above, if applicable.
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the CAN. The driver handles transmission and reception of
* CAN frames, as well as configuration of the controller. The driver is simply a
* pass-through mechanism between a protocol stack and the CAN. A single device
* driver can support multiple CANs.
*
* Since the driver is a simple pass-through mechanism between a protocol stack
* and the CAN, no assembly or disassembly of CAN frames is done at the
* driver-level. This assumes that the protocol stack passes a correctly
* formatted CAN frame to the driver for transmission, and that the driver
* does not validate the contents of an incoming frame
*
* <b>Operation Modes</b>
*
* The CAN controller supports the following modes of operation:
* - <b>Configuration Mode</b>: In this mode the CAN timing parameters and
* Baud Rate Pre-scalar parameters can be changed. In this mode the CAN
* controller loses synchronization with the CAN bus and drives a
* constant recessive bit on the bus line. The Error Counter Register are
* reset. The CAN controller does not receive or transmit any messages
* even if there are pending transmit requests from the TX FIFO or the TX
* High Priority Buffer. The Storage FIFOs and the CAN configuration
* registers are still accessible.
* - <b>Normal Mode</b>:In Normal Mode the CAN controller participates in bus
* communication, by transmitting and receiving messages.
* - <b>Sleep Mode</b>: In Sleep Mode the CAN Controller does not transmit any
* messages. However, if any other node transmits a message, then the CAN
* Controller receives the transmitted message and exits from Sleep Mode.
* If there are new transmission requests from either the TX FIFO or the
* TX High Priority Buffer when the CAN Controller is in Sleep Mode, these
* requests are not serviced, and the CAN Controller continues to remain
* in Sleep Mode. Interrupts are generated when the CAN controller enters
* Sleep mode or Wakes up from Sleep mode.
* - <b>Loop Back Mode</b>: In Loop Back mode, the CAN controller transmits a
* recessive bit stream on to the CAN Bus. Any message that is transmitted
* is looped back to the <20>Rx<52> line and acknowledged. The CAN controller
* thus receives any message that it transmits. It does not participate in
* normal bus communication and does not receive any messages that are
* transmitted by other CAN nodes. This mode is used for diagnostic
* purposes.
* - <b>Snoop Mode</b>: In Snoop mode, the CAN controller transmits a
* recessive bit stream on to the CAN Bus and does not participate
* in normal bus communication but receives messages that are transmitted
* by other CAN nodes. This mode is used for diagnostic purposes.
*
*
* <b>Buffer Alignment</b>
*
* It is important to note that frame buffers passed to the driver must be
* 32-bit aligned.
*
* <b>Receive Address Filtering</b>
*
* The device can be set to accept frames whose Identifiers match any of the
* 4 filters set in the Acceptance Filter Mask/ID registers.
*
* The incoming Identifier is masked with the bits in the Acceptance Filter Mask
* Register. This value is compared with the result of masking the bits in the
* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If
* both these values are equal, the message will be stored in the RX FIFO.
*
* Acceptance Filtering is performed by each of the defined acceptance filters.
* If the incoming identifier passes through any acceptance filter then the
* frame is stored in the RX FIFO.
*
* If the Accpetance Filters are not set up then all the received messages are
* stroed in the RX FIFO.
*
* <b>PHY Communication</b>
*
* This driver does not provide any mechanism for directly programming PHY.
*
* <b>Interrupts</b>
*
* The driver has no dependencies on the interrupt controller. The driver
* provides an interrupt handler. User of this driver needs to provide
* callback functions. An interrupt handler example is available with
* the driver.
*
* <b>Threads</b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b>Device Reset</b>
*
* Bus Off interrupt that can occur in the device requires a device reset.
* The user is responsible for resetting the device and re-configuring it
* based on its needs (the driver does not save the current configuration).
* When integrating into an RTOS, these reset and re-configure obligations are
* taken care of by the OS adapter software if it exists for that RTOS.
*
* <b>Device Configuration</b>
*
* The device can be configured in various ways during the FPGA implementation
* process. Configuration parameters are stored in the xcanps_g.c files.
* A table is defined where each entry contains configuration information
* for a CAN device. This information includes such things as the base address
* of the memory-mapped device.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b>Building the driver</b>
*
* The XCanPs driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
* <br><br>
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00a xd/sv 01/12/10 First release
* 1.01a bss 12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
* XCanPs_GetTxIntrWatermark.
* Updated the Register/bit definitions
* Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
* Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
* Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
* Changed XCANPS_IXR_RXFLL_MASK to
* XCANPS_IXR_RXFWMFLL_MASK
* Changed
* XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
* XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
* XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
* XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
* 2.1 adk 23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
* SDK claims a 40kbps baud rate but it's not.
* 3.0 adk 09/12/14 Added support for Zynq Ultrascale Mp.Also code
* modified for MISRA-C:2012 compliance.
* 3.1 adk 10/11/15 Fixed CR#911958 Add support for Tx Watermark example.
* Data mismatch while sending data less than 8 bytes.
* 3.1 nsk 12/21/15 Updated XCanPs_IntrHandler in xcanps_intr.c to handle
* error interrupts correctly. CR#925615
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* </pre>
*
******************************************************************************/
#ifndef XCANPS_H /* prevent circular inclusions */
#define XCANPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xcanps_hw.h"
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/** @name CAN operation modes
* @{
*/
#define XCANPS_MODE_CONFIG 0x00000001U /**< Configuration mode */
#define XCANPS_MODE_NORMAL 0x00000002U /**< Normal mode */
#define XCANPS_MODE_LOOPBACK 0x00000004U /**< Loop Back mode */
#define XCANPS_MODE_SLEEP 0x00000008U /**< Sleep mode */
#define XCANPS_MODE_SNOOP 0x00000010U /**< Snoop mode */
/* @} */
/** @name Callback identifiers used as parameters to XCanPs_SetHandler()
* @{
*/
#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */
#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/
#define XCANPS_HANDLER_ERROR 3U /**< Handler type for error interrupt */
#define XCANPS_HANDLER_EVENT 4U /**< Handler type for all other interrupts */
/* @} */
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddr; /**< Register base address */
} XCanPs_Config;
/******************************************************************************/
/**
* Callback type for frame sending and reception interrupts.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
*******************************************************************************/
typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef);
/******************************************************************************/
/**
* Callback type for error interrupt.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
* @param ErrorMask is a bit mask indicating the cause of the error. Its
* value equals 'OR'ing one or more XCANPS_ESR_* values defined in
* xcanps_hw.h
*******************************************************************************/
typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
/******************************************************************************/
/**
* Callback type for all kinds of interrupts except sending frame interrupt,
* receiving frame interrupt, and error interrupt.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
* @param Mask is a bit mask indicating the pending interrupts. Its value
* equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h
*******************************************************************************/
typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask);
/**
* The XCanPs driver instance data. The user is required to allocate a
* variable of this type for every CAN device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XCanPs_Config CanConfig; /**< Device configuration */
u32 IsReady; /**< Device is initialized and ready */
/**
* Callback and callback reference for TXOK interrupt.
*/
XCanPs_SendRecvHandler SendHandler;
void *SendRef;
/**
* Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts.
*/
XCanPs_SendRecvHandler RecvHandler;
void *RecvRef;
/**
* Callback and callback reference for ERROR interrupt.
*/
XCanPs_ErrorHandler ErrorHandler;
void *ErrorRef;
/**
* Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/
* Wakeup/Sleep/Bus off/ARBLST interrupts.
*/
XCanPs_EventHandler EventHandler;
void *EventRef;
} XCanPs;
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro checks if the transmission is complete.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return
* - TRUE if the transmission is done.
* - FALSE if the transmission is not done.
*
* @note C-Style signature:
* int XCanPs_IsTxDone(XCanPs *InstancePtr)
*
*******************************************************************************/
#define XCanPs_IsTxDone(InstancePtr) \
(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro checks if the transmission FIFO is full.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return
* - TRUE if TX FIFO is full.
* - FALSE if the TX FIFO is NOT full.
*
* @note C-Style signature:
* int XCanPs_IsTxFifoFull(XCanPs *InstancePtr)
*
*****************************************************************************/
#define XCanPs_IsTxFifoFull(InstancePtr) \
(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro checks if the Transmission High Priority Buffer is full.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return
* - TRUE if the TX High Priority Buffer is full.
* - FALSE if the TX High Priority Buffer is NOT full.
*
* @note C-Style signature:
* int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr)
*
*****************************************************************************/
#define XCanPs_IsHighPriorityBufFull(InstancePtr) \
(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro checks if the receive FIFO is empty.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return
* - TRUE if RX FIFO is empty.
* - FALSE if the RX FIFO is NOT empty.
*
* @note C-Style signature:
* int XCanPs_IsRxEmpty(XCanPs *InstancePtr)
*
*****************************************************************************/
#define XCanPs_IsRxEmpty(InstancePtr) \
(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE)
/****************************************************************************/
/**
*
* This macro checks if the CAN device is ready for the driver to change
* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask
* Registers (AFMR).
*
* AFIR and AFMR for a filter are changeable only after the filter is disabled
* and this routine returns FALSE. The filter can be disabled using the
* XCanPs_AcceptFilterDisable function.
*
* Use the XCanPs_Accept_* functions for configuring the acceptance filters.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return
* - TRUE if the device is busy and NOT ready to accept writes to
* AFIR and AFMR.
* - FALSE if the device is ready to accept writes to AFIR and
* AFMR.
*
* @note C-Style signature:
* int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr)
*
*****************************************************************************/
#define XCanPs_IsAcceptFilterBusy(InstancePtr) \
(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro calculates CAN message identifier value given identifier field
* values.
*
* @param StandardId contains Standard Message ID value.
* @param SubRemoteTransReq contains Substitute Remote Transmission
* Request value.
* @param IdExtension contains Identifier Extension value.
* @param ExtendedId contains Extended Message ID value.
* @param RemoteTransReq contains Remote Transmission Request value.
*
* @return Message Identifier value.
*
* @note C-Style signature:
* u32 XCanPs_CreateIdValue(u32 StandardId,
* u32 SubRemoteTransReq,
* u32 IdExtension, u32 ExtendedId,
* u32 RemoteTransReq)
*
* Read the CAN specification for meaning of each parameter.
*
*****************************************************************************/
#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \
ExtendedId, RemoteTransReq) \
((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \
(((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\
(((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \
(((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \
((RemoteTransReq) & XCANPS_IDR_RTR_MASK))
/****************************************************************************/
/**
*
* This macro calculates value for Data Length Code register given Data
* Length Code value.
*
* @param DataLengCode indicates Data Length Code value.
*
* @return Value that can be assigned to Data Length Code register.
*
* @note C-Style signature:
* u32 XCanPs_CreateDlcValue(u32 DataLengCode)
*
* Read the CAN specification for meaning of Data Length Code.
*
*****************************************************************************/
#define XCanPs_CreateDlcValue(DataLengCode) \
(((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK)
/****************************************************************************/
/**
*
* This macro clears the timestamp in the Timestamp Control Register.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return None.
*
* @note C-Style signature:
* void XCanPs_ClearTimestamp(XCanPs *InstancePtr)
*
*****************************************************************************/
#define XCanPs_ClearTimestamp(InstancePtr) \
XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \
XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK)
/************************** Function Prototypes ******************************/
/*
* Functions in xcanps.c
*/
s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
u32 EffectiveAddr);
void XCanPs_Reset(XCanPs *InstancePtr);
u8 XCanPs_GetMode(XCanPs *InstancePtr);
void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode);
u32 XCanPs_GetStatus(XCanPs *InstancePtr);
void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
u8 *TxErrorCount);
u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr);
void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask);
s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr);
s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr);
s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr);
void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes);
void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes);
u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr);
s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
u32 MaskValue, u32 IdValue);
void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
u32 *MaskValue, u32 *IdValue);
s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler);
u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr);
s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
u8 TimeSegment2, u8 TimeSegment1);
void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
u8 *TimeSegment2, u8 *TimeSegment1);
s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr);
s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr);
/*
* Diagnostic functions in xcanps_selftest.c
*/
s32 XCanPs_SelfTest(XCanPs *InstancePtr);
/*
* Functions in xcanps_intr.c
*/
void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask);
void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask);
u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr);
u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr);
void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask);
void XCanPs_IntrHandler(void *InstancePtr);
s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
void *CallBackFunc, void *CallBackRef);
/*
* Functions in xcanps_sinit.c
*/
XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcanps_hw.h
* @addtogroup canps_v3_2
* @{
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
* are defined in xcanps.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00a xd/sv 01/12/10 First release
* 1.01a sbs 12/27/11 Updated the Register/bit definitions
* Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
* Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
* Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
* Changed XCANPS_IXR_RXFLL_MASK to
* XCANPS_IXR_RXFWMFLL_MASK
* Changed
* XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
* XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
* XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
* XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
* 1.02a adk 08/08/13 Updated for inclding the function prototype
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
#ifndef XCANPS_HW_H /* prevent circular inclusions */
#define XCANPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register offsets for the CAN. Each register is 32 bits.
* @{
*/
#define XCANPS_SRR_OFFSET 0x00000000U /**< Software Reset Register */
#define XCANPS_MSR_OFFSET 0x00000004U /**< Mode Select Register */
#define XCANPS_BRPR_OFFSET 0x00000008U /**< Baud Rate Prescaler */
#define XCANPS_BTR_OFFSET 0x0000000CU /**< Bit Timing Register */
#define XCANPS_ECR_OFFSET 0x00000010U /**< Error Counter Register */
#define XCANPS_ESR_OFFSET 0x00000014U /**< Error Status Register */
#define XCANPS_SR_OFFSET 0x00000018U /**< Status Register */
#define XCANPS_ISR_OFFSET 0x0000001CU /**< Interrupt Status Register */
#define XCANPS_IER_OFFSET 0x00000020U /**< Interrupt Enable Register */
#define XCANPS_ICR_OFFSET 0x00000024U /**< Interrupt Clear Register */
#define XCANPS_TCR_OFFSET 0x00000028U /**< Timestamp Control Register */
#define XCANPS_WIR_OFFSET 0x0000002CU /**< Watermark Interrupt Reg */
#define XCANPS_TXFIFO_ID_OFFSET 0x00000030U /**< TX FIFO ID */
#define XCANPS_TXFIFO_DLC_OFFSET 0x00000034U /**< TX FIFO DLC */
#define XCANPS_TXFIFO_DW1_OFFSET 0x00000038U /**< TX FIFO Data Word 1 */
#define XCANPS_TXFIFO_DW2_OFFSET 0x0000003CU /**< TX FIFO Data Word 2 */
#define XCANPS_TXHPB_ID_OFFSET 0x00000040U /**< TX High Priority Buffer ID */
#define XCANPS_TXHPB_DLC_OFFSET 0x00000044U /**< TX High Priority Buffer DLC */
#define XCANPS_TXHPB_DW1_OFFSET 0x00000048U /**< TX High Priority Buf Data 1 */
#define XCANPS_TXHPB_DW2_OFFSET 0x0000004CU /**< TX High Priority Buf Data Word 2 */
#define XCANPS_RXFIFO_ID_OFFSET 0x00000050U /**< RX FIFO ID */
#define XCANPS_RXFIFO_DLC_OFFSET 0x00000054U /**< RX FIFO DLC */
#define XCANPS_RXFIFO_DW1_OFFSET 0x00000058U /**< RX FIFO Data Word 1 */
#define XCANPS_RXFIFO_DW2_OFFSET 0x0000005CU /**< RX FIFO Data Word 2 */
#define XCANPS_AFR_OFFSET 0x00000060U /**< Acceptance Filter Register */
#define XCANPS_AFMR1_OFFSET 0x00000064U /**< Acceptance Filter Mask 1 */
#define XCANPS_AFIR1_OFFSET 0x00000068U /**< Acceptance Filter ID 1 */
#define XCANPS_AFMR2_OFFSET 0x0000006CU /**< Acceptance Filter Mask 2 */
#define XCANPS_AFIR2_OFFSET 0x00000070U /**< Acceptance Filter ID 2 */
#define XCANPS_AFMR3_OFFSET 0x00000074U /**< Acceptance Filter Mask 3 */
#define XCANPS_AFIR3_OFFSET 0x00000078U /**< Acceptance Filter ID 3 */
#define XCANPS_AFMR4_OFFSET 0x0000007CU /**< Acceptance Filter Mask 4 */
#define XCANPS_AFIR4_OFFSET 0x00000080U /**< Acceptance Filter ID 4 */
/* @} */
/** @name Software Reset Register (SRR) Bit Definitions and Masks
* @{
*/
#define XCANPS_SRR_CEN_MASK 0x00000002U /**< Can Enable */
#define XCANPS_SRR_SRST_MASK 0x00000001U /**< Reset */
/* @} */
/** @name Mode Select Register (MSR) Bit Definitions and Masks
* @{
*/
#define XCANPS_MSR_SNOOP_MASK 0x00000004U /**< Snoop Mode Select */
#define XCANPS_MSR_LBACK_MASK 0x00000002U /**< Loop Back Mode Select */
#define XCANPS_MSR_SLEEP_MASK 0x00000001U /**< Sleep Mode Select */
/* @} */
/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks
* @{
*/
#define XCANPS_BRPR_BRP_MASK 0x000000FFU /**< Baud Rate Prescaler */
/* @} */
/** @name Bit Timing Register (BTR) Bit Definitions and Masks
* @{
*/
#define XCANPS_BTR_SJW_MASK 0x00000180U /**< Synchronization Jump Width */
#define XCANPS_BTR_SJW_SHIFT 7U
#define XCANPS_BTR_TS2_MASK 0x00000070U /**< Time Segment 2 */
#define XCANPS_BTR_TS2_SHIFT 4U
#define XCANPS_BTR_TS1_MASK 0x0000000FU /**< Time Segment 1 */
/* @} */
/** @name Error Counter Register (ECR) Bit Definitions and Masks
* @{
*/
#define XCANPS_ECR_REC_MASK 0x0000FF00U /**< Receive Error Counter */
#define XCANPS_ECR_REC_SHIFT 8U
#define XCANPS_ECR_TEC_MASK 0x000000FFU /**< Transmit Error Counter */
/* @} */
/** @name Error Status Register (ESR) Bit Definitions and Masks
* @{
*/
#define XCANPS_ESR_ACKER_MASK 0x00000010U /**< ACK Error */
#define XCANPS_ESR_BERR_MASK 0x00000008U /**< Bit Error */
#define XCANPS_ESR_STER_MASK 0x00000004U /**< Stuff Error */
#define XCANPS_ESR_FMER_MASK 0x00000002U /**< Form Error */
#define XCANPS_ESR_CRCER_MASK 0x00000001U /**< CRC Error */
/* @} */
/** @name Status Register (SR) Bit Definitions and Masks
* @{
*/
#define XCANPS_SR_SNOOP_MASK 0x00001000U /**< Snoop Mask */
#define XCANPS_SR_ACFBSY_MASK 0x00000800U /**< Acceptance Filter busy */
#define XCANPS_SR_TXFLL_MASK 0x00000400U /**< TX FIFO is full */
#define XCANPS_SR_TXBFLL_MASK 0x00000200U /**< TX High Priority Buffer full */
#define XCANPS_SR_ESTAT_MASK 0x00000180U /**< Error Status */
#define XCANPS_SR_ESTAT_SHIFT 7U
#define XCANPS_SR_ERRWRN_MASK 0x00000040U /**< Error Warning */
#define XCANPS_SR_BBSY_MASK 0x00000020U /**< Bus Busy */
#define XCANPS_SR_BIDLE_MASK 0x00000010U /**< Bus Idle */
#define XCANPS_SR_NORMAL_MASK 0x00000008U /**< Normal Mode */
#define XCANPS_SR_SLEEP_MASK 0x00000004U /**< Sleep Mode */
#define XCANPS_SR_LBACK_MASK 0x00000002U /**< Loop Back Mode */
#define XCANPS_SR_CONFIG_MASK 0x00000001U /**< Configuration Mode */
/* @} */
/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks
* @{
*/
#define XCANPS_IXR_TXFEMP_MASK 0x00004000U /**< Tx Fifo Empty Interrupt */
#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */
#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */
#define XCANPS_IXR_WKUP_MASK 0x00000800U /**< Wake up Interrupt */
#define XCANPS_IXR_SLP_MASK 0x00000400U /**< Sleep Interrupt */
#define XCANPS_IXR_BSOFF_MASK 0x00000200U /**< Bus Off Interrupt */
#define XCANPS_IXR_ERROR_MASK 0x00000100U /**< Error Interrupt */
#define XCANPS_IXR_RXNEMP_MASK 0x00000080U /**< RX FIFO Not Empty Interrupt */
#define XCANPS_IXR_RXOFLW_MASK 0x00000040U /**< RX FIFO Overflow Interrupt */
#define XCANPS_IXR_RXUFLW_MASK 0x00000020U /**< RX FIFO Underflow Interrupt */
#define XCANPS_IXR_RXOK_MASK 0x00000010U /**< New Message Received Intr */
#define XCANPS_IXR_TXBFLL_MASK 0x00000008U /**< TX High Priority Buf Full */
#define XCANPS_IXR_TXFLL_MASK 0x00000004U /**< TX FIFO Full Interrupt */
#define XCANPS_IXR_TXOK_MASK 0x00000002U /**< TX Successful Interrupt */
#define XCANPS_IXR_ARBLST_MASK 0x00000001U /**< Arbitration Lost Interrupt */
#define XCANPS_IXR_ALL ((u32)XCANPS_IXR_RXFWMFLL_MASK | \
(u32)XCANPS_IXR_WKUP_MASK | \
(u32)XCANPS_IXR_SLP_MASK | \
(u32)XCANPS_IXR_BSOFF_MASK | \
(u32)XCANPS_IXR_ERROR_MASK | \
(u32)XCANPS_IXR_RXNEMP_MASK | \
(u32)XCANPS_IXR_RXOFLW_MASK | \
(u32)XCANPS_IXR_RXUFLW_MASK | \
(u32)XCANPS_IXR_RXOK_MASK | \
(u32)XCANPS_IXR_TXBFLL_MASK | \
(u32)XCANPS_IXR_TXFLL_MASK | \
(u32)XCANPS_IXR_TXOK_MASK | \
(u32)XCANPS_IXR_ARBLST_MASK)
/* @} */
/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks
* @{
*/
#define XCANPS_TCR_CTS_MASK 0x00000001U /**< Clear Timestamp counter mask */
/* @} */
/** @name CAN Watermark Register (WIR) Bit Definitions and Masks
* @{
*/
#define XCANPS_WIR_FW_MASK 0x0000003FU /**< Rx Full Threshold mask */
#define XCANPS_WIR_EW_MASK 0x00003F00U /**< Tx Empty Threshold mask */
#define XCANPS_WIR_EW_SHIFT 0x00000008U /**< Tx Empty Threshold shift */
/* @} */
/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter
Mask/Acceptance Filter ID)
* @{
*/
#define XCANPS_IDR_ID1_MASK 0xFFE00000U /**< Standard Messg Identifier */
#define XCANPS_IDR_ID1_SHIFT 21U
#define XCANPS_IDR_SRR_MASK 0x00100000U /**< Substitute Remote TX Req */
#define XCANPS_IDR_SRR_SHIFT 20U
#define XCANPS_IDR_IDE_MASK 0x00080000U /**< Identifier Extension */
#define XCANPS_IDR_IDE_SHIFT 19U
#define XCANPS_IDR_ID2_MASK 0x0007FFFEU /**< Extended Message Ident */
#define XCANPS_IDR_ID2_SHIFT 1U
#define XCANPS_IDR_RTR_MASK 0x00000001U /**< Remote TX Request */
/* @} */
/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)
* @{
*/
#define XCANPS_DLCR_DLC_MASK 0xF0000000U /**< Data Length Code */
#define XCANPS_DLCR_DLC_SHIFT 28U
#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU /**< Timestamp Mask (Rx only) */
/* @} */
/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX)
* @{
*/
#define XCANPS_DW1R_DB0_MASK 0xFF000000U /**< Data Byte 0 */
#define XCANPS_DW1R_DB0_SHIFT 24U
#define XCANPS_DW1R_DB1_MASK 0x00FF0000U /**< Data Byte 1 */
#define XCANPS_DW1R_DB1_SHIFT 16U
#define XCANPS_DW1R_DB2_MASK 0x0000FF00U /**< Data Byte 2 */
#define XCANPS_DW1R_DB2_SHIFT 8U
#define XCANPS_DW1R_DB3_MASK 0x000000FFU /**< Data Byte 3 */
/* @} */
/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX)
* @{
*/
#define XCANPS_DW2R_DB4_MASK 0xFF000000U /**< Data Byte 4 */
#define XCANPS_DW2R_DB4_SHIFT 24U
#define XCANPS_DW2R_DB5_MASK 0x00FF0000U /**< Data Byte 5 */
#define XCANPS_DW2R_DB5_SHIFT 16U
#define XCANPS_DW2R_DB6_MASK 0x0000FF00U /**< Data Byte 6 */
#define XCANPS_DW2R_DB6_SHIFT 8U
#define XCANPS_DW2R_DB7_MASK 0x000000FFU /**< Data Byte 7 */
/* @} */
/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks
* @{
*/
#define XCANPS_AFR_UAF4_MASK 0x00000008U /**< Use Acceptance Filter No.4 */
#define XCANPS_AFR_UAF3_MASK 0x00000004U /**< Use Acceptance Filter No.3 */
#define XCANPS_AFR_UAF2_MASK 0x00000002U /**< Use Acceptance Filter No.2 */
#define XCANPS_AFR_UAF1_MASK 0x00000001U /**< Use Acceptance Filter No.1 */
#define XCANPS_AFR_UAF_ALL_MASK ((u32)XCANPS_AFR_UAF4_MASK | \
(u32)XCANPS_AFR_UAF3_MASK | \
(u32)XCANPS_AFR_UAF2_MASK | \
(u32)XCANPS_AFR_UAF1_MASK)
/* @} */
/** @name CAN frame length constants
* @{
*/
#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */
/* @} */
/* For backwards compatibilty */
#define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET
#define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET
#define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET
#define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET
#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK
#define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET
#define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the register offset to be read.
*
* @return The 32-bit value of the register
*
* @note None.
*
*****************************************************************************/
#define XCanPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* This macro writes the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the register offset to be written.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes ******************************/
/*
* Perform reset operation to the CanPs interface
*/
void XCanPs_ResetHw(u32 BaseAddr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcoresightpsdcc.h
* @addtogroup coresightps_dcc_v1_4
* @{
* @details
*
* CoreSight driver component.
*
* The coresight is a part of debug communication channel (DCC) group. Jtag UART
* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
* ARM target in XSDB console before running the jtag terminal command. Using the
* coresight driver component, the output stream can be directed to a log file.
*
* @note None.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00 kvn 02/14/15 First release
* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
* kvn 08/18/15 Modified Makefile according to compiler changes.
* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
* for MB BSPs. Instead it throws up a warning. This
* fixes the CR#953056.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#ifndef __MICROBLAZE__
#include <xil_types.h>
void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
#endif
/** @} */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcpu_cortexa53.h
* @addtogroup cpu_cortexa53_v1_5
* @{
* @details
*
* dummy file
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.4 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
* parameter of cpu_cortexa53 in xparameters.h
******************************************************************************/
/** @} */

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/******************************************************************************
*
* Copyright (C) 2014-2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* The CSU_DMA is present inside CSU (Configuration Security Unit) module which
* is located within the Low-Power Subsystem (LPS) internal to the PS.
* CSU_DMA allows the CSU to move data efficiently between the memory (32 bit
* AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure
* Stream Switch (SSS).
*
* The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC
* (read) channel and DST (write) channel. The DMA is effectively able to
* transfer data:
* - From PS-side to the SSS-side (SRC DMA only)
* - From SSS-side to the PS-side (DST DMA only)
* - Simultaneous PS-side to SSS_side and SSS-side to the PS-side
*
* <b>Initialization & Configuration</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the CSU_DMA core.
*
* XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core.
* The user needs to first call the XCsuDma_LookupConfig() API which returns
* the Configuration structure pointer which is passed as a parameter to the
* XCsuDma_CfgInitialize() API.
*
* <b> Interrupts </b>
* This driver will not support handling of interrupts user should write handler
* to handle the interrupts.
*
* <b> Virtual Memory </b>
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
* <b> Threads </b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b> Asserts </b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b> Building the driver </b>
*
* The XCsuDma driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* @file xcsudma.h
* @addtogroup csudma_v1_2
* @{
* @details
*
* This header file contains identifiers and register-level driver functions (or
* macros), range macros, structure typedefs that can be used to access the
* Xilinx CSU_DMA core instance.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------------
* 1.0 vnsld 22/10/14 First release
* 1.1 adk 10/05/16 Fixed CR#951040 race condition in the recv path when
* source and destination points to the same buffer.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/10/17 Modified filename tag in xcsudma_selftest_example.c to
* include the file in doxygen examples.
* 1.2 adk 11/22/17 Added peripheral test app support for CSUDMA driver.
* adk 09/03/18 Added new API XCsuDma_64BitTransfer() useful for 64-bit
* dma transfers through PMU processor(CR#996201).
* </pre>
*
******************************************************************************/
#ifndef XCSUDMA_H_
#define XCSUDMA_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xcsudma_hw.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xil_cache.h"
/************************** Constant Definitions *****************************/
/** @name CSU_DMA Channels
* @{
*/
typedef enum {
XCSUDMA_SRC_CHANNEL = 0U, /**< Source Channel of CSU_DMA */
XCSUDMA_DST_CHANNEL /**< Destination Channel of CSU_DMA */
}XCsuDma_Channel;
/*@}*/
/** @name CSU_DMA pause types
* @{
*/
typedef enum {
XCSUDMA_PAUSE_MEMORY, /**< Pauses memory data transfer
* to/from CSU_DMA */
XCSUDMA_PAUSE_STREAM, /**< Pauses stream data transfer
* to/from CSU_DMA */
}XCsuDma_PauseType;
/*@}*/
/** @name Ranges of Size
* @{
*/
#define XCSUDMA_SIZE_MAX 0x07FFFFFF /**< Maximum allowed no of words */
/*@}*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* This function resets the CSU_DMA core.
*
* @param None.
*
* @return None.
*
* @note None.
* C-style signature:
* void XCsuDma_Reset()
*
******************************************************************************/
#define XCsuDma_Reset() \
Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
(u32)(XCSUDMA_RESET_SET_MASK)); \
Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
(u32)(XCSUDMA_RESET_UNSET_MASK));
/*****************************************************************************/
/**
* This function will be in busy while loop until the data transfer is
* completed.
*
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return None.
*
* @note This function should be called after XCsuDma_Transfer in polled
* mode to wait until the data gets transfered completely.
* C-style signature:
* void XCsuDma_WaitForDone(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_WaitForDone(InstancePtr,Channel) \
while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_I_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK))
/*****************************************************************************/
/**
*
* This function returns the number of completed SRC/DST DMA transfers that
* have not been acknowledged by software based on the channel selection.
*
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return Count is number of completed DMA transfers but not acknowledged
* (Range is 0 to 7).
* - 000 - All finished transfers have been acknowledged.
* - Count - Count number of finished transfers are still
* outstanding.
*
* @note None.
* C-style signature:
* u8 XCsuDma_GetDoneCount(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_GetDoneCount(InstancePtr, Channel) \
((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_STS_DONE_CNT_MASK)) >> \
(u32)(XCSUDMA_STS_DONE_CNT_SHIFT))
/*****************************************************************************/
/**
*
* This function returns the current SRC/DST FIFO level in 32 bit words of the
* selected channel
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return FIFO level. (Range is 0 to 128)
* - 0 Indicates empty
* - Any number 1 to 128 indicates the number of entries in FIFO.
*
* @note None.
* C-style signature:
* u8 XCsuDma_GetFIFOLevel(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_GetFIFOLevel(InstancePtr, Channel) \
((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_STS_FIFO_LEVEL_MASK)) >> \
(u32)(XCSUDMA_STS_FIFO_LEVEL_SHIFT))
/*****************************************************************************/
/**
*
* This function returns the current number of read(src)/write(dst) outstanding
* commands based on the type of channel selected.
*
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return Count of outstanding commands. (Range is 0 to 9).
*
* @note None.
* C-style signature:
* u8 XCsuDma_GetWROutstandCount(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_GetWROutstandCount(InstancePtr, Channel) \
((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCUSDMA_STS_OUTSTDG_MASK)) >> \
(u32)(XCUSDMA_STS_OUTSTDG_SHIFT))
/*****************************************************************************/
/**
*
* This function returns the status of Channel either it is busy or not.
*
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return Returns the current status of the core.
* - TRUE represents core is currently busy.
* - FALSE represents core is not involved in any transfers.
*
* @note None.
* C-style signature:
* s32 XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_IsBusy(InstancePtr, Channel) \
((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_STS_BUSY_MASK)) == (XCSUDMA_STS_BUSY_MASK)) ? \
(TRUE) : (FALSE)
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for a CSU_DMA core.
* Each CSU_DMA core should have a configuration structure associated.
*/
typedef struct {
u16 DeviceId; /**< DeviceId is the unique ID of the
* device */
u32 BaseAddress; /**< BaseAddress is the physical base address
* of the device's registers */
} XCsuDma_Config;
/******************************************************************************/
/**
*
* The XCsuDma driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef struct {
XCsuDma_Config Config; /**< Hardware configuration */
u32 IsReady; /**< Device and the driver instance
* are initialized */
}XCsuDma;
/******************************************************************************/
/**
* This typedef contains all the configuration feilds which needs to be set
* before the start of the data transfer. All these feilds of CSU_DMA can be
* configured by using XCsuDma_SetConfig API.
*/
typedef struct {
u8 SssFifoThesh; /**< SSS FIFO threshold value */
u8 ApbErr; /**< ABP invalid access error */
u8 EndianType; /**< Type of endianess */
u8 AxiBurstType; /**< Type of AXI bus */
u32 TimeoutValue; /**< Time out value */
u8 FifoThresh; /**< FIFO threshold value */
u8 Acache; /**< AXI CACHE selection */
u8 RouteBit; /**< Selection of Route */
u8 TimeoutEn; /**< Enable of time out counters */
u16 TimeoutPre; /**< Pre scaler value */
u8 MaxOutCmds; /**< Maximum number of outstanding
* commands */
}XCsuDma_Configure;
/*****************************************************************************/
/************************** Function Prototypes ******************************/
XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId);
s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
u32 EffectiveAddr);
void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
UINTPTR Addr, u32 Size, u8 EnDataLast);
void XCsuDma_64BitTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast);
void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr,
u32 Size);
u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_PauseType Type);
s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_PauseType Type);
void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_PauseType Type);
u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr);
void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr);
void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_Configure *ConfigurValues);
void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_Configure *ConfigurValues);
void XCsuDma_ClearDoneCount(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
void XCsuDma_SetSafetyCheck(XCsuDma *InstancePtr, u32 Value);
u32 XCsuDma_GetSafetyCheck(XCsuDma *InstancePtr);
/* Interrupt related APIs */
u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 Mask);
void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 Mask);
void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 Mask);
u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
s32 XCsuDma_SelfTest(XCsuDma *InstancePtr);
/******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcsudma_hw.h
* @addtogroup csudma_v1_2
* @{
*
* This header file contains identifiers and register-level driver functions (or
* macros) that can be used to access the Xilinx CSU_DMA core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 1.0 vnsld 22/10/14 First release
* </pre>
*
******************************************************************************/
#ifndef XCSUDMA_HW_H_
#define XCSUDMA_HW_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Registers offsets
* @{
*/
#define XCSUDMA_ADDR_OFFSET 0x000 /**< Address Register Offset */
#define XCSUDMA_SIZE_OFFSET 0x004 /**< Size Register Offset */
#define XCSUDMA_STS_OFFSET 0x008 /**< Status Register Offset */
#define XCSUDMA_CTRL_OFFSET 0x00C /**< Control Register Offset */
#define XCSUDMA_CRC_OFFSET 0x010 /**< CheckSum Register Offset */
#define XCSUDMA_I_STS_OFFSET 0x014 /**< Interrupt Status Register
* Offset */
#define XCSUDMA_I_EN_OFFSET 0x018 /**< Interrupt Enable Register
* Offset */
#define XCSUDMA_I_DIS_OFFSET 0x01C /**< Interrupt Disable Register
* Offset */
#define XCSUDMA_I_MASK_OFFSET 0x020 /**< Interrupt Mask Register Offset */
#define XCSUDMA_CTRL2_OFFSET 0x024 /**< Interrupt Control Register 2
* Offset */
#define XCSUDMA_ADDR_MSB_OFFSET 0x028 /**< Address's MSB Register Offset */
#define XCSUDMA_SAFETY_CHK_OFFSET 0xFF8 /**< Safety Check Field Offset */
#define XCSUDMA_FUTURE_ECO_OFFSET 0xFFC /**< Future potential ECO Offset */
/*@}*/
/** @name CSU Base address and CSU_DMA reset offset
* @{
*/
#define XCSU_BASEADDRESS 0xFFCA0000
/**< CSU Base Address */
#define XCSU_DMA_RESET_OFFSET 0x0000000CU /**< CSU_DMA Reset offset */
/*@}*/
/** @name CSU_DMA Reset register bit masks
* @{
*/
#define XCSUDMA_RESET_SET_MASK 0x00000001U /**< Reset set mask */
#define XCSUDMA_RESET_UNSET_MASK 0x00000000U /**< Reset unset mask*/
/*@}*/
/** @name Offset difference for Source and destination
* @{
*/
#define XCSUDMA_OFFSET_DIFF 0x00000800U /**< Offset difference for
* source and
* destination channels */
/*@}*/
/** @name Address register bit masks
* @{
*/
#define XCSUDMA_ADDR_MASK 0xFFFFFFFCU /**< Address mask */
#define XCSUDMA_ADDR_LSB_MASK 0x00000003U /**< Address alignment check
* mask */
/*@}*/
/** @name Size register bit masks and shifts
* @{
*/
#define XCSUDMA_SIZE_MASK 0x1FFFFFFCU /**< Mask for size */
#define XCSUDMA_LAST_WORD_MASK 0x00000001U /**< Last word check bit mask*/
#define XCSUDMA_SIZE_SHIFT 2U /**< Shift for size */
/*@}*/
/** @name Status register bit masks and shifts
* @{
*/
#define XCSUDMA_STS_DONE_CNT_MASK 0x0000E000U /**< Count done mask */
#define XCSUDMA_STS_FIFO_LEVEL_MASK 0x00001FE0U /**< FIFO level mask */
#define XCUSDMA_STS_OUTSTDG_MASK 0x0000001EU /**< No.of outstanding
* read/write
* commands mask */
#define XCSUDMA_STS_BUSY_MASK 0x00000001U /**< Busy mask */
#define XCSUDMA_STS_DONE_CNT_SHIFT 13U /**< Shift for Count
* done */
#define XCSUDMA_STS_FIFO_LEVEL_SHIFT 5U /**< Shift for FIFO
* level */
#define XCUSDMA_STS_OUTSTDG_SHIFT 1U /**< Shift for No.of
* outstanding
* read/write
* commands */
/*@}*/
/** @name Control register bit masks and shifts
* @{
*/
#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK 0xFE000000U /**< SSS FIFO threshold
* value mask */
#define XCSUDMA_CTRL_APB_ERR_MASK 0x01000000U /**< APB register
* access error
* mask */
#define XCSUDMA_CTRL_ENDIAN_MASK 0x00800000U /**< Endianess mask */
#define XCSUDMA_CTRL_BURST_MASK 0x00400000U /**< AXI burst type
* mask */
#define XCSUDMA_CTRL_TIMEOUT_MASK 0x003FFC00U /**< Time out value
* mask */
#define XCSUDMA_CTRL_FIFO_THRESH_MASK 0x000003FCU /**< FIFO threshold
* mask */
#define XCSUDMA_CTRL_PAUSE_MEM_MASK 0x00000001U /**< Memory pause
* mask */
#define XCSUDMA_CTRL_PAUSE_STRM_MASK 0x00000002U /**< Stream pause
* mask */
#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT 25U /**< SSS FIFO threshold
* shift */
#define XCSUDMA_CTRL_APB_ERR_SHIFT 24U /**< APB error shift */
#define XCSUDMA_CTRL_ENDIAN_SHIFT 23U /**< Endianess shift */
#define XCSUDMA_CTRL_BURST_SHIFT 22U /**< AXI burst type
* shift */
#define XCSUDMA_CTRL_TIMEOUT_SHIFT 10U /**< Time out value
* shift */
#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT 2U /**< FIFO thresh
* shift */
/*@}*/
/** @name CheckSum register bit masks
* @{
*/
#define XCSUDMA_CRC_RESET_MASK 0x00000000U /**< Mask to reset
* value of
* check sum */
/*@}*/
/** @name Interrupt Enable/Disable/Mask/Status registers bit masks
* @{
*/
#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK 0x00000001U /**< FIFO overflow
* mask, it is valid
* only to Destination
* Channel */
#define XCSUDMA_IXR_INVALID_APB_MASK 0x00000040U /**< Invalid APB access
* mask */
#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK 0x00000020U /**< FIFO threshold hit
* indicator mask */
#define XCSUDMA_IXR_TIMEOUT_MEM_MASK 0x00000010U /**< Time out counter
* expired to access
* memory mask */
#define XCSUDMA_IXR_TIMEOUT_STRM_MASK 0x00000008U /**< Time out counter
* expired to access
* stream mask */
#define XCSUDMA_IXR_AXI_WRERR_MASK 0x00000004U /**< AXI Read/Write
* error mask */
#define XCSUDMA_IXR_DONE_MASK 0x00000002U /**< Done mask */
#define XCSUDMA_IXR_MEM_DONE_MASK 0x00000001U /**< Memory done
* mask, it is valid
* only for source
* channel*/
#define XCSUDMA_IXR_SRC_MASK 0x0000007FU
/**< ((XCSUDMA_IXR_INVALID_APB_MASK)|
(XCSUDMA_IXR_FIFO_THRESHHIT_MASK) |
(XCSUDMA_IXR_TIMEOUT_MEM_MASK) |
(XCSUDMA_IXR_TIMEOUT_STRM_MASK) |
(XCSUDMA_IXR_AXI_WRERR_MASK) |
(XCSUDMA_IXR_DONE_MASK) |
(XCSUDMA_IXR_MEM_DONE_MASK)) */
/**< All interrupt mask
* for source */
#define XCSUDMA_IXR_DST_MASK 0x000000FEU
/**< ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) |
(XCSUDMA_IXR_INVALID_APB_MASK) |
(XCSUDMA_IXR_FIFO_THRESHHIT_MASK) |
(XCSUDMA_IXR_TIMEOUT_MEM_MASK) |
(XCSUDMA_IXR_TIMEOUT_STRM_MASK) |
(XCSUDMA_IXR_AXI_WRERR_MASK) |
(XCSUDMA_IXR_DONE_MASK)) */
/**< All interrupt mask
* for destination */
/*@}*/
/** @name Control register 2 bit masks and shifts
* @{
*/
#define XCSUDMA_CTRL2_RESERVED_MASK 0x083F0000U /**< Reserved bits
* mask */
#define XCSUDMA_CTRL2_ACACHE_MASK 0X07000000U /**< AXI CACHE mask */
#define XCSUDMA_CTRL2_ROUTE_MASK 0x00800000U /**< Route mask */
#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK 0x00400000U /**< Time out counters
* enable mask */
#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK 0x0000FFF0U /**< Time out pre
* mask */
#define XCSUDMA_CTRL2_MAXCMDS_MASK 0x0000000FU /**< Maximum commands
* mask */
#define XCSUDMA_CTRL2_RESET_MASK 0x0000FFF8U /**< Reset mask */
#define XCSUDMA_CTRL2_ACACHE_SHIFT 24U /**< Shift for
* AXI R/W CACHE */
#define XCSUDMA_CTRL2_ROUTE_SHIFT 23U /**< Shift for route */
#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT 22U /**< Shift for Timeout
* enable feild */
#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT 4U /**< Shift for Timeout
* pre feild */
/*@}*/
/** @name MSB Address register bit masks and shifts
* @{
*/
#define XCSUDMA_MSB_ADDR_MASK 0x0001FFFFU /**< MSB bits of address
* mask */
#define XCSUDMA_MSB_ADDR_SHIFT 32U /**< Shift for MSB bits of
* address */
/*@}*/
/***************** Macros (Inline Functions) Definitions *********************/
#define XCsuDma_In32 Xil_In32 /**< Input operation */
#define XCsuDma_Out32 Xil_Out32 /**< Output operation */
/*****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddress is the Xilinx base address of the CSU_DMA core.
* @param RegOffset is the register offset of the register.
*
* @return The 32-bit value of the register.
*
* @note C-style signature:
* u32 XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define XCsuDma_ReadReg(BaseAddress, RegOffset) \
XCsuDma_In32((BaseAddress) + (u32)(RegOffset))
/*****************************************************************************/
/**
*
* This macro writes the value into the given register.
*
* @param BaseAddress is the Xilinx base address of the CSU_DMA core.
* @param RegOffset is the register offset of the register.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note C-style signature:
* void XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XCsuDma_WriteReg(BaseAddress, RegOffset, Data) \
XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */
/** @} */

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/*******************************************************************************
*
* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xddcrpsu.h
* @addtogroup ddrcpsu_v1_1
* @{
* @details
*
* The Xilinx DdrcPsu driver. This driver supports the Xilinx ddrcpsu
* IP core.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 ssc 04/28/16 First Release.
* 1.1 adk 04/08/16 Export DDR freq to xparameters.h file.
*
* </pre>
*
*******************************************************************************/
#ifndef XDDRCPS_H_
/* Prevent circular inclusions by using protection macros. */
#define XDDRCPS_H_
/******************************* Include Files ********************************/
#endif /* XDDRCPS_H_ */
/** @} */

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#ifndef XDEBUG /* prevent circular inclusions */
#define XDEBUG /* by using protection macros */
#if defined(DEBUG) && !defined(NDEBUG)
#ifndef XDEBUG_WARNING
#define XDEBUG_WARNING
#warning DEBUG is enabled
#endif
int printf(const char *format, ...);
#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
#define xdbg_current_types (XDBG_DEBUG_GENERAL)
#define xdbg_stmnt(x) x
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x)
#define xdbg_printf(...)
#endif /* defined(DEBUG) && !defined(NDEBUG) */
#endif /* XDEBUG */

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/******************************************************************************
*
* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdpdma.h
*
* This file defines the functions implemented by the DPDMA driver present
* in the Zynq Ultrascale MP.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- ----- -------- ----------------------------------------------------
* 1.0 aad 04/12/16 Initial release.
*
*****************************************************************************/
#ifndef XDPDMA_H_
/* Prevent circular inclusions by using protection macros. */
#define XDPDMA_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files **********************************/
#include "xdpdma_hw.h"
#include "xvidc.h"
#include "xil_io.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xavbuf.h"
/************************** Constant Definitions ******************************/
/* Alignment for DPDMA Descriptor and Payload */
#define XDPDMA_DESCRIPTOR_ALIGN 256
/* DPDMA preamble field */
#define XDPDMA_DESCRIPTOR_PREAMBLE 0xA5
/**************************** Type Definitions ********************************/
/**
* This typedef describes the DPDMA descriptor structure and its internals
* which will be used when fetching data from a nonlive path
*/
typedef struct {
u32 Control; /**< [7:0] Descriptor Preamble
[8] Enable completion Interrupt
[9] Enable descriptor update
[10] Ignore Done
[11] AXI burst type
[15:12] AXACHE
[17:16] AXPROT
[18] Descriptor mode
[19] Last Descriptor
[20] Enable CRC
[21] Last descriptor frame
[31:22] Reserved */
u32 DSCR_ID; /**< [15:0] Descriptor ID
[31:16] Reserved */
u32 XFER_SIZE; /**< Size of transfer in bytes */
u32 LINE_SIZE_STRIDE; /**< [17:0] Horizontal Resolution
[31:18] Stride */
u32 LSB_Timestamp; /**< LSB of the Timestamp */
u32 MSB_Timestamp; /**< MSB of the Timestamp */
u32 ADDR_EXT; /**< [15:0] Next descriptor
extenstion
[31:16] SRC address extemsion */
u32 NEXT_DESR; /**< Address of next descriptor */
u32 SRC_ADDR; /**< Source Address */
u32 ADDR_EXT_23; /**< [15:0] Address extension for SRC
Address2
[31:16] Address extension for
SRC Address 3 */
u32 ADDR_EXT_45; /**< [15:0] Address extension for SRC
Address4
[31:16] Address extension for
SRC Address 5 */
u32 SRC_ADDR2; /**< Source address of 2nd page */
u32 SRC_ADDR3; /**< Source address of 3rd page */
u32 SRC_ADDR4; /**< Source address of 4th page */
u32 SRC_ADDR5; /**< Source address of 5th page */
u32 CRC; /**< Reserved */
} XDpDma_Descriptor __attribute__ ((aligned(XDPDMA_DESCRIPTOR_ALIGN)));
/**
* This typedef contains configuration information for the DPDMA.
*/
typedef struct {
u16 DeviceId; /**< Device ID */
u32 BaseAddr; /**< Base Address */
} XDpDma_Config;
/**
* The following data structure enumerates the types of
* DPDMA channels
*/
typedef enum {
VideoChan,
GraphicsChan,
AudioChan0,
AudioChan1,
} XDpDma_ChannelType;
/**
* This typedef lists the channel status.
*/
typedef enum {
XDPDMA_DISABLE,
XDPDMA_ENABLE,
XDPDMA_IDLE,
XDPDMA_PAUSE
} XDpDma_ChannelState;
/**
* This typedef is the information needed to transfer video info.
*/
typedef struct {
u64 Address;
u32 Size;
u32 Stride;
u32 LineSize;
} XDpDma_FrameBuffer;
/**
* This typedef is the information needed to transfer audio info.
*/
typedef struct {
u64 Address;
u64 Size;
} XDpDma_AudioBuffer;
/**
* This typedef defines the Video/Graphics Channel attributes.
*/
typedef struct {
XDpDma_Descriptor Descriptor0;
XDpDma_Descriptor Descriptor1;
XDpDma_Descriptor *Current;
} XDpDma_Channel;
/**
* This typedef defines the Video Channel attributes.
*/
typedef struct {
XDpDma_Channel Channel[3];
u8 TriggerStatus;
u8 AVBufEn;
XAVBuf_VideoAttribute *VideoInfo;
XDpDma_FrameBuffer *FrameBuffer[3];
} XDpDma_VideoChannel;
/**
* This typedef defines the Graphics Channel attributes.
*/
typedef struct {
XDpDma_Channel Channel;
u8 TriggerStatus;
u8 AVBufEn;
XAVBuf_VideoAttribute *VideoInfo;
XDpDma_FrameBuffer *FrameBuffer;
} XDpDma_GfxChannel;
/**
* This typedef defines the Audio Channel attributes.
*/
typedef struct {
XDpDma_Descriptor Descriptor0, Descriptor1, Descriptor2;
XDpDma_Descriptor Descriptor3, Descriptor4, Descriptor5;
XDpDma_Descriptor Descriptor6, Descriptor7;
XDpDma_Descriptor *Current;
u8 TriggerStatus;
XDpDma_AudioBuffer *Buffer;
u8 Used;
} XDpDma_AudioChannel;
/*************************************************************************/
/**
* This callback type represents the handler for a DPDMA VSync interrupt.
*
* @param InstancePtr is a pointer to the XDpDma instance.
*
* @note None.
*
**************************************************************************/
typedef void (*XDpDma_VSyncInterruptHandler)(void *InstancePtr);
/*************************************************************************/
/**
* This callback type represents the handler for a DPDMA Done interrupt.
*
* @param InstancePtr is a pointer to the XDpDma instance.
*
* @note None.
*
**************************************************************************/
typedef void (*XDpDma_DoneInterruptHandler)(void *InstancePtr);
/**
* The XDpDma driver instance data representing the DPDMA operation.
*/
typedef struct {
XDpDma_Config Config;
XDpDma_VideoChannel Video;
XDpDma_GfxChannel Gfx;
XDpDma_AudioChannel Audio[2];
XVidC_VideoTiming *Timing;
u8 QOS;
XDpDma_VSyncInterruptHandler VSyncHandler;
void * VSyncInterruptHandler;
XDpDma_DoneInterruptHandler DoneHandler;
void * DoneInterruptHandler;
} XDpDma;
void XDpDma_CfgInitialize(XDpDma *InstancePtr, XDpDma_Config *CfgPtr);
XDpDma_Config *XDpDma_LookupConfig(u16 DeviceId);
int XDpDma_SetChannelState(XDpDma *InstancePtr, XDpDma_ChannelType Channel,
XDpDma_ChannelState ChannelState);
void XDpDma_SetQOS(XDpDma *InstancePtr, u8 QOS);
void XDpDma_SetupChannel(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
int XDpDma_SetVideoFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format);
int XDpDma_SetGraphicsFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format);
void XDpDma_SetVideoTiming(XDpDma *InstancePtr, XVidC_VideoTiming *Timing);
int XDpDma_Trigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
int XDpDma_ReTrigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
void XDpDma_InterruptEnable(XDpDma *InstancePtr, u32 Mask);
void XDpDma_InterruptHandler(XDpDma *InstancePtr);
void XDpDma_VSyncHandler(XDpDma *InstancePtr);
void XDpDma_DoneHandler(XDpDma *InstancePtr);
void XDpDma_InitVideoDescriptor(XDpDma_Descriptor *CurrDesc,
XDpDma_FrameBuffer *FrameBuffer);
void XDpDma_DisplayVideoFrameBuffer(XDpDma *InstancePtr,
XDpDma_FrameBuffer *Plane1,
XDpDma_FrameBuffer *Plane2,
XDpDma_FrameBuffer *Plane3);
void XDpDma_DisplayGfxFrameBuffer(XDpDma *InstancePtr,
XDpDma_FrameBuffer *Plane);
void XDpDma_InitAudioDescriptor(XDpDma_AudioChannel *Channel,
XDpDma_AudioBuffer *AudioBuffer);
int XDpDma_PlayAudio(XDpDma *InstancePtr, XDpDma_AudioBuffer *Buffer,
u8 ChannelNum);
#ifdef __cplusplus
}
#endif
#endif /* _XDPDMA_H_ */

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/******************************************************************************
*
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xemacps.h
* @addtogroup emacps_v3_7
* @{
* @details
*
* The Xilinx Embedded Processor Block Ethernet driver.
*
* For a full description of XEMACPS features, please see the hardware spec.
* This driver supports the following features:
* - Memory mapped access to host interface registers
* - Statistics counter registers for RMON/MIB
* - API for interrupt driven frame transfers for hardware configured DMA
* - Virtual memory support
* - Unicast, broadcast, and multicast receive address filtering
* - Full and half duplex operation
* - Automatic PAD & FCS insertion and stripping
* - Flow control
* - Support up to four 48bit addresses
* - Address checking for four specific 48bit addresses
* - VLAN frame support
* - Pause frame support
* - Large frame support up to 1536 bytes
* - Checksum offload
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the XEmacPs. The driver handles transmission and reception
* of Ethernet frames, as well as configuration and control. No pre or post
* processing of frame data is performed. The driver does not validate the
* contents of an incoming frame in addition to what has already occurred in
* hardware.
* A single device driver can support multiple devices even when those devices
* have significantly different configurations.
*
* <b>Initialization & Configuration</b>
*
* The XEmacPs_Config structure is used by the driver to configure itself.
* This configuration structure is typically created by the tool-chain based
* on hardware build properties.
*
* The driver instance can be initialized in
*
* - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* The device supports DMA only as current development plan. No FIFO mode is
* supported. The driver expects to start the DMA channels and expects that
* the user has set up the buffer descriptor lists.
*
* <b>Interrupts and Asynchronous Callbacks</b>
*
* The driver has no dependencies on the interrupt controller. When an
* interrupt occurs, the handler will perform a small amount of
* housekeeping work, determine the source of the interrupt, and call the
* appropriate callback function. All callbacks are registered by the user
* level application.
*
* <b>Virtual Memory</b>
*
* All virtual to physical memory mappings must occur prior to accessing the
* driver API.
*
* For DMA transactions, user buffers supplied to the driver must be in terms
* of their physical address.
*
* <b>DMA</b>
*
* The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
* These BDs are typically chained together into a list the hardware follows
* when transferring data in and out of the packet buffers. Each BD describes
* a memory region containing either a full or partial Ethernet packet.
*
* Interrupt coalescing is not suppoted from this built-in DMA engine.
*
* This API requires the user to understand how the DMA operates. The
* following paragraphs provide some explanation, but the user is encouraged
* to read documentation in xemacps_bdring.h as well as study example code
* that accompanies this driver.
*
* The API is designed to get BDs to and from the DMA engine in the most
* efficient means possible. The first step is to establish a memory region
* to contain all BDs for a specific channel. This is done with
* XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
* follow as BDs are processed. The ring will consist of a user defined number
* of BDs which will all be partially initialized. For example on the transmit
* channel, the driver will initialize all BDs' so that they are configured
* for transmit. The more fields that can be permanently setup at
* initialization, then the fewer accesses will be needed to each BD while
* the DMA engine is in operation resulting in better throughput and CPU
* utilization. The best case initialization would require the user to set
* only a frame buffer address and length prior to submitting the BD to the
* engine.
*
* BDs move through the engine with the help of functions
* XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
* and XEmacPs_BdRingFree().
* All these functions handle BDs that are in place. That is, there are no
* copies of BDs kept anywhere and any BD the user interacts with is an actual
* BD from the same ring hardware accesses.
*
* BDs in the ring go through a series of states as follows:
* 1. Idle. The driver controls BDs in this state.
* 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
* reserve BD(s). Once allocated, the user may setup the BD(s) with
* frame buffer address, length, and other attributes. The user controls
* BDs in this state.
* 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
* in this state are either waiting to be processed by hardware, are in
* process, or have been processed. The DMA engine controls BDs in this
* state.
* 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
* user. Once retrieved, the user can examine each BD for the outcome of
* the DMA transfer. The user controls BDs in this state. After examining
* the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
* into state 1.
*
* Each of the four BD accessor functions operate on a set of BDs. A set is
* defined as a segment of the BD ring consisting of one or more BDs. The user
* views the set as a pointer to the first BD along with the number of BDs for
* that set. The set can be navigated by using macros XEmacPs_BdNext(). The
* user must exercise extreme caution when changing BDs in a set as there is
* nothing to prevent doing a mBdNext past the end of the set and modifying a
* BD out of bounds.
*
* XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
* XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
* tandem. The same BD set retrieved with BdRingAlloc should be the same one
* provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
* BdRIngFree.
*
* <b>Alignment & Data Cache Restrictions</b>
*
* Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
* aligned. Please reference xemacps_bd.h for cache related macros.
*
* DMA Tx:
*
* - If frame buffers exist in cached memory, then they must be flushed
* prior to committing them to hardware.
*
* DMA Rx:
*
* - If frame buffers exist in cached memory, then the cache must be
* invalidated for the memory region containing the frame prior to data
* access
*
* Both cache invalidate/flush are taken care of in driver code.
*
* <b>Buffer Copying</b>
*
* The driver is designed for a zero-copy buffer scheme. That is, the driver
* will not copy buffers. This avoids potential throughput bottlenecks within
* the driver. If byte copying is required, then the transfer will take longer
* to complete.
*
* <b>Checksum Offloading</b>
*
* The Embedded Processor Block Ethernet can be configured to perform IP, TCP
* and UDP checksum offloading in both receive and transmit directions.
*
* IP packets contain a 16-bit checksum field, which is the 16-bit 1s
* complement of the 1s complement sum of all 16-bit words in the header.
* TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
* 1s complement of the 1s complement sum of all 16-bit words in the header,
* the data and a conceptual pseudo header.
*
* To calculate these checksums in software requires each byte of the packet
* to be read. For TCP and UDP this can use a large amount of processing power.
* Offloading the checksum calculation to hardware can result in significant
* performance improvements.
*
* The transmit checksum offload is only available to use DMA in packet buffer
* mode. This is because the complete frame to be transmitted must be read
* into the packet buffer memory before the checksum can be calculated and
* written to the header at the beginning of the frame.
*
* For IP, TCP or UDP receive checksum offload to be useful, the operating
* system containing the protocol stack must be aware that this offload is
* available so that it can make use of the fact that the hardware has verified
* the checksum.
*
* When receive checksum offloading is enabled in the hardware, the IP header
* checksum is checked, where the packet meets the following criteria:
*
* 1. If present, the VLAN header must be four octets long and the CFI bit
* must not be set.
* 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
* encoding.
* 3. IP v4 packet.
* 4. IP header is of a valid length.
* 5. Good IP header checksum.
* 6. No IP fragmentation.
* 7. TCP or UDP packet.
*
* When an IP, TCP or UDP frame is received, the receive buffer descriptor
* gives an indication if the hardware was able to verify the checksums.
* There is also an indication if the frame had SNAP encapsulation. These
* indication bits will replace the type ID match indication bits when the
* receive checksum offload is enabled.
*
* If any of the checksums are verified incorrect by the hardware, the packet
* is discarded and the appropriate statistics counter incremented.
*
* <b>PHY Interfaces</b>
*
* RGMII 1.3 is the only interface supported.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on
* parameters. Asserts can be turned off on a system-wide basis by defining,
* at compile time, the NDEBUG identifier. By default, asserts are turned on
* and it is recommended that users leave asserts on during development. For
* deployment use -DNDEBUG compiler switch to remove assert code.
*
* @note
*
* Xilinx drivers are typically composed of two parts, one is the driver
* and the other is the adapter. The driver is independent of OS and processor
* and is intended to be highly portable. The adapter is OS-specific and
* facilitates communication between the driver and an OS.
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, or cache
* control must be satisfied bythe layer above this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Earlier it was checking for
* "BdLimit"(passed argument) number of BDs for finding out
* which BDs are successfully processed. Now one more check
* is added. It looks for BDs till the current BD pointer
* reaches HwTail. By doing this processing time is saved.
* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Now start of packet is
* searched for returning the number of BDs processed.
* 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
* registers. Added a new API to set the bust length.
* Added some new hash-defines.
* 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
* Rx errors. Under heavy Rx traffic, there will be a large
* number of errors related to receive buffer not available.
* Because of a HW bug (SI #692601), under such heavy errors,
* the Rx data path can become unresponsive. To reduce the
* probabilities for hitting this HW bug, the SW writes to
* bit 18 to flush a packet from Rx DPRAM immediately. The
* changes for it are done in the function
* XEmacPs_IntrHandler.
* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
* removed. It is expected that all BDs are allocated in
* from uncached area.
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* Made changes in example file xemacps_example.h to fix compilation
* issues with iarcc compiler.
* 2.0 adk 10/12/13 Updated as per the New Tcl API's
* 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
* 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
* address in xparameters.h when GMII to RGMII converter
* is present in hw.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
* changes.
* 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
* 1000BASE-X mode export proper values to the xparameters.h
* file. Changes are made in the driver tcl file.
* 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
* configured with PCS/PMA Core. Changes are made in the
* test app tcl(CR:827686).
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
* Remove "used bit set" from TX error interrupt masks.
* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
* there is no error. CR# 869403
* 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
* 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Modified text file in examples folder for doxygen
* generation.
* ms 04/05/17 Added tabspace for return statements in functions of
* xemacps_ieee1588_example.c for proper documentation
* while generating doxygen.
* 3.5 hk 08/14/17 Update cache coherency information of the interface in
* its config structure.
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
* changed to volatile.
* Add API XEmacPs_BdRingPtrReset() to reset pointers
*
* </pre>
*
****************************************************************************/
#ifndef XEMACPS_H /* prevent circular inclusions */
#define XEMACPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xemacps_hw.h"
#include "xemacps_bd.h"
#include "xemacps_bdring.h"
/************************** Constant Definitions ****************************/
/*
* Device information
*/
#define XEMACPS_DEVICE_NAME "xemacps"
#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
/** @name Configuration options
*
* Device configuration options. See the XEmacPs_SetOptions(),
* XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
* use options.
*
* The default state of the options are noted and are what the device and
* driver will be set to after calling XEmacPs_Reset() or
* XEmacPs_Initialize().
*
* @{
*/
#define XEMACPS_PROMISC_OPTION 0x00000001U
/**< Accept all incoming packets.
* This option defaults to disabled (cleared) */
#define XEMACPS_FRAME1536_OPTION 0x00000002U
/**< Frame larger than 1516 support for Tx & Rx.
* This option defaults to disabled (cleared) */
#define XEMACPS_VLAN_OPTION 0x00000004U
/**< VLAN Rx & Tx frame support.
* This option defaults to disabled (cleared) */
#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
/**< Enable recognition of flow control frames on Rx
* This option defaults to enabled (set) */
#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
* stripped.
* This option defaults to enabled (set) */
#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
/**< Generate FCS field and add PAD automatically for outgoing frames.
* This option defaults to disabled (cleared) */
#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
/**< Enable Length/Type error checking for incoming frames. When this option is
* set, the MAC will filter frames that have a mismatched type/length field
* and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
* types of frames are encountered. When this option is cleared, the MAC will
* allow these types of frames to be received.
*
* This option defaults to disabled (cleared) */
#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
/**< Enable the transmitter.
* This option defaults to enabled (set) */
#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
/**< Enable the receiver
* This option defaults to enabled (set) */
#define XEMACPS_BROADCAST_OPTION 0x00000400U
/**< Allow reception of the broadcast address
* This option defaults to enabled (set) */
#define XEMACPS_MULTICAST_OPTION 0x00000800U
/**< Allows reception of multicast addresses programmed into hash
* This option defaults to disabled (clear) */
#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
/**< Enable the RX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
/**< Enable the TX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
#define XEMACPS_DEFAULT_OPTIONS \
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
(u32)XEMACPS_FCS_STRIP_OPTION | \
(u32)XEMACPS_BROADCAST_OPTION | \
(u32)XEMACPS_LENTYPE_ERR_OPTION | \
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
/**< Default options set when device is initialized or reset */
/*@}*/
/** @name Callback identifiers
*
* These constants are used as parameters to XEmacPs_SetHandler()
* @{
*/
#define XEMACPS_HANDLER_DMASEND 1U
#define XEMACPS_HANDLER_DMARECV 2U
#define XEMACPS_HANDLER_ERROR 3U
/*@}*/
/* Constants to determine the configuration of the hardware device. They are
* used to allow the driver to verify it can operate with the hardware.
*/
#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
/* The next few constants help upper layers determine the size of memory
* pools used for Ethernet buffers and descriptor lists.
*/
#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
/* DMACR Bust length hash defines */
#define XEMACPS_SINGLE_BURST 0x00000001
#define XEMACPS_4BYTE_BURST 0x00000004
#define XEMACPS_8BYTE_BURST 0x00000008
#define XEMACPS_16BYTE_BURST 0x00000010
/**************************** Type Definitions ******************************/
/** @name Typedefs for callback functions
*
* These callbacks are invoked in interrupt context.
* @{
*/
/**
* Callback invoked when frame(s) have been sent or received in interrupt
* driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
*
* @param CallBackRef is user data assigned when the callback was set.
*
* @note
* See xemacps_hw.h for bitmasks definitions and the device hardware spec for
* further information on their meaning.
*
*/
typedef void (*XEmacPs_Handler) (void *CallBackRef);
/**
* Callback when an asynchronous error occurs. To set this callback, invoke
* XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
* paramter.
*
* @param CallBackRef is user data assigned when the callback was set.
* @param Direction defines either receive or transmit error(s) has occurred.
* @param ErrorWord definition varies with Direction
*
*/
typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
u32 ErrorWord);
/*@}*/
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
* describes whether Cache Coherent or not */
} XEmacPs_Config;
/**
* The XEmacPs driver instance data. The user is required to allocate a
* structure of this type for every XEmacPs device in the system. A pointer
* to a structure of this type is then passed to the driver API functions.
*/
typedef struct XEmacPs_Instance {
XEmacPs_Config Config; /* Hardware configuration */
u32 IsStarted; /* Device is currently started */
u32 IsReady; /* Device is initialized and ready */
u32 Options; /* Current options word */
XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
XEmacPs_BdRing RxBdRing; /* Receive BD ring */
XEmacPs_Handler SendHandler;
XEmacPs_Handler RecvHandler;
void *SendRef;
void *RecvRef;
XEmacPs_ErrHandler ErrorHandler;
void *ErrorRef;
u32 Version;
u32 RxBufMask;
u32 MaxMtuSize;
u32 MaxFrameSize;
u32 MaxVlanFrameSize;
} XEmacPs;
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
* Retrieve the Tx ring object. This object can be used in the various Ring
* API functions.
*
* @param InstancePtr is the DMA channel to operate on.
*
* @return TxBdRing attribute
*
* @note
* C-style signature:
* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
/****************************************************************************/
/**
* Retrieve the Rx ring object. This object can be used in the various Ring
* API functions.
*
* @param InstancePtr is the DMA channel to operate on.
*
* @return RxBdRing attribute
*
* @note
* C-style signature:
* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntEnable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntDisable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* This macro triggers trasmit circuit to send data currently in TX buffer(s).
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* @note
*
* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_Transmit(InstancePtr) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
/****************************************************************************/
/**
*
* This macro determines if the device is configured with checksum offloading
* on the receive channel
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with checksum offloading, or
* FALSE otherwise.
*
* @note
*
* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_IsRxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro determines if the device is configured with checksum offloading
* on the transmit channel
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with checksum offloading, or
* FALSE otherwise.
*
* @note
*
* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_IsTxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
? TRUE : FALSE)
/************************** Function Prototypes *****************************/
/*
* Initialization functions in xemacps.c
*/
LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
UINTPTR EffectiveAddress);
void XEmacPs_Start(XEmacPs *InstancePtr);
void XEmacPs_Stop(XEmacPs *InstancePtr);
void XEmacPs_Reset(XEmacPs *InstancePtr);
void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
u16 Direction);
/*
* Lookup configuration in xemacps_sinit.c
*/
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
/*
* Interrupt-related functions in xemacps_intr.c
* DMA only and FIFO is not supported. This DMA does not support coalescing.
*/
LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPointer, void *CallBackRef);
void XEmacPs_IntrHandler(void *XEmacPsPtr);
/*
* MAC configuration/control functions in XEmacPs_control.c
*/
LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_ClearHash(XEmacPs *InstancePtr);
void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
XEmacPs_MdcDiv Divisor);
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 *PhyDataPtr);
LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 PhyData);
LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

804
freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps_bd.h Normal file
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@ -0,0 +1,804 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_bd.h
* @addtogroup emacps_v3_7
* @{
*
* This header provides operations to manage buffer descriptors in support
* of scatter-gather DMA.
*
* The API exported by this header defines abstracted macros that allow the
* user to read/write specific BD fields.
*
* <b>Buffer Descriptors</b>
*
* A buffer descriptor (BD) defines a DMA transaction. The macros defined by
* this header file allow access to most fields within a BD to tailor a DMA
* transaction according to user and hardware requirements. See the hardware
* IP DMA spec for more information on BD fields and how they affect transfers.
*
* The XEmacPs_Bd structure defines a BD. The organization of this structure
* is driven mainly by the hardware for use in scatter-gather DMA transfers.
*
* <b>Performance</b>
*
* Limiting I/O to BDs can improve overall performance of the DMA channel.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
* and 64-bit changes.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
* 3.2 hk 11/18/15 Change BD typedef and number of words.
*
* </pre>
*
* ***************************************************************************
*/
#ifndef XEMACPS_BD_H /* prevent circular inclusions */
#define XEMACPS_BD_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include <string.h>
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
#ifdef __aarch64__
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
#define XEMACPS_BD_NUM_WORDS 4U
#else
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
#define XEMACPS_BD_NUM_WORDS 2U
#endif
/**
* The XEmacPs_Bd is the type for buffer descriptors (BDs).
*/
typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Zero out BD fields
*
* @param BdPtr is the BD pointer to operate on
*
* @return Nothing
*
* @note
* C-style signature:
* void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClear(BdPtr) \
memset((BdPtr), 0, sizeof(XEmacPs_Bd))
/****************************************************************************/
/**
*
* Read the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to read
* @param Offset is the word offset to be read
*
* @return The 32-bit value of the field
*
* @note
* C-style signature:
* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
*
*****************************************************************************/
#define XEmacPs_BdRead(BaseAddress, Offset) \
(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
/****************************************************************************/
/**
*
* Write the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to write
* @param Offset is the word offset to be written
* @param Data is the 32-bit value to write to the field
*
* @return None.
*
* @note
* C-style signature:
* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
*
*****************************************************************************/
#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
(*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
/*****************************************************************************/
/**
* Set the BD's Address field (word 0).
*
* @param BdPtr is the BD pointer to operate on
* @param Addr is the value to write to BD's status field.
*
* @note :
*
* C-style signature:
* void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#ifdef __aarch64__
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
(u32)((Addr) & ULONG64_LO_MASK)); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
#endif
/*****************************************************************************/
/**
* Set the BD's Address field (word 0).
*
* @param BdPtr is the BD pointer to operate on
* @param Addr is the value to write to BD's status field.
*
* @note : Due to some bits are mixed within recevie BD's address field,
* read-modify-write is performed.
*
* C-style signature:
* void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#ifdef __aarch64__
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
#endif
/*****************************************************************************/
/**
* Set the BD's Status field (word 1).
*
* @param BdPtr is the BD pointer to operate on
* @param Data is the value to write to BD's status field.
*
* @note
* C-style signature:
* void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
*
*****************************************************************************/
#define XEmacPs_BdSetStatus(BdPtr, Data) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
/*****************************************************************************/
/**
* Retrieve the BD's Packet DMA transfer status word (word 1).
*
* @param BdPtr is the BD pointer to operate on
*
* @return Status word
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
*
* Due to the BD bit layout differences in transmit and receive. User's
* caution is required.
*****************************************************************************/
#define XEmacPs_BdGetStatus(BdPtr) \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
/*****************************************************************************/
/**
* Get the address (bits 0..31) of the BD's buffer address (word 0)
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#ifdef __aarch64__
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
#else
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
#endif
/*****************************************************************************/
/**
* Set transfer length in bytes for the given BD. The length must be set each
* time a BD is submitted to hardware.
*
* @param BdPtr is the BD pointer to operate on
* @param LenBytes is the number of bytes to transfer.
*
* @note
* C-style signature:
* void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
*
*****************************************************************************/
#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
/*****************************************************************************/
/**
* Set transfer length in bytes for the given BD. The length must be set each
* time a BD is submitted to hardware.
*
* @param BdPtr is the BD pointer to operate on
* @param LenBytes is the number of bytes to transfer.
*
* @note
* C-style signature:
* void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
*
*****************************************************************************/
#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
/*****************************************************************************/
/**
* Retrieve the BD length field.
*
* For Tx channels, the returned value is the same as that written with
* XEmacPs_BdSetLength().
*
* For Rx channels, the returned value is the size of the received packet.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Length field processed by hardware or set by
* XEmacPs_BdSetLength().
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
* XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
*
*****************************************************************************/
#define XEmacPs_BdGetLength(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_LEN_MASK)
/*****************************************************************************/
/**
* Retrieve the RX frame size.
*
* The returned value is the size of the received packet.
* This API supports jumbo frame sizes if enabled.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Length field processed by hardware or set by
* XEmacPs_BdSetLength().
*
* @note
* C-style signature:
* UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
* RxBufMask is dependent on whether jumbo is enabled or not.
*
*****************************************************************************/
#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
(InstancePtr)->RxBufMask)
/*****************************************************************************/
/**
* Test whether the given BD has been marked as the last BD of a packet.
*
* @param BdPtr is the BD pointer to operate on
*
* @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsLast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Tell the DMA engine that the given transmit BD marks the end of the current
* packet to be processed.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetLast(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_LAST_MASK))
/*****************************************************************************/
/**
* Tell the DMA engine that the current packet does not end with the given
* BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearLast(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LAST_MASK))
/*****************************************************************************/
/**
* Set this bit to mark the last descriptor in the receive buffer descriptor
* list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
/*#define XEmacPs_BdSetRxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
XEMACPS_RXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
* Determine the wrap bit of the receive BD which indicates end of the
* BD list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Sets this bit to mark the last descriptor in the transmit buffer
* descriptor list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
/*#define XEmacPs_BdSetTxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
* Determine the wrap bit of the transmit BD which indicates end of the
* BD list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/*
* Must clear this bit to enable the MAC to write data to the receive
* buffer. Hardware sets this bit once it has successfully written a frame to
* memory. Once set, software has to clear the bit before the buffer can be
* used again. This macro clear the new bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearRxNew(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_NEW_MASK))
/*****************************************************************************/
/**
* Determine the new bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxNew(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Software sets this bit to disable the buffer to be read by the hardware.
* Hardware sets this bit for the first buffer of a frame once it has been
* successfully transmitted. This macro sets this bit of transmit BD to avoid
* confusion.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxUsed(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_USED_MASK))
/*****************************************************************************/
/**
* Software clears this bit to enable the buffer to be read by the hardware.
* Hardware sets this bit for the first buffer of a frame once it has been
* successfully transmitted. This macro clears this bit of transmit BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearTxUsed(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_USED_MASK))
/*****************************************************************************/
/**
* Determine the used bit of the transmit BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUsed(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to too many retries.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxRetry(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to data can not be
* feteched in time or buffers are exhausted.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUrun(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to buffer is exhausted
* mid-frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxExh(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Sets this bit, no CRC will be appended to the current frame. This control
* bit must be set for the first buffer in a frame and will be ignored for
* the subsequent buffers of a frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* This bit must be clear when using the transmit checksum generation offload,
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxNoCRC(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_NOCRC_MASK))
/*****************************************************************************/
/**
* Clear this bit, CRC will be appended to the current frame. This control
* bit must be set for the first buffer in a frame and will be ignored for
* the subsequent buffers of a frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* This bit must be clear when using the transmit checksum generation offload,
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearTxNoCRC(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_NOCRC_MASK))
/*****************************************************************************/
/**
* Determine the broadcast bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxBcast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the multicast hash bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxMultiHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the unicast hash bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxUniHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame is a VLAN Tagged frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxVlan(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame has Type ID of 8100h and null VLAN
* identifier(Priority tag).
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxPri(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame's Concatenation Format Indicator (CFI) of
* the frames VLANTCI field was set.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxCFI(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the End Of Frame (EOF) bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxEOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the Start Of Frame (SOF) bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxSOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_bdring.h
* @addtogroup emacps_v3_7
* @{
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
* DMA functionalities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
* changed to volatile.
*
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
#define XEMACPS_BDRING_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/**************************** Type Definitions *******************************/
/** This is an internal structure used to maintain the DMA list */
typedef struct {
UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
u32 Length; /**< Total size of ring in bytes */
u32 RunState; /**< Flag to indicate DMA is started */
u32 Separation; /**< Number of bytes between the starting address
of adjacent BDs */
XEmacPs_Bd *FreeHead;
/**< First BD in the free group */
XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
XEmacPs_Bd *HwHead; /**< First BD in the work group */
XEmacPs_Bd *HwTail; /**< Last BD in the work group */
XEmacPs_Bd *PostHead;
/**< First BD in the post-work group */
XEmacPs_Bd *BdaRestart;
/**< BDA to load when channel is started */
volatile u32 HwCnt; /**< Number of BDs in work group */
u32 PreCnt; /**< Number of BDs in pre-work group */
u32 FreeCnt; /**< Number of allocatable BDs in the free group */
u32 PostCnt; /**< Number of BDs in post-work group */
u32 AllCnt; /**< Total Number of BDs for channel */
} XEmacPs_BdRing;
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many BDs will fit
* in a BD list within the given memory constraints.
*
* The results of this macro can be provided to XEmacPs_BdRingCreate().
*
* @param Alignment specifies what byte alignment the BDs must fall on and
* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
* @param Bytes is the number of bytes to be used to store BDs.
*
* @return Number of BDs that can fit in the given memory area
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
*
******************************************************************************/
#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
(u32)((Bytes) / (sizeof(XEmacPs_Bd)))
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many bytes of memory
* is required to contain a given number of BDs at a given alignment.
*
* @param Alignment specifies what byte alignment the BDs must fall on. This
* parameter must be a power of 2 to get an accurate calculation (32, 64,
* 128,...)
* @param NumBd is the number of BDs to calculate memory size requirements for
*
* @return The number of bytes of memory required to create a BD list with the
* given memory constraints.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
*
******************************************************************************/
#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
(u32)(sizeof(XEmacPs_Bd) * (NumBd))
/****************************************************************************/
/**
* Return the total number of BDs allocated by this channel with
* XEmacPs_BdRingCreate().
*
* @param RingPtr is the DMA channel to operate on.
*
* @return The total number of BDs allocated for this channel.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
/****************************************************************************/
/**
* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
* processing.
*
* @param RingPtr is the DMA channel to operate on.
*
* @return The number of BDs currently allocatable.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
/****************************************************************************/
/**
* Return the next BD from BdPtr in a list.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the BD to operate on.
*
* @return The next BD in the list relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
* XEmacPs_Bd *BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
(((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
(XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
(XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
/****************************************************************************/
/**
* Return the previous BD from BdPtr in the list.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the BD to operate on
*
* @return The previous BD in the list relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
* XEmacPs_Bd *BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
(((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
(XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
(XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
/************************** Function Prototypes ******************************/
/*
* Scatter gather DMA related functions in xemacps_bdring.c
*/
LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
u8 Direction);
LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macros */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_hw.h
* @addtogroup emacps_v3_7
* @{
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
* High-level driver functions are defined in xemacps.h.
*
* @note
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release.
* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 03/18/15 Added support for jumbo frames.
* Remove "used bit set" from TX error interrupt masks.
* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_HW_H /* prevent circular inclusions */
#define XEMACPS_HW_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
supported */
#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
#ifdef __aarch64__
#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
on the local bus */
#else
#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
on the local bus */
#endif
#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
options that impose alignment
restrictions on the buffer data on
the local bus */
/** @name Direction identifiers
*
* These are used by several functions and callbacks that need
* to specify whether an operation specifies a send or receive channel.
* @{
*/
#define XEMACPS_SEND 1U /**< send direction */
#define XEMACPS_RECV 2U /**< receive direction */
/*@}*/
/** @name MDC clock division
* currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
* @{
*/
typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
} XEmacPs_MdcDiv;
/*@}*/
#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
bytes, 64, 128, ... 10240 */
#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
unit, this is HW setup */
#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
/* Register offset definitions. Unless otherwise noted, register access is
* 32 bit. Names are self explained here.
*/
#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
reg */
#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
reg */
#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
transmitted counter */
#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
Frames counter*/
#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
Frame counter */
#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
Counter */
#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
Transmitted counter */
#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
Frames Transmitted
counter */
#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
Frames Transmitted
counter*/
#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
Frames transmitted
counter */
#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
Frames transmitted
counter */
#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
Frames transmitted
counter */
#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
1519 byte Frames
transmitted counter */
#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
counter */
#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
Counter */
#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
Counter */
#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
Counter */
#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
Counter */
#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
Frame Counter */
#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
Error Counter */
#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
Low */
#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
High */
#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
Received Counter */
#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
Frames Received Counter */
#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
Frames Received Counter */
#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
Received Counter */
#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
Received Counter */
#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
Frames Received Counter */
#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
Frames Received Counter */
#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
Frames Received Counter */
#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
Frames Received Counter */
#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
Frames Received Counter */
#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
Frames Received Counter */
#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
Counter */
#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
Counter */
#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
Counter */
#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
Error Counter */
#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
Counter */
#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
Counter */
#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
Counter */
#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
Counter */
#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
Counter */
#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
offset, for clearing */
#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
adjustment counter */
#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
increment counter */
#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
counter */
#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
nanosecond counter */
#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
counter */
#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
nanosecond counter */
#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
second counter */
#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
nanosecond counter */
#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
second counter */
#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
nanosecond counter */
#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
reg */
#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
reg */
#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
reg */
#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
reg */
#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
reg */
#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
reg */
#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
reg */
#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
reg */
/* Define some bit positions for registers. */
/** @name network control register bit definitions
* @{
*/
#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
Rx SRAM */
#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
pause frame */
#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
after current frame */
#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
stat counters */
#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
registers */
#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
registers */
#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
/*@}*/
/** @name network configuration register bit definitions
* @{
*/
#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
non-standard preamble */
#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
FCS error */
#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
offload */
#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
Frames to memory */
#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
received frames */
#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
/**< RX length error discard */
#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
/**< External address match enable */
#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
frames reception */
#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
frames */
#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
frames */
#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
broadcast frames */
#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
frames */
#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
/*@}*/
/** @name network status register bit definitaions
* @{
*/
#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
/*@}*/
/** @name MAC address register word 1 mask
* @{
*/
#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
bit[31:0] are in BOTTOM */
/*@}*/
/** @name DMA control register bit definitions
* @{
*/
#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
size */
#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
size */
#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
checksum offload */
#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
/*@}*/
/** @name transmit status register bit definitions
* @{
*/
#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
mid frame */
#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
(u32)XEMACPS_TXSR_URUN_MASK | \
(u32)XEMACPS_TXSR_BUFEXH_MASK | \
(u32)XEMACPS_TXSR_RXOVR_MASK | \
(u32)XEMACPS_TXSR_FRAMERX_MASK | \
(u32)XEMACPS_TXSR_USEDREAD_MASK)
/*@}*/
/**
* @name receive status register bit definitions
* @{
*/
#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
(u32)XEMACPS_RXSR_RXOVR_MASK | \
(u32)XEMACPS_RXSR_BUFFNA_MASK)
/*@}*/
/**
* @name Interrupt Q1 status register bit definitions
* @{
*/
#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
(u32)XEMACPS_INTQ1SR_TXERR_MASK)
/*@}*/
/**
* @name interrupts bit definitions
* Bits definitions are same in XEMACPS_ISR_OFFSET,
* XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
* @{
*/
#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Psync transmitted */
#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req
transmitted */
#define XEMACPS_IXR_PTPSTX_MASK 0x00800000U /**< PTP Sync transmitted */
#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000U /**< PTP Delay_req transmitted
*/
#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000U /**< PTP Psync received */
#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000U /**< PTP Pdelay_req received */
#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync received */
#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req received */
#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
zero */
#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
no buffers*/
#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
(u32)XEMACPS_IXR_RETRY_MASK | \
(u32)XEMACPS_IXR_URUN_MASK)
#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
(u32)XEMACPS_IXR_RXUSED_MASK | \
(u32)XEMACPS_IXR_RXOVR_MASK)
/*@}*/
/** @name PHY Maintenance bit definitions
* @{
*/
#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
/*@}*/
/* Transmit buffer descriptor status words offset
* @{
*/
#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
/*
* @}
*/
/* Transmit buffer descriptor status words bit positions.
* Transmit buffer descriptor consists of two 32-bit registers,
* the first - word0 contains a 32-bit address pointing to the location of
* the transmit data.
* The following register - word1, consists of various information to control
* the XEmacPs transmit process. After transmit, this is updated with status
* information, whether the frame was transmitted OK or why it had failed.
* @{
*/
#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
/*
* @}
*/
/* Receive buffer descriptor status words bit positions.
* Receive buffer descriptor consists of two 32-bit registers,
* the first - word0 contains a 32-bit word aligned address pointing to the
* address of the buffer. The lower two bits make up the wrap bit indicating
* the last descriptor and the ownership bit to indicate it has been used by
* the XEmacPs.
* The following register - word1, contains status information regarding why
* the frame was received (the filter match condition) as well as other
* useful info.
* @{
*/
#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
matched */
#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
/*
* @}
*/
/*
* Define appropriate I/O access method to memory mapped I/O or other
* interface if necessary.
*/
#define XEmacPs_In32 Xil_In32
#define XEmacPs_Out32 Xil_Out32
/****************************************************************************/
/**
*
* Read the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* Write the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
* u32 Data)
*
*****************************************************************************/
#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes *****************************/
/*
* Perform reset operation to the emacps interface
*/
void XEmacPs_ResetHw(u32 BaseAddr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv.h
*
* Defines common services that are typically found in a host operating.
* environment. This include file simply includes an OS specific file based
* on the compile-time constant BUILD_ENV_*, where * is the name of the target
* environment.
*
* All services are defined as macros.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b ch 10/24/02 Added XENV_LINUX
* 1.00a rmm 04/17/02 First release
* </pre>
*
******************************************************************************/
#ifndef XENV_H /* prevent circular inclusions */
#define XENV_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/*
* Select which target environment we are operating under
*/
/* VxWorks target environment */
#if defined XENV_VXWORKS
#include "xenv_vxworks.h"
/* Linux target environment */
#elif defined XENV_LINUX
#include "xenv_linux.h"
/* Unit test environment */
#elif defined XENV_UNITTEST
#include "ut_xenv.h"
/* Integration test environment */
#elif defined XENV_INTTEST
#include "int_xenv.h"
/* Standalone environment selected */
#else
#include "xenv_standalone.h"
#endif
/*
* The following comments specify the types and macro wrappers that are
* expected to be defined by the target specific header files
*/
/**************************** Type Definitions *******************************/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP
*
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
* Samples the processor's or external timer's time base counter.
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of microseconds.
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of milliseconds.
*/
/*****************************************************************************//**
*
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None
*/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_standalone.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
* used under Xilinx standalone BSP.
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a rmm 03/21/02 First release
* 1.00a wgr 03/22/07 Converted to new coding style.
* 1.00a rpm 06/29/07 Added udelay macro for standalone
* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
* to in MICROBLAZE section
* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
*
* </pre>
*
*
******************************************************************************/
#ifndef XENV_STANDALONE_H
#define XENV_STANDALONE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/******************************************************************************
*
* Get the processor dependent includes
*
******************************************************************************/
#include <string.h>
#if defined __MICROBLAZE__
# include "mb_interface.h"
# include "xparameters.h" /* XPAR constants used below in MB section */
#elif defined __PPC__
# include "sleep.h"
# include "xcache_l.h" /* also include xcache_l.h for caching macros */
#endif
/******************************************************************************
*
* MEMCPY / MEMSET related macros.
*
* The following are straight forward implementations of memset and memcpy.
*
* NOTE: memcpy may not work if source and target memory area are overlapping.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
* @note
* This implemention MAY BREAK work if source and target memory
* area are overlapping.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
/******************************************************************************
*
* TIME related macros
*
******************************************************************************/
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef s32 XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds. Not implemented without OS
* support.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#ifdef __PPC__
#define XENV_USLEEP(delay) usleep(delay)
#define udelay(delay) usleep(delay)
#else
#define XENV_USLEEP(delay)
#define udelay(delay)
#endif
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* Processor independent macros
*
******************************************************************************/
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
/******************************************************************************
*
* MicroBlaze case
*
* NOTE: Currently the following macros will only work on systems that contain
* only ONE MicroBlaze processor. Also, the macros will only be enabled if the
* system is built using a xparameters.h file.
*
******************************************************************************/
#if defined __MICROBLAZE__
/* Check if MicroBlaze data cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
#else
# define XCACHE_ENABLE_DCACHE()
# define XCACHE_DISABLE_DCACHE()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
/* Check if MicroBlaze instruction cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_ENABLE_ICACHE()
# define XCACHE_DISABLE_ICACHE()
#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
/******************************************************************************
*
* PowerPC case
*
* Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
* specific memory region (0x80000001). Each bit (0-30) in the regions
* bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
* range.
*
* regions --> cached address range
* ------------|--------------------------------------------------
* 0x80000000 | [0, 0x7FFFFFF]
* 0x00000001 | [0xF8000000, 0xFFFFFFFF]
* 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
*
******************************************************************************/
#elif defined __PPC__
#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifndef XENV_STANDALONE_H */

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/* ### HEADER ### */
#ifndef __XFPD_SLCR_H__
#define __XFPD_SLCR_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XfpdSlcr Base Address
*/
#define XFPD_SLCR_BASEADDR 0xFD610000UL
/**
* Register: XfpdSlcrWprot0
*/
#define XFPD_SLCR_WPROT0 ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
#define XFPD_SLCR_WPROT0_RSTVAL 0x00000001UL
#define XFPD_SLCR_WPROT0_ACT_SHIFT 0UL
#define XFPD_SLCR_WPROT0_ACT_WIDTH 1UL
#define XFPD_SLCR_WPROT0_ACT_MASK 0x00000001UL
#define XFPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL
/**
* Register: XfpdSlcrCtrl
*/
#define XFPD_SLCR_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
#define XFPD_SLCR_CTRL_RSTVAL 0x00000000UL
#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
#define XFPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIsr
*/
#define XFPD_SLCR_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
#define XFPD_SLCR_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrImr
*/
#define XFPD_SLCR_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
#define XFPD_SLCR_IMR_RSTVAL 0x00000001UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XfpdSlcrIer
*/
#define XFPD_SLCR_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
#define XFPD_SLCR_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIdr
*/
#define XFPD_SLCR_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
#define XFPD_SLCR_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrItr
*/
#define XFPD_SLCR_ITR ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
#define XFPD_SLCR_ITR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrWdtClkSel
*/
#define XFPD_SLCR_WDT_CLK_SEL ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL
#define XFPD_SLCR_WDT_CLK_SEL_SHIFT 0UL
#define XFPD_SLCR_WDT_CLK_SEL_WIDTH 1UL
#define XFPD_SLCR_WDT_CLK_SEL_MASK 0x00000001UL
#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIntFpd
*/
#define XFPD_SLCR_INT_FPD ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL )
#define XFPD_SLCR_INT_FPD_RSTVAL 0x00000000UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT 0UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH 1UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK 0x00000001UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL 0x0UL
/**
* Register: XfpdSlcrGpu
*/
#define XFPD_SLCR_GPU ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL )
#define XFPD_SLCR_GPU_RSTVAL 0x00000007UL
#define XFPD_SLCR_GPU_ARCACHE_SHIFT 7UL
#define XFPD_SLCR_GPU_ARCACHE_WIDTH 4UL
#define XFPD_SLCR_GPU_ARCACHE_MASK 0x00000780UL
#define XFPD_SLCR_GPU_ARCACHE_DEFVAL 0x0UL
#define XFPD_SLCR_GPU_AWCACHE_SHIFT 3UL
#define XFPD_SLCR_GPU_AWCACHE_WIDTH 4UL
#define XFPD_SLCR_GPU_AWCACHE_MASK 0x00000078UL
#define XFPD_SLCR_GPU_AWCACHE_DEFVAL 0x0UL
#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT 2UL
#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_PP1_IDLE_MASK 0x00000004UL
#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL 0x1UL
#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT 1UL
#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_PP0_IDLE_MASK 0x00000002UL
#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL 0x1UL
#define XFPD_SLCR_GPU_IDLE_SHIFT 0UL
#define XFPD_SLCR_GPU_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_IDLE_MASK 0x00000001UL
#define XFPD_SLCR_GPU_IDLE_DEFVAL 0x1UL
/**
* Register: XfpdSlcrGdmaCfg
*/
#define XFPD_SLCR_GDMA_CFG ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL )
#define XFPD_SLCR_GDMA_CFG_RSTVAL 0x00000048UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT 5UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH 2UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK 0x00000060UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL 0x2UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT 0UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH 5UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK 0x0000001fUL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL 0x8UL
/**
* Register: XfpdSlcrGdma
*/
#define XFPD_SLCR_GDMA ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL )
#define XFPD_SLCR_GDMA_RSTVAL 0x00003b3bUL
#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT 12UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK 0x00007000UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT 11UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH 1UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK 0x00000800UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL 0x1UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT 8UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK 0x00000700UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT 4UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK 0x00000070UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT 3UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH 1UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK 0x00000008UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL 0x1UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT 0UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK 0x00000007UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL 0x3UL
/**
* Register: XfpdSlcrAfiFs
*/
#define XFPD_SLCR_AFI_FS ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
#define XFPD_SLCR_AFI_FS_RSTVAL 0x00000a00UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH 2UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000c00UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x2UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH 2UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x2UL
/**
* Register: XfpdSlcrErrAtbIsr
*/
#define XFPD_SLCR_ERR_ATB_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL )
#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrErrAtbImr
*/
#define XFPD_SLCR_ERR_ATB_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL )
#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000007UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrErrAtbIer
*/
#define XFPD_SLCR_ERR_ATB_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL )
#define XFPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrErrAtbIdr
*/
#define XFPD_SLCR_ERR_ATB_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL )
#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrAtbCmdstore
*/
#define XFPD_SLCR_ATB_CMDSTORE ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL )
#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL 0x00000007UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrAtbRespEn
*/
#define XFPD_SLCR_ATB_RESP_EN ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL )
#define XFPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrAtbResptype
*/
#define XFPD_SLCR_ATB_RESPTYPE ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL )
#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL 0x00000007UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrAtbPrescale
*/
#define XFPD_SLCR_ATB_PRESCALE ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL )
#define XFPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL
#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL
#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL
#define XFPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL
#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL
#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_SLCR_H__ */

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freertos/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_slcr_secure.h Normal file
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/* ### HEADER ### */
#ifndef __XFPD_SLCR_SECURE_H__
#define __XFPD_SLCR_SECURE_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XfpdSlcrSecure Base Address
*/
#define XFPD_SLCR_SECURE_BASEADDR 0xFD690000UL
/**
* Register: XfpdSlcrSecCtrl
*/
#define XFPD_SLCR_SEC_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
#define XFPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecIsr
*/
#define XFPD_SLCR_SEC_ISR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
#define XFPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecImr
*/
#define XFPD_SLCR_SEC_IMR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
#define XFPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecIer
*/
#define XFPD_SLCR_SEC_IER ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
#define XFPD_SLCR_SEC_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecIdr
*/
#define XFPD_SLCR_SEC_IDR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
#define XFPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecItr
*/
#define XFPD_SLCR_SEC_ITR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
#define XFPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecSata
*/
#define XFPD_SLCR_SEC_SATA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
#define XFPD_SLCR_SEC_SATA_RSTVAL 0x0000000eUL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT 3UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK 0x00000008UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT 2UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK 0x00000004UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK 0x00000002UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT 0UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK 0x00000001UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecPcie
*/
#define XFPD_SLCR_SEC_PCIE ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
#define XFPD_SLCR_SEC_PCIE_RSTVAL 0x01ffffffUL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT 24UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK 0x01000000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT 23UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK 0x00800000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT 22UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK 0x00400000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT 21UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK 0x00200000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT 20UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK 0x00100000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT 19UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK 0x00080000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT 18UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK 0x00040000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT 17UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK 0x00020000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT 16UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK 0x00010000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT 15UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK 0x00008000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT 14UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK 0x00004000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT 13UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK 0x00002000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT 12UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK 0x00001000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT 11UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK 0x00000800UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT 10UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK 0x00000400UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT 9UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK 0x00000200UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT 8UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK 0x00000100UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT 7UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK 0x00000080UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT 6UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK 0x00000040UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT 5UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK 0x00000020UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT 4UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK 0x00000010UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT 3UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK 0x00000008UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT 2UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK 0x00000004UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK 0x00000002UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT 0UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecDpdma
*/
#define XFPD_SLCR_SEC_DPDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
#define XFPD_SLCR_SEC_DPDMA_RSTVAL 0x00000001UL
#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT 0UL
#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH 1UL
#define XFPD_SLCR_SEC_DPDMA_TZ_MASK 0x00000001UL
#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecGdma
*/
#define XFPD_SLCR_SEC_GDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
#define XFPD_SLCR_SEC_GDMA_RSTVAL 0x000000ffUL
#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT 0UL
#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH 8UL
#define XFPD_SLCR_SEC_GDMA_TZ_MASK 0x000000ffUL
#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL 0xffUL
/**
* Register: XfpdSlcrSecGic
*/
#define XFPD_SLCR_SEC_GIC ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
#define XFPD_SLCR_SEC_GIC_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT 0UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH 1UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK 0x00000001UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_SLCR_SECURE_H__ */

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/* ### HEADER ### */
#ifndef __XFPD_XMPU_SINK_H__
#define __XFPD_XMPU_SINK_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XfpdXmpuSink Base Address
*/
#define XFPD_XMPU_SINK_BASEADDR 0xFD4F0000UL
/**
* Register: XfpdXmpuSinkErrSts
*/
#define XFPD_XMPU_SINK_ERR_STS ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
#define XFPD_XMPU_SINK_ERR_STS_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT 31UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH 1UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT 0UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH 12UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkIsr
*/
#define XFPD_XMPU_SINK_ISR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
#define XFPD_XMPU_SINK_ISR_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkImr
*/
#define XFPD_XMPU_SINK_IMR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
#define XFPD_XMPU_SINK_IMR_RSTVAL 0x00000001UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL
/**
* Register: XfpdXmpuSinkIer
*/
#define XFPD_XMPU_SINK_IER ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
#define XFPD_XMPU_SINK_IER_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkIdr
*/
#define XFPD_XMPU_SINK_IDR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
#define XFPD_XMPU_SINK_IDR_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_XMPU_SINK_H__ */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops.h
* @addtogroup gpiops_v3_3
* @{
* @details
*
* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
* Controller.
*
* The GPIO Controller supports the following features:
* - 4 banks
* - Masked writes (There are no masked reads)
* - Bypass mode
* - Configurable Interrupts (Level/Edge)
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
* This driver supports all the features listed above, if applicable.
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the GPIO.
*
* <b>Interrupts</b>
*
* The driver provides interrupt management functions and an interrupt handler.
* Users of this driver need to provide callback functions. An interrupt handler
* example is available with the driver.
*
* <b>Threads</b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b>Building the driver</b>
*
* The XGpioPs driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
* <br><br>
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
* relevant to Zynq device.The interrupts are disabled
* for output pins on all banks during initialization.
* 1.02a hk 08/22/13 Added low level reset API
* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
* passed to APIs. CR# 822636
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Added tabspace for return statements in functions of
* gpiops examples for proper documentation while
* generating doxygen.
* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
* for zcu102 and zc702 boards in polled and interrupt
* example, configured Interrupt pin to input pin for
* proper functioning of interrupt example.
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_H /* prevent circular inclusions */
#define XGPIOPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xgpiops_hw.h"
#include "xplatform_info.h"
/************************** Constant Definitions *****************************/
/** @name Interrupt types
* @{
* The following constants define the interrupt types that can be set for each
* GPIO pin.
*/
#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
/*@}*/
#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
#ifdef XPAR_PSU_GPIO_0_BASEADDR
#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
#endif
#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
* Zynq Ultrascale+ MP GPIO device
*/
#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
* Zynq Ultrascale+ MP GPIO device
* 0 - 25, Bank 0
* 26 - 51, Bank 1
* 52 - 77, Bank 2
* 78 - 109, Bank 3
* 110 - 141, Bank 4
* 142 - 173, Bank 5
*/
#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
* 0 - 31, Bank 0
* 32 - 53, Bank 1
* 54 - 85, Bank 2
* 86 - 117, Bank 3
*/
/**************************** Type Definitions *******************************/
/****************************************************************************/
/**
* This handler data type allows the user to define a callback function to
* handle the interrupts for the GPIO device. The application using this
* driver is expected to define a handler of this type, to support interrupt
* driven mode. The handler executes in an interrupt context such that minimal
* processing should be performed.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions for a GPIO bank. It is
* passed back to the upper layer when the callback is invoked. Its
* type is not important to the driver component, so it is a void
* pointer.
* @param Bank is the bank for which the interrupt status has changed.
* @param Status is the Interrupt status of the GPIO bank.
*
*****************************************************************************/
typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddr; /**< Register base address */
} XGpioPs_Config;
/**
* The XGpioPs driver instance data. The user is required to allocate a
* variable of this type for the GPIO device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XGpioPs_Config GpioConfig; /**< Device configuration */
u32 IsReady; /**< Device is initialized and ready */
XGpioPs_Handler Handler; /**< Status handlers for all banks */
void *CallBackRef; /**< Callback ref for bank handlers */
u32 Platform; /**< Platform data */
u32 MaxPinNum; /**< Max pins in the GPIO device */
u8 MaxBanks; /**< Max banks in a GPIO device */
} XGpioPs;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* Functions in xgpiops.c */
s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
u32 EffectiveAddr);
/* Bank APIs in xgpiops.c */
u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
/* Pin APIs in xgpiops.c */
u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
/* Diagnostic functions in xgpiops_selftest.c */
s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
/* Functions in xgpiops_intr.c */
/* Bank APIs in xgpiops_intr.c */
void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
u32 IntrPolarity, u32 IntrOnAny);
void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
u32 *IntrPolarity, u32 *IntrOnAny);
void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
XGpioPs_Handler FuncPointer);
void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
/* Pin APIs in xgpiops_intr.c */
void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
/* Functions in xgpiops_sinit.c */
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops_hw.h
* @addtogroup gpiops_v3_3
* @{
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
* are defined in xgpiops.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.02a hk 08/22/13 Added low level reset API function prototype and
* related constant definitions
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/13/15 Corrected reset values of banks.
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
#define XGPIOPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register offsets for the GPIO. Each register is 32 bits.
* @{
*/
#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
/* @} */
/** @name Register offsets for each Bank.
* @{
*/
#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
/* @} */
/* For backwards compatibility */
#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
/** @name Interrupt type reset values for each bank
* @{
*/
#ifdef XPAR_PSU_GPIO_0_BASEADDR
#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
#else
#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
#endif
#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the register offset to be read.
*
* @return The 32-bit value of the register
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* This macro writes to the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the offset of the register to be written.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes ******************************/
void XGpioPs_ResetHw(u32 BaseAddress);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XGPIOPS_HW_H */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps.h
* @addtogroup iicps_v3_5
* @{
* @details
*
* This is an implementation of IIC driver in the PS block. The device can
* be either a master or a slave on the IIC bus. This implementation supports
* both interrupt mode transfer and polled mode transfer. Only 7-bit address
* is used in the driver, although the hardware also supports 10-bit address.
*
* IIC is a 2-wire serial interface. The master controls the clock, so it can
* regulate when it wants to send or receive data. The slave is under control of
* the master, it must respond quickly since it has no control of the clock and
* must send/receive data as fast or as slow as the master does.
*
* The higher level software must implement a higher layer protocol to inform
* the slave what to send to the master.
*
* <b>Initialization & Configuration</b>
*
* The XIicPs_Config structure is used by the driver to configure itself. This
* configuration structure is typically created by the tool-chain based on HW
* build properties.
*
* To support multiple runtime loading and initialization strategies employed by
* various operating systems, the driver instance can be initialized in the
* following way:
*
* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
* the static configuration structure defined in xiicps_g.c. This is
* setup by the tools. For some operating systems the config structure
* will be initialized by the software and this call is not needed.
*
* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
* configuration structure provided by the caller. If running in a
* system with address translation, the provided virtual memory base
* address replaces the physical address in the configuration
* structure.
*
* <b>Multiple Masters</b>
*
* More than one master can exist, bus arbitration is defined in the IIC
* standard. Lost of arbitration causes arbitration loss interrupt on the device.
*
* <b>Multiple Slaves</b>
*
* Multiple slaves are supported by selecting them with unique addresses. It is
* up to the system designer to be sure all devices on the IIC bus have
* unique addresses.
*
* <b>Addressing</b>
*
* The IIC hardware can use 7 or 10 bit addresses. The driver provides the
* ability to control which address size is sent in messages as a master to a
* slave device.
*
* <b>FIFO Size </b>
* The hardware FIFO is 32 bytes deep. The user must know the limitations of
* other IIC devices on the bus. Some are only able to receive a limited number
* of bytes in a single transfer.
*
* <b>Data Rates</b>
*
* The data rate is set by values in the control register. The formula for
* determining the correct register values is:
* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
*
* When the device is configured as a slave, the slck setting controls the
* sample rate and so must be set to be at least as fast as the fastest scl
* expected to be seen in the system.
*
* <b>Polled Mode Operation</b>
*
* This driver supports polled mode transfers.
*
* <b>Interrupts</b>
*
* The user must connect the interrupt handler of the driver,
* XIicPs_InterruptHandler to an interrupt system such that it will be called
* when an interrupt occurs. This function does not save and restore the
* processor context such that the user must provide this processing.
*
* The driver handles the following interrupts:
* - Transfer complete
* - More Data
* - Transfer not Acknowledged
* - Transfer Time out
* - Monitored slave ready - master mode only
* - Receive Overflow
* - Transmit FIFO overflow
* - Receive FIFO underflow
* - Arbitration lost
*
* <b>Bus Busy</b>
*
* Bus busy is checked before the setup of a master mode device, to avoid
* unnecessary arbitration loss interrupt.
*
* <b>RTOS Independence</b>
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads or
* thread mutual exclusion, virtual memory, or cache control must be satisfied by
* the layer above this driver.
*
*<b>Repeated Start</b>
*
* The I2C controller does not indicate completion of a receive transfer if HOLD
* bit is set. Due to this errata, repeated start cannot be used if a receive
* transfer is followed by any other transfer.
*
* <pre> MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00a drg/jz 01/30/08 First release
* 1.00a sdm 09/21/11 Fixed an issue in the XIicPs_SetOptions and
* XIicPs_ClearOptions where the InstancePtr->Options
* was not updated correctly.
* Updated the InstancePtr->Options in the
* XIicPs_CfgInitialize by calling XIicPs_GetOptions.
* Updated the XIicPs_SetupMaster to not check for
* Bus Busy condition when the Hold Bit is set.
* Removed some unused variables.
* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
* check for transfer completion is added, which indicates
* the completion of current transfer.
* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors
* to achieve I2C clock with minimum error for
* CR #674195
* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0.
* This is fix for CR#704398 to remove warning.
* 2.0 hk 03/07/14 Added check for error status in the while loop that
* checks for completion.
* (XIicPs_MasterSendPolled function). CR# 762244, 764875.
* Limited frequency set when 100KHz or 400KHz is
* selected. This is a hardware limitation. CR#779290.
* 2.1 hk 04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
* Explicitly reset CR and clear FIFO in Abort function
* and state the same in the comments. CR# 784254.
* Fix for CR# 761060 - provision for repeated start.
* 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable
* read mode and clear transfer size register.
* Disable NACK to avoid interrupts on each retry.
* 2.3 sk 10/07/14 Repeated start feature deleted.
* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
* in XIicPs_Reset.
* 12/06/14 Implemented Repeated start feature.
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
* 02/18/15 Implemented larger data transfer using repeated start
* in Zynq UltraScale MP.
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
*
* </pre>
*
******************************************************************************/
#ifndef XIICPS_H /* prevent circular inclusions */
#define XIICPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xiicps_hw.h"
#include "xplatform_info.h"
/************************** Constant Definitions *****************************/
/** @name Configuration options
*
* The following options may be specified or retrieved for the device and
* enable/disable additional features of the IIC. Each of the options
* are bit fields, so more than one may be specified.
*
* @{
*/
#define XIICPS_7_BIT_ADDR_OPTION 0x01U /**< 7-bit address mode */
#define XIICPS_10_BIT_ADDR_OPTION 0x02U /**< 10-bit address mode */
#define XIICPS_SLAVE_MON_OPTION 0x04U /**< Slave monitor mode */
#define XIICPS_REP_START_OPTION 0x08U /**< Repeated Start */
/*@}*/
/** @name Callback events
*
* These constants specify the handler events that are passed to an application
* event handler from the driver. These constants are bit masks such that
* more than one event can be passed to the handler.
*
* @{
*/
#define XIICPS_EVENT_COMPLETE_SEND 0x0001U /**< Transmit Complete Event*/
#define XIICPS_EVENT_COMPLETE_RECV 0x0002U /**< Receive Complete Event*/
#define XIICPS_EVENT_TIME_OUT 0x0004U /**< Transfer timed out */
#define XIICPS_EVENT_ERROR 0x0008U /**< Receive error */
#define XIICPS_EVENT_ARB_LOST 0x0010U /**< Arbitration lost */
#define XIICPS_EVENT_NACK 0x0020U /**< NACK Received */
#define XIICPS_EVENT_SLAVE_RDY 0x0040U /**< Slave ready */
#define XIICPS_EVENT_RX_OVR 0x0080U /**< RX overflow */
#define XIICPS_EVENT_TX_OVR 0x0100U /**< TX overflow */
#define XIICPS_EVENT_RX_UNF 0x0200U /**< RX underflow */
/*@}*/
/** @name Role constants
*
* These constants are used to pass into the device setup routines to
* set up the device according to transfer direction.
*/
#define SENDING_ROLE 1 /**< Transfer direction is sending */
#define RECVING_ROLE 0 /**< Transfer direction is receiving */
/* Maximum transfer size */
#define XIICPS_MAX_TRANSFER_SIZE (u32)(255U - 3U)
/**************************** Type Definitions *******************************/
/**
* The handler data type allows the user to define a callback function to
* respond to interrupt events in the system. This function is executed
* in interrupt context, so amount of processing should be minimized.
*
* @param CallBackRef is the callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* not important to the driver, so it is a void pointer.
* @param StatusEvent indicates one or more status events that occurred.
*/
typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
} XIicPs_Config;
/**
* The XIicPs driver instance data. The user is required to allocate a
* variable of this type for each IIC device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XIicPs_Config Config; /* Configuration structure */
u32 IsReady; /* Device is initialized and ready */
u32 Options; /* Options set in the device */
u8 *SendBufferPtr; /* Pointer to send buffer */
u8 *RecvBufferPtr; /* Pointer to recv buffer */
s32 SendByteCount; /* Number of bytes still expected to send */
s32 RecvByteCount; /* Number of bytes still expected to receive */
s32 CurrByteCount; /* No. of bytes expected in current transfer */
s32 UpdateTxSize; /* If tx size register has to be updated */
s32 IsSend; /* Whether master is sending or receiving */
s32 IsRepeatedStart; /* Indicates if user set repeated start */
XIicPs_IntrHandler StatusHandler; /* Event handler function */
void *CallBackRef; /* Callback reference for event handler */
} XIicPs;
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/*
*
* Place one byte into the transmit FIFO.
*
* @param InstancePtr is the instance of IIC
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_SendByte(XIicPs *InstancePtr)
*
*****************************************************************************/
#define XIicPs_SendByte(InstancePtr) \
{ \
u8 Data; \
Data = *((InstancePtr)->SendBufferPtr); \
XIicPs_Out32((InstancePtr)->Config.BaseAddress \
+ (u32)(XIICPS_DATA_OFFSET), \
(u32)(Data)); \
(InstancePtr)->SendBufferPtr += 1; \
(InstancePtr)->SendByteCount -= 1;\
}
/****************************************************************************/
/*
*
* Receive one byte from FIFO.
*
* @param InstancePtr is the instance of IIC
*
* @return None.
*
* @note C-Style signature:
* u8 XIicPs_RecvByte(XIicPs *InstancePtr)
*
*****************************************************************************/
#define XIicPs_RecvByte(InstancePtr) \
{ \
u8 *Data, Value; \
Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress \
+ (u32)XIICPS_DATA_OFFSET)); \
Data = &Value; \
*(InstancePtr)->RecvBufferPtr = *Data; \
(InstancePtr)->RecvBufferPtr += 1; \
(InstancePtr)->RecvByteCount --; \
}
/************************** Function Prototypes ******************************/
/*
* Function for configuration lookup, in xiicps_sinit.c
*/
XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
/*
* Functions for general setup, in xiicps.c
*/
s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
u32 EffectiveAddr);
void XIicPs_Abort(XIicPs *InstancePtr);
void XIicPs_Reset(XIicPs *InstancePtr);
s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
s32 TransmitFifoFill(XIicPs *InstancePtr);
/*
* Functions for interrupts, in xiicps_intr.c
*/
void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
XIicPs_IntrHandler FunctionPtr);
/*
* Functions for device as master, in xiicps_master.c
*/
void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
/*
* Functions for device as slave, in xiicps_slave.c
*/
void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
/*
* Functions for selftest, in xiicps_selftest.c
*/
s32 XIicPs_SelfTest(XIicPs *InstancePtr);
/*
* Functions for setting and getting data rate, in xiicps_options.c
*/
s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
u32 XIicPs_GetOptions(XIicPs *InstancePtr);
s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
u32 XIicPs_GetSClk(XIicPs *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_hw.h
* @addtogroup iicps_v3_5
* @{
*
* This header file contains the hardware definition for an IIC device.
* It includes register definitions and interface functions to read/write
* the registers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00a drg/jz 01/30/10 First release
* 1.04a kpc 11/07/13 Added function prototype.
* 3.0 sk 11/03/14 Modified the TimeOut Register value to 0xFF
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
* </pre>
*
******************************************************************************/
#ifndef XIICPS_HW_H /* prevent circular inclusions */
#define XIICPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
*
* Register offsets for the IIC.
* @{
*/
#define XIICPS_CR_OFFSET 0x00U /**< 32-bit Control */
#define XIICPS_SR_OFFSET 0x04U /**< Status */
#define XIICPS_ADDR_OFFSET 0x08U /**< IIC Address */
#define XIICPS_DATA_OFFSET 0x0CU /**< IIC FIFO Data */
#define XIICPS_ISR_OFFSET 0x10U /**< Interrupt Status */
#define XIICPS_TRANS_SIZE_OFFSET 0x14U /**< Transfer Size */
#define XIICPS_SLV_PAUSE_OFFSET 0x18U /**< Slave monitor pause */
#define XIICPS_TIME_OUT_OFFSET 0x1CU /**< Time Out */
#define XIICPS_IMR_OFFSET 0x20U /**< Interrupt Enabled Mask */
#define XIICPS_IER_OFFSET 0x24U /**< Interrupt Enable */
#define XIICPS_IDR_OFFSET 0x28U /**< Interrupt Disable */
/* @} */
/** @name Control Register
*
* This register contains various control bits that
* affects the operation of the IIC controller. Read/Write.
* @{
*/
#define XIICPS_CR_DIV_A_MASK 0x0000C000U /**< Clock Divisor A */
#define XIICPS_CR_DIV_A_SHIFT 14U /**< Clock Divisor A shift */
#define XIICPS_DIV_A_MAX 4U /**< Maximum value of Divisor A */
#define XIICPS_CR_DIV_B_MASK 0x00003F00U /**< Clock Divisor B */
#define XIICPS_CR_DIV_B_SHIFT 8U /**< Clock Divisor B shift */
#define XIICPS_CR_CLR_FIFO_MASK 0x00000040U /**< Clear FIFO, auto clears*/
#define XIICPS_CR_SLVMON_MASK 0x00000020U /**< Slave monitor mode */
#define XIICPS_CR_HOLD_MASK 0x00000010U /**< Hold bus 1=Hold scl,
0=terminate transfer */
#define XIICPS_CR_ACKEN_MASK 0x00000008U /**< Enable TX of ACK when
Master receiver*/
#define XIICPS_CR_NEA_MASK 0x00000004U /**< Addressing Mode 1=7 bit,
0=10 bit */
#define XIICPS_CR_MS_MASK 0x00000002U /**< Master mode bit 1=Master,
0=Slave */
#define XIICPS_CR_RD_WR_MASK 0x00000001U /**< Read or Write Master
transfer 0=Transmitter,
1=Receiver*/
#define XIICPS_CR_RESET_VALUE 0U /**< Reset value of the Control
register */
/* @} */
/** @name IIC Status Register
*
* This register is used to indicate status of the IIC controller. Read only
* @{
*/
#define XIICPS_SR_BA_MASK 0x00000100U /**< Bus Active Mask */
#define XIICPS_SR_RXOVF_MASK 0x00000080U /**< Receiver Overflow Mask */
#define XIICPS_SR_TXDV_MASK 0x00000040U /**< Transmit Data Valid Mask */
#define XIICPS_SR_RXDV_MASK 0x00000020U /**< Receiver Data Valid Mask */
#define XIICPS_SR_RXRW_MASK 0x00000008U /**< Receive read/write Mask */
/* @} */
/** @name IIC Address Register
*
* Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
* A write access to this register always initiates a transfer if the IIC is in
* master mode. Read/Write
* @{
*/
#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */
/* @} */
/** @name IIC Data Register
*
* When written to, the data register sets data to transmit. When read from, the
* data register reads the last received byte of data. Read/Write
* @{
*/
#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */
/* @} */
/** @name IIC Interrupt Registers
*
* <b>IIC Interrupt Status Register</b>
*
* This register holds the interrupt status flags for the IIC controller. Some
* of the flags are level triggered
* - i.e. are set as long as the interrupt condition exists. Other flags are
* edge triggered, which means they are set one the interrupt condition occurs
* then remain set until they are cleared by software.
* The interrupts are cleared by writing a one to the interrupt bit position
* in the Interrupt Status Register. Read/Write.
*
* <b>IIC Interrupt Enable Register</b>
*
* This register is used to enable interrupt sources for the IIC controller.
* Writing a '1' to a bit in this register clears the corresponding bit in the
* IIC Interrupt Mask register. Write only.
*
* <b>IIC Interrupt Disable Register </b>
*
* This register is used to disable interrupt sources for the IIC controller.
* Writing a '1' to a bit in this register sets the corresponding bit in the
* IIC Interrupt Mask register. Write only.
*
* <b>IIC Interrupt Mask Register</b>
*
* This register shows the enabled/disabled status of each IIC controller
* interrupt source. A bit set to 1 will ignore the corresponding interrupt in
* the status register. A bit set to 0 means the interrupt is enabled.
* All mask bits are set and all interrupts are disabled after reset. Read only.
*
* All four registers have the same bit definitions. They are only defined once
* for each of the Interrupt Enable Register, Interrupt Disable Register,
* Interrupt Mask Register, and Interrupt Status Register
* @{
*/
#define XIICPS_IXR_ARB_LOST_MASK 0x00000200U /**< Arbitration Lost Interrupt
mask */
#define XIICPS_IXR_RX_UNF_MASK 0x00000080U /**< FIFO Recieve Underflow
Interrupt mask */
#define XIICPS_IXR_TX_OVR_MASK 0x00000040U /**< Transmit Overflow
Interrupt mask */
#define XIICPS_IXR_RX_OVR_MASK 0x00000020U /**< Receive Overflow Interrupt
mask */
#define XIICPS_IXR_SLV_RDY_MASK 0x00000010U /**< Monitored Slave Ready
Interrupt mask */
#define XIICPS_IXR_TO_MASK 0x00000008U /**< Transfer Time Out
Interrupt mask */
#define XIICPS_IXR_NACK_MASK 0x00000004U /**< NACK Interrupt mask */
#define XIICPS_IXR_DATA_MASK 0x00000002U /**< Data Interrupt mask */
#define XIICPS_IXR_COMP_MASK 0x00000001U /**< Transfer Complete
Interrupt mask */
#define XIICPS_IXR_DEFAULT_MASK 0x000002FFU /**< Default ISR Mask */
#define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU /**< All ISR Mask */
/* @} */
/** @name IIC Transfer Size Register
*
* The register's meaning varies according to the operating mode as follows:
* - Master transmitter mode: number of data bytes still not transmitted minus
* one
* - Master receiver mode: number of data bytes that are still expected to be
* received
* - Slave transmitter mode: number of bytes remaining in the FIFO after the
* master terminates the transfer
* - Slave receiver mode: number of valid data bytes in the FIFO
*
* This register is cleared if CLR_FIFO bit in the control register is set.
* Read/Write
* @{
*/
#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */
#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */
#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */
/* @} */
/** @name IIC Slave Monitor Pause Register
*
* This register is associated with the slave monitor mode of the I2C interface.
* It is meaningful only when the module is in master mode and bit SLVMON in the
* control register is set.
*
* This register defines the pause interval between consecutive attempts to
* address the slave once a write to an I2C address register is done by the
* host. It represents the number of sclk cycles minus one between two attempts.
*
* The reset value of the register is 0, which results in the master repeatedly
* trying to access the slave immediately after unsuccessful attempt.
* Read/Write
* @{
*/
#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */
/* @} */
/** @name IIC Time Out Register
*
* The value of time out register represents the time out interval in number of
* sclk cycles minus one.
*
* When the accessed slave holds the sclk line low for longer than the time out
* period, thus prohibiting the I2C interface in master mode to complete the
* current transfer, an interrupt is generated and TO interrupt flag is set.
*
* The reset value of the register is 0x1f.
* Read/Write
* @{
*/
#define XIICPS_TIME_OUT_MASK 0x000000FFU /**< IIC Time Out mask */
#define XIICPS_TO_RESET_VALUE 0x000000FFU /**< IIC Time Out reset value */
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XIicPs_In32 Xil_In32
#define XIicPs_Out32 Xil_Out32
/****************************************************************************/
/**
* Read an IIC register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to select the specific register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XIicPs_ReadReg(BaseAddress, RegOffset) \
XIicPs_In32((BaseAddress) + (u32)(RegOffset))
/***************************************************************************/
/**
* Write an IIC register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to select the specific register.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
*
******************************************************************************/
#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
/***************************************************************************/
/**
* Read the interrupt enable register.
*
* @param BaseAddress contains the base address of the device.
*
* @return Current bit mask that represents currently enabled interrupts.
*
* @note C-Style signature:
* u32 XIicPs_ReadIER(u32 BaseAddress)
*
******************************************************************************/
#define XIicPs_ReadIER(BaseAddress) \
XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
/***************************************************************************/
/**
* Write to the interrupt enable register.
*
* @param BaseAddress contains the base address of the device.
*
* @param IntrMask is the interrupts to be enabled.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
*
******************************************************************************/
#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
/***************************************************************************/
/**
* Disable all interrupts.
*
* @param BaseAddress contains the base address of the device.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_DisableAllInterrupts(u32 BaseAddress)
*
******************************************************************************/
#define XIicPs_DisableAllInterrupts(BaseAddress) \
XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
XIICPS_IXR_ALL_INTR_MASK)
/***************************************************************************/
/**
* Disable selected interrupts.
*
* @param BaseAddress contains the base address of the device.
*
* @param IntrMask is the interrupts to be disabled.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
*
******************************************************************************/
#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
(IntrMask))
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/*
* Perform reset operation to the I2c interface
*/
void XIicPs_ResetHw(u32 BaseAddress);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_assert.h
*
* @addtogroup common_assert_apis Assert APIs and Macros
*
* The xil_assert.h file contains assert related functions and macros.
* Assert APIs/Macros specifies that a application program satisfies certain
* conditions at particular points in its execution. These function can be
* used by application programs to ensure that, application code is satisfying
* certain conditions.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
* </pre>
*
******************************************************************************/
#ifndef XIL_ASSERT_H /* prevent circular inclusions */
#define XIL_ASSERT_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#define XIL_ASSERT_NONE 0U
#define XIL_ASSERT_OCCURRED 1U
#define XNULL NULL
extern u32 Xil_AssertStatus;
extern s32 Xil_AssertWait;
extern void Xil_Assert(const char8 *File, s32 Line);
void XNullHandler(void *NullParameter);
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef NDEBUG
/*****************************************************************************/
/**
* @brief This assert macro is to be used for void functions. This in
* conjunction with the Xil_AssertWait boolean can be used to
* accomodate tests so that asserts which fail allow execution to
* continue.
*
* @param Expression: expression to be evaluated. If it evaluates to
* false, the assert occurs.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertVoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
} \
}
/*****************************************************************************/
/**
* @brief This assert macro is to be used for functions that do return a
* value. This in conjunction with the Xil_AssertWait boolean can be
* used to accomodate tests so that asserts which fail allow execution
* to continue.
*
* @param Expression: expression to be evaluated. If it evaluates to false,
* the assert occurs.
*
* @return Returns 0 unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertNonvoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
} \
}
/*****************************************************************************/
/**
* @brief Always assert. This assert macro is to be used for void functions.
* Use for instances where an assert should always occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertVoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
}
/*****************************************************************************/
/**
* @brief Always assert. This assert macro is to be used for functions that
* do return a value. Use for instances where an assert should always
* occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertNonvoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
}
#else
#define Xil_AssertVoid(Expression)
#define Xil_AssertVoidAlways()
#define Xil_AssertNonvoid(Expression)
#define Xil_AssertNonvoidAlways()
#endif
/************************** Function Prototypes ******************************/
void Xil_AssertSetCallback(Xil_AssertCallback Routine);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_assert_apis".
*/

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/******************************************************************************
*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache.h
*
* @addtogroup a53_64_cache_apis Cortex A53 64bit Processor Cache Functions
*
* Cache functions provide access to cache related operations such as flush
* and invalidate for instruction and data caches. It gives option to perform
* the cache operations on a single cacheline, a range of memory and an entire
* cache.
*
* @{
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_CACHE_H
#define XIL_CACHE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
#define L1_DATA_PREFETCH_CONTROL_MASK 0xE000
#define L1_DATA_PREFETCH_CONTROL_SHIFT 13
/************************** Function Prototypes ******************************/
void Xil_DCacheEnable(void);
void Xil_DCacheDisable(void);
void Xil_DCacheInvalidate(void);
void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len);
void Xil_DCacheInvalidateLine(INTPTR adr);
void Xil_DCacheFlush(void);
void Xil_DCacheFlushRange(INTPTR adr, INTPTR len);
void Xil_DCacheFlushLine(INTPTR adr);
void Xil_ICacheEnable(void);
void Xil_ICacheDisable(void);
void Xil_ICacheInvalidate(void);
void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len);
void Xil_ICacheInvalidateLine(INTPTR adr);
void Xil_ConfigureL1Prefetch(u8 num);
#ifdef __cplusplus
}
#endif
#endif
/**
* @} End of "addtogroup a53_64_cache_apis".
*/

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/******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache_vxworks.h
*
* Contains the cache related functions for VxWorks that is wrapped by
* xil_cache.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 12/11/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_CACHE_VXWORKS_H
#define XIL_CACHE_VXWORKS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "vxWorks.h"
#include "vxLib.h"
#include "sysLibExtra.h"
#include "cacheLib.h"
#if (CPU_FAMILY==PPC)
#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
#define Xil_DCacheInvalidateRange(Addr, Len) \
cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_DCacheFlushRange(Addr, Len) \
cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
#define Xil_ICacheInvalidateRange(Addr, Len) \
cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
#else
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#endif
#ifdef __cplusplus
}
#endif
#endif

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/******************************************************************************
*
* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_errata.h
*
* @addtogroup a53_errata Cortex A53 64 bit Processor Errata Support
* @{
* Various ARM errata are handled in the standalone BSP. The implementation for
* errata handling follows ARM guidelines and is based on the open source Linux
* support for these errata.
*
* @note
* The errata handling is enabled by default. To disable handling of all the
* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
* disable errata on a per-erratum basis, un-define relevant macros in
* xil_errata.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 6.4 mus 08/11/17 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_ERRATA_H
#define XIL_ERRATA_H
/**
* @name errata_definitions
*
* The errata conditions handled in the standalone BSP are listed below
* @{
*/
#define ENABLE_ARM_ERRATA 0
#ifdef ENABLE_ARM_ERRATA
/**
* Errata No: 855873
* Description: An eviction might overtake a cache clean operation
*/
#define CONFIG_ARM_ERRATA_855873 0
/*@}*/
#endif /* ENABLE_ARM_ERRATA */
#endif /* XIL_ERRATA_H */
/**
* @} End of "addtogroup a53_errata".
*/

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/******************************************************************************
*
* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_exception.h
*
* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
* For exception related functions that can be used across all Xilinx supported
* processors, please use xil_exception.h.
*
* @addtogroup arm_exception_apis ARM Processor Exception Handling
* @{
* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
* utilized for enabling/disabling IRQ, registering/removing handler for
* exceptions or initializing exception vector table with null handler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.2 pkp 28/05/15 First release
* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
* </pre>
*
******************************************************************************/
#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
#define XIL_EXCEPTION_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xpseudo_asm.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions ****************************/
#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
#define XIL_EXCEPTION_ID_FIRST 0U
#if defined (__aarch64__)
#define XIL_EXCEPTION_ID_SYNC_INT 1U
#define XIL_EXCEPTION_ID_IRQ_INT 2U
#define XIL_EXCEPTION_ID_FIQ_INT 3U
#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
#define XIL_EXCEPTION_ID_LAST 5U
#else
#define XIL_EXCEPTION_ID_RESET 0U
#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
#define XIL_EXCEPTION_ID_SWI_INT 2U
#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
#define XIL_EXCEPTION_ID_IRQ_INT 5U
#define XIL_EXCEPTION_ID_FIQ_INT 6U
#define XIL_EXCEPTION_ID_LAST 6U
#endif
/*
* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
*/
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
/**************************** Type Definitions ******************************/
/**
* This typedef is the exception handler function.
*/
typedef void (*Xil_ExceptionHandler)(void *data);
typedef void (*Xil_InterruptHandler)(void *data);
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
* @brief Enable Exceptions.
*
* @param Mask: Value for enabling the exceptions.
*
* @return None.
*
* @note If bit is 0, exception is enabled.
* C-Style signature: void Xil_ExceptionEnableMask(Mask)
*
******************************************************************************/
#if defined (__GNUC__) || defined (__ICCARM__)
#define Xil_ExceptionEnableMask(Mask) \
mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
#else
#define Xil_ExceptionEnableMask(Mask) \
{ \
register u32 Reg __asm("cpsr"); \
mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
}
#endif
/****************************************************************************/
/**
* @brief Enable the IRQ exception.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define Xil_ExceptionEnable() \
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
/****************************************************************************/
/**
* @brief Disable Exceptions.
*
* @param Mask: Value for disabling the exceptions.
*
* @return None.
*
* @note If bit is 1, exception is disabled.
* C-Style signature: Xil_ExceptionDisableMask(Mask)
*
******************************************************************************/
#if defined (__GNUC__) || defined (__ICCARM__)
#define Xil_ExceptionDisableMask(Mask) \
mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
#else
#define Xil_ExceptionDisableMask(Mask) \
{ \
register u32 Reg __asm("cpsr"); \
mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
}
#endif
/****************************************************************************/
/**
* Disable the IRQ exception.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define Xil_ExceptionDisable() \
Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
#if !defined (__aarch64__) && !defined (ARMA53_32)
/****************************************************************************/
/**
* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
* API is defined for cortex-a9 and cortex-r5.
*
* @return None.
*
* @note This macro is supposed to be used from interrupt handlers. In the
* interrupt handler the interrupts are disabled by default (I and F
* are 1). To allow nesting of interrupts, this macro should be
* used. It clears the I and F bits by changing the ARM mode to
* system mode. Once these bits are cleared and provided the
* preemption of interrupt conditions are met in the GIC, nesting of
* interrupts will start happening.
* Caution: This macro must be used with caution. Before calling this
* macro, the user must ensure that the source of the current IRQ
* is appropriately cleared. Otherwise, as soon as we clear the I and
* F bits, there can be an infinite loop of interrupts with an
* eventual crash (all the stack space getting consumed).
******************************************************************************/
#define Xil_EnableNestedInterrupts() \
__asm__ __volatile__ ("stmfd sp!, {lr}"); \
__asm__ __volatile__ ("mrs lr, spsr"); \
__asm__ __volatile__ ("stmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
__asm__ __volatile__ ("stmfd sp!, {lr}");
/****************************************************************************/
/**
* @brief Disable the nested interrupts by setting the I and F bits. This API
* is defined for cortex-a9 and cortex-r5.
*
* @return None.
*
* @note This macro is meant to be called in the interrupt service routines.
* This macro cannot be used independently. It can only be used when
* nesting of interrupts have been enabled by using the macro
* Xil_EnableNestedInterrupts(). In a typical flow, the user first
* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
* point. The user then must call this macro before exiting the interrupt
* service routine. This macro puts the ARM back in IRQ/FIQ mode and
* hence sets back the I and F bits.
******************************************************************************/
#define Xil_DisableNestedInterrupts() \
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr cpsr_c, #0x92"); \
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr spsr_cxsf, lr"); \
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
#endif
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
Xil_ExceptionHandler Handler,
void *Data);
extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
extern void Xil_ExceptionInit(void);
#if defined (__aarch64__)
void Xil_SyncAbortHandler(void *CallBackRef);
void Xil_SErrorAbortHandler(void *CallBackRef);
#else
extern void Xil_DataAbortHandler(void *CallBackRef);
extern void Xil_PrefetchAbortHandler(void *CallBackRef);
extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_EXCEPTION_H */
/**
* @} End of "addtogroup arm_exception_apis".
*/

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/******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_hal.h
*
* Contains all the HAL header files.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/28/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_HAL_H
#define XIL_HAL_H
#include "xil_cache.h"
#include "xil_io.h"
#include "xil_assert.h"
#include "xil_exception.h"
#include "xil_types.h"
#endif

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/******************************************************************************
*
* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_io.h
*
* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
*
* The xil_io.h file contains the interface for the general I/O component, which
* encapsulates the Input/Output functions for the processors that do not
* require any special I/O handling.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
* ARM processors
* </pre>
******************************************************************************/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_printf.h"
#if defined (__MICROBLAZE__)
#include "mb_interface.h"
#else
#include "xpseudo_asm.h"
#endif
/************************** Function Prototypes ******************************/
u16 Xil_EndianSwap16(u16 Data);
u32 Xil_EndianSwap32(u32 Data);
#ifdef ENABLE_SAFETY
extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
#endif
/***************** Macros (Inline Functions) Definitions *********************/
#if defined __GNUC__
#if defined (__MICROBLAZE__)
# define INST_SYNC mbar(0)
# define DATA_SYNC mbar(1)
# else
# define SYNCHRONIZE_IO dmb()
# define INST_SYNC isb()
# define DATA_SYNC dsb()
# endif
#else
# define SYNCHRONIZE_IO
# define INST_SYNC
# define DATA_SYNC
# define INST_SYNC
# define DATA_SYNC
#endif
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
#define INLINE inline
#else
#define INLINE __inline
#endif
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading
* from the specified address and returning the 8 bit Value read from
* that address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 8 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u8 Xil_In8(UINTPTR Addr)
{
return *(volatile u8 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading from
* the specified address and returning the 16 bit Value read from that
* address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 16 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u16 Xil_In16(UINTPTR Addr)
{
return *(volatile u16 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by
* reading from the specified address and returning the 32 bit Value
* read from that address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 32 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u32 Xil_In32(UINTPTR Addr)
{
return *(volatile u32 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading the
* 64 bit Value read from that address.
*
*
* @param Addr: contains the address to perform the input operation
*
* @return The 64 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u64 Xil_In64(UINTPTR Addr)
{
return *(volatile u64 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for an memory location by
* writing the 8 bit Value to the the specified address.
*
* @param Addr: contains the address to perform the output operation
* @param Value: contains the 8 bit Value to be written at the specified
* address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
{
volatile u8 *LocalAddr = (volatile u8 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 16 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains the Value to be written at the specified address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
{
volatile u16 *LocalAddr = (volatile u16 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 32 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains the 32 bit Value to be written at the specified
* address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
{
#ifndef ENABLE_SAFETY
volatile u32 *LocalAddr = (volatile u32 *)Addr;
*LocalAddr = Value;
#else
XStl_RegUpdate(Addr, Value);
#endif
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 64 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains 64 bit Value to be written at the specified address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
{
volatile u64 *LocalAddr = (volatile u64 *)Addr;
*LocalAddr = Value;
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
# else
# define Xil_In16BE Xil_In16
# define Xil_In32BE Xil_In32
# define Xil_Out16BE Xil_Out16
# define Xil_Out32BE Xil_Out32
# define Xil_Htons(Data) (Data)
# define Xil_Htonl(Data) (Data)
# define Xil_Ntohs(Data) (Data)
# define Xil_Ntohl(Data) (Data)
#endif
#else
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
#endif
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u16 Xil_In16BE(UINTPTR Addr)
#else
static INLINE u16 Xil_In16LE(UINTPTR Addr)
#endif
#else
static INLINE u16 Xil_In16BE(UINTPTR Addr)
#endif
{
u16 value = Xil_In16(Addr);
return Xil_EndianSwap16(value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#else
static INLINE u32 Xil_In32LE(UINTPTR Addr)
#endif
#else
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#endif
{
u32 value = Xil_In32(Addr);
return Xil_EndianSwap32(value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#else
static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
#endif
#else
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#endif
{
Value = Xil_EndianSwap16(Value);
Xil_Out16(Addr, Value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#else
static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
#endif
#else
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#endif
{
Value = Xil_EndianSwap32(Value);
Xil_Out32(Addr, Value);
}
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_io_interfacing_apis".
*/

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/******************************************************************************/
/**
* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
* @file xil_mem.h
*
* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
*
* The xil_mem.h file contains prototype for functions related
* to memory operations. These APIs are applicable for all processors supported
* by Xilinx.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.1 nsk 11/07/16 First release.
*
* </pre>
*
*****************************************************************************/
/************************** Function Prototypes *****************************/
void Xil_MemCpy(void* dst, const void* src, u32 cnt);
/**
* @} End of "addtogroup common_mem_operation_api".
*/

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/******************************************************************************
*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xil_mmu.h
*
* @addtogroup a53_64_mmu_apis Cortex A53 64bit Processor MMU Handling
*
* MMU function equip users to modify default memory attributes of MMU table as
* per the need.
*
* @{
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef XIL_MMU_H
#define XIL_MMU_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/***************************** Include Files *********************************/
#include "xil_types.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/* Memory type */
#define NORM_NONCACHE 0x401UL /* Normal Non-cacheable*/
#define STRONG_ORDERED 0x409UL /* Strongly ordered (Device-nGnRnE)*/
#define DEVICE_MEMORY 0x40DUL /* Device memory (Device-nGnRE)*/
#define RESERVED 0x0UL /* reserved memory*/
/* Normal write-through cacheable inner shareable*/
#define NORM_WT_CACHE 0x711UL
/* Normal write back cacheable inner-shareable */
#define NORM_WB_CACHE 0x705UL
/*
* shareability attribute only applicable to
* normal cacheable memory
*/
#define INNER_SHAREABLE (0x3 << 8)
#define OUTER_SHAREABLE (0x2 << 8)
#define NON_SHAREABLE (~(0x3 << 8))
/* Execution type */
#define EXECUTE_NEVER ((0x1 << 53) | (0x1 << 54))
/* Security type */
#define NON_SECURE (0x1 << 5)
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
void Xil_SetTlbAttributes(UINTPTR Addr, u64 attrib);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_MMU_H */
/**
* @} End of "addtogroup a53_64_mmu_apis".
*/

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#ifndef XIL_PRINTF_H
#define XIL_PRINTF_H
#ifdef __cplusplus
extern "C" {
#endif
#include <ctype.h>
#include <string.h>
#include <stdarg.h>
#include "xil_types.h"
#include "xparameters.h"
#include "bspconfig.h"
#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
#include "xen_console.h"
#endif
/*----------------------------------------------------*/
/* Use the following parameter passing structure to */
/* make xil_printf re-entrant. */
/*----------------------------------------------------*/
struct params_s;
/*---------------------------------------------------*/
/* The purpose of this routine is to output data the */
/* same as the standard printf function without the */
/* overhead most run-time libraries involve. Usually */
/* the printf brings in many kilobytes of code and */
/* that is unacceptable in most embedded systems. */
/*---------------------------------------------------*/
typedef char8* charptr;
typedef s32 (*func_ptr)(int c);
/* */
void xil_printf( const char8 *ctrl1, ...);
void print( const char8 *ptr);
extern void outbyte (char8 c);
extern char8 inbyte(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_sleeptimer.h
*
* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
* For sleep related functions that can be used across all Xilinx supported
* processors, please use xil_sleeptimer.h.
*
*
* <pre>
* MODIFICATION HISTORY :
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 6.6 srm 10/18/17 First Release.
*
* </pre>
*****************************************************************************/
#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
#define XIL_SLEEPTIMER_H /* by using protection macros */
/**************************** Include Files ********************************/
#include "xil_io.h"
#include "xparameters.h"
#include "bspconfig.h"
/************************** Constant Definitions *****************************/
#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
#define XSLEEP_TIMER_REG_SHIFT 32U
#define XSleep_ReadCounterVal Xil_In32
#define XCntrVal u32
#else
#define XSLEEP_TIMER_REG_SHIFT 16U
#define XSleep_ReadCounterVal Xil_In16
#define XCntrVal u16
#endif
#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
#define RST_LPD_IOU2 0xFF5E0238U
#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
#endif
#if defined (SLEEP_TIMER_BASEADDR)
/** @name Register Map
*
* Register offsets from the base address of the TTC device
*
* @{
*/
#define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
/**< Clock Control Register */
#define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
/**< Counter Control Register*/
#define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
/**< Current Counter Value */
/* @} */
/** @name Clock Control Register
* Clock Control Register definitions of TTC
* @{
*/
#define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
/**< Prescale enable */
/* @} */
/** @name Counter Control Register
* Counter Control Register definitions of TTC
* @{
*/
#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
/**< Disable the counter */
#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
/**< Reset counter */
/* @} */
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
void Xil_SleepTTCCommon(u32 delay, u64 frequency);
void XTime_StartTTCTimer();
#endif
#endif /* XIL_SLEEPTIMER_H */

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/******************************************************************************
*
* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_smc.h
*
* @addtogroup a53_64_smc_api Cortex A53 64bit EL1 Non-secure SMC Call
*
* Cortex A53 64bit EL1 Non-secure SMC Call provides a C wrapper for calling
* SMC from EL1 Non-secure application to request Secure monitor for secure
* services. SMC calling conventions should be followed.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.2 pkp 02/16/17 First release
* 6.4 mus 08/17/17 Added constant define for SMC ID , which is
* intended to read the version/idcode of the
* platform
*
*
* </pre>
*
******************************************************************************/
#ifndef XIL_SMC_H /* prevent circular inclusions */
#define XIL_SMC_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "bspconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#if EL1_NONSECURE
/************************** Constant Definitions ****************************/
#define SMC_FID_START 0xF2000000
#define SMC_FID_END 0xFF00FFFF
#define XILSP_INIT_DONE 0xF2000000
#define ARITH_SMC_FID 0xF2000001
#define PM_ASSERT_SMC_FID 0xC2000011
#define PM_GETSTATUS_SMC_FID 0xC2000012
#define MMIO_WRITE_SMC_FID 0xC2000013
#define MMIO_READ_SMC_FID 0xC2000014
#define GET_CHIPID_SMC_FID 0xC2000018
/**************************** Type Definitions ******************************/
typedef struct {
u64 Arg0;
u64 Arg1;
u64 Arg2;
u64 Arg3;
} XSmc_OutVar;
/***************** Macros (Inline Functions) Definitions ********************/
#define XSave_X8toX17() \
__asm__ __volatile__ ("stp X8, X9, [sp,#-0x10]!");\
__asm__ __volatile__ ("stp X10, X11, [sp,#-0x10]!");\
__asm__ __volatile__ ("stp X12, X13, [sp,#-0x10]!");\
__asm__ __volatile__ ("stp X14, X15, [sp,#-0x10]!");\
__asm__ __volatile__ ("stp X16, X17, [sp,#-0x10]!");
#define XRestore_X8toX17() \
__asm__ __volatile__ ("ldp X16, X17, [sp], #0x10");\
__asm__ __volatile__ ("ldp X14, X15, [sp], #0x10");\
__asm__ __volatile__ ("ldp X12, X13, [sp], #0x10");\
__asm__ __volatile__ ("ldp X10, X11, [sp], #0x10");\
__asm__ __volatile__ ("ldp X8, X9, [sp], #0x10");
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
XSmc_OutVar Xil_Smc(u64 FunctionID, u64 Arg1, u64 Arg2, u64 Arg3, u64 Arg4,
u64 Arg5, u64 Arg6, u64 Arg7);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_SMC_H */
/**
* @} End of "addtogroup a53_64_smc_api".
*/

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/******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testcache.h
*
* @addtogroup common_test_utils
* <h2>Cache test </h2>
* The xil_testcache.h file contains utility functions to test cache.
*
* @{
* <pre>
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 07/29/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
#define XIL_TESTCACHE_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern s32 Xil_TestDCacheRange(void);
extern s32 Xil_TestDCacheAll(void);
extern s32 Xil_TestICacheRange(void);
extern s32 Xil_TestICacheAll(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_test_utils".
*/

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/******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testio.h
*
* @addtogroup common_test_utils Test Utilities
* <h2>I/O test </h2>
* The xil_testio.h file contains utility functions to test endian related memory
* IO functions.
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00 hbm 08/05/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTIO_H /* prevent circular inclusions */
#define XIL_TESTIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#define XIL_TESTIO_DEFAULT 0
#define XIL_TESTIO_LE 1
#define XIL_TESTIO_BE 2
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_test_utils".
*/

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/******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmem.h
* @addtogroup common_test_utils
*
* <h2>Memory test</h2>
*
* The xil_testmem.h file contains utility functions to test memory.
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
* Following list describes the supported memory tests:
*
* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
*
* - XIL_TESTMEM_INCREMENT: This test
* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
* test value for memory.
*
* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
* uses a walking '1' as the test value for memory.
* @code
* location 1 = 0x00000001
* location 2 = 0x00000002
* ...
* @endcode
*
* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
* This test uses the inverse value of the walking ones test
* as the test value for memory.
* @code
* location 1 = 0xFFFFFFFE
* location 2 = 0xFFFFFFFD
* ...
*@endcode
*
* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
* This test uses the inverse of the address of the location under test
* as the test value for memory.
*
* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
* This test uses the provided patters as the test value for memory.
* If zero is provided as the pattern the test uses '0xDEADBEEF".
*
* @warning
* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
* have been set up.
* The address provided to the memory tests is not checked for
* validity except for the NULL case. It is possible to provide a code-space
* pointer for this test to start with and ultimately destroy executable code
* causing random failures.
*
* @note
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
* repeat on a boundry of a power of two making it more difficult to detect
* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
* tests suffer the same problem. Ideally, if large blocks of memory are to be
* tested, break them up into smaller regions of memory to allow the test
* patterns used not to repeat over the region tested.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 08/25/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
#define XIL_TESTMEM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* xutil_memtest defines */
#define XIL_TESTMEM_INIT_VALUE 1U
/** @name Memory subtests
* @{
*/
/**
* See the detailed description of the subtests in the file description.
*/
#define XIL_TESTMEM_ALLMEMTESTS 0x00U
#define XIL_TESTMEM_INCREMENT 0x01U
#define XIL_TESTMEM_WALKONES 0x02U
#define XIL_TESTMEM_WALKZEROS 0x03U
#define XIL_TESTMEM_INVERSEADDR 0x04U
#define XIL_TESTMEM_FIXEDPATTERN 0x05U
#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
/* @} */
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* xutil_testmem prototypes */
extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_test_utils".
*/

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_types.h
*
* @addtogroup common_types Basic Data types for Xilinx&reg; Software IP
*
* The xil_types.h file contains basic types for Xilinx software IP. These data types
* are applicable for all processors supported by Xilinx.
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
* Define LONG and ULONG datatypes and mask values
* </pre>
*
******************************************************************************/
#ifndef XIL_TYPES_H /* prevent circular inclusions */
#define XIL_TYPES_H /* by using protection macros */
#include <stdint.h>
#include <stddef.h>
/************************** Constant Definitions *****************************/
#ifndef TRUE
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
assigend to "IsReady" member of driver
instance to indicate that driver
instance is initialized and ready to use. */
#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
"IsStarted" member of driver instance
to indicate that driver instance is
started and it can be enabled. */
/* @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XBASIC_TYPES_H
/*
* guarded against xbasic_types.h.
*/
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
/** @}*/
#define __XUINT64__
typedef struct
{
u32 Upper;
u32 Lower;
} Xuint64;
/*****************************************************************************/
/**
* @brief Return the most significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The upper 32 bits of the 64 bit word.
*
******************************************************************************/
#define XUINT64_MSW(x) ((x).Upper)
/*****************************************************************************/
/**
* @brief Return the least significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The lower 32 bits of the 64 bit word.
*
******************************************************************************/
#define XUINT64_LSW(x) ((x).Lower)
#endif /* XBASIC_TYPES_H */
/*
* xbasic_types.h does not typedef s* or u64
*/
/** @{ */
typedef char char8;
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
typedef int64_t s64;
typedef uint64_t u64;
typedef int sint32;
typedef intptr_t INTPTR;
typedef uintptr_t UINTPTR;
typedef ptrdiff_t PTRDIFF;
/** @}*/
#if !defined(LONG) || !defined(ULONG)
typedef long LONG;
typedef unsigned long ULONG;
#endif
#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
#define ULONG64_LO_MASK ~ULONG64_HI_MASK
#else
#include <linux/types.h>
#endif
/** @{ */
/**
* This data type defines an interrupt handler for a device.
* The argument points to the instance of the component
*/
typedef void (*XInterruptHandler) (void *InstancePtr);
/**
* This data type defines an exception handler for a processor.
* The argument points to the instance of the component
*/
typedef void (*XExceptionHandler) (void *InstancePtr);
/**
* @brief Returns 32-63 bits of a number.
* @param n : Number being accessed.
* @return Bits 32-63 of number.
*
* @note A basic shift-right of a 64- or 32-bit quantity.
* Use this to suppress the "right shift count >= width of type"
* warning when that quantity is 32-bits.
*/
#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
/**
* @brief Returns 0-31 bits of a number
* @param n : Number being accessed.
* @return Bits 0-31 of number
*/
#define LOWER_32_BITS(n) ((u32)(n))
/************************** Constant Definitions *****************************/
#ifndef TRUE
#define TRUE 1U
#endif
#ifndef FALSE
#define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_types".
*/

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/* ### HEADER ### */
#ifndef __XIOU_SECURE_SLCR_H__
#define __XIOU_SECURE_SLCR_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XiouSecureSlcr Base Address
*/
#define XIOU_SECURE_SLCR_BASEADDR 0xFF240000UL
/**
* Register: XiouSecSlcrAxiWprtcn
*/
#define XIOU_SEC_SLCR_AXI_WPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT 25UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK 0x0e000000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT 22UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK 0x01c00000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 19UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00380000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 16UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00070000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 9UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000e00UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 6UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x000001c0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000038UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000007UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrAxiRprtcn
*/
#define XIOU_SEC_SLCR_AXI_RPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT 22UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK 0x01c00000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 19UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00380000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 16UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00070000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 9UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000e00UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 6UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x000001c0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000038UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000007UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrCtrl
*/
#define XIOU_SEC_SLCR_CTRL ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
#define XIOU_SEC_SLCR_CTRL_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrIsr
*/
#define XIOU_SEC_SLCR_ISR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
#define XIOU_SEC_SLCR_ISR_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrImr
*/
#define XIOU_SEC_SLCR_IMR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
#define XIOU_SEC_SLCR_IMR_RSTVAL 0x00000001UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XiouSecSlcrIer
*/
#define XIOU_SEC_SLCR_IER ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
#define XIOU_SEC_SLCR_IER_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrIdr
*/
#define XIOU_SEC_SLCR_IDR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
#define XIOU_SEC_SLCR_IDR_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrItr
*/
#define XIOU_SEC_SLCR_ITR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
#define XIOU_SEC_SLCR_ITR_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XIOU_SECURE_SLCR_H__ */

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/******************************************************************************
*
* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xipipsu.h
* @addtogroup ipipsu_v2_3
* @{
* @details
*
* This is the header file for implementation of IPIPSU driver.
* Inter Processor Interrupt (IPI) is used for communication between
* different processors on ZynqMP SoC. Each IPI register set has Trigger, Status
* and Observation registers for communication between processors. Each IPI path
* has a 32 byte buffer associated with it and these buffers are located in the
* XPPU RAM. This driver supports the following operations:
*
* - Trigger IPIs to CPUs on the SoC
* - Write and Read Message buffers
* - Read the status of Observation Register to get status of Triggered IPI
* - Enable/Disable IPIs from selected Masters
* - Read the Status register to get the source of an incoming IPI
*
* <b>Initialization</b>
* The config data for the driver is loaded and is based on the HW build. The
* XIpiPsu_Config data structure contains all the data related to the
* IPI driver instance and also teh available Target CPUs.
*
* <b>Sending an IPI</b>
* The following steps can be followed to send an IPI:
* - Write the Message into Message Buffer using XIpiPsu_WriteMessage()
* - Trigger IPI using XIpiPsu_TriggerIpi()
* - Wait for Ack using XIpiPsu_PollForAck()
* - Read response using XIpiPsu_ReadMessage()
*
* @note XIpiPsu_GetObsStatus() before sending an IPI to ensure that the
* previous IPI was serviced by the target
*
* <b>Receiving an IPI</b>
* To receive an IPI, the following sequence can be followed:
* - Register an interrupt handler for the IPIs interrupt ID
* - Enable the required sources using XIpiPsu_InterruptEnable()
* - In the interrupt handler, Check for source using XIpiPsu_GetInterruptStatus
* - Read the message form source using XIpiPsu_ReadMessage()
* - Write the response using XIpiPsu_WriteMessage()
* - Ack the IPI using XIpiPsu_ClearInterruptStatus()
*
* @note XIpiPsu_Reset can be used at startup to clear the status and
* disable all sources
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- --------------------------------------------------
* 2.2 ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* kvn 02/17/17 Add support for updating ConfigTable at run time
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 2.3 ms 04/11/17 Modified tcl file to add suffix U for all macro
* definitions of ipipsu in xparameters.h
* </pre>
*
*****************************************************************************/
/*****************************************************************************/
#ifndef XIPIPSU_H_
#define XIPIPSU_H_
/***************************** Include Files *********************************/
#include "xil_io.h"
#include "xstatus.h"
#include "xipipsu_hw.h"
/************************** Constant Definitions *****************************/
#define XIPIPSU_BUF_TYPE_MSG (0x00000001U)
#define XIPIPSU_BUF_TYPE_RESP (0x00000002U)
#define XIPIPSU_MAX_MSG_LEN XIPIPSU_MSG_BUF_SIZE
/**************************** Type Definitions *******************************/
/**
* Data structure used to refer IPI Targets
*/
typedef struct {
u32 Mask; /**< Bit Mask for the target */
u32 BufferIndex; /**< Buffer Index used for calculating buffer address */
} XIpiPsu_Target;
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u32 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 BitMask; /**< BitMask to be used to identify this CPU */
u32 BufferIndex; /**< Index of the IPI Message Buffer */
u32 IntId; /**< Interrupt ID on GIC **/
u32 TargetCount; /**< Number of available IPI Targets */
XIpiPsu_Target TargetList[XIPIPSU_MAX_TARGETS] ; /** < List of IPI Targets */
} XIpiPsu_Config;
/**
* The XIpiPsu driver instance data. The user is required to allocate a
* variable of this type for each IPI device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XIpiPsu_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
u32 Options; /**< Options set in the device */
} XIpiPsu;
/***************** Macros (Inline Functions) Definitions *********************/
/**
*
* Read the register specified by the base address and offset
*
* @param BaseAddress is the base address of the IPI instance
* @param RegOffset is the offset of the register relative to base
*
* @return Value of the specified register
* @note
* C-style signature
* u32 XIpiPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XIpiPsu_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
/****************************************************************************/
/**
*
* Write a value into a register specified by base address and offset
*
* @param BaseAddress is the base address of the IPI instance
* @param RegOffset is the offset of the register relative to base
* @param Data is a 32-bit value that is to be written into the specified register
*
* @note
* C-style signature
* void XIpiPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XIpiPsu_WriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values of individual CPU masks
*
* @note
* C-style signature
* void XIpiPsu_InterruptEnable(XIpiPsu *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XIpiPsu_InterruptEnable(InstancePtr, Mask) \
XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
XIPIPSU_IER_OFFSET, \
((Mask) & XIPIPSU_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be disabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values of individual CPU masks
*
* @note
* C-style signature
* void XIpiPsu_InterruptDisable(XIpiPsu *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XIpiPsu_InterruptDisable(InstancePtr, Mask) \
XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
XIPIPSU_IDR_OFFSET, \
((Mask) & XIPIPSU_ALL_MASK));
/****************************************************************************/
/**
*
* Get the <i>STATUS REGISTER</i> of the current IPI instance.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @return Returns the Interrupt Status register(ISR) contents
* @note User needs to parse this 32-bit value to check the source CPU
* C-style signature
* u32 XIpiPsu_GetInterruptStatus(XIpiPsu *InstancePtr)
*
*****************************************************************************/
#define XIpiPsu_GetInterruptStatus(InstancePtr) \
XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
XIPIPSU_ISR_OFFSET)
/****************************************************************************/
/**
*
* Clear the <i>STATUS REGISTER</i> of the current IPI instance.
* The corresponding interrupt status for
* each bit set to 1 in <i>Mask</i>, will be cleared
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask corresponding to the source CPU*
*
* @note This function should be used after handling the IPI.
* Clearing the status will automatically clear the corresponding bit in
* OBSERVATION register of Source CPU
* C-style signature
* void XIpiPsu_ClearInterruptStatus(XIpiPsu *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XIpiPsu_ClearInterruptStatus(InstancePtr, Mask) \
XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
XIPIPSU_ISR_OFFSET, \
((Mask) & XIPIPSU_ALL_MASK));
/****************************************************************************/
/**
*
* Get the <i>OBSERVATION REGISTER</i> of the current IPI instance.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @return Returns the Observation register(OBS) contents
* @note User needs to parse this 32-bit value to check the status of
* individual CPUs
* C-style signature
* u32 XIpiPsu_GetObsStatus(XIpiPsu *InstancePtr)
*
*****************************************************************************/
#define XIpiPsu_GetObsStatus(InstancePtr) \
XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
XIPIPSU_OBS_OFFSET)
/****************************************************************************/
/************************** Function Prototypes *****************************/
/* Static lookup function implemented in xipipsu_sinit.c */
XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId);
/* Interface Functions implemented in xipipsu.c */
XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
UINTPTR EffectiveAddress);
void XIpiPsu_Reset(XIpiPsu *InstancePtr);
XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask);
XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
u32 TimeOutCount);
XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
u32 MsgLength, u8 BufferType);
XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
u32 MsgLength, u8 BufferType);
void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr);
#endif /* XIPIPSU_H_ */
/** @} */

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/******************************************************************************
*
* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/**
*
* @file xipipsu_hw.h
* @addtogroup ipipsu_v2_3
* @{
*
* This file contains macro definitions for low level HW related params
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------.
* 1.0 mjr 03/15/15 First release
* 2.1 kvn 05/05/16 Modified code for MISRA-C:2012 Compliance
*
* </pre>
*
******************************************************************************/
#ifndef XIPIPSU_HW_H_ /* prevent circular inclusions */
#define XIPIPSU_HW_H_ /* by using protection macros */
/************************** Constant Definitions *****************************/
/* Message RAM related params */
#define XIPIPSU_MSG_RAM_BASE 0xFF990000U
#define XIPIPSU_MSG_BUF_SIZE 8U /* Size in Words */
#define XIPIPSU_MAX_BUFF_INDEX 7U
/* EIGHT pairs of TWO buffers(msg+resp) of THIRTY TWO bytes each */
#define XIPIPSU_BUFFER_OFFSET_GROUP (8U * 2U * 32U)
#define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U)
#define XIPIPSU_BUFFER_OFFSET_RESPONSE (32U)
/* Number of IPI slots enabled on the device */
#define XIPIPSU_MAX_TARGETS XPAR_XIPIPSU_NUM_TARGETS
/* Register Offsets for each member of IPI Register Set */
#define XIPIPSU_TRIG_OFFSET 0x00U
#define XIPIPSU_OBS_OFFSET 0x04U
#define XIPIPSU_ISR_OFFSET 0x10U
#define XIPIPSU_IMR_OFFSET 0x14U
#define XIPIPSU_IER_OFFSET 0x18U
#define XIPIPSU_IDR_OFFSET 0x1CU
/* MASK of all valid IPI bits in above registers */
#define XIPIPSU_ALL_MASK 0x0F0F0301U
#endif /* XIPIPSU_HW_H_ */
/** @} */

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/* ### HEADER ### */
#ifndef __XLPD_SLCR_SECURE_H__
#define __XLPD_SLCR_SECURE_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XlpdSlcrSecure Base Address
*/
#define XLPD_SLCR_SECURE_BASEADDR 0xFF4B0000UL
/**
* Register: XlpdSlcrSecCtrl
*/
#define XLPD_SLCR_SEC_CTRL ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
#define XLPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecIsr
*/
#define XLPD_SLCR_SEC_ISR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
#define XLPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecImr
*/
#define XLPD_SLCR_SEC_IMR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
#define XLPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XlpdSlcrSecIer
*/
#define XLPD_SLCR_SEC_IER ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
#define XLPD_SLCR_SEC_IER_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecIdr
*/
#define XLPD_SLCR_SEC_IDR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
#define XLPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecItr
*/
#define XLPD_SLCR_SEC_ITR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
#define XLPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecRpu
*/
#define XLPD_SLCR_SEC_RPU ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
#define XLPD_SLCR_SEC_RPU_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT 1UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH 1UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK 0x00000002UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL 0x0UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT 0UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH 1UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK 0x00000001UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecAdma
*/
#define XLPD_SLCR_SEC_ADMA ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL )
#define XLPD_SLCR_SEC_ADMA_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT 0UL
#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH 8UL
#define XLPD_SLCR_SEC_ADMA_TZ_MASK 0x000000ffUL
#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecSafetyChk
*/
#define XLPD_SLCR_SEC_SAFETY_CHK ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT 0UL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH 32UL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK 0xffffffffUL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecUsb
*/
#define XLPD_SLCR_SEC_USB ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL )
#define XLPD_SLCR_SEC_USB_RSTVAL 0x00000003UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT 1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH 1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK 0x00000002UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL 0x1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT 0UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH 1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK 0x00000001UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL 0x1UL
#ifdef __cplusplus
}
#endif
#endif /* __XLPD_SLCR_SECURE_H__ */

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