freertos: release the generic version source code
freertos runs on the second core (small one) of the CPU
This commit is contained in:
carbon
423
freertos/cvitek/arch/arm64/src/xil_exception.c
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423
freertos/cvitek/arch/arm64/src/xil_exception.c
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/******************************************************************************
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*
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* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file xil_exception.c
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*
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* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
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* Handler.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- -------- -------- -----------------------------------------------
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* 5.2 pkp 28/05/15 First release
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* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
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* processors and added Xil_UndefinedExceptionHandler
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* for a53 32 bit and r5 as well.
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* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to
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* fix the warnings.
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* </pre>
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*
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*****************************************************************************/
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/***************************** Include Files ********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_exception.h"
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#include "xpseudo_asm.h"
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#include "xdebug.h"
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/************************** Constant Definitions ****************************/
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/**************************** Type Definitions ******************************/
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typedef struct {
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Xil_ExceptionHandler Handler;
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void *Data;
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} XExc_VectorTableEntry;
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/***************** Macros (Inline Functions) Definitions ********************/
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/************************** Function Prototypes *****************************/
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static void Xil_ExceptionNullHandler(void *Data);
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/************************** Variable Definitions *****************************/
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/*
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* Exception vector table to store handlers for each exception vector.
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*/
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#if defined(__aarch64__)
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XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = {
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{ Xil_ExceptionNullHandler, NULL }, { Xil_SyncAbortHandler, NULL },
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{ Xil_ExceptionNullHandler, NULL }, { Xil_ExceptionNullHandler, NULL },
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{ Xil_SErrorAbortHandler, NULL },
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};
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#else
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XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = {
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{ Xil_ExceptionNullHandler, NULL },
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{ Xil_UndefinedExceptionHandler, NULL },
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{ Xil_ExceptionNullHandler, NULL },
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{ Xil_PrefetchAbortHandler, NULL },
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{ Xil_DataAbortHandler, NULL },
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{ Xil_ExceptionNullHandler, NULL },
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{ Xil_ExceptionNullHandler, NULL },
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};
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#endif
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#if !defined(__aarch64__)
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u32 DataAbortAddr; /* Address of instruction causing data abort */
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u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
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u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined
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exception */
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#endif
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/*****************************************************************************/
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/****************************************************************************/
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/**
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*
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* This function is a stub Handler that is the default Handler that gets called
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* if the application has not setup a Handler for a specific exception. The
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* function interface has to match the interface specified for a Handler even
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* though none of the arguments are used.
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*
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* @param Data is unused by this function.
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*
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* @return None.
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*
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* @note None.
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*
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*****************************************************************************/
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static void Xil_ExceptionNullHandler(void *Data)
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{
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(void)Data;
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DieLoop:
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goto DieLoop;
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}
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/****************************************************************************/
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/**
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* @brief The function is a common API used to initialize exception handlers
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* across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
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* and Cortex-A9, the exception handlers are being initialized
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* statically and this function does not do anything.
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* However, it is still present to take care of backward compatibility
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* issues (in earlier versions of BSPs, this API was being used to
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* initialize exception handlers).
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*
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* @param None.
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*
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* @return None.
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*
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* @note None.
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*
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*****************************************************************************/
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void Xil_ExceptionInit(void)
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{
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return;
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}
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/*****************************************************************************/
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/**
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* @brief Register a handler for a specific exception. This handler is being
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* called when the processor encounters the specified exception.
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*
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* @param exception_id contains the ID of the exception source and should
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* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
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* See xil_exception.h for further information.
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* @param Handler to the Handler for that exception.
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* @param Data is a reference to Data that will be passed to the
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* Handler when it gets called.
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void Xil_ExceptionRegisterHandler(u32 Exception_id,
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Xil_ExceptionHandler Handler, void *Data)
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{
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XExc_VectorTable[Exception_id].Handler = Handler;
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XExc_VectorTable[Exception_id].Data = Data;
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}
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/*****************************************************************************/
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/**
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*
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* @brief Removes the Handler for a specific exception Id. The stub Handler
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* is then registered for this exception Id.
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*
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* @param exception_id contains the ID of the exception source and should
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* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
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* See xil_exception.h for further information.
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void Xil_ExceptionRemoveHandler(u32 Exception_id)
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{
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Xil_ExceptionRegisterHandler(Exception_id, Xil_ExceptionNullHandler,
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NULL);
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}
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#if defined(__aarch64__)
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/*****************************************************************************/
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/**
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*
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* Default Synchronous abort handler which prints a debug message on console if
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* Debug flag is enabled
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*
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* @param None
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void Xil_SyncAbortHandler(void *CallBackRef)
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{
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(void)CallBackRef;
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xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
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while (1) {
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;
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}
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}
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/*****************************************************************************/
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/**
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*
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* Default SError abort handler which prints a debug message on console if
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* Debug flag is enabled
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*
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* @param None
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void Xil_SErrorAbortHandler(void *CallBackRef)
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{
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(void)CallBackRef;
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xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
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while (1) {
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;
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}
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}
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#else
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/*****************************************************************************/
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/*
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*
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* Default Data abort handler which prints data fault status register through
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* which information about data fault can be acquired
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*
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* @param None
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void Xil_DataAbortHandler(void *CallBackRef)
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{
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(void)CallBackRef;
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#ifdef DEBUG
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u32 FaultStatus;
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xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
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#ifdef __GNUC__
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FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
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#elif defined(__ICCARM__)
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mfcp(XREG_CP15_DATA_FAULT_STATUS, FaultStatus);
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#else
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{
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volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
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FaultStatus = Reg;
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}
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#endif
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xdbg_printf(XDBG_DEBUG_GENERAL,
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"Data abort with Data Fault Status Register %lx\n",
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FaultStatus);
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xdbg_printf(XDBG_DEBUG_GENERAL,
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"Address of Instruction causing Data abort %lx\n",
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DataAbortAddr);
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#endif
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while (1) {
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;
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}
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}
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/*****************************************************************************/
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/*
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*
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* Default Prefetch abort handler which prints prefetch fault status register through
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* which information about instruction prefetch fault can be acquired
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*
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* @param None
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void Xil_PrefetchAbortHandler(void *CallBackRef)
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{
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(void)CallBackRef;
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#ifdef DEBUG
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u32 FaultStatus;
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xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
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#ifdef __GNUC__
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FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
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#elif defined(__ICCARM__)
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mfcp(XREG_CP15_INST_FAULT_STATUS, FaultStatus);
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#else
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{
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volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
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FaultStatus = Reg;
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}
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#endif
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xdbg_printf(
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XDBG_DEBUG_GENERAL,
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"Prefetch abort with Instruction Fault Status Register %lx\n",
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FaultStatus);
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xdbg_printf(XDBG_DEBUG_GENERAL,
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"Address of Instruction causing Prefetch abort %lx\n",
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PrefetchAbortAddr);
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#endif
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while (1) {
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;
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}
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}
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/*****************************************************************************/
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/*
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*
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* Default undefined exception handler which prints address of the undefined
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* instruction if debug prints are enabled
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*
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* @param None
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void Xil_UndefinedExceptionHandler(void *CallBackRef)
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{
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(void)CallBackRef;
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xdbg_printf(XDBG_DEBUG_GENERAL,
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"Address of the undefined instruction %lx\n",
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UndefinedExceptionAddr);
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while (1) {
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;
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}
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}
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#endif
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/*****************************************************************************/
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/*
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* @brief Dump the register value in FreeRTOS abort.
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*
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* STP Xt1, Xt2, [Xn|SP, #imm]! ; 64-bit general registers, Pre-index.
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* portASM.S use pre-index STP to save all the registers.
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* In pre-index, STP Xt1, Xt2, [SP, #imm]! would have following action.
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* a. SP = SP + #imm
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* b. save Xt1 to MEM[SP]
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* c. save Xt2 to MEM[SP+8]
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*
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* All the register is needed to save by STP instructions in portASM.S.
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* 1. 8x32 bytes X0~X31
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* 2. 8x2 bytes ELR_EL1 and SPSR_EL1
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* 3. 8x2 bytes FPU context and critical section nesting depth
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*
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* @param[in] pt_regs A pointer point to SP for all the register value in stack.
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* @param[in] len Frame size including above 1. 2. 3. .
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*
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* @return None.
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*
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* @note Need to check the register order in memory.
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* For example, SP is 0x2b0
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* STP X0, X1, [SP, #-0x10]!
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* STP X2, X3, [SP, #-0x10]!
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* STP X4, X5, [SP, #-0x10]!
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* => memory layout:
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* offset 0x0 0x8
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* ====================
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* 0x280 X4 X5
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* 0x290 X2 X3
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* 0x2a0 X0 X1
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* 0x2b0
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*
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* From high address to low address, register order is
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* X1-> X0-> X3-> X2-> X5-> X4....
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*
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****************************************************************************/
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void vApplicationPrintRegister(size_t *pt_regs, int len)
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{
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int i;
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/* One time for 16 bytes from STP in portASM.S */
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for (i = 0; i < len / 8; i = i + 2) {
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pt_regs = pt_regs - 2;
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switch (i) {
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case 0 ... 9:
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printf("x%2d: ", i);
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printf("%lx ", *(pt_regs));
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printf("x%2d: ", i + 1);
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printf("%lx \n", *(pt_regs + 1));
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break;
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case 10 ... 31:
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printf("x%2d: ", i);
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printf("%lx ", *(pt_regs));
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printf("x%2d: ", i + 1);
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printf("%lx \n", *(pt_regs + 1));
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break;
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case 32:
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printf("ELR_EL1: ");
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printf("%lx \n", *(pt_regs));
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printf("SPSR_EL1: ");
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printf("%lx \n", *(pt_regs + 1));
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break;
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case 34:
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printf("FPU context: ");
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printf("%lx \n", *(pt_regs));
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printf("critical section nesting depth: ");
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printf("%lx \n", *(pt_regs + 1));
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break;
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}
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}
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}
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