Demo/Linux_Drivers
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

middleware: weekly update 2023-09-06

Browse Source 
update .gitignore file
1.cv1812h hw_mcu st7789v3 support 2.add sample_panel.
[sensor]cv4001 add wdr mode
[refactor](PQbin) refactor md5 value calculation way
[feat](fastboot): Renew fastboot interface
[sensor]drop frame in flip
[cv181x][vo]Bring up lvds panel.
[sensor]modify vts_reg value and def_vts

Change-Id: Ie9ebc4b4a969218cad8a6f4a7a9d5d65e54f155a
This commit is contained in:
forum_service
2023-09-11 16:27:17 +08:00
committed by carbon
parent ebdd1dbfcf
commit f6d4f57c24
264 changed files with 2748 additions and 1221 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
.gitignore vendored Normal file
View File

@ -0,0 +1,3 @@
/install/
__pycache__
host-tools

3
middleware/v2/.gitignore vendored
View File

@ -6,6 +6,8 @@
*.dwo
lib
ko
ko_shrink
bin
include
tags
@ -35,6 +37,7 @@ sample/osdc/sample_osdc
sample/scene_auto/sample_scene_auto
sample/sensor_test/sensor_test
sample/tp2863_tp2803/sample_test_tp2863_tp2803
sample/sample_panel/sample_panel
self_test/cvi_test/cvi_test
self_test/cvi_test/res

1
middleware/v2/component/isp/sensor.mk
View File

@ -68,6 +68,7 @@ sensor-$(CONFIG_SENSOR_GCORE_GC2145) += gcore_gc2145
sensor-$(CONFIG_SENSOR_GCORE_GC4023) += gcore_gc4023
sensor-$(CONFIG_SENSOR_GCORE_GC4653) += gcore_gc4653
sensor-$(CONFIG_SENSOR_IMGDS_MIS2008) += imgds_mis2008
sensor-$(CONFIG_SENSOR_IMGDS_MIS2008_1L) += imgds_mis2008_1L
sensor-$(CONFIG_SENSOR_NEXTCHIP_N5) += nextchip_n5
sensor-$(CONFIG_SENSOR_NEXTCHIP_N6) += nextchip_n6
sensor-$(CONFIG_SENSOR_OV_OS04A10) += ov_os04a10

391
middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos.c
View File

@ -66,17 +66,24 @@ static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
/*****CV4001 Lines Range*****/
#define CV4001_FULL_LINES_MAX (0xfffff)
#define CV4001_FULL_LINES_MAX (0xfffff / 2)//liner mode: vts_reg value is double real_vts
#define CV4001_FULL_LINES_MAX_2TO1_WDR (0xfffff / 4)//wdr mode: four
/*****CV4001 Register Address*****/
#define CV4001_EXP_ADDR0 0x3062 //bit[19:16]
#define CV4001_EXP_ADDR1 0x3061
#define CV4001_EXP_ADDR2 0x3060
#define CV4001_EXP1_ADDR0 0x3062 //bit[19:16]
#define CV4001_EXP1_ADDR1 0x3061
#define CV4001_EXP1_ADDR2 0x3060
#define CV4001_EXP2_ADDR0 0x3066
#define CV4001_EXP2_ADDR1 0x3065
#define CV4001_EXP2_ADDR2 0x3064
#define CV4001_AGAIN_ADDR 0x3180 //bit[7:0]
#define CV4001_AGAIN1_ADDR 0x3180 //bit[7:0]
#define CV4001_AGAIN2_ADDR 0x3181 //bit[7:0]
#define CV4001_DGAIN_H_ADDR 0x3179 //bit[15:8]
#define CV4001_DGAIN_L_ADDR 0x3178 //bit[7:0]
#define CV4001_DGAIN1_H_ADDR 0x3179 //bit[15:8]
#define CV4001_DGAIN1_L_ADDR 0x3178 //bit[7:0]
#define CV4001_DGAIN2_H_ADDR 0x317B //bit[15:8]
#define CV4001_DGAIN2_L_ADDR 0x317A //bit[7:0]
#define CV4001_VTS_ADDR0 0x302A //bit[19:16]
#define CV4001_VTS_ADDR1 0x3029
@ -84,26 +91,35 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
#define CV4001_FLIP_MIRROR_ADDR 0x3034
#define CV4001_RES_IS_1440P(w, h) ((w) <= 2560 && (h) <= 1440)
#define CV4001_RES_IS_1440P(w, h) ((w) == 2560 && (h) == 1440)
static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
const CV4001_MODE_S *pstMode;
CVI_U32 FpsMax;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astCV4001_mode[pstSnsState->u8ImgMode];
FpsMax = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MaxFps;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32FlickerFreq = 50 * 256;
pstAeSnsDft->u32FullLinesMax = CV4001_FULL_LINES_MAX;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 25);
pstAeSnsDft->u32FullLinesMax = (pstSnsState->enWDRMode == WDR_MODE_NONE) ?
CV4001_FULL_LINES_MAX : CV4001_FULL_LINES_MAX_2TO1_WDR;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * FpsMax);
pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
@ -112,27 +128,32 @@ static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSns
pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
if (g_au32LinesPer500ms[ViPipe] == 0)
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 25 / 2;
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * FpsMax / 2;
else
pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
switch (pstSnsState->enWDRMode) {
default:
case WDR_MODE_NONE: /*linear mode*/
pstAeSnsDft->f32Fps = g_astCV4001_mode[CV4001_MODE_2560X1440P25].f32MaxFps;
pstAeSnsDft->f32MinFps = g_astCV4001_mode[CV4001_MODE_2560X1440P25].f32MinFps;
pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xd;
pstAeSnsDft->au8HistThresh[1] = 0x28;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxAgain = 16384;
pstAeSnsDft->u32MinAgain = 1024;
pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max;
pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u32Max;
pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u32Min;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = 16384;
pstAeSnsDft->u32MinDgain = 1024;
pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u32Max;
pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u32Max;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
@ -142,14 +163,52 @@ static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSns
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ?
g_au32InitExposure[ViPipe] : g_astCV4001_mode[CV4001_MODE_2560X1440P25].stExp[0].u16Def;
g_au32InitExposure[ViPipe] : pstMode->stExp[0].u16Def;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstAeSnsDft->u32MinIntTime = g_astCV4001_mode[CV4001_MODE_2560X1440P25].stExp[0].u16Min;
break;
case WDR_MODE_2To1_LINE:
pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xC;
pstAeSnsDft->au8HistThresh[1] = 0x18;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max;
pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u32Max;
pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u32Min;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u32Max;
pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u32Min;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
pstAeSnsDft->u32MaxISPDgainTarget = 16 << pstAeSnsDft->u32ISPDgainShift;
pstAeSnsDft->u32InitAESpeed = 64;
pstAeSnsDft->u32InitAETolerance = 5;
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ?
g_au32InitExposure[ViPipe] : pstMode->stExp[0].u16Def;
if (genFSWDRMode[ViPipe] == ISP_FSWDR_LONG_FRAME_MODE) {
pstAeSnsDft->u8AeCompensation = 64;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
} else {
pstAeSnsDft->u8AeCompensation = 40;
pstAeSnsDft->enAeExpMode = AE_EXP_LOWLIGHT_PRIOR;
}
break;
}
CVI_TRACE_SNS(CVI_DBG_INFO, "again[%d, %d], dgain[%d, %d]\n",
pstAeSnsDft->u32MinAgain, pstAeSnsDft->u32MaxAgain, pstAeSnsDft->u32MinDgain, pstAeSnsDft->u32MaxDgain);
return CVI_SUCCESS;
}
@ -168,11 +227,12 @@ static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32Vts = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
u32Vts = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
f32MaxFps = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MaxFps;
f32MinFps = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MinFps;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
@ -180,17 +240,26 @@ static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX) ? CV4001_FULL_LINES_MAX : u32VMAX;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_VTS_0].u32Data = ((u32VMAX & 0xFF0000) >> 16);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_1].u32Data = ((u32VMAX & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_2].u32Data = (u32VMAX & 0xFF);
u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX) ?
CV4001_FULL_LINES_MAX : u32VMAX;
pstSnsRegsInfo->astI2cData[LINEAR_VTS_0].u32Data = (((u32VMAX * 2) & 0xFF0000) >> 16);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_1].u32Data = (((u32VMAX * 2) & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_2].u32Data = ((u32VMAX * 2) & 0xFF);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX_2TO1_WDR) ?
CV4001_FULL_LINES_MAX_2TO1_WDR : u32VMAX;
pstSnsRegsInfo->astI2cData[WDR2_VTS_0].u32Data = (((u32VMAX * 4) & 0xFF0000) >> 16);
pstSnsRegsInfo->astI2cData[WDR2_VTS_1].u32Data = (((u32VMAX * 4) & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[WDR2_VTS_2].u32Data = ((u32VMAX * 4) & 0xFF);
}
pstSnsState->u32FLStd = u32VMAX;
pstAeSnsDft->f32Fps = f32Fps;
@ -209,20 +278,37 @@ static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_S32 Cur_Vts;
CVI_S32 Reg_IntTime;
CVI_S32 Reg_IntTime1;
CVI_S32 Reg_IntTime2;
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(u32IntTime);
Cur_Vts = pstSnsState->u32FLStd;
Reg_IntTime = ((Cur_Vts / 2) - u32IntTime[0]) * 2;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = ((Reg_IntTime >> 16) & 0x0F);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = ((Reg_IntTime >> 8) & 0xFF);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_2].u32Data = (Reg_IntTime & 0xFF);
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
Reg_IntTime1 = (pstSnsState->u32FLStd - u32IntTime[0]) * 2;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = ((Reg_IntTime1 >> 16) & 0x0F);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = ((Reg_IntTime1 >> 8) & 0xFF);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_2].u32Data = (Reg_IntTime1 & 0xFF);
} else {
/* short exposure */
pstSnsState->au32WDRIntTime[0] = u32IntTime[0];//?
/* long exposure */
pstSnsState->au32WDRIntTime[1] = u32IntTime[1];
Reg_IntTime1 = (pstSnsState->u32FLStd - u32IntTime[1]) * 4;//u32IntTime[1] long exposure
Reg_IntTime2 = (pstSnsState->u32FLStd - u32IntTime[0]) * 4 + 2;//u32IntTime[0] short exposure
pstSnsRegsInfo->astI2cData[WDR2_EXP1_0].u32Data = ((Reg_IntTime1 >> 16) & 0x0F);
pstSnsRegsInfo->astI2cData[WDR2_EXP1_1].u32Data = ((Reg_IntTime1 >> 8) & 0xFF);
pstSnsRegsInfo->astI2cData[WDR2_EXP1_2].u32Data = (Reg_IntTime1 & 0xFF);
pstSnsRegsInfo->astI2cData[WDR2_EXP2_0].u32Data = ((Reg_IntTime2 >> 16) & 0x0F);
pstSnsRegsInfo->astI2cData[WDR2_EXP2_1].u32Data = ((Reg_IntTime2 >> 8) & 0xFF);
pstSnsRegsInfo->astI2cData[WDR2_EXP2_2].u32Data = (Reg_IntTime2 & 0xFF);
}
return CVI_SUCCESS;
}
@ -340,8 +426,13 @@ static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_H].u32Data = (u32Dgain >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_L].u32Data = (u32Dgain & 0xFF);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
pstSnsRegsInfo->astI2cData[WDR2_AGAIN1].u32Data = u32Again;
pstSnsRegsInfo->astI2cData[WDR2_AGAIN2].u32Data = u32Again;
pstSnsRegsInfo->astI2cData[WDR2_DGAIN1_H].u32Data = (u32Dgain >> 8);
pstSnsRegsInfo->astI2cData[WDR2_DGAIN1_L].u32Data = (u32Dgain & 0xFF);
pstSnsRegsInfo->astI2cData[WDR2_DGAIN2_H].u32Data = (u32Dgain >> 8);
pstSnsRegsInfo->astI2cData[WDR2_DGAIN2_L].u32Data = (u32Dgain & 0xFF);
}
return CVI_SUCCESS;
}
@ -349,14 +440,62 @@ static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu
static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio,
CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime)
{
UNUSED(ViPipe);
UNUSED(u16ManRatioEnable);
UNUSED(au32Ratio);
UNUSED(au32IntTimeMax);
UNUSED(au32IntTimeMin);
UNUSED(pu32LFMaxIntTime);
CVI_U32 u32IntTimeMaxTmp = 0, u32IntTimeMaxTmp0 = 0;
CVI_U32 u32RatioTmp = 0x40;
CVI_U32 u32ShortTimeMinLimit = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(au32Ratio);
CMOS_CHECK_POINTER(au32IntTimeMax);
CMOS_CHECK_POINTER(au32IntTimeMin);
CMOS_CHECK_POINTER(pu32LFMaxIntTime);
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32ShortTimeMinLimit = 1;
/*
* Long exp + Short exp < VTS
*/
u32IntTimeMaxTmp0 = ((pstSnsState->au32FL[1] - 1 - g_astCV4001_mode[pstSnsState->u8ImgMode].u32IspResTime -
pstSnsState->au32WDRIntTime[0]) * 0x40) / DIV_0_TO_1(au32Ratio[0]);
u32IntTimeMaxTmp = ((pstSnsState->au32FL[0] - 1 - g_astCV4001_mode[pstSnsState->u8ImgMode].u32IspResTime)
* 0x40) / DIV_0_TO_1(au32Ratio[0] + 0x40);
u32IntTimeMaxTmp = (u32IntTimeMaxTmp > u32IntTimeMaxTmp0) ? u32IntTimeMaxTmp0 : u32IntTimeMaxTmp;
u32IntTimeMaxTmp = (!u32IntTimeMaxTmp) ? u32ShortTimeMinLimit : u32IntTimeMaxTmp;
if (u32IntTimeMaxTmp >= u32ShortTimeMinLimit) {
if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
au32IntTimeMax[0] = u32IntTimeMaxTmp;
au32IntTimeMax[1] = au32IntTimeMax[0] * au32Ratio[0] >> 6;
au32IntTimeMax[2] = au32IntTimeMax[1] * au32Ratio[1] >> 6;
au32IntTimeMax[3] = au32IntTimeMax[2] * au32Ratio[2] >> 6;
au32IntTimeMin[0] = u32ShortTimeMinLimit;
au32IntTimeMin[1] = au32IntTimeMin[0] * au32Ratio[0] >> 6;
au32IntTimeMin[2] = au32IntTimeMin[1] * au32Ratio[1] >> 6;
au32IntTimeMin[3] = au32IntTimeMin[2] * au32Ratio[2] >> 6;
} else {
}
} else {
if (u16ManRatioEnable) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Manaul ExpRatio is too large!\n");
return CVI_FAILURE;
}
u32IntTimeMaxTmp = u32ShortTimeMinLimit;
if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
u32RatioTmp = 0xFFF;
au32IntTimeMax[0] = u32IntTimeMaxTmp;
au32IntTimeMax[1] = au32IntTimeMax[0] * u32RatioTmp >> 6;
} else {
}
au32IntTimeMin[0] = au32IntTimeMax[0];
au32IntTimeMin[1] = au32IntTimeMax[1];
au32IntTimeMin[2] = au32IntTimeMax[2];
au32IntTimeMin[3] = au32IntTimeMax[3];
}
CVI_TRACE_SNS(CVI_DBG_DEBUG, "sexp[%d, %d], lexp[%d, %d], ratio:%d\n",
au32IntTimeMin[0], au32IntTimeMax[0], au32IntTimeMin[1], au32IntTimeMax[1], au32Ratio[0]);
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode\n");
return CVI_SUCCESS;
}
@ -390,8 +529,9 @@ static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
{
CMOS_CHECK_POINTER(pstAwbSnsDft);
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pstAwbSnsDft);
memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
pstAwbSnsDft->u16InitGgain = 1024;
@ -414,6 +554,7 @@ static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
{
UNUSED(ViPipe);
memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
return CVI_SUCCESS;
@ -421,12 +562,22 @@ static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
{
CMOS_CHECK_POINTER(pstBlc);
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
UNUSED(ViPipe);
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstBlc);
memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
memcpy(pstBlc,
&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
else
memcpy(pstBlc,
&g_stIspBlcCalibratio_wdr, sizeof(ISP_CMOS_BLACK_LEVEL_S));
return CVI_SUCCESS;
}
@ -439,11 +590,13 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astCV4001_mode[pstSnsState->u8ImgMode];
if (pstSnsState->enWDRMode != WDR_MODE_NONE) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
} else {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
} else {
pstIspCfg->frm_num = 2;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S));
}
return CVI_SUCCESS;
@ -451,9 +604,42 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
{
UNUSED(ViPipe);
UNUSED(u8Mode);
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsState->bSyncInit = CVI_FALSE;
switch (u8Mode) {
case WDR_MODE_NONE:
if (pstSnsState->u8ImgMode == CV4001_MODE_2560X1440P15_WDR)
pstSnsState->u8ImgMode = CV4001_MODE_2560X1440P25;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
syslog(LOG_INFO, "WDR_MODE_NONE\n");
break;
case WDR_MODE_2To1_LINE:
if (pstSnsState->u8ImgMode == CV4001_MODE_2560X1440P25) {
pstSnsState->u8ImgMode = CV4001_MODE_2560X1440P15_WDR;
}
pstSnsState->enWDRMode = WDR_MODE_2To1_LINE;
pstSnsState->u32FLStd = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
syslog(LOG_INFO, "WDR_MODE_2To1_LINE 1440p mode(60fps->30fps)\n");
break;
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
return CVI_FAILURE;
}
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime));
return CVI_SUCCESS;
}
@ -505,7 +691,8 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunCV4001_BusInfo[ViPipe].s8I2cDev;
pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
pstCfg0->snsCfg.u32RegNum = (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) ?
WDR2_REGS_NUM : LINEAR_REGS_NUM;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
pstI2c_data[i].bUpdate = CVI_TRUE;
@ -514,65 +701,54 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
pstI2c_data[i].u32DataByteNum = cv4001_data_byte;
}
pstI2c_data[LINEAR_EXP_0].u32RegAddr = CV4001_EXP_ADDR0;
pstI2c_data[LINEAR_EXP_1].u32RegAddr = CV4001_EXP_ADDR1;
pstI2c_data[LINEAR_EXP_2].u32RegAddr = CV4001_EXP_ADDR2;
pstI2c_data[LINEAR_AGAIN].u32RegAddr = CV4001_AGAIN_ADDR;
pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = CV4001_DGAIN_H_ADDR;
pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = CV4001_DGAIN_L_ADDR;
switch (pstSnsState->enWDRMode) {
case WDR_MODE_2To1_LINE:
pstI2c_data[WDR2_EXP1_0].u32RegAddr = CV4001_EXP1_ADDR0;
pstI2c_data[WDR2_EXP1_1].u32RegAddr = CV4001_EXP1_ADDR1;
pstI2c_data[WDR2_EXP1_2].u32RegAddr = CV4001_EXP1_ADDR2;
pstI2c_data[WDR2_EXP2_0].u32RegAddr = CV4001_EXP2_ADDR0;
pstI2c_data[WDR2_EXP2_1].u32RegAddr = CV4001_EXP2_ADDR1;
pstI2c_data[WDR2_EXP2_2].u32RegAddr = CV4001_EXP2_ADDR2;
pstI2c_data[WDR2_AGAIN1].u32RegAddr = CV4001_AGAIN1_ADDR;
pstI2c_data[WDR2_AGAIN2].u32RegAddr = CV4001_AGAIN2_ADDR;
pstI2c_data[WDR2_DGAIN1_H].u32RegAddr = CV4001_DGAIN1_H_ADDR;
pstI2c_data[WDR2_DGAIN1_L].u32RegAddr = CV4001_DGAIN1_L_ADDR;
pstI2c_data[WDR2_DGAIN2_H].u32RegAddr = CV4001_DGAIN2_H_ADDR;
pstI2c_data[WDR2_DGAIN2_L].u32RegAddr = CV4001_DGAIN2_L_ADDR;
pstI2c_data[WDR2_VTS_0].u32RegAddr = CV4001_VTS_ADDR0;
pstI2c_data[WDR2_VTS_1].u32RegAddr = CV4001_VTS_ADDR1;
pstI2c_data[WDR2_VTS_2].u32RegAddr = CV4001_VTS_ADDR2;
pstI2c_data[WDR2_FLIP_MIRROR].u32RegAddr = CV4001_FLIP_MIRROR_ADDR;
break;
default:
pstI2c_data[LINEAR_EXP_0].u32RegAddr = CV4001_EXP1_ADDR0;
pstI2c_data[LINEAR_EXP_1].u32RegAddr = CV4001_EXP1_ADDR1;
pstI2c_data[LINEAR_EXP_2].u32RegAddr = CV4001_EXP1_ADDR2;
pstI2c_data[LINEAR_AGAIN].u32RegAddr = CV4001_AGAIN1_ADDR;
pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = CV4001_DGAIN1_H_ADDR;
pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = CV4001_DGAIN1_L_ADDR;
pstI2c_data[LINEAR_VTS_0].u32RegAddr = CV4001_VTS_ADDR0;
pstI2c_data[LINEAR_VTS_1].u32RegAddr = CV4001_VTS_ADDR1;
pstI2c_data[LINEAR_VTS_2].u32RegAddr = CV4001_VTS_ADDR2;
pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = CV4001_FLIP_MIRROR_ADDR;
break;
}
pstSnsState->bSyncInit = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
/* recalcualte WDR size */
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
pstCfg0->ispCfg.need_update = CVI_TRUE;
} else {
CVI_U32 gainsUpdate = 0, shutterUpdate = 0, vtsUpdate = 0;
pstCfg0->snsCfg.need_update = CVI_FALSE;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
} else {
if ((i >= LINEAR_AGAIN) && (i <= LINEAR_DGAIN_L)) {
gainsUpdate = 1;
}
if (i <= LINEAR_EXP_2) {
shutterUpdate = 1;
}
if ((i >= LINEAR_VTS_0) && (i <= LINEAR_VTS_2)) {
vtsUpdate = 1;
}
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
}
}
if (gainsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_L].bUpdate = CVI_TRUE;
}
if (shutterUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_0].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_1].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_2].bUpdate = CVI_TRUE;
}
if (vtsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_0].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_1].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_2].bUpdate = CVI_TRUE;
}
/* check update isp crop or not */
pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
CVI_TRUE : CVI_FALSE);
@ -582,7 +758,12 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
} else {
pstCfg0->snsCfg.astI2cData[WDR2_FLIP_MIRROR].bDropFrm = CVI_FALSE;
}
return CVI_SUCCESS;
}
@ -611,6 +792,17 @@ static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
if (CV4001_RES_IS_1440P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) {
u8SensorImageMode = CV4001_MODE_2560X1440P15_WDR;
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
@ -677,9 +869,17 @@ static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSn
return;
}
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2;
} else {
start_x = 0;
start_y = 0;
pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].u32Data = value;
pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].bDropFrm = 1;
pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].u8DropFrmNum = 2;
}
g_aeCV4001_MirrorFip[ViPipe] = eSnsMirrorFlip;
pstIspCfg0->img_size[0].stWndRect.s32X = start_x;
pstIspCfg0->img_size[0].stWndRect.s32Y = start_y;
@ -718,8 +918,11 @@ static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
pstRxAttr->img_size.width = g_astCV4001_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
pstRxAttr->img_size.height = g_astCV4001_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
} else {
pstRxAttr->mac_clk = RX_MAC_CLK_400M;
}
return CVI_SUCCESS;

23
middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos_ex.h
View File

@ -36,8 +36,30 @@ enum cv4001_linear_regs_e {
LINEAR_REGS_NUM
};
enum cv4001_wdr2_regs_e {
WDR2_EXP1_0,
WDR2_EXP1_1,
WDR2_EXP1_2,
WDR2_EXP2_0,
WDR2_EXP2_1,
WDR2_EXP2_2,
WDR2_AGAIN1,
WDR2_AGAIN2,
WDR2_DGAIN1_H,
WDR2_DGAIN1_L,
WDR2_DGAIN2_H,
WDR2_DGAIN2_L,
WDR2_VTS_0,
WDR2_VTS_1,
WDR2_VTS_2,
WDR2_FLIP_MIRROR,
WDR2_REGS_NUM
};
typedef enum _CV4001_MODE_E {
CV4001_MODE_2560X1440P25 = 0,
CV4001_MODE_LINEAR_NUM,
CV4001_MODE_2560X1440P15_WDR = CV4001_MODE_LINEAR_NUM,
CV4001_MODE_NUM
} CV4001_MODE_E;
@ -52,6 +74,7 @@ typedef struct _CV4001_MODE_S {
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp[2];
CVI_U32 u32IspResTime;
SNS_ATTR_LARGE_S stAgain[2];
SNS_ATTR_LARGE_S stDgain[2];
char name[64];

122
middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos_param.h
View File

@ -39,13 +39,13 @@ static const CV4001_MODE_S g_astCV4001_mode[CV4001_MODE_NUM] = {
},
},
.f32MaxFps = 25,
.f32MinFps = 0.076, /* 3200 * 25 / 0x0FFFFF */
.u32HtsDef = 743,
.u32VtsDef = 3200,
.f32MinFps = 0.072, /* 1500 * 25 / (0x0FFFFF / 2) */
.u32HtsDef = 1480, //hts_reg * 2
.u32VtsDef = 1500, //vts_reg / 2
.stExp[0] = {
.u16Min = 8,
.u16Max = 3200-4,
.u16Def = 8,
.u16Min = 4,
.u16Max = 1500-2,
.u16Def = 4,
.u16Step = 1,
},
.stAgain[0] = {
@ -61,6 +61,81 @@ static const CV4001_MODE_S g_astCV4001_mode[CV4001_MODE_NUM] = {
.u32Step = 64,
},
},
[CV4001_MODE_2560X1440P15_WDR] = {
.name = "2560X1440P15_WDR",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2560,
.u32Height = 1440,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2560,
.u32Height = 1440,
},
},
.astImg[1] = {
.stSnsSize = {
.u32Width = 2560,
.u32Height = 1440,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2560,
.u32Height = 1440,
},
},
.f32MaxFps = 15,
.f32MinFps = 0.084, /* 1474 * 15 / (0x0FFFFF / 4) */
.u32HtsDef = 5088, //hts_reg * 4
.u32VtsDef = 1474, //vts_reg / 4
.stExp[0] = {
.u16Min = 4,
.u16Max = 1474-1,
.u16Def = 4,
.u16Step = 1,
},
.stExp[1] = {
.u16Min = 4,
.u16Max = 98,
.u16Def = 4,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 1,
},
.stAgain[1] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 64,
},
.stDgain[1] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 64,
},
}
};
@ -97,6 +172,39 @@ static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
},
};
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio_wdr = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {196, 196, 196, 196, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1075, 1075, 1075, 1075
#endif
},
.stAuto = {
{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
1075, 1075},
{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
1075, 1075},
{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
1075, 1075},
{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
1075, 1075},
#endif
},
},
};
struct combo_dev_attr_s cv4001_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
@ -104,7 +212,7 @@ struct combo_dev_attr_s cv4001_rx_attr = {
.raw_data_type = RAW_DATA_12BIT,
.lane_id = {1, 2, 0, -1, -1},
.pn_swap = {1, 1, 1, 0, 0},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
.wdr_mode = CVI_MIPI_WDR_MODE_VC,
},
.mclk = {
.cam = 0,

111
middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_sensor_ctl.c
View File

@ -22,6 +22,7 @@
#define CV4001_CHIP_ID 0x4001
static void cv4001_linear_1440p25_init(VI_PIPE ViPipe);
static void cv4001_wdr_1440p15_2to1_init(VI_PIPE ViPipe);
CVI_U8 cv4001_i2c_addr = 0x35;
const CVI_U32 cv4001_addr_byte = 2;
@ -198,9 +199,23 @@ int cv4001_probe(VI_PIPE ViPipe)
void cv4001_init(VI_PIPE ViPipe)
{
WDR_MODE_E enWDRMode;
CVI_U8 u8ImgMode;
enWDRMode = g_pastCV4001[ViPipe]->enWDRMode;
u8ImgMode = g_pastCV4001[ViPipe]->u8ImgMode;
cv4001_i2c_init(ViPipe);
if (enWDRMode == WDR_MODE_2To1_LINE) {
if (u8ImgMode == CV4001_MODE_2560X1440P15_WDR) {
cv4001_wdr_1440p15_2to1_init(ViPipe);
}
} else {
if (u8ImgMode == CV4001_MODE_2560X1440P25) {
cv4001_linear_1440p25_init(ViPipe);
}
}
g_pastCV4001[ViPipe]->bInit = CVI_TRUE;
}
@ -292,3 +307,99 @@ static void cv4001_linear_1440p25_init(VI_PIPE ViPipe)
printf("ViPipe:%d,===CV4001 1440P 25fps 12bit LINEAR Init OK!===\n", ViPipe);
}
static void cv4001_wdr_1440p15_2to1_init(VI_PIPE ViPipe)
{
cv4001_write_register(ViPipe, 0x3028, 0x08);
cv4001_write_register(ViPipe, 0x3029, 0x17);
cv4001_write_register(ViPipe, 0x302C, 0xF8);
cv4001_write_register(ViPipe, 0x302D, 0x04);
cv4001_write_register(ViPipe, 0x3908, 0x4B);
cv4001_write_register(ViPipe, 0x3304, 0x01);
cv4001_write_register(ViPipe, 0x3305, 0x02);
cv4001_write_register(ViPipe, 0x3306, 0x01);
cv4001_write_register(ViPipe, 0x343E, 0x00);
cv4001_write_register(ViPipe, 0x3401, 0x03);
cv4001_write_register(ViPipe, 0x3035, 0x01);
cv4001_write_register(ViPipe, 0x3036, 0x01);
cv4001_write_register(ViPipe, 0x3020, 0x04);
cv4001_write_register(ViPipe, 0x3048, 0x44);
cv4001_write_register(ViPipe, 0x3049, 0x00);
cv4001_write_register(ViPipe, 0x304A, 0x00);
cv4001_write_register(ViPipe, 0x304B, 0x0A);
cv4001_write_register(ViPipe, 0x3054, 0x2C);
cv4001_write_register(ViPipe, 0x3056, 0xA8);
cv4001_write_register(ViPipe, 0x3057, 0x05);
cv4001_write_register(ViPipe, 0x3030, 0x05);
cv4001_write_register(ViPipe, 0x3060, 0x2C);
cv4001_write_register(ViPipe, 0x3064, 0x12);
cv4001_write_register(ViPipe, 0x3070, 0x1A);//62
cv4001_write_register(ViPipe, 0x3071, 0x00);
cv4001_write_register(ViPipe, 0x343C, 0x01);
cv4001_write_register(ViPipe, 0x3930, 0x00);
cv4001_write_register(ViPipe, 0x3040, 0x01);
cv4001_write_register(ViPipe, 0x3044, 0x04);
cv4001_write_register(ViPipe, 0x3046, 0xA0);
cv4001_write_register(ViPipe, 0x3047, 0x05);
cv4001_write_register(ViPipe, 0x362A, 0x00);
cv4001_write_register(ViPipe, 0x3625, 0x01);
cv4001_write_register(ViPipe, 0x35A4, 0x09);
cv4001_write_register(ViPipe, 0x35A8, 0x09);
cv4001_write_register(ViPipe, 0x35AE, 0x07);
cv4001_write_register(ViPipe, 0x35AF, 0x07);
cv4001_write_register(ViPipe, 0x34A2, 0x2C);
cv4001_write_register(ViPipe, 0x3416, 0x0F);
cv4001_write_register(ViPipe, 0x3418, 0x9F);
cv4001_write_register(ViPipe, 0x341A, 0x57);
cv4001_write_register(ViPipe, 0x341C, 0x57);
cv4001_write_register(ViPipe, 0x341E, 0x6F);
cv4001_write_register(ViPipe, 0x341F, 0x01);
cv4001_write_register(ViPipe, 0x3420, 0x57);
cv4001_write_register(ViPipe, 0x3422, 0x9F);
cv4001_write_register(ViPipe, 0x3424, 0x57);
cv4001_write_register(ViPipe, 0x3426, 0x8F);
cv4001_write_register(ViPipe, 0x3428, 0x47);
cv4001_write_register(ViPipe, 0x3348, 0x00);
cv4001_write_register(ViPipe, 0x3000, 0x00);
cv4001_write_register(ViPipe, 0x3220, 0x03);
cv4001_write_register(ViPipe, 0x3347, 0x01);
cv4001_write_register(ViPipe, 0x3348, 0x00);
cv4001_write_register(ViPipe, 0x3804, 0x0F);
cv4001_write_register(ViPipe, 0x3576, 0x06);
cv4001_write_register(ViPipe, 0x350F, 0x18);
cv4001_write_register(ViPipe, 0x3513, 0x07);
cv4001_write_register(ViPipe, 0x3517, 0x07);
cv4001_write_register(ViPipe, 0x351A, 0x05);
cv4001_write_register(ViPipe, 0x351E, 0x0B);
cv4001_write_register(ViPipe, 0x357A, 0x0B);
cv4001_write_register(ViPipe, 0x3244, 0x08);
cv4001_write_register(ViPipe, 0x3270, 0x60);
cv4001_write_register(ViPipe, 0x3271, 0x00);
cv4001_write_register(ViPipe, 0x3272, 0x00);
cv4001_write_register(ViPipe, 0x3890, 0x01);
cv4001_write_register(ViPipe, 0x3894, 0x05);
cv4001_write_register(ViPipe, 0x3690, 0x00);
cv4001_write_register(ViPipe, 0x3898, 0x20);
cv4001_write_register(ViPipe, 0x3899, 0x20);
cv4001_write_register(ViPipe, 0x389a, 0x20);
cv4001_write_register(ViPipe, 0x389b, 0x20);
cv4001_write_register(ViPipe, 0x389c, 0x20);
cv4001_write_register(ViPipe, 0x389d, 0x15);
cv4001_write_register(ViPipe, 0x389e, 0x05);
cv4001_write_register(ViPipe, 0x3583, 0x2f);
cv4001_write_register(ViPipe, 0x3b75, 0x00);
cv4001_write_register(ViPipe, 0x3b5E, 0x01);
cv4001_write_register(ViPipe, 0x3a10, 0x06);
cv4001_write_register(ViPipe, 0x3a11, 0x06);
cv4001_write_register(ViPipe, 0x316C, 0x64);
cv4001_write_register(ViPipe, 0x3162, 0x01);
cv4001_write_register(ViPipe, 0x3180, 0x00);
cv4001_write_register(ViPipe, 0x3178, 0x40);
cv4001_write_register(ViPipe, 0x3179, 0x00);
cv4001_default_reg_init(ViPipe);
delay_ms(100);
printf("ViPipe:%d,===CV4001 1440P 15fps 12bit WDR2TO1 Init OK!===\n", ViPipe);
}

48
middleware/v2/component/isp/sensor/cv180x/soi_k06/k06_sensor_ctl.c
View File

@ -160,26 +160,36 @@ void k06_default_reg_init(VI_PIPE ViPipe)
void k06_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 val = k06_read_register(ViPipe, 0x12) & (~0x30);
CVI_U8 val1 = k06_read_register(ViPipe, 0x12);
CVI_U8 val2 = k06_read_register(ViPipe, 0xAA);
CVI_U8 val3 = k06_read_register(ViPipe, 0x27);
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
val |= 0x30;
val1 = 0x30;
val2 = 0x84;
break;
case ISP_SNS_MIRROR:
val |= (0x1 << 4);
val1 = 0x10;
val2 = 0x8B;
val3 += 1;
break;
case ISP_SNS_FLIP:
val |= (0x2 << 4);
val1 = 0x20;
val2 = 0x84;
break;
case ISP_SNS_MIRROR_FLIP:
val &= ~(0x1 << 4);
val1 = 0x00;
val2 = 0x8B;
val3 += 1;
break;
default:
return;
}
k06_write_register(ViPipe, 0x12, val);
k06_write_register(ViPipe, 0x12, val1);
k06_write_register(ViPipe, 0xAA, val2);
k06_write_register(ViPipe, 0x27, val3);
}
int k06_probe(VI_PIPE ViPipe)
@ -235,6 +245,7 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
k06_write_register(ViPipe, 0x10, 0x48);
k06_write_register(ViPipe, 0x11, 0x80);
k06_write_register(ViPipe, 0x46, 0x08);
k06_write_register(ViPipe, 0x7F, 0x5E);
k06_write_register(ViPipe, 0x0D, 0xA0);
k06_write_register(ViPipe, 0x57, 0x67);
k06_write_register(ViPipe, 0x58, 0x1F);
@ -247,10 +258,10 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
k06_write_register(ViPipe, 0x24, 0x80);
k06_write_register(ViPipe, 0x25, 0xA0);
k06_write_register(ViPipe, 0x26, 0x52);
k06_write_register(ViPipe, 0x27, 0x27);
k06_write_register(ViPipe, 0x27, 0x46);
k06_write_register(ViPipe, 0x28, 0x15);
k06_write_register(ViPipe, 0x29, 0x04);
k06_write_register(ViPipe, 0x2A, 0x20);
k06_write_register(ViPipe, 0x2A, 0x40);
k06_write_register(ViPipe, 0x2B, 0x14);
k06_write_register(ViPipe, 0x2C, 0x00);
k06_write_register(ViPipe, 0x2D, 0x00);
@ -263,36 +274,35 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
k06_write_register(ViPipe, 0x77, 0x0C);
k06_write_register(ViPipe, 0x80, 0x01);
k06_write_register(ViPipe, 0xAF, 0x12);
k06_write_register(ViPipe, 0xAA, 0x04);
k06_write_register(ViPipe, 0xAA, 0x84);
k06_write_register(ViPipe, 0x1D, 0x00);
k06_write_register(ViPipe, 0x1E, 0x04);
k06_write_register(ViPipe, 0x6C, 0x40);
k06_write_register(ViPipe, 0x9E, 0xF8);
k06_write_register(ViPipe, 0x0C, 0x30);
k06_write_register(ViPipe, 0x6F, 0x80);
k06_write_register(ViPipe, 0x0C, 0x00);
k06_write_register(ViPipe, 0x6E, 0x2C);
k06_write_register(ViPipe, 0x70, 0xF9);
k06_write_register(ViPipe, 0x71, 0xDD);
k06_write_register(ViPipe, 0x72, 0xD5);
k06_write_register(ViPipe, 0x73, 0x5A);
k06_write_register(ViPipe, 0x74, 0x02);
k06_write_register(ViPipe, 0x78, 0x1D);
k06_write_register(ViPipe, 0x78, 0x1C);
k06_write_register(ViPipe, 0x89, 0x01);
k06_write_register(ViPipe, 0x6B, 0x20);
k06_write_register(ViPipe, 0x86, 0x40);
k06_write_register(ViPipe, 0x6F, 0x00);
k06_write_register(ViPipe, 0x30, 0x8D);
k06_write_register(ViPipe, 0x31, 0x08);
k06_write_register(ViPipe, 0x32, 0x20);
k06_write_register(ViPipe, 0x33, 0x5C);
k06_write_register(ViPipe, 0x34, 0x30);
k06_write_register(ViPipe, 0x35, 0x30);
k06_write_register(ViPipe, 0x3A, 0xB6);
k06_write_register(ViPipe, 0x3A, 0xB9);
k06_write_register(ViPipe, 0x56, 0x92);
k06_write_register(ViPipe, 0x59, 0x48);
k06_write_register(ViPipe, 0x59, 0x60);
k06_write_register(ViPipe, 0x5A, 0x01);
k06_write_register(ViPipe, 0x61, 0x00);
k06_write_register(ViPipe, 0x64, 0xC0);
k06_write_register(ViPipe, 0x7F, 0x46);
k06_write_register(ViPipe, 0x85, 0x44);
k06_write_register(ViPipe, 0x8A, 0x00);
k06_write_register(ViPipe, 0x91, 0x58);
@ -317,14 +327,14 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
k06_write_register(ViPipe, 0x8F, 0x90);
k06_write_register(ViPipe, 0xA4, 0xC7);
k06_write_register(ViPipe, 0xA5, 0xAF);
k06_write_register(ViPipe, 0xB7, 0x21);
k06_write_register(ViPipe, 0xB7, 0x61);
k06_write_register(ViPipe, 0x97, 0x20);
k06_write_register(ViPipe, 0x13, 0x81);
k06_write_register(ViPipe, 0x96, 0x84);
k06_write_register(ViPipe, 0x4A, 0x01);
k06_write_register(ViPipe, 0x7E, 0x4C);
k06_write_register(ViPipe, 0x50, 0x02);
k06_write_register(ViPipe, 0x93, 0xC0);
k06_write_register(ViPipe, 0x93, 0x00);
k06_write_register(ViPipe, 0xB5, 0x4C);
k06_write_register(ViPipe, 0xB1, 0x00);
k06_write_register(ViPipe, 0xA1, 0x0F);
@ -340,10 +350,12 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
k06_write_register(ViPipe, 0x1B, 0x4F);
k06_default_reg_init(ViPipe);
// k06_write_register(ViPipe, 0x12, 0x00);
k06_write_register(ViPipe, 0x12, 0x30);
k06_write_register(ViPipe, 0x48, 0x86);
k06_write_register(ViPipe, 0x48, 0x06);
k06_write_register(ViPipe, 0x00, 0x10);
printf("ViPipe:%d,===K06 1440P 25fps 10bit LINE Init OK!===\n", ViPipe);
}

32
middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos.c
View File

@ -67,6 +67,7 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
#define Q03P_SHS1_ADDR 0x01
#define Q03P_GAIN_ADDR 0x00
#define Q03P_VMAX_ADDR 0x22
#define Q03P_FLIP_MIRROR_ADDR 0x12
#define Q03P_TABLE_END 0xff
#define Q03P_RES_IS_1296P(w, h) ((w) <= 2304 && (h) <= 1296)
@ -500,6 +501,8 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
pstI2c_data[LINEAR_VMAX_1_DATA].u32RegAddr = Q03P_VMAX_ADDR + 1;
pstI2c_data[LINEAR_VMAX_1_DATA].u8DelayFrmNum = 2;
pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = Q03P_FLIP_MIRROR_ADDR;
break;
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode);
@ -529,6 +532,7 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
return CVI_SUCCESS;
}
@ -579,12 +583,38 @@ static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S
static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 value = q03p_read_register(ViPipe, Q03P_FLIP_MIRROR_ADDR) & ~0x30;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
/* Apply the setting on the fly */
if (pstSnsState->bInit == CVI_TRUE && g_aeQ03P_MirrorFip[ViPipe] != eSnsMirrorFlip) {
q03p_mirror_flip(ViPipe, eSnsMirrorFlip);
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
value |= 0x00;
break;
case ISP_SNS_MIRROR:
value |= 0x20;
break;
case ISP_SNS_FLIP:
value |= 0x10;
break;
case ISP_SNS_MIRROR_FLIP:
value |= 0x30;
break;
default:
return;
}
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2;
g_aeQ03P_MirrorFip[ViPipe] = eSnsMirrorFlip;
}
}

2
middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos_ex.h
View File

@ -28,6 +28,7 @@ enum q03p_linear_regs_e {
LINEAR_AGAIN_DATA,
LINEAR_VMAX_0_DATA,
LINEAR_VMAX_1_DATA,
LINEAR_FLIP_MIRROR,
LINEAR_REGS_NUM
};
@ -64,7 +65,6 @@ extern CVI_U16 g_au16Q03P_L2SMode[];
extern CVI_U8 q03p_i2c_addr;
extern const CVI_U32 q03p_addr_byte;
extern const CVI_U32 q03p_data_byte;
extern void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern void q03p_init(VI_PIPE ViPipe);
extern void q03p_exit(VI_PIPE ViPipe);
extern void q03p_standby(VI_PIPE ViPipe);

23
middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_sensor_ctl.c
View File

@ -175,29 +175,6 @@ void q03p_default_reg_init(VI_PIPE ViPipe)
}
}
void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 val = q03p_read_register(ViPipe, 0x12) & ~0x30;
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
break;
case ISP_SNS_MIRROR:
val |= 0x20;
break;
case ISP_SNS_FLIP:
val |= 0x10;
break;
case ISP_SNS_MIRROR_FLIP:
val |= 0x30;
break;
default:
return;
}
q03p_write_register(ViPipe, 0x12, val);
}
int q03p_probe(VI_PIPE ViPipe)
{
int nVal;

391
middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos.c
View File

@ -66,17 +66,24 @@ static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
/*****CV4001 Lines Range*****/
#define CV4001_FULL_LINES_MAX (0xfffff)
#define CV4001_FULL_LINES_MAX (0xfffff / 2)//liner mode: vts_reg value is double real_vts
#define CV4001_FULL_LINES_MAX_2TO1_WDR (0xfffff / 4)//wdr mode: four
/*****CV4001 Register Address*****/
#define CV4001_EXP_ADDR0 0x3062 //bit[19:16]
#define CV4001_EXP_ADDR1 0x3061
#define CV4001_EXP_ADDR2 0x3060
#define CV4001_EXP1_ADDR0 0x3062 //bit[19:16]
#define CV4001_EXP1_ADDR1 0x3061
#define CV4001_EXP1_ADDR2 0x3060
#define CV4001_EXP2_ADDR0 0x3066
#define CV4001_EXP2_ADDR1 0x3065
#define CV4001_EXP2_ADDR2 0x3064
#define CV4001_AGAIN_ADDR 0x3180 //bit[7:0]
#define CV4001_AGAIN1_ADDR 0x3180 //bit[7:0]
#define CV4001_AGAIN2_ADDR 0x3181 //bit[7:0]
#define CV4001_DGAIN_H_ADDR 0x3179 //bit[15:8]
#define CV4001_DGAIN_L_ADDR 0x3178 //bit[7:0]
#define CV4001_DGAIN1_H_ADDR 0x3179 //bit[15:8]
#define CV4001_DGAIN1_L_ADDR 0x3178 //bit[7:0]
#define CV4001_DGAIN2_H_ADDR 0x317B //bit[15:8]
#define CV4001_DGAIN2_L_ADDR 0x317A //bit[7:0]
#define CV4001_VTS_ADDR0 0x302A //bit[19:16]
#define CV4001_VTS_ADDR1 0x3029
@ -84,26 +91,35 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
#define CV4001_FLIP_MIRROR_ADDR 0x3034
#define CV4001_RES_IS_1440P(w, h) ((w) <= 2560 && (h) <= 1440)
#define CV4001_RES_IS_1440P(w, h) ((w) == 2560 && (h) == 1440)
static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
const CV4001_MODE_S *pstMode;
CVI_U32 FpsMax;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astCV4001_mode[pstSnsState->u8ImgMode];
FpsMax = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MaxFps;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32FlickerFreq = 50 * 256;
pstAeSnsDft->u32FullLinesMax = CV4001_FULL_LINES_MAX;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 25);
pstAeSnsDft->u32FullLinesMax = (pstSnsState->enWDRMode == WDR_MODE_NONE) ?
CV4001_FULL_LINES_MAX : CV4001_FULL_LINES_MAX_2TO1_WDR;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * FpsMax);
pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
@ -112,27 +128,32 @@ static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSns
pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
if (g_au32LinesPer500ms[ViPipe] == 0)
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 25 / 2;
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * FpsMax / 2;
else
pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
switch (pstSnsState->enWDRMode) {
default:
case WDR_MODE_NONE: /*linear mode*/
pstAeSnsDft->f32Fps = g_astCV4001_mode[CV4001_MODE_2560X1440P25].f32MaxFps;
pstAeSnsDft->f32MinFps = g_astCV4001_mode[CV4001_MODE_2560X1440P25].f32MinFps;
pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xd;
pstAeSnsDft->au8HistThresh[1] = 0x28;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxAgain = 16384;
pstAeSnsDft->u32MinAgain = 1024;
pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max;
pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u32Max;
pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u32Min;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = 16384;
pstAeSnsDft->u32MinDgain = 1024;
pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u32Max;
pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u32Max;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
@ -142,14 +163,52 @@ static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSns
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ?
g_au32InitExposure[ViPipe] : g_astCV4001_mode[CV4001_MODE_2560X1440P25].stExp[0].u16Def;
g_au32InitExposure[ViPipe] : pstMode->stExp[0].u16Def;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstAeSnsDft->u32MinIntTime = g_astCV4001_mode[CV4001_MODE_2560X1440P25].stExp[0].u16Min;
break;
case WDR_MODE_2To1_LINE:
pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xC;
pstAeSnsDft->au8HistThresh[1] = 0x18;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max;
pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u32Max;
pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u32Min;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u32Max;
pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u32Min;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
pstAeSnsDft->u32MaxISPDgainTarget = 16 << pstAeSnsDft->u32ISPDgainShift;
pstAeSnsDft->u32InitAESpeed = 64;
pstAeSnsDft->u32InitAETolerance = 5;
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ?
g_au32InitExposure[ViPipe] : pstMode->stExp[0].u16Def;
if (genFSWDRMode[ViPipe] == ISP_FSWDR_LONG_FRAME_MODE) {
pstAeSnsDft->u8AeCompensation = 64;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
} else {
pstAeSnsDft->u8AeCompensation = 40;
pstAeSnsDft->enAeExpMode = AE_EXP_LOWLIGHT_PRIOR;
}
break;
}
CVI_TRACE_SNS(CVI_DBG_INFO, "again[%d, %d], dgain[%d, %d]\n",
pstAeSnsDft->u32MinAgain, pstAeSnsDft->u32MaxAgain, pstAeSnsDft->u32MinDgain, pstAeSnsDft->u32MaxDgain);
return CVI_SUCCESS;
}
@ -168,11 +227,12 @@ static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32Vts = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
u32Vts = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
f32MaxFps = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MaxFps;
f32MinFps = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MinFps;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
@ -180,17 +240,26 @@ static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX) ? CV4001_FULL_LINES_MAX : u32VMAX;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_VTS_0].u32Data = ((u32VMAX & 0xFF0000) >> 16);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_1].u32Data = ((u32VMAX & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_2].u32Data = (u32VMAX & 0xFF);
u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX) ?
CV4001_FULL_LINES_MAX : u32VMAX;
pstSnsRegsInfo->astI2cData[LINEAR_VTS_0].u32Data = (((u32VMAX * 2) & 0xFF0000) >> 16);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_1].u32Data = (((u32VMAX * 2) & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_2].u32Data = ((u32VMAX * 2) & 0xFF);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX_2TO1_WDR) ?
CV4001_FULL_LINES_MAX_2TO1_WDR : u32VMAX;
pstSnsRegsInfo->astI2cData[WDR2_VTS_0].u32Data = (((u32VMAX * 4) & 0xFF0000) >> 16);
pstSnsRegsInfo->astI2cData[WDR2_VTS_1].u32Data = (((u32VMAX * 4) & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[WDR2_VTS_2].u32Data = ((u32VMAX * 4) & 0xFF);
}
pstSnsState->u32FLStd = u32VMAX;
pstAeSnsDft->f32Fps = f32Fps;
@ -209,20 +278,37 @@ static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_S32 Cur_Vts;
CVI_S32 Reg_IntTime;
CVI_S32 Reg_IntTime1;
CVI_S32 Reg_IntTime2;
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(u32IntTime);
Cur_Vts = pstSnsState->u32FLStd;
Reg_IntTime = ((Cur_Vts / 2) - u32IntTime[0]) * 2;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = ((Reg_IntTime >> 16) & 0x0F);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = ((Reg_IntTime >> 8) & 0xFF);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_2].u32Data = (Reg_IntTime & 0xFF);
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
Reg_IntTime1 = (pstSnsState->u32FLStd - u32IntTime[0]) * 2;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = ((Reg_IntTime1 >> 16) & 0x0F);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = ((Reg_IntTime1 >> 8) & 0xFF);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_2].u32Data = (Reg_IntTime1 & 0xFF);
} else {
/* short exposure */
pstSnsState->au32WDRIntTime[0] = u32IntTime[0];//?
/* long exposure */
pstSnsState->au32WDRIntTime[1] = u32IntTime[1];
Reg_IntTime1 = (pstSnsState->u32FLStd - u32IntTime[1]) * 4;//u32IntTime[1] long exposure
Reg_IntTime2 = (pstSnsState->u32FLStd - u32IntTime[0]) * 4 + 2;//u32IntTime[0] short exposure
pstSnsRegsInfo->astI2cData[WDR2_EXP1_0].u32Data = ((Reg_IntTime1 >> 16) & 0x0F);
pstSnsRegsInfo->astI2cData[WDR2_EXP1_1].u32Data = ((Reg_IntTime1 >> 8) & 0xFF);
pstSnsRegsInfo->astI2cData[WDR2_EXP1_2].u32Data = (Reg_IntTime1 & 0xFF);
pstSnsRegsInfo->astI2cData[WDR2_EXP2_0].u32Data = ((Reg_IntTime2 >> 16) & 0x0F);
pstSnsRegsInfo->astI2cData[WDR2_EXP2_1].u32Data = ((Reg_IntTime2 >> 8) & 0xFF);
pstSnsRegsInfo->astI2cData[WDR2_EXP2_2].u32Data = (Reg_IntTime2 & 0xFF);
}
return CVI_SUCCESS;
}
@ -340,8 +426,13 @@ static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_H].u32Data = (u32Dgain >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_L].u32Data = (u32Dgain & 0xFF);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
pstSnsRegsInfo->astI2cData[WDR2_AGAIN1].u32Data = u32Again;
pstSnsRegsInfo->astI2cData[WDR2_AGAIN2].u32Data = u32Again;
pstSnsRegsInfo->astI2cData[WDR2_DGAIN1_H].u32Data = (u32Dgain >> 8);
pstSnsRegsInfo->astI2cData[WDR2_DGAIN1_L].u32Data = (u32Dgain & 0xFF);
pstSnsRegsInfo->astI2cData[WDR2_DGAIN2_H].u32Data = (u32Dgain >> 8);
pstSnsRegsInfo->astI2cData[WDR2_DGAIN2_L].u32Data = (u32Dgain & 0xFF);
}
return CVI_SUCCESS;
}
@ -349,14 +440,62 @@ static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu
static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio,
CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime)
{
UNUSED(ViPipe);
UNUSED(u16ManRatioEnable);
UNUSED(au32Ratio);
UNUSED(au32IntTimeMax);
UNUSED(au32IntTimeMin);
UNUSED(pu32LFMaxIntTime);
CVI_U32 u32IntTimeMaxTmp = 0, u32IntTimeMaxTmp0 = 0;
CVI_U32 u32RatioTmp = 0x40;
CVI_U32 u32ShortTimeMinLimit = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(au32Ratio);
CMOS_CHECK_POINTER(au32IntTimeMax);
CMOS_CHECK_POINTER(au32IntTimeMin);
CMOS_CHECK_POINTER(pu32LFMaxIntTime);
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32ShortTimeMinLimit = 1;
/*
* Long exp + Short exp < VTS
*/
u32IntTimeMaxTmp0 = ((pstSnsState->au32FL[1] - 1 - g_astCV4001_mode[pstSnsState->u8ImgMode].u32IspResTime -
pstSnsState->au32WDRIntTime[0]) * 0x40) / DIV_0_TO_1(au32Ratio[0]);
u32IntTimeMaxTmp = ((pstSnsState->au32FL[0] - 1 - g_astCV4001_mode[pstSnsState->u8ImgMode].u32IspResTime)
* 0x40) / DIV_0_TO_1(au32Ratio[0] + 0x40);
u32IntTimeMaxTmp = (u32IntTimeMaxTmp > u32IntTimeMaxTmp0) ? u32IntTimeMaxTmp0 : u32IntTimeMaxTmp;
u32IntTimeMaxTmp = (!u32IntTimeMaxTmp) ? u32ShortTimeMinLimit : u32IntTimeMaxTmp;
if (u32IntTimeMaxTmp >= u32ShortTimeMinLimit) {
if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
au32IntTimeMax[0] = u32IntTimeMaxTmp;
au32IntTimeMax[1] = au32IntTimeMax[0] * au32Ratio[0] >> 6;
au32IntTimeMax[2] = au32IntTimeMax[1] * au32Ratio[1] >> 6;
au32IntTimeMax[3] = au32IntTimeMax[2] * au32Ratio[2] >> 6;
au32IntTimeMin[0] = u32ShortTimeMinLimit;
au32IntTimeMin[1] = au32IntTimeMin[0] * au32Ratio[0] >> 6;
au32IntTimeMin[2] = au32IntTimeMin[1] * au32Ratio[1] >> 6;
au32IntTimeMin[3] = au32IntTimeMin[2] * au32Ratio[2] >> 6;
} else {
}
} else {
if (u16ManRatioEnable) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Manaul ExpRatio is too large!\n");
return CVI_FAILURE;
}
u32IntTimeMaxTmp = u32ShortTimeMinLimit;
if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
u32RatioTmp = 0xFFF;
au32IntTimeMax[0] = u32IntTimeMaxTmp;
au32IntTimeMax[1] = au32IntTimeMax[0] * u32RatioTmp >> 6;
} else {
}
au32IntTimeMin[0] = au32IntTimeMax[0];
au32IntTimeMin[1] = au32IntTimeMax[1];
au32IntTimeMin[2] = au32IntTimeMax[2];
au32IntTimeMin[3] = au32IntTimeMax[3];
}
CVI_TRACE_SNS(CVI_DBG_DEBUG, "sexp[%d, %d], lexp[%d, %d], ratio:%d\n",
au32IntTimeMin[0], au32IntTimeMax[0], au32IntTimeMin[1], au32IntTimeMax[1], au32Ratio[0]);
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode\n");
return CVI_SUCCESS;
}
@ -390,8 +529,9 @@ static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
{
CMOS_CHECK_POINTER(pstAwbSnsDft);
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pstAwbSnsDft);
memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
pstAwbSnsDft->u16InitGgain = 1024;
@ -414,6 +554,7 @@ static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
{
UNUSED(ViPipe);
memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
return CVI_SUCCESS;
@ -421,12 +562,22 @@ static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
{
CMOS_CHECK_POINTER(pstBlc);
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
UNUSED(ViPipe);
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstBlc);
memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
memcpy(pstBlc,
&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
else
memcpy(pstBlc,
&g_stIspBlcCalibratio_wdr, sizeof(ISP_CMOS_BLACK_LEVEL_S));
return CVI_SUCCESS;
}
@ -439,11 +590,13 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astCV4001_mode[pstSnsState->u8ImgMode];
if (pstSnsState->enWDRMode != WDR_MODE_NONE) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
} else {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
} else {
pstIspCfg->frm_num = 2;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S));
}
return CVI_SUCCESS;
@ -451,9 +604,42 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
{
UNUSED(ViPipe);
UNUSED(u8Mode);
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsState->bSyncInit = CVI_FALSE;
switch (u8Mode) {
case WDR_MODE_NONE:
if (pstSnsState->u8ImgMode == CV4001_MODE_2560X1440P15_WDR)
pstSnsState->u8ImgMode = CV4001_MODE_2560X1440P25;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
syslog(LOG_INFO, "WDR_MODE_NONE\n");
break;
case WDR_MODE_2To1_LINE:
if (pstSnsState->u8ImgMode == CV4001_MODE_2560X1440P25) {
pstSnsState->u8ImgMode = CV4001_MODE_2560X1440P15_WDR;
}
pstSnsState->enWDRMode = WDR_MODE_2To1_LINE;
pstSnsState->u32FLStd = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
syslog(LOG_INFO, "WDR_MODE_2To1_LINE 1440p mode(60fps->30fps)\n");
break;
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
return CVI_FAILURE;
}
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime));
return CVI_SUCCESS;
}
@ -505,7 +691,8 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunCV4001_BusInfo[ViPipe].s8I2cDev;
pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
pstCfg0->snsCfg.u32RegNum = (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) ?
WDR2_REGS_NUM : LINEAR_REGS_NUM;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
pstI2c_data[i].bUpdate = CVI_TRUE;
@ -514,65 +701,54 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
pstI2c_data[i].u32DataByteNum = cv4001_data_byte;
}
pstI2c_data[LINEAR_EXP_0].u32RegAddr = CV4001_EXP_ADDR0;
pstI2c_data[LINEAR_EXP_1].u32RegAddr = CV4001_EXP_ADDR1;
pstI2c_data[LINEAR_EXP_2].u32RegAddr = CV4001_EXP_ADDR2;
pstI2c_data[LINEAR_AGAIN].u32RegAddr = CV4001_AGAIN_ADDR;
pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = CV4001_DGAIN_H_ADDR;
pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = CV4001_DGAIN_L_ADDR;
switch (pstSnsState->enWDRMode) {
case WDR_MODE_2To1_LINE:
pstI2c_data[WDR2_EXP1_0].u32RegAddr = CV4001_EXP1_ADDR0;
pstI2c_data[WDR2_EXP1_1].u32RegAddr = CV4001_EXP1_ADDR1;
pstI2c_data[WDR2_EXP1_2].u32RegAddr = CV4001_EXP1_ADDR2;
pstI2c_data[WDR2_EXP2_0].u32RegAddr = CV4001_EXP2_ADDR0;
pstI2c_data[WDR2_EXP2_1].u32RegAddr = CV4001_EXP2_ADDR1;
pstI2c_data[WDR2_EXP2_2].u32RegAddr = CV4001_EXP2_ADDR2;
pstI2c_data[WDR2_AGAIN1].u32RegAddr = CV4001_AGAIN1_ADDR;
pstI2c_data[WDR2_AGAIN2].u32RegAddr = CV4001_AGAIN2_ADDR;
pstI2c_data[WDR2_DGAIN1_H].u32RegAddr = CV4001_DGAIN1_H_ADDR;
pstI2c_data[WDR2_DGAIN1_L].u32RegAddr = CV4001_DGAIN1_L_ADDR;
pstI2c_data[WDR2_DGAIN2_H].u32RegAddr = CV4001_DGAIN2_H_ADDR;
pstI2c_data[WDR2_DGAIN2_L].u32RegAddr = CV4001_DGAIN2_L_ADDR;
pstI2c_data[WDR2_VTS_0].u32RegAddr = CV4001_VTS_ADDR0;
pstI2c_data[WDR2_VTS_1].u32RegAddr = CV4001_VTS_ADDR1;
pstI2c_data[WDR2_VTS_2].u32RegAddr = CV4001_VTS_ADDR2;
pstI2c_data[WDR2_FLIP_MIRROR].u32RegAddr = CV4001_FLIP_MIRROR_ADDR;
break;
default:
pstI2c_data[LINEAR_EXP_0].u32RegAddr = CV4001_EXP1_ADDR0;
pstI2c_data[LINEAR_EXP_1].u32RegAddr = CV4001_EXP1_ADDR1;
pstI2c_data[LINEAR_EXP_2].u32RegAddr = CV4001_EXP1_ADDR2;
pstI2c_data[LINEAR_AGAIN].u32RegAddr = CV4001_AGAIN1_ADDR;
pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = CV4001_DGAIN1_H_ADDR;
pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = CV4001_DGAIN1_L_ADDR;
pstI2c_data[LINEAR_VTS_0].u32RegAddr = CV4001_VTS_ADDR0;
pstI2c_data[LINEAR_VTS_1].u32RegAddr = CV4001_VTS_ADDR1;
pstI2c_data[LINEAR_VTS_2].u32RegAddr = CV4001_VTS_ADDR2;
pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = CV4001_FLIP_MIRROR_ADDR;
break;
}
pstSnsState->bSyncInit = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
/* recalcualte WDR size */
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
pstCfg0->ispCfg.need_update = CVI_TRUE;
} else {
CVI_U32 gainsUpdate = 0, shutterUpdate = 0, vtsUpdate = 0;
pstCfg0->snsCfg.need_update = CVI_FALSE;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
} else {
if ((i >= LINEAR_AGAIN) && (i <= LINEAR_DGAIN_L)) {
gainsUpdate = 1;
}
if (i <= LINEAR_EXP_2) {
shutterUpdate = 1;
}
if ((i >= LINEAR_VTS_0) && (i <= LINEAR_VTS_2)) {
vtsUpdate = 1;
}
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
}
}
if (gainsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_L].bUpdate = CVI_TRUE;
}
if (shutterUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_0].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_1].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_2].bUpdate = CVI_TRUE;
}
if (vtsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_0].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_1].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_2].bUpdate = CVI_TRUE;
}
/* check update isp crop or not */
pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
CVI_TRUE : CVI_FALSE);
@ -582,7 +758,12 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
} else {
pstCfg0->snsCfg.astI2cData[WDR2_FLIP_MIRROR].bDropFrm = CVI_FALSE;
}
return CVI_SUCCESS;
}
@ -611,6 +792,17 @@ static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
if (CV4001_RES_IS_1440P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) {
u8SensorImageMode = CV4001_MODE_2560X1440P15_WDR;
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
@ -677,9 +869,17 @@ static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSn
return;
}
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2;
} else {
start_x = 0;
start_y = 0;
pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].u32Data = value;
pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].bDropFrm = 1;
pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].u8DropFrmNum = 2;
}
g_aeCV4001_MirrorFip[ViPipe] = eSnsMirrorFlip;
pstIspCfg0->img_size[0].stWndRect.s32X = start_x;
pstIspCfg0->img_size[0].stWndRect.s32Y = start_y;
@ -718,8 +918,11 @@ static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
pstRxAttr->img_size.width = g_astCV4001_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
pstRxAttr->img_size.height = g_astCV4001_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
} else {
pstRxAttr->mac_clk = RX_MAC_CLK_400M;
}
return CVI_SUCCESS;

23
middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos_ex.h
View File

@ -36,8 +36,30 @@ enum cv4001_linear_regs_e {
LINEAR_REGS_NUM
};
enum cv4001_wdr2_regs_e {
WDR2_EXP1_0,
WDR2_EXP1_1,
WDR2_EXP1_2,
WDR2_EXP2_0,
WDR2_EXP2_1,
WDR2_EXP2_2,
WDR2_AGAIN1,
WDR2_AGAIN2,
WDR2_DGAIN1_H,
WDR2_DGAIN1_L,
WDR2_DGAIN2_H,
WDR2_DGAIN2_L,
WDR2_VTS_0,
WDR2_VTS_1,
WDR2_VTS_2,
WDR2_FLIP_MIRROR,
WDR2_REGS_NUM
};
typedef enum _CV4001_MODE_E {
CV4001_MODE_2560X1440P25 = 0,
CV4001_MODE_LINEAR_NUM,
CV4001_MODE_2560X1440P15_WDR = CV4001_MODE_LINEAR_NUM,
CV4001_MODE_NUM
} CV4001_MODE_E;
@ -52,6 +74,7 @@ typedef struct _CV4001_MODE_S {
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp[2];
CVI_U32 u32IspResTime;
SNS_ATTR_LARGE_S stAgain[2];
SNS_ATTR_LARGE_S stDgain[2];
char name[64];

122
middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos_param.h
View File

@ -39,13 +39,13 @@ static const CV4001_MODE_S g_astCV4001_mode[CV4001_MODE_NUM] = {
},
},
.f32MaxFps = 25,
.f32MinFps = 0.076, /* 3200 * 25 / 0x0FFFFF */
.u32HtsDef = 743,
.u32VtsDef = 3200,
.f32MinFps = 0.072, /* 1500 * 25 / (0x0FFFFF / 2) */
.u32HtsDef = 1480, //hts_reg * 2
.u32VtsDef = 1500, //vts_reg / 2
.stExp[0] = {
.u16Min = 8,
.u16Max = 3200-4,
.u16Def = 8,
.u16Min = 4,
.u16Max = 1500-2,
.u16Def = 4,
.u16Step = 1,
},
.stAgain[0] = {
@ -61,6 +61,81 @@ static const CV4001_MODE_S g_astCV4001_mode[CV4001_MODE_NUM] = {
.u32Step = 64,
},
},
[CV4001_MODE_2560X1440P15_WDR] = {
.name = "2560X1440P15_WDR",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2560,
.u32Height = 1440,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2560,
.u32Height = 1440,
},
},
.astImg[1] = {
.stSnsSize = {
.u32Width = 2560,
.u32Height = 1440,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2560,
.u32Height = 1440,
},
},
.f32MaxFps = 15,
.f32MinFps = 0.084, /* 1474 * 15 / (0x0FFFFF / 4) */
.u32HtsDef = 5088, //hts_reg * 4
.u32VtsDef = 1474, //vts_reg / 4
.stExp[0] = {
.u16Min = 4,
.u16Max = 1474-1,
.u16Def = 4,
.u16Step = 1,
},
.stExp[1] = {
.u16Min = 4,
.u16Max = 98,
.u16Def = 4,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 1,
},
.stAgain[1] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 64,
},
.stDgain[1] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 64,
},
}
};
@ -97,6 +172,39 @@ static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
},
};
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio_wdr = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {196, 196, 196, 196, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1075, 1075, 1075, 1075
#endif
},
.stAuto = {
{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
1075, 1075},
{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
1075, 1075},
{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
1075, 1075},
{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
1075, 1075},
#endif
},
},
};
struct combo_dev_attr_s cv4001_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
@ -104,7 +212,7 @@ struct combo_dev_attr_s cv4001_rx_attr = {
.raw_data_type = RAW_DATA_12BIT,
.lane_id = {1, 2, 0, -1, -1},
.pn_swap = {1, 1, 1, 0, 0},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
.wdr_mode = CVI_MIPI_WDR_MODE_VC,
},
.mclk = {
.cam = 0,

111
middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_sensor_ctl.c
View File

@ -22,6 +22,7 @@
#define CV4001_CHIP_ID 0x4001
static void cv4001_linear_1440p25_init(VI_PIPE ViPipe);
static void cv4001_wdr_1440p15_2to1_init(VI_PIPE ViPipe);
CVI_U8 cv4001_i2c_addr = 0x35;
const CVI_U32 cv4001_addr_byte = 2;
@ -198,9 +199,23 @@ int cv4001_probe(VI_PIPE ViPipe)
void cv4001_init(VI_PIPE ViPipe)
{
WDR_MODE_E enWDRMode;
CVI_U8 u8ImgMode;
enWDRMode = g_pastCV4001[ViPipe]->enWDRMode;
u8ImgMode = g_pastCV4001[ViPipe]->u8ImgMode;
cv4001_i2c_init(ViPipe);
if (enWDRMode == WDR_MODE_2To1_LINE) {
if (u8ImgMode == CV4001_MODE_2560X1440P15_WDR) {
cv4001_wdr_1440p15_2to1_init(ViPipe);
}
} else {
if (u8ImgMode == CV4001_MODE_2560X1440P25) {
cv4001_linear_1440p25_init(ViPipe);
}
}
g_pastCV4001[ViPipe]->bInit = CVI_TRUE;
}
@ -292,3 +307,99 @@ static void cv4001_linear_1440p25_init(VI_PIPE ViPipe)
printf("ViPipe:%d,===CV4001 1440P 25fps 12bit LINEAR Init OK!===\n", ViPipe);
}
static void cv4001_wdr_1440p15_2to1_init(VI_PIPE ViPipe)
{
cv4001_write_register(ViPipe, 0x3028, 0x08);
cv4001_write_register(ViPipe, 0x3029, 0x17);
cv4001_write_register(ViPipe, 0x302C, 0xF8);
cv4001_write_register(ViPipe, 0x302D, 0x04);
cv4001_write_register(ViPipe, 0x3908, 0x4B);
cv4001_write_register(ViPipe, 0x3304, 0x01);
cv4001_write_register(ViPipe, 0x3305, 0x02);
cv4001_write_register(ViPipe, 0x3306, 0x01);
cv4001_write_register(ViPipe, 0x343E, 0x00);
cv4001_write_register(ViPipe, 0x3401, 0x03);
cv4001_write_register(ViPipe, 0x3035, 0x01);
cv4001_write_register(ViPipe, 0x3036, 0x01);
cv4001_write_register(ViPipe, 0x3020, 0x04);
cv4001_write_register(ViPipe, 0x3048, 0x44);
cv4001_write_register(ViPipe, 0x3049, 0x00);
cv4001_write_register(ViPipe, 0x304A, 0x00);
cv4001_write_register(ViPipe, 0x304B, 0x0A);
cv4001_write_register(ViPipe, 0x3054, 0x2C);
cv4001_write_register(ViPipe, 0x3056, 0xA8);
cv4001_write_register(ViPipe, 0x3057, 0x05);
cv4001_write_register(ViPipe, 0x3030, 0x05);
cv4001_write_register(ViPipe, 0x3060, 0x2C);
cv4001_write_register(ViPipe, 0x3064, 0x12);
cv4001_write_register(ViPipe, 0x3070, 0x1A);//62
cv4001_write_register(ViPipe, 0x3071, 0x00);
cv4001_write_register(ViPipe, 0x343C, 0x01);
cv4001_write_register(ViPipe, 0x3930, 0x00);
cv4001_write_register(ViPipe, 0x3040, 0x01);
cv4001_write_register(ViPipe, 0x3044, 0x04);
cv4001_write_register(ViPipe, 0x3046, 0xA0);
cv4001_write_register(ViPipe, 0x3047, 0x05);
cv4001_write_register(ViPipe, 0x362A, 0x00);
cv4001_write_register(ViPipe, 0x3625, 0x01);
cv4001_write_register(ViPipe, 0x35A4, 0x09);
cv4001_write_register(ViPipe, 0x35A8, 0x09);
cv4001_write_register(ViPipe, 0x35AE, 0x07);
cv4001_write_register(ViPipe, 0x35AF, 0x07);
cv4001_write_register(ViPipe, 0x34A2, 0x2C);
cv4001_write_register(ViPipe, 0x3416, 0x0F);
cv4001_write_register(ViPipe, 0x3418, 0x9F);
cv4001_write_register(ViPipe, 0x341A, 0x57);
cv4001_write_register(ViPipe, 0x341C, 0x57);
cv4001_write_register(ViPipe, 0x341E, 0x6F);
cv4001_write_register(ViPipe, 0x341F, 0x01);
cv4001_write_register(ViPipe, 0x3420, 0x57);
cv4001_write_register(ViPipe, 0x3422, 0x9F);
cv4001_write_register(ViPipe, 0x3424, 0x57);
cv4001_write_register(ViPipe, 0x3426, 0x8F);
cv4001_write_register(ViPipe, 0x3428, 0x47);
cv4001_write_register(ViPipe, 0x3348, 0x00);
cv4001_write_register(ViPipe, 0x3000, 0x00);
cv4001_write_register(ViPipe, 0x3220, 0x03);
cv4001_write_register(ViPipe, 0x3347, 0x01);
cv4001_write_register(ViPipe, 0x3348, 0x00);
cv4001_write_register(ViPipe, 0x3804, 0x0F);
cv4001_write_register(ViPipe, 0x3576, 0x06);
cv4001_write_register(ViPipe, 0x350F, 0x18);
cv4001_write_register(ViPipe, 0x3513, 0x07);
cv4001_write_register(ViPipe, 0x3517, 0x07);
cv4001_write_register(ViPipe, 0x351A, 0x05);
cv4001_write_register(ViPipe, 0x351E, 0x0B);
cv4001_write_register(ViPipe, 0x357A, 0x0B);
cv4001_write_register(ViPipe, 0x3244, 0x08);
cv4001_write_register(ViPipe, 0x3270, 0x60);
cv4001_write_register(ViPipe, 0x3271, 0x00);
cv4001_write_register(ViPipe, 0x3272, 0x00);
cv4001_write_register(ViPipe, 0x3890, 0x01);
cv4001_write_register(ViPipe, 0x3894, 0x05);
cv4001_write_register(ViPipe, 0x3690, 0x00);
cv4001_write_register(ViPipe, 0x3898, 0x20);
cv4001_write_register(ViPipe, 0x3899, 0x20);
cv4001_write_register(ViPipe, 0x389a, 0x20);
cv4001_write_register(ViPipe, 0x389b, 0x20);
cv4001_write_register(ViPipe, 0x389c, 0x20);
cv4001_write_register(ViPipe, 0x389d, 0x15);
cv4001_write_register(ViPipe, 0x389e, 0x05);
cv4001_write_register(ViPipe, 0x3583, 0x2f);
cv4001_write_register(ViPipe, 0x3b75, 0x00);
cv4001_write_register(ViPipe, 0x3b5E, 0x01);
cv4001_write_register(ViPipe, 0x3a10, 0x06);
cv4001_write_register(ViPipe, 0x3a11, 0x06);
cv4001_write_register(ViPipe, 0x316C, 0x64);
cv4001_write_register(ViPipe, 0x3162, 0x01);
cv4001_write_register(ViPipe, 0x3180, 0x00);
cv4001_write_register(ViPipe, 0x3178, 0x40);
cv4001_write_register(ViPipe, 0x3179, 0x00);
cv4001_default_reg_init(ViPipe);
delay_ms(100);
printf("ViPipe:%d,===CV4001 1440P 15fps 12bit WDR2TO1 Init OK!===\n", ViPipe);
}

48
middleware/v2/component/isp/sensor/cv181x/soi_k06/k06_sensor_ctl.c
View File

@ -160,26 +160,36 @@ void k06_default_reg_init(VI_PIPE ViPipe)
void k06_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 val = k06_read_register(ViPipe, 0x12) & (~0x30);
CVI_U8 val1 = k06_read_register(ViPipe, 0x12);
CVI_U8 val2 = k06_read_register(ViPipe, 0xAA);
CVI_U8 val3 = k06_read_register(ViPipe, 0x27);
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
val |= 0x30;
val1 = 0x30;
val2 = 0x84;
break;
case ISP_SNS_MIRROR:
val |= (0x1 << 4);
val1 = 0x10;
val2 = 0x8B;
val3 += 1;
break;
case ISP_SNS_FLIP:
val |= (0x2 << 4);
val1 = 0x20;
val2 = 0x84;
break;
case ISP_SNS_MIRROR_FLIP:
val &= ~(0x1 << 4);
val1 = 0x00;
val2 = 0x8B;
val3 += 1;
break;
default:
return;
}
k06_write_register(ViPipe, 0x12, val);
k06_write_register(ViPipe, 0x12, val1);
k06_write_register(ViPipe, 0xAA, val2);
k06_write_register(ViPipe, 0x27, val3);
}
int k06_probe(VI_PIPE ViPipe)
@ -235,6 +245,7 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
k06_write_register(ViPipe, 0x10, 0x48);
k06_write_register(ViPipe, 0x11, 0x80);
k06_write_register(ViPipe, 0x46, 0x08);
k06_write_register(ViPipe, 0x7F, 0x5E);
k06_write_register(ViPipe, 0x0D, 0xA0);
k06_write_register(ViPipe, 0x57, 0x67);
k06_write_register(ViPipe, 0x58, 0x1F);
@ -247,10 +258,10 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
k06_write_register(ViPipe, 0x24, 0x80);
k06_write_register(ViPipe, 0x25, 0xA0);
k06_write_register(ViPipe, 0x26, 0x52);
k06_write_register(ViPipe, 0x27, 0x27);
k06_write_register(ViPipe, 0x27, 0x46);
k06_write_register(ViPipe, 0x28, 0x15);
k06_write_register(ViPipe, 0x29, 0x04);
k06_write_register(ViPipe, 0x2A, 0x20);
k06_write_register(ViPipe, 0x2A, 0x40);
k06_write_register(ViPipe, 0x2B, 0x14);
k06_write_register(ViPipe, 0x2C, 0x00);
k06_write_register(ViPipe, 0x2D, 0x00);
@ -263,36 +274,35 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
k06_write_register(ViPipe, 0x77, 0x0C);
k06_write_register(ViPipe, 0x80, 0x01);
k06_write_register(ViPipe, 0xAF, 0x12);
k06_write_register(ViPipe, 0xAA, 0x04);
k06_write_register(ViPipe, 0xAA, 0x84);
k06_write_register(ViPipe, 0x1D, 0x00);
k06_write_register(ViPipe, 0x1E, 0x04);
k06_write_register(ViPipe, 0x6C, 0x40);
k06_write_register(ViPipe, 0x9E, 0xF8);
k06_write_register(ViPipe, 0x0C, 0x30);
k06_write_register(ViPipe, 0x6F, 0x80);
k06_write_register(ViPipe, 0x0C, 0x00);
k06_write_register(ViPipe, 0x6E, 0x2C);
k06_write_register(ViPipe, 0x70, 0xF9);
k06_write_register(ViPipe, 0x71, 0xDD);
k06_write_register(ViPipe, 0x72, 0xD5);
k06_write_register(ViPipe, 0x73, 0x5A);
k06_write_register(ViPipe, 0x74, 0x02);
k06_write_register(ViPipe, 0x78, 0x1D);
k06_write_register(ViPipe, 0x78, 0x1C);
k06_write_register(ViPipe, 0x89, 0x01);
k06_write_register(ViPipe, 0x6B, 0x20);
k06_write_register(ViPipe, 0x86, 0x40);
k06_write_register(ViPipe, 0x6F, 0x00);
k06_write_register(ViPipe, 0x30, 0x8D);
k06_write_register(ViPipe, 0x31, 0x08);
k06_write_register(ViPipe, 0x32, 0x20);
k06_write_register(ViPipe, 0x33, 0x5C);
k06_write_register(ViPipe, 0x34, 0x30);
k06_write_register(ViPipe, 0x35, 0x30);
k06_write_register(ViPipe, 0x3A, 0xB6);
k06_write_register(ViPipe, 0x3A, 0xB9);
k06_write_register(ViPipe, 0x56, 0x92);
k06_write_register(ViPipe, 0x59, 0x48);
k06_write_register(ViPipe, 0x59, 0x60);
k06_write_register(ViPipe, 0x5A, 0x01);
k06_write_register(ViPipe, 0x61, 0x00);
k06_write_register(ViPipe, 0x64, 0xC0);
k06_write_register(ViPipe, 0x7F, 0x46);
k06_write_register(ViPipe, 0x85, 0x44);
k06_write_register(ViPipe, 0x8A, 0x00);
k06_write_register(ViPipe, 0x91, 0x58);
@ -317,14 +327,14 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
k06_write_register(ViPipe, 0x8F, 0x90);
k06_write_register(ViPipe, 0xA4, 0xC7);
k06_write_register(ViPipe, 0xA5, 0xAF);
k06_write_register(ViPipe, 0xB7, 0x21);
k06_write_register(ViPipe, 0xB7, 0x61);
k06_write_register(ViPipe, 0x97, 0x20);
k06_write_register(ViPipe, 0x13, 0x81);
k06_write_register(ViPipe, 0x96, 0x84);
k06_write_register(ViPipe, 0x4A, 0x01);
k06_write_register(ViPipe, 0x7E, 0x4C);
k06_write_register(ViPipe, 0x50, 0x02);
k06_write_register(ViPipe, 0x93, 0xC0);
k06_write_register(ViPipe, 0x93, 0x00);
k06_write_register(ViPipe, 0xB5, 0x4C);
k06_write_register(ViPipe, 0xB1, 0x00);
k06_write_register(ViPipe, 0xA1, 0x0F);
@ -340,10 +350,12 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
k06_write_register(ViPipe, 0x1B, 0x4F);
k06_default_reg_init(ViPipe);
// k06_write_register(ViPipe, 0x12, 0x00);
k06_write_register(ViPipe, 0x12, 0x30);
k06_write_register(ViPipe, 0x48, 0x86);
k06_write_register(ViPipe, 0x48, 0x06);
k06_write_register(ViPipe, 0x00, 0x10);
printf("ViPipe:%d,===K06 1440P 25fps 10bit LINE Init OK!===\n", ViPipe);
}

32
middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos.c
View File

@ -67,6 +67,7 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
#define Q03P_SHS1_ADDR 0x01
#define Q03P_GAIN_ADDR 0x00
#define Q03P_VMAX_ADDR 0x22
#define Q03P_FLIP_MIRROR_ADDR 0x12
#define Q03P_TABLE_END 0xff
#define Q03P_RES_IS_1296P(w, h) ((w) <= 2304 && (h) <= 1296)
@ -500,6 +501,8 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
pstI2c_data[LINEAR_VMAX_1_DATA].u32RegAddr = Q03P_VMAX_ADDR + 1;
pstI2c_data[LINEAR_VMAX_1_DATA].u8DelayFrmNum = 2;
pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = Q03P_FLIP_MIRROR_ADDR;
break;
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode);
@ -529,6 +532,7 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
return CVI_SUCCESS;
}
@ -579,12 +583,38 @@ static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S
static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 value = q03p_read_register(ViPipe, Q03P_FLIP_MIRROR_ADDR) & ~0x30;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
/* Apply the setting on the fly */
if (pstSnsState->bInit == CVI_TRUE && g_aeQ03P_MirrorFip[ViPipe] != eSnsMirrorFlip) {
q03p_mirror_flip(ViPipe, eSnsMirrorFlip);
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
value |= 0x00;
break;
case ISP_SNS_MIRROR:
value |= 0x20;
break;
case ISP_SNS_FLIP:
value |= 0x10;
break;
case ISP_SNS_MIRROR_FLIP:
value |= 0x30;
break;
default:
return;
}
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2;
g_aeQ03P_MirrorFip[ViPipe] = eSnsMirrorFlip;
}
}

2
middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos_ex.h
View File

@ -28,6 +28,7 @@ enum q03p_linear_regs_e {
LINEAR_AGAIN_DATA,
LINEAR_VMAX_0_DATA,
LINEAR_VMAX_1_DATA,
LINEAR_FLIP_MIRROR,
LINEAR_REGS_NUM
};
@ -64,7 +65,6 @@ extern CVI_U16 g_au16Q03P_L2SMode[];
extern CVI_U8 q03p_i2c_addr;
extern const CVI_U32 q03p_addr_byte;
extern const CVI_U32 q03p_data_byte;
extern void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern void q03p_init(VI_PIPE ViPipe);
extern void q03p_exit(VI_PIPE ViPipe);
extern void q03p_standby(VI_PIPE ViPipe);

23
middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_sensor_ctl.c
View File

@ -175,29 +175,6 @@ void q03p_default_reg_init(VI_PIPE ViPipe)
}
}
void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 val = q03p_read_register(ViPipe, 0x12) & ~0x30;
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
break;
case ISP_SNS_MIRROR:
val |= 0x20;
break;
case ISP_SNS_FLIP:
val |= 0x10;
break;
case ISP_SNS_MIRROR_FLIP:
val |= 0x30;
break;
default:
return;
}
q03p_write_register(ViPipe, 0x12, val);
}
int q03p_probe(VI_PIPE ViPipe)
{
int nVal;

4
middleware/v2/component/panel/cv180x/bt656_tp2803.h
View File

@ -3,7 +3,7 @@
#include <linux/cvi_comm_vo.h>
const struct VO_BT_PINS tp2803_pins_cfg = {
const struct VO_PINMUX tp2803_pins_cfg = {
.pin_num = 9,
.d_pins = {
{VO_VIVO_D0, VO_MUX_BT_DATA0},
@ -20,8 +20,6 @@ const struct VO_BT_PINS tp2803_pins_cfg = {
const VO_BT_ATTR_S stTP2803Cfg = {
.pins = tp2803_pins_cfg,
.mode = VO_BT_MODE_656,
.bt_clk = VO_BT_CLK_MODE_72M,
};
#endif // _I80_PARAM_ST7789V_H_

117
middleware/v2/component/panel/cv180x/hw_mcu_st7789v3.h Normal file
View File

@ -0,0 +1,117 @@
#ifndef _MCU_PARAM_ST7789V_H_
#define _MCU_PARAM_ST7789V_H_
#include <linux/cvi_comm_vo.h>
#define COMMAND 0
#define DATA 1
const struct VO_PINMUX st7789v3_pins_cfg = {
.pin_num = 11,
.d_pins = {
{VO_MIPI_TXM4, VO_MUX_MCU_DATA0},
{VO_MIPI_TXP4, VO_MUX_MCU_DATA1},
{VO_MIPI_TXM3, VO_MUX_MCU_DATA2},
{VO_MIPI_TXP3, VO_MUX_MCU_DATA3},
{VO_MIPI_TXM2, VO_MUX_MCU_DATA4},
{VO_MIPI_TXP2, VO_MUX_MCU_DATA5},
{VO_MIPI_TXM1, VO_MUX_MCU_DATA6},
{VO_MIPI_TXP1, VO_MUX_MCU_DATA7},
{VO_MIPI_TXM0, VO_MUX_MCU_RD},
{VO_MIPI_TXP0, VO_MUX_MCU_WR},
{VO_VIVO_D10, VO_MUX_MCU_RS},
}
};
const struct VO_MCU_INSTRS st7789v3_instrs = {
.instr_num = 72,
.instr_cmd = {
{.delay = 0, .data_type = COMMAND, .data = 0x11},
{.delay = 0, .data_type = COMMAND, .data = 0x35},
{.delay = 0, .data_type = DATA, .data = 0x00},
{.delay = 0, .data_type = COMMAND, .data = 0x36},//Display Setting
{.delay = 0, .data_type = DATA, .data = (1<<6)/*(1<<5)|(1<<6)*/},
{.delay = 0, .data_type = COMMAND, .data = 0x3A},
{.delay = 0, .data_type = DATA, .data = 0x05},
{.delay = 0, .data_type = COMMAND, .data = 0xB2},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = DATA, .data = 0x00},
{.delay = 0, .data_type = DATA, .data = 0x33},
{.delay = 0, .data_type = DATA, .data = 0x33},
{.delay = 0, .data_type = COMMAND, .data = 0xB7},
{.delay = 0, .data_type = DATA, .data = 0x75},
{.delay = 0, .data_type = COMMAND, .data = 0xBB},
{.delay = 0, .data_type = DATA, .data = 0x19},
{.delay = 0, .data_type = COMMAND, .data = 0xC0},
{.delay = 0, .data_type = DATA, .data = 0x2C},
{.delay = 0, .data_type = COMMAND, .data = 0xC2},
{.delay = 0, .data_type = DATA, .data = 0x01},
{.delay = 0, .data_type = COMMAND, .data = 0xC3},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = COMMAND, .data = 0xC4},
{.delay = 0, .data_type = DATA, .data = 0x20},
{.delay = 0, .data_type = COMMAND, .data = 0xC6},
{.delay = 0, .data_type = DATA, .data = 0x0F},
{.delay = 0, .data_type = COMMAND, .data = 0xD0},
{.delay = 0, .data_type = DATA, .data = 0xA4},
{.delay = 0, .data_type = DATA, .data = 0xA1},
{.delay = 0, .data_type = COMMAND, .data = 0xE0},//Gamma setting
{.delay = 0, .data_type = DATA, .data = 0xD0},
{.delay = 0, .data_type = DATA, .data = 0x04},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = DATA, .data = 0x0E},
{.delay = 0, .data_type = DATA, .data = 0x0E},
{.delay = 0, .data_type = DATA, .data = 0x29},
{.delay = 0, .data_type = DATA, .data = 0x37},
{.delay = 0, .data_type = DATA, .data = 0x44},
{.delay = 0, .data_type = DATA, .data = 0x47},
{.delay = 0, .data_type = DATA, .data = 0x0B},
{.delay = 0, .data_type = DATA, .data = 0x17},
{.delay = 0, .data_type = DATA, .data = 0x16},
{.delay = 0, .data_type = DATA, .data = 0x1B},
{.delay = 0, .data_type = DATA, .data = 0x1F},
{.delay = 0, .data_type = COMMAND, .data = 0xE1},
{.delay = 0, .data_type = DATA, .data = 0xD0},
{.delay = 0, .data_type = DATA, .data = 0x04},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = DATA, .data = 0x0E},
{.delay = 0, .data_type = DATA, .data = 0x0F},
{.delay = 0, .data_type = DATA, .data = 0x29},
{.delay = 0, .data_type = DATA, .data = 0x37},
{.delay = 0, .data_type = DATA, .data = 0x44},
{.delay = 0, .data_type = DATA, .data = 0x4A},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = DATA, .data = 0x17},
{.delay = 0, .data_type = DATA, .data = 0x16},
{.delay = 0, .data_type = DATA, .data = 0x1B},
{.delay = 0, .data_type = DATA, .data = 0x1F},
{.delay = 0, .data_type = COMMAND, .data = 0x29},
{.delay = 0, .data_type = COMMAND, .data = 0x2A},
{.delay = 0, .data_type = DATA, .data = 0x0 },//Xstart
{.delay = 0, .data_type = DATA, .data = 0x0 },
{.delay = 0, .data_type = DATA, .data = 0x0 },//Xend
{.delay = 0, .data_type = DATA, .data = 0xEF},
{.delay = 0, .data_type = COMMAND, .data = 0x2B},
{.delay = 0, .data_type = DATA, .data = 0x0 },//Ystart
{.delay = 0, .data_type = DATA, .data = 0x0 },
{.delay = 0, .data_type = DATA, .data = 0x01},//Yend
{.delay = 0, .data_type = DATA, .data = 0x3F},
{.delay = 0, .data_type = COMMAND, .data = 0x2C},
}
};
const VO_HW_MCU_CFG_S st7789v3Cfg = {
.pins = st7789v3_pins_cfg,
.mode = VO_MCU_MODE_RGB565,
.lcd_power_gpio_num = GPIOB_03,
.lcd_power_avtive = GPIO_ACTIVE_HIGH,
.backlight_gpio_num = GPIOA_30,
.backlight_avtive = GPIO_ACTIVE_HIGH,
.reset_gpio_num = GPIOE_13,
.reset_avtive = GPIO_ACTIVE_LOW,
.instrs = st7789v3_instrs,
};
#endif // _MCU_PARAM_ST7789V_H_

15
middleware/v2/component/panel/cv180x/lvds_lcm185x56.h Normal file
View File

@ -0,0 +1,15 @@
#ifndef _LVDS_PARAM_LCM185X56_H_
#define _LVDS_PARAM_LCM185X56_H_
#include <linux/cvi_comm_vo.h>
const VO_LVDS_ATTR_S lvds_lcm185x56_cfg = {
.lvds_vesa_mode = VO_LVDS_MODE_JEIDA,
.out_bits = VO_LVDS_OUT_8BIT,
.chn_num = 1,
.data_big_endian = 0,
.lane_id = {VO_LVDS_LANE_0, VO_LVDS_LANE_1, VO_LVDS_LANE_CLK, VO_LVDS_LANE_2, VO_LVDS_LANE_3},
.lane_pn_swap = {false, false, false, false, false},
};
#endif // _LVDS_PARAM_LCM185X56_H_

4
middleware/v2/component/panel/cv181x/bt656_tp2803.h
View File

@ -3,7 +3,7 @@
#include <linux/cvi_comm_vo.h>
const struct VO_BT_PINS tp2803_pins_cfg = {
const struct VO_PINMUX tp2803_pins_cfg = {
.pin_num = 9,
.d_pins = {
{VO_VIVO_D0, VO_MUX_BT_DATA0},
@ -20,8 +20,6 @@ const struct VO_BT_PINS tp2803_pins_cfg = {
const VO_BT_ATTR_S stTP2803Cfg = {
.pins = tp2803_pins_cfg,
.mode = VO_BT_MODE_656,
.bt_clk = VO_BT_CLK_MODE_72M,
};
#endif // _I80_PARAM_ST7789V_H_

117
middleware/v2/component/panel/cv181x/hw_mcu_st7789v3.h Normal file
View File

@ -0,0 +1,117 @@
#ifndef _MCU_PARAM_ST7789V_H_
#define _MCU_PARAM_ST7789V_H_
#include <linux/cvi_comm_vo.h>
#define COMMAND 0
#define DATA 1
const struct VO_PINMUX st7789v3_pins_cfg = {
.pin_num = 11,
.d_pins = {
{VO_MIPI_TXM4, VO_MUX_MCU_DATA0},
{VO_MIPI_TXP4, VO_MUX_MCU_DATA1},
{VO_MIPI_TXM3, VO_MUX_MCU_DATA2},
{VO_MIPI_TXP3, VO_MUX_MCU_DATA3},
{VO_MIPI_TXM2, VO_MUX_MCU_DATA4},
{VO_MIPI_TXP2, VO_MUX_MCU_DATA5},
{VO_MIPI_TXM1, VO_MUX_MCU_DATA6},
{VO_MIPI_TXP1, VO_MUX_MCU_DATA7},
{VO_MIPI_TXM0, VO_MUX_MCU_RD},
{VO_MIPI_TXP0, VO_MUX_MCU_WR},
{VO_VIVO_D10, VO_MUX_MCU_RS},
}
};
const struct VO_MCU_INSTRS st7789v3_instrs = {
.instr_num = 72,
.instr_cmd = {
{.delay = 0, .data_type = COMMAND, .data = 0x11},
{.delay = 0, .data_type = COMMAND, .data = 0x35},
{.delay = 0, .data_type = DATA, .data = 0x00},
{.delay = 0, .data_type = COMMAND, .data = 0x36},//Display Setting
{.delay = 0, .data_type = DATA, .data = (1<<6)/*(1<<5)|(1<<6)*/},
{.delay = 0, .data_type = COMMAND, .data = 0x3A},
{.delay = 0, .data_type = DATA, .data = 0x05},
{.delay = 0, .data_type = COMMAND, .data = 0xB2},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = DATA, .data = 0x00},
{.delay = 0, .data_type = DATA, .data = 0x33},
{.delay = 0, .data_type = DATA, .data = 0x33},
{.delay = 0, .data_type = COMMAND, .data = 0xB7},
{.delay = 0, .data_type = DATA, .data = 0x75},
{.delay = 0, .data_type = COMMAND, .data = 0xBB},
{.delay = 0, .data_type = DATA, .data = 0x19},
{.delay = 0, .data_type = COMMAND, .data = 0xC0},
{.delay = 0, .data_type = DATA, .data = 0x2C},
{.delay = 0, .data_type = COMMAND, .data = 0xC2},
{.delay = 0, .data_type = DATA, .data = 0x01},
{.delay = 0, .data_type = COMMAND, .data = 0xC3},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = COMMAND, .data = 0xC4},
{.delay = 0, .data_type = DATA, .data = 0x20},
{.delay = 0, .data_type = COMMAND, .data = 0xC6},
{.delay = 0, .data_type = DATA, .data = 0x0F},
{.delay = 0, .data_type = COMMAND, .data = 0xD0},
{.delay = 0, .data_type = DATA, .data = 0xA4},
{.delay = 0, .data_type = DATA, .data = 0xA1},
{.delay = 0, .data_type = COMMAND, .data = 0xE0},//Gamma setting
{.delay = 0, .data_type = DATA, .data = 0xD0},
{.delay = 0, .data_type = DATA, .data = 0x04},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = DATA, .data = 0x0E},
{.delay = 0, .data_type = DATA, .data = 0x0E},
{.delay = 0, .data_type = DATA, .data = 0x29},
{.delay = 0, .data_type = DATA, .data = 0x37},
{.delay = 0, .data_type = DATA, .data = 0x44},
{.delay = 0, .data_type = DATA, .data = 0x47},
{.delay = 0, .data_type = DATA, .data = 0x0B},
{.delay = 0, .data_type = DATA, .data = 0x17},
{.delay = 0, .data_type = DATA, .data = 0x16},
{.delay = 0, .data_type = DATA, .data = 0x1B},
{.delay = 0, .data_type = DATA, .data = 0x1F},
{.delay = 0, .data_type = COMMAND, .data = 0xE1},
{.delay = 0, .data_type = DATA, .data = 0xD0},
{.delay = 0, .data_type = DATA, .data = 0x04},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = DATA, .data = 0x0E},
{.delay = 0, .data_type = DATA, .data = 0x0F},
{.delay = 0, .data_type = DATA, .data = 0x29},
{.delay = 0, .data_type = DATA, .data = 0x37},
{.delay = 0, .data_type = DATA, .data = 0x44},
{.delay = 0, .data_type = DATA, .data = 0x4A},
{.delay = 0, .data_type = DATA, .data = 0x0C},
{.delay = 0, .data_type = DATA, .data = 0x17},
{.delay = 0, .data_type = DATA, .data = 0x16},
{.delay = 0, .data_type = DATA, .data = 0x1B},
{.delay = 0, .data_type = DATA, .data = 0x1F},
{.delay = 0, .data_type = COMMAND, .data = 0x29},
{.delay = 0, .data_type = COMMAND, .data = 0x2A},
{.delay = 0, .data_type = DATA, .data = 0x0 },//Xstart
{.delay = 0, .data_type = DATA, .data = 0x0 },
{.delay = 0, .data_type = DATA, .data = 0x0 },//Xend
{.delay = 0, .data_type = DATA, .data = 0xEF},
{.delay = 0, .data_type = COMMAND, .data = 0x2B},
{.delay = 0, .data_type = DATA, .data = 0x0 },//Ystart
{.delay = 0, .data_type = DATA, .data = 0x0 },
{.delay = 0, .data_type = DATA, .data = 0x01},//Yend
{.delay = 0, .data_type = DATA, .data = 0x3F},
{.delay = 0, .data_type = COMMAND, .data = 0x2C},
}
};
const VO_HW_MCU_CFG_S st7789v3Cfg = {
.pins = st7789v3_pins_cfg,
.mode = VO_MCU_MODE_RGB565,
.lcd_power_gpio_num = GPIOB_03,
.lcd_power_avtive = GPIO_ACTIVE_HIGH,
.backlight_gpio_num = GPIOA_30,
.backlight_avtive = GPIO_ACTIVE_HIGH,
.reset_gpio_num = GPIOE_13,
.reset_avtive = GPIO_ACTIVE_LOW,
.instrs = st7789v3_instrs,
};
#endif // _MCU_PARAM_ST7789V_H_

15
middleware/v2/component/panel/cv181x/lvds_lcm185x56.h Normal file
View File

@ -0,0 +1,15 @@
#ifndef _LVDS_PARAM_LCM185X56_H_
#define _LVDS_PARAM_LCM185X56_H_
#include <linux/cvi_comm_vo.h>
const VO_LVDS_ATTR_S lvds_lcm185x56_cfg = {
.lvds_vesa_mode = VO_LVDS_MODE_JEIDA,
.out_bits = VO_LVDS_OUT_8BIT,
.chn_num = 1,
.data_big_endian = 0,
.lane_id = {VO_LVDS_LANE_0, VO_LVDS_LANE_1, VO_LVDS_LANE_CLK, VO_LVDS_LANE_2, VO_LVDS_LANE_3},
.lane_pn_swap = {false, false, false, false, false},
};
#endif // _LVDS_PARAM_LCM185X56_H_

BIN
middleware/v2/cv180x/ko/cv180x_base.ko
View File

Binary file not shown.

BIN
middleware/v2/cv180x/ko/cv180x_rgn.ko
View File

Binary file not shown.

BIN
middleware/v2/cv180x/ko/cv180x_vi.ko
View File

Binary file not shown.

BIN
middleware/v2/cv180x/ko/cv180x_vpss.ko
View File

Binary file not shown.

BIN
middleware/v2/cv180x/ko/cvi_vc_driver.ko
View File

Binary file not shown.

BIN
middleware/v2/cv180x/ko_shrink/3rd/cvi_wiegand_gpio.ko
View File

Binary file not shown.

BIN
middleware/v2/cv180x/ko_shrink/cv180x_base.ko
View File

Binary file not shown.

BIN
middleware/v2/cv180x/ko_shrink/cv180x_rgn.ko
View File

Binary file not shown.

BIN
middleware/v2/cv180x/ko_shrink/cv180x_saradc.ko
View File

Binary file not shown.

BIN
middleware/v2/cv180x/ko_shrink/cv180x_vpss.ko
View File

Binary file not shown.

BIN
middleware/v2/cv180x/ko_shrink/cvi_vc_driver.ko
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/3rd/libini.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/3rd/libini.so
View File

Binary file not shown.

1
middleware/v2/cv180x/lib_glibc_riscv64/3rd/libjson-c.so.5 Symbolic link
View File

@ -0,0 +1 @@
libjson-c.so.5.1.0

BIN
middleware/v2/cv180x/lib_glibc_riscv64/3rd/libjson-c.so.5.1.0 Normal file
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libae.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libae.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libaf.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libaf.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libawb.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libawb.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcipher.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcipher.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_VoiceEngine.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_VoiceEngine.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_audio.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_audio.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_bin.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_bin_isp.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_ispd2.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_ispd2.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_ssp.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_ssp.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_vqe.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libcvi_vqe.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libdnvqe.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libdnvqe.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libisp.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libisp.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libisp_algo.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libisp_algo.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libmipi_tx.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libmipi_tx.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libmisc.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libmisc.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libosdc.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libosdc.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libraw_dump.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libraw_dump.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libraw_replay.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libraw_replay.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libsys.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libsys.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libvdec.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libvdec.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libvenc.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libvenc.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libvpu.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_glibc_riscv64/libvpu.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/3rd/libini.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/3rd/libini.so
View File

Binary file not shown.

1
middleware/v2/cv180x/lib_musl_riscv64/3rd/libjson-c.so.5 Symbolic link
View File

@ -0,0 +1 @@
libjson-c.so.5.1.0

BIN
middleware/v2/cv180x/lib_musl_riscv64/3rd/libjson-c.so.5.1.0 Normal file
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libae.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libae.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libaf.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libaf.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libawb.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libawb.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libcipher.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libcipher.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libcvi_VoiceEngine.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libcvi_VoiceEngine.so
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libcvi_audio.a
View File

Binary file not shown.

BIN
middleware/v2/cv180x/lib_musl_riscv64/libcvi_audio.so
View File

Binary file not shown.

Some files were not shown because too many files have changed in this diff Show More