776 lines
18 KiB
Plaintext
776 lines
18 KiB
Plaintext
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/cv1835-resets.h>
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#include <dt-bindings/sound/cv1835-audio.h>
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/dts-v1/;
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/memreserve/ 0x0000000100000000 0x0000000000020000; // ATF BL31
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/ {
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compatible = "linux,dummy-virt";
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#size-cells = <0x2>;
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#address-cells = <0x2>;
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interrupt-parent = <&gic>;
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rst: reset-controller {
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#reset-cells = <1>;
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compatible = "cvitek,reset";
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reg = <0x0 0x03003000 0x0 0x10>;
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};
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gic: interrupt-controller {
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compatible = "arm,cortex-a15-gic";
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ranges;
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#size-cells = <0x2>;
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#address-cells = <0x2>;
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0x0 0x01F01000 0x0 0x1000>,
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<0x0 0x01F02000 0x0 0x2000>;
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};
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psci {
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migrate = <0xc4000005>;
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cpu_on = <0xc4000003>;
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cpu_off = <0x84000002>;
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cpu_suspend = <0xc4000001>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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method = "smc";
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compatible = "arm,psci-0.2", "arm,psci";
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};
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cpus {
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#size-cells = <0x0>;
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#address-cells = <0x1>;
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A53_0: cpu@0 {
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reg = <0x0>;
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enable-method = "psci";
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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next-level-cache = <&CA53_L2>;
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};
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A53_1: cpu@1 {
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reg = <0x1>;
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enable-method = "psci";
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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next-level-cache = <&CA53_L2>;
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};
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CA53_L2: l2-cache0 {
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compatible = "cache";
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};
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};
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cvitek-ion {
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compatible = "cvitek,cvitek-ion";
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heap_carveout@0 {
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compatible = "cvitek,carveout";
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memory-region = <&ion_reserved>;
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};
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};
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reserved-memory {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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ranges;
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cma_reserved: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x1000000>; // 16MB
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alignment = <0x0 0x2000>; // 8KB
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linux,cma-default;
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};
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ion_reserved: ion {
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compatible = "ion-region";
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size = <0x0 0x07000000>; // 96MB + vip 16MB
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};
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vcodec_reserved: vcodec {
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/* <start, length> pair
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* and restrict to 4G address range
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*/
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alloc-ranges = <0x1 0x00000000 0 0xF0000000>;
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size = <0x0 0x06000000>; // 96MB
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no-map;
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};
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jpu_reserved: jpu {
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/* <start, length> pair
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* and restrict to 4G address range
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*/
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alloc-ranges = <0x1 0x00000000 0 0xFFFFFFFF>;
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size = <0x0 0x01000000>; // 16MB
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no-map;
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};
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};
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dmac: dma@0x4330000 {
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compatible = "snps,dmac-bm";
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reg = <0x0 0x04330000 0x0 0x1000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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dma-channels = /bits/ 8 <8>;
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#dma-cells = <3>;
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dma-requests = /bits/ 8 <16>;
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chan_allocation_order = /bits/ 8 <0>;
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chan_priority = /bits/ 8 <0>;
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block_size = <32>; /* max 32 data items */
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dma-masters = /bits/ 8 <2>;
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data-width = <4 4>; /* bytes */
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axi_tr_width = <4>; /* bytes */
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block-ts = <15>;
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};
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pwm0: pwm@3060000 {
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compatible = "cvitek,cvi-pwm";
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reg = <0x0 0x3060000 0x0 0x1000>;
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clocks = <&pclk>;
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#pwm-cells = <1>;
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};
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pwm1: pwm@3061000 {
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compatible = "cvitek,cvi-pwm";
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reg = <0x0 0x3061000 0x0 0x1000>;
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clocks = <&pclk>;
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#pwm-cells = <2>;
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};
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pwm2: pwm@3062000 {
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compatible = "cvitek,cvi-pwm";
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reg = <0x0 0x3062000 0x0 0x1000>;
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clocks = <&pclk>;
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#pwm-cells = <3>;
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};
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pwm3: pwm@3063000 {
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compatible = "cvitek,cvi-pwm";
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reg = <0x0 0x3063000 0x0 0x1000>;
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clocks = <&pclk>;
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#pwm-cells = <4>;
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};
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watchdog0: cv-wd@0x3010000 {
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compatible = "snps,dw-wdt";
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reg = <0x0 0x03010000 0x0 0x1000>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_WDT>;
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clocks = <&pclk>;
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};
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timer {
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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always-on;
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clock-frequency = <25000000>;
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compatible = "arm,armv8-timer";
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};
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i2c_srcclk: clk25mhz {
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clock-output-names = "clk25mhz";
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clock-frequency = <25000000>;
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#clock-cells = <0x0>;
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compatible = "fixed-clock";
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};
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audio_clock: audio_clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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#if 0
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clock-frequency = <12288000>;
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#else
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clock-frequency = <24576000>;
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#endif
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};
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i2c0: i2c@04000000 {
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compatible = "snps,designware-i2c";
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clocks = <&i2c_srcclk>;
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reg = <0x0 0x04000000 0x0 0x1000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000>;
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#size-cells = <0x0>;
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#address-cells = <0x1>;
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resets = <&rst RST_I2C0>;
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reset-names = "i2c0";
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adau1372_1: adau1372@3c {
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compatible = "adi,adau1372";
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reg = <0x3c>;
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clocks = <&audio_clock>;
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clock-names = "mclk";
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};
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};
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i2c3: i2c@04030000 {
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compatible = "snps,designware-i2c";
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clocks = <&i2c_srcclk>;
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reg = <0x0 0x04030000 0x0 0x1000>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000>;
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#size-cells = <0x0>;
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#address-cells = <0x1>;
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resets = <&rst RST_I2C3>;
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reset-names = "i2c3";
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};
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pclk: pclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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gpio0: gpio@03020000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x03020000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "porta";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio1: gpio@03021000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x03021000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portb: gpio-controller@1 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "portb";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio2: gpio@03022000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x03022000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portc: gpio-controller@2 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "portc";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio3: gpio@03023000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x03023000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portd: gpio-controller@2 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "portd";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <12>;
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reg = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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spi0:spi0@04180000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x0 0x04180000 0x0 0x10000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pclk>;
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clock-frequency = <25000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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//switch-gpios = <&port0a 7 0>;
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spidev: spidev@0 {
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compatible = "rohm,dh2228fv";
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//memory-region = <&spi_lcd_reserved>;
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spi-max-frequency = <25000000>;
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reg = <0>;
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};
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};
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eth_csrclk: eth_csrclk {
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clock-output-names = "eth_csrclk";
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clock-frequency = <25000000>;
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#clock-cells = <0x0>;
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compatible = "fixed-clock";
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};
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eth_ptpclk: eth_ptpclk {
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clock-output-names = "eth_ptpclk";
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clock-frequency = <50000000>;
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#clock-cells = <0x0>;
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compatible = "fixed-clock";
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};
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uart0: serial@04140000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x04140000 0x0 0x1000>;
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clock-frequency = <25000000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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#if 0
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uart1: serial@04150000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x04150000 0x0 0x1000>;
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clock-frequency = <25000000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart2: serial@04160000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x04160000 0x0 0x1000>;
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clock-frequency = <25000000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart3: serial@04170000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x04170000 0x0 0x1000>;
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clock-frequency = <25000000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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#endif
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stmmac_axi_setup: stmmac-axi-config {
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snps,wr_osr_lmt = <1>;
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snps,rd_osr_lmt = <2>;
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snps,blen = <4 8 16 0 0 0 0>;
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};
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mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <4>;
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queue0 {};
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queue1 {};
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queue2 {};
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queue3 {};
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};
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mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <4>;
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queue0 {};
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queue1 {};
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queue2 {};
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queue3 {};
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};
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#if 1
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ethernet0: ethernet@4510000 {
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compatible = "cvitek,ethernet";
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reg = <0x0 0x04510000 0x0 0x10000>;
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interrupt-names = "macirq";
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "stmmaceth", "ptp_ref";
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clocks = <ð_csrclk>, <ð_ptpclk>;
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phy-reset-gpios = <&porta 26 0>;
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/* no hash filter and perfect filter support */
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snps,multicast-filter-bins = <0>;
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snps,perfect-filter-entries = <1>;
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snps,txpbl = <16>;
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snps,rxpbl = <16>;
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snps,aal;
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snps,axi-config = <&stmmac_axi_setup>;
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snps,mtl-rx-config = <&mtl_rx_setup>;
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snps,mtl-tx-config = <&mtl_tx_setup>;
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};
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#endif
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#if 1
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ethernet1: ethernet@04520000 {
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compatible = "cvitek,ethernet";
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reg = <0x0 0x04520000 0x0 0x10000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clock-names = "stmmaceth", "ptp_ref";
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clocks = <ð_csrclk>, <ð_ptpclk>;
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phy-reset-gpios = <&porta 26 0>;
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/* no hash filter and perfect filter support */
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snps,multicast-filter-bins = <0>;
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snps,perfect-filter-entries = <1>;
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snps,txpbl = <16>;
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snps,rxpbl = <16>;
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snps,aal;
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snps,axi-config = <&stmmac_axi_setup>;
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snps,mtl-rx-config = <&mtl_rx_setup>;
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snps,mtl-tx-config = <&mtl_tx_setup>;
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};
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#endif
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emmc:cv-emmc@4300000 {
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compatible = "cvitek,cv1835-fpga-emmc";
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reg = <0x0 0x4300000 0x0 0x1000>;
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reg-names = "core_mem";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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bus-width = <4>;
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non-removable;
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max-frequency = <12000000>;
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no-sdio;
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no-sd;
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};
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sd:cv-sd@4310000 {
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compatible = "cvitek,cv1835-fpga-sd";
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reg = <0x0 0x4310000 0x0 0x1000>;
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reg-names = "core_mem";
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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bus-width = <4>;
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max-frequency = <12000000>;
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no-sdio;
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no-mmc;
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};
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i2s_subsys {
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compatible = "cvitek,i2s_tdm_subsys";
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reg = <0x0 0x04108000 0x0 0x100>;
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master_base = <0x04120000>; /* I2S2 is master, only useful while using multi I2S IPs work on same IO */
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};
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mipi_rx: cif {
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compatible = "cvitek,cif";
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reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0300b000 0x0 0x1000>;
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reg-names = "csi_mac0", "csi_wrap0";
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "csi0";
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snsr-reset = <&portd 7 GPIO_ACTIVE_LOW>;
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resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
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<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
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reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
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};
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mipi_tx {
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compatible = "cvitek,mipi_tx";
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reg = <0x0 0x0a080000 0x0 0x10000>,<0x0 0x0300c000 0x0 0x100>;
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reg-names = "sc","dphy";
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};
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vip {
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compatible = "cvitek,vip";
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reg = <0x0 0x0a080000 0x0 0x10000>,<0x0 0x0a0a0000 0x0 0x2000>,
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<0x0 0x0a0c8000 0x0 0x20>,<0x0 0x0a000000 0x0 0x80000>,
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<0x0 0x0300c000 0x0 0x100>;
|
|
reg-names = "sc","dwa","vip_sys","isp","dphy";
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "sc","dwa","isp";
|
|
cvitek,cif-modules = <&mipi_rx>;
|
|
snsr-num = <1>;
|
|
};
|
|
|
|
vcodec {
|
|
compatible = "cvitek,vcodec";
|
|
memory-region = <&vcodec_reserved>;
|
|
reg = <0x0 0xb020000 0x0 0x10000>;
|
|
reg-names = "vcodec";
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vcodec";
|
|
};
|
|
|
|
jpu {
|
|
compatible = "cvitek,jpeg";
|
|
memory-region = <&jpu_reserved>;
|
|
reg = <0x0 0x0B000000 0x0 0x300>;
|
|
reg-names = "jpu";
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "jpu";
|
|
resets = <&rst RST_JPEG>;
|
|
reset-names = "jpeg";
|
|
};
|
|
|
|
i2s_mclk: i2s_mclk {
|
|
clock-output-names = "i2s_mclk";
|
|
clock-frequency = <24576000>; /* use internal audio PLL */
|
|
#clock-cells = <0x0>;
|
|
compatible = "fixed-clock";
|
|
};
|
|
|
|
#ifdef CV1835_AUDIO_CODEC_EN
|
|
adc: adc@0300A000 {
|
|
compatible = "cvitek,cv1835adc";
|
|
reg = <0x0 0x0300A000 0x0 0x100>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
};
|
|
|
|
dac: dac@0300A400 {
|
|
compatible = "cvitek,cv1835dac";
|
|
reg = <0x0 0x0300A400 0x0 0x100>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
};
|
|
|
|
sound_adc {
|
|
compatible = "cvitek,cv1835-adc";
|
|
cvi,model = "CV1835";
|
|
cvi,card_name = "cvi_adc";
|
|
};
|
|
|
|
sound_dac {
|
|
compatible = "cvitek,cv1835-dac";
|
|
cvi,model = "CV1835";
|
|
cvi,card_name = "cvi_dac";
|
|
};
|
|
#endif
|
|
|
|
|
|
i2s0: i2s@04100000 {
|
|
compatible = "cvitek,cv1835-i2s";
|
|
reg = <0x0 0x04100000 0x0 0x2000>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
dev-id = <0>;
|
|
#sound-dai-cells = <0>;
|
|
dmas = <&dmac 0 1 1 /* read channel */
|
|
&dmac 1 1 1>; /* write channel */
|
|
dma-names = "rx", "tx";
|
|
capability = "rx"; /* I2S0 connect to internal ADC as RX */
|
|
};
|
|
|
|
i2s1: i2s@04110000 {
|
|
compatible = "cvitek,cv1835-i2s";
|
|
reg = <0x0 0x04110000 0x0 0x2000>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
dev-id = <1>;
|
|
#sound-dai-cells = <0>;
|
|
dmas = <&dmac 2 1 1 /* read channel */
|
|
&dmac 3 1 1>; /* write channel */
|
|
dma-names = "rx", "tx";
|
|
#ifndef CV1835_CONCURRENT_I2S /* refer to /include/dt-bindings/sound/cv1835-audio.h */
|
|
capability = "txrx";
|
|
#else
|
|
capability = "tx";
|
|
#endif
|
|
};
|
|
|
|
#ifdef CV1835_EXT_CARD_1_EN
|
|
/* sound_ext1 use external codec */
|
|
sound_ext1 {
|
|
compatible = "cvitek,cv1835-adau1372";
|
|
cvi,model = "CV1835";
|
|
cvi,mode = "I2S";
|
|
cvi,fmt = "IBNF";
|
|
cvi,card_name = "cvi_sound_card_0";
|
|
cvi,slot_no=<2>;
|
|
dai@0 {
|
|
cvi,dai_name = "cv1835-i2s-1";
|
|
cvi,stream_name = "adau1372-aif";
|
|
cvi,cpu_dai_name = "4110000.i2s";
|
|
cvi,codec_dai_name = "adau1372-aif";
|
|
cvi,platform_name = "4110000.i2s";
|
|
cvi,codec_name = "adau1372.0-003c";
|
|
cvi,role = "master";
|
|
};
|
|
#ifdef CV1835_CONCURRENT_I2S
|
|
dai@1 {
|
|
cvi,dai_name = "cv1835-i2s-0";
|
|
cvi,stream_name = "adau1372-aif";
|
|
cvi,cpu_dai_name = "4100000.i2s";
|
|
cvi,codec_dai_name = "adau1372-aif";
|
|
cvi,platform_name = "4100000.i2s";
|
|
cvi,codec_name = "adau1372.0-003c";
|
|
cvi,role = "slave";
|
|
};
|
|
#endif
|
|
};
|
|
#endif
|
|
|
|
pdm: pdm@0x041D0C00 {
|
|
compatible = "cvitek,cv1835pdm";
|
|
reg = <0x0 0x041D0C00 0x0 0x100>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
};
|
|
|
|
#ifdef CV1835_PDM_EN
|
|
/* sound_PDM use PDM to transfer DMIC signal to I2S signal as audio input */
|
|
sound_PDM {
|
|
compatible = "cvitek,cv1835-pdm";
|
|
cvi,model = "CV1835";
|
|
cvi,card_name = "cv1835_internal_PDM";
|
|
};
|
|
#endif
|
|
|
|
i2s2: i2s@04120000 {
|
|
compatible = "cvitek,cv1835-i2s";
|
|
reg = <0x0 0x04120000 0x0 0x2000>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
dev-id = <2>;
|
|
#sound-dai-cells = <0>;
|
|
dmas = <&dmac 4 1 1 /* read channel */
|
|
&dmac 5 1 1>; /* write channel */
|
|
dma-names = "rx", "tx";
|
|
#ifndef CV1835_CONCURRENT_I2S
|
|
capability = "txrx";
|
|
#else
|
|
capability = "rx";
|
|
#endif
|
|
};
|
|
|
|
i2s3: i2s@04130000 {
|
|
compatible = "cvitek,cv1835-i2s";
|
|
reg = <0x0 0x04130000 0x0 0x2000>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&i2s_mclk 0>;
|
|
clock-names = "i2sclk";
|
|
dev-id = <3>;
|
|
#sound-dai-cells = <0>;
|
|
dmas = <&dmac 6 1 1 /* read channel */
|
|
&dmac 7 1 1>; /* write channel */
|
|
dma-names = "rx", "tx";
|
|
capability = "tx"; /* I2S3 connect to internal DAC as TX */
|
|
};
|
|
#ifdef CV1835_EXT_CARD_2_EN
|
|
/* sound_ext2 use external codec */
|
|
sound_ext2 {
|
|
compatible = "cvitek,cv1835-adau1372";
|
|
cvi,model = "CV1835";
|
|
cvi,mode = "I2S";
|
|
cvi,fmt = "IBNF";
|
|
cvi,card_name = "cv1835_external_card";
|
|
cvi,slot_no=<2>;
|
|
|
|
dai@0 {
|
|
cvi,dai_name = "cv1835-i2s-2";
|
|
cvi,stream_name = "adau1372-aif";
|
|
cvi,cpu_dai_name = "4120000.i2s";
|
|
cvi,codec_dai_name = "adau1372-aif";
|
|
cvi,platform_name = "4120000.i2s";
|
|
cvi,codec_name = "adau1372.0-003c";
|
|
cvi,role = "master";
|
|
};
|
|
#ifdef CV1835_CONCURRENT_I2S
|
|
dai@1 {
|
|
cvi,dai_name = "cv1835-i2s-3";
|
|
cvi,stream_name = "adau1372-aif";
|
|
cvi,cpu_dai_name = "4130000.i2s";
|
|
cvi,codec_dai_name = "adau1372-aif";
|
|
cvi,platform_name = "4130000.i2s";
|
|
cvi,codec_name = "adau1372.0-003c";
|
|
cvi,role = "slave";
|
|
};
|
|
#endif
|
|
};
|
|
#endif
|
|
otg0:cvi-usb-otg@040C0000 {
|
|
compatible = "cvitek,usb-otg";
|
|
reg = <0x0 0x040C0000 0x0 0x10000>,
|
|
<0x0 0x03000064 0x0 0x04>,//ddr_addr_mode
|
|
<0x0 0x03000038 0x0 0x08>,//USB Control and Status Register 0
|
|
<0x0 0x03000048 0x0 0x08>;//USB PHY Control and Status Register
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
|
|
clock-frequency = <25000000>;
|
|
//dr_mode = "peripheral";
|
|
dr_mode = "otg";
|
|
dis_ss = "true";
|
|
resets = <&rst RST_USB>;
|
|
reset-names = "usb";
|
|
//vbus-gpio = <&port0a 4 0>;
|
|
otg_bypass = "true";
|
|
status = "disabled"; // fpga not support
|
|
};
|
|
|
|
host0:cvi-usb-host@040D0000 {
|
|
compatible = "cvitek,xhci-platform";
|
|
reg = <0x0 0x040D0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
|
|
otg-controller = <&otg0>;
|
|
clock-frequency = <25000000>;
|
|
status = "disabled"; // fpga not support
|
|
};
|
|
|
|
usb0:cvi-usb-dev@040E0000 {
|
|
compatible = "cvitek,usb-dev";
|
|
reg = <0x0 0x040E0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <25000000>;
|
|
otg-controller = <&otg0>;
|
|
dma_mode = "new";
|
|
status = "disabled"; // fpga not support
|
|
};
|
|
|
|
memory {
|
|
reg = <0x1 0x00000000 0x0 0x40000000>;
|
|
device_type = "memory";
|
|
};
|
|
|
|
|
|
aliases {
|
|
serial0 = &uart0;
|
|
ethernet0 = ðernet0;
|
|
ethernet1 = ðernet1;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0"; // "serial0:115200n8", no arguments means no re-initialization
|
|
};
|
|
|
|
firmware {
|
|
optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
};
|
|
};
|
|
|
|
pmu_a53 {
|
|
compatible = "arm,cortex-a53-pmu";
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-affinity = <&A53_0>,
|
|
<&A53_1>;
|
|
};
|
|
|
|
};
|
|
|