151 lines
4.5 KiB
C
151 lines
4.5 KiB
C
/*
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* Based on arch/arm/include/asm/io.h
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*
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* Copyright (C) 1996-2000 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_IO_H
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#define __ASM_IO_H
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#include "asm/barrier.h"
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#include "xil_types.h"
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/*
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* Generic IO read/write. These perform native-endian accesses.
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*/
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#ifdef __CHECKER__
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#define __iomem __attribute__((noderef, address_space(2)))
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#else
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#define __iomem
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#endif
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
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{
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asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr));
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 val, volatile void __iomem *addr)
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{
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asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr));
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 val, volatile void __iomem *addr)
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{
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asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
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}
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
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{
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asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr));
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}
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 val;
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asm volatile("ldrb %w0, [%1]"
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: "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 val;
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asm volatile("ldrh %w0, [%1]"
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: "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 val;
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asm volatile("ldr %w0, [%1]"
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: "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readq __raw_readq
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 val;
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asm volatile("ldr %0, [%1]"
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: "=r" (val) : "r" (addr));
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return val;
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}
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/* IO barriers */
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#define mmiowb() do { } while (0)
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/* move from uapi/linux/byteorder/little_endian.h */
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#define cpu_to_le64(x) ((__force __le64)(__u64)(x))
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#define le64_to_cpu(x) ((__force __u64)(__le64)(x))
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#define cpu_to_le32(x) ((__force __le32)(__u32)(x))
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#define le32_to_cpu(x) ((__force __u32)(__le32)(x))
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#define cpu_to_le16(x) ((__force __le16)(__u16)(x))
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#define le16_to_cpu(x) ((__force __u16)(__le16)(x))
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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* accesses.
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*/
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#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
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#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
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#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c)))
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#define writew_relaxed(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
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#define writel_relaxed(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
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#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
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/*
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* I/O memory access primitives. Reads are ordered relative to any
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* following Normal memory access. Writes are ordered relative to any prior
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* Normal memory access.
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*/
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
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#define writeb(v, c) ({ __iowmb(); writeb_relaxed((v), (c)); })
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#define writew(v, c) ({ __iowmb(); writew_relaxed((v), (c)); })
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#define writel(v, c) ({ __iowmb(); writel_relaxed((v), (c)); })
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#define writeq(v, c) ({ __iowmb(); writeq_relaxed((v), (c)); })
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#define ioread8 readb
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#define ioread16 readw
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#define ioread32 readl
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#define ioread64 readq
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#define iowrite8 writeb
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#define iowrite16 writew
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#define iowrite32 writel
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#define iowrite64 writeq
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#endif /* __ASM_IO_H */
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