255 lines
9.9 KiB
C
255 lines
9.9 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xil_exception.h
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*
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* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
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* For exception related functions that can be used across all Xilinx supported
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* processors, please use xil_exception.h.
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*
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* @addtogroup arm_exception_apis ARM Processor Exception Handling
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* @{
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* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
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* utilized for enabling/disabling IRQ, registering/removing handler for
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* exceptions or initializing exception vector table with null handler.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- -------- -------- -----------------------------------------------
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* 5.2 pkp 28/05/15 First release
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* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
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* </pre>
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*
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******************************************************************************/
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#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
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#define XIL_EXCEPTION_H /* by using protection macros */
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/***************************** Include Files ********************************/
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#include "xil_types.h"
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#include "xpseudo_asm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/************************** Constant Definitions ****************************/
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#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
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#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
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#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
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#define XIL_EXCEPTION_ID_FIRST 0U
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#if defined(__aarch64__)
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#define XIL_EXCEPTION_ID_SYNC_INT 1U
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#define XIL_EXCEPTION_ID_IRQ_INT 2U
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#define XIL_EXCEPTION_ID_FIQ_INT 3U
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#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
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#define XIL_EXCEPTION_ID_LAST 5U
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#else
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#define XIL_EXCEPTION_ID_RESET 0U
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#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
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#define XIL_EXCEPTION_ID_SWI_INT 2U
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#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
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#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
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#define XIL_EXCEPTION_ID_IRQ_INT 5U
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#define XIL_EXCEPTION_ID_FIQ_INT 6U
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#define XIL_EXCEPTION_ID_LAST 6U
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#endif
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/*
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* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
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*/
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#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
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/**************************** Type Definitions ******************************/
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/**
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* This typedef is the exception handler function.
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*/
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typedef void (*Xil_ExceptionHandler)(void *data);
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typedef void (*Xil_InterruptHandler)(uint32_t irqn, void *data);
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/***************** Macros (Inline Functions) Definitions ********************/
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/****************************************************************************/
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/**
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* @brief Enable Exceptions.
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*
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* @param Mask: Value for enabling the exceptions.
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*
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* @return None.
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*
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* @note If bit is 0, exception is enabled.
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* C-Style signature: void Xil_ExceptionEnableMask(Mask)
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*
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******************************************************************************/
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#if defined(__GNUC__) || defined(__ICCARM__)
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#define Xil_ExceptionEnableMask(Mask) \
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mtcpsr(mfcpsr() & ~((Mask)&XIL_EXCEPTION_ALL))
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#else
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#define Xil_ExceptionEnableMask(Mask) \
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{ \
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register u32 Reg __asm("cpsr"); \
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mtcpsr((Reg) & (~((Mask)&XIL_EXCEPTION_ALL))); \
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}
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#endif
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/****************************************************************************/
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/**
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* @brief Enable the IRQ exception.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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#define Xil_ExceptionEnable() Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
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/****************************************************************************/
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/**
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* @brief Disable Exceptions.
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*
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* @param Mask: Value for disabling the exceptions.
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*
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* @return None.
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*
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* @note If bit is 1, exception is disabled.
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* C-Style signature: Xil_ExceptionDisableMask(Mask)
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*
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******************************************************************************/
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#if defined(__GNUC__) || defined(__ICCARM__)
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#define Xil_ExceptionDisableMask(Mask) \
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mtcpsr(mfcpsr() | ((Mask)&XIL_EXCEPTION_ALL))
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#else
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#define Xil_ExceptionDisableMask(Mask) \
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{ \
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register u32 Reg __asm("cpsr"); \
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mtcpsr((Reg) | ((Mask)&XIL_EXCEPTION_ALL)); \
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}
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#endif
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/****************************************************************************/
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/**
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* Disable the IRQ exception.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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#define Xil_ExceptionDisable() Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
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#if !defined(__aarch64__) && !defined(ARMA53_32)
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/****************************************************************************/
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/**
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* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
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* API is defined for cortex-a9 and cortex-r5.
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*
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* @return None.
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*
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* @note This macro is supposed to be used from interrupt handlers. In the
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* interrupt handler the interrupts are disabled by default (I and F
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* are 1). To allow nesting of interrupts, this macro should be
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* used. It clears the I and F bits by changing the ARM mode to
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* system mode. Once these bits are cleared and provided the
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* preemption of interrupt conditions are met in the GIC, nesting of
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* interrupts will start happening.
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* Caution: This macro must be used with caution. Before calling this
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* macro, the user must ensure that the source of the current IRQ
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* is appropriately cleared. Otherwise, as soon as we clear the I and
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* F bits, there can be an infinite loop of interrupts with an
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* eventual crash (all the stack space getting consumed).
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******************************************************************************/
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#define Xil_EnableNestedInterrupts() \
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__asm__ __volatile__("stmfd sp!, {lr}"); \
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__asm__ __volatile__("mrs lr, spsr"); \
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__asm__ __volatile__("stmfd sp!, {lr}"); \
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__asm__ __volatile__("msr cpsr_c, #0x1F"); \
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__asm__ __volatile__("stmfd sp!, {lr}");
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/****************************************************************************/
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/**
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* @brief Disable the nested interrupts by setting the I and F bits. This API
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* is defined for cortex-a9 and cortex-r5.
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*
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* @return None.
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*
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* @note This macro is meant to be called in the interrupt service routines.
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* This macro cannot be used independently. It can only be used when
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* nesting of interrupts have been enabled by using the macro
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* Xil_EnableNestedInterrupts(). In a typical flow, the user first
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* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
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* point. The user then must call this macro before exiting the interrupt
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* service routine. This macro puts the ARM back in IRQ/FIQ mode and
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* hence sets back the I and F bits.
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******************************************************************************/
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#define Xil_DisableNestedInterrupts() \
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__asm__ __volatile__("ldmfd sp!, {lr}"); \
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__asm__ __volatile__("msr cpsr_c, #0x92"); \
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__asm__ __volatile__("ldmfd sp!, {lr}"); \
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__asm__ __volatile__("msr spsr_cxsf, lr"); \
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__asm__ __volatile__("ldmfd sp!, {lr}");
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#endif
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/************************** Variable Definitions ****************************/
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/************************** Function Prototypes *****************************/
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extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
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Xil_ExceptionHandler Handler,
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void *Data);
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extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
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extern void Xil_ExceptionInit(void);
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#if defined(__aarch64__)
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void Xil_SyncAbortHandler(void *CallBackRef);
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void Xil_SErrorAbortHandler(void *CallBackRef);
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#else
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extern void Xil_DataAbortHandler(void *CallBackRef);
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extern void Xil_PrefetchAbortHandler(void *CallBackRef);
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extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
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#endif
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* XIL_EXCEPTION_H */
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/**
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* @} End of "addtogroup arm_exception_apis".
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*/
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