469 lines
17 KiB
C
469 lines
17 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xttcps.h
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* @addtogroup ttcps_v3_5
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* @{
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* @details
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*
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* This is the driver for one 16-bit timer counter in the Triple Timer Counter
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* (TTC) module in the Ps block.
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*
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* The TTC module provides three independent timer/counter modules that can each
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* be clocked using either the system clock (pclk) or an externally driven
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* clock (ext_clk). In addition, each counter can independently prescale its
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* selected clock input (divided by 2 to 65536). Counters can be set to
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* decrement or increment.
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*
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* Each of the counters can be programmed to generate interrupt pulses:
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* . At a regular, predefined period, that is on a timed interval
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* . When the counter registers overflow
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* . When the count matches any one of the three 'match' registers
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*
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* Therefore, up to six different events can trigger a timer interrupt: three
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* match interrupts, an overflow interrupt, an interval interrupt and an event
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* timer interrupt. Note that the overflow interrupt and the interval interrupt
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* are mutually exclusive.
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*
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* <b>Initialization & Configuration</b>
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*
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* An XTtcPs_Config structure is used to configure a driver instance.
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* Information in the XTtcPs_Config structure is the hardware properties
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* about the device.
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*
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* A driver instance is initialized through
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* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
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* is a pointer to the XTtcPs_Config structure, it can be looked up statically
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* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
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* EffectiveAddr can be the static base address of the device or virtual
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* mapped address if address translation is supported.
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*
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* <b>Interrupts</b>
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*
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* Interrupt handler is not provided by the driver, as handling of interrupt
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* is application specific.
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*
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* @note
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* The default setting for a timer/counter is:
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* - Overflow Mode
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* - Internal clock (pclk) selected
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* - Counter disabled
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* - All Interrupts disabled
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* - Output waveforms disabled
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- -----------------------------------------------------
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* 1.00a drg/jz 01/20/10 First release..
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* 2.0 adk 12/10/13 Updated as per the New Tcl API's
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* 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
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* modified for MISRA-C:2012 compliance.
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* 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
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* macros to return 32 bit values for zynq ultrascale+mpsoc
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* ms 01/23/17 Modified printf statement in main function for all
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* examples to ensure that "Successfully ran" and "Failed"
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* strings are available in all examples. This is a fix
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* for CR-965028.
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* ms 03/17/17 Added readme.txt file in examples folder for doxygen
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* generation.
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* 3.4 ms 04/18/17 Modified tcl file to add suffix U for all macros
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* definitions of ttcps in xparameters.h
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* 3.5 srm 10/06/17 Added new typedef XMatchRegValue for match register width
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XTTCPS_H /* prevent circular inclusions */
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#define XTTCPS_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xttcps_hw.h"
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#include "xstatus.h"
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/************************** Constant Definitions *****************************/
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/*
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* Maximum Value for interval counter
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*/
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#if defined(ARMA9)
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#define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
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#else
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#define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
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#endif
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/** @name Configuration options
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*
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* Options for the device. Each of the options is bit field, so more than one
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* options can be specified.
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*
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* @{
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*/
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#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
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#define XTTCPS_OPTION_CLK_EDGE_NEG \
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0x00000002U /**< Clock on trailing edge for
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external clock*/
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#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
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#define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
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#define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
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#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
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#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
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/*@}*/
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/**************************** Type Definitions *******************************/
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/**
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* This typedef contains configuration information for the device.
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*/
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typedef struct {
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u16 DeviceId; /**< Unique ID for device */
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u32 BaseAddress; /**< Base address for device */
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u32 InputClockHz; /**< Input clock frequency */
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} XTtcPs_Config;
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/**
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* The XTtcPs driver instance data. The user is required to allocate a
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* variable of this type for each PS timer/counter device in the system. A
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* pointer to a variable of this type is then passed to various driver API
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* functions.
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*/
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typedef struct {
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XTtcPs_Config Config; /**< Configuration structure */
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u32 IsReady; /**< Device is initialized and ready */
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} XTtcPs;
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/**
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* This typedef contains interval count and Match register value
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*/
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#if defined(ARMA9)
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typedef u16 XInterval;
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typedef u16 XMatchRegValue;
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#else
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typedef u32 XInterval;
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typedef u32 XMatchRegValue;
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#endif
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/***************** Macros (Inline Functions) Definitions *********************/
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/*
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* Internal helper macros
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*/
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#define InstReadReg(InstancePtr, RegOffset) \
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(Xil_In32((u32)((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
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#define InstWriteReg(InstancePtr, RegOffset, Data) \
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(Xil_Out32((u32)((InstancePtr)->Config.BaseAddress) + \
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(u32)(RegOffset), \
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(u32)(Data)))
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/*****************************************************************************/
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/**
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*
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* This function starts the counter/timer without resetting the counter value.
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*
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* @param InstancePtr is a pointer to the XTtcPs instance.
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*
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* @return None
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*
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* @note C-style signature:
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* void XTtcPs_Start(XTtcPs *InstancePtr)
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*
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****************************************************************************/
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#define XTtcPs_Start(InstancePtr) \
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InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
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(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
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~XTTCPS_CNT_CNTRL_DIS_MASK))
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/*****************************************************************************/
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/**
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*
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* This function stops the counter/timer. This macro may be called at any time
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* to stop the counter. The counter holds the last value until it is reset,
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* restarted or enabled.
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*
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* @param InstancePtr is a pointer to the XTtcPs instance.
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*
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* @return None
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*
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* @note C-style signature:
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* void XTtcPs_Stop(XTtcPs *InstancePtr)
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*
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****************************************************************************/
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#define XTtcPs_Stop(InstancePtr) \
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InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
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(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
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XTTCPS_CNT_CNTRL_DIS_MASK))
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/*****************************************************************************/
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/**
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*
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* This function checks whether the timer counter has already started.
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*
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* @param InstancePtr is a pointer to the XTtcPs instance
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*
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* @return Non-zero if the device has started, '0' otherwise.
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*
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* @note C-style signature:
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* int XTtcPs_IsStarted(XTtcPs *InstancePtr)
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*
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****************************************************************************/
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#define XTtcPs_IsStarted(InstancePtr) \
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((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
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XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
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/*****************************************************************************/
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/**
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*
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* This function returns the current 16-bit counter value. It may be called at
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* any time.
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*
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* @param InstancePtr is a pointer to the XTtcPs instance.
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*
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* @return zynq:16 bit counter value.
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* zynq ultrascale+mpsoc:32 bit counter value.
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*
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* @note C-style signature:
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* zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
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* zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
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*
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****************************************************************************/
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#if defined(ARMA9)
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/*
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* ttc supports 16 bit counter for zynq
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*/
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#define XTtcPs_GetCounterValue(InstancePtr) \
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(u16) InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
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#else
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/*
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* ttc supports 32 bit counter for zynq ultrascale+mpsoc
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*/
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#define XTtcPs_GetCounterValue(InstancePtr) \
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InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
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#endif
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/*****************************************************************************/
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/**
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*
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* This function sets the interval value to be used in interval mode.
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*
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* @param InstancePtr is a pointer to the XTtcPs instance.
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* @param Value is the 16-bit value to be set in the interval register.
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*
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* @return None
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*
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* @note C-style signature:
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* void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value)
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*
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****************************************************************************/
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#define XTtcPs_SetInterval(InstancePtr, Value) \
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InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
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/*****************************************************************************/
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/**
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*
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* This function gets the interval value from the interval register.
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*
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* @param InstancePtr is a pointer to the XTtcPs instance.
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*
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* @return zynq:16 bit interval value.
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* zynq ultrascale+mpsoc:32 bit interval value.
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*
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* @note C-style signature:
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* zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
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* zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
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*
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****************************************************************************/
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#if defined(ARMA9)
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/*
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* ttc supports 16 bit interval counter for zynq
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*/
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#define XTtcPs_GetInterval(InstancePtr) \
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(u16) InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
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#else
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/*
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* ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
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*/
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#define XTtcPs_GetInterval(InstancePtr) \
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InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
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#endif
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/*****************************************************************************/
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/**
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*
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* This macro resets the count register. It may be called at any time. The
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* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
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* the increment/decrement mode. The state of the counter, as started or
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* stopped, is not affected by calling reset.
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*
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* @param InstancePtr is a pointer to the XTtcPs instance.
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*
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* @return None
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*
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* @note C-style signature:
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* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
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*
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****************************************************************************/
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#define XTtcPs_ResetCounterValue(InstancePtr) \
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InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
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(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
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(u32)XTTCPS_CNT_CNTRL_RST_MASK))
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/*****************************************************************************/
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/**
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*
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* This function enables the interrupts.
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*
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* @param InstancePtr is a pointer to the XTtcPs instance.
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* @param InterruptMask defines which interrupt should be enabled.
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* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
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* This is a bit mask, all set bits will be enabled, cleared bits
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* will not be disabled.
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*
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* @return None.
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*
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* @note
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* C-style signature:
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* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
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*
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******************************************************************************/
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#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \
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InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
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(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \
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(InterruptMask)))
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/*****************************************************************************/
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/**
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*
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* This function disables the interrupts.
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*
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* @param InstancePtr is a pointer to the XTtcPs instance.
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* @param InterruptMask defines which interrupt should be disabled.
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* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
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* This is a bit mask, all set bits will be disabled, cleared bits
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* will not be disabled.
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*
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* @return None.
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*
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* @note
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* C-style signature:
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* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
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*
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******************************************************************************/
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#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
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InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
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(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \
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~(InterruptMask)))
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/*****************************************************************************/
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/**
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*
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* This function reads the interrupt status.
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*
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* @param InstancePtr is a pointer to the XTtcPs instance.
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*
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* @return None.
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*
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* @note C-style signature:
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* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
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*
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******************************************************************************/
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#define XTtcPs_GetInterruptStatus(InstancePtr) \
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InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
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/*****************************************************************************/
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/**
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*
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* This function clears the interrupt status.
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*
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* @param InstancePtr is a pointer to the XTtcPs instance.
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* @param InterruptMask defines which interrupt should be cleared.
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* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
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* This is a bit mask, all set bits will be cleared, cleared bits
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* will not be cleared.
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*
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* @return None.
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*
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* @note
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* C-style signature:
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* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
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*
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******************************************************************************/
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#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
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InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, (InterruptMask))
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/************************** Function Prototypes ******************************/
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/*
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* Initialization functions in xttcps_sinit.c
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*/
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XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
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/*
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* Required functions, in xttcps.c
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*/
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s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
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u32 EffectiveAddr);
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void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex,
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XMatchRegValue Value);
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XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
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void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
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u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
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void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
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XInterval *Interval, u8 *Prescaler);
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/*
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* Functions for options, in file xttcps_options.c
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*/
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s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
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u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
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/*
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* Function for self-test, in file xttcps_selftest.c
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*/
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s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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/** @} */
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