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ASoC: codecs: rk3528: fix pop sound when system suspend & resume

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Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I3bb10e31e38f01cc1938659f623fad6bb9acea3a
This commit is contained in:
Jason Zhu
2022-12-29 18:49:02 +08:00
parent 939428f876
commit 153d7168d7
2 changed files with 28 additions and 8 deletions
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19
sound/soc/codecs/rk3528_codec.c
View File

@ -111,8 +111,6 @@ static int rk3528_codec_power_off(struct rk3528_codec_priv *rk3528)
regmap_update_bits(rk3528->regmap, ACODEC_ANA01,
ACODEC_VREF_SEL_MASK, ACODEC_VREF_SEL(0xff));
/* vendor step 2 */
regmap_update_bits(rk3528->regmap, ACODEC_ANA01,
ACODEC_VREF_SEL_MASK, ACODEC_DAC_R_POP_CTRL_OFF);
/* vendor step 3 */
regmap_update_bits(rk3528->regmap, ACODEC_ANA00,
ACODEC_VREF_MASK, ACODEC_VREF_DIS);
@ -417,8 +415,6 @@ static int rk3528_codec_close_playback(struct rk3528_codec_priv *rk3528)
static int rk3528_codec_dlp_down(struct rk3528_codec_priv *rk3528)
{
rk3528_codec_power_off(rk3528);
return 0;
}
@ -610,6 +606,21 @@ static const struct snd_soc_component_driver soc_codec_dev_rk3528 = {
/* Set the default value or reset value */
static const struct reg_default rk3528_codec_reg_defaults[] = {
{ ACODEC_DIG00, 0x71 },
{ ACODEC_DIG03, 0x53 },
{ ACODEC_DIG07, 0x03 },
{ ACODEC_DIG08, 0xc3 },
{ ACODEC_DIG09, 0x28 },
{ ACODEC_DIG0A, 0x1 },
{ ACODEC_DIG0B, 0x80 },
{ ACODEC_DIG0D, 0xc3 },
{ ACODEC_DIG0E, 0xc3 },
{ ACODEC_DIG10, 0xf1 },
{ ACODEC_DIG11, 0xf1 },
{ ACODEC_ANA02, 0x77 },
{ ACODEC_ANA08, 0x20 },
{ ACODEC_ANA0A, 0x8 },
{ ACODEC_ANA0C, 0x20 },
{ ACODEC_ANA0E, 0x8 },
};
static bool rk3528_codec_volatile_reg(struct device *dev, unsigned int reg)

17
sound/soc/codecs/rk3528_codec.h
View File

@ -15,6 +15,15 @@
#define ACODEC_DIG04 0x10 /* REG 0x04 */
#define ACODEC_DIG05 0x14 /* REG 0x05 */
#define ACODEC_DIG06 0x18 /* REG 0x06 */
#define ACODEC_DIG07 0x1c /* REG 0x07 */
#define ACODEC_DIG08 0x20 /* REG 0x08 */
#define ACODEC_DIG09 0x24 /* REG 0x09 */
#define ACODEC_DIG0A 0x28 /* REG 0x0a */
#define ACODEC_DIG0B 0x2c /* REG 0x0b */
#define ACODEC_DIG0D 0x34 /* REG 0x0d */
#define ACODEC_DIG0E 0x38 /* REG 0x0e */
#define ACODEC_DIG10 0x40 /* REG 0x10 */
#define ACODEC_DIG11 0x44 /* REG 0x11 */
#define ACODEC_ANA00 0x80 /* REG 0x20 */
#define ACODEC_ANA01 0x84 /* REG 0x21 */
@ -133,8 +142,8 @@
/* ACODEC_ANA08 */
#define ACODEC_DAC_L_POP_CTRL_SHIFT 5
#define ACODEC_DAC_L_POP_CTRL_MASK (0x3 << ACODEC_DAC_L_POP_CTRL_SHIFT)
#define ACODEC_DAC_L_POP_CTRL_OFF (0x1 << ACODEC_DAC_L_POP_CTRL_SHIFT)
#define ACODEC_DAC_L_POP_CTRL_ON (0x2 << ACODEC_DAC_L_POP_CTRL_SHIFT)
#define ACODEC_DAC_L_POP_CTRL_ON (0x1 << ACODEC_DAC_L_POP_CTRL_SHIFT)
#define ACODEC_DAC_L_POP_CTRL_OFF (0x0 << ACODEC_DAC_L_POP_CTRL_SHIFT)
#define ACODEC_DAC_L_INIT_MASK (0x1 << 4)
#define ACODEC_DAC_L_WORK (0x1 << 4)
#define ACODEC_DAC_L_INIT (0x0 << 4)
@ -174,8 +183,8 @@
/* ACODEC_ANA0C */
#define ACODEC_DAC_R_POP_CTRL_SHIFT 5
#define ACODEC_DAC_R_POP_CTRL_MASK (0x3 << ACODEC_DAC_R_POP_CTRL_SHIFT)
#define ACODEC_DAC_R_POP_CTRL_OFF (0x1 << ACODEC_DAC_R_POP_CTRL_SHIFT)
#define ACODEC_DAC_R_POP_CTRL_ON (0x2 << ACODEC_DAC_R_POP_CTRL_SHIFT)
#define ACODEC_DAC_R_POP_CTRL_ON (0x1 << ACODEC_DAC_R_POP_CTRL_SHIFT)
#define ACODEC_DAC_R_POP_CTRL_OFF (0x0 << ACODEC_DAC_R_POP_CTRL_SHIFT)
#define ACODEC_DAC_R_INIT_MASK (0x1 << 4)
#define ACODEC_DAC_R_WORK (0x1 << 4)
#define ACODEC_DAC_R_INIT (0x0 << 4)