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arm64: dts: rockchip: rk3568j-core-ddr4-v10: add gamc0&gmac1 support

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Signed-off-by: Jianlong Wang <jianlong.wang@rock-chips.com>
Change-Id: Id5910a742ae9e7b99eb307db365081bce37423ad
This commit is contained in:
Jianlong Wang
2022-08-22 17:07:01 +08:00
committed by Tao Huang
parent 43d8d26778
commit 6dc85ffccf
1 changed files with 14 additions and 11 deletions
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25
arch/arm64/boot/dts/rockchip/rk3568j-core-ddr4-v10.dts
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@ -102,13 +102,13 @@
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default";
@ -123,25 +123,28 @@
status = "okay";
};
&gmac1 {
phy-mode = "rgmii";
clock_in_out = "output";
&gmac1_clkin {
clock-frequency = <50000000>;
};
snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
&gmac1 {
phy-mode = "rmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
assigned-clock-rates = <0>, <125000000>;
assigned-clock-parents = <&cru SCLK_GMAC1_RMII_SPEED>, <&gmac1_clkin>;
assigned-clock-rates = <0>, <50000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m0_miim
&gmac1m0_clkinout
&gmac1m0_tx_bus2
&gmac1m0_rx_bus2
&gmac1m0_rgmii_clk
&gmac1m0_rgmii_bus>;
&gmac1m0_rx_bus2>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
phy-handle = <&rgmii_phy1>;