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Merge tag 'linux-4.19-gen-rkr4' into stable-4.19-rk356x

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Linux 4.19 Gen release rkr4
This commit is contained in:
hejiawencc
2023-09-01 15:38:43 +08:00
parent ddf356c1c5 319a6c0cf0
commit f65c765612
904 changed files with 264753 additions and 52052 deletions
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107
Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml Normal file
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@ -0,0 +1,107 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip Clock Out Control Module Binding
maintainers:
- Sugar Zhang <sugar.zhang@rock-chips.com>
description: |
This add support switch for clk-bidirection which located
at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
and these config maybe located in many pieces of GRF,
which hard to addressed in one single clk driver. so, we add
this simple helper driver to address this situation.
In order to simplify implement and usage, and also for safety
clk usage (avoid high freq glitch), we set all clk out as disabled
(which means Input default for clk-bidrection) in the pre-stage,
such boot-loader or init by HW default. And then set a safety freq
before enable clk-out, such as "assign-clock-rates" or clk_set_rate
in drivers.
properties:
compatible:
enum:
- rockchip,clk-out
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
maxItems: 1
description: parent clocks.
power-domains:
maxItems: 1
clock-output-names:
maxItems: 1
rockchip,bit-shift:
$ref: /schemas/types.yaml#/definitions/uint32
description: Defines the bit shift of clk out enable.
rockchip,bit-set-to-disable:
type: boolean
description: |
By default this clock sets the bit at bit-shift to enable the clock.
Setting this property does the opposite: setting the bit disable
the clock and clearing it enables the clock.
required:
- compatible
- reg
- clocks
- "#clock-cells"
- clock-output-names
- rockchip,bit-shift
additionalProperties: false
examples:
# Clock Provider node:
- |
mclkin_sai0: mclkin-sai0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
clock-output-names = "mclk_sai0_from_io";
};
mclkout_sai0: mclkout-sai0@ff040070 {
compatible = "rockchip,clk-out";
reg = <0 0xff040070 0 0x4>;
clocks = <&cru MCLK_SAI0_OUT2IO>;
#clock-cells = <0>;
clock-output-names = "mclk_sai0_to_io";
rockchip,bit-shift = <4>;
};
# Clock mclkout Consumer node:
- |
ext_codec {
clocks = <&mclkout_sai0>;
clock-names = "mclk";
assigned-clocks = <&mclkout_sai0>;
assigned-clock-rates = <12288000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0m0_mclk>;
};
# Clock mclkin Consumer node:
- |
ext_codec {
clocks = <&mclkin_sai0>;
clock-names = "mclk";
assigned-clocks = <&cru CLK_SAI0>;
assigned-clock-parents = <&mclkin_sai0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0m0_mclk>;
};

1
Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
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@ -10,6 +10,7 @@ Required properties:
- "rockchip,rk3328-dfi" - for RK3328 SoCs. - "rockchip,rk3328-dfi" - for RK3328 SoCs.
- "rockchip,rk3368-dfi" - for RK3368 SoCs. - "rockchip,rk3368-dfi" - for RK3368 SoCs.
- "rockchip,rk3399-dfi" - for RK3399 SoCs. - "rockchip,rk3399-dfi" - for RK3399 SoCs.
- "rockchip,rk3528-dfi" - for RK3528 SoCs.
- "rockchip,rk3568-dfi" - for RK3568 SoCs. - "rockchip,rk3568-dfi" - for RK3568 SoCs.
- "rockchip,rv1126-dfi" - for RV1126 SoCs. - "rockchip,rv1126-dfi" - for RV1126 SoCs.

1
Documentation/devicetree/bindings/devfreq/rockchip_dmc.txt
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@ -11,6 +11,7 @@ Required properties:
- "rockchip,rk3328-dmc" - for RK3328 SoCs. - "rockchip,rk3328-dmc" - for RK3328 SoCs.
- "rockchip,rk3368-dmc" - for RK3368 SoCs. - "rockchip,rk3368-dmc" - for RK3368 SoCs.
- "rockchip,rk3399-dmc" - for RK3399 SoCs. - "rockchip,rk3399-dmc" - for RK3399 SoCs.
- "rockchip,rk3528-dmc" - for RK3528 SoCs.
- "rockchip,rk3568-dmc" - for RK3568 SoCs. - "rockchip,rk3568-dmc" - for RK3568 SoCs.
- "rockchip,rv1126-dmc" - for RV1126 SoCs. - "rockchip,rv1126-dmc" - for RV1126 SoCs.
- devfreq-events: Node to get DDR loading, Refer to - devfreq-events: Node to get DDR loading, Refer to

4
Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
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@ -17,6 +17,10 @@ Required properties:
- #mbox-cells: Common mailbox binding property to identify the number - #mbox-cells: Common mailbox binding property to identify the number
of cells required for the mailbox specifier. Should be 1 of cells required for the mailbox specifier. Should be 1
Optional properties :
- rockchip,txpoll-period-ms: TX Done polling interval in milliseconds.
Example: Example:
-------- --------

33
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
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@ -38,6 +38,12 @@ Optional Properties:
execute tuning when needed. If not specified, the host will do tuning execute tuning when needed. If not specified, the host will do tuning
for 360 times, namely tuning for each degree. for 360 times, namely tuning for each degree.
* pinctrl-names: should be "default" or "normal" combined with "idle". For
SDIO or eMMC devices, recommend to use "default". For SD/MMC cards, recommend
to use "normal" combined with "idle" to prevent power leak if vqmmc can't be
powered off. "normal" state is the same as "default" state, but "idle" state
should define the clk/cmd/data line to be pulled down or pulled none.
Example: Example:
rkdwmmc0@12200000 { rkdwmmc0@12200000 {
@ -47,3 +53,30 @@ Example:
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
}; };
/* "default" pinctrl */
&rkdwmmc0{
...
pinctrl-names = "default"
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
...
};
/* "normal" combined with "idle" pinctrl */
sdmmc_idle_gpios: sdmmc-idle-gpios {
rockchip,pins =
<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
&rkdwmmc0{
...
pinctrl-names = "normal", "idle";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc_idle_gpios &sdmmc0_det>;
...
}

2
Documentation/devicetree/bindings/net/can/rockchip_canfd.txt
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@ -4,6 +4,8 @@ Rockchip CANFD controller Device Tree Bindings
Required properties: Required properties:
- compatible : Should be: - compatible : Should be:
- "rockchip,canfd-1.0" for CANFD controllers 1.0 - "rockchip,canfd-1.0" for CANFD controllers 1.0
- "rockchip,can-2.0" for RK3588 CAN controllers 2.0
- "rockchip,rk3568-can-2.0" for RK3568 CAN controllers 2.0
- reg : Physical base address and size of the controller - reg : Physical base address and size of the controller
registers map. registers map.
- interrupts : Property with a value describing the interrupt - interrupts : Property with a value describing the interrupt

1
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
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@ -14,6 +14,7 @@ Required properties:
"rockchip,rk3366-gmac": found on RK3366 SoCs "rockchip,rk3366-gmac": found on RK3366 SoCs
"rockchip,rk3368-gmac": found on RK3368 SoCs "rockchip,rk3368-gmac": found on RK3368 SoCs
"rockchip,rk3399-gmac": found on RK3399 SoCs "rockchip,rk3399-gmac": found on RK3399 SoCs
"rockchip,rk3528-gmac": found on RK3528 SoCs
"rockchip,rk3568-gmac": found on RK3568 SoCs "rockchip,rk3568-gmac": found on RK3568 SoCs
"rockchip,rv1108-gmac": found on RV1108 SoCs "rockchip,rv1108-gmac": found on RV1108 SoCs
"rockchip,rv1126-gmac": found on RV1126 SoCs "rockchip,rv1126-gmac": found on RV1126 SoCs

3
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
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@ -10,6 +10,7 @@ Required properties (phy (parent) node):
* "rockchip,rk3366-usb2phy" * "rockchip,rk3366-usb2phy"
* "rockchip,rk3368-usb2phy" * "rockchip,rk3368-usb2phy"
* "rockchip,rk3399-usb2phy" * "rockchip,rk3399-usb2phy"
* "rockchip,rk3528-usb2phy"
* "rockchip,rk3568-usb2phy" * "rockchip,rk3568-usb2phy"
* "rockchip,rv1108-usb2phy" * "rockchip,rv1108-usb2phy"
- reg : the address offset of grf for usb-phy configuration. - reg : the address offset of grf for usb-phy configuration.
@ -64,6 +65,7 @@ Optional properties:
is always powered on. is always powered on.
- rockchip,low-power-mode: when set, the port will enter low power - rockchip,low-power-mode: when set, the port will enter low power
state when suspend. state when suspend.
- rockchip,dis-u2-susphy: when set, disable otg suspend phy.
Example: Example:
@ -102,6 +104,7 @@ Required properties (usb2phy grf node):
"rockchip,rk1808-usb2phy-grf", "syscon", "simple-mfd"; "rockchip,rk1808-usb2phy-grf", "syscon", "simple-mfd";
"rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
"rockchip,rk3328-usb2phy-grf", "syscon", "simple-mfd"; "rockchip,rk3328-usb2phy-grf", "syscon", "simple-mfd";
"rockchip,rk3528-grf", "syscon", "simple-mfd";
"rockchip,rk3568-usb2phy-grf", "syscon"; "rockchip,rk3568-usb2phy-grf", "syscon";
- reg : the address offset of grf for usb-phy configuration. - reg : the address offset of grf for usb-phy configuration.
- #address-cells : should be 1. - #address-cells : should be 1.

1
Documentation/devicetree/bindings/rng/rockchip,rng.txt
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@ -5,6 +5,7 @@ Required properties:
- compatible : should be one of the following. - compatible : should be one of the following.
"rockchip,cryptov1-rng" for crypto v1 "rockchip,cryptov1-rng" for crypto v1
"rockchip,cryptov2-rng" for crypto v2 "rockchip,cryptov2-rng" for crypto v2
"rockchip,trngv1" for independent trng, such as rk3588.
- reg : Specifies base physical address and size of the registers map. - reg : Specifies base physical address and size of the registers map.
- clocks : Phandle to clock-controller plus clock-specifier pair. - clocks : Phandle to clock-controller plus clock-specifier pair.
- clock-names : "clk_crypto", "clk_crypto_apk", "aclk_crypto", "hclk_crypto" as a clock name. - clock-names : "clk_crypto", "clk_crypto_apk", "aclk_crypto", "hclk_crypto" as a clock name.

46
Documentation/devicetree/bindings/rpmsg/rpmsg-rockchip.txt Normal file
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@ -0,0 +1,46 @@
* Rockchip RPMsg Platform Driver
The Rockchip RPMsg Platform Driver is used for Remote Processors Messaging.
Required Properties:
- compatible: should be one of the following.
"rockchip,rk3568-rpmsg" for rk3568 SoCs.
- mbox-names: mailbox name for "rpmsg-rx" or "rpmsg-tx".
- mboxes: mailbox channel for rpmsg.
- rockchip,vdev-nums: number of rpmsg instance.
- rockchip,link-id: link_id of rpmsg instance. 4bit for master cpu_id and 4bit
for remote cpu_id.
Optional Properties:
Example:
rpmsg: rpmsg {
compatible = "rockchip,rk3568-rpmsg";
mbox-names = "rpmsg-rx", "rpmsg-tx";
mboxes = <&mailbox 0 &mailbox 3>;
rockchip,vdev-nums = <1>;
rockchip,link-id = <0x03>;
reg = <0x0 0x7c00000 0x0 0x20000>;
memory-region = <&rpmsg_dma_reserved>;
status = "okay";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
rpmsg_reserved: rpmsg@7c00000 {
reg = <0x0 0x7c00000 0x0 0x400000>;
no-map;
};
rpmsg_dma_reserved: rpmsg-dma@8000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x8000000 0x0 0x100000>;
no-map;
};
};

18
Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt
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@ -9,6 +9,7 @@ Required properties:
- "rockchip,pm-rk3328" - for RK3328 SOCs. - "rockchip,pm-rk3328" - for RK3328 SOCs.
- "rockchip,pm-rk3368" - for RK3368 SoCs. - "rockchip,pm-rk3368" - for RK3368 SoCs.
- "rockchip,pm-rk3399" - for RK3399 SoCs. - "rockchip,pm-rk3399" - for RK3399 SoCs.
- "rockchip,pm-rk3528" - for RK3528 SoCs.
- "rockchip,pm-rv1126" - for RV1126 SoCs. - "rockchip,pm-rv1126" - for RV1126 SoCs.
- rockchip,sleep-mode-config : the sleep mode config, - rockchip,sleep-mode-config : the sleep mode config,
@ -164,6 +165,23 @@ Example:
>; >;
}; };
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-rk3528";
status = "disabled";
rockchip,sleep-debug-en = <0>;
rockchip,sleep-mode-config = <
(0
| RKPM_SLP_ARMPD
)
>;
rockchip,wakeup-config = <
(0
| RKPM_CPU0_WKUP_EN
| RKPM_GPIO_WKUP_EN
)
>;
};
rockchip_suspend: rockchip_suspend { rockchip_suspend: rockchip_suspend {
compatible = "rockchip,pm-rk3568"; compatible = "rockchip,pm-rk3568";
status = "okay"; status = "okay";

5
Documentation/devicetree/bindings/spi/spi-rockchip.txt
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@ -35,6 +35,11 @@ Optional Properties:
- rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling - rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling
Rx data (may need to be fine tuned for high capacitance lines). Rx data (may need to be fine tuned for high capacitance lines).
No delay (0) by default. No delay (0) by default.
- csm: ss_n be high for half or one sclk_out cycle after every frame data is
transferred:
- "0" for keep low;
- "1" for half sclk_out;
- "2" for one sclk_out.
- pinctrl-names: Names for the pin configuration(s); may be "default" or - pinctrl-names: Names for the pin configuration(s); may be "default" or
"sleep", where the "sleep" configuration may describe the state "sleep", where the "sleep" configuration may describe the state
the pins should be in during system suspend. See also the pins should be in during system suspend. See also

2
Documentation/devicetree/bindings/usb/usb-xhci.txt
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@ -42,6 +42,8 @@ Optional properties:
- xhci-trb-ent-quirk: set if this xhci platform need to enable the Evaluate - xhci-trb-ent-quirk: set if this xhci platform need to enable the Evaluate
Next TRB(ENT) flag in the TRB data structure to force xHC to pre-fetch Next TRB(ENT) flag in the TRB data structure to force xHC to pre-fetch
the next TRB of a TD. the next TRB of a TD.
- quirk-skip-phy-init: indicate that do not manage the PHY state in the HCD core
and handle this in the controller's driver.
- imod-interval-ns: default interrupt moderation interval is 5000ns - imod-interval-ns: default interrupt moderation interval is 5000ns
- phys : see usb-hcd.txt in the current directory - phys : see usb-hcd.txt in the current directory

6
MAINTAINERS
View File

@ -9773,6 +9773,12 @@ F: Documentation/media/v4l-drivers/meye*
F: drivers/media/pci/meye/ F: drivers/media/pci/meye/
F: include/uapi/linux/meye.h F: include/uapi/linux/meye.h
MOTORCOMM PHY DRIVER
M: Peter Geis <pgwipeout@gmail.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/phy/motorcomm.c
MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD
M: Jiri Slaby <jirislaby@gmail.com> M: Jiri Slaby <jirislaby@gmail.com>
S: Maintained S: Maintained

1
arch/arm/Makefile
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@ -158,6 +158,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
textofs-$(CONFIG_ARCH_MESON) := 0x00208000 textofs-$(CONFIG_ARCH_MESON) := 0x00208000
textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
textofs-$(CONFIG_CPU_RK3308) := 0x00058000 textofs-$(CONFIG_CPU_RK3308) := 0x00058000
textofs-$(CONFIG_CPU_RK3528) := 0x00208000
textofs-$(CONFIG_CPU_PX30) := 0x00208000 textofs-$(CONFIG_CPU_PX30) := 0x00208000
ifeq ($(CONFIG_ROCKCHIP_THUNDER_BOOT),y) ifeq ($(CONFIG_ROCKCHIP_THUNDER_BOOT),y)
textofs-$(CONFIG_CPU_RV1126) := 0x00608000 textofs-$(CONFIG_CPU_RV1126) := 0x00608000

6
arch/arm/boot/dts/Makefile
View File

@ -930,7 +930,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3326-evb-lp3-v10.dtb \ rk3326-evb-lp3-v10.dtb \
rk3326-863-lp3-v10.dtb \ rk3326-863-lp3-v10.dtb \
rk3326-evb-lp3-v10-avb.dtb \ rk3326-evb-lp3-v10-avb.dtb \
rk3326-863-lp3-v10-avb.dtb rk3326-863-lp3-v10-avb.dtb \
rk3528-evb1-ddr4-v10.dtb \
rk3528-evb2-ddr3-v10.dtb \
rk3528-evb3-lp4x-v10.dtb \
rk3528-evb4-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += \ dtb-$(CONFIG_ARCH_S3C24XX) += \
s3c2416-smdk2416.dtb s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += \ dtb-$(CONFIG_ARCH_S3C64XX) += \

24
arch/arm/boot/dts/rk3036.dtsi
View File

@ -742,35 +742,31 @@
bias-pull-pin-default; bias-pull-pin-default;
}; };
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_none: pcfg-pull-none { pcfg_pull_none: pcfg-pull-none {
bias-disable; bias-disable;
}; };
pwm0 { pwm0 {
pwm0_pin: pwm0-pin { pwm0_pin: pwm0-pin {
rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; rockchip,pins = <0 RK_PA0 2 &pcfg_pull_default>;
}; };
}; };
pwm1 { pwm1 {
pwm1_pin: pwm1-pin { pwm1_pin: pwm1-pin {
rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>;
}; };
}; };
pwm2 { pwm2 {
pwm2_pin: pwm2-pin { pwm2_pin: pwm2-pin {
rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>;
}; };
}; };
pwm3 { pwm3 {
pwm3_pin: pwm3-pin { pwm3_pin: pwm3-pin {
rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; rockchip,pins = <0 RK_PD3 1 &pcfg_pull_default>;
}; };
}; };
@ -906,8 +902,8 @@
uart0 { uart0 {
uart0_xfer: uart0-xfer { uart0_xfer: uart0-xfer {
rockchip,pins = <0 RK_PC0 1 &pcfg_pull_up>, rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
<0 RK_PC1 1 &pcfg_pull_up>; <0 RK_PC1 1 &pcfg_pull_default>;
}; };
uart0_cts: uart0-cts { uart0_cts: uart0-cts {
@ -921,16 +917,16 @@
uart1 { uart1 {
uart1_xfer: uart1-xfer { uart1_xfer: uart1-xfer {
rockchip,pins = <2 RK_PC6 1 &pcfg_pull_up>, rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
<2 RK_PC7 1 &pcfg_pull_up>; <2 RK_PC7 1 &pcfg_pull_default>;
}; };
/* no rts / cts for uart1 */ /* no rts / cts for uart1 */
}; };
uart2 { uart2 {
uart2_xfer: uart2-xfer { uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
<1 RK_PC3 2 &pcfg_pull_up>; <1 RK_PC3 2 &pcfg_pull_default>;
}; };
/* no rts / cts for uart2 */ /* no rts / cts for uart2 */
}; };

20
arch/arm/boot/dts/rk3066a.dtsi
View File

@ -465,10 +465,6 @@
bias-pull-pin-default; bias-pull-pin-default;
}; };
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_none: pcfg_pull_none { pcfg_pull_none: pcfg_pull_none {
bias-disable; bias-disable;
}; };
@ -609,8 +605,8 @@
uart0 { uart0 {
uart0_xfer: uart0-xfer { uart0_xfer: uart0-xfer {
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
<1 RK_PA1 1 &pcfg_pull_up>; <1 RK_PA1 1 &pcfg_pull_default>;
}; };
uart0_cts: uart0-cts { uart0_cts: uart0-cts {
@ -624,8 +620,8 @@
uart1 { uart1 {
uart1_xfer: uart1-xfer { uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
<1 RK_PA5 1 &pcfg_pull_up>; <1 RK_PA5 1 &pcfg_pull_default>;
}; };
uart1_cts: uart1-cts { uart1_cts: uart1-cts {
@ -639,16 +635,16 @@
uart2 { uart2 {
uart2_xfer: uart2-xfer { uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
<1 RK_PB1 1 &pcfg_pull_up>; <1 RK_PB1 1 &pcfg_pull_default>;
}; };
/* no rts / cts for uart2 */ /* no rts / cts for uart2 */
}; };
uart3 { uart3 {
uart3_xfer: uart3-xfer { uart3_xfer: uart3-xfer {
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_up>, rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
<3 RK_PD4 1 &pcfg_pull_up>; <3 RK_PD4 1 &pcfg_pull_default>;
}; };
uart3_cts: uart3-cts { uart3_cts: uart3-cts {

16
arch/arm/boot/dts/rk312x.dtsi
View File

@ -1292,10 +1292,6 @@
bias-pull-pin-default; bias-pull-pin-default;
}; };
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_output_high: pcfg-output-high { pcfg_output_high: pcfg-output-high {
output-high; output-high;
}; };
@ -1420,8 +1416,8 @@
uart0 { uart0 {
uart0_xfer: uart0-xfer { uart0_xfer: uart0-xfer {
rockchip,pins = <2 RK_PD2 2 &pcfg_pull_up>, rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
<2 RK_PD3 2 &pcfg_pull_up>; <2 RK_PD3 2 &pcfg_pull_none>;
}; };
uart0_cts: uart0-cts { uart0_cts: uart0-cts {
@ -1435,8 +1431,8 @@
uart1 { uart1 {
uart1_xfer: uart1-xfer { uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PB1 2 &pcfg_pull_up>, rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
<1 RK_PB2 2 &pcfg_pull_up>; <1 RK_PB2 2 &pcfg_pull_default>;
}; };
uart1_cts: uart1-cts { uart1_cts: uart1-cts {
@ -1450,8 +1446,8 @@
uart2 { uart2 {
uart2_xfer: uart2-xfer { uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
<1 RK_PC3 2 &pcfg_pull_up>; <1 RK_PC3 2 &pcfg_pull_none>;
}; };
uart2_cts: uart2-cts { uart2_cts: uart2-cts {

1
arch/arm/boot/dts/rk322x.dtsi
View File

@ -1032,6 +1032,7 @@
reg-io-width = <4>; reg-io-width = <4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hdmi", "hdmi_wakeup";
clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>,
<&cru SCLK_HDMI_CEC>; <&cru SCLK_HDMI_CEC>;
clock-names = "isfr", "iahb", "cec"; clock-names = "isfr", "iahb", "cec";

9
arch/arm/boot/dts/rk3288.dtsi
View File

@ -1390,7 +1390,8 @@
vopb: vop@ff930000 { vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop-big"; compatible = "rockchip,rk3288-vop-big";
reg = <0x0 0xff930000 0x0 0x19c>; reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
reg-names = "regs", "gamma_lut";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@ -1451,7 +1452,8 @@
vopl: vop@ff940000 { vopl: vop@ff940000 {
compatible = "rockchip,rk3288-vop-lit"; compatible = "rockchip,rk3288-vop-lit";
reg = <0x0 0xff940000 0x0 0x19c>; reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
reg-names = "regs", "gamma_lut";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@ -1647,7 +1649,8 @@
reg-io-width = <4>; reg-io-width = <4>;
#sound-dai-cells = <0>; #sound-dai-cells = <0>;
rockchip,grf = <&grf>; rockchip,grf = <&grf>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hdmi", "hdmi_wakeup";
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
clock-names = "iahb", "isfr", "cec"; clock-names = "iahb", "isfr", "cec";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";

12
arch/arm/boot/dts/rk3528-evb1-ddr4-v10.dts Normal file
View File

@ -0,0 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "arm64/rockchip/rk3528-evb1-ddr4-v10.dts"
/ {
model = "Rockchip RK3528 EVB1 DDR4 V10 Board (AArch32)";
compatible = "rockchip,rk3528-evb1-ddr4-v10", "rockchip,rk3528";
};

12
arch/arm/boot/dts/rk3528-evb2-ddr3-v10.dts Normal file
View File

@ -0,0 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "arm64/rockchip/rk3528-evb2-ddr3-v10.dts"
/{
model = "Rockchip RK3528 EVB2 DDR3 V10 Board (AArch32)";
compatible = "rockchip,rk3528-evb2-ddr3-v10", "rockchip,rk3528";
};

12
arch/arm/boot/dts/rk3528-evb3-lp4x-v10.dts Normal file
View File

@ -0,0 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "arm64/rockchip/rk3528-evb3-lp4x-v10.dts"
/{
model = "Rockchip RK3528 EVB3 LP4X V10 Board (AArch32)";
compatible = "rockchip,rk3528-evb3-lp4x-v10", "rockchip,rk3528";
};

12
arch/arm/boot/dts/rk3528-evb4-ddr4-v10.dts Normal file
View File

@ -0,0 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "arm64/rockchip/rk3528-evb1-ddr4-v10.dts"
/{
model = "Rockchip RK3528 EVB4 DDR4 V10 Board (AArch32)";
compatible = "rockchip,rk3528-evb4-ddr4-v10", "rockchip,rk3528";
};

11
arch/arm/boot/dts/rv1126-pinctrl.dtsi
View File

@ -1214,6 +1214,17 @@
/* sdmmc0_pwr */ /* sdmmc0_pwr */
<0 RK_PC0 1 &pcfg_pull_none>; <0 RK_PC0 1 &pcfg_pull_none>;
}; };
/omit-if-no-ref/
sdmmc0_idle_pins: sdmmc0-idle-pins {
rockchip,pins =
<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>,
<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>,
<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>,
<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>,
<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
};
}; };
spi0 { spi0 {
/omit-if-no-ref/ /omit-if-no-ref/

7
arch/arm/boot/dts/rv1126-thunder-boot-emmc.dtsi
View File

@ -19,6 +19,8 @@
thunder_boot_mmc: thunder-boot-mmc { thunder_boot_mmc: thunder-boot-mmc {
compatible = "rockchip,thunder-boot-mmc"; compatible = "rockchip,thunder-boot-mmc";
reg = <0xffc50000 0x4000>; reg = <0xffc50000 0x4000>;
clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>;
clock-names = "biu", "ciu";
memory-region-src = <&ramdisk_c>; memory-region-src = <&ramdisk_c>;
memory-region-dst = <&ramdisk_r>; memory-region-dst = <&ramdisk_r>;
memory-region-idmac = <&mmc_idmac>; memory-region-idmac = <&mmc_idmac>;
@ -26,6 +28,11 @@
}; };
&emmc { &emmc {
/delete-property/ power-domains;
memory-region-ecsd = <&mmc_ecsd>; memory-region-ecsd = <&mmc_ecsd>;
post-power-on-delay-ms = <0>; post-power-on-delay-ms = <0>;
}; };
&power {
/delete-node/ pd_nvm@RV1126_PD_NVM;
};

6
arch/arm/boot/dts/rv1126.dtsi
View File

@ -2125,7 +2125,7 @@
iommus = <&rkvdec_mmu>; iommus = <&rkvdec_mmu>;
rockchip,srv = <&mpp_srv>; rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <0>; rockchip,taskqueue-node = <0>;
rockchip,resetgroup-node = <0>; rockchip,resetgroup-node = <1>;
status = "disabled"; status = "disabled";
}; };
@ -2364,8 +2364,9 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>; fifo-depth = <0x100>;
max-frequency = <200000000>; max-frequency = <200000000>;
pinctrl-names = "default"; pinctrl-names = "normal", "idle";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
status = "disabled"; status = "disabled";
}; };
@ -2539,6 +2540,7 @@
snps,tx-ipgap-linecheck-dis-quirk; snps,tx-ipgap-linecheck-dis-quirk;
snps,tx-fifo-resize; snps,tx-fifo-resize;
snps,xhci-trb-ent-quirk; snps,xhci-trb-ent-quirk;
snps,usb2-lpm-disable;
status = "disabled"; status = "disabled";
}; };
}; };

4
arch/arm/configs/rockchip_defconfig
View File

@ -302,6 +302,7 @@ CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_SYNOPSYS is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_MOTORCOMM_PHY=y
CONFIG_ROCKCHIP_PHY=y CONFIG_ROCKCHIP_PHY=y
CONFIG_PPP=y CONFIG_PPP=y
CONFIG_PPP_BSDCOMP=y CONFIG_PPP_BSDCOMP=y
@ -513,8 +514,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set # CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_PWM=y
CONFIG_ROCKCHIP_RGA=y CONFIG_ROCKCHIP_MULTI_RGA=y
CONFIG_ROCKCHIP_RGA2=y
CONFIG_IEP=y CONFIG_IEP=y
CONFIG_ROCKCHIP_MPP_SERVICE=y CONFIG_ROCKCHIP_MPP_SERVICE=y
CONFIG_ROCKCHIP_MPP_RKVDEC=y CONFIG_ROCKCHIP_MPP_RKVDEC=y

3
arch/arm/configs/rockchip_linux_defconfig
View File

@ -173,12 +173,12 @@ CONFIG_MD=y
CONFIG_BLK_DEV_DM=y CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y CONFIG_DM_CRYPT=y
CONFIG_DM_THIN_PROVISIONING=y CONFIG_DM_THIN_PROVISIONING=y
CONFIG_DM_VERITY=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_TUN=y CONFIG_TUN=y
CONFIG_VETH=y CONFIG_VETH=y
CONFIG_EMAC_ROCKCHIP=y CONFIG_EMAC_ROCKCHIP=y
CONFIG_STMMAC_ETH=y CONFIG_STMMAC_ETH=y
CONFIG_MOTORCOMM_PHY=y
CONFIG_ROCKCHIP_PHY=y CONFIG_ROCKCHIP_PHY=y
CONFIG_PPP=y CONFIG_PPP=y
CONFIG_PPP_ASYNC=y CONFIG_PPP_ASYNC=y
@ -348,6 +348,7 @@ CONFIG_SND_SEQ_DUMMY=y
CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_AUDIO=y
CONFIG_SND_SOC=y CONFIG_SND_SOC=y
CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_SAI=y
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
CONFIG_SND_SOC_ROCKCHIP_MAX98090=y CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
CONFIG_SND_SOC_ROCKCHIP_RT5645=y CONFIG_SND_SOC_ROCKCHIP_RT5645=y

2
arch/arm/configs/rv1126-snapshot.config
View File

@ -17,7 +17,7 @@ CONFIG_BATTERY_CW2015=y
# CONFIG_PM_DEBUG is not set # CONFIG_PM_DEBUG is not set
# CONFIG_PM_DEVFREQ_EVENT is not set # CONFIG_PM_DEVFREQ_EVENT is not set
# CONFIG_PPS is not set # CONFIG_PPS is not set
CONFIG_PSTORE_MCU_LOG=y CONFIG_PSTORE_BOOT_LOG=y
# CONFIG_PTP_1588_CLOCK is not set # CONFIG_PTP_1588_CLOCK is not set
# CONFIG_PWRSEQ_EMMC is not set # CONFIG_PWRSEQ_EMMC is not set
# CONFIG_PWRSEQ_SIMPLE is not set # CONFIG_PWRSEQ_SIMPLE is not set

2
arch/arm/configs/rv1126-trailcamera.config
View File

@ -19,7 +19,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_PM_DEBUG is not set # CONFIG_PM_DEBUG is not set
# CONFIG_PM_DEVFREQ_EVENT is not set # CONFIG_PM_DEVFREQ_EVENT is not set
# CONFIG_PPS is not set # CONFIG_PPS is not set
CONFIG_PSTORE_MCU_LOG=y CONFIG_PSTORE_BOOT_LOG=y
# CONFIG_PTP_1588_CLOCK is not set # CONFIG_PTP_1588_CLOCK is not set
# CONFIG_PWRSEQ_EMMC is not set # CONFIG_PWRSEQ_EMMC is not set
# CONFIG_PWRSEQ_SIMPLE is not set # CONFIG_PWRSEQ_SIMPLE is not set

266
arch/arm64/boot/dts/rockchip/Makefile
View File

@ -1,142 +1,138 @@
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ad-d6-anx6345.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ad-r35-mb-rk618-dual-lvds.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ad-r35-mb-rk618-hdmi.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ad-r35-mb-rk618-hdmi-lvds.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ad-r35-mb-rk618-lvds.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-lvds-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-robot-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-robot-no-gpu-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v11.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v11-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v11-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr4-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr4-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ext-rk618.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ext-rk618-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-z7-a0-rk618-dsi.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-ai-va-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-ai-va-v11.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-ai-va-v11-i2s-dmic.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-ai-va-v12.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10-robot-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10-robot-no-gpu-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v11.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v11-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v12-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-863-lp3-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-863-lp3-v10-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-863-lp3-v10-rkisp1.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-86v-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-box-liantong.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-box-liantong-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb-android.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb-android-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64-android.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64-android-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358-evb-ddr3-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358m-vehicle-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-808-evb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-tablet.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368a-817-tablet.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368a-817-tablet-bnd.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-ind-lpddr4-android.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-ind-lpddr4-android-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-ind-lpddr4-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-ind-lpddr4-v13-android-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator-edp-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator-lp4-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-tve1030g-avb.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-evb-lp4-v11-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-evb-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-evb-v11-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-evb-v14-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo1-lp4-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb2-ddr3-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb3-lp4x-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb4-ddr4-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-iotest-lp3-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10-android9.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb-mipitest-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10-lvds.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-edp.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-eink.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-i2s-mic-array.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-pdm-mic-array.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb3-ddr3-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb3-ddr3-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb5-lp4x-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink-w6.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink-w103.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-android9.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-dual-camera.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux-amp.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux-spi-nor.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10-bt1120-to-hdmi.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb4-lp3-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb5-ddr4-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb7-ddr4-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux-spi-nand.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux-spi-nand.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568j-core-ddr4-v10.dtb
# dtb-$(CONFIG_ARCH_ROCKCHIP) += rk630-rk3568-ddr3-v10.dtb
ifeq ($(CONFIG_ARCH_ROCKCHIP), y) ifeq ($(CONFIG_ARCH_ROCKCHIP), y)
dtb-$(CONFIG_CPU_PX30) += \
px30-ad-d6-anx6345.dtb \
px30-ad-r35-mb-rk618-dual-lvds.dtb \
px30-ad-r35-mb-rk618-hdmi.dtb \
px30-ad-r35-mb-rk618-hdmi-lvds.dtb \
px30-ad-r35-mb-rk618-lvds.dtb \
px30-evb-ddr3-lvds-v10.dtb \
px30-evb-ddr3-v10.dtb \
px30-evb-ddr3-v10-avb.dtb \
px30-evb-ddr3-v10-linux.dtb \
px30-evb-ddr3-v10-robot-linux.dtb \
px30-evb-ddr3-v10-robot-no-gpu-linux.dtb \
px30-evb-ddr3-v11.dtb \
px30-evb-ddr3-v11-avb.dtb \
px30-evb-ddr3-v11-linux.dtb \
px30-evb-ddr4-v10.dtb \
px30-evb-ext-rk618.dtb \
px30-evb-ext-rk618-avb.dtb \
px30-z7-a0-rk618-dsi.dtb \
dtb-$(CONFIG_CPU_RK3326) += \
rk3326-evb-ai-va-v10.dtb \
rk3326-evb-ai-va-v11.dtb \
rk3326-evb-ai-va-v11-i2s-dmic.dtb \
rk3326-evb-ai-va-v12.dtb \
rk3326-evb-lp3-v10.dtb \
rk3326-evb-lp3-v10-avb.dtb \
rk3326-evb-lp3-v10-linux.dtb \
rk3326-evb-lp3-v10-robot-linux.dtb \
rk3326-evb-lp3-v10-robot-no-gpu-linux.dtb \
rk3326-evb-lp3-v11.dtb \
rk3326-evb-lp3-v11-avb.dtb \
rk3326-863-lp3-v10.dtb \
rk3326-863-lp3-v10-avb.dtb \
rk3326-863-lp3-v10-rkisp1.dtb \
rk3326-86v-v10.dtb \
dtb-$(CONFIG_CPU_RK3328) += \
rk3328-box-liantong.dtb \
rk3328-box-liantong-avb.dtb \
rk3328-evb.dtb \
rk3328-evb-android.dtb \
rk3328-evb-android-avb.dtb \
rk3328-rock64.dtb \
rk3328-rock64-android.dtb \
rk3328-rock64-android-avb.dtb \
rk3328-roc-cc.dtb \
dtb-$(CONFIG_CPU_RK3358) += \
rk3358-evb-ddr3-v10-linux.dtb \
dtb-$(CONFIG_CPU_RK3368) += \
rk3368-808-evb.dtb \
rk3368-evb-act8846.dtb \
rk3368-geekbox.dtb \
rk3368-lion-haikou.dtb \
rk3368-orion-r68-meta.dtb \
rk3368-px5-evb.dtb \
rk3368-r88.dtb \
rk3368-tablet.dtb \
rk3368a-817-tablet.dtb \
rk3368a-817-tablet-bnd.dtb \
dtb-$(CONFIG_CPU_RK3399) += \
rk3399-evb.dtb \
rk3399-evb-ind-lpddr4-android.dtb \
rk3399-evb-ind-lpddr4-android-avb.dtb \
rk3399-evb-ind-lpddr4-linux.dtb \
rk3399-evb-ind-lpddr4-v13-android-avb.dtb \
rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-puma-haikou.dtb \
rk3399-sapphire.dtb \
rk3399-sapphire-excavator.dtb \
rk3399-sapphire-excavator-edp-avb.dtb \
rk3399-sapphire-excavator-linux.dtb \
rk3399-sapphire-excavator-lp4-linux.dtb \
rk3399-tve1030g-avb.dtb \
rk3399pro-evb-lp4-v11-linux.dtb \
rk3399pro-evb-v10-linux.dtb \
rk3399pro-evb-v11-linux.dtb \
rk3399pro-evb-v14-linux.dtb
# dtb-$(CONFIG_CPU_RK3568) += \
# rk3566-box-demo-v10.dtb \
# rk3566-evb-mipitest-v10.dtb \
# rk3566-evb1-ddr4-v10.dtb \
# rk3566-evb1-ddr4-v10-linux.dtb \
# rk3566-evb1-ddr4-v10-lvds.dtb \
# rk3566-evb2-lp4x-v10.dtb \
# rk3566-evb2-lp4x-v10-edp.dtb \
# rk3566-evb2-lp4x-v10-eink.dtb \
# rk3566-evb2-lp4x-v10-i2s-mic-array.dtb \
# rk3566-evb2-lp4x-v10-linux.dtb \
# rk3566-evb2-lp4x-v10-pdm-mic-array.dtb \
# rk3566-evb3-ddr3-v10.dtb \
# rk3566-evb3-ddr3-v10-linux.dtb \
# rk3566-evb5-lp4x-v10.dtb \
# rk3566-rk817-eink.dtb \
# rk3566-rk817-eink-w6.dtb \
# rk3566-rk817-eink-w103.dtb \
# rk3566-rk817-tablet.dtb \
# rk3566-rk817-tablet-k108.dtb \
# rk3566-rk817-tablet-rkg11.dtb \
# rk3566-rk817-tablet-v10.dtb \
# rk3568-evb1-ddr4-v10.dtb \
# rk3568-evb1-ddr4-v10-linux.dtb \
# rk3568-evb1-ddr4-v10-linux-spi-nor.dtb \
# rk3568-evb2-lp4x-v10.dtb \
# rk3568-evb2-lp4x-v10-bt1120-to-hdmi.dtb \
# rk3568-evb4-lp3-v10.dtb \
# rk3568-evb5-ddr4-v10.dtb \
# rk3568-evb6-ddr3-v10.dtb \
# rk3568-evb6-ddr3-v10-linux.dtb \
# rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dtb \
# rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dtb \
# rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dtb \
# rk3568-evb7-ddr4-v10.dtb \
# rk3568-iotest-ddr3-v10.dtb \
# rk3568-iotest-ddr3-v10-linux.dtb \
# rk3568-nvr-demo-v10.dtb \
# rk3568-nvr-demo-v10-linux.dtb \
# rk3568-nvr-demo-v10-linux-spi-nand.dtb \
# rk3568-nvr-demo-v12-linux.dtb \
# rk3568-nvr-demo-v12-linux-spi-nand.dtb \
# rk3566-lubancat1-n.dtb \
# rk3568-lubancat2.dtb \
# rk3568-lubancat2-io.dtb \
# rk3568-lubancat2-io-mipi.dtb \
# rk3568-lubancat2@_saradc_ch3=288.dtb \
# rk3568-lubancat2-io@_saradc_ch3=407.dtb \
# rk3568-lubancat2-io-mipi@_saradc_ch3=1024.dtb
# endif
dtb-$(CONFIG_CPU_RK3568) += \ dtb-$(CONFIG_CPU_RK3568) += \
rk3566-lubancat-0.dtb \ rk3566-lubancat-0.dtb \
rk3566-lubancat-1.dtb \ rk3566-lubancat-1.dtb \

43
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dtsi
View File

@ -99,33 +99,26 @@
status = "okay"; status = "okay";
}; };
rk809-sound { rk809_sound: rk809-sound {
compatible = "simple-audio-card"; status = "okay";
simple-audio-card,format = "i2s"; compatible = "rockchip,multicodecs-card";
simple-audio-card,name = "rockchip,rk809-codec"; rockchip,card-name = "rockchip-rk809";
simple-audio-card,mclk-fs = <256>; hp-det-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
simple-audio-card,widgets = io-channels = <&saradc 1>;
"Microphone", "Mic Jack", io-channel-names = "adc-detect";
"Headphone", "Headphone Jack"; keyup-threshold-microvolt = <1800000>;
simple-audio-card,routing = poll-interval = <100>;
"Mic Jack", "MICBIAS1", rockchip,format = "i2s";
"IN1P", "Mic Jack", rockchip,mclk-fs = <256>;
"Headphone Jack", "HPOL", rockchip,cpu = <&i2s1_2ch>;
"Headphone Jack", "HPOR"; rockchip,codec = <&rk809_codec>;
simple-audio-card,cpu {
sound-dai = <&i2s1_2ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809_codec>;
};
};
rk_headset: rk-headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&hp_det>; pinctrl-0 = <&hp_det>;
io-channels = <&saradc 1>; play-pause-key {
label = "playpause";
linux,code = <KEY_PLAYPAUSE>;
press-threshold-microvolt = <2000>;
};
}; };
sdio_pwrseq: sdio-pwrseq { sdio_pwrseq: sdio-pwrseq {

13
arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10-linux.dts Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include "px30-evb-ddr3-v10-linux.dts"
#include "px30-ddr4p416dd6-timing.dtsi"
/ {
model = "Rockchip linux PX30 evb ddr4 board";
compatible = "rockchip,px30-evb-ddr4-v10-linux", "rockchip,px30";
};

12
arch/arm64/boot/dts/rockchip/px30.dtsi
View File

@ -982,6 +982,7 @@
pwm0: pwm@ff200000 { pwm0: pwm@ff200000 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200000 0x0 0x10>; reg = <0x0 0xff200000 0x0 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>; #pwm-cells = <3>;
pinctrl-names = "active"; pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>; pinctrl-0 = <&pwm0_pin>;
@ -993,6 +994,7 @@
pwm1: pwm@ff200010 { pwm1: pwm@ff200010 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200010 0x0 0x10>; reg = <0x0 0xff200010 0x0 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>; #pwm-cells = <3>;
pinctrl-names = "active"; pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>; pinctrl-0 = <&pwm1_pin>;
@ -1004,6 +1006,7 @@
pwm2: pwm@ff200020 { pwm2: pwm@ff200020 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200020 0x0 0x10>; reg = <0x0 0xff200020 0x0 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>; #pwm-cells = <3>;
pinctrl-names = "active"; pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>; pinctrl-0 = <&pwm2_pin>;
@ -1015,6 +1018,8 @@
pwm3: pwm@ff200030 { pwm3: pwm@ff200030 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200030 0x0 0x10>; reg = <0x0 0xff200030 0x0 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>; #pwm-cells = <3>;
pinctrl-names = "active"; pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>; pinctrl-0 = <&pwm3_pin>;
@ -1026,6 +1031,7 @@
pwm4: pwm@ff208000 { pwm4: pwm@ff208000 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208000 0x0 0x10>; reg = <0x0 0xff208000 0x0 0x10>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>; #pwm-cells = <3>;
pinctrl-names = "active"; pinctrl-names = "active";
pinctrl-0 = <&pwm4_pin>; pinctrl-0 = <&pwm4_pin>;
@ -1037,6 +1043,7 @@
pwm5: pwm@ff208010 { pwm5: pwm@ff208010 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208010 0x0 0x10>; reg = <0x0 0xff208010 0x0 0x10>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>; #pwm-cells = <3>;
pinctrl-names = "active"; pinctrl-names = "active";
pinctrl-0 = <&pwm5_pin>; pinctrl-0 = <&pwm5_pin>;
@ -1048,6 +1055,7 @@
pwm6: pwm@ff208020 { pwm6: pwm@ff208020 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208020 0x0 0x10>; reg = <0x0 0xff208020 0x0 0x10>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>; #pwm-cells = <3>;
pinctrl-names = "active"; pinctrl-names = "active";
pinctrl-0 = <&pwm6_pin>; pinctrl-0 = <&pwm6_pin>;
@ -1059,6 +1067,8 @@
pwm7: pwm@ff208030 { pwm7: pwm@ff208030 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208030 0x0 0x10>; reg = <0x0 0xff208030 0x0 0x10>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>; #pwm-cells = <3>;
pinctrl-names = "active"; pinctrl-names = "active";
pinctrl-0 = <&pwm7_pin>; pinctrl-0 = <&pwm7_pin>;
@ -1720,6 +1730,7 @@
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>; power-domains = <&power PX30_PD_VO>;
#iommu-cells = <0>; #iommu-cells = <0>;
rockchip,disable-device-link-resume;
status = "disabled"; status = "disabled";
}; };
@ -1766,6 +1777,7 @@
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>; power-domains = <&power PX30_PD_VO>;
#iommu-cells = <0>; #iommu-cells = <0>;
rockchip,disable-device-link-resume;
status = "disabled"; status = "disabled";
}; };

10
arch/arm64/boot/dts/rockchip/px30s-dram-default-timing.dtsi
View File

@ -310,12 +310,12 @@
dram_dll_dis_freq = <IGNORE_THIS>; dram_dll_dis_freq = <IGNORE_THIS>;
phy_dll_dis_freq = <IGNORE_THIS>; phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */ /* drv when odt on */
phy_dq_drv_odten = <35>; phy_dq_drv_odten = <44>;
phy_ca_drv_odten = <38>; phy_ca_drv_odten = <38>;
phy_clk_drv_odten = <47>; phy_clk_drv_odten = <47>;
dram_dq_drv_odten = <40>; dram_dq_drv_odten = <40>;
/* drv when odt off */ /* drv when odt off */
phy_dq_drv_odtoff = <35>; phy_dq_drv_odtoff = <44>;
phy_ca_drv_odtoff = <38>; phy_ca_drv_odtoff = <38>;
phy_clk_drv_odtoff = <47>; phy_clk_drv_odtoff = <47>;
dram_dq_drv_odtoff = <40>; dram_dq_drv_odtoff = <40>;
@ -328,11 +328,11 @@
dram_dq_odt_en_freq = <800>; dram_dq_odt_en_freq = <800>;
phy_odt_en_freq = <800>; phy_odt_en_freq = <800>;
/* slew rate when odt enable */ /* slew rate when odt enable */
phy_dq_sr_odten = <0x0>; phy_dq_sr_odten = <0x7>;
phy_ca_sr_odten = <0x1>; phy_ca_sr_odten = <0x1>;
phy_clk_sr_odten = <0x1>; phy_clk_sr_odten = <0x1>;
/* slew rate when odt disable */ /* slew rate when odt disable */
phy_dq_sr_odtoff = <0x0>; phy_dq_sr_odtoff = <0x7>;
phy_ca_sr_odtoff = <0x1>; phy_ca_sr_odtoff = <0x1>;
phy_clk_sr_odtoff = <0x1>; phy_clk_sr_odtoff = <0x1>;
/* ssmod setting*/ /* ssmod setting*/
@ -371,7 +371,7 @@
lp4_dq_vref_odten = <276>; lp4_dq_vref_odten = <276>;
lp4_ca_vref_odten = <380>; lp4_ca_vref_odten = <380>;
/* lp4 vref info when odt disable */ /* lp4 vref info when odt disable */
phy_lp4_dq_vref_odtoff = <340>; phy_lp4_dq_vref_odtoff = <420>;
lp4_dq_vref_odtoff = <420>; lp4_dq_vref_odtoff = <420>;
lp4_ca_vref_odtoff = <420>; lp4_ca_vref_odtoff = <420>;
}; };

397
arch/arm64/boot/dts/rockchip/rk-stb-ir-keymap.dtsi Normal file
View File

@ -0,0 +1,397 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/input/rk-ir.h>
&pwm3 {
ir_key1 {
rockchip,usercode = <0xff00>;
rockchip,key_table =
<0xf9 KEY_HOME>,
<0xbf KEY_BACK>,
<0xfb KEY_MENU>,
<0xaa KEY_REPLY>,
<0xb9 KEY_UP>,
<0xe9 KEY_DOWN>,
<0xb8 KEY_LEFT>,
<0xea KEY_RIGHT>,
<0xeb KEY_VOLUMEDOWN>,
<0xef KEY_VOLUMEUP>,
<0xf7 KEY_MUTE>,
<0xe7 KEY_POWER>,
<0xfc KEY_POWER>,
<0xa9 KEY_VOLUMEDOWN>,
<0xa8 KEY_PLAYPAUSE>,
<0xe0 KEY_VOLUMEDOWN>,
<0xa5 KEY_VOLUMEDOWN>,
<0xab 183>,
<0xb7 388>,
<0xe8 388>,
<0xf8 184>,
<0xaf 185>,
<0xed KEY_VOLUMEDOWN>,
<0xee 186>,
<0xb3 KEY_VOLUMEDOWN>,
<0xf1 KEY_VOLUMEDOWN>,
<0xf2 KEY_VOLUMEDOWN>,
<0xf3 KEY_SEARCH>,
<0xb4 KEY_VOLUMEDOWN>,
<0xa4 KEY_SETUP>,
<0xbe KEY_SEARCH>;
};
/*for IPTV ltjc*/
ir_key2 {
rockchip,usercode = <0xc43b>;
rockchip,key_table =
<0x7e KEY_REPLY>,
<0x7f KEY_BACK>,
<0x7a KEY_UP>,
<0x78 KEY_DOWN>,
<0x7b KEY_LEFT>,
<0x79 KEY_RIGHT>,
<0x66 KEY_VOLUMEUP>,
<0x65 KEY_VOLUMEDOWN>,
<0x69 KEY_POWER>,
<0x64 KEY_MUTE>,
<0x76 KEY_1>,
<0x75 KEY_2>,
<0x74 KEY_3>,
<0x73 KEY_4>,
<0x72 KEY_5>,
<0x71 KEY_6>,
<0x70 KEY_7>,
<0x6f KEY_8>,
<0x6e KEY_9>,
<0x77 KEY_0>,
<0x7c KEY_PAGEDOWN>,
<0x7d KEY_PAGEUP>,
<0x6a KEY_SETUP>,
<0x68 KEY_CHANNEL_UP>,
<0x67 KEY_CHANNEL_DN>,
<0x39 KEY_PORTAL>,
<0x29 KEY_HOME_PAGE>,
<0x33 KEY_CH_CUT_BACK>,
<0x34 KEY_LOCAL>,
<0x2d KEY_REVIEW>,
<0x2c KEY_ON_DEMAND>,
<0x2b KEY_INFO1>,
<0x2e KEY_DIRECT_SEEDING>,
<0x2d KEY_REVIEW>,
<0x2c KEY_ON_DEMAND>,
<0x2b KEY_INFO1>,
<0x63 KEY_SOUND1>,
<0x6c KEY_X1>,
<0x6d KEY_X2>,
<0x62 KEY_PLAYPAUSE>,
<0x6b KEY_EQUAL>,
<0x61 KEY_FASTFORWARD>,
<0x60 KEY_REWIND>,
<0x3b KEY_STOP>,
<0x35 KEY_BLUE>,
<0x36 KEY_YELLOW>,
<0x37 KEY_GREEN>,
<0x38 KEY_RED>,
<0x00 KEY_AUTOPAIR>;
};
ir_key3 {
rockchip,usercode = <0x1dcc>;
rockchip,key_table =
<0xee KEY_REPLY>,
<0xf0 KEY_BACK>,
<0xf8 KEY_UP>,
<0xbb KEY_DOWN>,
<0xef KEY_LEFT>,
<0xed KEY_RIGHT>,
<0xfc KEY_HOME>,
<0xf1 KEY_VOLUMEUP>,
<0xfd KEY_VOLUMEDOWN>,
<0xb7 KEY_SEARCH>,
<0xff KEY_POWER>,
<0xf3 KEY_MUTE>,
<0xbf KEY_MENU>,
<0xf9 0x191>,
<0xf5 0x192>,
<0xb3 388>,
<0xbe KEY_1>,
<0xba KEY_2>,
<0xb2 KEY_3>,
<0xbd KEY_4>,
<0xf9 KEY_5>,
<0xb1 KEY_6>,
<0xfc KEY_7>,
<0xf8 KEY_8>,
<0xb0 KEY_9>,
<0xb6 KEY_0>,
<0xb5 KEY_BACKSPACE>;
};
/* for IPTV */
ir_key4 {
rockchip,usercode = <0x4db2>;
rockchip,key_table =
<0x31 KEY_REPLY>,
<0x3a KEY_BACK>,
<0x35 KEY_UP>,
<0x2d KEY_DOWN>,
<0x66 KEY_LEFT>,
<0x3e KEY_RIGHT>,
<0x7f KEY_VOLUMEUP>,
<0xfe KEY_VOLUMEDOWN>,
<0x23 KEY_POWER>,
<0x63 KEY_MUTE>,
<0x6d KEY_1>,
<0x6c KEY_2>,
<0x33 KEY_3>,
<0x71 KEY_4>,
<0x70 KEY_5>,
<0x37 KEY_6>,
<0x75 KEY_7>,
<0x74 KEY_8>,
<0x3b KEY_9>,
<0x78 KEY_0>,
<0x73 KEY_PAGEDOWN>,
<0x22 KEY_PAGEUP>,
<0x72 KEY_SETUP>,
<0x7a KEY_CHANNEL_UP>,
<0x79 KEY_CHANNEL_DN>,
<0x77 KEY_HOME_PAGE>,
<0x29 KEY_CH_CUT_BACK>,
<0x32 KEY_DIRECT_SEEDING>,
<0x6e KEY_REVIEW>,
<0x7c KEY_ON_DEMAND>,
<0x3c KEY_INFO1>,
<0x67 KEY_SOUND1>,
<0x25 KEY_X1>,
<0x2f KEY_X2>,
<0x7d KEY_LOCAL>,
<0x6a KEY_PLAYPAUSE>,
<0x0b KEY_EQUAL>;
};
/* for CMCC */
ir_key5 {
rockchip,usercode = <0x1608>;
rockchip,key_table =
<0x4c KEY_REPLY>,
<0x4d KEY_BACK>,
<0x4b KEY_UP>,
<0x4a KEY_DOWN>,
<0x49 KEY_LEFT>,
<0x48 KEY_RIGHT>,
<0x4e KEY_HOME>,
<0x0b KEY_VOLUMEUP>,
<0x0c KEY_VOLUMEDOWN>,
<0x23 KEY_POWER>,
<0x45 KEY_MUTE>,
<0x44 KEY_MENU>,
<0x78 KEY_1>,
<0x77 KEY_2>,
<0x76 KEY_3>,
<0x75 KEY_4>,
<0x74 KEY_5>,
<0x73 KEY_6>,
<0x72 KEY_7>,
<0x71 KEY_8>,
<0x70 KEY_9>,
<0x79 KEY_0>,
<0x43 KEY_EQUAL>,
<0x72 KEY_X1>,
<0x5f KEY_SETUP>,
<0x25 KEY_DIRECT_SEEDING>,
<0x24 KEY_REVIEW>,
<0x21 KEY_ON_DEMAND>,
<0x20 KEY_INFO1>;
};
/* rk new remote */
ir_key6 {
rockchip,usercode = <0xfe01>;
rockchip,key_table =
<0xec KEY_REPLY>,
<0xe6 KEY_BACK>,
<0xe9 KEY_UP>,
<0xe5 KEY_DOWN>,
<0xae KEY_LEFT>,
<0xaf KEY_RIGHT>,
<0xee KEY_HOME>,
<0xe7 KEY_VOLUMEUP>,
<0xef KEY_VOLUMEDOWN>,
<0xbf KEY_POWER>,
<0xbe KEY_MUTE>,
<0xb3 KEY_MENU>,
<0xff 388>,
<0xb1 KEY_1>,
<0xf2 KEY_2>,
<0xf3 KEY_3>,
<0xb5 KEY_4>,
<0xf6 KEY_5>,
<0xf7 KEY_6>,
<0xb9 KEY_7>,
<0xfa KEY_8>,
<0xfb KEY_9>,
<0xfe KEY_0>,
<0xbd KEY_EQUAL>,
<0xbc KEY_SETUP>,
<0xf0 KEY_LOCAL>,
<0x0d KEY_DIRECT_SEEDING>,
<0x0c KEY_REVIEW>,
<0x0b KEY_ON_DEMAND>,
<0x0a KEY_INFO1>,
<0x0e KEY_CH_CUT_BACK>;
};
/* for CTC */
ir_key7 {
rockchip,usercode = <0x4cb3>;
rockchip,key_table =
<0x31 KEY_REPLY>,
<0x3a KEY_BACK>,
<0x35 KEY_UP>,
<0x2d KEY_DOWN>,
<0x66 KEY_LEFT>,
<0x3e KEY_RIGHT>,
<0x7f KEY_VOLUMEUP>,
<0x7e KEY_VOLUMEDOWN>,
<0x23 KEY_POWER>,
<0x63 KEY_MUTE>,
<0x6d KEY_1>,
<0x6c KEY_2>,
<0x33 KEY_3>,
<0x71 KEY_4>,
<0x70 KEY_5>,
<0x37 KEY_6>,
<0x75 KEY_7>,
<0x74 KEY_8>,
<0x3b KEY_9>,
<0x78 KEY_0>,
<0x73 KEY_PAGEDOWN>,
<0x22 KEY_PAGEUP>,
<0x72 KEY_SETUP>,
<0x7a KEY_CHANNEL_UP>,
<0x79 KEY_CHANNEL_DN>,
<0x77 KEY_MENU>,
<0x29 KEY_CH_CUT_BACK>,
<0x32 KEY_DIRECT_SEEDING>,
<0x6e KEY_REVIEW>,
<0x7c KEY_ON_DEMAND>,
<0x3c KEY_AUTOPAIR>,
<0x67 KEY_SOUND1>,
<0x25 KEY_X1>,
<0x2f KEY_X2>,
<0x7d KEY_HOME_PAGE>,
<0x6a KEY_PLAYPAUSE>,
<0x0b KEY_EQUAL>,
<0x1a KEY_F12>,
<0xbc KEY_F22>;
};
/* for CMCC */
ir_key8 {
rockchip,usercode = <0xdd22>;
rockchip,key_table =
<0x31 KEY_REPLY>,
<0x6a KEY_BACK>,
<0x35 KEY_UP>,
<0x2d KEY_DOWN>,
<0x66 KEY_LEFT>,
<0x3e KEY_RIGHT>,
<0x7f KEY_VOLUMEUP>,
<0x7e KEY_VOLUMEDOWN>,
<0x23 KEY_POWER>,
<0x63 KEY_MUTE>,
<0x6d KEY_1>,
<0x6c KEY_2>,
<0x33 KEY_3>,
<0x71 KEY_4>,
<0x70 KEY_5>,
<0x37 KEY_6>,
<0x75 KEY_7>,
<0x74 KEY_8>,
<0x3b KEY_9>,
<0x78 KEY_0>,
<0x73 KEY_PAGEDOWN>,
<0x22 KEY_PAGEUP>,
<0x72 KEY_SETUP>,
<0x7a KEY_CHANNEL_UP>,
<0x79 KEY_CHANNEL_DN>,
<0x77 KEY_HOME_PAGE>,
<0x2f KEY_CH_CUT_BACK>,
<0x32 KEY_DIRECT_SEEDING>,
<0x6e KEY_REVIEW>,
<0x7c KEY_ON_DEMAND>,
<0x3c KEY_INFO1>,
<0x3a KEY_HELP>,
<0x67 KEY_SOUND1>,
<0x25 KEY_X2>,
<0x7d KEY_MENU>,
<0x3f KEY_EQUAL>,
<0x29 388>,
<0x26 KEY_PLAYPAUSE>,
<0x76 401>,
<0x7b 400>,
<0x69 66>;
};
/* for BJLT IPTV */
ir_key9 {
rockchip,usercode = <0x3bc4>;
rockchip,key_table =
<0x81 KEY_REPLY>,
<0x80 KEY_BACK>,
<0x85 KEY_UP>,
<0x87 KEY_DOWN>,
<0x84 KEY_LEFT>,
<0x86 KEY_RIGHT>,
<0x99 KEY_VOLUMEUP>,
<0x9a KEY_VOLUMEDOWN>,
<0x96 KEY_POWER>,
<0x9b KEY_MUTE>,
<0x89 KEY_1>,
<0x8a KEY_2>,
<0x8b KEY_3>,
<0x8c KEY_4>,
<0x8d KEY_5>,
<0x8e KEY_6>,
<0x8f KEY_7>,
<0x90 KEY_8>,
<0x91 KEY_9>,
<0x88 KEY_0>,
<0x83 KEY_PAGEDOWN>,
<0x82 KEY_PAGEUP>,
<0x95 KEY_SETUP>,
<0x97 KEY_CHANNEL_UP>,
<0x98 KEY_CHANNEL_DN>,
<0xc6 KEY_LOCAL>,
<0xd6 KEY_HOME_PAGE>,
<0xd7 KEY_TRACK>,
<0xcc KEY_CH_CUT_BACK>,
<0xc3 KEY_INTERX>,
<0xd1 KEY_DIRECT_SEEDING>,
<0xd2 KEY_REVIEW>,
<0xd3 KEY_ON_DEMAND>,
<0xd4 KEY_INFO1>,
<0xc7 KEY_DIRECT_SEEDING>,
<0xc8 KEY_REVIEW>,
<0xc9 KEY_ON_DEMAND>,
<0xca KEY_INFO1>,
<0xcd KEY_FAVORITE>,
<0xce KEY_CHANNEL_POS>,
<0xcf KEY_HELP>,
<0xd0 KEY_EVENT>,
<0x9c KEY_SOUND1>,
<0x93 KEY_X1>,
<0x92 KEY_X2>,
<0xc0 KEY_END>,
<0xc1 KEY_GO_BEGINNING>,
<0x9d KEY_PLAYPAUSE>,
<0xc4 KEY_STOP>,
<0x94 KEY_EQUAL>,
<0x9e KEY_YELLOW>,
<0x9f KEY_BLUE>,
<0xcb KEY_APPLICATION>,
<0xc5 KEY_POS>;
};
};

6
arch/arm64/boot/dts/rockchip/rk3326-linux.dtsi
View File

@ -43,6 +43,12 @@
/ { / {
compatible = "rockchip,linux", "rockchip,rk3326"; compatible = "rockchip,linux", "rockchip,rk3326";
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
mmc2 = &sdio;
};
chosen { chosen {
bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootwait"; bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootwait";
}; };

1
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -1006,6 +1006,7 @@
reg-io-width = <4>; reg-io-width = <4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hdmi", "hdmi_wakeup";
clocks = <&cru PCLK_HDMI>, clocks = <&cru PCLK_HDMI>,
<&cru SCLK_HDMI_SFC>, <&cru SCLK_HDMI_SFC>,
<&cru SCLK_RTC32K>, <&cru SCLK_RTC32K>,

9
arch/arm64/boot/dts/rockchip/rk3358-linux.dtsi
View File

@ -33,6 +33,15 @@
compatible = "rockchip,drm-logo"; compatible = "rockchip,drm-logo";
reg = <0x0 0x0 0x0 0x0>; reg = <0x0 0x0 0x0 0x0>;
}; };
ramoops: ramoops@110000 {
compatible = "ramoops";
reg = <0x0 0x110000 0x0 0xf0000>;
record-size = <0x20000>;
console-size = <0x80000>;
ftrace-size = <0x00000>;
pmsg-size = <0x50000>;
};
}; };
}; };

3
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View File

@ -1658,7 +1658,8 @@
compatible = "rockchip,rk3368-dw-hdmi"; compatible = "rockchip,rk3368-dw-hdmi";
reg = <0x0 0xff980000 0x0 0x20000>; reg = <0x0 0xff980000 0x0 0x20000>;
reg-io-width = <4>; reg-io-width = <4>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hdmi", "hdmi_wakeup";
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
clock-names = "iahb", "isfr", "cec"; clock-names = "iahb", "isfr", "cec";
pinctrl-names = "default"; pinctrl-names = "default";

29
arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-v13-android-avb.dts
View File

@ -184,6 +184,29 @@
}; };
}; };
gc8034: gc8034@37 {
compatible = "galaxycore,gc8034";
status = "okay";
reg = <0x37>;
clocks = <&cru SCLK_CIF_OUT>;
clock-names = "xvclk";
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&cif_clkout>;
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "LH-RK-8034-v1.0";
rockchip,camera-module-lens-name = "CK8401";
lens-focus = <&vm149c>;
port {
gc8034_out: endpoint {
remote-endpoint = <&mipi_in_gc8034>;
data-lanes = <1 2 3 4>;
};
};
};
ov13850: ov13850@10 { ov13850: ov13850@10 {
compatible = "ovti,ov13850"; compatible = "ovti,ov13850";
status = "okay"; status = "okay";
@ -300,6 +323,12 @@
remote-endpoint = <&ucam_out0>; remote-endpoint = <&ucam_out0>;
data-lanes = <1 2>; data-lanes = <1 2>;
}; };
mipi_in_gc8034: endpoint@0 {
reg = <0>;
remote-endpoint = <&gc8034_out>;
data-lanes = <1 2 3 4>;
};
}; };
port@1 { port@1 {

6
arch/arm64/boot/dts/rockchip/rk3399-linux.dtsi
View File

@ -46,6 +46,12 @@
/ { / {
compatible = "rockchip,linux", "rockchip,rk3399"; compatible = "rockchip,linux", "rockchip,rk3399";
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
mmc2 = &sdio0;
};
chosen { chosen {
bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait coherent_pool=1m"; bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait coherent_pool=1m";
}; };

6
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
View File

@ -11,7 +11,7 @@
opp-shared; opp-shared;
rockchip,temp-hysteresis = <5000>; rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>; rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <900000>; rockchip,low-temp-min-volt = <900000>;
nvmem-cells = <&cpul_leakage>, <&specification_serial_number>, nvmem-cells = <&cpul_leakage>, <&specification_serial_number>,
@ -104,7 +104,7 @@
opp-shared; opp-shared;
rockchip,temp-hysteresis = <5000>; rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>; rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <900000>; rockchip,low-temp-min-volt = <900000>;
nvmem-cells = <&cpub_leakage>, <&specification_serial_number>, nvmem-cells = <&cpub_leakage>, <&specification_serial_number>,
@ -224,7 +224,7 @@
rockchip,thermal-zone = "soc-thermal"; rockchip,thermal-zone = "soc-thermal";
rockchip,temp-hysteresis = <5000>; rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>; rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <900000>; rockchip,low-temp-min-volt = <900000>;
nvmem-cells = <&gpu_leakage>; nvmem-cells = <&gpu_leakage>;

38
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -290,6 +290,7 @@
<&pcie_phy 2>, <&pcie_phy 3>; <&pcie_phy 2>, <&pcie_phy 3>;
phy-names = "pcie-phy-0", "pcie-phy-1", phy-names = "pcie-phy-0", "pcie-phy-1",
"pcie-phy-2", "pcie-phy-3"; "pcie-phy-2", "pcie-phy-3";
power-domains = <&power RK3399_PD_PERIHP>;
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
@ -447,6 +448,16 @@
status = "disabled"; status = "disabled";
}; };
debug: debug@fe430000 {
compatible = "rockchip,debug";
reg = <0x0 0xfe430000 0x0 0x1000>,
<0x0 0xfe432000 0x0 0x1000>,
<0x0 0xfe434000 0x0 0x1000>,
<0x0 0xfe436000 0x0 0x1000>,
<0x0 0xfe610000 0x0 0x1000>,
<0x0 0xfe710000 0x0 0x1000>;
};
usbdrd3_0: usb@fe800000 { usbdrd3_0: usb@fe800000 {
compatible = "rockchip,rk3399-dwc3"; compatible = "rockchip,rk3399-dwc3";
#address-cells = <2>; #address-cells = <2>;
@ -2044,7 +2055,9 @@
hdmi: hdmi@ff940000 { hdmi: hdmi@ff940000 {
compatible = "rockchip,rk3399-dw-hdmi"; compatible = "rockchip,rk3399-dw-hdmi";
reg = <0x0 0xff940000 0x0 0x20000>; reg = <0x0 0xff940000 0x0 0x20000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "hdmi", "hdmi_wakeup";
clocks = <&cru PCLK_HDMI_CTRL>, clocks = <&cru PCLK_HDMI_CTRL>,
<&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>,
<&cru PLL_VPLL>, <&cru PLL_VPLL>,
@ -2300,6 +2313,29 @@
reg = <0x0 0xffa8f800 0x0 0x400>; reg = <0x0 0xffa8f800 0x0 0x400>;
}; };
cci: cci@ffb00000 {
compatible = "arm,cci-500";
reg = <0x0 0xffb00000 0x0 0x10000>;
ranges = <0x0 0x0 0xffb00000 0xa0000>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
cci_pmu: pmu@10000 {
compatible = "arm,cci-500-pmu,r0";
reg = <0x10000 0x80000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
};
rockchip_system_monitor: rockchip-system-monitor { rockchip_system_monitor: rockchip-system-monitor {
compatible = "rockchip,system-monitor"; compatible = "rockchip,system-monitor";

106
arch/arm64/boot/dts/rockchip/rk3528-android.dtsi Normal file
View File

@ -0,0 +1,106 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/ {
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 driver_async_probe=dwmmc_rockchip,rk_gmac-dwmac,rockchip-drm drm_kms_helper.fbdev_emulation=0";
};
fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <0>;
rockchip,wake-irq = <0>;
/* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <1>;
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
status = "okay";
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x00800000>;
linux,cma-default;
};
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0 0x0 0x0>;
};
drm_cubic_lut: drm-cubic-lut@00000000 {
compatible = "rockchip,drm-cubic-lut";
reg = <0x0 0x0 0x0 0x0>;
};
ramoops: ramoops@110000 {
compatible = "ramoops";
/* 0x110000 to 0x1f0000 is for ramoops */
reg = <0x0 0x110000 0x0 0xe0000>;
boot-log-size = <0x8000>; /* do not change */
boot-log-count = <0x1>; /* do not change */
console-size = <0x80000>;
pmsg-size = <0x30000>;
ftrace-size = <0x00000>;
record-size = <0x14000>;
};
};
};
&display_subsystem {
memory-region = <&drm_logo>, <&drm_cubic_lut>;
memory-region-names = "drm-logo", "drm-cubic-lut";
/* devfreq = <&dmc>; */
route {
route_hdmi: route-hdmi {
status = "okay";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "fullscreen";
charge_logo,mode = "center";
connect = <&vp0_out_hdmi>;
};
route_tve: route-tve {
status = "okay";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "fullscreen";
charge_logo,mode = "center";
connect = <&vp1_out_tve>;
};
};
};
&rng {
status = "okay";
};
&vop {
/*
* VOP3_ESMART_8K_MODE = 0,
* VOP3_ESMART_4K_4K_MODE = 1,
* VOP3_ESMART_4K_2K_2K_MODE = 2,
* VOP3_ESMART_2K_2K_2K_2K_MODE = 3,
*/
esmart_lb_mode = /bits/ 8 <3>;
support-multi-area;
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/rk-input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk-stb-ir-keymap.dtsi"
/ {
acodec_sound: acodec-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,name = "rk3528-acodec";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&sai2>;
};
simple-audio-card,codec {
sound-dai = <&acodec>;
};
};
adc_keys: adc-keys {
status = "okay";
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
vol-up-key {
label = "volume up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <1750>;
};
};
bt_sco: bt-sco {
status = "disabled";
compatible = "delta,dfbmcs320";
#sound-dai-cells = <1>;
};
bt_sound: bt-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <0>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {
sound-dai = <&sai0>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco 1>;
};
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
leds: gpio-leds {
compatible = "gpio-leds";
ir {
gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
};
net-red {
gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
};
net-green {
gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
};
pwr-red {
gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
retain-state-suspended;
retain-state-shutdown;
};
pwr-green {
gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "on";
retain-state-suspended;
retain-state-shutdown;
};
};
hdmi_sound: hdmi-sound {
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,card-name = "rockchip,hdmi";
rockchip,cpu = <&sai3>;
rockchip,codec = <&hdmi>;
rockchip,jack-det;
};
pdmics: dummy-codec {
status = "disabled";
compatible = "rockchip,dummy-codec";
#sound-dai-cells = <0>;
};
pdm_mic_array: pdm-mic-array {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,name = "rockchip,pdm-mic-array";
simple-audio-card,cpu {
sound-dai = <&pdm>;
};
simple-audio-card,codec {
sound-dai = <&pdmics>;
};
};
spdif-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,name = "ROCKCHIP,SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif_8ch>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
spdif_out: spdif-out {
status = "okay";
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
};
vdd_logic: vdd-logic {
compatible = "pwm-regulator";
pwms = <&pwm2 0 5000 1>;
regulator-name = "vdd_logic";
regulator-min-microvolt = <703000>;
regulator-max-microvolt = <1006000>;
regulator-init-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
status = "okay";
};
vdd_cpu: vdd-cpu {
compatible = "pwm-regulator";
pwms = <&pwm1 0 5000 1>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <746000>;
regulator-max-microvolt = <1201000>;
regulator-init-microvolt = <953000>;
regulator-always-on;
regulator-boot-on;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
status = "okay";
};
vdd_0v9_s3: vdd-0v9-s3 {
compatible = "regulator-fixed";
regulator-name = "vdd_0v9_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc5v0_sys>;
};
vdd_1v8_s3: vdd-1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_3v3_s3: vcc-3v3-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_ddr_s3: vcc-ddr-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_ddr_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vcc5v0_sys>;
};
};
&acodec {
pa-ctl-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&avsd {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&crypto {
status = "okay";
};
&dfi {
status = "okay";
};
&display_subsystem {
status = "okay";
};
&dmc {
center-supply = <&vdd_logic>;
status = "okay";
};
&gmac0 {
status = "okay";
};
&gpu {
mali-supply = <&vdd_logic>;
status = "okay";
};
&gpu_bus {
bus-supply = <&vdd_logic>;
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_in_vp0 {
status = "okay";
};
&hdmiphy {
status = "okay";
};
&iep {
status = "okay";
};
&iep_mmu {
status = "okay";
};
&jpegd {
status = "okay";
};
&jpegd_mmu {
status = "okay";
};
&mpp_srv {
status = "okay";
};
&pinctrl {
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&pwm3 {
compatible = "rockchip,remotectl-pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm3m0_pins>;
remote_pwm_id = <3>;
handle_cpu_id = <1>;
remote_support_psci = <0>;
status = "okay";
};
&rga2 {
status = "okay";
};
&rga2_mmu {
status = "okay";
};
&rkvdec {
status = "okay";
};
&rkvdec_mmu {
status = "okay";
};
&rkvenc {
status = "okay";
};
&rkvenc_mmu {
status = "okay";
};
&rmii0_phy {
/delete-property/ pinctrl-names;
/delete-property/ pinctrl-0;
};
&rockchip_suspend {
status = "okay";
rockchip,sleep-debug-en = <1>;
rockchip,virtual-poweroff = <1>;
rockchip,sleep-mode-config = <
(0
| RKPM_SLP_ARMPD
)
>;
rockchip,wakeup-config = <
(0
| RKPM_CPU0_WKUP_EN
| RKPM_GPIO_WKUP_EN
)
>;
rockchip,pwm-regulator-config = <
(0
| RKPM_PWM1_M0_REGULATOR_EN
)
>;
};
&sai0 {
pinctrl-0 = <&i2s0m0_lrck &i2s0m0_sclk &i2s0m0_sdi &i2s0m0_sdo>;
status = "disabled";
};
&sai2 {
status = "okay";
};
&sai3 {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vdd_1v8_s3>;
};
&sdhci {
bus-width = <8>;
supports-emmc;
non-removable;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
max-frequency = <200000000>;
fixed-emmc-driver-type = <4>;
status = "okay";
};
&spdif_8ch {
status = "okay";
};
&tsadc {
status = "okay";
};
&tve {
status = "okay";
};
&tve_in_vp1 {
status = "okay";
};
&u2phy_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy_otg {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&usb2phy {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usbdrd30 {
status = "okay";
};
&usbdrd_dwc3 {
dr_mode = "otg";
maximum-speed = "high-speed";
extcon = <&usb2phy>;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
status = "okay";
};
&vdpp {
status = "okay";
};
&vdpu {
status = "okay";
};
&vdpu_mmu {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528-demo1-lp4-v10.dtsi"
#include "rk3528-android.dtsi"
/{
firmware {
android {
compatible = "android,firmware";
boot_devices = "ffbf0000.mmc";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,avb";
};
};
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3528.dtsi"
#include "rk3528-demo.dtsi"
/ {
model = "Rockchip RK3528 DEMO1 LP4 V10 Board";
compatible = "rockchip,rk3528-demo1-lp4-v10", "rockchip,rk3528";
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h &wifi_reset &clkm0_32k_out>;
reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
};
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart2m0_rtsn>;
pinctrl-1 = <&uart2m0_gpios>;
BT,reset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "rtl8822cs";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
WIFI,host_wake_irq = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&sdio1 {
max-frequency = <200000000>;
no-sd;
no-mmc;
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
mmc-pwrseq = <&sdio_pwrseq>;
pinctrl-names = "default";
pinctrl-0 = <&sdio1_bus4 &sdio1_cmd &sdio1_clk>;
sd-uhs-sdr104;
status = "okay";
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer &uart2m0_ctsn>;
};
&pinctrl {
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
};
wifi_reset: wifi-reset {
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
};
};
wireless-bluetooth {
uart2m0_gpios: uart2m0-gpios {
rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528-demo4-ddr4-v10.dtsi"
#include "rk3528-android.dtsi"
/{
firmware {
android {
compatible = "android,firmware";
boot_devices = "ffbf0000.mmc";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,avb";
};
};
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3528.dtsi"
#include "rk3528-demo.dtsi"
/ {
model = "Rockchip RK3528 DEMO4 DDR4 V10 Board";
compatible = "rockchip,rk3528-demo4-ddr4-v10", "rockchip,rk3528";
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h &wifi_reset>;
reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
};
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart2m0_rtsn>;
pinctrl-1 = <&uart2m0_gpios>;
BT,reset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "rtl8822cs";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
WIFI,host_wake_irq = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&sdio1 {
max-frequency = <200000000>;
no-sd;
no-mmc;
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
mmc-pwrseq = <&sdio_pwrseq>;
pinctrl-names = "default";
pinctrl-0 = <&sdio1_bus4 &sdio1_cmd &sdio1_clk>;
sd-uhs-sdr104;
status = "okay";
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer &uart2m0_ctsn>;
};
&pinctrl {
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
};
wifi_reset: wifi-reset {
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
};
};
wireless-bluetooth {
uart2m0_gpios: uart2m0-gpios {
rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/rk-input.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
acodec_sound: acodec-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,name = "rk3528-acodec";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&sai2>;
};
simple-audio-card,codec {
sound-dai = <&acodec>;
};
};
adc_keys: adc-keys {
status = "okay";
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
vol-up-key {
label = "volume up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <1750>;
};
};
bt_sco: bt-sco {
status = "disabled";
compatible = "delta,dfbmcs320";
#sound-dai-cells = <1>;
};
bt_sound: bt-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <0>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {
sound-dai = <&sai0>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco 1>;
};
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
es7243_sound: es7243-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,name = "rockchip,es7243";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
simple-audio-card,codec {
sound-dai = <&es7243e>;
};
};
hdmi_sound: hdmi-sound {
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,card-name = "rockchip,hdmi";
rockchip,cpu = <&sai3>;
rockchip,codec = <&hdmi>;
rockchip,jack-det;
};
pdmics: dummy-codec {
status = "disabled";
compatible = "rockchip,dummy-codec";
#sound-dai-cells = <0>;
};
pdm_mic_array: pdm-mic-array {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,name = "rockchip,pdm-mic-array";
simple-audio-card,cpu {
sound-dai = <&pdm>;
};
simple-audio-card,codec {
sound-dai = <&pdmics>;
};
};
spdif-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,name = "ROCKCHIP,SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif_8ch>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
spdif_out: spdif-out {
status = "okay";
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
};
vcc5v0_otg: vcc5v0-otg-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_otg_en>;
};
/omit-if-no-ref/
vccio_sd: vccio-sd {
compatible = "regulator-gpio";
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
states = <1800000 0x0
3300000 0x1>;
};
vdd_logic: vdd-logic {
compatible = "pwm-regulator";
pwms = <&pwm2 0 5000 1>;
regulator-name = "vdd_logic";
regulator-min-microvolt = <705000>;
regulator-max-microvolt = <1006000>;
regulator-init-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
status = "okay";
};
vdd_cpu: vdd-cpu {
compatible = "pwm-regulator";
pwms = <&pwm1 0 5000 1>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <746000>;
regulator-max-microvolt = <1201000>;
regulator-init-microvolt = <953000>;
regulator-always-on;
regulator-boot-on;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
status = "okay";
};
vdd_gpu: vdd-gpu {
compatible = "pwm-regulator";
pwms = <&pwm0 0 5000 1>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <705000>;
regulator-max-microvolt = <1148000>;
regulator-init-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
status = "okay";
};
vdd_0v9_s3: vdd-0v9-s3 {
compatible = "regulator-fixed";
regulator-name = "vdd_0v9_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc5v0_sys>;
};
vdd_1v8_s3: vdd-1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_3v3_s3: vcc-3v3-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
/omit-if-no-ref/
vcc_sd: vcc-sd {
compatible = "regulator-fixed";
gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
regulator-name = "vcc_sd";
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_s3>;
};
vcc_ddr_s3: vcc-ddr-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_ddr_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vcc5v0_sys>;
};
};
&acodec {
pa-ctl-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&avsd {
status = "okay";
};
&combphy_pu {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&crypto {
status = "okay";
};
&dfi {
status = "okay";
};
&display_subsystem {
status = "okay";
};
&dmc {
center-supply = <&vdd_logic>;
status = "okay";
};
&gmac0 {
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&gpu_bus {
bus-supply = <&vdd_logic>;
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_in_vp0 {
status = "okay";
};
&hdmiphy {
status = "okay";
};
&i2c6 {
status = "disabled";
es7243e: es7243e@10 {
status = "okay";
#sound-dai-cells = <0>;
compatible = "ES7243E_MicArray_0";
reg = <0x10>;
};
es7243e_11: es7243e@11 {
status = "okay";
#sound-dai-cells = <0>;
compatible = "ES7243E_MicArray_1";
reg = <0x11>;
};
es7243e_12: es7243e@12 {
status = "okay";
#sound-dai-cells = <0>;
compatible = "ES7243E_MicArray_2";
reg = <0x12>;
};
};
&iep {
status = "okay";
};
&iep_mmu {
status = "okay";
};
&jpegd {
status = "okay";
};
&jpegd_mmu {
status = "okay";
};
&mpp_srv {
status = "okay";
};
&pinctrl {
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_otg_en: vcc5v0-otg-en {
rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&pwm3 {
compatible = "rockchip,remotectl-pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm3m0_pins>;
remote_pwm_id = <3>;
handle_cpu_id = <1>;
remote_support_psci = <0>;
status = "okay";
ir_key1 {
rockchip,usercode = <0x4040>;
rockchip,key_table =
<0xf2 KEY_REPLY>,
<0xba KEY_BACK>,
<0xf4 KEY_UP>,
<0xf1 KEY_DOWN>,
<0xef KEY_LEFT>,
<0xee KEY_RIGHT>,
<0xbd KEY_HOME>,
<0xea KEY_VOLUMEUP>,
<0xe3 KEY_VOLUMEDOWN>,
<0xe2 KEY_SEARCH>,
<0xb2 KEY_POWER>,
<0xbc KEY_MUTE>,
<0xec KEY_MENU>,
<0xbf 0x190>,
<0xe0 0x191>,
<0xe1 0x192>,
<0xe9 183>,
<0xe6 248>,
<0xe8 185>,
<0xe7 186>,
<0xf0 388>,
<0xbe 0x175>;
};
ir_key2 {
rockchip,usercode = <0xff00>;
rockchip,key_table =
<0xf9 KEY_HOME>,
<0xbf KEY_BACK>,
<0xfb KEY_MENU>,
<0xaa KEY_REPLY>,
<0xb9 KEY_UP>,
<0xe9 KEY_DOWN>,
<0xb8 KEY_LEFT>,
<0xea KEY_RIGHT>,
<0xeb KEY_VOLUMEDOWN>,
<0xef KEY_VOLUMEUP>,
<0xf7 KEY_MUTE>,
<0xe7 KEY_POWER>,
<0xfc KEY_POWER>,
<0xa9 KEY_VOLUMEDOWN>,
<0xa8 KEY_PLAYPAUSE>,
<0xe0 KEY_VOLUMEDOWN>,
<0xa5 KEY_VOLUMEDOWN>,
<0xab 183>,
<0xb7 388>,
<0xe8 388>,
<0xf8 184>,
<0xaf 185>,
<0xed KEY_VOLUMEDOWN>,
<0xee 186>,
<0xb3 KEY_VOLUMEDOWN>,
<0xf1 KEY_VOLUMEDOWN>,
<0xf2 KEY_VOLUMEDOWN>,
<0xf3 KEY_SEARCH>,
<0xb4 KEY_VOLUMEDOWN>,
<0xa4 KEY_SETUP>,
<0xbe KEY_SEARCH>;
};
ir_key3 {
rockchip,usercode = <0x1dcc>;
rockchip,key_table =
<0xee KEY_REPLY>,
<0xf0 KEY_BACK>,
<0xf8 KEY_UP>,
<0xbb KEY_DOWN>,
<0xef KEY_LEFT>,
<0xed KEY_RIGHT>,
<0xfc KEY_HOME>,
<0xf1 KEY_VOLUMEUP>,
<0xfd KEY_VOLUMEDOWN>,
<0xb7 KEY_SEARCH>,
<0xff KEY_POWER>,
<0xf3 KEY_MUTE>,
<0xbf KEY_MENU>,
<0xf9 0x191>,
<0xf5 0x192>,
<0xb3 388>,
<0xbe KEY_1>,
<0xba KEY_2>,
<0xb2 KEY_3>,
<0xbd KEY_4>,
<0xf9 KEY_5>,
<0xb1 KEY_6>,
<0xfc KEY_7>,
<0xf8 KEY_8>,
<0xb0 KEY_9>,
<0xb6 KEY_0>,
<0xb5 KEY_BACKSPACE>;
};
};
&rga2 {
status = "okay";
};
&rga2_mmu {
status = "okay";
};
&rkvdec {
status = "okay";
};
&rkvdec_mmu {
status = "okay";
};
&rkvenc {
status = "okay";
};
&rkvenc_mmu {
status = "okay";
};
&rockchip_suspend {
status = "okay";
rockchip,sleep-debug-en = <1>;
rockchip,virtual-poweroff = <1>;
rockchip,sleep-mode-config = <
(0
| RKPM_SLP_ARMPD
)
>;
rockchip,wakeup-config = <
(0
| RKPM_CPU0_WKUP_EN
| RKPM_GPIO_WKUP_EN
)
>;
rockchip,pwm-regulator-config = <
(0
| RKPM_PWM0_M0_REGULATOR_EN
| RKPM_PWM1_M0_REGULATOR_EN
)
>;
};
&sai0 {
pinctrl-0 = <&i2s0m1_lrck &i2s0m1_sclk &i2s0m1_sdi &i2s0m1_sdo>;
status = "disabled";
};
&sai2 {
status = "okay";
};
&sai3 {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vdd_1v8_s3>;
};
&sdhci {
bus-width = <8>;
supports-emmc;
non-removable;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
max-frequency = <200000000>;
fixed-emmc-driver-type = <4>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
rockchip,default-sample-phase = <90>;
supports-sd;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
vqmmc-supply = <&vccio_sd>;
vmmc-supply = <&vcc_sd>;
status = "disabled";
};
&sfc {
status = "okay";
};
&spdif_8ch {
status = "okay";
};
&tsadc {
status = "okay";
};
&tve {
status = "okay";
};
&tve_in_vp1 {
status = "okay";
};
&u2phy_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy_otg {
vbus-supply = <&vcc5v0_otg>;
status = "okay";
};
&usb2phy {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usbdrd30 {
status = "okay";
};
&usbdrd_dwc3 {
dr_mode = "otg";
extcon = <&usb2phy>;
status = "okay";
};
&vdpp {
status = "okay";
};
&vdpu {
status = "okay";
};
&vdpu_mmu {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528-evb1-ddr4-v10.dtsi"
#include "rk3528-linux.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528-evb1-ddr4-v10.dtsi"
#include "rk3528-android.dtsi"
/{
firmware {
android {
compatible = "android,firmware";
boot_devices = "ffbf0000.mmc";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,avb";
};
};
};
};
};
&sdmmc {
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3528.dtsi"
#include "rk3528-evb.dtsi"
/ {
model = "Rockchip RK3528 EVB1 DDR4 V10 Board";
compatible = "rockchip,rk3528-evb1-ddr4-v10", "rockchip,rk3528";
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h &clkm1_32k_out>;
reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
};
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart2m1_rtsn>;
pinctrl-1 = <&uart2m1_gpios>;
BT,reset_gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "ap6275s";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&es7243_sound {
status = "disabled";
};
&gmac1 {
/* Use rgmii-rxid mode to disable rx delay inside Soc */
phy-mode = "rgmii-rxid";
clock_in_out = "output";
snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x30>;
/* rx_delay = <0x3f>; */
pinctrl-names = "default";
pinctrl-0 = <&rgmii_miim
&rgmii_tx_bus2
&rgmii_rx_bus2
&rgmii_rgmii_clk
&rgmii_rgmii_bus>;
phy-handle = <&rgmii_phy>;
status = "okay";
};
&i2c6 {
status = "okay";
};
&mdio1 {
rgmii_phy: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
};
};
&sai1 {
status = "okay";
};
&sdio0 {
max-frequency = <200000000>;
no-sd;
no-mmc;
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
mmc-pwrseq = <&sdio_pwrseq>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn>;
};
&pinctrl {
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_32k: wifi-32k {
rockchip,pins = <1 RK_PC3 1 &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
wireless-bluetooth {
uart2m1_gpios: uart2m1-gpios {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528-evb2-ddr3-v10.dtsi"
#include "rk3528-android.dtsi"
/{
firmware {
android {
compatible = "android,firmware";
boot_devices = "ffbf0000.mmc";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,avb";
};
};
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3528.dtsi"
#include "rk3528-evb.dtsi"
/ {
model = "Rockchip RK3528 EVB2 DDR3 V10 Board";
compatible = "rockchip,rk3528-evb2-ddr3-v10", "rockchip,rk3528";
pcie20_usb30_avdd0v9: pcie20-usb30-avdd0v9 {
compatible = "regulator-fixed";
regulator-name = "pcie20_usb30-avdd0v9";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vdd_0v9_s3>;
};
pcie20_usb30_avdd1v8: pcie20-usb30-avdd1v8 {
compatible = "regulator-fixed";
regulator-name = "pcie20_usb30_avdd1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vdd_1v8_s3>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h &clkm1_32k_out>;
reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
};
vcc3v3_pcie20: vcc3v3-pcie20 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie20";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
startup-delay-us = <5000>;
vin-supply = <&dc_12v>;
};
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart2m1_rtsn>;
pinctrl-1 = <&uart2m1_gpios>;
BT,reset_gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "ap6275s";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&pcie2x1 {
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie20>;
status = "okay";
};
&sdio0 {
max-frequency = <200000000>;
no-sd;
no-mmc;
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
mmc-pwrseq = <&sdio_pwrseq>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn>;
};
&usbdrd_dwc3 {
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
};
&pinctrl {
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_32k: wifi-32k {
rockchip,pins = <1 RK_PC3 1 &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
wireless-bluetooth {
uart2m1_gpios: uart2m1-gpios {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

50
arch/arm64/boot/dts/rockchip/rk3528-evb3-lp4x-v10.dts Normal file
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@ -0,0 +1,50 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528-evb3-lp4x-v10.dtsi"
#include "rk3528-android.dtsi"
/{
firmware {
android {
compatible = "android,firmware";
boot_devices = "ffbf0000.mmc";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,avb";
};
};
};
};
};
&pdm {
status = "okay";
pinctrl-0 = <&pdm_clk1
&pdm_sdi0
&pdm_sdi2>;
};
&pdmics {
status = "okay";
};
&pdm_mic_array {
status = "okay";
};
&sdmmc {
status = "okay";
};

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arch/arm64/boot/dts/rockchip/rk3528-evb3-lp4x-v10.dtsi Normal file
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@ -0,0 +1,132 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3528.dtsi"
#include "rk3528-evb.dtsi"
/ {
model = "Rockchip RK3528 EVB3 LP4X V10 Board";
compatible = "rockchip,rk3528-evb3-lp4x-v10", "rockchip,rk3528";
vcc5v0_sys_s0: vcc5v0-sys-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_1v8_s0: vcc-1v8-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc5v0_sys_s0>;
};
vcc_3v3_s0: vcc-3v3-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys_s0>;
};
vdd_0v9_s0: vdd-0v9-s0 {
compatible = "regulator-fixed";
regulator-name = "vdd_0v9_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc5v0_sys_s0>;
};
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
uart_rts_gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart2m0_rtsn>;
pinctrl-1 = <&uart2m0_gpios>;
BT,reset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "ap6275p";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable &wifi_host_wake_irq &clkm0_32k_out>;
WIFI,reset_gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
WIFI,host_wake_irq = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&pcie2x1 {
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_perst>;
rockchip,skip-scan-in-resume;
status = "okay";
};
&sai0 {
pinctrl-0 = <&i2s0m0_lrck &i2s0m0_sclk &i2s0m0_sdi &i2s0m0_sdo>;
status = "disabled";
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer &uart2m0_ctsn>;
};
&usbdrd_dwc3 {
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
};
&pinctrl {
wireless-wlan {
wifi_perst: wifi-perst {
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
wifi_enable: wifi-enable {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_output_high>;
};
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
wireless-bluetooth {
uart2m0_gpios: uart2m0-gpios {
rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&acodec {
pa-ctl-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
status = "okay";
};

35
arch/arm64/boot/dts/rockchip/rk3528-evb4-ddr4-v10.dts Normal file
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@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528-evb1-ddr4-v10.dtsi"
#include "rk3528-android.dtsi"
/{
firmware {
android {
compatible = "android,firmware";
boot_devices = "ffbf0000.mmc";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,avb";
};
};
};
};
};
&sdmmc {
status = "okay";
};

203
arch/arm64/boot/dts/rockchip/rk3528-iotest-lp3-v10.dts Normal file
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@ -0,0 +1,203 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "rk3528.dtsi"
#include "rk3528-android.dtsi"
/ {
model = "Rockchip RK3528 IOTEST LP3 V10 Board";
compatible = "rockchip,rk3528-iotest-lp3-v10", "rockchip,rk3528";
firmware {
android {
compatible = "android,firmware";
boot_devices = "ffbf0000.mmc";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,avb";
};
};
};
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vdd_logic: vdd-logic {
compatible = "pwm-regulator";
pwms = <&pwm2 0 5000 1>;
regulator-name = "vdd_logic";
regulator-min-microvolt = <705000>;
regulator-max-microvolt = <1006000>;
regulator-init-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
status = "okay";
};
vdd_cpu: vdd-cpu {
compatible = "pwm-regulator";
pwms = <&pwm1 0 5000 1>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <746000>;
regulator-max-microvolt = <1201000>;
regulator-init-microvolt = <953000>;
regulator-always-on;
regulator-boot-on;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
status = "okay";
};
vdd_gpu: vdd-gpu {
compatible = "pwm-regulator";
pwms = <&pwm0 0 5000 1>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <705000>;
regulator-max-microvolt = <1148000>;
regulator-init-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
status = "okay";
};
vdd_0v9_s3: vdd-0v9-s3 {
compatible = "regulator-fixed";
regulator-name = "vdd_0v9_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc5v0_sys>;
};
vdd_1v8_s3: vdd-1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_3v3_s3: vcc-3v3-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_ddr_s3: vcc-ddr-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_ddr_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vcc5v0_sys>;
};
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu0_opp_table {
/delete-node/ opp-1416000000;
/delete-node/ opp-1608000000;
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&sdhci {
bus-width = <8>;
supports-emmc;
non-removable;
max-frequency = <200000000>;
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usb2phy {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usbdrd30 {
status = "okay";
};
&usbdrd_dwc3 {
dr_mode = "peripheral";
maximum-speed = "high-speed";
extcon = <&usb2phy>;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
status = "okay";
};

88
arch/arm64/boot/dts/rockchip/rk3528-linux.dtsi Normal file
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@ -0,0 +1,88 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/ {
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
};
fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <0>;
rockchip,wake-irq = <0>;
/* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <1>;
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
status = "okay";
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0 0x0 0x0>;
};
drm_cubic_lut: drm-cubic-lut@00000000 {
compatible = "rockchip,drm-cubic-lut";
reg = <0x0 0x0 0x0 0x0>;
};
ramoops: ramoops@110000 {
compatible = "ramoops";
/* 0x110000 to 0x1f0000 is for ramoops */
reg = <0x0 0x110000 0x0 0xe0000>;
boot-log-size = <0x8000>; /* do not change */
boot-log-count = <0x1>; /* do not change */
console-size = <0x80000>;
pmsg-size = <0x30000>;
ftrace-size = <0x00000>;
record-size = <0x14000>;
};
};
};
&display_subsystem {
memory-region = <&drm_logo>, <&drm_cubic_lut>;
memory-region-names = "drm-logo", "drm-cubic-lut";
/* devfreq = <&dmc>; */
route {
route_hdmi: route-hdmi {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vp0_out_hdmi>;
};
route_tve: route-tve {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vp1_out_tve>;
};
};
};
&rng {
status = "okay";
};

1406
arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi Normal file
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2489
arch/arm64/boot/dts/rockchip/rk3528.dtsi Normal file
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File diff suppressed because it is too large Load Diff

27
arch/arm64/boot/dts/rockchip/rk3566-box.dtsi
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@ -32,6 +32,27 @@
}; };
}; };
bt_sco: bt-sco {
status = "disabled";
compatible = "delta,dfbmcs320";
#sound-dai-cells = <1>;
};
bt_sound: bt-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <0>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {
sound-dai = <&i2s2_2ch>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco 1>;
};
};
dc_12v: dc-12v { dc_12v: dc-12v {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "dc_12v"; regulator-name = "dc_12v";
@ -215,6 +236,12 @@
&i2s1m0_sdo0>; &i2s1m0_sdo0>;
}; };
&i2s2_2ch {
pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>;
rockchip,bclk-fs = <32>;
status = "disabled";
};
&iep { &iep {
status = "okay"; status = "okay";
}; };

13
arch/arm64/boot/dts/rockchip/rk3566-eink.dtsi
View File

@ -14,7 +14,7 @@
}; };
display_reserved: framebuffer@10900000 { display_reserved: framebuffer@10900000 {
reg = <0x0 0x10900000 0x0 0x2c00000>; reg = <0x0 0x10900000 0x0 0x3300000>;
}; };
}; };
@ -57,17 +57,6 @@
status = "okay"; status = "okay";
}; };
&dmc_opp_table {
opp-324000000 {
opp-hz = /bits/ 64 <324000000>;
opp-microvolt = <875000>;
};
opp-528000000 {
opp-hz = /bits/ 64 <528000000>;
opp-microvolt = <875000>;
};
};
&ebc { &ebc {
status = "okay"; status = "okay";
}; };

12
arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dts
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@ -5,3 +5,15 @@
#include "rk3566-evb1-ddr4-v10.dtsi" #include "rk3566-evb1-ddr4-v10.dtsi"
#include "rk3568-android.dtsi" #include "rk3568-android.dtsi"
&bt_sco {
status = "okay";
};
&bt_sound {
status = "okay";
};
&i2s3_2ch {
status = "okay";
};

26
arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi
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@ -25,13 +25,6 @@
vin-supply = <&dc_12v>; vin-supply = <&dc_12v>;
}; };
rk_headset: rk-headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
};
vcc3v3_vga: vcc3v3-vga { vcc3v3_vga: vcc3v3-vga {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "vcc3v3_vga"; regulator-name = "vcc3v3_vga";
@ -54,6 +47,13 @@
}; };
}; };
&bt_sound {
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&i2s2_2ch>;
};
};
&audiopwmout_diff { &audiopwmout_diff {
status = "disabled"; status = "disabled";
}; };
@ -280,6 +280,12 @@
}; };
}; };
&i2s2_2ch {
pinctrl-0 = <&i2s2m1_sclktx &i2s2m1_lrcktx &i2s2m1_sdi &i2s2m1_sdo>;
rockchip,bclk-fs = <32>;
status = "disabled";
};
&i2s3_2ch { &i2s3_2ch {
status = "disabled"; status = "disabled";
}; };
@ -456,12 +462,6 @@
}; };
}; };
headphone {
hp_det: hp-det {
rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
lcd0 { lcd0 {
lcd0_rst_gpio: lcd0-rst-gpio { lcd0_rst_gpio: lcd0-rst-gpio {
rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;

10
arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-linux.dts
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@ -6,13 +6,3 @@
#include "rk3566-evb2-lp4x-v10.dtsi" #include "rk3566-evb2-lp4x-v10.dtsi"
#include "rk3568-linux.dtsi" #include "rk3568-linux.dtsi"
#include <dt-bindings/display/rockchip_vop.h>
&vp0 {
cursor-win-id = <ROCKCHIP_VOP2_CLUSTER0>;
};
&vp1 {
cursor-win-id = <ROCKCHIP_VOP2_CLUSTER1>;
};

26
arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi
View File

@ -16,13 +16,6 @@
model = "Rockchip RK3566 EVB2 LP4X V10 Board"; model = "Rockchip RK3566 EVB2 LP4X V10 Board";
compatible = "rockchip,rk3566-evb2-lp4x-v10", "rockchip,rk3566"; compatible = "rockchip,rk3566-evb2-lp4x-v10", "rockchip,rk3566";
rk_headset: rk-headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
};
vcc_camera: vcc-camera-regulator { vcc_camera: vcc-camera-regulator {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
@ -46,6 +39,13 @@
}; };
}; };
&bt_sound {
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&i2s2_2ch>;
};
};
&combphy1_usq { &combphy1_usq {
status = "okay"; status = "okay";
}; };
@ -369,6 +369,12 @@
}; };
}; };
&i2s2_2ch {
pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>;
rockchip,bclk-fs = <32>;
status = "disabled";
};
&mdio1 { &mdio1 {
rgmii_phy0: phy@0 { rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
@ -442,12 +448,6 @@
}; };
}; };
headphone {
hp_det: hp-det {
rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq { sdio-pwrseq {
wifi_enable_h: wifi-enable-h { wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;

13
arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi
View File

@ -44,6 +44,13 @@
}; };
}; };
&bt_sound {
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&i2s2_2ch>;
};
};
&combphy1_usq { &combphy1_usq {
status = "okay"; status = "okay";
}; };
@ -266,6 +273,12 @@
status = "disabled"; status = "disabled";
}; };
&i2s2_2ch {
pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>;
rockchip,bclk-fs = <32>;
status = "disabled";
};
&i2s3_2ch { &i2s3_2ch {
status = "okay"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";

13
arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi
View File

@ -47,6 +47,13 @@
status = "disabled"; status = "disabled";
}; };
&bt_sound {
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&i2s2_2ch>;
};
};
&combphy1_usq { &combphy1_usq {
status = "okay"; status = "okay";
}; };
@ -169,6 +176,12 @@
status = "disabled"; status = "disabled";
}; };
&i2s2_2ch {
pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>;
rockchip,bclk-fs = <32>;
status = "disabled";
};
&i2s3_2ch { &i2s3_2ch {
status = "disabled"; status = "disabled";
}; };

4
arch/arm64/boot/dts/rockchip/rk3566.dtsi
View File

@ -38,7 +38,7 @@
}; };
&rkisp { &rkisp {
rockchip,iq-feature = /bits/ 64 <0x3FBF7FE67FF>; rockchip,iq-feature = /bits/ 64 <0x1BFBF7FE67FF>;
}; };
&usbdrd_dwc3 { &usbdrd_dwc3 {
@ -47,12 +47,14 @@
extcon = <&usb2phy0>; extcon = <&usb2phy0>;
maximum-speed = "high-speed"; maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk; snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
}; };
/delete-node/ &combphy0_us; /delete-node/ &combphy0_us;
/delete-node/ &gmac0_clkin; /delete-node/ &gmac0_clkin;
/delete-node/ &gmac0_xpcsclk; /delete-node/ &gmac0_xpcsclk;
/delete-node/ &gmac0; /delete-node/ &gmac0;
/delete-node/ &gmac_uio0;
/delete-node/ &pcie30_phy_grf; /delete-node/ &pcie30_phy_grf;
/delete-node/ &pcie30phy; /delete-node/ &pcie30phy;
/delete-node/ &pcie3x1; /delete-node/ &pcie3x1;

58
arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi
View File

@ -7,7 +7,8 @@
rockchip_amp: rockchip-amp { rockchip_amp: rockchip-amp {
compatible = "rockchip,rk3568-amp"; compatible = "rockchip,rk3568-amp";
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>, clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>,
<&cru PCLK_TIMER>, <&cru CLK_TIMER4>, <&cru CLK_TIMER5>; <&cru PCLK_TIMER>, <&cru CLK_TIMER4>, <&cru CLK_TIMER5>,
<&cru ACLK_MCU>;
clock-names = "baudclk", "apb_pclk", "pclk", "timer"; clock-names = "baudclk", "apb_pclk", "pclk", "timer";
assigned-clocks = <&cru SCLK_UART4>, assigned-clocks = <&cru SCLK_UART4>,
<&cru CLK_TIMER4>, <&cru CLK_TIMER4>,
@ -16,20 +17,59 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart4m1_xfer>; pinctrl-0 = <&uart4m1_xfer>;
status = "disabled"; status = "okay";
amp_cpus: amp-cpus { amp_cpus: amp-cpus {
amp-cpu2 {
id = <0x0 0x200>;
entry = <0x0 0x3800000>;
mode = <0>;
};
amp-cpu3 { amp-cpu3 {
id = <0x0 0x300>; id = <0x0 0x300>;
entry = <0x0 0x5800000>; entry = <0x0 0x1800000>;
mode = <0>; mode = <0>;
}; };
}; };
}; };
rpmsg: rpmsg@7c00000 {
compatible = "rockchip,rk3568-rpmsg";
mbox-names = "rpmsg-rx", "rpmsg-tx";
mboxes = <&mailbox 0 &mailbox 3>;
rockchip,vdev-nums = <1>;
rockchip,link-id = <0x03>;
reg = <0x0 0x7c00000 0x0 0x20000>;
memory-region = <&rpmsg_dma_reserved>;
status = "okay";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* remote amp core address */
amp_shmem_reserved: amp-shmem@7800000 {
reg = <0x0 0x7800000 0x0 0x400000>;
no-map;
};
rpmsg_reserved: rpmsg@7c00000 {
reg = <0x0 0x7c00000 0x0 0x400000>;
no-map;
};
rpmsg_dma_reserved: rpmsg-dma@8000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x8000000 0x0 0x100000>;
no-map;
};
/* mcu address */
mcu_reserved: mcu@8200000 {
reg = <0x0 0x8200000 0x0 0x100000>;
no-map;
};
};
};
&mailbox {
status = "okay";
}; };

2
arch/arm64/boot/dts/rockchip/rk3568-android.dtsi
View File

@ -47,7 +47,7 @@
}; };
&reserved_memory { &reserved_memory {
linux,cma { cma {
compatible = "shared-dma-pool"; compatible = "shared-dma-pool";
inactive; inactive;
reusable; reusable;

4
arch/arm64/boot/dts/rockchip/rk3568-dram-default-timing.dtsi
View File

@ -94,7 +94,7 @@
standby_idle = <0>; standby_idle = <0>;
pd_dis_freq = <1066>; pd_dis_freq = <1066>;
sr_dis_freq = <800>; sr_dis_freq = <800>;
dram_dll_dis_freq = <625>; dram_dll_dis_freq = <500>;
phy_dll_dis_freq = <IGNORE_THIS>; phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */ /* drv when odt on */
phy_dq_drv_odten = <37>; phy_dq_drv_odten = <37>;
@ -393,7 +393,7 @@
lp4_dq_vref_odten = <228>; lp4_dq_vref_odten = <228>;
lp4_ca_vref_odten = <343>; lp4_ca_vref_odten = <343>;
/* lp4 vref info when odt disable */ /* lp4 vref info when odt disable */
phy_lp4_dq_vref_odtoff = <420>; phy_lp4_dq_vref_odtoff = <245>;
lp4_dq_vref_odtoff = <420>; lp4_dq_vref_odtoff = <420>;
lp4_ca_vref_odtoff = <343>; lp4_ca_vref_odtoff = <343>;
}; };

61
arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi
View File

@ -141,6 +141,27 @@
default-brightness-level = <200>; default-brightness-level = <200>;
}; };
bt_sco: bt-sco {
status = "disabled";
compatible = "delta,dfbmcs320";
#sound-dai-cells = <1>;
};
bt_sound: bt-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <0>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {
sound-dai = <&i2s3_2ch>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco 1>;
};
};
dc_12v: dc-12v { dc_12v: dc-12v {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "dc_12v"; regulator-name = "dc_12v";
@ -187,17 +208,15 @@
rk809_sound: rk809-sound { rk809_sound: rk809-sound {
status = "okay"; status = "okay";
compatible = "simple-audio-card"; compatible = "rockchip,multicodecs-card";
simple-audio-card,format = "i2s"; rockchip,card-name = "rockchip-rk809";
simple-audio-card,name = "rockchip,rk809-codec"; hp-det-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
simple-audio-card,mclk-fs = <256>; rockchip,format = "i2s";
rockchip,mclk-fs = <256>;
simple-audio-card,cpu { rockchip,cpu = <&i2s1_8ch>;
sound-dai = <&i2s1_8ch>; rockchip,codec = <&rk809_codec>;
}; pinctrl-names = "default";
simple-audio-card,codec { pinctrl-0 = <&hp_det>;
sound-dai = <&rk809_codec>;
};
}; };
spdif-sound { spdif-sound {
@ -1264,8 +1283,8 @@
vccio_acodec: LDO_REG4 { vccio_acodec: LDO_REG4 {
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3000000>;
regulator-name = "vccio_acodec"; regulator-name = "vccio_acodec";
regulator-state-mem { regulator-state-mem {
regulator-off-in-suspend; regulator-off-in-suspend;
@ -1422,6 +1441,12 @@
&i2s1m0_sdo0>; &i2s1m0_sdo0>;
}; };
&i2s3_2ch {
pinctrl-0 = <&i2s3m0_sclk &i2s3m0_lrck &i2s3m0_sdi &i2s3m0_sdo>;
rockchip,bclk-fs = <32>;
status = "disabled";
};
&iep { &iep {
status = "okay"; status = "okay";
}; };
@ -1458,6 +1483,12 @@
&pinctrl { &pinctrl {
headphone {
hp_det: hp-det {
rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
mxc6655xa { mxc6655xa {
mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { mxc6655xa_irq_gpio: mxc6655xa_irq_gpio {
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
@ -1819,8 +1850,8 @@
&vop { &vop {
status = "okay"; status = "okay";
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>;
}; };
&vop_mmu { &vop_mmu {

9
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-dual-camera.dts Normal file
View File

@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3568-evb1-ddr4-v10.dtsi"
#include "rk3568-android.dtsi"
#include "rk3568-evb1-dual-camera.dtsi"

28
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-linux-amp.dts Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3568-evb1-ddr4-v10-linux.dts"
#include "rk3568-amp.dtsi"
/ {
memory {
device_type = "memory";
reg = <0x0 0x03880000 0x0 0x04b80000>,
<0x0 0x0a200000 0x0 0x75e00000>;
};
};
&cpu1 {
status = "disabled";
};
&cpu2 {
status = "disabled";
};
&cpu3 {
status = "disabled";
};

12
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dts
View File

@ -6,3 +6,15 @@
#include "rk3568-evb1-ddr4-v10.dtsi" #include "rk3568-evb1-ddr4-v10.dtsi"
#include "rk3568-android.dtsi" #include "rk3568-android.dtsi"
&bt_sco {
status = "okay";
};
&bt_sound {
status = "okay";
};
&i2s3_2ch {
status = "okay";
};

16
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi
View File

@ -15,13 +15,6 @@
model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
compatible = "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568"; compatible = "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568";
rk_headset: rk-headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
};
vcc2v5_sys: vcc2v5-ddr { vcc2v5_sys: vcc2v5-ddr {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "vcc2v5-sys"; regulator-name = "vcc2v5-sys";
@ -399,6 +392,10 @@
}; };
}; };
&rk809_sound {
hp-det-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
};
&rkisp { &rkisp {
status = "okay"; status = "okay";
}; };
@ -426,6 +423,11 @@
connect = <&vp1_out_dsi0>; connect = <&vp1_out_dsi0>;
}; };
&route_edp {
status = "okay";
connect = <&vp0_out_edp>;
};
&sata2 { &sata2 {
status = "okay"; status = "okay";
}; };

247
arch/arm64/boot/dts/rockchip/rk3568-evb1-dual-camera.dtsi Normal file
View File

@ -0,0 +1,247 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
&csi2_dphy_hw {
status = "okay";
};
/*
* csi2_dphy1 & csi2_dphy2 used for split mode,
* csi2_dphy0 used for full mode,
* full mode and split mode are mutually exclusive
*/
&csi2_dphy0 {
status = "disabled";
/delete-node/ ports;
};
&csi2_dphy1 {
status = "okay";
/*
* dphy1 only used for split mode,
* can be used concurrently with dphy2
* full mode and split mode are mutually exclusive
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_gc2093_rgb: endpoint@2 {
reg = <2>;
remote-endpoint = <&gc2093_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy1_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
&csi2_dphy2 {
status = "okay";
/*
* dphy2 only used for split mode,
* can be used concurrently with dphy1
* full mode and split mode are mutually exclusive
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_gc2053_ir: endpoint@1 {
reg = <1>;
remote-endpoint = <&gc2053_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy2_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp_in1>;
};
};
};
};
&mipi_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&dphy1_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
data-lanes = <1 2>;
};
};
};
};
&i2c4 {
status = "okay";
/delete-node/ gc8034@37;
/delete-node/ os04a10@36;
/delete-node/ ov5695@36;
gc2053: gc2053@37 {
status = "okay";
compatible = "galaxycore,gc2053";
reg = <0x37>;
clocks = <&pmucru CLK_WIFI>;
clock-names = "xvclk";
power-domains = <&power RK3568_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&refclk_pins>;
reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "DW-RV2093-V1.0";
rockchip,camera-module-lens-name = "JZ-7070AS-A3";
port {
gc2053_out: endpoint {
remote-endpoint = <&mipi_in_gc2053_ir>;
data-lanes = <1 2>;
};
};
};
gc2093: gc2093@7e {
status = "okay";
compatible = "galaxycore,gc2093";
reg = <0x7e>;
clocks = <&cru CLK_CIF_OUT>;
clock-names = "xvclk";
power-domains = <&power RK3568_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cif_clk>;
reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "DW-RV2093-V1.0";
rockchip,camera-module-lens-name = "JZ-7070AS-A1";
port {
gc2093_out: endpoint {
remote-endpoint = <&mipi_in_gc2093_rgb>;
data-lanes = <1 2>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
port {
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
data-lanes = <1 2>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_in2>;
data-lanes = <1 2>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&rkisp {
status = "okay";
max-input = <3840 2160 30>;
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
/* gc2053-ir->dphy2->isp_vir0 */
port {
#address-cells = <1>;
#size-cells = <0>;
isp_in1: endpoint@0 {
reg = <0>;
remote-endpoint = <&dphy2_out>;
};
};
};
&rkisp_vir1 {
status = "okay";
/* gc2093-rgb->dphy1->csi2->vicap */
/* vicap sditf->isp_vir1 */
port {
#address-cells = <1>;
#size-cells = <0>;
isp_in2: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};

13
arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi
View File

@ -72,6 +72,13 @@
}; };
}; };
&bt_sound {
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&i2s2_2ch>;
};
};
&combphy0_us { &combphy0_us {
status = "okay"; status = "okay";
}; };
@ -219,6 +226,12 @@
status = "disabled"; status = "disabled";
}; };
&i2s2_2ch {
pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>;
rockchip,bclk-fs = <32>;
status = "disabled";
};
&mdio1 { &mdio1 {
qsgmii_phy0: phy@0 { qsgmii_phy0: phy@0 {
compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22";

25
arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi
View File

@ -84,16 +84,19 @@
}; };
}; };
&bt_sound {
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&i2s2_2ch>;
};
};
&combphy0_us { &combphy0_us {
status = "okay"; status = "okay";
}; };
&combphy1_usq {
rockchip,sgmii-mac-sel = <0>;
status = "okay";
};
&combphy2_psq { &combphy2_psq {
rockchip,sgmii-mac-sel = <0>;
status = "okay"; status = "okay";
}; };
@ -216,7 +219,7 @@
pinctrl-0 = <&gmac0_miim>; pinctrl-0 = <&gmac0_miim>;
power-domains = <&power RK3568_PD_PIPE>; power-domains = <&power RK3568_PD_PIPE>;
phys = <&combphy1_usq PHY_TYPE_SGMII>; phys = <&combphy2_psq PHY_TYPE_SGMII>;
phy-handle = <&sgmii_phy>; phy-handle = <&sgmii_phy>;
status = "okay"; status = "okay";
@ -360,6 +363,12 @@
status = "disabled"; status = "disabled";
}; };
&i2s2_2ch {
pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>;
rockchip,bclk-fs = <32>;
status = "disabled";
};
&mdio0 { &mdio0 {
sgmii_phy: phy@1 { sgmii_phy: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
@ -473,10 +482,6 @@
connect = <&vp1_out_dsi0>; connect = <&vp1_out_dsi0>;
}; };
&sata2 {
status = "okay";
};
&sdmmc2 { &sdmmc2 {
max-frequency = <150000000>; max-frequency = <150000000>;
supports-sdio; supports-sdio;

13
arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi
View File

@ -50,6 +50,13 @@
}; };
}; };
&bt_sound {
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&i2s2_2ch>;
};
};
&combphy0_us { &combphy0_us {
status = "okay"; status = "okay";
}; };
@ -235,6 +242,12 @@
/delete-node/ mxc6655xa@15; /delete-node/ mxc6655xa@15;
}; };
&i2s2_2ch {
pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>;
rockchip,bclk-fs = <32>;
status = "disabled";
};
&csi2_dphy_hw { &csi2_dphy_hw {
status = "okay"; status = "okay";
}; };

42
arch/arm64/boot/dts/rockchip/rk3568-linux.dtsi
View File

@ -5,6 +5,13 @@
*/ */
/ { / {
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc0;
mmc2 = &sdmmc1;
mmc3 = &sdmmc2;
};
chosen: chosen { chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
}; };
@ -37,22 +44,6 @@
<0x0 0xfd90e000 0x0 0x1000>, <0x0 0xfd90e000 0x0 0x1000>,
<0x0 0xfd90f000 0x0 0x1000>; <0x0 0xfd90f000 0x0 0x1000>;
}; };
rk809_sound: rk809-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,hp-det-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
simple-audio-card,name = "rockchip,rk809-codec";
simple-audio-card,widgets = "Headphones", "Headphones Jack";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809_codec>;
};
};
}; };
&reserved_memory { &reserved_memory {
@ -66,25 +57,6 @@
}; };
}; };
&rk809_codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
clocks = <&cru I2S1_MCLKOUT>;
clock-names = "mclk";
assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
assigned-clock-rates = <12288000>;
assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_mclk &hp_det>;
hp-volume = <20>;
spk-volume = <3>;
status = "okay";
};
&rk_headset {
status = "disabled";
};
&rng { &rng {
status = "okay"; status = "okay";
}; };

30
arch/arm64/boot/dts/rockchip/rk3568-nvr-demo-v10.dtsi
View File

@ -35,7 +35,7 @@
compatible = "simple-audio-card"; compatible = "simple-audio-card";
simple-audio-card,format = "i2s"; simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>; simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,i2s1-sound"; simple-audio-card,name = "rockchip-i2s1";
simple-audio-card,cpu { simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>; sound-dai = <&i2s1_8ch>;
}; };
@ -44,6 +44,16 @@
}; };
}; };
rk618_hdmi_sound: rk618-hdmi-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,card-name = "rk618-hdmi";
rockchip,cpu = <&spdif_8ch>;
rockchip,codec = <&rk618_hdmi>;
rockchip,jack-det;
};
vcc2v5_sys: vcc2v5-ddr { vcc2v5_sys: vcc2v5-ddr {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "vcc2v5-sys"; regulator-name = "vcc2v5-sys";
@ -230,7 +240,7 @@
status = "okay"; status = "okay";
}; };
hdmi { rk618_hdmi: hdmi {
compatible = "rockchip,rk618-hdmi"; compatible = "rockchip,rk618-hdmi";
clocks = <&clock HDMI_CLK>; clocks = <&clock HDMI_CLK>;
clock-names = "hdmi"; clock-names = "hdmi";
@ -238,6 +248,8 @@
assigned-clock-parents = <&clock VIF0_CLK>; assigned-clock-parents = <&clock VIF0_CLK>;
interrupt-parent = <&gpio0>; interrupt-parent = <&gpio0>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
rockchip,format = "spdif";
#sound-dai-cells = <0>;
status = "okay"; status = "okay";
ports { ports {
@ -420,6 +432,20 @@
status = "okay"; status = "okay";
}; };
&spdif_out {
status = "disabled";
};
&spdif_sound {
status = "disabled";
};
&spdif_8ch {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spdifm1_tx>;
};
&pinctrl { &pinctrl {
rk618 { rk618 {
rk618_reset: rk618-reeset { rk618_reset: rk618-reeset {

21
arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi
View File

@ -42,24 +42,19 @@
}; };
hdmi_sound: hdmi-sound { hdmi_sound: hdmi-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <128>;
simple-audio-card,name = "hdmi-sound";
status = "okay"; status = "okay";
compatible = "rockchip,hdmi";
simple-audio-card,cpu { rockchip,mclk-fs = <128>;
sound-dai = <&i2s0_8ch>; rockchip,card-name = "rockchip-hdmi0";
}; rockchip,cpu = <&i2s0_8ch>;
simple-audio-card,codec { rockchip,codec = <&hdmi>;
sound-dai = <&hdmi>; rockchip,jack-det;
};
}; };
spdif-sound { spdif_sound: spdif-sound {
status = "okay"; status = "okay";
compatible = "simple-audio-card"; compatible = "simple-audio-card";
simple-audio-card,name = "ROCKCHIP,SPDIF"; simple-audio-card,name = "ROCKCHIP-SPDIF";
simple-audio-card,cpu { simple-audio-card,cpu {
sound-dai = <&spdif_8ch>; sound-dai = <&spdif_8ch>;
}; };

332
arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
View File

File diff suppressed because it is too large Load Diff

297
arch/arm64/boot/dts/rockchip/rk3568.dtsi
View File

@ -126,12 +126,14 @@
opp-shared; opp-shared;
mbist-vmin = <825000 900000 950000>; mbist-vmin = <825000 900000 950000>;
nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>; nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>;
nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
rockchip,max-volt = <1150000>;
rockchip,pvtm-voltage-sel = < rockchip,pvtm-voltage-sel = <
0 84000 0 0 84000 0
84001 91000 1 84001 87000 1
91001 100000 2 87001 91000 2
91001 100000 3
>; >;
rockchip,pvtm-freq = <408000>; rockchip,pvtm-freq = <408000>;
rockchip,pvtm-volt = <900000>; rockchip,pvtm-volt = <900000>;
@ -146,31 +148,22 @@
rockchip,low-temp = <0>; rockchip,low-temp = <0>;
rockchip,low-temp-adjust-volt = < rockchip,low-temp-adjust-volt = <
/* MHz MHz uV */ /* MHz MHz uV */
0 1608 75000 0 1992 75000
>; >;
opp-408000000 { opp-408000000 {
opp-hz = /bits/ 64 <408000000>; opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <850000 850000 1150000>; opp-microvolt = <850000 850000 1150000>;
opp-microvolt-L0 = <850000 850000 1150000>;
opp-microvolt-L1 = <825000 825000 1150000>;
opp-microvolt-L2 = <825000 825000 1150000>;
clock-latency-ns = <40000>; clock-latency-ns = <40000>;
}; };
opp-600000000 { opp-600000000 {
opp-hz = /bits/ 64 <600000000>; opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <850000 825000 1150000>; opp-microvolt = <850000 850000 1150000>;
opp-microvolt-L0 = <850000 850000 1150000>;
opp-microvolt-L1 = <825000 825000 1150000>;
opp-microvolt-L2 = <825000 825000 1150000>;
clock-latency-ns = <40000>; clock-latency-ns = <40000>;
}; };
opp-816000000 { opp-816000000 {
opp-hz = /bits/ 64 <816000000>; opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <850000 850000 1150000>; opp-microvolt = <850000 850000 1150000>;
opp-microvolt-L0 = <850000 850000 1150000>;
opp-microvolt-L1 = <825000 825000 1150000>;
opp-microvolt-L2 = <825000 825000 1150000>;
clock-latency-ns = <40000>; clock-latency-ns = <40000>;
opp-suspend; opp-suspend;
}; };
@ -178,40 +171,45 @@
opp-hz = /bits/ 64 <1104000000>; opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <900000 900000 1150000>; opp-microvolt = <900000 900000 1150000>;
opp-microvolt-L0 = <900000 900000 1150000>; opp-microvolt-L0 = <900000 900000 1150000>;
opp-microvolt-L1 = <825000 825000 1150000>; opp-microvolt-L1 = <850000 850000 1150000>;
opp-microvolt-L2 = <825000 825000 1150000>; opp-microvolt-L2 = <850000 850000 1150000>;
opp-microvolt-L3 = <850000 850000 1150000>;
clock-latency-ns = <40000>; clock-latency-ns = <40000>;
}; };
opp-1416000000 { opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>; opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1000000 1000000 1150000>; opp-microvolt = <1025000 1025000 1150000>;
opp-microvolt-L0 = <1000000 1000000 1150000>; opp-microvolt-L0 = <1025000 1025000 1150000>;
opp-microvolt-L1 = <925000 925000 1150000>; opp-microvolt-L1 = <975000 975000 1150000>;
opp-microvolt-L2 = <925000 925000 1150000>; opp-microvolt-L2 = <950000 950000 1150000>;
opp-microvolt-L3 = <925000 925000 1150000>;
clock-latency-ns = <40000>; clock-latency-ns = <40000>;
}; };
opp-1608000000 { opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>; opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1075000 1075000 1150000>; opp-microvolt = <1100000 1100000 1150000>;
opp-microvolt-L0 = <1075000 1075000 1150000>; opp-microvolt-L0 = <1100000 1100000 1150000>;
opp-microvolt-L1 = <1000000 1000000 1150000>; opp-microvolt-L1 = <1050000 1050000 1150000>;
opp-microvolt-L2 = <1000000 1000000 1150000>; opp-microvolt-L2 = <1025000 1025000 1150000>;
opp-microvolt-L3 = <1000000 1000000 1150000>;
clock-latency-ns = <40000>; clock-latency-ns = <40000>;
}; };
opp-1800000000 { opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>; opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1125000 1125000 1150000>; opp-microvolt = <1150000 1150000 1150000>;
opp-microvolt-L0 = <1125000 1125000 1150000>; opp-microvolt-L0 = <1150000 1150000 1150000>;
opp-microvolt-L1 = <1050000 1050000 1150000>; opp-microvolt-L1 = <1100000 1100000 1150000>;
opp-microvolt-L2 = <1050000 1050000 1150000>; opp-microvolt-L2 = <1075000 1075000 1150000>;
opp-microvolt-L3 = <1050000 1050000 1150000>;
clock-latency-ns = <40000>; clock-latency-ns = <40000>;
}; };
opp-1992000000 { opp-1992000000 {
opp-hz = /bits/ 64 <1992000000>; opp-hz = /bits/ 64 <1992000000>;
opp-microvolt = <1150000 1150000 1150000>; opp-microvolt = <1150000 1150000 1150000>;
opp-microvolt-L0 = <1150000 1150000 1150000>; opp-microvolt-L0 = <1150000 1150000 1150000>;
opp-microvolt-L1 = <1100000 1100000 1150000>; opp-microvolt-L1 = <1150000 1150000 1150000>;
opp-microvolt-L2 = <1075000 1075000 1150000>; opp-microvolt-L2 = <1125000 1125000 1150000>;
opp-microvolt-L3 = <1100000 1100000 1150000>;
clock-latency-ns = <40000>; clock-latency-ns = <40000>;
}; };
}; };
@ -307,7 +305,7 @@
reg = <0x14>; reg = <0x14>;
#clock-cells = <1>; #clock-cells = <1>;
rockchip,clk-init = <1416000000>; rockchip,clk-init = <1104000000>;
}; };
}; };
@ -354,7 +352,7 @@
| RKPM_SLP_ARMOFF_LOGOFF | RKPM_SLP_ARMOFF_LOGOFF
| RKPM_SLP_CENTER_OFF | RKPM_SLP_CENTER_OFF
| RKPM_SLP_HW_PLLS_OFF | RKPM_SLP_HW_PLLS_OFF
// | RKPM_SLP_PMUALIVE_32K | RKPM_SLP_PMUALIVE_32K
| RKPM_SLP_OSC_DIS | RKPM_SLP_OSC_DIS
| RKPM_SLP_PMIC_LP | RKPM_SLP_PMIC_LP
| RKPM_SLP_32K_PVTM | RKPM_SLP_32K_PVTM
@ -589,7 +587,7 @@
snps,dis-tx-ipgap-linecheck-quirk; snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk; snps,dis_rxdet_inp3_quirk;
snps,xhci-trb-ent-quirk; snps,xhci-trb-ent-quirk;
snps,usb2-lpm-disable; quirk-skip-phy-init;
status = "disabled"; status = "disabled";
}; };
}; };
@ -622,7 +620,6 @@
snps,dis-tx-ipgap-linecheck-quirk; snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk; snps,dis_rxdet_inp3_quirk;
snps,xhci-trb-ent-quirk; snps,xhci-trb-ent-quirk;
snps,usb2-lpm-disable;
status = "disabled"; status = "disabled";
}; };
}; };
@ -1111,76 +1108,70 @@
compatible = "operating-points-v2"; compatible = "operating-points-v2";
mbist-vmin = <825000 900000 950000>; mbist-vmin = <825000 900000 950000>;
nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>; nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>;
nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
rockchip,max-volt = <1000000>;
rockchip,temp-hysteresis = <5000>; rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>; rockchip,low-temp = <0>;
rockchip,low-temp-adjust-volt = < rockchip,low-temp-adjust-volt = <
/* MHz MHz uV */ /* MHz MHz uV */
0 700 50000 0 1000 50000
>; >;
rockchip,pvtm-voltage-sel = < rockchip,pvtm-voltage-sel = <
0 84000 0 0 84000 0
84001 91000 1 84001 87000 1
91001 100000 2 87001 91000 2
91001 100000 3
>; >;
rockchip,pvtm-ch = <0 5>; rockchip,pvtm-ch = <0 5>;
opp-200000000 { opp-200000000 {
opp-hz = /bits/ 64 <200000000>; opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <850000 850000 1000000>; opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <850000 850000 1000000>;
opp-microvolt-L1 = <825000 825000 1000000>;
opp-microvolt-L2 = <825000 825000 1000000>;
}; };
opp-300000000 { opp-300000000 {
opp-hz = /bits/ 64 <297000000>; opp-hz = /bits/ 64 <297000000>;
opp-microvolt = <850000 850000 1000000>; opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <850000 850000 1000000>;
opp-microvolt-L1 = <825000 825000 1000000>;
opp-microvolt-L2 = <825000 825000 1000000>;
}; };
opp-400000000 { opp-400000000 {
opp-hz = /bits/ 64 <400000000>; opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <850000 850000 1000000>; opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <850000 850000 1000000>;
opp-microvolt-L1 = <825000 825000 1000000>;
opp-microvolt-L2 = <825000 825000 1000000>;
}; };
opp-600000000 { opp-600000000 {
opp-hz = /bits/ 64 <600000000>; opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <875000 875000 1000000>; opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <875000 875000 1000000>;
opp-microvolt-L1 = <825000 825000 1000000>;
opp-microvolt-L2 = <825000 825000 1000000>;
}; };
opp-700000000 { opp-700000000 {
opp-hz = /bits/ 64 <700000000>; opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <900000 900000 1000000>; opp-microvolt = <875000 875000 1000000>;
opp-microvolt-L0 = <900000 900000 1000000>; opp-microvolt-L0 = <875000 875000 1000000>;
opp-microvolt-L1 = <850000 850000 1000000>; opp-microvolt-L1 = <850000 850000 1000000>;
opp-microvolt-L2 = <850000 850000 1000000>; opp-microvolt-L2 = <850000 850000 1000000>;
opp-microvolt-L3 = <850000 850000 1000000>;
}; };
opp-800000000 { opp-800000000 {
opp-hz = /bits/ 64 <800000000>; opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <925000 925000 1000000>; opp-microvolt = <925000 925000 1000000>;
opp-microvolt-L0 = <925000 925000 1000000>; opp-microvolt-L0 = <925000 925000 1000000>;
opp-microvolt-L1 = <875000 875000 1000000>; opp-microvolt-L1 = <900000 900000 1000000>;
opp-microvolt-L2 = <875000 875000 1000000>; opp-microvolt-L2 = <875000 875000 1000000>;
opp-microvolt-L3 = <875000 875000 1000000>;
}; };
opp-900000000 { opp-900000000 {
opp-hz = /bits/ 64 <900000000>; opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <975000 975000 1000000>; opp-microvolt = <975000 975000 1000000>;
opp-microvolt-L0 = <975000 975000 1000000>; opp-microvolt-L0 = <975000 975000 1000000>;
opp-microvolt-L1 = <925000 925000 1000000>; opp-microvolt-L1 = <950000 950000 1000000>;
opp-microvolt-L2 = <900000 900000 1000000>; opp-microvolt-L2 = <925000 925000 1000000>;
opp-microvolt-L3 = <900000 900000 1000000>;
}; };
opp-1000000000 { opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>; opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1000000 1000000 1000000>; opp-microvolt = <1000000 1000000 1000000>;
opp-microvolt-L0 = <1000000 1000000 1000000>; opp-microvolt-L0 = <1000000 1000000 1000000>;
opp-microvolt-L1 = <950000 950000 1000000>; opp-microvolt-L1 = <975000 975000 1000000>;
opp-microvolt-L2 = <925000 925000 1000000>; opp-microvolt-L2 = <950000 950000 1000000>;
opp-microvolt-L3 = <925000 925000 1000000>;
status = "disabled"; status = "disabled";
}; };
}; };
@ -1209,7 +1200,10 @@
opp-700000000 { opp-700000000 {
opp-hz = /bits/ 64 <700000000>; opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <0>; opp-microvolt = <900000>;
opp-microvolt-L0 = <900000>;
opp-microvolt-L1 = <875000>;
opp-microvolt-L2 = <875000>;
}; };
opp-900000000 { opp-900000000 {
opp-hz = /bits/ 64 <900000000>; opp-hz = /bits/ 64 <900000000>;
@ -1220,7 +1214,7 @@
opp-microvolt = <950000>; opp-microvolt = <950000>;
opp-microvolt-L0 = <950000>; opp-microvolt-L0 = <950000>;
opp-microvolt-L1 = <925000>; opp-microvolt-L1 = <925000>;
opp-microvolt-L2 = <0>; opp-microvolt-L2 = <900000>;
}; };
}; };
@ -1270,56 +1264,58 @@
compatible = "operating-points-v2"; compatible = "operating-points-v2";
mbist-vmin = <825000 900000 950000>; mbist-vmin = <825000 900000 950000>;
nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>; nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>;
nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
rockchip,max-volt = <1000000>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>;
rockchip,low-temp-adjust-volt = <
/* MHz MHz uV */
0 800 50000
>;
rockchip,pvtm-voltage-sel = < rockchip,pvtm-voltage-sel = <
0 84000 0 0 84000 0
84001 91000 1 84001 87000 1
91001 100000 2 87001 91000 2
91001 100000 3
>; >;
rockchip,pvtm-ch = <0 5>; rockchip,pvtm-ch = <0 5>;
opp-200000000 { opp-200000000 {
opp-hz = /bits/ 64 <200000000>; opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <850000>; opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <850000>;
opp-microvolt-L1 = <825000>;
opp-microvolt-L2 = <825000>;
}; };
opp-300000000 { opp-300000000 {
opp-hz = /bits/ 64 <300000000>; opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <850000>; opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <850000>;
opp-microvolt-L1 = <825000>;
opp-microvolt-L2 = <825000>;
}; };
opp-400000000 { opp-400000000 {
opp-hz = /bits/ 64 <400000000>; opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <850000>; opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <850000>;
opp-microvolt-L1 = <825000>;
opp-microvolt-L2 = <825000>;
}; };
opp-600000000 { opp-600000000 {
opp-hz = /bits/ 64 <600000000>; opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <875000>; opp-microvolt = <900000 900000 1000000>;
opp-microvolt-L0 = <875000>; opp-microvolt-L0 = <900000 900000 1000000>;
opp-microvolt-L1 = <825000>; opp-microvolt-L1 = <875000 875000 1000000>;
opp-microvolt-L2 = <825000>; opp-microvolt-L2 = <850000 850000 1000000>;
opp-microvolt-L3 = <850000 850000 1000000>;
}; };
opp-700000000 { opp-700000000 {
opp-hz = /bits/ 64 <700000000>; opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <950000>; opp-microvolt = <950000 950000 1000000>;
opp-microvolt-L0 = <950000>; opp-microvolt-L0 = <950000 950000 1000000>;
opp-microvolt-L1 = <900000>; opp-microvolt-L1 = <925000 925000 1000000>;
opp-microvolt-L2 = <850000>; opp-microvolt-L2 = <900000 900000 1000000>;
opp-microvolt-L3 = <875000 875000 1000000>;
}; };
opp-800000000 { opp-800000000 {
opp-hz = /bits/ 64 <800000000>; opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1000000>; opp-microvolt = <1000000 1000000 1000000>;
opp-microvolt-L0 = <1000000>; opp-microvolt-L0 = <1000000 1000000 1000000>;
opp-microvolt-L1 = <950000>; opp-microvolt-L1 = <975000 975000 1000000>;
opp-microvolt-L2 = <900000>; opp-microvolt-L2 = <950000 950000 1000000>;
opp-microvolt-L3 = <925000 925000 1000000>;
}; };
}; };
@ -1379,6 +1375,7 @@
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
power-domains = <&power RK3568_PD_VPU>; power-domains = <&power RK3568_PD_VPU>;
rockchip,shootdown-entire;
#iommu-cells = <0>; #iommu-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -1431,6 +1428,7 @@
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
power-domains = <&power RK3568_PD_RGA>; power-domains = <&power RK3568_PD_RGA>;
rockchip,shootdown-entire;
#iommu-cells = <0>; #iommu-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -1460,6 +1458,7 @@
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
power-domains = <&power RK3568_PD_RGA>; power-domains = <&power RK3568_PD_RGA>;
rockchip,shootdown-entire;
#iommu-cells = <0>; #iommu-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -1490,6 +1489,7 @@
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&power RK3568_PD_RGA>; power-domains = <&power RK3568_PD_RGA>;
rockchip,shootdown-entire;
//rockchip,disable-device-link-resume; //rockchip,disable-device-link-resume;
status = "disabled"; status = "disabled";
}; };
@ -1541,14 +1541,17 @@
opp-297000000 { opp-297000000 {
opp-hz = /bits/ 64 <297000000>; opp-hz = /bits/ 64 <297000000>;
opp-microvolt = <0>; opp-microvolt = <900000>;
opp-microvolt-L0 = <900000>;
opp-microvolt-L1 = <875000>;
opp-microvolt-L2 = <875000>;
}; };
opp-400000000 { opp-400000000 {
opp-hz = /bits/ 64 <400000000>; opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <950000>; opp-microvolt = <950000>;
opp-microvolt-L0 = <950000>; opp-microvolt-L0 = <950000>;
opp-microvolt-L1 = <925000>; opp-microvolt-L1 = <925000>;
opp-microvolt-L2 = <0>; opp-microvolt-L2 = <900000>;
}; };
}; };
@ -1562,6 +1565,7 @@
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
rockchip,disable-mmu-reset; rockchip,disable-mmu-reset;
rockchip,enable-cmd-retry; rockchip,enable-cmd-retry;
rockchip,shootdown-entire;
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&power RK3568_PD_RKVENC>; power-domains = <&power RK3568_PD_RKVENC>;
status = "disabled"; status = "disabled";
@ -1609,9 +1613,23 @@
rkvdec_opp_table: rkvdec-opp-table { rkvdec_opp_table: rkvdec-opp-table {
compatible = "operating-points-v2"; compatible = "operating-points-v2";
nvmem-cells = <&log_leakage>, <&core_pvtm>;
nvmem-cell-names = "leakage", "pvtm";
rockchip,leakage-voltage-sel = <
1 80 0
81 254 1
>;
rockchip,pvtm-voltage-sel = <
0 84000 0
84001 100000 1
>;
rockchip,pvtm-ch = <0 5>;
opp-297000000 { opp-297000000 {
opp-hz = /bits/ 64 <297000000>; opp-hz = /bits/ 64 <297000000>;
opp-microvolt = <0>; opp-microvolt = <900000>;
opp-microvolt-L0 = <900000>;
opp-microvolt-L1 = <875000>;
}; };
opp-400000000 { opp-400000000 {
opp-hz = /bits/ 64 <400000000>; opp-hz = /bits/ 64 <400000000>;
@ -1627,6 +1645,7 @@
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
power-domains = <&power RK3568_PD_RKVDEC>; power-domains = <&power RK3568_PD_RKVDEC>;
rockchip,shootdown-entire;
#iommu-cells = <0>; #iommu-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -1721,7 +1740,7 @@
rockchip,grf = <&grf>; rockchip,grf = <&grf>;
power-domains = <&power RK3568_PD_VI>; power-domains = <&power RK3568_PD_VI>;
iommus = <&rkisp_mmu>; iommus = <&rkisp_mmu>;
rockchip,iq-feature = /bits/ 64 <0x3FBFFFE67FF>; rockchip,iq-feature = /bits/ 64 <0x1BFBFFFE67FF>;
status = "disabled"; status = "disabled";
}; };
@ -1750,6 +1769,13 @@
status = "disabled"; status = "disabled";
}; };
gmac_uio0: uio@fe2a0000 {
compatible = "rockchip,uio-gmac";
reg = <0x0 0xfe2a0000 0x0 0x10000>;
rockchip,ethernet = <&gmac0>;
status = "disabled";
};
gmac0: ethernet@fe2a0000 { gmac0: ethernet@fe2a0000 {
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe2a0000 0x0 0x10000>; reg = <0x0 0xfe2a0000 0x0 0x10000>;
@ -1761,12 +1787,12 @@
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
<&cru PCLK_XPCS>; <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
clock-names = "stmmaceth", "mac_clk_rx", clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_refout", "mac_clk_tx", "clk_mac_refout",
"aclk_mac", "pclk_mac", "aclk_mac", "pclk_mac",
"clk_mac_speed", "ptp_ref", "clk_mac_speed", "ptp_ref",
"pclk_xpcs"; "pclk_xpcs", "clk_xpcs_eee";
resets = <&cru SRST_A_GMAC0>; resets = <&cru SRST_A_GMAC0>;
reset-names = "stmmaceth"; reset-names = "stmmaceth";
@ -1801,6 +1827,13 @@
}; };
}; };
gmac_uio1: uio@fe010000 {
compatible = "rockchip,uio-gmac";
reg = <0x0 0xfe010000 0x0 0x10000>;
rockchip,ethernet = <&gmac1>;
status = "disabled";
};
gmac1: ethernet@fe010000 { gmac1: ethernet@fe010000 {
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe010000 0x0 0x10000>; reg = <0x0 0xfe010000 0x0 0x10000>;
@ -1812,12 +1845,12 @@
<&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
<&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
<&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>, <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
<&cru PCLK_XPCS>; <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
clock-names = "stmmaceth", "mac_clk_rx", clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_refout", "mac_clk_tx", "clk_mac_refout",
"aclk_mac", "pclk_mac", "aclk_mac", "pclk_mac",
"clk_mac_speed", "ptp_ref", "clk_mac_speed", "ptp_ref",
"pclk_xpcs"; "pclk_xpcs", "clk_xpcs_eee";
resets = <&cru SRST_A_GMAC1>; resets = <&cru SRST_A_GMAC1>;
reset-names = "stmmaceth"; reset-names = "stmmaceth";
@ -2038,7 +2071,8 @@
hdmi: hdmi@fe0a0000 { hdmi: hdmi@fe0a0000 {
compatible = "rockchip,rk3568-dw-hdmi"; compatible = "rockchip,rk3568-dw-hdmi";
reg = <0x0 0xfe0a0000 0x0 0x20000>; reg = <0x0 0xfe0a0000 0x0 0x20000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hdmi", "hdmi_wakeup";
clocks = <&cru PCLK_HDMI_HOST>, clocks = <&cru PCLK_HDMI_HOST>,
<&cru CLK_HDMI_SFR>, <&cru CLK_HDMI_SFR>,
<&cru CLK_HDMI_CEC>, <&cru CLK_HDMI_CEC>,
@ -2357,8 +2391,9 @@
compatible = "operating-points-v2"; compatible = "operating-points-v2";
mbist-vmin = <825000 900000 950000>; mbist-vmin = <825000 900000 950000>;
nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>; nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>;
nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
rockchip,max-volt = <1000000>;
rockchip,temp-hysteresis = <5000>; rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>; rockchip,low-temp = <0>;
rockchip,low-temp-adjust-volt = < rockchip,low-temp-adjust-volt = <
@ -2377,9 +2412,9 @@
opp-1560000000 { opp-1560000000 {
opp-hz = /bits/ 64 <1560000000>; opp-hz = /bits/ 64 <1560000000>;
opp-microvolt = <900000>; opp-microvolt = <900000 900000 1000000>;
opp-microvolt-L0 = <900000>; opp-microvolt-L0 = <900000 900000 1000000>;
opp-microvolt-L1 = <850000>; opp-microvolt-L1 = <875000 875000 1000000>;
}; };
}; };
@ -2679,6 +2714,39 @@
core_pvtm:core-pvtm@2a { core_pvtm:core-pvtm@2a {
reg = <0x2a 0x2>; reg = <0x2a 0x2>;
}; };
cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e {
reg = <0x2e 0x1>;
};
cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f {
reg = <0x2f 0x1>;
bits = <0 4>;
};
gpu_tsadc_trim_l: npu-tsadc-trim-l@30 {
reg = <0x30 0x1>;
};
gpu_tsadc_trim_h: npu-tsadc-trim-h@31 {
reg = <0x31 0x1>;
bits = <0 4>;
};
tsadc_trim_base_frac: tsadc-trim-base-frac@31 {
reg = <0x31 0x1>;
bits = <4 4>;
};
tsadc_trim_base: tsadc-trim-base@32 {
reg = <0x32 0x1>;
};
cpu_opp_info: cpu-opp-info@36 {
reg = <0x36 0x6>;
};
gpu_opp_info: gpu-opp-info@3c {
reg = <0x3c 0x6>;
};
npu_opp_info: npu-opp-info@42 {
reg = <0x42 0x6>;
};
dmc_opp_info: dmc-opp-info@48 {
reg = <0x48 0x6>;
};
}; };
i2s0_8ch: i2s@fe400000 { i2s0_8ch: i2s@fe400000 {
@ -2877,7 +2945,7 @@
}; };
can0: can@fe570000 { can0: can@fe570000 {
compatible = "rockchip,canfd-1.0"; compatible = "rockchip,rk3568-can-2.0";
reg = <0x0 0xfe570000 0x0 0x1000>; reg = <0x0 0xfe570000 0x0 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
@ -2890,7 +2958,7 @@
}; };
can1: can@fe580000 { can1: can@fe580000 {
compatible = "rockchip,canfd-1.0"; compatible = "rockchip,rk3568-can-2.0";
reg = <0x0 0xfe580000 0x0 0x1000>; reg = <0x0 0xfe580000 0x0 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
@ -2903,7 +2971,7 @@
}; };
can2: can@fe590000 { can2: can@fe590000 {
compatible = "rockchip,canfd-1.0"; compatible = "rockchip,rk3568-can-2.0";
reg = <0x0 0xfe590000 0x0 0x1000>; reg = <0x0 0xfe590000 0x0 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
@ -3338,13 +3406,28 @@
<&cru SRST_TSADCPHY>; <&cru SRST_TSADCPHY>;
reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
nvmem-cells = <&tsadc_trim_base>, <&tsadc_trim_base_frac>;
nvmem-cell-names = "trim_base", "trim_base_frac";
rockchip,hw-tshut-temp = <120000>; rockchip,hw-tshut-temp = <120000>;
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
pinctrl-names = "gpio", "otpout"; pinctrl-names = "gpio", "otpout";
pinctrl-0 = <&tsadc_gpio_func>; pinctrl-0 = <&tsadc_gpio_func>;
pinctrl-1 = <&tsadc_shutorg>; pinctrl-1 = <&tsadc_shutorg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; status = "disabled";
tsadc@0 {
reg = <0>;
nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>;
nvmem-cell-names = "trim_l", "trim_h";
};
tsadc@1 {
reg = <1>;
nvmem-cells = <&gpu_tsadc_trim_l>, <&gpu_tsadc_trim_h>;
nvmem-cell-names = "trim_l", "trim_h";
};
}; };
saradc: saradc@fe720000 { saradc: saradc@fe720000 {

608
arch/arm64/boot/dts/rockchip/rk3568j-core-ddr4-v10.dts Normal file
View File

@ -0,0 +1,608 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3568j.dtsi"
/ {
model = "Rockchip RK3568J CORE DDR4 V10 Board";
compatible = "rockchip,rk3568j-core-ddr4-v10", "rockchip,rk3568";
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
};
fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <2>;
rockchip,wake-irq = <0>;
/* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <1>;
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
debug: debug@fd904000 {
compatible = "rockchip,debug";
reg = <0x0 0xfd904000 0x0 0x1000>,
<0x0 0xfd905000 0x0 0x1000>,
<0x0 0xfd906000 0x0 0x1000>,
<0x0 0xfd907000 0x0 0x1000>;
};
cspmu: cspmu@fd90c000 {
compatible = "rockchip,cspmu";
reg = <0x0 0xfd90c000 0x0 0x1000>,
<0x0 0xfd90d000 0x0 0x1000>,
<0x0 0xfd90e000 0x0 0x1000>,
<0x0 0xfd90f000 0x0 0x1000>;
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
};
vcc5v0_otg: vcc5v0-otg-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_otg_en>;
};
};
&can1 {
assigned-clocks = <&cru CLK_CAN1>;
assigned-clock-rates = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&can1m1_pins>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&dfi {
status = "okay";
};
&dmc {
center-supply = <&vdd_logic>;
status = "okay";
};
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&gmac1_clkin {
clock-frequency = <50000000>;
};
&gmac1 {
phy-mode = "rmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RMII_SPEED>, <&gmac1_clkin>;
assigned-clock-rates = <0>, <50000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m0_miim
&gmac1m0_clkinout
&gmac1m0_tx_bus2
&gmac1m0_rx_bus2>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&i2c0 {
status = "okay";
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
//fb-inner-reg-idxs = <2>;
/* 1: rst regs (default in codes), 0: rst the pmic */
pmic-reset-func = <0>;
/* not save the PMIC_POWER_EN register in uboot */
not-save-power-en = <1>;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
pwrkey {
status = "okay";
};
pinctrl_rk8xx: pinctrl_rk8xx {
gpio-controller;
#gpio-cells = <2>;
rk817_slppin_null: rk817_slppin_null {
pins = "gpio_slp";
function = "pin_fun0";
};
rk817_slppin_slp: rk817_slppin_slp {
pins = "gpio_slp";
function = "pin_fun1";
};
rk817_slppin_pwrdn: rk817_slppin_pwrdn {
pins = "gpio_slp";
function = "pin_fun2";
};
rk817_slppin_rst: rk817_slppin_rst {
pins = "gpio_slp";
function = "pin_fun3";
};
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_cpu";
regulator-state-mem {
regulator-off-iemmcn-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_buck4: DCDC_REG4 {
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_buck4";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda_0v9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca_1v8: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ldo3: LDO_REG3 {
regulator-name = "vcc_ldo3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ldo5: LDO_REG5 {
regulator-name = "vcc_ldo5";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ldo6: LDO_REG6 {
regulator-name = "vcc_ldo6";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ldo7: LDO_REG7 {
regulator-name = "vcc_ldo7";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ldo8: LDO_REG8 {
regulator-name = "vcc_ldo8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ldo9: LDO_REG9 {
regulator-name = "vcc_ldo9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sys: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_sys";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_sw1: SWITCH_REG1 {
regulator-name = "vcc_sw1";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_3v3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&i2c1 {
status = "okay";
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4m1_xfer>;
status = "okay";
};
&i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5m1_xfer>;
status = "okay";
};
&mdio0 {
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
&mdio1 {
rgmii_phy1: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
&pinctrl {
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
soc_slppin_gpio: soc_slppin_gpio {
rockchip,pins =
<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>;
};
soc_slppin_slp: soc_slppin_slp {
rockchip,pins =
<0 RK_PA2 1 &pcfg_pull_up>;
};
soc_slppin_rst: soc_slppin_rst {
rockchip,pins =
<0 RK_PA2 2 &pcfg_pull_none>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_otg_en: vcc5v0-otg-en {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
status = "okay";
pmuio2-supply = <&vcc_3v3>;
vccio1-supply = <&vcc_3v3>;
vccio3-supply = <&vcc_3v3>;
vccio4-supply = <&vcc_3v3>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_3v3>;
vccio7-supply = <&vcc_3v3>;
};
&pwm3 {
status = "okay";
};
&pwm4 {
status = "okay";
};
&pwm14 {
pinctrl-0 = <&pwm14m1_pins>;
status = "okay";
};
&pwm15 {
pinctrl-0 = <&pwm15m1_pins>;
status = "okay";
};
&reserved_memory {
ramoops: ramoops@110000 {
compatible = "ramoops";
reg = <0x0 0x110000 0x0 0xf0000>;
record-size = <0x20000>;
console-size = <0x80000>;
ftrace-size = <0x00000>;
pmsg-size = <0x50000>;
};
};
&rng {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcca_1v8>;
};
&sdhci {
bus-width = <8>;
supports-emmc;
non-removable;
max-frequency = <200000000>;
status = "okay";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi1m1_cs0 &spi1m0_cs1 &spi1m1_pins>;
pinctrl-1 = <&spi1m1_cs0 &spi1m0_cs1 &spi1m1_pins_hs>;
};
&spi2 {
status = "okay";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins>;
pinctrl-1 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins_hs>;
};
&tsadc {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart4 {
status = "okay";
};
&uart5 {
status = "okay";
};
&uart6 {
status = "okay";
pinctrl-0 = <&uart6m1_xfer>;
};
&uart9 {
status = "okay";
pinctrl-0 = <&uart9m1_xfer>;
};
&u2phy0_otg {
vbus-supply = <&vcc5v0_otg>;
status = "okay";
};
&u2phy1_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy1_otg {
vbus-supply = <&vcc5v0_host>;
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd_dwc3 {
extcon = <&usb2phy0>;
phys = <&u2phy0_otg>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
status = "okay";
};
&usbdrd30 {
status = "okay";
};

120
arch/arm64/boot/dts/rockchip/rk3568j.dtsi Normal file
View File

@ -0,0 +1,120 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3568.dtsi"
&cru {
/* remove PLL_NPLL and ACLK_VOP */
assigned-clocks =
<&pmucru CLK_RTC_32K>, <&cru ACLK_RKVDEC_PRE>,
<&cru CLK_RKVDEC_CORE>, <&pmucru PLL_PPLL>,
<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
<&cru CPLL_500M>, <&cru CPLL_333M>,
<&cru CPLL_250M>, <&cru CPLL_125M>,
<&cru CPLL_100M>, <&cru CPLL_62P5M>,
<&cru CPLL_50M>, <&cru CPLL_25M>,
<&cru PLL_GPLL>,
<&cru ACLK_BUS>, <&cru PCLK_BUS>,
<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
<&cru HCLK_TOP>, <&cru PCLK_TOP>,
<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
<&cru ACLK_PIPE>,
<&cru PCLK_PIPE>, <&cru CLK_I2S0_8CH_TX_SRC>,
<&cru CLK_I2S0_8CH_RX_SRC>, <&cru CLK_I2S1_8CH_TX_SRC>,
<&cru CLK_I2S1_8CH_RX_SRC>, <&cru CLK_I2S2_2CH_SRC>,
<&cru CLK_I2S2_2CH_SRC>, <&cru CLK_I2S3_2CH_RX_SRC>,
<&cru CLK_I2S3_2CH_TX_SRC>, <&cru MCLK_SPDIF_8CH_SRC>;
assigned-clock-rates =
<32768>, <300000000>,
<300000000>, <200000000>,
<100000000>, <1000000000>,
<500000000>, <333000000>,
<250000000>, <125000000>,
<100000000>, <62500000>,
<50000000>, <25000000>,
<1188000000>,
<150000000>, <100000000>,
<500000000>, <400000000>,
<150000000>, <100000000>,
<300000000>, <150000000>,
<400000000>,
<100000000>, <1188000000>,
<1188000000>, <1188000000>,
<1188000000>, <1188000000>,
<1188000000>, <1188000000>,
<1188000000>, <1188000000>;
assigned-clock-parents =
<&pmucru CLK_RTC32K_FRAC>, <&cru PLL_GPLL>,
<&cru PLL_GPLL>;
};
&cpu0_opp_table {
/delete-node/ mbist-vmin;
/delete-node/ opp-408000000;
/delete-node/ opp-600000000;
/delete-node/ opp-816000000;
/delete-node/ opp-1104000000;
/delete-node/ opp-1416000000;
/delete-node/ opp-1608000000;
/delete-node/ opp-1800000000;
/delete-node/ opp-1992000000;
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <900000 900000 900000>;
clock-latency-ns = <40000>;
};
};
&display_subsystem {
status = "disabled";
};
&dmc {
system-status-level = <
/*system status freq level*/
SYS_STATUS_NORMAL DMC_FREQ_LEVEL_HIGH
>;
auto-freq-en = <0>;
};
&dmc_opp_table {
/delete-node/ mbist-vmin;
/delete-node/ opp-1560000000;
opp-780000000 {
opp-hz = /bits/ 64 <780000000>;
opp-microvolt = <875000>;
};
};
&gpu_opp_table {
/delete-node/ mbist-vmin;
/delete-node/ opp-200000000;
/delete-node/ opp-300000000;
/delete-node/ opp-400000000;
/delete-node/ opp-600000000;
/delete-node/ opp-700000000;
/delete-node/ opp-800000000;
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <900000>;
};
};
&npu_opp_table {
/delete-node/ mbist-vmin;
/delete-node/ opp-200000000;
/delete-node/ opp-300000000;
/delete-node/ opp-400000000;
/delete-node/ opp-600000000;
/delete-node/ opp-700000000;
/delete-node/ opp-800000000;
/delete-node/ opp-900000000;
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <900000 900000 900000>;
};
};

20
arch/arm64/configs/lubancat2_defconfig
View File

@ -303,6 +303,7 @@ CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_TI is not set # CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_MOTORCOMM_PHY=y
CONFIG_LED_TRIGGER_PHY=y CONFIG_LED_TRIGGER_PHY=y
CONFIG_JLSEMI_PHY=y CONFIG_JLSEMI_PHY=y
CONFIG_ROCKCHIP_PHY=y CONFIG_ROCKCHIP_PHY=y
@ -534,11 +535,12 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set # CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_PWM=y
CONFIG_ROCKCHIP_RGA2=y CONFIG_ROCKCHIP_MULTI_RGA=y
CONFIG_ROCKCHIP_MPP_SERVICE=y CONFIG_ROCKCHIP_MPP_SERVICE=y
CONFIG_ROCKCHIP_MPP_RKVDEC=y CONFIG_ROCKCHIP_MPP_RKVDEC=y
CONFIG_ROCKCHIP_MPP_RKVDEC2=y CONFIG_ROCKCHIP_MPP_RKVDEC2=y
CONFIG_ROCKCHIP_MPP_RKVENC=y CONFIG_ROCKCHIP_MPP_RKVENC=y
CONFIG_ROCKCHIP_MPP_RKVENC2=y
CONFIG_ROCKCHIP_MPP_VDPU1=y CONFIG_ROCKCHIP_MPP_VDPU1=y
CONFIG_ROCKCHIP_MPP_VEPU1=y CONFIG_ROCKCHIP_MPP_VEPU1=y
CONFIG_ROCKCHIP_MPP_VDPU2=y CONFIG_ROCKCHIP_MPP_VDPU2=y
@ -548,6 +550,7 @@ CONFIG_ROCKCHIP_MPP_JPGDEC=y
CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
CONFIG_ROCKCHIP_MPP_VDPP=y
CONFIG_SOUND=y CONFIG_SOUND=y
CONFIG_SND=y CONFIG_SND=y
CONFIG_SND_HRTIMER=y CONFIG_SND_HRTIMER=y
@ -562,6 +565,7 @@ CONFIG_SND_SOC=y
CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
CONFIG_SND_SOC_ROCKCHIP_PDM=y CONFIG_SND_SOC_ROCKCHIP_PDM=y
CONFIG_SND_SOC_ROCKCHIP_SAI=y
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
CONFIG_SND_SOC_ROCKCHIP_MAX98090=y CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
@ -651,6 +655,11 @@ CONFIG_RTC_DRV_RK808=y
CONFIG_RTC_DRV_RX8010=y CONFIG_RTC_DRV_RX8010=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_PL330_DMA=y CONFIG_PL330_DMA=y
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_HEAPS_DEFERRED_FREE=y
CONFIG_DMABUF_HEAPS_PAGE_POOL=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
CONFIG_STAGING=y CONFIG_STAGING=y
CONFIG_FIQ_DEBUGGER=y CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
@ -661,8 +670,12 @@ CONFIG_RK_CONSOLE_THREAD=y
CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_SCMI=y
CONFIG_MAILBOX=y CONFIG_MAILBOX=y
CONFIG_ROCKCHIP_MBOX=y
CONFIG_ROCKCHIP_IOMMU=y CONFIG_ROCKCHIP_IOMMU=y
CONFIG_RPMSG_ROCKCHIP=y
CONFIG_RPMSG_VIRTIO=y
CONFIG_CPU_RK3568=y CONFIG_CPU_RK3568=y
CONFIG_ROCKCHIP_AMP=y
CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ROCKCHIP_PVTM=y CONFIG_ROCKCHIP_PVTM=y
CONFIG_ROCKCHIP_SUSPEND_MODE=y CONFIG_ROCKCHIP_SUSPEND_MODE=y
@ -676,9 +689,6 @@ CONFIG_ARM_ROCKCHIP_DMC_DEBUG=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=y CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=y
CONFIG_MEMORY=y CONFIG_MEMORY=y
CONFIG_IIO=y CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGER=y
CONFIG_ROCKCHIP_SARADC=y CONFIG_ROCKCHIP_SARADC=y
CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29018=y
CONFIG_SENSORS_TSL2563=y CONFIG_SENSORS_TSL2563=y
@ -778,6 +788,8 @@ CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0 CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0
CONFIG_HARDLOCKUP_DETECTOR=y
# CONFIG_DETECT_HUNG_TASK is not set
CONFIG_SCHEDSTATS=y CONFIG_SCHEDSTATS=y
CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_CREDENTIALS=y CONFIG_DEBUG_CREDENTIALS=y

5
arch/arm64/configs/px30_linux_defconfig
View File

@ -365,9 +365,6 @@ CONFIG_ARM_ROCKCHIP_DMC_DEBUG=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=y CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=y
CONFIG_MEMORY=y CONFIG_MEMORY=y
CONFIG_IIO=y CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGER=y
CONFIG_ROCKCHIP_SARADC=y CONFIG_ROCKCHIP_SARADC=y
CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29018=y
CONFIG_SENSORS_TSL2563=y CONFIG_SENSORS_TSL2563=y
@ -403,6 +400,8 @@ CONFIG_TMPFS_POSIX_ACL=y
CONFIG_SQUASHFS=y CONFIG_SQUASHFS=y
CONFIG_PSTORE=y CONFIG_PSTORE=y
CONFIG_PSTORE_CONSOLE=y CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_FTRACE=y
CONFIG_PSTORE_RAM=y CONFIG_PSTORE_RAM=y
CONFIG_NFS_FS=y CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y CONFIG_NFS_V3_ACL=y

17
arch/arm64/configs/rk3326_linux.config
View File

@ -1,26 +1,13 @@
# CONFIG_ETHERNET is not set # CONFIG_ETHERNET is not set
CONFIG_MD=y CONFIG_MD=y
CONFIG_PSTORE=y
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set # CONFIG_ROCKCHIP_ANALOGIX_DP is not set
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
CONFIG_SND_SOC_ROCKCHIP_MULTI_DAIS=y CONFIG_SND_SOC_ROCKCHIP_MULTI_DAIS=y
CONFIG_SND_SOC_ROCKCHIP_PDM=y
CONFIG_USB_CONFIGFS_F_MTP=y
CONFIG_VIDEO_GC2155=y CONFIG_VIDEO_GC2155=y
CONFIG_VIDEO_ROCKCHIP_CIF=y CONFIG_VIDEO_ROCKCHIP_CIF=y
# CONFIG_BCACHE is not set # CONFIG_BCACHE is not set
# CONFIG_BLK_DEV_DM is not set # CONFIG_BLK_DEV_DM is not set
# CONFIG_BLK_DEV_MD is not set # CONFIG_BLK_DEV_MD is not set
# CONFIG_DPM_WATCHDOG is not set CONFIG_ROCKCHIP_CIF_USE_DUMMY_BUF=y
CONFIG_PSTORE_CONSOLE=y # CONFIG_ROCKCHIP_CIF_USE_NONE_DUMMY_BUF is not set
# CONFIG_PSTORE_FTRACE is not set
# CONFIG_PSTORE_PMSG is not set
CONFIG_PSTORE_RAM=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_REED_SOLOMON_ENC8=y
# CONFIG_ROCKCHIP_CIF_WORKMODE_ONEFRAME is not set # CONFIG_ROCKCHIP_CIF_WORKMODE_ONEFRAME is not set
CONFIG_ROCKCHIP_CIF_WORKMODE_PINGPONG=y CONFIG_ROCKCHIP_CIF_WORKMODE_PINGPONG=y
# CONFIG_USB_CONFIGFS_F_PTP is not set
CONFIG_USB_F_MTP=y
CONFIG_ZLIB_DEFLATE=y

13
arch/arm64/configs/rk3358_linux.config
View File

@ -1,2 +1,15 @@
# CONFIG_ETHERNET is not set
CONFIG_LTE=y CONFIG_LTE=y
CONFIG_MD=y
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
CONFIG_SND_SOC_ROCKCHIP_MULTI_DAIS=y
CONFIG_VIDEO_GC2155=y
CONFIG_VIDEO_ROCKCHIP_CIF=y
# CONFIG_BCACHE is not set
# CONFIG_BLK_DEV_DM is not set
# CONFIG_BLK_DEV_MD is not set
CONFIG_LTE_RM310=y CONFIG_LTE_RM310=y
CONFIG_ROCKCHIP_CIF_USE_DUMMY_BUF=y
# CONFIG_ROCKCHIP_CIF_USE_NONE_DUMMY_BUF is not set
# CONFIG_ROCKCHIP_CIF_WORKMODE_ONEFRAME is not set
CONFIG_ROCKCHIP_CIF_WORKMODE_PINGPONG=y

65
arch/arm64/configs/rk3528_box.config Normal file
View File

@ -0,0 +1,65 @@
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_CHARGER_BQ25700 is not set
# CONFIG_CPU_PX30 is not set
# CONFIG_CPU_RK3328 is not set
# CONFIG_CPU_RK3368 is not set
# CONFIG_CPU_RK3399 is not set
# CONFIG_CPU_RK3568 is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP_V1 is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP_V2 is not set
# CONFIG_DRM_ROCKCHIP_RK618 is not set
# CONFIG_DRM_ROCKCHIP_RK628 is not set
# CONFIG_FUSB_30X is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_LEDS_RGB13H is not set
# CONFIG_MALI_BIFROST is not set
# CONFIG_MALI_MIDGARD is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_DIO5632 is not set
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_REGULATOR_LP8752 is not set
# CONFIG_REGULATOR_MP8865 is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_XZ3216 is not set
# CONFIG_RK_NAND is not set
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
# CONFIG_ROCKCHIP_CDN_DP is not set
# CONFIG_ROCKCHIP_CLK_BOOST is not set
# CONFIG_ROCKCHIP_DDRCLK_SIP is not set
# CONFIG_ROCKCHIP_DW_MIPI_DSI is not set
# CONFIG_ROCKCHIP_INNO_HDMI is not set
# CONFIG_ROCKCHIP_LVDS is not set
# CONFIG_ROCKCHIP_PLL_RK3066 is not set
# CONFIG_ROCKCHIP_PLL_RK3399 is not set
# CONFIG_ROCKCHIP_RGB is not set
# CONFIG_ROCKCHIP_RKNPU is not set
# CONFIG_ROCKCHIP_VOP is not set
# CONFIG_SENSOR_DEVICE is not set
# CONFIG_VIDEO_DW9714 is not set
# CONFIG_VIDEO_GC0312 is not set
# CONFIG_VIDEO_GC032A is not set
# CONFIG_VIDEO_GC2053 is not set
# CONFIG_VIDEO_GC2093 is not set
# CONFIG_VIDEO_GC2145 is not set
# CONFIG_VIDEO_GC2355 is not set
# CONFIG_VIDEO_GC2385 is not set
# CONFIG_VIDEO_GC4C33 is not set
# CONFIG_VIDEO_GC8034 is not set
# CONFIG_VIDEO_LT6911UXC is not set
# CONFIG_VIDEO_LT8619C is not set
# CONFIG_VIDEO_OV13850 is not set
# CONFIG_VIDEO_OV2680 is not set
# CONFIG_VIDEO_OV5648 is not set
# CONFIG_VIDEO_OV5695 is not set
# CONFIG_VIDEO_OV8858 is not set
# CONFIG_VIDEO_RK628_CSI is not set
# CONFIG_VIDEO_ROCKCHIP_ISP is not set
# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
# CONFIG_VIDEO_SGM3784 is not set
# CONFIG_VIDEO_TC35874X is not set
# CONFIG_VIDEO_VM149C is not set
CONFIG_VLAN_8021Q=y
# CONFIG_BRIDGE_VLAN_FILTERING is not set
# CONFIG_VLAN_8021Q_GVRP is not set
# CONFIG_VLAN_8021Q_MVRP is not set

136
arch/arm64/configs/rk3568j.config Normal file
View File

@ -0,0 +1,136 @@
# CONFIG_ALLOW_DEV_COREDUMP is not set
# CONFIG_ARM64_CRYPTO is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
# CONFIG_BT is not set
# CONFIG_CAVIUM_ERRATUM_27456 is not set
# CONFIG_CAVIUM_ERRATUM_30115 is not set
# CONFIG_CFG80211 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_PX30 is not set
# CONFIG_CPU_RK1808 is not set
# CONFIG_CPU_RK3328 is not set
# CONFIG_CPU_RK3399 is not set
# CONFIG_CRC7 is not set
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC_ITU_T is not set
# CONFIG_CRC_T10DIF is not set
CONFIG_CRYPTO_AEAD=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_CFB is not set
# CONFIG_CRYPTO_CMAC is not set
# CONFIG_CRYPTO_CRCT10DIF is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
CONFIG_CRYPTO_DRBG=m
CONFIG_CRYPTO_DRBG_MENU=m
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_ECDH is not set
CONFIG_CRYPTO_ECHAINIV=m
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_GF128MUL is not set
# CONFIG_CRYPTO_GHASH is not set
CONFIG_CRYPTO_HMAC=m
CONFIG_CRYPTO_JITTERENTROPY=m
CONFIG_CRYPTO_MANAGER=m
# CONFIG_CRYPTO_MD5 is not set
CONFIG_CRYPTO_NULL=m
# CONFIG_CRYPTO_OFB is not set
CONFIG_CRYPTO_RNG=m
CONFIG_CRYPTO_RNG_DEFAULT=m
# CONFIG_CRYPTO_RSA is not set
# CONFIG_CRYPTO_SEQIV is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
# CONFIG_DRM is not set
# CONFIG_FB is not set
# CONFIG_FUSB_30X is not set
# CONFIG_HIDRAW is not set
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HISILICON_ERRATUM_161600802 is not set
# CONFIG_I2C_HID is not set
# CONFIG_I2C_MUX is not set
# CONFIG_INPUT_MATRIXKMAP is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_IPV6 is not set
# CONFIG_KEYS is not set
# CONFIG_LEDS_TRIGGERS is not set
# CONFIG_MALI400 is not set
# CONFIG_MALI_BIFROST is not set
# CONFIG_MALI_MIDGARD is not set
# CONFIG_MEDIA_SUPPORT is not set
# CONFIG_MFD_CROS_EC is not set
# CONFIG_MFD_RK618 is not set
# CONFIG_MFD_RK628 is not set
# CONFIG_MFD_RK630 is not set
# CONFIG_MFD_RK630_I2C is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MMC_TEST is not set
# CONFIG_MOUSE_CYAPA is not set
# CONFIG_MOUSE_ELAN_I2C is not set
# CONFIG_MTD is not set
# CONFIG_NET_KEY is not set
# CONFIG_NFS_FS is not set
# CONFIG_PHY_ROCKCHIP_DP is not set
# CONFIG_PHY_ROCKCHIP_INNO_HDMI_PHY is not set
# CONFIG_PHY_ROCKCHIP_INNO_MIPI_DPHY is not set
# CONFIG_PHY_ROCKCHIP_INNO_VIDEO_COMBO_PHY is not set
# CONFIG_PHY_ROCKCHIP_NANENG_EDP is not set
# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_DEBUG is not set
# CONFIG_REGULATOR_LP8752 is not set
# CONFIG_REGULATOR_MP8865 is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_XZ3216 is not set
# CONFIG_RK630_PHY is not set
# CONFIG_RK_FLASH is not set
# CONFIG_RK_HEADSET is not set
# CONFIG_ROCKCHIP_CLK_BOOST is not set
# CONFIG_ROCKCHIP_DDRCLK_SIP is not set
# CONFIG_ROCKCHIP_EFUSE is not set
# CONFIG_ROCKCHIP_MPP_SERVICE is not set
# CONFIG_ROCKCHIP_PLL_RK3399 is not set
# CONFIG_ROCKCHIP_RGA2 is not set
# CONFIG_SATA_AHCI is not set
# CONFIG_SATA_AHCI_PLATFORM is not set
# CONFIG_SDIO_KEEPALIVE is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SENSORS_ISL29018 is not set
# CONFIG_SENSORS_TSL2563 is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
# CONFIG_SOUND is not set
# CONFIG_SYNC_FILE is not set
# CONFIG_TCG_TPM is not set
# CONFIG_TSL2583 is not set
# CONFIG_UHID is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HIDDEV is not set
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_WDM is not set
# CONFIG_WL_ROCKCHIP is not set
# CONFIG_XFRM_USER is not set

15
arch/arm64/configs/rockchip_defconfig
View File

@ -356,6 +356,7 @@ CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_TI is not set # CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_MOTORCOMM_PHY=y
CONFIG_ROCKCHIP_PHY=y CONFIG_ROCKCHIP_PHY=y
CONFIG_RK630_PHY=y CONFIG_RK630_PHY=y
CONFIG_PPP=y CONFIG_PPP=y
@ -581,6 +582,8 @@ CONFIG_VIDEO_OV8858=y
CONFIG_VIDEO_OV13850=y CONFIG_VIDEO_OV13850=y
CONFIG_VIDEO_GC0312=y CONFIG_VIDEO_GC0312=y
CONFIG_VIDEO_GC032A=y CONFIG_VIDEO_GC032A=y
CONFIG_VIDEO_GC2053=y
CONFIG_VIDEO_GC2093=y
CONFIG_VIDEO_GC2145=y CONFIG_VIDEO_GC2145=y
CONFIG_VIDEO_GC2355=y CONFIG_VIDEO_GC2355=y
CONFIG_VIDEO_GC2385=y CONFIG_VIDEO_GC2385=y
@ -636,12 +639,14 @@ CONFIG_ROCKCHIP_MPP_SERVICE=y
CONFIG_ROCKCHIP_MPP_RKVDEC=y CONFIG_ROCKCHIP_MPP_RKVDEC=y
CONFIG_ROCKCHIP_MPP_RKVDEC2=y CONFIG_ROCKCHIP_MPP_RKVDEC2=y
CONFIG_ROCKCHIP_MPP_RKVENC=y CONFIG_ROCKCHIP_MPP_RKVENC=y
CONFIG_ROCKCHIP_MPP_RKVENC2=y
CONFIG_ROCKCHIP_MPP_VDPU1=y CONFIG_ROCKCHIP_MPP_VDPU1=y
CONFIG_ROCKCHIP_MPP_VEPU1=y CONFIG_ROCKCHIP_MPP_VEPU1=y
CONFIG_ROCKCHIP_MPP_VDPU2=y CONFIG_ROCKCHIP_MPP_VDPU2=y
CONFIG_ROCKCHIP_MPP_VEPU2=y CONFIG_ROCKCHIP_MPP_VEPU2=y
CONFIG_ROCKCHIP_MPP_IEP2=y CONFIG_ROCKCHIP_MPP_IEP2=y
CONFIG_ROCKCHIP_MPP_JPGDEC=y CONFIG_ROCKCHIP_MPP_JPGDEC=y
CONFIG_ROCKCHIP_MPP_VDPP=y
CONFIG_SOUND=y CONFIG_SOUND=y
CONFIG_SND=y CONFIG_SND=y
CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_DYNAMIC_MINORS=y
@ -655,6 +660,7 @@ CONFIG_SND_SOC=y
CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
CONFIG_SND_SOC_ROCKCHIP_PDM=y CONFIG_SND_SOC_ROCKCHIP_PDM=y
CONFIG_SND_SOC_ROCKCHIP_SAI=y
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
CONFIG_SND_SOC_ROCKCHIP_RT5651=y CONFIG_SND_SOC_ROCKCHIP_RT5651=y
@ -669,6 +675,7 @@ CONFIG_SND_SOC_ES8311=y
CONFIG_SND_SOC_ES8316=y CONFIG_SND_SOC_ES8316=y
CONFIG_SND_SOC_ES8396=y CONFIG_SND_SOC_ES8396=y
CONFIG_SND_SOC_RK3328=y CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK3528=y
CONFIG_SND_SOC_RK817=y CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RK_CODEC_DIGITAL=y CONFIG_SND_SOC_RK_CODEC_DIGITAL=y
CONFIG_SND_SOC_RT5640=y CONFIG_SND_SOC_RT5640=y
@ -808,6 +815,11 @@ CONFIG_RTC_DRV_RK808=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_PL330_DMA=y CONFIG_PL330_DMA=y
CONFIG_SW_SYNC=y CONFIG_SW_SYNC=y
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_HEAPS_DEFERRED_FREE=y
CONFIG_DMABUF_HEAPS_PAGE_POOL=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
CONFIG_STAGING=y CONFIG_STAGING=y
CONFIG_ASHMEM=y CONFIG_ASHMEM=y
CONFIG_ION=y CONFIG_ION=y
@ -833,6 +845,7 @@ CONFIG_CPU_PX30=y
CONFIG_CPU_RK3328=y CONFIG_CPU_RK3328=y
CONFIG_CPU_RK3368=y CONFIG_CPU_RK3368=y
CONFIG_CPU_RK3399=y CONFIG_CPU_RK3399=y
CONFIG_CPU_RK3528=y
CONFIG_CPU_RK3568=y CONFIG_CPU_RK3568=y
CONFIG_ANDROID_VERSION=0x08000000 CONFIG_ANDROID_VERSION=0x08000000
CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ROCKCHIP_PM_DOMAINS=y
@ -933,7 +946,7 @@ CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ=y
CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_HARDLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
CONFIG_PANIC_TIMEOUT=5 CONFIG_PANIC_TIMEOUT=5
CONFIG_SCHEDSTATS=y CONFIG_SCHEDSTATS=y

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