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merge into: RTOS:Branch_Develop
Branches Tags
RTOS:Trunk RTOS:Develop_Eval-CMT2310_868 RTOS:Develop_Eval-CMT2310 RTOS:Branch_Develop_Eval-CMT2310 RTOS:Branch_Develop_Eval RTOS:Branch_Develop
...
pull from: RTOS:Develop_Eval-CMT2310
Branches Tags
RTOS:Develop_Eval-CMT2310_868 RTOS:Develop_Eval-CMT2310 RTOS:Branch_Develop_Eval-CMT2310 RTOS:Branch_Develop_Eval RTOS:Branch_Develop RTOS:Trunk

44 Commits
Branch_Dev ... Develop_Ev

Author SHA1 Message Date
gaoyang3513
8862e54265 [Mod] 使用NCVI->ICER 清除所有已使用的中断 2024-08-02 21:04:24 +08:00
gaoyang3513
b7c27bc14f [Mod] CMT2310 跳转前切换至Standby，成功免初始化 
1. 新增Standby切换入口；
2. ping接收打印优化；
 2024-08-02 19:53:56 +08:00
gaoyang3513
293d9b3be1 [Mod] 优化systick 退出实现 2024-08-02 19:16:53 +08:00
gaoyang3513
d587362102 [Mod] 完善退出流程 2024-08-02 19:04:30 +08:00
gaoyang3513
d0892c2256 [Mod] Ebyte退出，Systick_deinit 2024-08-02 17:24:42 +08:00
gaoyang3513
aa36ca5d96 [Mod] 调整systick初始化位置 2024-08-02 16:29:54 +08:00
gaoyang3513
711f15677d [Mod] 支持发送ping命令控制跳转 2024-08-02 16:19:58 +08:00
gaoyang3513
6337bafb99 [Fix] 解决串口打印错误问题 
1. 待优化：使用snprintf格式化，但长度限定为32，与128有差距；
2. 开启Timer；
3. 解决字符串的串口打印错误；
 2024-08-02 10:42:56 +08:00
gaoyang3513
0a96026659 [Mod] 支持CMT2310 接收 
1. 关联gd32w51x中断处理；
  1.1. 支持基于SysTick的延时；
  1.2. 支持基于Timer2中断的数据接收；
2. 解决程序过大问题，链接中移除printf的浮点支持；
3. 支持CMT2310初始化并进入接收模式；
  3.1. 支持HAL层替换打印EBYTE_LOG；
 2024-08-01 20:42:42 +08:00
gaoyang3513
cdb997cc8a [Mod] 未加入调用，编译通过 2024-08-01 13:58:42 +08:00
gaoyang3513
f35fba223c [Add] NBL 新增CMT2310 驱动 2024-08-01 11:44:58 +08:00
gaoyang3513
762b604ba6 [Mod] 优化方案 支持bootm 跳转至MBL 2024-08-01 11:34:35 +08:00
gaoyang3513
eacd045dfd [Mod] 按优化方案修改，完整初始化正常 2024-08-01 10:17:12 +08:00
gaoyang3513
2ea3d7e844 [Mod] 文件目录调整 +3 新增CMT2310目录 2024-07-31 20:51:10 +08:00
gaoyang3513
c9defe4bc5 [Mod] 文档更新 
1. 更新readme
 2024-07-31 20:46:25 +08:00
gaoyang3513
35d5e78a6d [Mod] 文件目录调整 +2 重命名readme文档 2024-07-31 20:44:43 +08:00
gaoyang3513
9eab78d648 [Mod] 中断调整 引用cmt2310下的回调 
1. 中断必须在gd_it.c中定义，否则可能卡死；
2. 中断处理中再调用CMT2310 中断处理；
 2024-07-31 20:42:14 +08:00
gaoyang3513
8fab7d67c4 [Mod] 文件目录调整 +1 删除空余文件或目录 2024-07-31 19:56:24 +08:00
gaoyang3513
1b7f3c470d [Mod] 文件目录调整 转unix文件 2024-07-31 19:11:21 +08:00
gaoyang3513
473660f75a [Mod] 支持按键发送 
1. 全开启main
 2024-07-31 18:32:25 +08:00
gaoyang3513
ce1f140584 [Mod] 支持按键发送 
1. 启用Timer中断(周期1ms)，以支持按键状态获取；
 2024-07-29 23:56:12 +08:00
gaoyang3513
e0900f9b73 [Mod] CMT2310 初始化完成 
1. 使用系统延时实现硬件抽象层us、ms延时；
2. 完成SPI初始化、收发实现；
 2024-07-25 20:35:55 +08:00
gaoyang3513
bb7b6e452b [Fix] 解决启动崩溃问题 
Timer时钟使能，入参错误导致地址访问的硬件错误
 2024-07-25 18:55:45 +08:00
gaoyang3513
f135363861 [Mod] 禁用led_task， 与CMT2310 冲突 2024-07-25 18:22:39 +08:00
gaoyang3513
48bc218fb1 [Mod] CMT2310 GPIO SPI初始化 2024-07-25 18:21:42 +08:00
gaoyang3513
47725a5b15 [Mod] 启用顺序打印 2024-07-24 23:40:24 +08:00
gaoyang3513
94bc1e6d21 [Mod] sub1g_task 置空 2024-07-24 23:12:37 +08:00
gaoyang3513
951fa34fad [Mod] 解决链接异常问题 2024-07-24 23:01:39 +08:00
gaoyang3513
7625fd6912 [Mod] 调整Cmake产物到output目录下 2024-07-24 00:05:46 +08:00
gaoyang3513
8b6fe7ef86 [Mod] 解决GCC版本，串口无法接收问题 2024-07-24 00:05:14 +08:00
gaoyang3513
d39d11abad [Mod] 解决编译错误 2024-07-23 22:03:19 +08:00
gaoyang3513
e1549ed7f3 [Bak] 备份 驱动移植 23.07.22 2024-07-22 23:30:05 +08:00
gaoyang3513
ad41b080e9 [Mod] CMakelist 添加模块 2024-07-22 23:00:52 +08:00
gaoyang3513
e71ca26d50 [Mod] 修改工具链为：gcc-arm-none-eabi-9-2020-q2-update 2024-07-22 20:17:45 +08:00
gaoyang3513
2c317efbcd [Add] 添加E48 测试用例 2024-07-21 21:18:32 +08:00
gaoyang3513
f453b08452 [Mod] 暂存，LED、fscan非中断 2023-06-18 15:59:15 +00:00
gaoyang3513
f4ac7db357 [修改] Keil工程支持MDK5 
[详细说明]
    1. 兼容MDK4、MDK5编译；
    2. NSPE 增加自定义内容
        2.1. 增加开关宏： CONFIG_GY3513；
        2.2. 增加EVAL板定义集；
 2023-06-15 16:26:54 +00:00
gaoyang3513
6503e589b4 [修改] bat脚本与exe工具增加可执行权限 2023-06-15 16:13:40 +00:00
gaoyang3513
58a63c59fb [修改] 忽略Keil工程中间产物 2023-06-15 16:11:08 +00:00
gaoyang3513
ada62165a6 [修改] 更新Readme说明 2023-06-14 16:03:01 +00:00
gaoyang3513
853a9461a0 [修改] 增加CONFIG_GY3513定制内容 
[详细说明]
    1. 增加LED任务；
    2. 修复LED3配置错误问题；
 2023-06-14 16:01:34 +00:00
gaoyang3513
242a8865ae [修改] VSCode工程 clang插件相关配置 2023-06-14 16:00:40 +00:00
gaoyang3513
3ca2c491d5 [Mod] 修改目标单板 EVAL 2023-06-13 16:38:23 +00:00
gaoyang3513
a389b906af [修改] 支持clangd插件 2023-06-13 16:37:59 +00:00
126 changed files with 25120 additions and 6955 deletions
Expand all files Collapse all files

192
.clang-format Normal file
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@ -0,0 +1,192 @@
---
Language: Cpp
# BasedOnStyle: WebKit
AccessModifierOffset: -4
AlignAfterOpenBracket: DontAlign
AlignArrayOfStructures: None
AlignConsecutiveMacros: None
AlignConsecutiveAssignments: None
AlignConsecutiveBitFields: None
AlignConsecutiveDeclarations: None
AlignEscapedNewlines: Right
AlignOperands: DontAlign
AlignTrailingComments: false
AllowAllArgumentsOnNextLine: true
AllowAllParametersOfDeclarationOnNextLine: true
AllowShortEnumsOnASingleLine: true
AllowShortBlocksOnASingleLine: Empty
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: All
AllowShortLambdasOnASingleLine: All
AllowShortIfStatementsOnASingleLine: Never
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: MultiLine
AttributeMacros:
- __capability
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterCaseLabel: false
AfterClass: false
AfterControlStatement: Never
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AfterFunction: true
AfterNamespace: false
AfterObjCDeclaration: false
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AfterUnion: false
AfterExternBlock: false
BeforeCatch: false
BeforeElse: false
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BeforeWhile: false
IndentBraces: false
SplitEmptyFunction: true
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakBeforeBinaryOperators: All
BreakBeforeConceptDeclarations: true
BreakBeforeBraces: WebKit
BreakBeforeInheritanceComma: false
BreakInheritanceList: BeforeColon
BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: false
BreakConstructorInitializers: BeforeComma
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: true
ColumnLimit: 0
CommentPragmas: '^ IWYU pragma:'
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ConstructorInitializerIndentWidth: 4
ContinuationIndentWidth: 4
Cpp11BracedListStyle: false
DeriveLineEnding: true
DerivePointerAlignment: false
DisableFormat: false
EmptyLineAfterAccessModifier: Never
EmptyLineBeforeAccessModifier: LogicalBlock
ExperimentalAutoDetectBinPacking: false
PackConstructorInitializers: BinPack
BasedOnStyle: ''
ConstructorInitializerAllOnOneLineOrOnePerLine: false
AllowAllConstructorInitializersOnNextLine: true
FixNamespaceComments: false
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- foreach
- Q_FOREACH
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- KJ_IF_MAYBE
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SpaceBeforeCaseColon: false
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AfterControlStatements: true
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...

9
.gitignore vendored
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@ -1,6 +1,7 @@
_build_date.h _build_date.h
.cache/
.cmake/ .cmake/
output/ output/
scripts/images/ scripts/images/
@ -9,3 +10,11 @@ scripts/images/
## Keil Project ## Keil Project
MBL/Project/KEIL/*.ini MBL/Project/KEIL/*.ini
*.uvgui*
MBL/Project/KEIL/RTE/
MBL/Project/KEIL/mbl_ns/
NSPE/Project/WIFI_IOT/KEIL/RTE/
NSPE/Project/WIFI_IOT/KEIL/wifi_iot/
# Clang
compile_commands.json

10
CMakeLists.txt
View File

@ -5,6 +5,7 @@ project(GD32W51X LANGUAGES C ASM)
set(CONFIG_TZ_ENABLED OFF CACHE BOOL "Whether to enable trustzone") set(CONFIG_TZ_ENABLED OFF CACHE BOOL "Whether to enable trustzone")
set(CONFIG_OS "FREERTOS" CACHE STRING "Select which OS") set(CONFIG_OS "FREERTOS" CACHE STRING "Select which OS")
set(CONFIG_STATIC_LIB_BUILDED ON CACHE BOOL "Whether static lib builded, like wlan, iperf3 lib") set(CONFIG_STATIC_LIB_BUILDED ON CACHE BOOL "Whether static lib builded, like wlan, iperf3 lib")
set(CONFIG_GY3513 ON CACHE BOOL "Whether to allow gaoyang3513's modification or not.")
include(${CMAKE_TOOLCHAIN_FILE}) include(${CMAKE_TOOLCHAIN_FILE})
toolchain_reload_compiler() toolchain_reload_compiler()
@ -23,6 +24,14 @@ include_directories(
ROM-EXPORT/mbedtls-2.17.0-rom/include ROM-EXPORT/mbedtls-2.17.0-rom/include
) )
if(CONFIG_GY3513)
add_definitions(-DCONFIG_GY3513)
include_directories(
NSPE/Utilities
)
endif(CONFIG_GY3513)
if (CONFIG_TZ_ENABLED) if (CONFIG_TZ_ENABLED)
add_subdirectory(MBL/source) add_subdirectory(MBL/source)
include_directories(MBL/source) include_directories(MBL/source)
@ -31,5 +40,4 @@ else()
add_subdirectory(MBL/source_ns) add_subdirectory(MBL/source_ns)
endif() endif()
add_subdirectory(NSPE) add_subdirectory(NSPE)

906
MBL/Project/KEIL/Project_MBL_NS.uvoptx
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@ -1,453 +1,453 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd"> <ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion> <SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header> <Header>### uVision Project, (C) Keil Software</Header>
<Extensions> <Extensions>
<cExt>*.c</cExt> <cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt> <aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt> <oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt> <lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt> <tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt> <pExt>*.plm</pExt>
<CppX>*.cpp</CppX> <CppX>*.cpp</CppX>
<nMigrate>0</nMigrate> <nMigrate>0</nMigrate>
</Extensions> </Extensions>
<DaveTm> <DaveTm>
<dwLowDateTime>0</dwLowDateTime> <dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime> <dwHighDateTime>0</dwHighDateTime>
</DaveTm> </DaveTm>
<Target> <Target>
<TargetName>Target_GDM32</TargetName> <TargetName>Target_GDM32</TargetName>
<ToolsetNumber>0x4</ToolsetNumber> <ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName> <ToolsetName>ARM-ADS</ToolsetName>
<TargetOption> <TargetOption>
<CLKADS>12000000</CLKADS> <CLKADS>12000000</CLKADS>
<OPTTT> <OPTTT>
<gFlags>1</gFlags> <gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd> <BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim> <RunSim>0</RunSim>
<RunTarget>1</RunTarget> <RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc> <RunAbUc>0</RunAbUc>
</OPTTT> </OPTTT>
<OPTHX> <OPTHX>
<HexSelection>1</HexSelection> <HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte> <FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress> <HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress> <HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset> <HexOffset>0</HexOffset>
</OPTHX> </OPTHX>
<OPTLEX> <OPTLEX>
<PageWidth>79</PageWidth> <PageWidth>79</PageWidth>
<PageLength>66</PageLength> <PageLength>66</PageLength>
<TabStop>8</TabStop> <TabStop>8</TabStop>
<ListingPath>.\mbl_ns\Listings\</ListingPath> <ListingPath>.\mbl_ns\Listings\</ListingPath>
</OPTLEX> </OPTLEX>
<ListingPage> <ListingPage>
<CreateCListing>1</CreateCListing> <CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing> <CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing> <CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing> <CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond> <AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb> <AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref> <AsmXref>0</AsmXref>
<CCond>1</CCond> <CCond>1</CCond>
<CCode>0</CCode> <CCode>0</CCode>
<CListInc>0</CListInc> <CListInc>0</CListInc>
<CSymb>0</CSymb> <CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing> <LinkerCodeListing>0</LinkerCodeListing>
</ListingPage> </ListingPage>
<OPTXL> <OPTXL>
<LMap>1</LMap> <LMap>1</LMap>
<LComments>1</LComments> <LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols> <LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym> <LLibSym>1</LLibSym>
<LLines>1</LLines> <LLines>1</LLines>
<LLocSym>1</LLocSym> <LLocSym>1</LLocSym>
<LPubSym>1</LPubSym> <LPubSym>1</LPubSym>
<LXref>0</LXref> <LXref>0</LXref>
<LExpSel>0</LExpSel> <LExpSel>0</LExpSel>
</OPTXL> </OPTXL>
<OPTFL> <OPTFL>
<tvExp>1</tvExp> <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget> <IsCurrentTarget>1</IsCurrentTarget>
</OPTFL> </OPTFL>
<CpuCode>255</CpuCode> <CpuCode>255</CpuCode>
<DebugOpt> <DebugOpt>
<uSim>0</uSim> <uSim>0</uSim>
<uTrg>1</uTrg> <uTrg>1</uTrg>
<sLdApp>1</sLdApp> <sLdApp>1</sLdApp>
<sGomain>1</sGomain> <sGomain>1</sGomain>
<sRbreak>1</sRbreak> <sRbreak>1</sRbreak>
<sRwatch>1</sRwatch> <sRwatch>1</sRwatch>
<sRmem>1</sRmem> <sRmem>1</sRmem>
<sRfunc>1</sRfunc> <sRfunc>1</sRfunc>
<sRbox>1</sRbox> <sRbox>1</sRbox>
<tLdApp>0</tLdApp> <tLdApp>0</tLdApp>
<tGomain>0</tGomain> <tGomain>0</tGomain>
<tRbreak>1</tRbreak> <tRbreak>1</tRbreak>
<tRwatch>1</tRwatch> <tRwatch>1</tRwatch>
<tRmem>1</tRmem> <tRmem>1</tRmem>
<tRfunc>0</tRfunc> <tRfunc>0</tRfunc>
<tRbox>1</tRbox> <tRbox>1</tRbox>
<tRtrace>1</tRtrace> <tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw> <sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw> <tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb> <sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime> <sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn> <bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf> <bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf> <bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel> <nTsel>14</nTsel>
<sDll></sDll> <sDll></sDll>
<sDllPa></sDllPa> <sDllPa></sDllPa>
<sDlgDll></sDlgDll> <sDlgDll></sDlgDll>
<sDlgPa></sDlgPa> <sDlgPa></sDlgPa>
<sIfile></sIfile> <sIfile></sIfile>
<tDll></tDll> <tDll></tDll>
<tDllPa></tDllPa> <tDllPa></tDllPa>
<tDlgDll></tDlgDll> <tDlgDll></tDlgDll>
<tDlgPa></tDlgPa> <tDlgPa></tDlgPa>
<tIfile>.\mbl_ns.ini</tIfile> <tIfile>.\mbl_ns.ini</tIfile>
<pMon>BIN\CMSIS_AGDI_V8M.DLL</pMon> <pMon>BIN\CMSIS_AGDI_V8M.DLL</pMon>
</DebugOpt> </DebugOpt>
<TargetDriverDllRegistry> <TargetDriverDllRegistry>
<SetRegEntry> <SetRegEntry>
<Number>0</Number> <Number>0</Number>
<Key>CMSIS_AGDI_V8M</Key> <Key>CMSIS_AGDI_V8M</Key>
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<FileType>1</FileType> <FileType>1</FileType>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_misc.c</PathWithFileName> <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_misc.c</PathWithFileName>
<FilenameWithoutPath>gd32w51x_misc.c</FilenameWithoutPath> <FilenameWithoutPath>gd32w51x_misc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg> <RteFlg>0</RteFlg>
<bShared>0</bShared> <bShared>0</bShared>
</File> </File>
</Group> </Group>
<Group> <Group>
<GroupName>::CMSIS</GroupName> <GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel> <cbSel>0</cbSel>
<RteFlg>1</RteFlg> <RteFlg>1</RteFlg>
</Group> </Group>
</ProjectOpt> </ProjectOpt>

1005
MBL/Project/KEIL/Project_MBL_NS.uvprojx
View File

File diff suppressed because it is too large Load Diff

20
MBL/Project/mbl_afterbuild.bat Normal file → Executable file
View File

@ -10,12 +10,22 @@ set ROOT=%OUTPUT_PATH%\..\..\..\..\..
set SREC_CAT=%ROOT%\scripts\imgtool\srec_cat.exe set SREC_CAT=%ROOT%\scripts\imgtool\srec_cat.exe
set OUTPUT_IMAGE_PATH=%ROOT%\scripts\images set OUTPUT_IMAGE_PATH=%ROOT%\scripts\images
if "%TOOLKIT%" == "KEIL" ( for /f "tokens=1,2 delims=\" %%a in ("%TOOLKIT_PATH%") do set driver=%%a &set version=%%b
:: Generate txt for debug
%TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --text -c -d --output=%OUTPUT_PATH%\..\%OUTPUT_NAME%.txt %OUTPUT_PATH%\%OUTPUT_NAME%.axf
:: Generate binary image if "%TOOLKIT%" == "KEIL" (
%TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --bin --8x1 --bincombined --output=%OUTPUT_PATH%\..\%OUTPUT_NAME%.bin %OUTPUT_PATH%\%OUTPUT_NAME%.axf if "%version%" == "Keil_v5" (
:: Generate txt for debug
%TOOLKIT_PATH%\ARM\ARMCLANG\bin\fromelf.exe --text -c -d --output=%OUTPUT_PATH%\..\%OUTPUT_NAME%.txt %OUTPUT_PATH%\%OUTPUT_NAME%.axf
:: Generate binary image
%TOOLKIT_PATH%\ARM\ARMCLANG\bin\fromelf.exe --bin --8x1 --bincombined --output=%OUTPUT_PATH%\..\%OUTPUT_NAME%.bin %OUTPUT_PATH%\%OUTPUT_NAME%.axf
) else (
:: Generate txt for debug
%TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --text -c -d --output=%OUTPUT_PATH%\..\%OUTPUT_NAME%.txt %OUTPUT_PATH%\%OUTPUT_NAME%.axf
:: Generate binary image
%TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --bin --8x1 --bincombined --output=%OUTPUT_PATH%\..\%OUTPUT_NAME%.bin %OUTPUT_PATH%\%OUTPUT_NAME%.axf
)
) )
if "%TOOLKIT%" == "IAR" ( if "%TOOLKIT%" == "IAR" (
:: Generate ASM file :: Generate ASM file

1
MBL/Project/mbl_afterbuild.sh
View File

@ -37,4 +37,3 @@ fi
cp ${OUTPUT_PATH}/../${OUTPUT_NAME}.bin ${OUTPUT_IMAGE_PATH} cp ${OUTPUT_PATH}/../${OUTPUT_NAME}.bin ${OUTPUT_IMAGE_PATH}
# Generate Hex file # Generate Hex file
${SREC_CAT} ${OUTPUT_IMAGE_PATH}/${OUTPUT_NAME}.bin -Binary -offset 0x0C000000 -o ${OUTPUT_IMAGE_PATH}/${OUTPUT_NAME}.hex -Intel ${SREC_CAT} ${OUTPUT_IMAGE_PATH}/${OUTPUT_NAME}.bin -Binary -offset 0x0C000000 -o ${OUTPUT_IMAGE_PATH}/${OUTPUT_NAME}.hex -Intel

5
MBL/platform/gdm32/cmsis_core/mbl_system_gdm32.c
View File

@ -42,6 +42,11 @@
} \ } \
} }
#define __SYSTEM_CLOCK_180M_PLLP_40M_HXTAL (uint32_t)(180000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_180M_PLLP_40M_HXTAL;
/*! /*!
\brief configure the system clock to HXTAL \brief configure the system clock to HXTAL
\param[in] none \param[in] none

24
MBL/platform/gdm32/gd32w51x_it.c
View File

@ -34,6 +34,8 @@ OF SUCH DAMAGE.
#include "gd32w51x_it.h" #include "gd32w51x_it.h"
#include "rom_export.h" #include "rom_export.h"
#include <systick.h>
#include <irq_handle.h>
/*! /*!
\brief this function handles NMI exception \brief this function handles NMI exception
@ -127,3 +129,25 @@ void UsageFault_Handler(void)
while(1){ while(1){
} }
} }
/*!
\brief this function handles SysTick exception
\param[in] none
\param[out] none
\retval none
*/
void SysTick_Handler(void)
{
delay_decrement();
}
/*!
\brief This function handles TIMER2 interrupt request.
\param[in] none
\param[out] none
\retval none
*/
void TIMER2_IRQHandler(void)
{
__TIMER2_IRQHandler();
}

112
MBL/platform/gdm32/systick.c Normal file
View File

@ -0,0 +1,112 @@
/*!
\file systick.c
\brief the systick configuration file
\version 2021-10-30, V1.0.0, firmware for GD32W51x
*/
/*
Copyright (c) 2021, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32w51x.h"
#include "systick.h"
volatile static uint32_t delay;
static uint32_t priority_orig;
/*!
\brief configure systick
\param[in] none
\param[out] none
\retval none
*/
void systick_config(void)
{
priority_orig = __NVIC_GetPriority(SysTick_IRQn);
/* setup systick timer for 1MHz interrupts */
if (SysTick_Config(SystemCoreClock / 1000000U)) {
/* capture error */
while(1);
}
/* configure the systick handler priority */
NVIC_SetPriority(SysTick_IRQn, 0x00U);
}
/*!
\brief configure systick
\param[in] none
\param[out] none
\retval none
*/
void systick_deinit(void)
{
NVIC_SetPriority(SysTick_IRQn, priority_orig);
SysTick->LOAD = 0UL; /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
}
/*!
\brief delay a time in milliseconds
\param[in] count: count in milliseconds
\param[out] none
\retval none
*/
void delay_1us(uint32_t count)
{
delay = count;
while(0U != delay);
}
/*!
\brief delay a time in milliseconds
\param[in] count: count in milliseconds
\param[out] none
\retval none
*/
void delay_1ms(uint32_t count)
{
delay = count * 1000;
while(0U != delay);
}
/*!
\brief delay decrement
\param[in] none
\param[out] none
\retval none
*/
void delay_decrement(void)
{
if (0U != delay)
delay--;
}

51
MBL/platform/gdm32/systick.h Normal file
View File

@ -0,0 +1,51 @@
/*!
\file systick.h
\brief the header file of systick
\version 2021-10-30, V1.0.0, firmware for GD32W51x
*/
/*
Copyright (c) 2021, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef SYSTICK_H
#define SYSTICK_H
#include <stdint.h>
/* configure systick */
void systick_config(void);
/* Deinit systick */
void systick_deinit(void);
/* delay a time in milliseconds */
void delay_1us(uint32_t count);
/* delay a time in milliseconds */
void delay_1ms(uint32_t count);
/* delay decrement */
void delay_decrement(void);
#endif /* SYSTICK_H */

39
MBL/source_ns/CMakeLists.txt
View File

@ -1,5 +1,5 @@
cmake_minimum_required(VERSION 3.15) cmake_minimum_required(VERSION 3.15)
set(TARGET_EXE mbl-ns) set(TARGET_EXE mbl-ns)
set(TAGET_PROJECT_DIR ${PROJECT_SOURCE_DIR}/MBL/Project) set(TAGET_PROJECT_DIR ${PROJECT_SOURCE_DIR}/MBL/Project)
add_executable(${TARGET_EXE}) add_executable(${TARGET_EXE})
@ -25,7 +25,27 @@ target_sources(${TARGET_EXE}
mbl_qspi_flash.c mbl_qspi_flash.c
mbl_sys.c mbl_sys.c
mbl_uart.c mbl_uart.c
) drivers/CMT2310/0_Project/Uart_PingPong/main.c
drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.c
drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.c
drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.c
drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.c
drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.c
drivers/CMT2310/1_Middleware/Produce/ebyte_debug.c
drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.c
drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.c
drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.c
drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_433mhz.c
drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c
drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_868mhz.c
drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_915mhz.c
drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.c
drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c
drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_410mhz.c
drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.c
drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.c
drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c
)
target_sources(${TARGET_EXE} target_sources(${TARGET_EXE}
PRIVATE PRIVATE
@ -37,17 +57,28 @@ target_sources(${TARGET_EXE}
${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_qspi.c ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_qspi.c
${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_rcu.c ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_rcu.c
${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_usart.c ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_usart.c
${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_spi.c
${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_timer.c
) )
target_sources(${TARGET_EXE} target_sources(${TARGET_EXE}
PRIVATE PRIVATE
../platform/gdm32/cmsis_core/mbl_system_gdm32.c ../platform/gdm32/cmsis_core/mbl_system_gdm32.c
../platform/gdm32/gcc/mbl_startup_gdm32.s ../platform/gdm32/gcc/mbl_startup_gdm32.s
../platform/gdm32/gd32w51x_it.c
../platform/gdm32/systick.c
) )
target_include_directories(${TARGET_EXE} target_include_directories(${TARGET_EXE}
PRIVATE PRIVATE
${PROJECT_SOURCE_DIR}/MBL/platform/gdm32/
${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Include ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Include
${CMAKE_CURRENT_SOURCE_DIR}/drivers/CMT2310/0_Project/Uart_PingPong/
${CMAKE_CURRENT_SOURCE_DIR}/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/
${CMAKE_CURRENT_SOURCE_DIR}/drivers/CMT2310/1_Middleware/Kfifo/
${CMAKE_CURRENT_SOURCE_DIR}/drivers/CMT2310/1_Middleware/Produce/
${CMAKE_CURRENT_SOURCE_DIR}/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/
${CMAKE_CURRENT_SOURCE_DIR}/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/
) )
target_add_scatter_file(${TARGET_EXE} target_add_scatter_file(${TARGET_EXE}
@ -61,6 +92,10 @@ target_link_options(${TARGET_EXE}
-Wl,-Map=${TAGET_PROJECT_DIR}/GCC/output/bin/${TARGET_EXE}.map -Wl,-Map=${TAGET_PROJECT_DIR}/GCC/output/bin/${TARGET_EXE}.map
) )
get_target_property(LINK_FLAGS ${TARGET_EXE} LINK_OPTIONS)
string(REGEX REPLACE "(.*)-u._printf_float(.*)" "\\1\\2" LINK_FLAGS "${LINK_FLAGS}")
set_target_properties(${TARGET_EXE} PROPERTIES LINK_OPTIONS "${LINK_FLAGS}")
if(CMAKE_HOST_UNIX) if(CMAKE_HOST_UNIX)
add_custom_command(TARGET ${TARGET_EXE} POST_BUILD add_custom_command(TARGET ${TARGET_EXE} POST_BUILD
COMMAND ${TAGET_PROJECT_DIR}/mbl_afterbuild.sh ${TAGET_PROJECT_DIR}/GCC/output/bin ${TARGET_EXE} GCC \"\" COMMAND ${TAGET_PROJECT_DIR}/mbl_afterbuild.sh ${TAGET_PROJECT_DIR}/GCC/output/bin ${TARGET_EXE} GCC \"\"

12
MBL/source_ns/drivers/.editorconfig Normal file
View File

@ -0,0 +1,12 @@
# EditorConfig is awesome: https://EditorConfig.org
# top-most EditorConfig file
root = true
[*]
indent_style = tab
indent_size = 8
end_of_line = lf
charset = utf-8
trim_trailing_whitespace = true
insert_final_newline = false

131
MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.c Executable file
View File

@ -0,0 +1,131 @@
/**
**********************************************************************************
* @file ebyte_callback.h
* @brief EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>շ<EFBFBD><D5B7><EFBFBD><EFBFBD>ɻص<C9BB><D8B5><EFBFBD><EFBFBD><EFBFBD> <20>ɿͻ<C9BF>ʵ<EFBFBD><CAB5><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD>߼<EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-13
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "ebyte_callback.h"
/*= !!!<21><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨ͷ<CCA8>ļ<EFBFBD> =======================================*/
#include "board.h" //E15-EVB02 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#include "ebyte_debug.h" //E15-EVB02 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#include <stdint.h>
#include <stdio.h>
/*= !!!<21><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD> =======================================*/
extern uint8_t RxBuffer[64];
extern uint8_t BufferPing[5];
extern uint8_t BufferPong[5];
extern uint8_t Callback_isPingCheckReady;
extern uint8_t PC_isConnected;
extern uint8_t PcEchoBuffer[20];
extern uint8_t is_jump_main;
/*==================================================================*/
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɻص<C9BB><D8B5>ӿ<EFBFBD> <20>ɿͻ<C9BF>ʵ<EFBFBD><CAB5><EFBFBD>Լ<EFBFBD><D4BC>ķ<EFBFBD><C4B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD>
*
* @param state <20>ϲ<EFBFBD><CFB2>ص<EFBFBD><D8B5>ṩ<EFBFBD><E1B9A9>״̬<D7B4><CCAC> <20>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE>ע<EFBFBD><D7A2><EFBFBD>ҵ<EFBFBD><D2B5><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD>
*
*/
void Ebyte_Port_TransmitCallback( uint16e_t state )
{
/* <20><><EFBFBD><EFBFBD>: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if( state &= 0x0001 )
{
//To-do ʵ<><CAB5><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD>߼<EFBFBD>
}
/* <20><><EFBFBD><EFBFBD>: <20>쳣<EFBFBD><ECB3A3>ʱ */
else if ( state &= 0x0200 )
{
//To-do ʵ<><CAB5><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD>߼<EFBFBD>
}
/* <20><><EFBFBD><EFBFBD>: δ֪<CEB4><D6AA><EFBFBD><EFBFBD> */
else
{
/* <20><><EFBFBD><EFBFBD>״̬<D7B4><CCAC>ʶ<EFBFBD><CAB6><EFBFBD><EFBFBD>ȷ<EFBFBD><C8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2>
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1:SPIͨ<49>Ų<EFBFBD><C5B2><EFBFBD>ȷ 2:ģ<>鹩<EFBFBD>粻<EFBFBD><E7B2BB> */
while(1);
}
}
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɻص<C9BB><D8B5>ӿ<EFBFBD> <20>ɿͻ<C9BF>ʵ<EFBFBD><CAB5><EFBFBD>Լ<EFBFBD><D4BC>ķ<EFBFBD><C4B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD>
*
* @param state <20>ϲ<EFBFBD><CFB2>ص<EFBFBD><D8B5>ṩ<EFBFBD><E1B9A9>״̬<D7B4><CCAC> <20>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE>ע<EFBFBD><D7A2><EFBFBD>ҵ<EFBFBD><D2B5><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD>
*
*/
void Ebyte_Port_ReceiveCallback( uint16_t state, uint8_t *buffer, uint8_t length )
{
uint8_t j, pcEchoLength;
uint8_t *p;
uint8_t rx_data[32] = {0};
/* <20><><EFBFBD><EFBFBD>: <20><><EFBFBD><EFBFBD> */
if( state &= 0x0002 ) {
//To-do ʵ<><CAB5><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD>߼<EFBFBD>
/* ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD>ping pongָ<67><D6B8> */
if( length == 4 || length == 5 ) {
p = buffer;
for( j = 0; j < 4; j++ ) {
if( BufferPing[j] != *p++ )
break;
}
if( j == 4 ) { //<2F>Ƚϵ<C8BD><CFB5><EFBFBD>ĩβ<C4A9><CEB2>ʾ<EFBFBD><CABE>ȫƥ<C8AB><C6A5>ping
Callback_isPingCheckReady = 1;//֪ͨ<CDA8>ظ<EFBFBD>Pong
if( length == 5 && PC_isConnected )
BufferPong[4] = buffer[4];//<2F><>5<EFBFBD>ֽ<EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʶ
}
if( j!=4 && length == 5 && PC_isConnected ) {
p = buffer;
for( j = 0; j < 4; j++ ) {
if( BufferPong[j] != *p++ )
break;
}
if( j == 4 ) {//<2F><>ȫƥ<C8AB><C6A5>pong
if( 0x01 == buffer[4] )
Ebyte_DEBUG_CommandEcho( ( uint8_t* )SimulatedCommandsWireless1, EBYTE_CMD_PACKAGE_LENGTH, PcEchoBuffer, &pcEchoLength );
else
Ebyte_DEBUG_CommandEcho( ( uint8_t* )SimulatedCommandsWireless2, EBYTE_CMD_PACKAGE_LENGTH, PcEchoBuffer, &pcEchoLength );
Ebyte_BSP_UartTransmit( PcEchoBuffer, pcEchoLength );
}
}
}
Ebyte_BSP_LedControl( BSP_LED_1, ON );
if( ! PC_isConnected ) {
is_jump_main = 1;
snprintf(rx_data, sizeof(rx_data), "%s", buffer);
EBYTE_LOG(" Receive Data: %s\r\n", rx_data);
}
Ebyte_BSP_LedControl( BSP_LED_1, OFF );
}
else if ( state &= 0x0200 ) { /* <20><><EFBFBD><EFBFBD>: <20>쳣<EFBFBD><ECB3A3>ʱ */
//To-do ʵ<><CAB5><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD>߼<EFBFBD>
}
else { /* <20><><EFBFBD><EFBFBD>: δ֪<CEB4><D6AA><EFBFBD><EFBFBD> */
/* <20><><EFBFBD><EFBFBD>״̬<D7B4><CCAC>ʶ<EFBFBD><CAB6><EFBFBD><EFBFBD>ȷ<EFBFBD><C8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2>
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1:SPIͨ<49>Ų<EFBFBD><C5B2><EFBFBD>ȷ 2:ģ<>鹩<EFBFBD>粻<EFBFBD><E7B2BB> */
while(1);
}
}

8
MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.h Executable file
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#ifndef _EBYTE_CALLBACK_H_
#define _EBYTE_CALLBACK_H_
#include "ebyte_port.h"
void Ebyte_Port_TransmitCallback( uint16e_t state );
void Ebyte_Port_ReceiveCallback( uint16e_t state ,uint8e_t *buffer, uint8e_t length);
#endif

34
MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_conf.h Executable file
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/**
**********************************************************************************
* @file ebyte_conf.h
* @brief EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-13
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
/*= !!!<21><><EFBFBD>ò<EFBFBD>Ʒ<EFBFBD>ͺ<EFBFBD> <20><>ѡ ============================================*/
#define EBYTE_E48_433M20S
//#define EBYTE_E48_900M20S
/*==================================================================*/
/* SPIͨ<49><CDA8> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CS(NSS)<29>ź<EFBFBD> 0:<3A><><EFBFBD><EFBFBD> 1:<3A><><EFBFBD><EFBFBD> */
#define EBYTE_PORT_SPI_CS_SOFTWARE 1
/* <20><><EFBFBD>μ<EFBFBD><CEBC><EFBFBD>ģ<EFBFBD>鷢<EFBFBD><E9B7A2>ʱ<EFBFBD><CAB1>״̬ 0:<3A>첽<EFBFBD>ж<EFBFBD>֪ͨ 1:ͬ<><CDAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define EBYTE_RF_TRANSMIT_CHECK_MODE 1

49
MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.c Executable file
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/**
**********************************************************************************
* @file ebyte_core.c
* @brief EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϲ<EFBFBD>API<50><49>װ<EFBFBD><D7B0> <20><><EFBFBD><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ײ<EFBFBD><D7B2>߼<EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-13
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "ebyte_core.h"
/* ָ<><D6B8> E48x <20>ײ<EFBFBD><D7B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#if defined(EBYTE_E48_433M20S)||defined(EBYTE_E48_900M20S)
const Ebyte_RF_t Ebyte_RF =
{
Ebyte_E48x_Init,
Ebyte_E48x_SendPayload,
Ebyte_E48x_SetStandby,
Ebyte_E48x_SetSleep,
Ebyte_E48x_SetRx,
Ebyte_E48x_IntOrPollTask,
Ebyte_E48x_InterruptTrigger,
Ebyte_E48x_GetName,
Ebyte_E48x_GetDriverVersion
};
#else
/* ebyte_conf.h <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD>IJ<EFBFBD>Ʒ<EFBFBD>ͺŲ<CDBA><C5B2><EFBFBD>ȷ */
#error No product selected !
#endif

47
MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.h Executable file
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/**
**********************************************************************************
* @file ebyte_core.h
* @brief EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϲ<EFBFBD>API<50><49>װ<EFBFBD><D7B0> <20><><EFBFBD><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ײ<EFBFBD><D7B2>߼<EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-13
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include <stdint.h>
#include "ebyte_conf.h"
#if defined(EBYTE_E48_433M20S)||defined(EBYTE_E48_900M20S)
#include "ebyte_e48x.h"
#else
#error No product selected !
#endif
typedef struct
{
void ( *Init )( void );
void ( *Send )( uint8e_t *buffer, uint8e_t size , uint32e_t timeout);
void ( *EnterStandby )( uint8e_t command);
void ( *EnterSleepMode )( uint8e_t command);
void ( *EnterReceiveMode )( uint32e_t timeout );
void ( *StartPollTask)( void );
void ( *InterruptTrigger)( void );
uint32e_t ( *GetName ) (void );
uint8e_t ( *GetDriverVersion ) (void );
}Ebyte_RF_t;
extern const Ebyte_RF_t Ebyte_RF;

96
MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.c Executable file
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/**
**********************************************************************************
* @file ebyte_port.h
* @brief EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD>ӿڲ<D3BF> <20>ɿͻ<C9BF><CDBB>Լ<EFBFBD><D4BC>ṩIO<49>ӿ<EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-13
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "ebyte_port.h"
/*= !!!<21><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨ͷ<CCA8>ļ<EFBFBD> =======================================*/
#include "board.h" //E15-EVB02 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#include "drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h"
#include "systick.h"
/*==================================================================*/
/* !
* @brief <20><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨SPI<50>ӿ<EFBFBD><D3BF>շ<EFBFBD><D5B7><EFBFBD><EFBFBD><EFBFBD>
*
* @param send EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 Byte
* @return SPI<50><49><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD> 1 Byte
* @note <20><>Ŀ<EFBFBD><C4BF>ƽ̨<C6BD><CCA8><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2>SPI_NSSʱ<53><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ebyte_conf.h<>ļ<EFBFBD> <20>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPI_CS(NSS)
* <20><>Ŀ<EFBFBD><C4BF>ƽ̨<C6BD><CCA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPI_NSSʱ<53><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ebyte_Port_SpiCsIoControl() <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĺ<EFBFBD><C4BA><EFBFBD>˵<EFBFBD><CBB5>
*/
uint8e_t Ebyte_Port_SpiTransmitAndReceivce( uint8e_t send )
{
uint8e_t result = 0;
/* !<21><><EFBFBD><EFBFBD><EFBFBD>ṩ: SPI<50>ӿ<EFBFBD> */
result = Ebyte_BSP_SpiTransAndRecv( send );
return result;
}
/* !
* @brief (<28><>ѡ)<29><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨SPI_CS(NSS)<29><><EFBFBD><EFBFBD>
*
* @param cmd EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD>ָ<EFBFBD><D6B8>
* @arg 0: <20><><EFBFBD><EFBFBD>CS(NSS)<29><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>ƽ<EFBFBD>߼<EFBFBD><DFBC>ź<EFBFBD> EBYTEģ<45><C4A3>SPI<50>ӿ<EFBFBD>Ϊ<EFBFBD>͵<EFBFBD>ƽѡ<C6BD><D1A1>
* @arg 1: <20><><EFBFBD><EFBFBD>CS(NSS)<29><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD>ƽ<EFBFBD>߼<EFBFBD><DFBC>ź<EFBFBD>
* @note <20><>Ŀ<EFBFBD><C4BF>ƽ̨<C6BD><CCA8><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2>SPI_NSSʱ<53><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> <20>˺<EFBFBD><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
* <20><>Ŀ<EFBFBD><C4BF>ƽ̨<C6BD><CCA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPI_NSSʱ<53><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ô˺<C3B4><CBBA><EFBFBD>
*/
void Ebyte_Port_SpiCsIoControl( uint8e_t cmd )
{
if ( cmd == 1 )
{
/* !<21><>ѡ: SPI CS<43><53><EFBFBD><EFBFBD> <20>ߵ<EFBFBD>ƽδѡ<CEB4><D1A1> */
Ebyte_BSP_RfSpiUnselected();
}
else
{
/* !<21><>ѡ: SPI CS<43><53><EFBFBD><EFBFBD> <20>͵<EFBFBD>ƽѡ<C6BD><D1A1> */
Ebyte_BSP_RfSpiSelected( );
}
}
/* !
* @brief <20><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨<C6BD><CCA8>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
*
* @param time <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
* @note <20><>ע<EFBFBD><D7A2>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ô˺<C3B4><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD>Ӱ<EFBFBD>쵽<EFBFBD>˺<EFBFBD><CBBA><EFBFBD>
*/
void Ebyte_Port_DelayMs( uint16e_t time )
{
/* !<21><><EFBFBD><EFBFBD><EFBFBD>ṩ: <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> */
delay_1ms(time);
}
/* !
* @brief <20><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨<C6BD><CCA8>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
*
* @param time <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
* @note <20><>ע<EFBFBD><D7A2>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ô˺<C3B4><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD>Ӱ<EFBFBD>쵽<EFBFBD>˺<EFBFBD><CBBA><EFBFBD>
*/
void Ebyte_Port_DelayUs( uint16e_t time )
{
/* !<21><><EFBFBD><EFBFBD><EFBFBD>ṩ: <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> */
delay_1us(time);
}

33
MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.h Executable file
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#ifndef __EBYTE_PORT_H
#define __EBYTE_PORT_H
#include <stdio.h>
#include "ebyte_conf.h"
//#include "stm8l15x.h"
//typedef unsigned char uint8e_t;
//typedef unsigned short uint16e_t;
//typedef unsigned long uint32e_t;
//
//typedef signed char int8e_t;
//typedef signed short int16e_t;
//typedef signed long int32e_t;
#define uint8e_t uint8_t
#define uint16e_t uint16_t
#define uint32e_t uint32_t
#define int8e_t int8_t
#define int16e_t int16_t
#define int32e_t int32_t
void Ebyte_Port_RstIoControl( uint8e_t cmd );
void Ebyte_Port_TxenIoControl( uint8e_t cmd );
void Ebyte_Port_RxenIoControl( uint8e_t cmd );
void Ebyte_Port_DelayMs( uint16e_t time );
void Ebyte_Port_DelayUs( uint16e_t time );
void Ebyte_Port_SpiCsIoControl( uint8e_t cmd );
uint8e_t Ebyte_Port_BusyIoRead( void );
uint8e_t Ebyte_Port_SpiTransmitAndReceivce( uint8e_t send );
#endif /* __EBYTE_PORT_H */

8
MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte_e48.h Normal file
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#ifndef __EBYTE_E48_H__
#define __EBYTE_E48_H__
#include <board.h>
int ebyte_main( void );
#endif /* __EBYTE_E48_H__ */

211
MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.c Executable file
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/**
******************************************************************************
* @file stm8l15x_it.c
* @author MCD Application Team
* @version V1.0.0
* @date 09/28/2010
* @brief Main Interrupt Service Routines.
* This file provides template for all peripherals interrupt service routine.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32_it.h"
#include "ebyte_kfifo.h"
#include "ebyte_core.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
static uint8_t Uart_isInRecvState = 0;
static uint8_t Uart_isContinuousRecv = 0;
static uint32_t Uart_TickCounter = 0;
extern uint8_t Uart_isRecvReady;
static uint16_t Button1_TickCounter = 0;
static uint16_t Button2_TickCounter = 0;
extern Ebyte_FIFO_t hfifo;
extern uint8_t FIFO_isTimeCheckReady;
static uint32_t FIFO_TickCounter = 0;
/* Private function prototypes -----------------------------------------------*/
void IT_Timer_ButtonCheck(void);
void IT_Timer_UartCheck(void);
/* Private functions ---------------------------------------------------------*/
/** @addtogroup IT_Functions
* @{
*/
#ifdef _COSMIC_
/**
* @brief Dummy interrupt routine
* @par Parameters:
* None
* @retval
* None
*/
INTERRUPT_HANDLER(NonHandledInterrupt, 0)
{
/* In order to detect unexpected events during development,
it is recommended to set a breakpoint on the following instruction.
*/
}
#endif
/*!
\brief This function handles TIMER2 interrupt request.
\param[in] none
\param[out] none
\retval none
*/
void __TIMER2_IRQHandler(void)
{
if(SET == timer_interrupt_flag_get(TIMER2, TIMER_INT_UP)){
/* clear channel 0 interrupt bit */
timer_interrupt_flag_clear(TIMER2, TIMER_INT_UP);
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
IT_Timer_ButtonCheck();
/* <20><><EFBFBD><EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD> */
// IT_Timer_UartCheck();
/* <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
Ebyte_BSP_TimerDecrement();
}
}
#if 0 // GY3513
/**
* @brief USART1 RX / Timer5 Capture/Compare Interrupt routine.
* @param None
* @retval None
*/
INTERRUPT_HANDLER(USART1_RX_TIM5_CC_IRQHandler, 28)
{
/* <20><>֡<EFBFBD>ж<EFBFBD> ״̬<D7B4><CCAC> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʱ 10ms<6D><73>δ<EFBFBD>յ<EFBFBD><D5B5><EFBFBD>һ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>֡ */
if( !Uart_isInRecvState )
{
Uart_isInRecvState = 1;
}
Uart_isContinuousRecv = 1;
/* <20><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 Byte */
uint8_t temp = USART_ReceiveData8(USART1) ;
/* д<>뻺<EFBFBD><EBBBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 Byte */
Ebyte_FIFO_Write( &hfifo, &temp, 1 );
/* <20><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>ʶ */
USART_ClearITPendingBit( USART1, USART_IT_RXNE );
}
/* !
* @brief <20><>ʱ<EFBFBD><CAB1><EFBFBD>ж<EFBFBD> ״̬<D7B4><CCAC> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
void IT_Timer_ButtonCheck(void)
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if( !Ebyte_BSP_ReadButton( BSP_BUTTON_1 ) )
{
Button1_TickCounter++;
}
else
{
if( Button1_TickCounter > 1000 ) // 1<><31> <20><><EFBFBD><EFBFBD>
{
Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_1_LONG);
}
else if( Button1_TickCounter > 50 ) //50<35><30><EFBFBD><EFBFBD> <20>̰<EFBFBD>
{
Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_1_SHORT);
}
else {} //50<35><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ϊ<EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
Button1_TickCounter=0;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if( !Ebyte_BSP_ReadButton( BSP_BUTTON_2 ) )
{
Button2_TickCounter++;
}
else
{
if( Button2_TickCounter > 1000 ) // 1<><31> <20><><EFBFBD><EFBFBD>
{
Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_2_LONG);
}
else if( Button2_TickCounter > 50 ) //50<35><30><EFBFBD><EFBFBD> <20>̰<EFBFBD>
{
Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_2_SHORT);
}
else {} //50<35><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ϊ<EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
Button2_TickCounter=0;
}
}
/* !
* @brief <20><>ʱ<EFBFBD><CAB1><EFBFBD>ж<EFBFBD> ״̬<D7B4><CCAC> <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>֡
*/
void IT_Timer_UartCheck(void)
{
/* <20><><EFBFBD>ڽ<EFBFBD><DABD>յ<EFBFBD><D5B5><EFBFBD>һ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD>Ϳ<EFBFBD>ʼ<EFBFBD><CABC>ʱ */
if( Uart_isInRecvState )
{
Uart_TickCounter++;
/* <20><><EFBFBD><EFBFBD>10msû<73>н<EFBFBD><D0BD>յ<EFBFBD><D5B5>ڶ<EFBFBD><DAB6>ֽ<EFBFBD> <20><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>֡ */
if( Uart_TickCounter > 10 )
{
/* ֪ͨ<CDA8><D6AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD>һ֡ */
Uart_isRecvReady ++;
/* ֹͣ<CDA3><D6B9>ʱ */
Uart_isInRecvState = 0;
Uart_TickCounter = 0;
}
/* <20><>λFIFO<46><4F>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> */
FIFO_TickCounter = 0;
}
else
{
/* <20><><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD>û<EFBFBD>н<EFBFBD><D0BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡ 500ms<6D><73><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>FIFO<46>е<EFBFBD><D0B5><EFBFBD><EFBFBD><EFBFBD> */
if( (!Uart_isInRecvState) && Uart_isRecvReady )
{
FIFO_TickCounter++;
if( FIFO_TickCounter > 500)
{
FIFO_isTimeCheckReady=1;
Uart_isRecvReady = 0;
FIFO_TickCounter = 0;
}
}
}
/* <20><><EFBFBD><EFBFBD>ÿ<EFBFBD><C3BF><EFBFBD>յ<EFBFBD>1<EFBFBD><31><EFBFBD>ֽھ<D6BD><DABE><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD> */
if( Uart_isInRecvState && Uart_isContinuousRecv )
{
Uart_TickCounter = 0;
Uart_isContinuousRecv = 0;
}
}
#endif // GY3513
/**
* @}
*/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

38
MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.h Executable file
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@ -0,0 +1,38 @@
/**
******************************************************************************
* @file stm8l15x_it.h
* @author MCD Application Team
* @version V1.0.0
* @date 09/28/2010
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_IT_H
#define __STM8L15x_IT_H
/* Includes ------------------------------------------------------------------*/
//#include "stm8l15x.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void __TIMER2_IRQHandler(void);
#endif /* __STM8L15x_IT_H */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

233
MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/main.c Executable file
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/**
**********************************************************************************
* @file main.c
* @brief E15-EVB02 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̼<EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͸<EFBFBD><CDB8>ʾ<EFBFBD><CABE> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author yxw
* @date 2023-12-25
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "ebyte_core.h"
#include "ebyte_kfifo.h"
#include "ebyte_debug.h"
#include "systick.h"
void Task_Transmit( void );
void Task_Button( void );
/* <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ݴ洢<DDB4><E6B4A2><EFBFBD><EFBFBD> */
Ebyte_FIFO_t hfifo;
/* <20><><EFBFBD><EFBFBD> ֡<><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD>ʶ */
uint8_t Uart_isRecvReady = 0;
/* <20><><EFBFBD><EFBFBD> FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʶ */
uint8_t FIFO_isTimeCheckReady = 0;
/* <20><><EFBFBD><EFBFBD> <20>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
uint8_t TxBuffer[64] = {0};
uint8_t RxBuffer[64] = {0};
uint8_t PcEchoBuffer[20] = {0};
uint8_t BufferPing[5] = {'p', 'i', 'n', 'g'};
uint8_t BufferPong[5] = {'p', 'o', 'n', 'g'};
/* <20><><EFBFBD><EFBFBD> FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʶ */
uint8_t Callback_isPingCheckReady = 0;
/* <20>Լ<EFBFBD>ģʽ <20><>ʶ */
uint8_t PC_isConnected = 0;
uint8_t is_jump_main = 0;
static BSP_BTN_EVENT_t BTN_Event;
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
int ebyte_main( void )
{
/* Init Systick */
systick_config();
/* <20><><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>Դ <20><>ʼ<EFBFBD><CABC> */
Ebyte_BSP_Init();
/* (<28><>ѡ) <20><><EFBFBD><EFBFBD><EFBFBD>жϽ<D0B6><CFBD><EFBFBD>FIFO <20>ɸ<EFBFBD><C9B8><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>д<EFBFBD><D0B4><EFBFBD> */
Ebyte_FIFO_Init( &hfifo, EBYTE_FIFO_SIZE );
/* EBYTE <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC> */
Ebyte_RF.Init();
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
Ebyte_RF.EnterReceiveMode( 0 );
EBYTE_LOG( "Start PingPong.....\r\n" );
EBYTE_LOG( "Please push button1 or button2.....\r\n" );
while( !is_jump_main ) {
/* <20><><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD>Ӧ */
Task_Button();
/* <20><><EFBFBD><EFBFBD>:<3A><><EFBFBD>⴮<EFBFBD><E2B4AE><EFBFBD><EFBFBD><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD>߷<EFBFBD><DFB7><EFBFBD> <20>ͻ<EFBFBD><CDBB>밴<EFBFBD><EBB0B4><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD> */
Task_Transmit();
/* <20><><EFBFBD><EFBFBD>:EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>޸<EFBFBD> */
Ebyte_RF.StartPollTask();
delay_1ms(100);
}
Ebyte_RF.EnterStandby(0);
Ebyte_BSP_Deinit();
systick_deinit();
}
/* !
* @brief <20><>ѯ<EFBFBD><D1AF><EFBFBD><EFBFBD> <20><><EFBFBD>ڽ<EFBFBD><DABD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>ģ<EFBFBD>鷢<EFBFBD><E9B7A2>
*
* @note <20><><EFBFBD><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>͵<EFBFBD><CDB5><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߴ<EFBFBD><DFB4>俪<EFBFBD><E4BFAA>
* ע<><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ģʽ<C4A3>л<EFBFBD><D0BB><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¿<EFBFBD><C2BF>Դ<EFBFBD><D4B4>ڽ<EFBFBD><DABD><EFBFBD>/<2F><><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ: <20><><EFBFBD><EFBFBD>ģʽ-><3E><><EFBFBD><EFBFBD>ģʽ-><3E><><EFBFBD><EFBFBD>ģʽ
*/
void Task_Transmit( void )
{
uint16_t length = 0;
uint8_t pcEchoLength = 0;
uint8_t pongLength = 0;
/* <20>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>ߴ<EFBFBD><DFB4><EFBFBD> (<28><><EFBFBD>Դ<EFBFBD><D4B4>ڽ<EFBFBD><DABD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD>) */
Ebyte_FIFO_GetDataLength( &hfifo, &length );
/* <20>漰<EFBFBD><E6BCB0><EFBFBD>첽<EFBFBD>ж<EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE> <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
1; <20><><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ѿ<EFBFBD><D1BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD>֡<EFBFBD><D6A1><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߷<EFBFBD><DFB7><EFBFBD>( <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>֡<EFBFBD><D6A1>ʽ,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ᵼ<EFBFBD><E1B5BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ճ<EFBFBD><D5B3> <20><><EFBFBD><EFBFBD><EFBFBD>ݾ<EFBFBD><DDBE><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD>п<EFBFBD><D0BF><EFBFBD>֡<EFBFBD>ж<EFBFBD> )
2: <20><><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD><DDB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ѿ<EFBFBD><D1BE>˳<EFBFBD><CBB3>˽<EFBFBD><CBBD><EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ( <20>ᵼ<EFBFBD><E1B5BC>FIFOʣ<4F><CAA3>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߷<EFBFBD><DFB7><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ݾ<EFBFBD><DDBE><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD>п<EFBFBD><D0BF><EFBFBD>֡<EFBFBD>ж<EFBFBD> )*/
if( ( length != 0 && Uart_isRecvReady ) || ( length != 0 && FIFO_isTimeCheckReady ) )
{
Ebyte_BSP_LedControl( BSP_LED_1, ON );
/* <20><>ȡFIFO <20><><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD>TxBuffer */
Ebyte_FIFO_Read( &hfifo, TxBuffer, length );
/* PC<50><43><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>Ӧ */
if( Ebyte_DEBUG_CommandEcho( TxBuffer,length, PcEchoBuffer, &pcEchoLength ) )
{
Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength);
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͸<EFBFBD><CDB8> */
else
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD>з<EFBFBD><D0B7><EFBFBD> */
Ebyte_RF.Send( TxBuffer, length, 0 );
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
Ebyte_RF.EnterReceiveMode( 0 );
}
/* ÿ<><C3BF><EFBFBD><EFBFBD>һ֡<D2BB>ͼ<EFBFBD><CDBC><EFBFBD>֡<EFBFBD><D6A1><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>жϿ<D0B6><CFBF><EFBFBD><EFBFBD>Ѿ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>˶<EFBFBD>֡ */
if( Uart_isRecvReady ) Uart_isRecvReady --;
if( FIFO_isTimeCheckReady ) FIFO_isTimeCheckReady = 0;
Ebyte_BSP_LedControl( BSP_LED_1, OFF );
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɻص<C9BB><D8B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>⵽<EFBFBD><E2B5BD> ping <20><><EFBFBD><EFBFBD> <20>ظ<EFBFBD> pong */
if( Callback_isPingCheckReady )
{
if( PC_isConnected )
{
pongLength = 5;
}else{
EBYTE_LOG( " Echo : pong \r\n" );
pongLength = 4;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD>з<EFBFBD><D0B7><EFBFBD> */
Ebyte_RF.Send( BufferPong, pongLength, 0 );
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
Ebyte_RF.EnterReceiveMode( 0 );
Callback_isPingCheckReady = 0;
}
}
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD>Ӧ
*/
void Task_Button( void )
{
uint8_t pcEchoLength = 0;
uint8_t pingLength = 0;
if( ! Ebyte_BTN_FIFO_Pop( &BSP_BTN_FIFO, &BTN_Event ) )
{
switch( BTN_Event )
{
/* <20><><EFBFBD><EFBFBD>1 <20>̰<EFBFBD> */
case BTN_1_SHORT:
Ebyte_BSP_LedControl( BSP_LED_1, ON );
if( PC_isConnected )
{
/* ֪ͨPC */
Ebyte_DEBUG_CommandEcho( (uint8_t*)SimulatedCommandsButton1, EBYTE_CMD_PACKAGE_LENGTH , PcEchoBuffer, &pcEchoLength );
Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength);
BufferPing[4] = 0x01;
pingLength = 5;
}else
{
EBYTE_LOG( "\r\n Send Command : ping \r\n" );
pingLength = 4;
}
/* <20><><EFBFBD><EFBFBD> ping */
Ebyte_RF.Send( BufferPing, pingLength, 0 );
Ebyte_RF.EnterReceiveMode( 0 );
Ebyte_BSP_LedControl( BSP_LED_1, OFF );
break;
/* <20><><EFBFBD><EFBFBD>1 <20><><EFBFBD><EFBFBD> */
case BTN_1_LONG:
Ebyte_BSP_LedControl( BSP_LED_1, TOGGLE );
break;
/* <20><><EFBFBD><EFBFBD>2 <20>̰<EFBFBD> */
case BTN_2_SHORT:
Ebyte_BSP_LedControl( BSP_LED_2, ON );
if( PC_isConnected )
{
/* ֪ͨPC */
Ebyte_DEBUG_CommandEcho( (uint8_t*)SimulatedCommandsButton2, EBYTE_CMD_PACKAGE_LENGTH , PcEchoBuffer, &pcEchoLength );
Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength);
BufferPing[4] = 0x02;
pingLength = 5;
}else
{
EBYTE_LOG( "\r\n Send Command : ping \r\n" );
pingLength = 4;
}
/* <20><><EFBFBD><EFBFBD> ping */
Ebyte_RF.Send( BufferPing, pingLength, 0 );
Ebyte_RF.EnterReceiveMode( 0 );
Ebyte_BSP_LedControl( BSP_LED_2, OFF );
break;
/* <20><><EFBFBD><EFBFBD>2 <20><><EFBFBD><EFBFBD> */
case BTN_2_LONG:
Ebyte_BSP_LedControl( BSP_LED_2, TOGGLE );
break;
default :
break;
}
}
}

107
MBL/source_ns/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.c Executable file
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/* Includes ------------------------------------------------------------------*/
#include "ebyte_kfifo.h"
uint8_t Ebyte_FIFO_Init( Ebyte_FIFO_t *fifo, uint16_t size )
{
uint8_t result = 0;
if( ( size & ( size - 1 ) ) != 0 ) //Warning ! Size must be 2^n ! Please view linux kfifo
{
result = 1;
}
fifo->size = size;
fifo->in = 0;
fifo->out = 0;
return result;
}
uint8_t Ebyte_FIFO_Write( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length )
{
uint8_t result = 0;
uint32_t i, j;
uint16_t endLength, orgLength;
uint8_t *pFifoBuffer;
orgLength = length;
/* calculate the length of data that can be written */
length = MIN( length, fifo->size - fifo->in + fifo->out );
/* first put the data starting from fifo->in to buffer end */
endLength = MIN( length, fifo->size - ( fifo->in & ( fifo->size - 1 ) ) );
pFifoBuffer = fifo->buffer + ( fifo->in & ( fifo->size - 1 ) );
for( i = 0; i < endLength; i++ )
{
*( pFifoBuffer++ ) = *( pData++ );
}
/* then put the rest (if any) at the beginning of the buffer */
j = length - endLength;
if ( j > 0 )
{
pFifoBuffer = fifo->buffer;
for( i = 0; i < j; i++ )
{
*( pFifoBuffer++ ) = *( pData++ );
}
}
fifo->in += length;
if( length < orgLength )
{
result = 1; // Means fifo is full , some data can not be written in
}
return result;
}
uint8_t Ebyte_FIFO_Read( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length )
{
uint8_t result = 0;
uint16_t i, j;
uint16_t endLength, orgLength;
uint8_t *pFifoBuffer;
orgLength = length;
length = MIN( length, fifo->in - fifo->out );
/* first get the data from fifo->out until the end of the buffer */
endLength = MIN( length, fifo->size - ( fifo->out & ( fifo->size - 1 ) ) );
pFifoBuffer = fifo->buffer + ( fifo->out & ( fifo->size - 1 ) );
for( i = 0; i < endLength; i++ )
{
*( pData++ ) = *( pFifoBuffer++ );
}
/* then get the rest (if any) from the beginning of the buffer */
j = length - endLength;
if ( j > 0 )
{
pFifoBuffer = fifo->buffer;
for( i = 0; i < j; i++ )
{
*( pData++ ) = *( pFifoBuffer++ ) ;
}
}
fifo->out += length;
if( length < orgLength )
{
result = 1; // not enough data
}
return result;
}
uint8_t Ebyte_FIFO_GetDataLength( Ebyte_FIFO_t *fifo, uint16_t *pLength )
{
uint8_t result = 0;
*pLength = ( fifo->in - fifo->out );
return result;
}
uint8_t Ebyte_FIFO_Clear( Ebyte_FIFO_t *fifo )
{
uint8_t result = 0;
fifo->in = 0;
fifo->out = 0;
return result;
}

19
MBL/source_ns/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.h Executable file
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#include "board.h"
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#define EBYTE_FIFO_SIZE 64 // Warning ! Size must be 2^n ! Please view linux kfifo
typedef struct
{
uint32_t in;
uint32_t out;
uint32_t size;
uint8_t buffer[EBYTE_FIFO_SIZE];
} Ebyte_FIFO_t;
uint8_t Ebyte_FIFO_Init( Ebyte_FIFO_t *fifo, uint16_t size );
uint8_t Ebyte_FIFO_Write( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length );
uint8_t Ebyte_FIFO_GetDataLength( Ebyte_FIFO_t *fifo, uint16_t *pLength );
uint8_t Ebyte_FIFO_Read( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length );
uint8_t Ebyte_FIFO_Clear( Ebyte_FIFO_t *fifo );

122
MBL/source_ns/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.c Executable file
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/**
**********************************************************************************
* @file board.c
* @brief E15-EVB02 <20><><EFBFBD><EFBFBD>ģʽ
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-20
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "ebyte_core.h"
#include "ebyte_debug.h"
extern unsigned char PC_isConnected;
const unsigned char SimulatedCommandsButton1[5] = { EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_TEST_BUTTON,
0x01
};
const unsigned char SimulatedCommandsButton2[5] = { EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_TEST_BUTTON,
0x02
};
const unsigned char SimulatedCommandsWireless1[5] = { EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_TEST_WIRELESS,
0x01
};
const unsigned char SimulatedCommandsWireless2[5] = { EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_TEST_WIRELESS,
0x02
};
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* @param rxBuffer <20><><EFBFBD>ܺ<EFBFBD><DCBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>
* @param length rxBuffer<65><72><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
* @param txBuffer <20><>Ӧ<EFBFBD><D3A6><EFBFBD>ݰ<EFBFBD> <20><><EFBFBD><EFBFBD>>10
* @param tLength <20><>Ӧ<EFBFBD><D3A6><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>
* @return 0:δ<><CEB4><EFBFBD>⵽<EFBFBD><E2B5BD><EFBFBD><EFBFBD> 1:<3A><><EFBFBD>⵽<EFBFBD><E2B5BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
unsigned char Ebyte_DEBUG_CommandEcho( unsigned char *rxBuffer , unsigned char length, unsigned char *txBuffer, unsigned char *tLength)
{
unsigned char result = 0;
unsigned char *p;
unsigned char tmp,version;
unsigned long name;
/* ֻ<><D6BB><EFBFBD>Ĺ̶<C4B9><CCB6><EFBFBD><EFBFBD><EFBFBD>Ϊ10<31><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡ <20><><EFBFBD><EFBFBD>ʱ<EFBFBD>䳤 ճ<><D5B3><EFBFBD><EFBFBD><EFBFBD>ʺ<EFBFBD>С*/
if( length == EBYTE_CMD_PACKAGE_LENGTH )
{
p = rxBuffer;
if( *p++== EBYTE_CMD_PACKAGE_START && *p++== EBYTE_CMD_PACKAGE_START && *p++== EBYTE_CMD_PACKAGE_START)
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>ֽ<EFBFBD> ָ<><D6B8><EFBFBD><EFBFBD> */
tmp = *p;
switch( tmp )
{
case EBYTE_CMD_TEST_MODE:
name = Ebyte_RF.GetName();
version = Ebyte_RF.GetDriverVersion();
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_TEST_MODE;
*txBuffer++ = (unsigned char)(name>>24);
*txBuffer++ = (unsigned char)(name>>16);
*txBuffer++ = (unsigned char)(name>>8);
*txBuffer++ = (unsigned char)(name);
*txBuffer++ = version;
*tLength = EBYTE_CMD_PACKAGE_LENGTH;
PC_isConnected = 1; //ģʽ<C4A3><CABD><EFBFBD><EFBFBD>
break;
case EBYTE_CMD_TEST_BUTTON:
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_TEST_BUTTON;
*txBuffer = *++p;
*tLength = EBYTE_CMD_PACKAGE_LENGTH;
break;
case EBYTE_CMD_TEST_WIRELESS:
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_TEST_WIRELESS;
*txBuffer = *++p;
*tLength = EBYTE_CMD_PACKAGE_LENGTH;
break;
}
result = 1;
}
}
return result;
}

14
MBL/source_ns/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.h Executable file
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#define EBYTE_CMD_PACKAGE_START 0xC5
#define EBYTE_CMD_PACKAGE_LENGTH 0x0A
#define EBYTE_CMD_TEST_MODE 0x01
#define EBYTE_CMD_TEST_BUTTON 0x02
#define EBYTE_CMD_TEST_WIRELESS 0x03
extern const unsigned char SimulatedCommandsButton1[5];
extern const unsigned char SimulatedCommandsButton2[5];
extern const unsigned char SimulatedCommandsWireless1[5];
extern const unsigned char SimulatedCommandsWireless2[5];
unsigned char Ebyte_DEBUG_CommandEcho( unsigned char *rxBuffer , unsigned char length, unsigned char *txBuffer, unsigned char *tLength);

431
MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.c Executable file
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/**
**********************************************************************************
* @file board.c
* @brief E15-EVB02 <20>弶<EFBFBD><E5BCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-06
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "board.h"
#include "ebyte_port.h"
#include "ebyte_conf.h"
#include "gd32w51x_gpio.h"
#include "gd32w51x_misc.h"
#include "gd32w51x_rcu.h"
#include "gd32w51x_spi.h"
#include "gd32w51x_timer.h"
#include "platform_def.h"
BSP_BTN_FIFO_t BSP_BTN_FIFO;
/*!< @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> <20><><EFBFBD>ڶ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ж<EFBFBD> <20>ݼ<EFBFBD> */
volatile uint32_t Ebyte_TimerDelayCounter = 0;
/* !
* @brief <20>ڲ<EFBFBD>ʱ<EFBFBD>ӳ<EFBFBD>ʼ<EFBFBD><CABC>
*/
void Ebyte_BSP_HSI_Init(void)
{
// /* <20>ڲ<EFBFBD> 16M HSI ʱ<><CAB1> */
// CLK_SYSCLKSourceConfig( CLK_SYSCLKSource_HSI );
//
// /* 1<><31>Ƶ 16M/1 */
// CLK_SYSCLKDivConfig( CLK_SYSCLKDiv_1 );
}
void Ebyte_BSP_E48xGPIO_Init(void)
{
rcu_periph_clock_enable(BSP_GPIO_RCU_E48_GPIO);
gpio_mode_set( BSP_GPIO_PORT_E48_GP0, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_GP0);
gpio_mode_set( BSP_GPIO_PORT_E48_NIRQ, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_NIRQ);
gpio_mode_set( BSP_GPIO_PORT_E48_GP3, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_GP3);
gpio_mode_set( BSP_GPIO_PORT_E48_GP4, GPIO_MODE_INPUT, GPIO_PUPD_NONE, BSP_GPIO_PIN_E48_GP4);
gpio_mode_set( BSP_GPIO_PORT_E48_GP5, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_GP5);
}
void Ebyte_BSP_E48xGPIO_Deinit(void)
{
rcu_periph_clock_disable(BSP_GPIO_RCU_E48_GPIO);
}
/* !
* @brief <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO
*
* @note Ŀ<><C4BF>Ӳ<EFBFBD><D3B2>: EBYTE E15-EVB02
*/
void Ebyte_BSP_GPIO_Init(void)
{
/* <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>״̬<D7B4><CCAC><EFBFBD><EFBFBD> */
Ebyte_BSP_E48xGPIO_Init();
/* LED */
rcu_periph_clock_enable(BSP_GPIO_RCU_E48_LED);
gpio_mode_set( BSP_GPIO_PORT_LED_1, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_LED_1 );
gpio_mode_set( BSP_GPIO_PORT_LED_2, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_LED_2 );
gpio_output_options_set(BSP_GPIO_PORT_LED_1, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, BSP_GPIO_PIN_LED_1);
gpio_output_options_set(BSP_GPIO_PORT_LED_2, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, BSP_GPIO_PIN_LED_2);
/* Button */
rcu_periph_clock_enable(BSP_GPIO_RCU_E48_BUTTON);
gpio_mode_set( BSP_GPIO_PORT_BUTTON_1, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_BUTTON_1);
// GPIO_Init( BSP_GPIO_PORT_BUTTON_2, BSP_GPIO_PIN_BUTTON_2, GPIO_Mode_In_PU_No_IT );
}
/* !
* @brief <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO
*
* @note Ŀ<><C4BF>Ӳ<EFBFBD><D3B2>: EBYTE E15-EVB02
*/
void Ebyte_BSP_GPIO_Deinit(void)
{
/* Button */
rcu_periph_clock_disable(BSP_GPIO_RCU_E48_BUTTON);
/* LED */
rcu_periph_clock_disable(BSP_GPIO_RCU_E48_LED);
/* E48 */
Ebyte_BSP_E48xGPIO_Deinit();
}
/* !
* @brief ͨ<>Ŵ<EFBFBD><C5B4>ڳ<EFBFBD>ʼ<EFBFBD><CABC>
*
* @note <20><>ע<EFBFBD>⣬<EFBFBD><E2A3AC>ͬ<EFBFBD><CDAC>MCU<43><55><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD>ӳ<EFBFBD><D3B3>
*/
void Ebyte_BSP_UART_Init( void )
{
// /* ʱ<><CAB1> */
// CLK_PeripheralClockConfig( BSP_USER_UART_CLOCK, ENABLE);
//
// /* GPIO */
// GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_UART_TX, BSP_GPIO_PIN_UART_TX, ENABLE );
// GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_UART_RX, BSP_GPIO_PIN_UART_RX, ENABLE );
//
// /* <20>˿<EFBFBD><CBBF><EFBFBD>ӳ<EFBFBD><D3B3> */
// SYSCFG_REMAPPinConfig( REMAP_Pin_USART1TxRxPortA, ENABLE );
//
// /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> E15-EVB02Ĭ<32>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD>9600 8N1 */
// USART_Init( BSP_USER_UART, BSP_USER_UART_BAUDRATE, USART_WordLength_8b, USART_StopBits_1, BSP_USER_UART_PARITY, (USART_Mode_TypeDef)(USART_Mode_Rx | USART_Mode_Tx ));//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>պͷ<D5BA><CDB7><EFBFBD>
//
// /* <20>򿪽<EFBFBD><F2BFAABD><EFBFBD><EFBFBD>ж<EFBFBD> */;
// USART_ITConfig( BSP_USER_UART, USART_IT_RXNE, ENABLE );
//
// /* <20><><EFBFBD><EFBFBD> ʹ<><CAB9> */
// USART_Cmd( BSP_USER_UART, ENABLE);
}
void Ebyte_BSP_ThreeLinesSPI_Init()
{
/* <20>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD>E49 GPIO<49><4F>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD> */
}
/* !
* @brief <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>ͨ<EFBFBD><CDA8>SPI<50>ӿڳ<D3BF>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
void Ebyte_BSP_SPI_Init( void )
{
spi_parameter_struct spi_init_struct;
/* ʱ<><CAB1> */
rcu_periph_clock_enable(BSP_RF_SPI_CLOCK);
rcu_periph_clock_enable(BSP_GPIO_RCU_E48_SPI);
/* SPI1 GPIO config: SCK/PB13, MISO/PB14, MOSI/PB15 */
gpio_af_set(BSP_GPIO_PORT_SPI, GPIO_AF_5, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_mode_set(BSP_GPIO_PORT_SPI, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_output_options_set(BSP_GPIO_PORT_SPI, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
/* SPI0_NSS */
gpio_mode_set(BSP_GPIO_PORT_SPI, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_SPI_NSS); //Ƭѡ CS
gpio_output_options_set(BSP_GPIO_PORT_SPI, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, BSP_GPIO_PIN_SPI_NSS);
// GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_SPI_SCK, BSP_GPIO_PIN_SPI_MOSI | BSP_GPIO_PIN_SPI_MISO | BSP_GPIO_PIN_SPI_SCK, ENABLE); // MOSI MISO SCK
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
spi_init_struct.device_mode = SPI_MASTER; //<2F><><EFBFBD><EFBFBD>ģʽ
spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; // Mode0 {CPOL=0, CPHA=0}
spi_init_struct.nss = SPI_NSS_SOFT; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƴӻ<C6B4>CSƬѡ
spi_init_struct.prescale = SPI_PSC_8; //16M/2 SCK<43><4B><EFBFBD><EFBFBD>
spi_init_struct.endian = SPI_ENDIAN_MSB; //<2F>Ӹ<EFBFBD>λ<EFBFBD><CEBB>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
spi_init(BSP_RF_SPI, &spi_init_struct);
/* ʹ<><CAB9> */
/* SPI enable */
spi_enable(BSP_RF_SPI);
}
/* !
* @brief <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>ͨ<EFBFBD><CDA8>SPI<50>ӿڳ<D3BF>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
void Ebyte_BSP_SPI_Deinit( void )
{
/* SPI enable */
spi_disable(BSP_RF_SPI);
spi_i2s_deinit(BSP_RF_SPI);
spi_parameter_struct spi_init_struct;
rcu_periph_clock_disable(BSP_RF_SPI_CLOCK);
}
/* !
* @brief RFģ<46><C4A3>SPIͨ<49><CDA8><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* @param data <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @return <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @note stm8l SPI<50>⺯<EFBFBD><E2BAAF><EFBFBD>е<EFBFBD>SPI_SendData()/SPI_ReceiveData() <20><><EFBFBD><EFBFBD>ֱ<EFBFBD><D6B1>ʹ<EFBFBD><CAB9>
*/
uint8_t Ebyte_BSP_SpiTransAndRecv( uint8_t data )
{
while(RESET == spi_i2s_flag_get(BSP_RF_SPI, SPI_FLAG_TBE));
spi_i2s_data_transmit(BSP_RF_SPI, data);
while(RESET == spi_i2s_flag_get(BSP_RF_SPI, SPI_FLAG_RBNE));
return spi_i2s_data_receive(BSP_RF_SPI);
// BSP_RF_SPI->DR = data;
// while ((BSP_RF_SPI->SR & SPI_FLAG_TXE) == RESET);
//
// while ((BSP_RF_SPI->SR & SPI_FLAG_RXNE) == RESET);
// return BSP_RF_SPI->DR;
}
/* !
* @brief <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>
*
* @note ʹ<><CAB9><EFBFBD><EFBFBD>TIM3<4D><33><EFBFBD><EFBFBD>1ms<6D><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
* TIM3<4D><33><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ΪHSI 16MHz, 128<32><38>Ƶ<EFBFBD><C6B5>Ϊ 16 MHz / 128 = 125 000 Hz
* Ŀ<>궨ʱ1ms <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڼ<EFBFBD>Ϊ ( 0.001 x 125000 - 1) = 124
*/
void Ebyte_BSP_TIMER_Init( void )
{
timer_parameter_struct timer_initpara;
/**
TIMER2 Configuration:
TIMER2CLK = SystemCoreClock/180 = 1MHz.
TIMER2 configuration is timing mode, and the timing is 1ms(1000/1 = 1ms).
*/
/* enable the peripherals clock */
rcu_timer_clock_prescaler_config(RCU_TIMER_PSC_MUL4);
rcu_periph_clock_enable(BSP_RF_TIMER_RCU);
/* deinit a TIMER */
timer_deinit(BSP_RF_TIMER);
/* initialize TIMER init parameter struct */
timer_struct_para_init(&timer_initpara);
/* TIMER2 configuration */
timer_initpara.prescaler = 179;
timer_initpara.alignedmode = TIMER_COUNTER_EDGE;
timer_initpara.counterdirection = TIMER_COUNTER_UP;
timer_initpara.period = 1000;
timer_initpara.clockdivision = TIMER_CKDIV_DIV1;
timer_init(BSP_RF_TIMER, &timer_initpara);
/* clear interrupt bit */
timer_interrupt_flag_clear(BSP_RF_TIMER, TIMER_INT_FLAG_UP);
/* enable the TIMER interrupt */
timer_interrupt_enable(BSP_RF_TIMER, TIMER_INT_UP);
/* enable a TIMER */
timer_enable(BSP_RF_TIMER);
nvic_irq_enable(TIMER2_IRQn, 0, 0);
}
/* !
* @brief <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>
*
* @note ʹ<><CAB9><EFBFBD><EFBFBD>TIM3<4D><33><EFBFBD><EFBFBD>1ms<6D><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
* TIM3<4D><33><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ΪHSI 16MHz, 128<32><38>Ƶ<EFBFBD><C6B5>Ϊ 16 MHz / 128 = 125 000 Hz
* Ŀ<>궨ʱ1ms <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڼ<EFBFBD>Ϊ ( 0.001 x 125000 - 1) = 124
*/
void Ebyte_BSP_TIMER_Deinit( void )
{
nvic_irq_disable(TIMER2_IRQn);
/* enable a TIMER */
timer_disable(BSP_RF_TIMER);
/* enable the TIMER interrupt */
timer_interrupt_disable(BSP_RF_TIMER, TIMER_INT_UP);
/* clear interrupt bit */
timer_interrupt_flag_clear(BSP_RF_TIMER, TIMER_INT_FLAG_UP);
/* enable the peripherals clock */
rcu_periph_clock_disable(BSP_RF_TIMER_RCU);
/* deinit a TIMER */
timer_deinit(BSP_RF_TIMER);
}
/* !
* @brief E15-EVB02 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>ʼ<EFBFBD><CABC>
*
* @note <20>ڲ<EFBFBD>ʱ<EFBFBD><CAB1>HSI x 16MHz
* <20>û<EFBFBD>ͨ<EFBFBD>Ŵ<EFBFBD><C5B4><EFBFBD> x USART1
* <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>ͨ<EFBFBD>Žӿ<C5BD> x SPI1
* <20><>ʱ<EFBFBD><CAB1> x TIM3
* <20><><EFBFBD><EFBFBD> x 2
* ָʾ<D6B8><CABE> x 2
*/
void Ebyte_BSP_Init( void )
{
/* ʱ<><CAB1> <20><>ʼ<EFBFBD><CABC> */
// Ebyte_BSP_HSI_Init();
/* IO <20><>ʼ<EFBFBD><CABC> */
Ebyte_BSP_GPIO_Init();
/* <20><><EFBFBD><EFBFBD> <20><>ʼ<EFBFBD><CABC> */
// Ebyte_BSP_UART_Init();
/* SPI<50>ӿ<EFBFBD> <20><>ʼ<EFBFBD><CABC> */
Ebyte_BSP_SPI_Init();
/* <20><>ʱ<EFBFBD><CAB1> <20><>ʼ<EFBFBD><CABC> */
Ebyte_BSP_TIMER_Init();
/* <20><><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD> <20><>ʼ<EFBFBD><CABC> */
Ebyte_BTN_FIFO_Init( &BSP_BTN_FIFO );
}
/* !
* @brief E15-EVB02 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>ʼ<EFBFBD><CABC>
*
* @note <20>ڲ<EFBFBD>ʱ<EFBFBD><CAB1>HSI x 16MHz
* <20>û<EFBFBD>ͨ<EFBFBD>Ŵ<EFBFBD><C5B4><EFBFBD> x USART1
* <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>ͨ<EFBFBD>Žӿ<C5BD> x SPI1
* <20><>ʱ<EFBFBD><CAB1> x TIM3
* <20><><EFBFBD><EFBFBD> x 2
* ָʾ<D6B8><CABE> x 2
*/
void Ebyte_BSP_Deinit( void )
{
/* <20><>ʱ<EFBFBD><CAB1> <20><>ʼ<EFBFBD><CABC> */
Ebyte_BSP_TIMER_Deinit();
/* SPI<50>ӿ<EFBFBD> <20><>ʼ<EFBFBD><CABC> */
Ebyte_BSP_SPI_Deinit();
/* <20><><EFBFBD><EFBFBD> <20><>ʼ<EFBFBD><CABC> */
// Ebyte_BSP_UART_Init();
/* IO <20><>ʼ<EFBFBD><CABC> */
Ebyte_BSP_GPIO_Deinit();
}
/* !
* @brief <20><><EFBFBD><EFBFBD>LED <20><>/<2F><>/<2F><>ת
*
* @param LEDx <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ŷ<EFBFBD><C5B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg BSP_LED_1 : LED1
* @arg BSP_LED_2 : LED2
*
* @param ctl <20><> / <20><>
* @arg OFF : <20><>
* @arg ON : <20><>
* @arg TOGGLE : <20><>ת
*/
void Ebyte_BSP_LedControl( BSP_LED_t LEDx , BSP_LED_Ctl_t ctl)
{
if( TOGGLE == ctl )
{
switch( LEDx )
{
case BSP_LED_1 : gpio_bit_toggle( BSP_GPIO_PORT_LED_1, BSP_GPIO_PIN_LED_1); break;
case BSP_LED_2 : gpio_bit_toggle( BSP_GPIO_PORT_LED_2, BSP_GPIO_PIN_LED_2); break;
default: break;
}
}
else
{
switch( LEDx )
{
case BSP_LED_1 : gpio_bit_write( BSP_GPIO_PORT_LED_1, BSP_GPIO_PIN_LED_1, (BitAction)ctl); break;
case BSP_LED_2 : gpio_bit_write( BSP_GPIO_PORT_LED_2, BSP_GPIO_PIN_LED_2, (BitAction)ctl); break;
default: break;
}
}
}
/* !
* @brief <20><><EFBFBD>ڶ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ĺ<EFBFBD><C4BA><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
*
* @param nTime <20><>λ:<3A><><EFBFBD><EFBFBD>
*/
void Ebyte_BSP_DelayMs( volatile uint32_t nTime )
{
Ebyte_TimerDelayCounter = nTime;
while( Ebyte_TimerDelayCounter !=0 );
}
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> <20><>ʱ<EFBFBD><CAB1><EFBFBD>жϵ<D0B6><CFB5><EFBFBD>
*/
void Ebyte_BSP_TimerDecrement(void)
{
if( Ebyte_TimerDelayCounter != 0 )
{
Ebyte_TimerDelayCounter--;
}
}
/* !
* @brief <20><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>״̬
*
* @param btn <20><>Ӧ<EFBFBD>İ<EFBFBD><C4B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg BSP_BUTTON_1 :<3A><><EFBFBD><EFBFBD>1
* @arg BSP_BUTTON_2 :<3A><><EFBFBD><EFBFBD>2
* @return 0:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>0:<3A><><EFBFBD><EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD>
* @note <20><><EFBFBD>ذ<EFBFBD><D8B0><EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD>ʱ IO<49><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬ <20><>Ϊ1<CEAA><31><EFBFBD><EFBFBD><EFBFBD>º<EFBFBD>IO<49>ӵ<EFBFBD> <20><>Ϊ0
*/
uint8_t Ebyte_BSP_ReadButton( BSP_BUTTON_t btn )
{
BitStatus result = RESET;
switch ( btn )
{
case BSP_BUTTON_1: result = gpio_input_bit_get( BSP_GPIO_PORT_BUTTON_1 , BSP_GPIO_PIN_BUTTON_1); break;
// case BSP_BUTTON_2: result = GPIO_ReadInputDataBit( BSP_GPIO_PORT_BUTTON_2 , BSP_GPIO_PIN_BUTTON_2); break;
default : break;
}
return result;
}
/* !
* @brief <20><><EFBFBD>ڷ<EFBFBD><DAB7>ͺ<EFBFBD><CDBA><EFBFBD>
*/
void Ebyte_BSP_UartTransmit( uint8_t *buffer , uint16_t length )
{
uint8_t i;
for( i = 0; i < length; i++ ) {
while(RESET == usart_flag_get(LOG_UART, USART_FLAG_TBE));
usart_data_transmit(LOG_UART, buffer[i]);
}
}

181
MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.h Executable file
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@ -0,0 +1,181 @@
/**
**********************************************************************************
* @file board.h
* @brief E15-EVB02 <20>弶<EFBFBD><E5BCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-06
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#ifndef __EBYTE_BOARD_H__
#define __EBYTE_BOARD_H__
#include <stdint.h>
#include <gd32w51x.h>
#include <systick.h>
#include "board_mini_printf.h"
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> LED */
#define BSP_GPIO_RCU_E48_LED RCU_GPIOB
#define BSP_GPIO_PORT_LED_1 GPIOB
#define BSP_GPIO_PIN_LED_1 GPIO_PIN_6
#define BSP_GPIO_PORT_LED_2 GPIOA
#define BSP_GPIO_PIN_LED_2 GPIO_PIN_15
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> */
#define BSP_GPIO_RCU_E48_BUTTON RCU_GPIOA
#define BSP_GPIO_PORT_BUTTON_1 GPIOA
#define BSP_GPIO_PIN_BUTTON_1 GPIO_PIN_2
//#define BSP_GPIO_PORT_BUTTON_2 GPIOA
//#define BSP_GPIO_PIN_BUTTON_2 GPIO_PIN_5
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SPIͨ<49>Žӿ<C5BD> */
#define BSP_GPIO_RCU_E48_SPI RCU_GPIOB
#define BSP_GPIO_PORT_SPI GPIOB
#define BSP_GPIO_PIN_SPI_NSS GPIO_PIN_12
#define BSP_GPIO_PIN_SPI_SCK GPIO_PIN_13
#define BSP_GPIO_PIN_SPI_MISO GPIO_PIN_14
#define BSP_GPIO_PIN_SPI_MOSI GPIO_PIN_15
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ͨ<>Ŵ<EFBFBD><C5B4><EFBFBD> */
#define BSP_GPIO_PORT_UART_TX GPIOA
#define BSP_GPIO_PIN_UART_TX GPIO_PIN_2
#define BSP_GPIO_PORT_UART_RX GPIOA
#define BSP_GPIO_PIN_UART_RX GPIO_PIN_3
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> EBYTE<54><45><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/* E48 */
#define BSP_GPIO_RCU_E48_GPIO RCU_GPIOC
#define BSP_GPIO_PORT_E48_GP0 GPIOC
#define BSP_GPIO_PIN_E48_GP0 GPIO_PIN_0
#define BSP_GPIO_PORT_E48_NIRQ GPIOC
#define BSP_GPIO_PIN_E48_NIRQ GPIO_PIN_1
#define BSP_GPIO_PORT_E48_GP3 GPIOC
#define BSP_GPIO_PIN_E48_GP3 GPIO_PIN_3
#define BSP_GPIO_PORT_E48_GP4 GPIOC
#define BSP_GPIO_PIN_E48_GP4 GPIO_PIN_4
#define BSP_GPIO_PORT_E48_GP5 GPIOC
#define BSP_GPIO_PIN_E48_GP5 GPIO_PIN_5
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SPI */
#define BSP_RF_SPI SPI1
#define BSP_RF_SPI_CLOCK RCU_SPI1
#define Ebyte_BSP_RfSpiSelected() gpio_bit_write( BSP_GPIO_PORT_SPI, BSP_GPIO_PIN_SPI_NSS, RESET )
#define Ebyte_BSP_RfSpiUnselected() gpio_bit_write( BSP_GPIO_PORT_SPI, BSP_GPIO_PIN_SPI_NSS, SET )
/* <20><><EFBFBD><EFBFBD> Timer */
#define BSP_RF_TIMER TIMER2
#define BSP_RF_TIMER_RCU RCU_TIMER2
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO */
///* E07 */
//#define Ebyte_BSP_RfBusyIoRead() gpio_input_bit_get( BSP_GPIO_PORT_BUSY , BSP_GPIO_PIN_BUSY)
//#define Ebyte_BSP_RfGdo0IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E07_GDO0 , BSP_GPIO_PIN_E07_GDO0)
//#define Ebyte_BSP_RfGdo1IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E07_GDO1 , BSP_GPIO_PIN_E07_GDO1)
///* E10 */
//#define Ebyte_BSP_E10IrqIoRead() gpio_input_bit_get( BSP_GPIO_PORT_E10_IRQ , BSP_GPIO_PIN_E10_IRQ)
//#define Ebyte_BSP_E10Dio2Read() gpio_input_bit_get( BSP_GPIO_PORT_E10_DIO2 , BSP_GPIO_PIN_E10_DIO2)
//#define Ebyte_BSP_E10Dio3Read() gpio_input_bit_get( BSP_GPIO_PORT_E10_DIO3 , BSP_GPIO_PIN_E10_DIO3)
//#define Ebyte_BSP_E10SdnIoLow() gpio_bit_write( BSP_GPIO_PORT_E10_SDN , BSP_GPIO_PIN_E10_SDN, RESET )
//#define Ebyte_BSP_E10SdnIoHigh() gpio_bit_write( BSP_GPIO_PORT_E10_SDN , BSP_GPIO_PIN_E10_SDN, SET )
///* E49 */
//#define Ebyte_BSP_E49Dio1IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E49_DIO1 , BSP_GPIO_PIN_E49_DIO1)
//#define Ebyte_BSP_E49Dio2IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E49_DIO2 , BSP_GPIO_PIN_E49_DIO2)
//#define Ebyte_BSP_E49FcsbIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_FCSB , BSP_GPIO_PIN_E49_FCSB, RESET )
//#define Ebyte_BSP_E49FcsbIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_FCSB , BSP_GPIO_PIN_E49_FCSB, SET )
//#define Ebyte_BSP_E49CsbIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_CSB , BSP_GPIO_PIN_E49_CSB, RESET )
//#define Ebyte_BSP_E49CsbIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_CSB , BSP_GPIO_PIN_E49_CSB, SET )
//#define Ebyte_BSP_E49SlckIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_SLCK , BSP_GPIO_PIN_E49_SLCK, RESET )
//#define Ebyte_BSP_E49SlckIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_SLCK , BSP_GPIO_PIN_E49_SLCK, SET )
//#define Ebyte_BSP_E49SdioIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO, RESET )
//#define Ebyte_BSP_E49SdioIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO, SET )
//#define Ebyte_BSP_E49SdioIoOutput() gpio_mode_set( BSP_GPIO_PORT_E49_SDIO, BSP_GPIO_PIN_E49_SDIO, GPIO_Mode_Out_PP_High_Fast )
//#define Ebyte_BSP_E49SdioIoInput() GPIO_Init( BSP_GPIO_PORT_E49_SDIO, BSP_GPIO_PIN_E49_SDIO, GPIO_Mode_In_FL_No_IT )
//#define Ebyte_BSP_E49SdioIoRead() GPIO_ReadInputDataBit( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO)
/* E48 */
#define Ebyte_BSP_E48GPIO4Read() gpio_input_bit_get( BSP_GPIO_PORT_E48_GP4 , BSP_GPIO_PIN_E48_GP4)
/* ȫ<><C8AB><EFBFBD>ж<EFBFBD> */
#define Ebyte_BSP_GlobalIntEnable() __enable_irq()
#define Ebyte_BSP_GlobalIntDisable() __disable_irq()
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> UART */
#define BSP_USER_UART USART1
#define BSP_USER_UART_CLOCK CLK_Peripheral_USART1
#define BSP_USER_UART_BAUDRATE 9600 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define BSP_USER_UART_PARITY USART_Parity_No //USART_Parity_No:<3A><>У<EFBFBD><D0A3> USART_Parity_Even:<3A><>У<EFBFBD><D0A3> USART_Parity_Odd:żУ<C5BC><D0A3>
#define BSP_USER_UART_IRQ USART1_RX_IRQn //<2F>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>
#define BSP_USER_UART_IRQ_LEVEL ITC_PriorityLevel_2 //<2F><><EFBFBD>ȼ<EFBFBD>
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD> */
#define BSP_BTN_FIFO_LENGTH 16
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>Դ<EFBFBD>ӡ<EFBFBD><D3A1>Ϣ <20>رմ<D8B1>ӡ<EFBFBD><D3A1>Ҫע<D2AA>͵<EFBFBD><CDB5>궨<EFBFBD><EAB6A8> EBYTE_DEBUG */
#define EBYTE_DEBUG
#ifdef EBYTE_DEBUG
#define DEBUG(format, ...) mprintf(format, ##__VA_ARGS__)
#else
#define DEBUG(...)
#endif
typedef enum { BSP_LED_1 = 0, BSP_LED_2 } BSP_LED_t;
typedef enum { OFF = 0, ON , TOGGLE} BSP_LED_Ctl_t;
typedef enum { UART_8N1 = 0, UART_8O1, UART_8E1 } BSP_UART_Parity_t;
typedef enum { BSP_BUTTON_1 = 0, BSP_BUTTON_2 } BSP_BUTTON_t;
typedef enum
{
BTN_1_SHORT, //<2F><><EFBFBD><EFBFBD>1 <20>̰<EFBFBD>
BTN_1_LONG, //<2F><><EFBFBD><EFBFBD>1 <20><><EFBFBD><EFBFBD>
BTN_2_SHORT, //<2F><><EFBFBD><EFBFBD>2 <20>̰<EFBFBD>
BTN_2_LONG, //<2F><><EFBFBD><EFBFBD>2 <20><><EFBFBD><EFBFBD>
}BSP_BTN_EVENT_t;
typedef struct
{
uint8_t fifoLen ;
uint8_t fifoRead ;
uint8_t fifoWrite ;
uint8_t buff[BSP_BTN_FIFO_LENGTH];
}BSP_BTN_FIFO_t;
extern BSP_BTN_FIFO_t BSP_BTN_FIFO;
void Ebyte_BSP_Init( void );
void Ebyte_BSP_Deinit( void );
void Ebyte_BTN_FIFO_Init(BSP_BTN_FIFO_t *fifo);
void Ebyte_BSP_DelayMs( volatile uint32_t nTime );
void Ebyte_BSP_TimerDecrement(void);
void Ebyte_BSP_LedControl( BSP_LED_t LEDx , BSP_LED_Ctl_t ctl);
void Ebyte_BSP_UartTransmit( uint8_t *buffer , uint16_t length );
uint8_t Ebyte_BSP_ReadButton( BSP_BUTTON_t btn );
uint8_t Ebyte_BSP_SpiTransAndRecv( uint8_t data );
uint8_t Ebyte_BTN_FIFO_Push(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t event);
uint8_t Ebyte_BTN_FIFO_Pop(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t *event);
uint32_t Ebyte_BSP_TimerGetTick(void);
#endif // !__EBYTE_BOARD_H__

147
MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.c Executable file
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/**
**********************************************************************************
* @file board_button.c
* @brief ͨ<><CDA8> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @author JiangHeng
* @date 2021-05-06
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "board.h"
#include "ebyte_kfifo.h"
#include "ebyte_core.h"
static uint16_t Button1_TickCounter = 0;
static uint16_t Button2_TickCounter = 0;
extern Ebyte_FIFO_t hfifo;
extern uint8_t FIFO_isTimeCheckReady;
static uint32_t FIFO_TickCounter = 0;
/* Private function prototypes -----------------------------------------------*/
void IT_Timer_ButtonCheck(void);
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>г<EFBFBD>ʼ<EFBFBD><CABC>
*
* @param fifo ָ<>򰴼<EFBFBD><F2B0B4BC>¼<EFBFBD><C2BC><EFBFBD><EFBFBD>нṹ<D0BD><E1B9B9><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
*/
void Ebyte_BTN_FIFO_Init(BSP_BTN_FIFO_t *fifo)
{
fifo->fifoLen = 0;
fifo->fifoRead = 0;
fifo->fifoWrite = 0;
}
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* @param fifo ָ<>򰴼<EFBFBD><F2B0B4BC>¼<EFBFBD><C2BC><EFBFBD><EFBFBD>нṹ<D0BD><E1B9B9><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
* @param event <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD> <20><>ҪΪ<D2AA><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ķ̰<C4B6>/<2F><><EFBFBD><EFBFBD>
* @return 0:<3A><><EFBFBD><EFBFBD> 1:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @note <20><><EFBFBD><EFBFBD>λ<EFBFBD>ÿ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ḳ<EFBFBD><E1B8B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ᵼ<EFBFBD><E1B5BC><EFBFBD><EFBFBD><EFBFBD>ݶ<EFBFBD>ʧ<EFBFBD><CAA7>
*/
uint8_t Ebyte_BTN_FIFO_Push(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t event)
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
fifo->fifoLen++;
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӳ<EFBFBD><D3B3>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD> */
if(fifo->fifoLen > BSP_BTN_FIFO_LENGTH)
{
fifo->fifoLen = BSP_BTN_FIFO_LENGTH;//<2F><><EFBFBD>ӳ<EFBFBD><D3B3>Ȳ<EFBFBD><C8B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
return 1;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
fifo->buff[fifo->fifoWrite] = event;
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD>Ѿ<EFBFBD><D1BE><EFBFBD><EFBFBD>˶<EFBFBD>β */
if(++fifo->fifoWrite >= BSP_BTN_FIFO_LENGTH)
{
fifo->fifoWrite = 0; //<2F><>ô<EFBFBD><C3B4>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>׿<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
}
return 0;
}
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>г<EFBFBD><D0B3><EFBFBD>
*
* @param fifo ָ<>򰴼<EFBFBD><F2B0B4BC>¼<EFBFBD><C2BC><EFBFBD><EFBFBD>нṹ<D0BD><E1B9B9><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
* @param event <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD> <20><>ҪΪ<D2AA><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ķ̰<C4B6>/<2F><><EFBFBD><EFBFBD>
* @return 0:<3A><><EFBFBD><EFBFBD> 1:<3A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>
*/
uint8_t Ebyte_BTN_FIFO_Pop(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t *event)
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӳ<EFBFBD><D3B3><EFBFBD>Ϊ0 <20><><EFBFBD>ն<EFBFBD><D5B6><EFBFBD> */
if(fifo->fifoLen == 0)
{
return 1;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD><EFBFBD>Լ<EFBFBD> */
fifo->fifoLen--;
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
*event = (BSP_BTN_EVENT_t )(fifo->buff[fifo->fifoRead]);
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD>Ѿ<EFBFBD><D1BE><EFBFBD><EFBFBD>˶<EFBFBD>β */
if(++fifo->fifoRead >= BSP_BTN_FIFO_LENGTH)
{
fifo->fifoRead = 0;//<2F><>ô<EFBFBD><C3B4>һ<EFBFBD>ν<EFBFBD><CEBD>Ӷ<EFBFBD><D3B6>׿<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
}
return 0;
}
/* !
* @brief <20><>ʱ<EFBFBD><CAB1><EFBFBD>ж<EFBFBD> ״̬<D7B4><CCAC> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
void IT_Timer_ButtonCheck(void)
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if (!Ebyte_BSP_ReadButton(BSP_BUTTON_1)) {
Button1_TickCounter++;
} else {
if (Button1_TickCounter > 1000) // 1<><31> <20><><EFBFBD><EFBFBD>
{
Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_1_LONG);
} else if (Button1_TickCounter > 50) // 50<35><30><EFBFBD><EFBFBD> <20>̰<EFBFBD>
{
Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_1_SHORT);
} else {
} // 50<35><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ϊ<EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
Button1_TickCounter = 0;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if (!Ebyte_BSP_ReadButton(BSP_BUTTON_2)) {
Button2_TickCounter++;
} else {
if (Button2_TickCounter > 1000) // 1<><31> <20><><EFBFBD><EFBFBD>
{
Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_2_LONG);
} else if (Button2_TickCounter > 50) // 50<35><30><EFBFBD><EFBFBD> <20>̰<EFBFBD>
{
Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_2_SHORT);
} else {
} // 50<35><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ϊ<EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
Button2_TickCounter = 0;
}
}

6
MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.h Executable file
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#ifndef __BOARD_BUTTON_H__
#define __BOARD_BUTTON_H__
void IT_Timer_ButtonCheck(void);
#endif // !__BOARD_BUTTON_H__

203
MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.c Executable file
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#include <stdio.h>
#include "stdarg.h"
#include "gd32w51x.h"
//#include "stm8l15x_usart.h"
#include "board_mini_printf.h"
#include "platform_def.h"
/* !
* @brief Ŀ<><C4BF>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD>Žӿ<C5BD>
*
* @param data д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 Byte
*/
static void send_uart_data(uint8_t data)
{
while(RESET == usart_flag_get(LOG_UART, USART_FLAG_TBE));
usart_data_transmit(LOG_UART, data);
}
/*
<20><><EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD>int<6E><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD>תΪ2<CEAA><32>8<EFBFBD><38>10<31><30>16<31><36><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>value --- <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>int<6E><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
str --- <20>洢ת<E6B4A2><D7AA><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
radix --- <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
ע<>⣺8λ<38><CEBB>Ƭ<EFBFBD><C6AC>int<6E>ֽ<EFBFBD>ֻռ2<D5BC><32><EFBFBD>ֽ<EFBFBD>
*/
static char *sky_itoa(int value, char *str, unsigned int radix)
{
char list[] = "0123456789ABCDEF";
unsigned int tmp_value;
int i = 0, j, k = 0;
// if (NULL == str) {
if (0 == str) {
// return NULL;
return 0;
}
if (2 != radix && 8 != radix && 10 != radix && 16 != radix) {
// return NULL;
return 0;
}
if (radix == 10 && value < 0) {
//ʮ<><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
tmp_value = (unsigned int)(0 - value);
str[i++] = '-';
k = 1;
} else {
tmp_value = (unsigned int)value;
}
//<2F><><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>洢
do {
str[i ++] = list[tmp_value%radix];
tmp_value /= radix;
} while(tmp_value);
str[i] = '\0';
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
char tmp;
for (j = k; j < (i+k)/2; j++) {
tmp = str[j];
str[j] = str[i-j-1+k];
str[i-j-1+k] = tmp;
}
return str;
}
/*
<20><><EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD>double<6C><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>תΪ<D7AA>ַ<EFBFBD><D6B7><EFBFBD>
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>value --- <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>double<6C><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
str --- <20>洢ת<E6B4A2><D7AA><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
eps --- <20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1>λѡ<CEBB><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٱ<EFBFBD><D9B1><EFBFBD>һ<EFBFBD><D2BB>С<EFBFBD><D0A1>λ,<2C><><EFBFBD>ౣ<EFBFBD><E0B1A3>4<EFBFBD><34>С<EFBFBD><D0A1>λ
ע<>⣺8λ<38><CEBB>Ƭ<EFBFBD><C6AC>int<6E>ֽ<EFBFBD>ֻռ2<D5BC><32><EFBFBD>ֽ<EFBFBD>
*/
static void sky_ftoa(double value, char *str, unsigned int eps)
{
unsigned int integer;
double decimal;
char list[] = "0123456789";
int i = 0, j, k = 0;
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
if (value < 0) {
decimal = (double)(((int)value) - value);
integer = (unsigned int)(0 - value);
str[i ++] = '-';
k = 1;
} else {
integer = (unsigned int)(value);
decimal = (double)(value - integer);
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>洢
do {
str[i ++] = list[integer%10];
integer /= 10;
} while(integer);
str[i] = '\0';
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
char tmp;
for (j = k; j < (i+k)/2; j++) {
tmp = str[j];
str[j] = str[i-j-1+k];
str[i-j-1+k] = tmp;
}
//<2F><><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
if (eps < 1 || eps > 4) {
eps = 4;
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>⣬<EFBFBD><E2A3AC>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>1.2<EFBFBD><EFBFBD><EFBFBD><EFBFBD>1.19<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
double pp = 0.1;
for (j = 0; j <= eps; j++) {
pp *= 0.1;
}
decimal += pp;
while (eps) {
decimal *= 10;
eps --;
}
int tmp_decimal = (int)decimal;
str[i ++] = '.';
k = i;
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>洢
do {
str[i ++] = list[tmp_decimal%10];
tmp_decimal /= 10;
} while(tmp_decimal);
str[i] = '\0';
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
for (j = k; j < (i+k)/2; j++) {
tmp = str[j];
str[j] = str[i-j-1+k];
str[i-j-1+k] = tmp;
}
str[i] = '\0';
}
void mprintf(char * Data, ...)
{
const char *s;
int d;
char buf[16];
uint8_t txdata;
va_list ap;
va_start(ap, Data);
while ( * Data != 0 ) {
if ( * Data == 0x5c ) {
switch ( *++Data ) {
case 'r':
txdata = 0x0d;
send_uart_data(txdata);
Data ++;
break;
case 'n':
txdata = 0x0a;
send_uart_data(txdata);
Data ++;
break;
default:
Data ++;
break;
}
} else if ( * Data == '%') {
switch ( *++Data ) {
case 's':
s = va_arg(ap, const char *);
for ( ; *s; s++) {
send_uart_data(*((uint8_t *)s));
}
Data++;
break;
case 'd':
d = va_arg(ap, int);
sky_itoa(d, buf, 10);
for (s = buf; *s; s++) {
send_uart_data(*((uint8_t *)s));
}
Data++;
break;
case 'x': {
d = va_arg(ap, int);
sky_itoa(d, buf, 16);
for (s = buf; *s; s++) {
send_uart_data(*((uint8_t *)s));
}
Data++;
break;
}
case 'f': {
double num = va_arg(ap, double);
sky_ftoa(num, buf, 4);
for (s = buf; *s; s++) {
send_uart_data(*((uint8_t *)s));
}
Data++;
break;
}
default:
Data++;
break;
}
} else {
send_uart_data(*((uint8_t *)Data));
Data++;
}
}
}

8
MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.h Executable file
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#ifndef __BOARD_PRINTF_H__
#define __BOARD_PRINTF_H__
void mprintf(char * Data, ...);
#define EBYTE_LOG printf
#endif // !__BOARD_PRINTF_H__

578
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h Executable file
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/*
* THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND
* (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
* CONSEQUENTLY, CMOSTEK SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* Copyright (C) CMOSTEK SZ.
*/
/*!
* @file CMT2310A_def.h
* @brief CMT2310A transceiver RF chip driver
*
* @version 1.0
* @date Dec 7 2021
* @author CMOSTEK R&D
*/
#ifndef __CMT2310A_DEF_H
#define __CMT2310A_DEF_H
//Exit State
#define EXIT_TO_SLEEP 1
#define EXIT_TO_READY 2
#define EXIT_TO_TFS 3
#define EXIT_TO_TX 4
#define EXIT_TO_RFS 5
#define EXIT_TO_RX 6
//Prefxi select
#define TX_PREFIX_SEL_0 0
#define TX_PREFIX_SEL_1 1
#define TX_PREFIX_SEL_PREAMBLE 2
//## interrupt source config
typedef union
{
struct
{
uint8_t PKT_DONE_EN: 1; //pkt_done_en //bit0
uint8_t CRC_PASS_EN: 1; //crc_pass_en //bit1
uint8_t ADDR_PASS_EN: 1; //node_address_pass_en //bit2
uint8_t SYNC_PASS_EN: 1; //sync_pass_en //bit3
uint8_t PREAM_PASS_EN: 1; //preamble_pass_en //bit4
uint8_t TX_DONE_EN: 1; //tx_done_en //bit5
uint8_t RX_TOUT_EN: 1; //rx_timeout_en //bit6
uint8_t SLP_TOUT_EN: 1; //sleep_timeout_en //bit7
uint8_t LD_STOP_EN: 1; //ld_stop_en(PLL lock detect)//bit0
uint8_t LBD_STOP_EN: 1; //lbd_stop_en //bit1
uint8_t LBD_STAT_EN: 1; //lbd_status_en //bit2
uint8_t PKT_ERR_EN: 1; //pkt_err_en //bit3
uint8_t RSSI_COLL_EN: 1; //rssi_collision_en //bit4
uint8_t OP_CMD_FAILED_EN: 1; //op_cmd_failed_en //bit5
uint8_t RSSI_PJD_EN: 1; //rssi_pjd_valid_en //bit6
uint8_t RESV_2_1: 1; //reserve, don't used //bit7
uint8_t SEQ_MATCH_EN: 1; //seq_match_en //bit0
uint8_t NACK_RECV_EN: 1; //nack_recv_en //bit1
uint8_t TX_RESEND_DONE_EN: 1; //tx_resend_done_en //bit2
uint8_t ACK_RECV_FAILED_EN: 1; //ack_recv_failed_en //bit3
uint8_t TX_DC_DONE_EN: 1; //tx_dc_done_en //bit4
uint8_t CSMA_DONE_EN: 1; //csma_max_en //bit5
uint8_t CCA_STAT_EN: 1; //cca_status_en //bit6
uint8_t API_DONE_EN: 1; //api_done_en //bit7
uint8_t TX_FIFO_TH_EN: 1; //tx_fifo_threshold_en //bit0
uint8_t TX_FIFO_NMTY_EN: 1; //tx_fifo_non_empty_en //bit1
uint8_t TX_FIFO_FULL_EN: 1; //tx_fifo_full_en //bit2
uint8_t RX_FIFO_OVF_EN: 1; //rx_fifo_overflow_en //bit3
uint8_t RESV_4_1: 1; //reserve, don't used //bit4
uint8_t RX_FIFO_TH_EN: 1; //rx_fifo_threshold_en //bit5
uint8_t RX_FIFO_NMTY_EN: 1; //rx_fifo_non_empty_en //bit6
uint8_t RX_FIFO_FULL_EN: 1; //rx_fifo_full_en //bit7
} _BITS;
struct
{
uint8_t INT_CTL1_REG; //CTL_REG_18, 0x12
uint8_t INT_CTL2_REG; //CTL_REG_21, 0x15
uint8_t INT_CTL3_REG; //CTL_REG_23, 0x17
uint8_t INT_CTL4_REG; //CTL_REG_14, 0x0E
} _BYTE;
} INT_SRC_CFG;
//## interrupt flag
typedef union
{
struct
{
uint8_t RESV_3: 3; //reserve, don't used //bit0/1/2
uint8_t TX_DONE_FLG: 1; //tx_done_flag //bit3
uint8_t RX_TMO_FLG: 1; //rx_timer_timeout_flag //bit4
uint8_t SLEEP_TMO_FLG: 1; //sleep_timer_timeout_flag //bit5
uint8_t RESV_2: 2; //reserve, don't used //bit6/7
uint8_t PKT_DONE_FLG: 1; //pkt_done_flag //bit0
uint8_t CRC_PASS_FLG: 1; //crc_pass_flag //bit1
uint8_t ADDR_PASS_FLG: 1; //addr_pass_flag //bit2
uint8_t SYNC_PASS_FLG: 1; //sync_pass_flag //bit3
uint8_t PREAM_PASS_FLG: 1; //preamble_pass_flag //bit4
uint8_t SYNC1_PASS_FLG: 1; //sync1_pass_flag //bit5
uint8_t RESV_2_2: 2; //reserve, don't used //bit6/7
uint8_t LBD_STATUS_FLG: 1; //lbd_status_flag //bit0
uint8_t PKT_ERR_FLG: 1; //pkt_err_flag //bit1
uint8_t RSSI_COLL_FLG: 1; //rssi_collision_flag //bit2
uint8_t OP_CMD_FAILED_FLG: 1; //op_cmd_failed_flag //bit3
uint8_t ANT_LOCK_FLG: 1; //ant_lock_flag //bit4
uint8_t RESV_3_3: 3; //reserve, don't used //bit5/6/7
uint8_t SEQ_MATCH_FLG: 1; //seq_match_flag //bit0
uint8_t NACK_RECV_FLG: 1; //nack_recv_flag //bit1
uint8_t TX_RESEND_DONE_FLG: 1; //tx_resend_max_flag //bit2
uint8_t ACK_RECV_FAILED_FLG: 1; //ack_recv_failed_flag //bit3
uint8_t TX_DC_DONE_FLG: 1; //tx_dc_done_flag //bit4
uint8_t CSMA_DONE_FLG: 1; //csma_done_flag //bit5
uint8_t CCA_STATUS_FLG: 1; //cca_status_flag //bit6
uint8_t API_DONE_FLG: 1; //api_done_flag //bit7
} _BITS;
struct
{
uint8_t INT_FLAG1_REG; //CTL_REG_24, 0x18
uint8_t INT_FLAG2_REG; //CTL_REG_26, 0x1A
uint8_t INT_FLAG3_REG; //CTL_REG_30, 0x1E
uint8_t INT_FLAG4_REG; //CTL_REG_32, 0x20
} _BYTE;
} INT_SRC_FLG;
//## interrupt clear
typedef union
{
struct
{
uint8_t TX_DONE_CLR: 1; //tx_done_clr //bit0
uint8_t RX_TMO_CLR: 1; //rx_timer_timeout_clr //bit1
uint8_t SLEEP_TMO_CLR: 1; //sleep_timer_timeout_clr //bit2
uint8_t RESV_5: 5; //reserve, don't used //bit3-7
uint8_t PKT_DONE_CLR: 1; //pkt_done_clr //bit0
uint8_t CRC_PASS_CLR: 1; //crc_pass_clr //bit1
uint8_t ADDR_PASS_CLR: 1; //addr_pass_clr //bit2
uint8_t SYNC_PASS_CLR: 1; //sync_pass_clr //bit3
uint8_t PREAM_PASS_CLR: 1; //preamble_pass_clr //bit4
uint8_t RESV_3: 3; //reserve, don't used //bit5/6/7
uint8_t LBD_STAT_CLR: 1; //lbd_status_clr //bit0
uint8_t PKT_ERR_CLR: 1; //packet_err_clr //bit1
uint8_t RSSI_COLL_CLR: 1; //rssi_collision_clr //bit2
uint8_t OP_CMD_FAILED_CLR: 1; //op_cmd_failed_clr //bit3
uint8_t ANT_LOCK_CLR: 1; //antenna_lock_clr //bit4
uint8_t RESV_2_3: 3; //reserve, don't used //bit5/6/7
uint8_t SEQ_MATCH_CLR: 1; //seq_match_clr //bit0
uint8_t NACK_RECV_CLR: 1; //nack_recv_clr //bit1
uint8_t TX_RESEND_DONE_CLR: 1; //tx_resend_done_clr //bit2
uint8_t ACK_RECV_FAILED_CLR: 1; //ack_recv_failed_clr //bit3
uint8_t TX_DC_DONE_CLR: 1; //tx_dc_done_clr //bit4
uint8_t CSMA_DONE_CLR: 1; //csma_done_clr //bit5
uint8_t CCA_STATUS_CLR: 1; //cca_status_clr //bit6
uint8_t API_DONE_CLR: 1; //api_done_clr //bit7
} _BITS;
struct
{
uint8_t INT_CLR1_REG; //CTL_REG_24, 0x18
uint8_t INT_CLR2_REG; //CTL_REG_25, 0x19
uint8_t INT_CLR3_REG; //CTL_REG_29, 0x1D
uint8_t INT_CLR4_REG; //CTL_REG_31, 0x1F
} _BYTE;
} INT_SRC_CLR;
//## fifo status flag
typedef union
{
struct
{
uint8_t TX_FIFO_TH_FLG: 1; //tx_fifo_threshold_flag //bit0
uint8_t TX_FIFO_NMTY_FLG: 1; //tx_fifo_non_empty_flag //bit1
uint8_t TX_FIFO_FULL_FLG: 1; //tx_fifo_full_flag //bit2
uint8_t RX_FIFO_OVF_FLG: 1; //rx_fifo_overflow_flag //bit3
uint8_t RESV_1: 1; //reserve, don't used //bit4
uint8_t RX_FIFO_TH_FLG: 1; //rx_fifo_threshold_flag //bit5
uint8_t RX_FIFO_NMTY_FLG: 1; //rx_fifo_non_empty_flag //bit6
uint8_t RX_FIFO_FULL_FLG: 1; //rx_fifo_full_flag //bit7
} _BITS;
uint8_t FIFO_FLG_REG; //CTL_REG_28, 0x1c
} FIFO_STATUS_FLG;
//## packet preamble config
typedef struct //Packet Preamble
{
uint8_t PREAM_LENG_UNIT; //0=preamble unit as 8bits, !0=preamble unit as 4bits (nibble mode)
uint8_t PREAM_VALUE; //preamble value
uint8_t RX_PREAM_SIZE; //rx preamble length, range: 0-31, 0==disable rx preamble detect
uint16_t TX_PREAM_SIZE; //tx preamble length //## note: for arm mcu uint16_t is 16bits
} PREAMBLE_CFG;
//## packet syncword config
typedef struct
{
union
{
struct
{
uint8_t SYNC_MAN_EN: 1; //sync word manchester coding enable
uint8_t SYNC_SIZE: 3; // n+1 bytes
uint8_t SYNC_TOL: 3; // n bits tolerence error
uint8_t SYNC_MODE_SEL: 1; // 0: compatible S2LP; 1: compatible 802.15.4
} _BITS;
uint8_t SYNC_CFG_REG; //CTL_REG_44, 0x2c
} SYN_CFG_u;
uint8_t SYNC_VALUE[8]; //CTL_REG_45-CTL_REG_53, 0x2D-0x34
uint8_t SYNC_FEC_VALUE[8]; //CTL_REG_53-CTL_REG_60, 0x35-0x3C
uint8_t SYNC_VALUE_SEL; // 0: select SYN_VAL; !0: select SYN_FEC_VAL
} SYNC_CFG;
//## packet node address config
typedef struct
{
union
{
struct
{
uint8_t ADDR_DET_MODE: 2; //node address mode: 0,disable; 1,only match; 2,add all 0; 3,add all 1 & 0
uint8_t ADDR_SIZE: 2; // n+1 bytes
uint8_t ADDR_ERR_MASK: 1; // 0: trigger PKT_ERR flag, when node address not match, and reset decode; 1: non-reset decode, when node address not match
uint8_t ADDR_FREE_EN: 1; // 0: disable; 1: enable node address match as stand-alone working
uint8_t ADDR_SPLIT_MODE: 1; // 0: disable, dest_addr==node_addr; 1: enable, node_addr==src_addr+des_addr
uint8_t RESV_1: 1;
} _BITS;
uint8_t ADDR_CFG_REG; //CTL_REG_64, 0x40
} ADDR_CFG_u;
uint8_t SRC_ADDR[2]; //CTL_REG_65, CTL_REG_66
uint8_t DEST_ADDR[2]; //CTL_REG_67, CTL_REG_68
uint8_t SRC_BITMASK[2]; //CTL_REG_69, CTL_REG_70
uint8_t DEST_BITMASK[2]; //CTL_REG_71, CTL_REG_72
} ADDR_CFG;
//## packet crc config
typedef struct
{
union
{
struct
{
uint8_t CRC_EN: 1; // 0:disable CRC; 1:enable CRC
uint8_t CRC_BIT_ORDER: 1; // 0:crc result MSB output first; 1:crc result LSB output first; active unit is byte
uint8_t CRC_REFIN: 1; // 0:normal input; 1:inverse input;
uint8_t CRC_RANGE: 1; // 0:whole payload; 1:only data
uint8_t CRC_BIT_INV: 1; // 0:crc result non-invert; 1:crc result all bits invert
uint8_t CRC_BYTE_SWAP: 1; // 0:crc result HighByte output first; 1:crc result LowByte output first
uint8_t CRC_SIZE: 2; // 0:crc8; 1:crc16; 2:crc24; 3:crc32
uint8_t CRC_REFOUT: 1; // 0:result whole bit MSB->LSB 1:result whole bit LSB->MSB
uint8_t CRCERR_CLR_FIFO_EN: 1; // 0:disable 1:enable when crc error, clear fifo function
uint8_t RESV_6: 6;
} _BITS;
uint16_t CRC_CFG_REG; //CTL_REG_73, 0x49 & CTL_REG_82[7] & CTL_REG_84[7]
} CRC_CFG_u;
union //CTL_REG_74-CTL_REG_77, 0x4A-0x4D //## note: for arm mcu uint32_t is 32bits
{
uint8_t u8_SEED[4];
uint32_t u32_SEED;
} CRC_SEED_u;
union //CTL_REG_78-CTL_REG_81, 0x4E-0x51 //## note: for arm mcu uint32_t is 32bits
{
uint8_t u8_POLY[4];
uint32_t u32_POLY;
} CRC_POLY_u;
} CRC_CFG;
//## packet encode/decode format config
typedef struct
{
union
{
struct
{
uint8_t MANCH_EN: 1; // 0:disable manchester coding; 1:enable manchester coding
uint8_t MANCH_TYPE: 1; // 0: 2'b01=1, 2'b10=0; 1: 2'b01=0, 2'b10=1
uint8_t WHITEN_EN: 1; // 0:disable whiten coding; 1:enable whiten coding
uint8_t WHITEN_TYPE: 2; // 0:PN9-CCITT, 1:PN9-IBM, 2:PN7, 3:NA
uint8_t WHITEN_SEED_TYP: 1; // 0:compatible A7139; 1:customer seed; note: when select PN7 active
uint8_t RESV_2: 2;
uint8_t FEC_EN: 1; // 0:disable FEC Coding; 1:enable FEC Coding
uint8_t FEC_RSC_NRNSC_SEL: 1; // 0:RSC Mode; 1:NRNSC Mode
uint8_t RESV_5: 5;
uint8_t FEC_TICC: 1; // 0:ui invert ouput in FEC calucate; 1:ui non-invert ouput in FEC calucate
} _BITS;
uint16_t CODING_CFG_REG; // CTL_REG_82, 0x52 & CTL_REG_93, 0x5D
} CODING_FORMAT_CFG_u;
uint16_t WHITEN_SEED; // CTL_REG_83, 0x53 & CTL_REG_82[6]
uint16_t FEC_PAD_CODE; // CTL_REG_94, 0x5E & CTL_REG_93[6:2], 0x5D
} CODING_FORMAT_CFG;
//## frame struct config
typedef struct
{
uint8_t DATA_MODE; //0: direct mode; 2: packet mode; 1&3: na
union
{
struct
{
uint8_t PKT_TYPE: 1; //0: fixed length; 1: variable length
uint8_t PAYLOAD_BIT_ORDER: 1; //0: MSB output first; 1: LSB output first
uint8_t ADDR_LEN_CONF: 1; //0: node_addr+length; 1: length+node_addr
uint8_t ADDR_FIELD_EN: 1; //0: disable; 1: enable address field
uint8_t PAGGYBACKING_EN: 1; //0: disable 1: enable
uint8_t LENGTH_SIZE: 1; //0: length range 1 byte; 1: length range 2 bytes
uint8_t RESV_1_2: 1;
uint8_t INTERLEAVE_EN: 1; //0: disable interleave 1: enable interleave
} _BITS;
uint8_t FRAME_CFG1_REG; //CTL_REG_63, 0x3F
} FRAME_CFG1_u;
union
{
struct
{
uint8_t TX_PREFIX_TYPE: 2; //0:transmit_0; 1:transmit_1; 2:transmit_preamble 3:NA
uint8_t SEQNUM_EN: 1; //0:disable; 1:enable; note: SEQ_NUM is the same with FCS1
uint8_t SEQNUM_AUTO_INC: 1; //0:disable SEQNUM increase; 1:enable
uint8_t SEQNUM_SIZE: 1; //0:1byte for SEQNUM; 1:2bytes for SEQNUM
uint8_t SEQNUM_MACH_EN: 1; //0:disable; 1:enable compare with local SEQNUM, when TX_ACK enable
uint8_t FCS2_EN: 1; //0:not include FCS2 filed; 1:include FCS2 filed
uint8_t RESV_1: 1;
} _BITS;
uint8_t FRAME_CFG2_REG; //CTL_REG_84, 0x54
} FRAME_CFG2_u;
uint16_t TX_PKT_NUM; //CTL_REG_85, 0x55[7:0] & CTL_REG_86, 0x56[15:8]
uint16_t SEQNUM_TX_IN; //CTL_REG_88/87, 0x58[15:8], 0x57[7:0]
uint16_t SEQNUM_TX_CURRENT_OUT; //CTL_REG_39/38, 0x27[15:8]/0x26[7:0]
uint8_t TX_PKT_GAP; //CTL_REG_89, 0x59
uint8_t FCS2_TX_IN; //CTL_REG_91, 0x5B
uint8_t FCS2_RX_OUT; //CTL_REG_92, 0x5C
uint16_t PAYLOAD_LENGTH; //CTL_REG_62/61, 0x3E[15:8], 0x3D[7:0]
} FRAME_CFG;
//## Wi-SUN V1.0 packet format compatible
typedef union
{
struct
{
uint8_t WISUN_DW: 1; // 0:not whiten, 1: whiten
uint8_t WISUN_FCS: 1; // 0:CRC-32 for PSDU, 1: CRC-16 for PSDU
uint8_t RESV_2: 2; //
uint8_t WISUN_MS: 1; // default for 0
uint8_t WHITEN_WISUN: 1; // 0: for normal used, 1: for Wi-SUN whitenning
uint8_t WISUN_ALLIN: 1; // 0: WISUN_FCS & WISUN_DW not active, 1: FCS & DW depend on WISUN_FCS & WISUN_DW,
uint8_t LENGTH_MODE: 1; // 0: for normal used, 1: for Wi-SUN used, PSDU length filed is 11bits
} _BITS;
uint8_t WI_SUN_REG; //CTL_REG_111, 0x6F
} WI_SUN_CFG;
//## working mode
typedef struct
{
union
{
struct
{
uint8_t TX_DC_EN: 1; //0:disable TxDutyCycle; 1:enable
uint8_t TX_DC_PERSIST_EN: 1; //0:run TX_DC_TIMES; 1:always run until this bit set 0
uint8_t TX_ACK_EN: 1; //0:disable 1:enable
uint8_t TX_AUTO_HOP_EN: 1; //0:disable 1:enable tx frequency auto hopping
uint8_t TX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
uint8_t RESV: 1;
} _BITS;
uint8_t WORK_MODE_CFG1_REG; //CTL_REG_96, 0x60
} WORK_MODE_CFG1_u;
union
{
struct
{
uint8_t RX_DC_EN: 1; //0:disable RxDutyCycle; 1:enable
uint8_t RX_AUTO_HOP_EN: 1; //0:disable RxAutoHop; 1:enable
uint8_t RX_ACK_EN: 1; //0:disable 1:enable
uint8_t RX_TIMER_EN: 1; //0:disable 1:enable
uint8_t RX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
uint8_t CSMA_EN: 1; //0:disable 1:enable
} _BITS;
uint8_t WORK_MODE_CFG2_REG; //CTL_REG_97, 0x61
} WORK_MODE_CFG2_u;
union
{
struct
{
uint8_t SLP_MODE: 4; //14 items for select
uint8_t RX_HOP_SLP_MODE: 3; //7 items for select
uint8_t PKT_DONE_EXIT_EN: 1; //0:keep on current state; 1:depends on RX_EXIT_STATE
} _BITS;
uint8_t WORK_MODE_CFG3_REG; //CTL_REG_98, 0x62
} WORK_MODE_CFG3_u;
union
{
struct
{
uint8_t LFCLK_OUT_EN: 1; //0:disable; 1:enable LFCLK output to GPIO4
uint8_t LFCLK_SEL: 1; //0:LFOSC; 1:LFXO (32768Hz)
uint8_t RESV_1: 1; //
uint8_t SLEEP_TIMER_EN: 1; //0:disable 1:enable
uint8_t TIMER_RAND_MODE: 2; //00:random R, 01:random M, 10:both M&R random, 11:depends on config value
uint8_t RESV_2: 2;
} _BITS;
uint8_t WORK_MODE_CFG4_REG; //CTL_REG_105, 0x69
} WORK_MODE_CFG4_u;
union
{
struct
{
uint8_t CSMA_CCA_WIN_SEL: 2; //00:32symbol, 01:64symbol, 10:128symbol, 11:256symbol
uint8_t CSMA_CCA_INT_SEL: 2; //00:PJD, 01:RSSI, 10:PJD & RSSI, 11:NA
uint8_t CSMA_PERSIST_EN: 1; //0:auto exit when reach max & channel still busy, 1:keep on work until send out
uint8_t CSMA_CCA_MODE: 3; //000:idle, 001:>=1 RSSI, 010:>=1 PJD, 011:>=1 RSSI or PJD,
//100:>=1 SYNC, 101:>=1 SYNC or RSSI, 110:>=1 SYNC or PJD, 111:>=1 SYNC or PJD or RSSI
} _BITS;
uint8_t WORK_MODE_CFG5_REG; //CTL_REG_106, 0x6A
} WORK_MODE_CFG5_u;
union
{
struct
{
uint8_t RESV_5: 5;
uint8_t FREQ_SW_STATE: 1; //0:switch to RFS/TFS, and then to the next channel; 1:switch to RDY, and then to the next channel;
uint8_t RX_HOP_PERSIST: 1; //0:depend on TX/RX_EXIT_STATE, 1:go on next cycle from 0 label
uint8_t FREQ_HOP_MANU_EN: 1; //0:auto hopping mode; 1:hopping by manual
} _BITS;
uint8_t WORK_MODE_CFG6_REG;
} WORK_MODE_CFG6_u; //CTL_REG_22, 0x16
uint8_t FREQ_CHANL_NANU; //CTL_REG_3, 0x03, frequency hopping by manual, set channel number
uint8_t FREQ_DONE_TIMES; //CTL_REG_11, 0x0B, auto frequency hopping times have done
uint8_t FREQ_SPACE; //CTL_REG_12, 0x0C, auto frequency channel interval
uint8_t FREQ_TIMES; //CTL_REG_13, 0x0D, auto frequency hopping set range, 1-64
uint16_t SLEEP_TIMER_M; //CTL_REG_100[7:5]|CLT_REG_99, 11bits, 0x64,0x63
uint8_t SLEEP_TIMER_R; //CTL_REG_100[4:0], 0x64
uint16_t RX_TIMER_T1_M; //CTL_REG_102[7:5]|CLT_REG_101, 11bits, 0x66, 0x65
uint8_t RX_TIMER_T1_R; //CTL_REG_102[4:0], 0x66
uint16_t RX_TIMER_T2_M; //CTL_REG_104[7:5]|CLT_REG_103, 11bits, 0x68, 0x67
uint8_t RX_TIMER_T2_R; //CTL_REG_104[4:0], 0x68
uint16_t RX_TIMER_CSMA_M; //CTL_REG_108[7:5]|CLT_REG_107, 11bits, 0x6C,0x6B
uint8_t RX_TIMER_CSMA_R; //CTL_REG_108[4:0], 0x6C
uint8_t TX_DC_TIMES; //CTL_REG_110, 0x6E, tx duty cycle, set maximum times
uint8_t TX_DC_DONE_TIMES; //CTL_REG_112, 0x70, tx duty cycle, times have done
uint8_t TX_RS_TIMES; //CTL_REG_113, 0x71, tx ack mode, set maximum times
uint8_t TX_RS_DONE_TIMES; //CLT_REG_114, 0x72, tx ack mode, times have done
uint8_t CSMA_TIMES; //CTL_REG_115, 0x73, csma, set maximum times
uint8_t CSMA_DONE_TIMES; //CTL_REG_116, 0x74, csma, times have done
uint16_t SLEEP_TIMER_CSMA_M; //CTL_REG_119[7:5]|CTL_REG_118, 11bits
uint8_t SLEEP_TIMER_CSMA_R; //CTL_REG_119, 0x77[4:0]
} WORK_MODE_CFG;
//## RSSI config (in page1)
typedef struct
{
union
{
struct
{
uint8_t COLL_DET_EN: 1; //0: disable, 1: enable collision detect;
uint8_t RESV_1: 1;
uint8_t RSSI_UPDATE_SEL: 2; //0:always update, 1:when PREAM_OK, 2:when SYNC_OK, 3:when PKT_DONE
uint8_t COLL_STEP_SEL: 2; //0:6dB, 1:10dB, 2:16dB 3:20dB
uint8_t RESV_2: 2;
} _BITS;
uint8_t RSSI_CFG_REG; //RX_RSSI_REG_00, 0x62, page1
} FRAME_CFG1_u;
uint8_t RSSI_ABS_TH; //RX_RSSI_REG_01, 0x63, page1
} RSSI_CFG;
//## Antenna config (in page0 & page1)
typedef struct
{
union
{
struct
{
uint8_t ANT_SELECT: 1; //0: antenna1, 1: antenna2, for antenna diversity manual mode
uint8_t ANT_DIV_MANU: 1; //0: auto antenna diversity, 1: manual antenna diversity
uint8_t RESV_6: 6;
} _BITS;
uint8_t ANT_CFG1_REG; // CTL_REG_02, 0x02, page0
} ANT_CFG1_u;
union
{
struct
{
uint8_t ANT_INSTR: 1; //0: antenna1 was used, 1: antenna2 was used, for indicate which antenna was used in antenna diversity auto mode
uint8_t RESV_7: 6;
} _BITS;
uint8_t ANT_CFG2_REG; // CTL_REG_14, 0x0E, page0
} ANT_CFG2_u;
union
{
struct
{
uint8_t ANT_DIV_EN: 1; //0: disable, 1: enable antenna diversity
uint8_t ANT_SW_DIS: 1; //0: enable, 1: disable antenna diversity switch
uint8_t ANT_WAIT_PMB: 2; //0: RX_PREAM_SIZE x1.5, 1: RX_PREAM_SIZE x2, 2: RX_PREAM_SIZE x2.5, 3: RX_PREAM_SIZE x3
uint8_t RESV_4: 4;
} _BITS;
uint8_t RX_ANTD_REG; //RX_ANTD_REG_00, 0x67, page1
} ANT_CFG3_u;
} ANT_DIV_CFG;
//## CDR Tracing (in page1)
typedef struct
{
union
{
struct
{
uint8_t CDR_MODE: 2; //0:tracing, 1:counting, 2:manchester, 3:no_cdr
uint8_t CDR_RANGE_SEL: 2; //0:+/-6.3%, 1:+/-9.4%, 2:+/-12.5%, 3:+/-15.6%
uint8_t CDR_AVG_SEL: 3; //0:48/64, 1:32/64 2:24/64 3:16/64, 4:11/64 5:8/64 6:6/64 7:4/64
uint8_t CDR_DET_SEL: 1; //0:mode0, 1:mode1(recommand)
} _BITS;
uint8_t CDR_CFG0_REG; //RX_CDR_REG_00, 0x44, page1
} CDR_CFG0_u;
union
{
struct
{
uint8_t RESV_3: 3; //CDR_BR_TH<18:16>
uint8_t CDR_3RD_EN: 1; //0:disable, 1:enable
uint8_t CDR_4TH_EN: 1; //0:disable, 1:enable
uint8_t RESV_3_2: 3; //0:mode0, 1:mode1(recommend)
} _BITS;
uint8_t CDR_CFG1_REG; //RX_CDR_REG_00, 0x44, page1
} CDR_CFG1_u;
uint32_t CDR_BR_TH; //RX_CDR_REG_03<18:16> & RX_CDR_REG_02<15:8> & RX_CDR_REG_01<7:0>, page1(0x47,0x45,0x46)
} CDR_TRACING_CFG;
enum CDR_MODE
{
CDR_SEL_TRACING = 0,
CDR_SEL_COUNTING = 1,
CDR_SEL_MANCHESTER = 2,
CDR_SEL_RAW = 3,
};
typedef struct
{
INT_SRC_CFG int_src_en;
INT_SRC_FLG int_src_flag;
INT_SRC_CLR int_src_clear;
FIFO_STATUS_FLG fifo_status_flag;
PREAMBLE_CFG preamble_cfg;
SYNC_CFG sync_cfg;
ADDR_CFG addr_cfg;
CRC_CFG crc_cfg;
CODING_FORMAT_CFG coding_format_cfg;
FRAME_CFG frame_cfg;
WI_SUN_CFG wi_sun_cfg;
WORK_MODE_CFG word_mode_cfg;
RSSI_CFG rssi_cfg;
ANT_DIV_CFG antenna_cfg;
CDR_TRACING_CFG cdr_tracing_cfg;
} CMT2310A_CFG;
#endif
//******************************************************************************
//* EOF (not truncated)
//******************************************************************************

578
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h.orig Executable file
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@ -0,0 +1,578 @@
/*
* THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND
* (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
* CONSEQUENTLY, CMOSTEK SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* Copyright (C) CMOSTEK SZ.
*/
/*!
* @file CMT2310A_def.h
* @brief CMT2310A transceiver RF chip driver
*
* @version 1.0
* @date Dec 7 2021
* @author CMOSTEK R&D
*/
#ifndef __CMT2310A_DEF_H
#define __CMT2310A_DEF_H
//Exit State
#define EXIT_TO_SLEEP 1
#define EXIT_TO_READY 2
#define EXIT_TO_TFS 3
#define EXIT_TO_TX 4
#define EXIT_TO_RFS 5
#define EXIT_TO_RX 6
//Prefxi select
#define TX_PREFIX_SEL_0 0
#define TX_PREFIX_SEL_1 1
#define TX_PREFIX_SEL_PREAMBLE 2
//## interrupt source config
typedef union
{
struct
{
uint8_t PKT_DONE_EN: 1; //pkt_done_en //bit0
uint8_t CRC_PASS_EN: 1; //crc_pass_en //bit1
uint8_t ADDR_PASS_EN: 1; //node_address_pass_en //bit2
uint8_t SYNC_PASS_EN: 1; //sync_pass_en //bit3
uint8_t PREAM_PASS_EN: 1; //preamble_pass_en //bit4
uint8_t TX_DONE_EN: 1; //tx_done_en //bit5
uint8_t RX_TOUT_EN: 1; //rx_timeout_en //bit6
uint8_t SLP_TOUT_EN: 1; //sleep_timeout_en //bit7
uint8_t LD_STOP_EN: 1; //ld_stop_en(PLL lock detect)//bit0
uint8_t LBD_STOP_EN: 1; //lbd_stop_en //bit1
uint8_t LBD_STAT_EN: 1; //lbd_status_en //bit2
uint8_t PKT_ERR_EN: 1; //pkt_err_en //bit3
uint8_t RSSI_COLL_EN: 1; //rssi_collision_en //bit4
uint8_t OP_CMD_FAILED_EN: 1; //op_cmd_failed_en //bit5
uint8_t RSSI_PJD_EN: 1; //rssi_pjd_valid_en //bit6
uint8_t RESV_2_1: 1; //reserve, don't used //bit7
uint8_t SEQ_MATCH_EN: 1; //seq_match_en //bit0
uint8_t NACK_RECV_EN: 1; //nack_recv_en //bit1
uint8_t TX_RESEND_DONE_EN: 1; //tx_resend_done_en //bit2
uint8_t ACK_RECV_FAILED_EN: 1; //ack_recv_failed_en //bit3
uint8_t TX_DC_DONE_EN: 1; //tx_dc_done_en //bit4
uint8_t CSMA_DONE_EN: 1; //csma_max_en //bit5
uint8_t CCA_STAT_EN: 1; //cca_status_en //bit6
uint8_t API_DONE_EN: 1; //api_done_en //bit7
uint8_t TX_FIFO_TH_EN: 1; //tx_fifo_threshold_en //bit0
uint8_t TX_FIFO_NMTY_EN: 1; //tx_fifo_non_empty_en //bit1
uint8_t TX_FIFO_FULL_EN: 1; //tx_fifo_full_en //bit2
uint8_t RX_FIFO_OVF_EN: 1; //rx_fifo_overflow_en //bit3
uint8_t RESV_4_1: 1; //reserve, don't used //bit4
uint8_t RX_FIFO_TH_EN: 1; //rx_fifo_threshold_en //bit5
uint8_t RX_FIFO_NMTY_EN: 1; //rx_fifo_non_empty_en //bit6
uint8_t RX_FIFO_FULL_EN: 1; //rx_fifo_full_en //bit7
}_BITS;
struct
{
uint8_t INT_CTL1_REG; //CTL_REG_18, 0x12
uint8_t INT_CTL2_REG; //CTL_REG_21, 0x15
uint8_t INT_CTL3_REG; //CTL_REG_23, 0x17
uint8_t INT_CTL4_REG; //CTL_REG_14, 0x0E
}_BYTE;
}INT_SRC_CFG;
//## interrupt flag
typedef union
{
struct
{
uint8_t RESV_3: 3; //reserve, don't used //bit0/1/2
uint8_t TX_DONE_FLG: 1; //tx_done_flag //bit3
uint8_t RX_TMO_FLG: 1; //rx_timer_timeout_flag //bit4
uint8_t SLEEP_TMO_FLG: 1; //sleep_timer_timeout_flag //bit5
uint8_t RESV_2: 2; //reserve, don't used //bit6/7
uint8_t PKT_DONE_FLG: 1; //pkt_done_flag //bit0
uint8_t CRC_PASS_FLG: 1; //crc_pass_flag //bit1
uint8_t ADDR_PASS_FLG: 1; //addr_pass_flag //bit2
uint8_t SYNC_PASS_FLG: 1; //sync_pass_flag //bit3
uint8_t PREAM_PASS_FLG: 1; //preamble_pass_flag //bit4
uint8_t SYNC1_PASS_FLG: 1; //sync1_pass_flag //bit5
uint8_t RESV_2_2: 2; //reserve, don't used //bit6/7
uint8_t LBD_STATUS_FLG: 1; //lbd_status_flag //bit0
uint8_t PKT_ERR_FLG: 1; //pkt_err_flag //bit1
uint8_t RSSI_COLL_FLG: 1; //rssi_collision_flag //bit2
uint8_t OP_CMD_FAILED_FLG: 1; //op_cmd_failed_flag //bit3
uint8_t ANT_LOCK_FLG: 1; //ant_lock_flag //bit4
uint8_t RESV_3_3: 3; //reserve, don't used //bit5/6/7
uint8_t SEQ_MATCH_FLG: 1; //seq_match_flag //bit0
uint8_t NACK_RECV_FLG: 1; //nack_recv_flag //bit1
uint8_t TX_RESEND_DONE_FLG: 1; //tx_resend_max_flag //bit2
uint8_t ACK_RECV_FAILED_FLG: 1; //ack_recv_failed_flag //bit3
uint8_t TX_DC_DONE_FLG: 1; //tx_dc_done_flag //bit4
uint8_t CSMA_DONE_FLG: 1; //csma_done_flag //bit5
uint8_t CCA_STATUS_FLG: 1; //cca_status_flag //bit6
uint8_t API_DONE_FLG: 1; //api_done_flag //bit7
}_BITS;
struct
{
uint8_t INT_FLAG1_REG; //CTL_REG_24, 0x18
uint8_t INT_FLAG2_REG; //CTL_REG_26, 0x1A
uint8_t INT_FLAG3_REG; //CTL_REG_30, 0x1E
uint8_t INT_FLAG4_REG; //CTL_REG_32, 0x20
}_BYTE;
}INT_SRC_FLG;
//## interrupt clear
typedef union
{
struct
{
uint8_t TX_DONE_CLR: 1; //tx_done_clr //bit0
uint8_t RX_TMO_CLR: 1; //rx_timer_timeout_clr //bit1
uint8_t SLEEP_TMO_CLR: 1; //sleep_timer_timeout_clr //bit2
uint8_t RESV_5: 5; //reserve, don't used //bit3-7
uint8_t PKT_DONE_CLR: 1; //pkt_done_clr //bit0
uint8_t CRC_PASS_CLR: 1; //crc_pass_clr //bit1
uint8_t ADDR_PASS_CLR: 1; //addr_pass_clr //bit2
uint8_t SYNC_PASS_CLR: 1; //sync_pass_clr //bit3
uint8_t PREAM_PASS_CLR: 1; //preamble_pass_clr //bit4
uint8_t RESV_3: 3; //reserve, don't used //bit5/6/7
uint8_t LBD_STAT_CLR: 1; //lbd_status_clr //bit0
uint8_t PKT_ERR_CLR: 1; //packet_err_clr //bit1
uint8_t RSSI_COLL_CLR: 1; //rssi_collision_clr //bit2
uint8_t OP_CMD_FAILED_CLR: 1; //op_cmd_failed_clr //bit3
uint8_t ANT_LOCK_CLR: 1; //antenna_lock_clr //bit4
uint8_t RESV_2_3: 3; //reserve, don't used //bit5/6/7
uint8_t SEQ_MATCH_CLR: 1; //seq_match_clr //bit0
uint8_t NACK_RECV_CLR: 1; //nack_recv_clr //bit1
uint8_t TX_RESEND_DONE_CLR: 1; //tx_resend_done_clr //bit2
uint8_t ACK_RECV_FAILED_CLR: 1; //ack_recv_failed_clr //bit3
uint8_t TX_DC_DONE_CLR: 1; //tx_dc_done_clr //bit4
uint8_t CSMA_DONE_CLR: 1; //csma_done_clr //bit5
uint8_t CCA_STATUS_CLR: 1; //cca_status_clr //bit6
uint8_t API_DONE_CLR: 1; //api_done_clr //bit7
}_BITS;
struct
{
uint8_t INT_CLR1_REG; //CTL_REG_24, 0x18
uint8_t INT_CLR2_REG; //CTL_REG_25, 0x19
uint8_t INT_CLR3_REG; //CTL_REG_29, 0x1D
uint8_t INT_CLR4_REG; //CTL_REG_31, 0x1F
}_BYTE;
}INT_SRC_CLR;
//## fifo status flag
typedef union
{
struct
{
uint8_t TX_FIFO_TH_FLG: 1; //tx_fifo_threshold_flag //bit0
uint8_t TX_FIFO_NMTY_FLG: 1; //tx_fifo_non_empty_flag //bit1
uint8_t TX_FIFO_FULL_FLG: 1; //tx_fifo_full_flag //bit2
uint8_t RX_FIFO_OVF_FLG: 1; //rx_fifo_overflow_flag //bit3
uint8_t RESV_1: 1; //reserve, don't used //bit4
uint8_t RX_FIFO_TH_FLG: 1; //rx_fifo_threshold_flag //bit5
uint8_t RX_FIFO_NMTY_FLG: 1; //rx_fifo_non_empty_flag //bit6
uint8_t RX_FIFO_FULL_FLG: 1; //rx_fifo_full_flag //bit7
}_BITS;
uint8_t FIFO_FLG_REG; //CTL_REG_28, 0x1c
}FIFO_STATUS_FLG;
//## packet preamble config
typedef struct //Packet Preamble
{
uint8_t PREAM_LENG_UNIT; //0=preamble unit as 8bits, !0=preamble unit as 4bits (nibble mode)
uint8_t PREAM_VALUE; //preamble value
uint8_t RX_PREAM_SIZE; //rx preamble length, range: 0-31, 0==disable rx preamble detect
uint16_t TX_PREAM_SIZE; //tx preamble length //## note: for arm mcu uint16_t is 16bits
}PREAMBLE_CFG;
//## packet syncword config
typedef struct
{
union
{
struct
{
uint8_t SYNC_MAN_EN: 1; //sync word manchester coding enable
uint8_t SYNC_SIZE: 3; // n+1 bytes
uint8_t SYNC_TOL: 3; // n bits tolerence error
uint8_t SYNC_MODE_SEL: 1; // 0: compatible S2LP; 1: compatible 802.15.4
}_BITS;
uint8_t SYNC_CFG_REG; //CTL_REG_44, 0x2c
}SYN_CFG_u;
uint8_t SYNC_VALUE[8]; //CTL_REG_45-CTL_REG_53, 0x2D-0x34
uint8_t SYNC_FEC_VALUE[8]; //CTL_REG_53-CTL_REG_60, 0x35-0x3C
uint8_t SYNC_VALUE_SEL; // 0: select SYN_VAL; !0: select SYN_FEC_VAL
}SYNC_CFG;
//## packet node address config
typedef struct
{
union
{
struct
{
uint8_t ADDR_DET_MODE: 2; //node address mode: 0,disable; 1,only match; 2,add all 0; 3,add all 1 & 0
uint8_t ADDR_SIZE: 2; // n+1 bytes
uint8_t ADDR_ERR_MASK: 1; // 0: trigger PKT_ERR flag, when node address not match, and reset decode; 1: non-reset decode, when node address not match
uint8_t ADDR_FREE_EN: 1; // 0: disable; 1: enable node address match as stand-alone working
uint8_t ADDR_SPLIT_MODE: 1; // 0: disable, dest_addr==node_addr; 1: enable, node_addr==src_addr+des_addr
uint8_t RESV_1: 1;
}_BITS;
uint8_t ADDR_CFG_REG; //CTL_REG_64, 0x40
}ADDR_CFG_u;
uint8_t SRC_ADDR[2]; //CTL_REG_65, CTL_REG_66
uint8_t DEST_ADDR[2]; //CTL_REG_67, CTL_REG_68
uint8_t SRC_BITMASK[2]; //CTL_REG_69, CTL_REG_70
uint8_t DEST_BITMASK[2]; //CTL_REG_71, CTL_REG_72
}ADDR_CFG;
//## packet crc config
typedef struct
{
union
{
struct
{
uint8_t CRC_EN: 1; // 0:disable CRC; 1:enable CRC
uint8_t CRC_BIT_ORDER: 1; // 0:crc result MSB output first; 1:crc result LSB output first; active unit is byte
uint8_t CRC_REFIN: 1; // 0:normal input; 1:inverse input;
uint8_t CRC_RANGE: 1; // 0:whole payload; 1:only data
uint8_t CRC_BIT_INV: 1; // 0:crc result non-invert; 1:crc result all bits invert
uint8_t CRC_BYTE_SWAP: 1; // 0:crc result HighByte output first; 1:crc result LowByte output first
uint8_t CRC_SIZE: 2; // 0:crc8; 1:crc16; 2:crc24; 3:crc32
uint8_t CRC_REFOUT: 1; // 0:result whole bit MSB->LSB 1:result whole bit LSB->MSB
uint8_t CRCERR_CLR_FIFO_EN: 1; // 0:disable 1:enable when crc error, clear fifo function
uint8_t RESV_6: 6;
}_BITS;
uint16_t CRC_CFG_REG; //CTL_REG_73, 0x49 & CTL_REG_82[7] & CTL_REG_84[7]
}CRC_CFG_u;
union //CTL_REG_74-CTL_REG_77, 0x4A-0x4D //## note: for arm mcu uint32_t is 32bits
{
uint8_t u8_SEED[4];
uint32_t u32_SEED;
}CRC_SEED_u;
union //CTL_REG_78-CTL_REG_81, 0x4E-0x51 //## note: for arm mcu uint32_t is 32bits
{
uint8_t u8_POLY[4];
uint32_t u32_POLY;
}CRC_POLY_u;
}CRC_CFG;
//## packet encode/decode format config
typedef struct
{
union
{
struct
{
uint8_t MANCH_EN: 1; // 0:disable manchester coding; 1:enable manchester coding
uint8_t MANCH_TYPE: 1; // 0: 2'b01=1, 2'b10=0; 1: 2'b01=0, 2'b10=1
uint8_t WHITEN_EN: 1; // 0:disable whiten coding; 1:enable whiten coding
uint8_t WHITEN_TYPE: 2; // 0:PN9-CCITT, 1:PN9-IBM, 2:PN7, 3:NA
uint8_t WHITEN_SEED_TYP: 1; // 0:compatible A7139; 1:customer seed; note: when select PN7 active
uint8_t RESV_2: 2;
uint8_t FEC_EN: 1; // 0:disable FEC Coding; 1:enable FEC Coding
uint8_t FEC_RSC_NRNSC_SEL: 1; // 0:RSC Mode; 1:NRNSC Mode
uint8_t RESV_5: 5;
uint8_t FEC_TICC: 1; // 0:ui invert ouput in FEC calucate; 1:ui non-invert ouput in FEC calucate
}_BITS;
uint16_t CODING_CFG_REG; // CTL_REG_82, 0x52 & CTL_REG_93, 0x5D
}CODING_FORMAT_CFG_u;
uint16_t WHITEN_SEED; // CTL_REG_83, 0x53 & CTL_REG_82[6]
uint16_t FEC_PAD_CODE; // CTL_REG_94, 0x5E & CTL_REG_93[6:2], 0x5D
}CODING_FORMAT_CFG;
//## frame struct config
typedef struct
{
uint8_t DATA_MODE; //0: direct mode; 2: packet mode; 1&3: na
union
{
struct
{
uint8_t PKT_TYPE: 1; //0: fixed length; 1: variable length
uint8_t PAYLOAD_BIT_ORDER: 1; //0: MSB output first; 1: LSB output first
uint8_t ADDR_LEN_CONF: 1; //0: node_addr+length; 1: length+node_addr
uint8_t ADDR_FIELD_EN: 1; //0: disable; 1: enable address field
uint8_t PAGGYBACKING_EN: 1; //0: disable 1: enable
uint8_t LENGTH_SIZE: 1; //0: length range 1 byte; 1: length range 2 bytes
uint8_t RESV_1_2: 1;
uint8_t INTERLEAVE_EN: 1; //0: disable interleave 1: enable interleave
}_BITS;
uint8_t FRAME_CFG1_REG; //CTL_REG_63, 0x3F
}FRAME_CFG1_u;
union
{
struct
{
uint8_t TX_PREFIX_TYPE: 2; //0:transmit_0; 1:transmit_1; 2:transmit_preamble 3:NA
uint8_t SEQNUM_EN: 1; //0:disable; 1:enable; note: SEQ_NUM is the same with FCS1
uint8_t SEQNUM_AUTO_INC: 1; //0:disable SEQNUM increase; 1:enable
uint8_t SEQNUM_SIZE: 1; //0:1byte for SEQNUM; 1:2bytes for SEQNUM
uint8_t SEQNUM_MACH_EN: 1; //0:disable; 1:enable compare with local SEQNUM, when TX_ACK enable
uint8_t FCS2_EN: 1; //0:not include FCS2 filed; 1:include FCS2 filed
uint8_t RESV_1: 1;
}_BITS;
uint8_t FRAME_CFG2_REG; //CTL_REG_84, 0x54
}FRAME_CFG2_u;
uint16_t TX_PKT_NUM; //CTL_REG_85, 0x55[7:0] & CTL_REG_86, 0x56[15:8]
uint16_t SEQNUM_TX_IN; //CTL_REG_88/87, 0x58[15:8], 0x57[7:0]
uint16_t SEQNUM_TX_CURRENT_OUT; //CTL_REG_39/38, 0x27[15:8]/0x26[7:0]
uint8_t TX_PKT_GAP; //CTL_REG_89, 0x59
uint8_t FCS2_TX_IN; //CTL_REG_91, 0x5B
uint8_t FCS2_RX_OUT; //CTL_REG_92, 0x5C
uint16_t PAYLOAD_LENGTH; //CTL_REG_62/61, 0x3E[15:8], 0x3D[7:0]
}FRAME_CFG;
//## Wi-SUN V1.0 packet format compatible
typedef union
{
struct
{
uint8_t WISUN_DW: 1; // 0:not whiten, 1: whiten
uint8_t WISUN_FCS: 1; // 0:CRC-32 for PSDU, 1: CRC-16 for PSDU
uint8_t RESV_2: 2; //
uint8_t WISUN_MS: 1; // default for 0
uint8_t WHITEN_WISUN: 1; // 0: for normal used, 1: for Wi-SUN whitenning
uint8_t WISUN_ALLIN: 1; // 0: WISUN_FCS & WISUN_DW not active, 1: FCS & DW depend on WISUN_FCS & WISUN_DW,
uint8_t LENGTH_MODE: 1; // 0: for normal used, 1: for Wi-SUN used, PSDU length filed is 11bits
}_BITS;
uint8_t WI_SUN_REG; //CTL_REG_111, 0x6F
}WI_SUN_CFG;
//## working mode
typedef struct
{
union
{
struct
{
uint8_t TX_DC_EN: 1; //0:disable TxDutyCycle; 1:enable
uint8_t TX_DC_PERSIST_EN: 1; //0:run TX_DC_TIMES; 1:always run until this bit set 0
uint8_t TX_ACK_EN: 1; //0:disable 1:enable
uint8_t TX_AUTO_HOP_EN: 1; //0:disable 1:enable tx frequency auto hopping
uint8_t TX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
uint8_t RESV: 1;
}_BITS;
uint8_t WORK_MODE_CFG1_REG; //CTL_REG_96, 0x60
}WORK_MODE_CFG1_u;
union
{
struct
{
uint8_t RX_DC_EN: 1; //0:disable RxDutyCycle; 1:enable
uint8_t RX_AUTO_HOP_EN: 1; //0:disable RxAutoHop; 1:enable
uint8_t RX_ACK_EN: 1; //0:disable 1:enable
uint8_t RX_TIMER_EN: 1; //0:disable 1:enable
uint8_t RX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
uint8_t CSMA_EN: 1; //0:disable 1:enable
}_BITS;
uint8_t WORK_MODE_CFG2_REG; //CTL_REG_97, 0x61
}WORK_MODE_CFG2_u;
union
{
struct
{
uint8_t SLP_MODE: 4; //14 items for select
uint8_t RX_HOP_SLP_MODE: 3; //7 items for select
uint8_t PKT_DONE_EXIT_EN: 1; //0:keep on current state; 1:depends on RX_EXIT_STATE
}_BITS;
uint8_t WORK_MODE_CFG3_REG; //CTL_REG_98, 0x62
}WORK_MODE_CFG3_u;
union
{
struct
{
uint8_t LFCLK_OUT_EN: 1; //0:disable; 1:enable LFCLK output to GPIO4
uint8_t LFCLK_SEL: 1; //0:LFOSC; 1:LFXO (32768Hz)
uint8_t RESV_1: 1; //
uint8_t SLEEP_TIMER_EN: 1; //0:disable 1:enable
uint8_t TIMER_RAND_MODE: 2; //00:random R, 01:random M, 10:both M&R random, 11:depends on config value
uint8_t RESV_2: 2;
}_BITS;
uint8_t WORK_MODE_CFG4_REG; //CTL_REG_105, 0x69
}WORK_MODE_CFG4_u;
union
{
struct
{
uint8_t CSMA_CCA_WIN_SEL: 2; //00:32symbol, 01:64symbol, 10:128symbol, 11:256symbol
uint8_t CSMA_CCA_INT_SEL: 2; //00:PJD, 01:RSSI, 10:PJD & RSSI, 11:NA
uint8_t CSMA_PERSIST_EN: 1; //0:auto exit when reach max & channel still busy, 1:keep on work until send out
uint8_t CSMA_CCA_MODE: 3; //000:idle, 001:>=1 RSSI, 010:>=1 PJD, 011:>=1 RSSI or PJD,
//100:>=1 SYNC, 101:>=1 SYNC or RSSI, 110:>=1 SYNC or PJD, 111:>=1 SYNC or PJD or RSSI
}_BITS;
uint8_t WORK_MODE_CFG5_REG; //CTL_REG_106, 0x6A
}WORK_MODE_CFG5_u;
union
{
struct
{
uint8_t RESV_5: 5;
uint8_t FREQ_SW_STATE: 1; //0:switch to RFS/TFS, and then to the next channel; 1:switch to RDY, and then to the next channel;
uint8_t RX_HOP_PERSIST: 1; //0:depend on TX/RX_EXIT_STATE, 1:go on next cycle from 0 label
uint8_t FREQ_HOP_MANU_EN: 1; //0:auto hopping mode; 1:hopping by manual
}_BITS;
uint8_t WORK_MODE_CFG6_REG;
}WORK_MODE_CFG6_u; //CTL_REG_22, 0x16
uint8_t FREQ_CHANL_NANU; //CTL_REG_3, 0x03, frequency hopping by manual, set channel number
uint8_t FREQ_DONE_TIMES; //CTL_REG_11, 0x0B, auto frequency hopping times have done
uint8_t FREQ_SPACE; //CTL_REG_12, 0x0C, auto frequency channel interval
uint8_t FREQ_TIMES; //CTL_REG_13, 0x0D, auto frequency hopping set range, 1-64
uint16_t SLEEP_TIMER_M; //CTL_REG_100[7:5]|CLT_REG_99, 11bits, 0x64,0x63
uint8_t SLEEP_TIMER_R; //CTL_REG_100[4:0], 0x64
uint16_t RX_TIMER_T1_M; //CTL_REG_102[7:5]|CLT_REG_101, 11bits, 0x66, 0x65
uint8_t RX_TIMER_T1_R; //CTL_REG_102[4:0], 0x66
uint16_t RX_TIMER_T2_M; //CTL_REG_104[7:5]|CLT_REG_103, 11bits, 0x68, 0x67
uint8_t RX_TIMER_T2_R; //CTL_REG_104[4:0], 0x68
uint16_t RX_TIMER_CSMA_M; //CTL_REG_108[7:5]|CLT_REG_107, 11bits, 0x6C,0x6B
uint8_t RX_TIMER_CSMA_R; //CTL_REG_108[4:0], 0x6C
uint8_t TX_DC_TIMES; //CTL_REG_110, 0x6E, tx duty cycle, set maximum times
uint8_t TX_DC_DONE_TIMES; //CTL_REG_112, 0x70, tx duty cycle, times have done
uint8_t TX_RS_TIMES; //CTL_REG_113, 0x71, tx ack mode, set maximum times
uint8_t TX_RS_DONE_TIMES; //CLT_REG_114, 0x72, tx ack mode, times have done
uint8_t CSMA_TIMES; //CTL_REG_115, 0x73, csma, set maximum times
uint8_t CSMA_DONE_TIMES; //CTL_REG_116, 0x74, csma, times have done
uint16_t SLEEP_TIMER_CSMA_M; //CTL_REG_119[7:5]|CTL_REG_118, 11bits
uint8_t SLEEP_TIMER_CSMA_R; //CTL_REG_119, 0x77[4:0]
}WORK_MODE_CFG;
//## RSSI config (in page1)
typedef struct
{
union
{
struct
{
uint8_t COLL_DET_EN: 1; //0: disable, 1: enable collision detect;
uint8_t RESV_1: 1;
uint8_t RSSI_UPDATE_SEL: 2; //0:always update, 1:when PREAM_OK, 2:when SYNC_OK, 3:when PKT_DONE
uint8_t COLL_STEP_SEL: 2; //0:6dB, 1:10dB, 2:16dB 3:20dB
uint8_t RESV_2: 2;
}_BITS;
uint8_t RSSI_CFG_REG; //RX_RSSI_REG_00, 0x62, page1
}FRAME_CFG1_u;
uint8_t RSSI_ABS_TH; //RX_RSSI_REG_01, 0x63, page1
}RSSI_CFG;
//## Antenna config (in page0 & page1)
typedef struct
{
union
{
struct
{
uint8_t ANT_SELECT: 1; //0: antenna1, 1: antenna2, for antenna diversity manual mode
uint8_t ANT_DIV_MANU: 1; //0: auto antenna diversity, 1: manual antenna diversity
uint8_t RESV_6: 6;
}_BITS;
uint8_t ANT_CFG1_REG; // CTL_REG_02, 0x02, page0
}ANT_CFG1_u;
union
{
struct
{
uint8_t ANT_INSTR: 1; //0: antenna1 was used, 1: antenna2 was used, for indicate which antenna was used in antenna diversity auto mode
uint8_t RESV_7: 6;
}_BITS;
uint8_t ANT_CFG2_REG; // CTL_REG_14, 0x0E, page0
}ANT_CFG2_u;
union
{
struct
{
uint8_t ANT_DIV_EN: 1; //0: disable, 1: enable antenna diversity
uint8_t ANT_SW_DIS: 1; //0: enable, 1: disable antenna diversity switch
uint8_t ANT_WAIT_PMB: 2; //0: RX_PREAM_SIZE x1.5, 1: RX_PREAM_SIZE x2, 2: RX_PREAM_SIZE x2.5, 3: RX_PREAM_SIZE x3
uint8_t RESV_4: 4;
}_BITS;
uint8_t RX_ANTD_REG; //RX_ANTD_REG_00, 0x67, page1
}ANT_CFG3_u;
}ANT_DIV_CFG;
//## CDR Tracing (in page1)
typedef struct
{
union
{
struct
{
uint8_t CDR_MODE: 2; //0:tracing, 1:counting, 2:manchester, 3:no_cdr
uint8_t CDR_RANGE_SEL: 2; //0:+/-6.3%, 1:+/-9.4%, 2:+/-12.5%, 3:+/-15.6%
uint8_t CDR_AVG_SEL: 3; //0:48/64, 1:32/64 2:24/64 3:16/64, 4:11/64 5:8/64 6:6/64 7:4/64
uint8_t CDR_DET_SEL: 1; //0:mode0, 1:mode1(recommand)
}_BITS;
uint8_t CDR_CFG0_REG; //RX_CDR_REG_00, 0x44, page1
}CDR_CFG0_u;
union
{
struct
{
uint8_t RESV_3: 3; //CDR_BR_TH<18:16>
uint8_t CDR_3RD_EN: 1; //0:disable, 1:enable
uint8_t CDR_4TH_EN: 1; //0:disable, 1:enable
uint8_t RESV_3_2: 3; //0:mode0, 1:mode1(recommend)
}_BITS;
uint8_t CDR_CFG1_REG; //RX_CDR_REG_00, 0x44, page1
}CDR_CFG1_u;
uint32_t CDR_BR_TH; //RX_CDR_REG_03<18:16> & RX_CDR_REG_02<15:8> & RX_CDR_REG_01<7:0>, page1(0x47,0x45,0x46)
}CDR_TRACING_CFG;
enum CDR_MODE
{
CDR_SEL_TRACING = 0,
CDR_SEL_COUNTING = 1,
CDR_SEL_MANCHESTER = 2,
CDR_SEL_RAW = 3,
};
typedef struct
{
INT_SRC_CFG int_src_en;
INT_SRC_FLG int_src_flag;
INT_SRC_CLR int_src_clear;
FIFO_STATUS_FLG fifo_status_flag;
PREAMBLE_CFG preamble_cfg;
SYNC_CFG sync_cfg;
ADDR_CFG addr_cfg;
CRC_CFG crc_cfg;
CODING_FORMAT_CFG coding_format_cfg;
FRAME_CFG frame_cfg;
WI_SUN_CFG wi_sun_cfg;
WORK_MODE_CFG word_mode_cfg;
RSSI_CFG rssi_cfg;
ANT_DIV_CFG antenna_cfg;
CDR_TRACING_CFG cdr_tracing_cfg;
}CMT2310A_CFG;
#endif
//******************************************************************************
//* EOF (not truncated)
//******************************************************************************

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MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h Executable file
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MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_410mhz.c Executable file
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#include "radio_hal.h"
#include "CMT2310A_reg.h"
#include "CMT2310A_def.h"
/****************************************************************************
;---------------------------------------
; CMT2310A Configuration File
; Generated by CMOSTEK RFPDK 1.54
; 2023.12.07 13:35
;---------------------------------------
; Mode = Advanced
; Part Number = CMT2310A
; Frequency = 410.000 MHz
; DC-DC = Off
; Demodulation = GFSK
; Xtal Cap Load = 2
; Data Rate = 2.400 kbps
; Deviation = 4.800 kHz
; Tx Xtal Tol. = 10 ppm
; Rx Xtal Tol. = 10 ppm
; TRx Matching Network Type = 20 dBm
; Tx Power = +20 dBm
; Gaussian BT = 0.5
; PA Ramp = On-Autosel Rampstep
; PA Ramp Step = NA
; RF Performance = NA
; Output Drive Capability = 0.5mA
; Rx Duty-Cycle = Off
; Tx Duty-Cycle = Off
; Sleep Timer = Off
; Sleep Time = NA
; Rx Timer = Off
; Rx Time T1 = NA
; Rx Time T2 = NA
; Rx Exit State = STBY
; Tx Exit State = STBY
; TX Duty Cycle Persist = Off
; Packet Done Exit = Off
; TX Duty-Cycle Times = 0
; SLP Mode = Mode 0
; RSSI Valid Source = RSSI Compare
; PJD Window = NA
; RSSI Compare TH = -127 dBm
; CDR Type = Counting
; AFC = autosel
; FSK2 Data Map = 0:F-low 1:F-high
; FSK4 Data Map = NA
; FSK4 RX Data Map = NA
; CDR Type = Counting
; CDR Range Sel FSK = NA
; Channel BW = autosel
; Baseband BW FSK = autosel
; Data Mode = Packet
; Packet Mode = Normal
; PiggyBacking = Disable
; Manchester = Disable
; Manchester Type = NA
; Whitening = Disable
; Whiten Type = NA
; Whiten Seed Type = NA
; Whiten Seed = NA
; FEC = Disable
; FEC Type = NA
; FEC Padding Code = NA
; crc err clear fifo = Not Clear
; Tx Packet Gap = 32 symbol(s)
; Tx Packet Number = 1 packet(s)
; Tx Prefix Type = 0
; Packet Type = Fixed Length
; Address-Length Position = NA
; Length Size = 1-byte
; Payload Bit Order = Start from msb
; Address Field = Disable
; Preamble Rx Size = 2
; Preamble Tx Size = 8
; Preamble Value = 170
; Preamble Unit = 8-bit
; Sync Size = 3-byte
; Sync Format = S2LP
; Sync Value = 3003605
; Sync Manchester = Disable
; Sync Value Selection = Sync Value
; Sync FEC Value = 3003605
; Sync Tolerance = None
; Address Detect Mode = None
; Address Split Mode = NA
; Address Size = NA
; Address Err Mask = NA
; Address Free = NA
; Dest Addr Value = NA
; Src Addr Value = NA
; Dest Addr Bit Mask = NA
; Src Addr Bit Mask = NA
; Sequence Num = None
; Sequence Num Match = off
; Sequence Num Mode = NA
; Sequence Num Value = NA
; FCS2 = None
; FCS2 Value = NA
; Payload Length = 32
; CRC Options = None
; CRC Swap = NA
; CRC Seed = NA
; CRC Bit Invert = NA
; CRC Range = NA
; CRC Polynomial = NA
; CRC Bit Order = NA
; CRC Refin = NA
; CRC_Refout = NA
; Frequency Hopping Mode = Mode 2
; Freq Hopping Space = 10 kHz
; Hopping Channels = 10
; CSMA Mode = Disable
; CSMA RSSI Detection = NA
; Hopping Persist = Disable
; Hopping Intermediate State = TRFS
; CSMA Sleep Timer Random = NA
; CSMA Rx Time = NA
; CSMA Sleep Time M = NA
; CSMA Sleep Time R = NA
; CSMA Persist = NA
; CSMA Detect Times = NA
; Tx Auto Hopping = Disable
; Rx Auto Hopping = Disable
; Auto Acknowledge = off
; Auto Resend = off
; Maximum Resend Times = 1
; RSSI Detect Mode = always
; LFOSC LFXO Sel = LFOSC(32kHz)
; LF Clock Out = off
; Dout Mute = disable
; Dout Mute Sel = NA
; dout adjust mode = disable
; Dout Adjust Percentage = NA
; LBD Threshold = 2.4 v
; Antenna Diversity = off
; Antenna Switch Mode = NA
; Collision Detect = off
; Collision Step = NA
; RSSI Offset dB = NA
; RSSI Offset Sel = autosel
; i_fir_bb_bw_for_cal_freq = 1
;---------------------------------------
; The following are the Register contents
;---------------------------------------
*****************************************************************************/
#if (PRODUCT_FREQUENCY == CM2310A_410MHZ)
/* [CMT page0] */
const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = {
0x12,
0x08,
0x00,
0xAA,
0x04,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0x45,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x08,
0x00,
0x00,
0x00,
0x00,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x00,
0xE4,
0x20,
0x20,
0x20,
0x01,
0x00,
0xD0,
0xE0,
0xE2,
0x84,
0x30,
0x04,
0xD0,
0xE0,
0x80,
0x00,
0x41,
0x00,
0x01,
0x00,
0x02,
0x00,
0x00,
0x03,
0x04,
};
/* [CMT page1] */
const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = {
0x10,
0x06,
0x00,
0xFF,
0x00,
0xCD,
0x02,
0x28,
0x50,
0x87,
0x31,
0x5B,
0x08,
0x00,
0xFF,
0x00,
0x66,
0x00,
0x00,
0x08,
0xB4,
0xEA,
0x04,
0xE0,
0x20,
0x08,
0x05,
0x8D,
0x06,
0x00,
0xA0,
0x7F,
0x00,
0x18,
0x00,
0x00,
0x1F,
0xE4,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0xCA,
0x66,
0x00,
0x80,
0xD8,
0x63,
0x00,
0x80,
0x0F,
0x64,
0x06,
0x02,
0xEA,
0x04,
0x00,
0x36,
0x01,
0x20,
0xC8,
0x63,
0xA1,
0x15,
0x34,
0x58,
0x40,
0xD2,
0x74,
0xF0,
0x0F,
0x01,
0x17,
0xE6,
0x54,
0x08,
0x39,
0xE6,
0x27,
0x0C,
0x01,
0xB4,
0x06,
0x0F,
0x00,
0x4C,
0x00,
0x00,
0xF6,
0x00,
0x00,
0x00,
0x10,
0x81,
0x00,
0x00,
0x47,
0x12,
0x25,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
//#define CMT2310A_AUTO_HOP_ENABLE
#ifdef CMT2310A_AUTO_HOP_ENABLE
#define freq_space_val 0x0A
#define freq_times_val 0x0A
#define freq_switch_state_val 0x01
#define freq_hop_persist_val 0x00
/* [CMT page2] */
const uint8_t g_cmt2310a_page2[CMT2310A_PAGE2_SIZE] = {
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
#endif
#endif

351
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_433mhz.c Executable file
View File

@ -0,0 +1,351 @@
#include "radio_hal.h"
#include "CMT2310A_reg.h"
#include "CMT2310A_def.h"
/****************************************************************************
;---------------------------------------
; CMT2310A Configuration File
; Generated by CMOSTEK RFPDK 1.53_Update4
; 2023.01.14 10:34
;---------------------------------------
; Mode = Advanced
; Part Number = CMT2310A
; Frequency = 433.920 MHz
; DC-DC = Off
; Demodulation = GFSK
; Xtal Cap Load = 2
; Data Rate = 2.400 kbps
; Deviation = 4.800 kHz
; Tx Xtal Tol. = 10 ppm
; Rx Xtal Tol. = 10 ppm
; TRx Matching Network Type = 20 dBm
; Tx Power = +20 dBm
; Gaussian BT = 0.5
; PA Ramp = On-Autosel Rampstep
; PA Ramp Step = NA
; RF Performance = NA
; Output Drive Capability = 0.5mA
; Rx Duty-Cycle = Off
; Tx Duty-Cycle = Off
; Sleep Timer = Off
; Sleep Time = NA
; Rx Timer = Off
; Rx Time T1 = NA
; Rx Time T2 = NA
; Rx Exit State = STBY
; Tx Exit State = STBY
; TX Duty Cycle Persist = Off
; Packet Done Exit = Off
; TX Duty-Cycle Times = 0
; SLP Mode = Mode 0
; RSSI Valid Source = RSSI Compare
; PJD Window = NA
; RSSI Compare TH = -127 dBm
; CDR Type = Counting
; AFC = autosel
; FSK2 Data Map = 0:F-low 1:F-high
; FSK4 Data Map = NA
; FSK4 RX Data Map = NA
; CDR Type = Counting
; CDR Range Sel FSK = NA
; Channel BW = autosel
; Baseband BW FSK = autosel
; Data Mode = Packet
; Packet Mode = Normal
; PiggyBacking = Disable
; Manchester = Disable
; Manchester Type = NA
; Whitening = Disable
; Whiten Type = NA
; Whiten Seed Type = NA
; Whiten Seed = NA
; FEC = Disable
; FEC Type = NA
; FEC Padding Code = NA
; crc err clear fifo = Not Clear
; Tx Packet Gap = 32 symbol(s)
; Tx Packet Number = 1 packet(s)
; Tx Prefix Type = 0
; Packet Type = Fixed Length
; Address-Length Position = NA
; Length Size = 1-byte
; Payload Bit Order = Start from msb
; Address Field = Disable
; Preamble Rx Size = 2
; Preamble Tx Size = 8
; Preamble Value = 170
; Preamble Unit = 8-bit
; Sync Size = 3-byte
; Sync Format = S2LP
; Sync Value = 3003605
; Sync Manchester = Disable
; Sync Value Selection = Sync Value
; Sync FEC Value = 3003605
; Sync Tolerance = None
; Address Detect Mode = None
; Address Split Mode = NA
; Address Size = NA
; Address Err Mask = NA
; Address Free = NA
; Dest Addr Value = NA
; Src Addr Value = NA
; Dest Addr Bit Mask = NA
; Src Addr Bit Mask = NA
; Sequence Num = None
; Sequence Num Match = off
; Sequence Num Mode = NA
; Sequence Num Value = NA
; FCS2 = None
; FCS2 Value = NA
; Payload Length = 32
; CRC Options = None
; CRC Swap = NA
; CRC Seed = NA
; CRC Bit Invert = NA
; CRC Range = NA
; CRC Polynomial = NA
; CRC Bit Order = NA
; CRC Refin = NA
; CRC_Refout = NA
; Frequency Hopping Mode = Mode 2
; Freq Hopping Space = 10 kHz
; Hopping Channels = 10
; CSMA Mode = Disable
; CSMA RSSI Detection = NA
; Hopping Persist = Disable
; Hopping Intermediate State = TRFS
; CSMA Sleep Timer Random = NA
; CSMA Rx Time = NA
; CSMA Sleep Time M = NA
; CSMA Sleep Time R = NA
; CSMA Persist = NA
; CSMA Detect Times = NA
; Tx Auto Hopping = Disable
; Rx Auto Hopping = Disable
; Auto Acknowledge = off
; Auto Resend = off
; Maximum Resend Times = 1
; RSSI Detect Mode = always
; LFOSC LFXO Sel = LFOSC(32kHz)
; LF Clock Out = off
; Dout Mute = disable
; Dout Mute Sel = NA
; dout adjust mode = disable
; Dout Adjust Percentage = NA
; LBD Threshold = 2.4 v
; Antenna Diversity = off
; Antenna Switch Mode = NA
; Collision Detect = off
; Collision Step = NA
; RSSI Offset dB = NA
; RSSI Offset Sel = autosel
;---------------------------------------
; The following are the Register contents
;---------------------------------------
*****************************************************************************/
#if (PRODUCT_FREQUENCY == CM2310A_433MHZ)
/* [CMT page0] */
const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = {
0x12,
0x08,
0x00,
0xAA,
0x04,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0x45,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x08,
0x00,
0x00,
0x00,
0x00,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x00,
0xE4,
0x20,
0x20,
0x20,
0x01,
0x00,
0xD0,
0xE0,
0xE2,
0x84,
0x30,
0x04,
0xD0,
0xE0,
0x80,
0x00,
0x41,
0x00,
0x01,
0x00,
0x02,
0x00,
0x00,
0x03,
0x04,
};
/* [CMT page1] */
const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = {
0x10,
0x06,
0x00,
0xFF,
0x00,
0xCD,
0x02,
0x28,
0x50,
0x87,
0x31,
0x5B,
0x08,
0x00,
0xFF,
0x00,
0x6C,
0x14,
0xAE,
0x07,
0xB4,
0xEA,
0x04,
0xE0,
0x20,
0x08,
0x05,
0x8D,
0x06,
0x00,
0xA0,
0x7F,
0x00,
0x18,
0x00,
0x00,
0x1F,
0xE4,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0xCA,
0x6C,
0x14,
0x2E,
0xD8,
0x6B,
0x00,
0x80,
0x0F,
0x64,
0x06,
0x02,
0xEA,
0x04,
0x00,
0x36,
0x01,
0x20,
0xC8,
0x63,
0xA1,
0x15,
0x34,
0x58,
0x40,
0xD2,
0x74,
0xF0,
0x0F,
0x01,
0x17,
0xE6,
0x54,
0x08,
0x39,
0xE2,
0x27,
0x0C,
0x01,
0xB4,
0x06,
0x0F,
0x0E,
0x4C,
0x00,
0x00,
0xF6,
0x00,
0x00,
0x00,
0x10,
0x81,
0x00,
0x00,
0x47,
0x12,
0x25,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
#endif

352
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_868mhz.c Executable file
View File

@ -0,0 +1,352 @@
#include "radio_hal.h"
#include "CMT2310A_reg.h"
#include "CMT2310A_def.h"
/****************************************************************************
;---------------------------------------
; CMT2310A Configuration File
; Generated by CMOSTEK RFPDK 1.53_Update4
; 2023.01.14 10:34
;---------------------------------------
; Mode = Advanced
; Part Number = CMT2310A
; Frequency = 868.000 MHz
; DC-DC = Off
; Demodulation = GFSK
; Xtal Cap Load = 2
; Data Rate = 2.400 kbps
; Deviation = 4.800 kHz
; Tx Xtal Tol. = 10 ppm
; Rx Xtal Tol. = 10 ppm
; TRx Matching Network Type = 20 dBm
; Tx Power = +20 dBm
; Gaussian BT = 0.5
; PA Ramp = On-Autosel Rampstep
; PA Ramp Step = NA
; RF Performance = NA
; Output Drive Capability = 0.5mA
; Rx Duty-Cycle = Off
; Tx Duty-Cycle = Off
; Sleep Timer = Off
; Sleep Time = NA
; Rx Timer = Off
; Rx Time T1 = NA
; Rx Time T2 = NA
; Rx Exit State = STBY
; Tx Exit State = STBY
; TX Duty Cycle Persist = Off
; Packet Done Exit = Off
; TX Duty-Cycle Times = 0
; SLP Mode = Mode 0
; RSSI Valid Source = RSSI Compare
; PJD Window = NA
; RSSI Compare TH = -127 dBm
; CDR Type = Counting
; AFC = autosel
; FSK2 Data Map = 0:F-low 1:F-high
; FSK4 Data Map = NA
; FSK4 RX Data Map = NA
; CDR Type = Counting
; CDR Range Sel FSK = NA
; Channel BW = autosel
; Baseband BW FSK = autosel
; Data Mode = Packet
; Packet Mode = Normal
; PiggyBacking = Disable
; Manchester = Disable
; Manchester Type = NA
; Whitening = Disable
; Whiten Type = NA
; Whiten Seed Type = NA
; Whiten Seed = NA
; FEC = Disable
; FEC Type = NA
; FEC Padding Code = NA
; crc err clear fifo = Not Clear
; Tx Packet Gap = 32 symbol(s)
; Tx Packet Number = 1 packet(s)
; Tx Prefix Type = 0
; Packet Type = Fixed Length
; Address-Length Position = NA
; Length Size = 1-byte
; Payload Bit Order = Start from msb
; Address Field = Disable
; Preamble Rx Size = 2
; Preamble Tx Size = 8
; Preamble Value = 170
; Preamble Unit = 8-bit
; Sync Size = 3-byte
; Sync Format = S2LP
; Sync Value = 3003605
; Sync Manchester = Disable
; Sync Value Selection = Sync Value
; Sync FEC Value = 3003605
; Sync Tolerance = None
; Address Detect Mode = None
; Address Split Mode = NA
; Address Size = NA
; Address Err Mask = NA
; Address Free = NA
; Dest Addr Value = NA
; Src Addr Value = NA
; Dest Addr Bit Mask = NA
; Src Addr Bit Mask = NA
; Sequence Num = None
; Sequence Num Match = off
; Sequence Num Mode = NA
; Sequence Num Value = NA
; FCS2 = None
; FCS2 Value = NA
; Payload Length = 32
; CRC Options = None
; CRC Swap = NA
; CRC Seed = NA
; CRC Bit Invert = NA
; CRC Range = NA
; CRC Polynomial = NA
; CRC Bit Order = NA
; CRC Refin = NA
; CRC_Refout = NA
; Frequency Hopping Mode = Mode 2
; Freq Hopping Space = 10 kHz
; Hopping Channels = 10
; CSMA Mode = Disable
; CSMA RSSI Detection = NA
; Hopping Persist = Disable
; Hopping Intermediate State = TRFS
; CSMA Sleep Timer Random = NA
; CSMA Rx Time = NA
; CSMA Sleep Time M = NA
; CSMA Sleep Time R = NA
; CSMA Persist = NA
; CSMA Detect Times = NA
; Tx Auto Hopping = Disable
; Rx Auto Hopping = Disable
; Auto Acknowledge = off
; Auto Resend = off
; Maximum Resend Times = 1
; RSSI Detect Mode = always
; LFOSC LFXO Sel = LFOSC(32kHz)
; LF Clock Out = off
; Dout Mute = disable
; Dout Mute Sel = NA
; dout adjust mode = disable
; Dout Adjust Percentage = NA
; LBD Threshold = 2.4 v
; Antenna Diversity = off
; Antenna Switch Mode = NA
; Collision Detect = off
; Collision Step = NA
; RSSI Offset dB = NA
; RSSI Offset Sel = autosel
;---------------------------------------
; The following are the Register contents
;---------------------------------------
*****************************************************************************/
#if ( PRODUCT_FREQUENCY == CM2310A_868MHZ)
/* [CMT page0] */
const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = {
0x12,
0x08,
0x00,
0xAA,
0x04,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0x45,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x08,
0x00,
0x00,
0x00,
0x00,
0x1F,
0x04,
0x00,
0x00,
0x00,
0x00,
0xE4,
0x20,
0x20,
0x20,
0x01,
0x00,
0xD0,
0xE0,
0xE2,
0x84,
0x30,
0x04,
0xD0,
0xE0,
0x80,
0x00,
0x41,
0x00,
0x01,
0x00,
0x02,
0x00,
0x00,
0x03,
0x04,
};
/* [CMT page1] */
const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = {
0x10,
0x06,
0x00,
0xFF,
0x00,
0xCD,
0x02,
0x20,
0x50,
0x87,
0x31,
0x5B,
0x08,
0x00,
0xFF,
0x00,
0x6C,
0x00,
0x00,
0x08,
0xB4,
0xEA,
0x04,
0xE0,
0x20,
0x08,
0x05,
0x47,
0x03,
0x00,
0x91,
0x7F,
0x00,
0x18,
0x00,
0x00,
0x1F,
0xE4,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0xC0,
0x6C,
0x00,
0x40,
0xD8,
0x6B,
0x00,
0xC0,
0x0F,
0x64,
0x06,
0x02,
0xEA,
0x04,
0x00,
0x36,
0x01,
0x20,
0xC8,
0x63,
0xA1,
0x15,
0x34,
0x58,
0x40,
0xC3,
0x74,
0xF0,
0x0F,
0x01,
0x17,
0xE6,
0x54,
0x08,
0x39,
0xE2,
0x14,
0x18,
0x01,
0xB4,
0x06,
0x0F,
0x07,
0x4C,
0x00,
0x00,
0xF6,
0x00,
0x00,
0x00,
0x10,
0x81,
0x00,
0x00,
0x47,
0x12,
0x25,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
#endif

352
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_915mhz.c Executable file
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#include "radio_hal.h"
#include "CMT2310A_reg.h"
#include "CMT2310A_def.h"
/****************************************************************************
;---------------------------------------
; CMT2310A Configuration File
; Generated by CMOSTEK RFPDK 1.53_Update4
; 2023.01.14 10:34
;---------------------------------------
; Mode = Advanced
; Part Number = CMT2310A
; Frequency = 915.000 MHz
; DC-DC = Off
; Demodulation = GFSK
; Xtal Cap Load = 2
; Data Rate = 2.400 kbps
; Deviation = 4.800 kHz
; Tx Xtal Tol. = 10 ppm
; Rx Xtal Tol. = 10 ppm
; TRx Matching Network Type = 20 dBm
; Tx Power = +20 dBm
; Gaussian BT = 0.5
; PA Ramp = On-Autosel Rampstep
; PA Ramp Step = NA
; RF Performance = NA
; Output Drive Capability = 0.5mA
; Rx Duty-Cycle = Off
; Tx Duty-Cycle = Off
; Sleep Timer = Off
; Sleep Time = NA
; Rx Timer = Off
; Rx Time T1 = NA
; Rx Time T2 = NA
; Rx Exit State = STBY
; Tx Exit State = STBY
; TX Duty Cycle Persist = Off
; Packet Done Exit = Off
; TX Duty-Cycle Times = 0
; SLP Mode = Mode 0
; RSSI Valid Source = RSSI Compare
; PJD Window = NA
; RSSI Compare TH = -127 dBm
; CDR Type = Counting
; AFC = autosel
; FSK2 Data Map = 0:F-low 1:F-high
; FSK4 Data Map = NA
; FSK4 RX Data Map = NA
; CDR Type = Counting
; CDR Range Sel FSK = NA
; Channel BW = autosel
; Baseband BW FSK = autosel
; Data Mode = Packet
; Packet Mode = Normal
; PiggyBacking = Disable
; Manchester = Disable
; Manchester Type = NA
; Whitening = Disable
; Whiten Type = NA
; Whiten Seed Type = NA
; Whiten Seed = NA
; FEC = Disable
; FEC Type = NA
; FEC Padding Code = NA
; crc err clear fifo = Not Clear
; Tx Packet Gap = 32 symbol(s)
; Tx Packet Number = 1 packet(s)
; Tx Prefix Type = 0
; Packet Type = Fixed Length
; Address-Length Position = NA
; Length Size = 1-byte
; Payload Bit Order = Start from msb
; Address Field = Disable
; Preamble Rx Size = 2
; Preamble Tx Size = 8
; Preamble Value = 170
; Preamble Unit = 8-bit
; Sync Size = 3-byte
; Sync Format = S2LP
; Sync Value = 3003605
; Sync Manchester = Disable
; Sync Value Selection = Sync Value
; Sync FEC Value = 3003605
; Sync Tolerance = None
; Address Detect Mode = None
; Address Split Mode = NA
; Address Size = NA
; Address Err Mask = NA
; Address Free = NA
; Dest Addr Value = NA
; Src Addr Value = NA
; Dest Addr Bit Mask = NA
; Src Addr Bit Mask = NA
; Sequence Num = None
; Sequence Num Match = off
; Sequence Num Mode = NA
; Sequence Num Value = NA
; FCS2 = None
; FCS2 Value = NA
; Payload Length = 32
; CRC Options = None
; CRC Swap = NA
; CRC Seed = NA
; CRC Bit Invert = NA
; CRC Range = NA
; CRC Polynomial = NA
; CRC Bit Order = NA
; CRC Refin = NA
; CRC_Refout = NA
; Frequency Hopping Mode = Mode 2
; Freq Hopping Space = 10 kHz
; Hopping Channels = 10
; CSMA Mode = Disable
; CSMA RSSI Detection = NA
; Hopping Persist = Disable
; Hopping Intermediate State = TRFS
; CSMA Sleep Timer Random = NA
; CSMA Rx Time = NA
; CSMA Sleep Time M = NA
; CSMA Sleep Time R = NA
; CSMA Persist = NA
; CSMA Detect Times = NA
; Tx Auto Hopping = Disable
; Rx Auto Hopping = Disable
; Auto Acknowledge = off
; Auto Resend = off
; Maximum Resend Times = 1
; RSSI Detect Mode = always
; LFOSC LFXO Sel = LFOSC(32kHz)
; LF Clock Out = off
; Dout Mute = disable
; Dout Mute Sel = NA
; dout adjust mode = disable
; Dout Adjust Percentage = NA
; LBD Threshold = 2.4 v
; Antenna Diversity = off
; Antenna Switch Mode = NA
; Collision Detect = off
; Collision Step = NA
; RSSI Offset dB = NA
; RSSI Offset Sel = autosel
;---------------------------------------
; The following are the Register contents
;---------------------------------------
*****************************************************************************/
#if (PRODUCT_FREQUENCY == CM2310A_915MHZ)
/* [CMT page0] */
const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = {
0x12,
0x08,
0x00,
0xAA,
0x04,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0x45,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x08,
0x00,
0x00,
0x00,
0x00,
0x1F,
0x04,
0x00,
0x00,
0x00,
0x00,
0xE4,
0x20,
0x20,
0x20,
0x01,
0x00,
0xD0,
0xE0,
0xE2,
0x84,
0x30,
0x04,
0xD0,
0xE0,
0x80,
0x00,
0x41,
0x00,
0x01,
0x00,
0x02,
0x00,
0x00,
0x03,
0x04,
};
/* [CMT page1] */
const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = {
0x10,
0x06,
0x00,
0xFF,
0x00,
0xCD,
0x02,
0x20,
0x50,
0x87,
0x31,
0x5B,
0x08,
0x00,
0xFF,
0x00,
0x72,
0x00,
0x00,
0x06,
0xB4,
0xEA,
0x04,
0xE0,
0x20,
0x08,
0x05,
0x47,
0x03,
0x00,
0x88,
0x7F,
0x00,
0x18,
0x00,
0x00,
0x14,
0xE4,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0xC0,
0x72,
0x00,
0x40,
0xD6,
0x73,
0x00,
0xC0,
0x0F,
0x64,
0x06,
0x02,
0xEA,
0x04,
0x00,
0x36,
0x01,
0x20,
0xC8,
0x63,
0xA1,
0x15,
0x34,
0x58,
0x40,
0xC3,
0x74,
0xF0,
0x0F,
0x01,
0x17,
0xE6,
0x54,
0x08,
0x39,
0xE2,
0x14,
0x18,
0x01,
0xB4,
0x06,
0x0F,
0x07,
0x4C,
0x00,
0x00,
0xF6,
0x00,
0x00,
0x00,
0x10,
0x81,
0x00,
0x00,
0x47,
0x12,
0x25,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
#endif

115
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c Executable file
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#include "ebyte_e48x.h"
#include "ebyte_callback.h"
/* <20><><EFBFBD><EFBFBD>ʶ<EFBFBD><CAB6>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define EBYTE_E48_NAME_TYPE 0x00000048
/* <20><><EFBFBD><EFBFBD>ʶ<EFBFBD><CAB6>ģ<EFBFBD><C4A3>Ƶ<EFBFBD><C6B5> */
#if defined(EBYTE_E48_433M20S)
#define EBYTE_E48_FREQUENCY_TYPE 0x00000433
#elif defined(EBYTE_E48_900M20S)
#define EBYTE_E48_FREQUENCY_TYPE 0x00000900
#endif
/* <20><><EFBFBD><EFBFBD>ʶ<EFBFBD><CAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>汾<EFBFBD><E6B1BE> */
#define EBYTE_E48_PROGRAM_TYPE 0x10
#include "board.h"
uint8_t rf_rxbuffer[200];
uint8_t rf_rxsize;
uint8_t radio_rece_data_flag;
extern uint32_t g_chip_id;
void Ebyte_E48x_Init( void )
{
/* Step1 */
vRadioPowerUp(); // Release RST(GPIO5)
vRadioSetAntSwitch(FALSE, FALSE); // Disable GPIO0 & GPIO1 as antenna switch control
vRadioSpiModeSel(FALSE); // SPI 4-Wire mode
/* Step2 */
g_chip_id = lRadioChipVersion();
if(0x00231000 != (g_chip_id & 0x00FFFF00)) {
EBYTE_LOG("[%s|%u] Error, dismatch Chip-ID[%#x](!=0x231000).\r\n", __FUNCTION__, __LINE__, g_chip_id);
return;
}
EBYTE_LOG("[%s|%u] Info, Link Device:E48-XXXM20S.\r\n", __FUNCTION__, __LINE__);
/* Step3 */
if (bRadioGetState() == CMT2310A_STATE_IS_READY) {
EBYTE_LOG("[%s|%u] Infor, CMT2310 already in State[READY], so skip initialization.\r\n", __FUNCTION__, __LINE__);
return;
}
EBYTE_LOG("[%s|%u] Info, goto initialize E48-XXXM20S.\r\n", __FUNCTION__, __LINE__);
/* Step4 */
vRadioInit();
}
void Ebyte_E48x_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout )
{
vRadioTransmit( payload, size );
}
void Ebyte_E48x_SetRx( uint32_t timeout )
{
vRadioReceive();
}
void Ebyte_E48x_SetStandby( uint8_t cmd )
{
vRadioStandby();
}
void Ebyte_E48x_SetSleep( uint8_t cmd )
{
return;
}
void Ebyte_E48x_IntOrPollTask( void )
{
radio_rece_data_flag = gpio_input_bit_get( BSP_GPIO_PORT_E48_GP4 , BSP_GPIO_PIN_E48_GP4);
/* <20>н<EFBFBD><D0BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if( radio_rece_data_flag != RESET ) {
vRadioGetPacket(rf_rxbuffer, &rf_rxsize);
Ebyte_Port_ReceiveCallback(0x0002,rf_rxbuffer,rf_rxsize);
}
}
void Ebyte_E48x_InterruptTrigger( void )
{
}
/* !
* @brief <20><>ȡģ<C8A1><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* @return 32λ<32>ı<EFBFBD><C4B1><EFBFBD>
* @note <20><>16λ<36><CEBB><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>0x0220 <20><><EFBFBD><EFBFBD>E22ģ<32><C4A3>
* <20><>16λ<36><CEBB><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>0x0400 <20><><EFBFBD><EFBFBD>400Ƶ<30><C6B5>
*/
uint32_t Ebyte_E48x_GetName(void)
{
return ( ( (uint32_t)EBYTE_E48_NAME_TYPE << 16 ) | (uint32_t)EBYTE_E48_FREQUENCY_TYPE);
}
/* !
* @brief <20><>ȡģ<C8A1><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>汾
*
* @return 8λ<38>ı<EFBFBD><C4B1><EFBFBD>
* @note <20><><EFBFBD><EFBFBD>0x10 <20><><EFBFBD><EFBFBD>V1.0
*/
uint8_t Ebyte_E48x_GetDriverVersion(void)
{
return EBYTE_E48_PROGRAM_TYPE;
}

24
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.h Executable file
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#ifndef _EBYTE_E48X_H_
#define _EBYTE_E48X_H_
#include "radio.h"
#include "radio_hal.h"
#include "radio_mac.h"
#include "radio_phy.h"
#include "radio_spi.h"
#include "ebyte_conf.h"
void Ebyte_E48x_Init( void );
void Ebyte_E48x_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout );
void Ebyte_E48x_SetRx( uint32_t timeout );
void Ebyte_E48x_SetSleep( uint8_t cmd );
void Ebyte_E48x_SetStandby( uint8_t cmd );
void Ebyte_E48x_IntOrPollTask( void );
void Ebyte_E48x_InterruptTrigger( void );
uint32_t Ebyte_E48x_GetName(void);
uint8_t Ebyte_E48x_GetDriverVersion(void);
#endif

423
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c Executable file
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#include "radio.h"
#include "board.h"
CMT2310A_CFG g_radio; //
uint8_t g_reg_read_buf[128];
uint32_t g_chip_id = 0;
//<2F><><EFBFBD>ɵ<EFBFBD><C9B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD>270~276<37>У<EFBFBD><D0A3><EFBFBD>Ӧ<EFBFBD><D3A6>7<EFBFBD><37><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>
const uint8_t cmt2310a_power[55][7] = {
{0x20,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-0.h */
{0x25,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-1.h */
{0x68,0x1B,0x00,0x3A,0x00,0x00,0x05 }, /* cmt2310a_params13-10.h */
{0x36,0x2D,0x00,0x22,0x00,0x00,0x07 }, /* cmt2310a_params13-11.h */
{0x40,0x2D,0x00,0x22,0x00,0x00,0x08 }, /* cmt2310a_params13-12.h */
{0x4D,0x2D,0x00,0x22,0x00,0x00,0x0C }, /* cmt2310a_params13-13.h */
{0x2A,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-2.h */
{0x30,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-3.h */
{0x35,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-4.h */
{0x3A,0x1B,0x00,0x3A,0x00,0x00,0x02 }, /* cmt2310a_params13-5.h */
{0x41,0x1B,0x00,0x3A,0x00,0x00,0x02 }, /* cmt2310a_params13-6.h */
{0x48,0x1B,0x00,0x3A,0x00,0x00,0x02 }, /* cmt2310a_params13-7.h */
{0x50,0x1B,0x00,0x3A,0x00,0x00,0x03 }, /* cmt2310a_params13-8.h */
{0x5B,0x1B,0x00,0x3A,0x00,0x00,0x04 }, /* cmt2310a_params13-9.h */
{0x1C,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-N1.h */
{0x19,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N10.h */
{0x19,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-N2.h */
{0x16,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-N3.h */
{0x35,0x12,0x00,0x57,0x00,0x00,0x02 }, /* cmt2310a_params13-N4.h */
{0x2F,0x12,0x00,0x57,0x00,0x00,0x02 }, /* cmt2310a_params13-N5.h */
{0x29,0x12,0x00,0x57,0x00,0x00,0x02 }, /* cmt2310a_params13-N6.h */
{0x25,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N7.h */
{0x20,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N8.h */
{0x1C,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N9.h */
{0x2A,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-0.h */
{0x2F,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-1.h */
{0x39,0x3F,0x00,0x18,0x00,0x00,0x06 }, /* cmt2310a_params20-10.h */
{0x40,0x3F,0x00,0x18,0x00,0x00,0x07 }, /* cmt2310a_params20-11.h */
{0x49,0x3F,0x00,0x18,0x00,0x00,0x08 }, /* cmt2310a_params20-12.h */
{0x53,0x3F,0x00,0x18,0x00,0x00,0x0A }, /* cmt2310a_params20-13.h */
{0x5F,0x3F,0x00,0x18,0x00,0x00,0x0C }, /* cmt2310a_params20-14.h */
{0x70,0x3F,0x00,0x18,0x00,0x00,0x0F }, /* cmt2310a_params20-15.h */
{0x85,0x3F,0x00,0x18,0x00,0x00,0x14 }, /* cmt2310a_params20-16.h */
{0x50,0x7F,0x00,0x18,0x00,0x00,0x12 }, /* cmt2310a_params20-17.h */
{0x69,0x7F,0x00,0x18,0x00,0x00,0x18 }, /* cmt2310a_params20-18.h */
{0x80,0x7F,0x00,0x18,0x00,0x00,0x1C }, /* cmt2310a_params20-19.h */
{0x35,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-2.h */
{0xA0,0x7F,0x00,0x18,0x00,0x00,0x1F }, /* cmt2310a_params20-20.h */
{0x3C,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-3.h */
{0x42,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-4.h */
{0x49,0x1F,0x00,0x32,0x00,0x00,0x02 }, /* cmt2310a_params20-5.h */
{0x54,0x1F,0x00,0x32,0x00,0x00,0x02 }, /* cmt2310a_params20-6.h */
{0x5F,0x1F,0x00,0x32,0x00,0x00,0x03 }, /* cmt2310a_params20-7.h */
{0x6B,0x1F,0x00,0x32,0x00,0x00,0x03 }, /* cmt2310a_params20-8.h */
{0x33,0x3F,0x00,0x18,0x00,0x00,0x05 }, /* cmt2310a_params20-9.h */
{0x25,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-N1.h */
{0x1A,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N10.h */
{0x21,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-N2.h */
{0x1D,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-N3.h */
{0x36,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N4.h */
{0x30,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N5.h */
{0x2A,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N6.h */
{0x25,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N7.h */
{0x21,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N8.h */
{0x1D,0x16,0x00,0x47,0x00,0x00,0x01 } /* cmt2310a_params20-N9.h */
};
/******************************
**Name: vRadioInit
**Func: Radio config spi & reset
**Input: None
*Output: None
********************************/
void vRadioInit( void )
{
byte fw_rev;
/* Step4 */
vRadioHardReset();
/* Step5 */
vRadioConfigPageReg( 0, g_cmt2310a_page0, CMT2310A_PAGE0_SIZE ); //config page 0
vRadioConfigPageReg( 1, g_cmt2310a_page1, CMT2310A_PAGE1_SIZE ); //config page 1
vRadioSetNirq( CMT2310A_nIRQ_TCXO ); //for TCXO need cofig as nIRQ pin at first
vRadioTcxoDrvSel( 0 ); //drive power
fw_rev = (byte)g_chip_id; //dealwith Xtal
switch(fw_rev)
{
case 0xC0:
vRadioXoWaitCfg(RADIO_CGU_DIV4);
break;
default:
break;
}
/* Step6 */
vRadioPowerUpBoot();
delay1ms( 10 );
/* Step7 */
bRadioGoStandby();
delay1ms( 2 );
bRadioApiCommand( 0x02 ); //
delay1ms( 10 );
/* Step8 */
bRadioApiCommand( 0x01 ); //IR Calibration, need some times
vRadioCapLoad( 2 ); //Xo Cap
/* Step9, GPIOn and interrupt setting */
vRadioSetGpio0( CMT2310A_GPIO0_INT3 );
vRadioSetGpio1( CMT2310A_GPIO1_INT2 );
vRadioSetGpio2( CMT2310A_GPIO2_DCLK );
vRadioSetGpio3( CMT2310A_GPIO3_DOUT );
vRadioSetGpio4( CMT2310A_GPIO4_INT1 );
vRadioSetGpio5( CMT2310A_GPIO5_nRST );
//INT1 = RX_FIFO_WBYTE, INT2 = PKT_DONE
vRadioSetInt1Sel( INT_SRC_RX_FIFO_WBYTE );
vRadioSetInt2Sel( INT_SRC_PKT_DONE );
vRadioSetInt1Polar( FALSE );
vRadioSetInt2Polar( FALSE );
vRadioSetInt3Polar( FALSE );
//interrupt source enable config
g_radio.int_src_en._BITS.PKT_DONE_EN = 1;
g_radio.int_src_en._BITS.CRC_PASS_EN = 1;
g_radio.int_src_en._BITS.ADDR_PASS_EN = 0;
g_radio.int_src_en._BITS.SYNC_PASS_EN = 1;
g_radio.int_src_en._BITS.PREAM_PASS_EN = 1;
g_radio.int_src_en._BITS.TX_DONE_EN = 1;
g_radio.int_src_en._BITS.RX_TOUT_EN = 1;
g_radio.int_src_en._BITS.LD_STOP_EN = 0;
g_radio.int_src_en._BITS.LBD_STOP_EN = 0;
g_radio.int_src_en._BITS.LBD_STAT_EN = 0;
g_radio.int_src_en._BITS.PKT_ERR_EN = 0;
g_radio.int_src_en._BITS.RSSI_COLL_EN = 0;
g_radio.int_src_en._BITS.OP_CMD_FAILED_EN = 0;
g_radio.int_src_en._BITS.RSSI_PJD_EN = 0;
g_radio.int_src_en._BITS.SEQ_MATCH_EN = 0;
g_radio.int_src_en._BITS.NACK_RECV_EN = 0;
g_radio.int_src_en._BITS.TX_RESEND_DONE_EN = 0;
g_radio.int_src_en._BITS.ACK_RECV_FAILED_EN = 0;
g_radio.int_src_en._BITS.TX_DC_DONE_EN = 0;
g_radio.int_src_en._BITS.CSMA_DONE_EN = 0;
g_radio.int_src_en._BITS.CCA_STAT_EN = 0;
g_radio.int_src_en._BITS.API_DONE_EN = 0;
g_radio.int_src_en._BITS.TX_FIFO_TH_EN = 1;
g_radio.int_src_en._BITS.TX_FIFO_NMTY_EN = 1;
g_radio.int_src_en._BITS.TX_FIFO_FULL_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_OVF_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_TH_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_NMTY_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_FULL_EN = 1;
vRadioInterruptSoucreCfg( &g_radio.int_src_en );
//packet preamble config
g_radio.preamble_cfg.PREAM_LENG_UNIT = 0; //8-bits mode
g_radio.preamble_cfg.PREAM_VALUE = 0xAA; //
g_radio.preamble_cfg.RX_PREAM_SIZE = 2; //
g_radio.preamble_cfg.TX_PREAM_SIZE = 16;
vRadioCfgPreamble( &g_radio.preamble_cfg );
//packet syncword config
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MAN_EN = 0; //disable syncword manchester coding
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_SIZE = 2; //enable 3 bytes for syncword
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_TOL = 0;
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MODE_SEL = 0; //normal packet
g_radio.sync_cfg.SYNC_VALUE[0] = 0xAA;
g_radio.sync_cfg.SYNC_VALUE[1] = 0x2D;
g_radio.sync_cfg.SYNC_VALUE[2] = 0xD4;
g_radio.sync_cfg.SYNC_VALUE_SEL = 0; //select SYN_VAL
vRadioCfgSyncWord( &g_radio.sync_cfg );
//packet node address config
g_radio.addr_cfg.ADDR_CFG_u._BITS.ADDR_DET_MODE = 0; //disable Node Address
vRadioCfgNodeAddr( &g_radio.addr_cfg );
//packet crc config
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_EN = 1; //enable crc
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_ORDER = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFIN = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_RANGE = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_INV = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BYTE_SWAP = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFOUT = 0; //whole payload
g_radio.crc_cfg.CRC_CFG_u._BITS.CRCERR_CLR_FIFO_EN = 0; //note: need ative FIFO_AUTO_CLR_RX_EN = 1 or call vRadioFifoAutoClearGoRx(1)
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_SIZE = 1; //crc-16 mode
g_radio.crc_cfg.CRC_POLY_u.u32_POLY = 0x10210000;
g_radio.crc_cfg.CRC_SEED_u.u32_SEED = 0x00000000;
vRadioCfgCrc( &g_radio.crc_cfg );
//packet coding format
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_EN = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_TYPE = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_EN = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_TYPE = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_SEED_TYP = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_EN = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_RSC_NRNSC_SEL = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_TICC = 0;
g_radio.coding_format_cfg.WHITEN_SEED = 0x01FF;
g_radio.coding_format_cfg.FEC_PAD_CODE = 0;
vRadioCfgCodeFormat( &g_radio.coding_format_cfg );
//packet frame format
g_radio.frame_cfg.DATA_MODE = 2; //0=direct mode, 2=packet mode
g_radio.frame_cfg.FRAME_CFG1_u._BITS.PKT_TYPE = 1; //0=fixd-length packet mode 1=<3D>ɱ䳤
g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAYLOAD_BIT_ORDER = 0; //msb first
g_radio.frame_cfg.FRAME_CFG1_u._BITS.ADDR_LEN_CONF = 0;
g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAGGYBACKING_EN = 0;
g_radio.frame_cfg.FRAME_CFG1_u._BITS.LENGTH_SIZE = 0;
g_radio.frame_cfg.FRAME_CFG1_u._BITS.INTERLEAVE_EN = 0; //note: when FEC enable, INTERLEAVE_EN should be set 1
g_radio.frame_cfg.FRAME_CFG2_u._BITS.TX_PREFIX_TYPE = TX_PREFIX_SEL_PREAMBLE; //transmit preamble
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_EN = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_AUTO_INC = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_SIZE = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_MACH_EN = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.FCS2_EN = 0;
g_radio.frame_cfg.TX_PKT_NUM = 0;
g_radio.frame_cfg.TX_PKT_GAP = 0;
g_radio.frame_cfg.FCS2_TX_IN = 0;
g_radio.frame_cfg.PAYLOAD_LENGTH = UHF_LEN;
vRadioCfgFrameFormat( &g_radio.frame_cfg );
//Run Mode Config
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_ACK_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_PERSIST_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_AUTO_HOP_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_EXIT_STATE = EXIT_TO_READY;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_DC_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_AUTO_HOP_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_EXIT_STATE = EXIT_TO_READY;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.CSMA_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.PKT_DONE_EXIT_EN = 0; //depend on RX_EXIT_STATE
g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.RX_HOP_SLP_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.SLP_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_OUT_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_SEL = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.TIMER_RAND_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_WIN_SEL = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_INT_SEL = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_PERSIST_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG6_u._BITS.FREQ_HOP_MANU_EN = 1;//ʹ<><CAB9><EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD>Ƶ<EFBFBD>޷<EFBFBD>ʹ<EFBFBD><CAB9>
g_radio.word_mode_cfg.FREQ_CHANL_NANU = 92;//<2F>ֶ<EFBFBD><D6B6><EFBFBD>Ƶ<EFBFBD>ŵ<EFBFBD>0~255
g_radio.word_mode_cfg.FREQ_DONE_TIMES = 0;
g_radio.word_mode_cfg.FREQ_SPACE = 250;//<2F><>Ƶ<EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>0~255 KHz
g_radio.word_mode_cfg.FREQ_TIMES = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_M = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_R = 0;
g_radio.word_mode_cfg.RX_TIMER_T1_M = 0; //M*2^(R+1)*5us=M*2^R*10us,
g_radio.word_mode_cfg.RX_TIMER_T1_R = 0; //R=7, unit=0.64ms
g_radio.word_mode_cfg.RX_TIMER_T2_M = 0;
g_radio.word_mode_cfg.RX_TIMER_T2_R = 0;
g_radio.word_mode_cfg.RX_TIMER_CSMA_M = 0;
g_radio.word_mode_cfg.RX_TIMER_CSMA_R = 0;
g_radio.word_mode_cfg.TX_DC_TIMES = 0;
g_radio.word_mode_cfg.TX_RS_TIMES = 0;
g_radio.word_mode_cfg.CSMA_TIMES = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_M = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_R = 0;
vRadioCfgWorkMode( &g_radio.word_mode_cfg );
//FIFO Init
vRadioFifoMerge( FALSE );
vRadioSetFifoTH( 30 );
vRadioClearRxFifo(); //reset & clear fifo
vRadioClearTxFifo();
vRadioFifoAutoClearGoRx( TRUE ); //when crc error, need to auto clear fifo, should enable
vRadioRssiUpdateSel( CMT2310A_RSSI_UPDATE_ALWAYS );
vRadioSetAntSwitch( FALSE, FALSE ); //
vRadioDcdcCfg( TRUE ); //dc-dc off
}
void vRadioClearInterrupt( void )
{
vRadioInterruptSoucreFlag( &g_radio.int_src_flag );
g_radio.int_src_clear._BITS.SLEEP_TMO_CLR = g_radio.int_src_flag._BITS.SLEEP_TMO_FLG;
g_radio.int_src_clear._BITS.RX_TMO_CLR = g_radio.int_src_flag._BITS.RX_TMO_FLG;
g_radio.int_src_clear._BITS.TX_DONE_CLR = g_radio.int_src_flag._BITS.TX_DONE_FLG;
g_radio.int_src_clear._BITS.PKT_DONE_CLR = g_radio.int_src_flag._BITS.PKT_DONE_FLG;
g_radio.int_src_clear._BITS.CRC_PASS_CLR = g_radio.int_src_flag._BITS.CRC_PASS_FLG;
g_radio.int_src_clear._BITS.ADDR_PASS_CLR = g_radio.int_src_flag._BITS.ADDR_PASS_FLG;
g_radio.int_src_clear._BITS.SYNC_PASS_CLR = g_radio.int_src_flag._BITS.SYNC_PASS_FLG | g_radio.int_src_flag._BITS.SYNC1_PASS_FLG;
g_radio.int_src_clear._BITS.PREAM_PASS_CLR = g_radio.int_src_flag._BITS.PREAM_PASS_FLG;
g_radio.int_src_clear._BITS.LBD_STAT_CLR = g_radio.int_src_flag._BITS.LBD_STATUS_FLG;
g_radio.int_src_clear._BITS.PKT_ERR_CLR = g_radio.int_src_flag._BITS.PKT_ERR_FLG;
g_radio.int_src_clear._BITS.RSSI_COLL_CLR = g_radio.int_src_flag._BITS.RSSI_COLL_FLG;
g_radio.int_src_clear._BITS.OP_CMD_FAILED_CLR = g_radio.int_src_flag._BITS.OP_CMD_FAILED_FLG;
g_radio.int_src_clear._BITS.ANT_LOCK_CLR = g_radio.int_src_flag._BITS.ANT_LOCK_FLG;
g_radio.int_src_clear._BITS.SEQ_MATCH_CLR = g_radio.int_src_flag._BITS.SEQ_MATCH_FLG;
g_radio.int_src_clear._BITS.NACK_RECV_CLR = g_radio.int_src_flag._BITS.NACK_RECV_FLG;
g_radio.int_src_clear._BITS.TX_RESEND_DONE_CLR = g_radio.int_src_flag._BITS.TX_RESEND_DONE_FLG ;
g_radio.int_src_clear._BITS.ACK_RECV_FAILED_CLR = g_radio.int_src_flag._BITS.ACK_RECV_FAILED_FLG;
g_radio.int_src_clear._BITS.TX_DC_DONE_CLR = g_radio.int_src_flag._BITS.TX_DC_DONE_FLG;
g_radio.int_src_clear._BITS.CSMA_DONE_CLR = g_radio.int_src_flag._BITS.CSMA_DONE_FLG;
g_radio.int_src_clear._BITS.CCA_STATUS_CLR = g_radio.int_src_flag._BITS.CCA_STATUS_FLG;
g_radio.int_src_clear._BITS.API_DONE_CLR = g_radio.int_src_flag._BITS.API_DONE_FLG;
vRadioInterruptSoucreClear( &g_radio.int_src_clear );
}
void vRadioReadAllStatus( void )
{
bRadioGetState(); //read work status
vRadioFifoGetStatus( &g_radio.fifo_status_flag ); //read fifo status
vRadioInterruptSoucreFlag( &g_radio.int_src_flag ); //read interrupt flag
bRadioReadReg( CMT2310A_CTL_REG_04 ); //get GPIO1/GPIO0 selection
bRadioReadReg( CMT2310A_CTL_REG_05 ); //get GPIO3/GPIO2 selection
bRadioReadReg( CMT2310A_CTL_REG_06 ); //get GPIO5/GPIO4 selection
bRadioReadReg( CMT2310A_CTL_REG_16 ); //get INT1 selection
bRadioReadReg( CMT2310A_CTL_REG_17 ); //get INT2 selection
}
void vRadioCmpReg( byte const wr_ptr[], byte rd_ptr[], byte cmp_ptr[], byte length )
{
byte i;
for( i = 0; i < length; i++ )
{
if( wr_ptr[i] != rd_ptr[i] )
{
cmp_ptr[i] = 0xFF;
}
else
{
cmp_ptr[i] = 0x00;
}
}
}
void vRadioGoTxInit( void )
{
}
void vRadioGoRxInit( void )
{
}
void vRadioReceive(void)
{
g_radio.frame_cfg.PAYLOAD_LENGTH = UHF_LEN;
vRadioSetPayloadLength(&g_radio.frame_cfg);
vRadioSetInt1Sel(CMT2310A_INT_PKT_DONE);
vRadioSetInt2Sel(CMT2310A_INT_RX_FIFO_WBYTE);
bRadioGoRx();
}
void vRadioTransmit(uint8_t* buffer, uint8_t length )
{
vRadioSetInt1Sel( CMT2310A_INT_TX_DONE );
vRadioSetInt2Sel( CMT2310A_INT_TX_FIFO_NMTY );
g_radio.frame_cfg.PAYLOAD_LENGTH = length;
vRadioSetPayloadLength( &g_radio.frame_cfg );
vRadioWriteFifo( buffer, length );
// vRadioReadTxFifo(radio_rx_buf, 20);
// vRadioManualResetTxFifoPointer();
bRadioGoTx();
while ( gpio_input_bit_get( BSP_GPIO_PORT_E48_GP4 , BSP_GPIO_PIN_E48_GP4) == RESET);
bRadioGoStandby();
vRadioClearTxFifo();
vRadioClearInterrupt();
vRadioReceive();
}
void vRadioStandby( void )
{
bRadioGoStandby();
vRadioClearTxFifo();
vRadioClearRxFifo();
vRadioClearInterrupt();
}
uint8_t vRadioGetPacket(uint8_t *buffer,uint8_t *length)
{
uint8_t rx_length;
if( g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_EN == 1 )
{
vRadioInterruptSoucreFlag( &g_radio.int_src_flag );
if( g_radio.int_src_flag._BITS.CRC_PASS_FLG == 1 )
{
// g_rx_count++;
}
}
else
{
// g_rx_count++;
}
vRadioReadFifo(&rx_length, 1);
vRadioReadFifo(buffer, rx_length);
*length = rx_length;
vRadioClearRxFifo();
vRadioClearInterrupt();
bRadioGoRx();
return 0;
}
void vRadioCheckLink(void)
{
uint8_t i = 0;
while(1) {
vRadioSoftReset();
vRadioPowerUpBoot();
delay1ms(10);
g_chip_id = lRadioChipVersion();
if(0x00231000==(g_chip_id&0x00FFFF00)) break;
EBYTE_LOG( "Link Error.....\r\n" );
delay1ms(500);
i++;
if(i >= 20) while(1);
}
EBYTE_LOG( "Link Device:E48-XXXM20S....\r\n" );
}
void vRadioSetFreqChannel(uint8_t channel)
{
bRadioGoStandby();
bRadioWriteReg( CMT2310A_CTL_REG_03, channel);
}

41
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.h Executable file
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#ifndef __RADIO_H
#define __RADIO_H
#include <stdint.h>
#include "radio_phy.h"
#include "radio_mac.h"
#include "CMT2310A_def.h"
#include "CMT2310A_reg.h"
#define UHF_LEN 30 //
extern const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE];
extern const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE];
extern const uint8_t g_cmt2310a_page2[CMT2310A_PAGE2_SIZE];
extern void vRadioInit( void );
extern void vRadioClearInterrupt( void );
extern void vRadioReadAllStatus( void );
extern void vRadioCmpReg( byte const wr_ptr[], byte rd_ptr[], byte cmp_ptr[], byte length );
extern void vRadioGoTxInit( void );
extern void vRadioGoRxInit( void );
extern void vRadioTransmit(uint8_t* buffer, uint8_t length );
extern void vRadioReceive(void);
extern void vRadioStandby(void);
extern uint8_t vRadioGetPacket(uint8_t *buffer,uint8_t *length);
extern void vRadioCheckLink(void);
extern void vRadioSetFreqChannel(uint8_t channel);
#endif

626
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c Executable file
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#include "radio_hal.h"
#include "board.h"
void delay1ms(uint16_t cnt)
{
Ebyte_Port_DelayMs(cnt);
}
void delay10us(uint32_t cnt)
{
Ebyte_Port_DelayUs(cnt * 10);
}
/******************************
**Name: vRadioGpioInit
**Func: Radio SPI-4 and GPIO config
**Input: None
*Output: None
********************************/
void vRadioGpioInit( void )
{
vSpiMasterInit(); //init spi-4 gpio
}
/******************************
**Name: bRadioReadReg
**Func: radio read one register
**Input: None
*Output: read out data
********************************/
uint8_t bRadioReadReg( uint8_t addr )
{
return( bSpiReadByte( addr ) );
}
/******************************
**Name: bRadioWriteReg
**Func: radio write one register
**Input: None
*Output: old data
********************************/
uint8_t bRadioWriteReg( uint8_t addr, uint8_t reg_dat )
{
return( bSpiWriteByte( addr, reg_dat ) );
}
/******************************
**Name: bRadioSetReg
**Func: radio set some bits of register
**Input: None
*Output: old data
********************************/
uint8_t bRadioSetReg( uint8_t addr, uint8_t set_bits, uint8_t mask_bits )
{
uint8_t tmp_dat;
tmp_dat = bSpiReadByte( addr );
tmp_dat &= ( ~mask_bits );
tmp_dat |= ( set_bits & mask_bits );
return( bSpiWriteByte( addr, tmp_dat ) );
}
/******************************
**Name: vRadioLoadRegs
**Func: radio read some registers
**Input: None
*Output: None
********************************/
void vRadioLoadRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length )
{
uint8_t i;
for( i = 0; i < length; i++ )
{
ptr_buf[i] = bSpiReadByte( sta_adr++ );
}
}
/******************************
**Name: vRadioStoreRegs
**Func: radio write some registers
**Input: None
*Output: None
********************************/
void vRadioStoreRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length )
{
uint8_t i;
for( i = 0; i < length; i++ )
{
bSpiWriteByte( sta_adr++, ptr_buf[i] );
}
}
/******************************
**Name: vRadioBurstReadRegs
**Func: radio read some registers, just for
** Page0, start from 0x28, Packet Config Area & System Config Area, bank 5~15
** Page1, start from 0x00
**Input: None
*Output: None
********************************/
void vRadioBurstReadRegs( uint8_t* ptr_buf, uint8_t length )
{
vSpiBurstRead( CMT2310A_CRW_PORT, ptr_buf, length );
}
/******************************
**Name: vRadioBurstWriteRegs
**Func: radio write some registers, just for
** Page0, start from 0x28, Packet Config Area & System Config Area, bank 5~15
** Page1, start from 0x00
**Input: None
*Output: None
********************************/
void vRadioBurstWriteRegs( uint8_t* ptr_buf, uint8_t length )
{
vSpiBurstWrite( CMT2310A_CRW_PORT, ptr_buf, length );
}
/******************************
**Name: vRadioReadFifo
**Func: radio read FIFO
**Input: None
*Output: None
********************************/
void vRadioReadFifo( uint8_t* ptr_fifo, uint8_t length )
{
uint8_t tmp;
tmp = bRadioReadReg( CMT2310A_CTL_REG_19 );
if( tmp & M_FIFO_MERGE_EN ) //when fifo merge
{
tmp &= ( ~M_FIFO_TX_RX_SEL );
bRadioWriteReg( CMT2310A_CTL_REG_19, tmp );
}
vSpiBurstRead( CMT2310A_FIFO_RW_PORT, ptr_fifo, length );
}
/******************************
**Name: vRadioWriteFifo
**Func: radio write FIFO
**Input: None
*Output: None
********************************/
void vRadioWriteFifo( uint8_t* ptr_fifo, uint8_t length )
{
uint8_t tmp;
tmp = bRadioReadReg( CMT2310A_CTL_REG_19 );
if( tmp & M_FIFO_MERGE_EN ) //when fifo merge
{
tmp &= ( ~M_FIFO_TX_RX_SEL );
bRadioWriteReg( CMT2310A_CTL_REG_19, tmp ); //TX FIFO
}
vSpiBurstWrite( CMT2310A_FIFO_RW_PORT, ptr_fifo, length );
}
/******************************
**Name: vRadioReadTxFifo
**Func: radio read FIFO
**Input: None
*Output: None
********************************/
void vRadioReadTxFifo( uint8_t* ptr_fifo, uint8_t length )
{
uint8_t tmp;
tmp = bRadioReadReg( CMT2310A_CTL_REG_19 );
if( tmp & M_FIFO_MERGE_EN ) //when fifo merge
{
tmp &= ( ~M_FIFO_TX_RX_SEL );
}
tmp |= M_FIFO_TX_TEST_EN;
bRadioWriteReg( CMT2310A_CTL_REG_19, tmp );
vSpiBurstRead( CMT2310A_FIFO_RW_PORT, ptr_fifo, length );
tmp &= ( ~M_FIFO_TX_TEST_EN );
bRadioWriteReg( CMT2310A_CTL_REG_19, tmp );
}
//######################################################################
// GPIO
//######################################################################
/******************************
**Name: vRadioSpiModeSel
**Func: Radio SPI-4 or SPI-3 Select
**Input: FALSE: select SPI-4
* TRUE: select SPI-3
*Output: None
**note: should be point to page0
********************************/
void vRadioSpiModeSel( boolean_t spi_mod )
{
if( spi_mod )
{
bRadioSetReg( CMT2310A_CTL_REG_07, M_SPI_3W_EN, VAL_BIT3 );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_07, 0, VAL_BIT3 );
}
}
/******************************
**Name: vRadioSetTxDin
**Func: Radio tx_din enable or disable
**Input: cfg_din, FALSE: disable
* TRUE: enable
* pin_sel, CMT2310A_TX_DIN_GPIO3: GPIO3 as Tx Din
* CMT2310A_TX_DIN_GPIO4: GPIO4 as Tx Din
* CMT2310A_TX_DIN_nIRQ: NIRQ as Tx Din
*Output: None
********************************/
void vRadioSetTxDin( boolean_t cfg_din, uint8_t pin_sel )
{
bRadioSetReg( CMT2310A_CTL_REG_05, pin_sel, CMT2310A_TX_DIN_SEL );
if( cfg_din )
{
bRadioSetReg( CMT2310A_CTL_REG_04, CMT2310A_TX_DIN_EN, CMT2310A_TX_DIN_EN );
vRadioRegPageSel( 1 );
bRadioSetReg( CMT2310A_TX_DR_REG_02, ( 0 << 7 ), ( 1 << 7 ) );
vRadioRegPageSel( 0 );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_04, 0, CMT2310A_TX_DIN_EN );
vRadioRegPageSel( 1 );
bRadioSetReg( CMT2310A_TX_DR_REG_02, ( 1 << 7 ), ( 1 << 7 ) );
vRadioRegPageSel( 0 );
}
}
/******************************
**Name: vRadioSetDclk
**Func: Radio digital clkout enable or disable
**Input: FALSE: disable
* TRUE: enable
*Output: None
* note: only active on GPIO4, and priority high over than other function on GPIO4
********************************/
void vRadioSetDigClkOut( boolean_t cfg_out )
{
if( cfg_out )
{
bRadioSetReg( CMT2310A_CTL_REG_06, CMT2310A_DIG_CLKOUT_EN, CMT2310A_DIG_CLKOUT_EN );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_06, 0, CMT2310A_DIG_CLKOUT_EN );
}
}
/******************************
**Name: vRadioSetLfxoPad
**Func: Radio enable or disable exteral 32768Hz xo connect
** when enable this functiong, GPIO2 & GPIO3 as lfxo connect pin
**Input: FALSE: disable
* TRUE: enable
*Output: None
* note: only active on GPIO2 & GPIO3, and priority high over than other function on GPIO2 & GPIO3
********************************/
void vRadioSetLfxoPad( boolean_t cfg_lfxo )
{
if( cfg_lfxo )
{
bRadioSetReg( CMT2310A_CTL_REG_07, CMT2310A_LFXO_PAD_EN, CMT2310A_LFXO_PAD_EN );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_07, 0, CMT2310A_LFXO_PAD_EN );
}
}
/******************************
**Name: vRadioSetGpio0
**Func: Radio config GPIO0
**Input: CMT2310A_GPIO0_DOUT
* CMT2310A_GPIO0_INT1
* CMT2310A_GPIO0_INT2
* CMT2310A_GPIO0_DCLK
* CMT2310A_GPIO0_INT3
*Output: None
********************************/
void vRadioSetGpio0( uint8_t gpio0_sel )
{
bRadioSetReg( CMT2310A_CTL_REG_04, gpio0_sel, CMT2310A_GPIO0_SEL );
}
/******************************
**Name: vRadioSetGpio1
**Func: Radio config GPIO1
**Input: CMT2310A_GPIO1_DCLK
* CMT2310A_GPIO1_INT1
* CMT2310A_GPIO1_INT2
* CMT2310A_GPIO1_DOUT
*Output: None
********************************/
void vRadioSetGpio1( uint8_t gpio1_sel )
{
bRadioSetReg( CMT2310A_CTL_REG_04, gpio1_sel, CMT2310A_GPIO1_SEL );
}
/******************************
**Name: vRadioSetGpio2
**Func: Radio config GPIO2
**Input: CMT2310A_GPIO2_INT1
* CMT2310A_GPIO2_INT2
* CMT2310A_GPIO2_DCLK
* CMT2310A_GPIO2_DOUT
* CMT2310A_GPIO2_INT3
*Output: None
********************************/
void vRadioSetGpio2( uint8_t gpio2_sel )
{
bRadioSetReg( CMT2310A_CTL_REG_05, gpio2_sel, CMT2310A_GPIO2_SEL );
}
/******************************
**Name: vRadioSetGpio3
**Func: Radio config GPIO3
**Input: CMT2310A_GPIO3_INT2
* CMT2310A_GPIO3_INT1
* CMT2310A_GPIO3_DCLK
* CMT2310A_GPIO3_DOUT
* CMT2310A_GPIO3_DIN
*Output: None
********************************/
void vRadioSetGpio3( uint8_t gpio3_sel )
{
bRadioSetReg( CMT2310A_CTL_REG_05, gpio3_sel, CMT2310A_GPIO3_SEL );
}
/******************************
**Name: vRadioSetGpio4
**Func: Radio config GPIO4
**Input: CMT2310A_GPIO4_DOUT
* CMT2310A_GPIO4_INT1
* CMT2310A_GPIO4_INT2
* CMT2310A_GPIO4_DCLK
* CMT2310A_GPIO4_DIN
*Output: None
********************************/
void vRadioSetGpio4( uint8_t gpio4_sel )
{
bRadioSetReg( CMT2310A_CTL_REG_06, gpio4_sel, CMT2310A_GPIO4_SEL );
}
/******************************
**Name: vRadioSetGpio5
**Func: Radio config GPIO5
**Input: CMT2310A_GPIO5_nRST
* CMT2310A_GPIO5_INT1
* CMT2310A_GPIO5_INT2
* CMT2310A_GPIO5_DOUT
* CMT2310A_GPIO5_DCLK
*Output: None
********************************/
void vRadioSetGpio5( uint8_t gpio5_sel )
{
bRadioSetReg( CMT2310A_CTL_REG_06, gpio5_sel, CMT2310A_GPIO5_SEL );
}
/******************************
**Name: vRadioSetNirq
**Func: Radio config NIRQ pin
**Input: CMT2310A_nIRQ_INT1
* CMT2310A_nIRQ_INT2
* CMT2310A_nIRQ_DCLK
* CMT2310A_nIRQ_DOUT
* CMT2310A_nIRQ_DIN
*Output: None
********************************/
void vRadioSetNirq( uint8_t nirq_sel )
{
bRadioSetReg( CMT2310A_CTL_REG_07, nirq_sel, CMT2310A_nIRQ_SEL );
}
/******************************
**Name: vRadioTcxoDrvSel
**Func: Radio set TCXO drive power, nIRQ pin
**Input: 0=strengh
3=week
*Output: None
********************************/
void vRadioTcxoDrvSel( uint8_t drv_sel )
{
vRadioRegPageSel( 1 );
switch( drv_sel & 0x03 )
{
case 0:
bRadioSetReg( CMT2310A_CMT_REG_05, ( 0 << 6 ), ( 3 << 6 ) );
break;
case 1:
bRadioSetReg( CMT2310A_CMT_REG_05, ( 1 << 6 ), ( 3 << 6 ) );
break;
case 2:
bRadioSetReg( CMT2310A_CMT_REG_05, ( 2 << 6 ), ( 3 << 6 ) );
break;
default:
bRadioSetReg( CMT2310A_CMT_REG_05, ( 3 << 6 ), ( 3 << 6 ) );
break;
}
vRadioRegPageSel( 0 );
}
//######################################################################
// Auxrl
//######################################################################
/******************************
**Name: vRadioRegPageSel
**Func: Radio register page select(page0, page1, page2)
**Input: 1: select page 1
* 0: select page 0
* 2: select page 2
*Output: None
********************************/
void vRadioRegPageSel( uint8_t page_sel )
{
page_sel &= 0x03;
switch( page_sel )
{
case 2:
bRadioSetReg( CMT2310A_PAGE_CTL_REG, CMT2310A_PAGE_2, CMT2310A_PAGE_SEL_MASK );
break;
case 1:
bRadioSetReg( CMT2310A_PAGE_CTL_REG, CMT2310A_PAGE_1, CMT2310A_PAGE_SEL_MASK );
break;
case 0:
default:
bRadioSetReg( CMT2310A_PAGE_CTL_REG, CMT2310A_PAGE_0, CMT2310A_PAGE_SEL_MASK );
break;
}
}
/******************************
**Name: vRadioPowerUpBoot
**Func: Radio power up boot start
**Input: None
*Output: None
********************************/
void vRadioPowerUpBoot( void )
{
bSpiWriteByte( CMT2310A_CTL_REG_00, CMT2310A_REBOOT );
}
/******************************
**Name: vRadioPowerUpBoot
**Func: Radio power up boot start
**Input: None
*Output: None
********************************/
void vRadioPowerUp( void )
{
gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, RESET);
delay1ms(10);
}
/******************************
**Name: vRadioSoftReset
**Func: Radio soft reset
**Input: None
*Output: None
********************************/
void vRadioSoftReset( void )
{
uint8_t i;
bRadioWriteReg( CMT2310A_SOFT_RST, 0xFF );
for( i = 0; i < 20; i++ )
delay10us( 100 );
}
/******************************
**Name: vRadioSoftReset
**Func: Radio soft reset
**Input: None
*Output: None
********************************/
void vRadioHardReset( void )
{
gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, SET);
delay10us(10);
gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, RESET);
delay1ms(10);
}
/******************************
**Name: vRadioSetPaOutputMode
**Func: Radio config PA output mode
**Input: cfg_en
* FALSE: single ended PA output mode
* TRUE: differential PA output mode
*Output: None
********************************/
void vRadioSetPaOutputMode( boolean_t cfg_en )
{
if( cfg_en )
{
bRadioSetReg( CMT2310A_CTL_REG_22, CMT2310A_PA_DIFF_SEL, CMT2310A_PA_DIFF_SEL );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_22, 0, CMT2310A_PA_DIFF_SEL );
}
}
/******************************
**Name: vRadioSetTxDataInverse
**Func: Radio config Tx Data inverse
**Input: cfg_en
* FALSE: normal
* TRUE: inverse
*Output: None
********************************/
void vRadioSetTxDataInverse( boolean_t cfg_en )
{
if( cfg_en )
{
bRadioSetReg( CMT2310A_CTL_REG_22, CMT2310A_TX_DATA_INV, CMT2310A_TX_DATA_INV );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_22, 0, CMT2310A_TX_DATA_INV );
}
}
/******************************
**Name: vRadioSetAntSwitch
**Func: Radio config GPIO0 & GPIO1 as antenna switch control
**Input: cfg_en, FALSE: disable antenna switch function
* TRUE: enable antenna switch function
*
* GPIO0 GPIO1
* cfg_polar, FALSE: RX_STATE 1 0
* TX_STATE 0 1
*
* TRUE: RX_STATE 0 1
* TX_STATE 1 0
*Output: None
* note: priority high over than other function on GPIO0 & GPIO1
********************************/
void vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar )
{
uint8_t cfg_tmp = 0;
if( cfg_en )
cfg_tmp |= CMT2310A_TRX_SWT_EN;
if( cfg_polar )
cfg_tmp |= CMT2310A_TRX_SWT_INV;
bRadioSetReg( CMT2310A_CTL_REG_22, cfg_tmp, ( CMT2310A_TRX_SWT_EN | CMT2310A_TRX_SWT_INV ) );
}
/******************************
**Name: vRadioDcdcCfg
**Func: Radio DC-DC config
**Input: cfg_en
* FALSE: normal
* TRUE: inverse
*Output: None
********************************/
void vRadioDcdcCfg( boolean_t on_off )
{
vRadioRegPageSel( 1 );
if( on_off ) //Buck_sel = 1;
{
bRadioSetReg( CMT2310A_CMT_REG_01, 0x10, 0x10 );
}
else
{
bRadioSetReg( CMT2310A_CMT_REG_01, 0x00, 0x10 );
}
vRadioRegPageSel( 0 );
}
/******************************
**Name: vRadioCapLoad
**Func: Radio Set Cap load value
**Input: cap value, range 0-31
*Output: None
********************************/
void vRadioCapLoad( uint8_t cap_value )
{
cap_value &= 0x1F;
vRadioRegPageSel( 1 );
bRadioSetReg( CMT2310A_CMT_REG_06, cap_value, 0x1F );
vRadioRegPageSel( 0 );
}
/******************************
**Name: vRadioLfoscCfg
**Func: Radio Set LFOSC
**Input: TRUE: enable
** FALSE: disable
*Output: None
********************************/
void vRadioLfoscCfg( boolean_t on_off )
{
vRadioRegPageSel( 1 );
if( on_off )
{
bRadioSetReg( CMT2310A_CMT_REG_13, 0x38, 0x38 );
}
else
{
bRadioSetReg( CMT2310A_CMT_REG_13, 0x00, 0x38 );
}
vRadioRegPageSel( 0 );
}
/******************************
**Name: vRadioXoWaitCfg
**Func: Radio Set xtal wait for pu_boot
**Input:
pu_boot(us) slp2rdy(us)
RADIO_CGU_DIV1-> 1344 584
RADIO_CGU_DIV4-> 3972 1013
RADIO_CGU_DIV8-> 6624 1586
*Output: None
********************************/
void vRadioXoWaitCfg( uint8_t div_sel )
{
div_sel &= 0x03;
div_sel <<= 6;
vRadioRegPageSel( 0 );
bRadioSetReg( CMT2310A_CTL_REG_07, div_sel, CMT2310A_CTL_REG_07_MASK );
vRadioRegPageSel( 0 );
}

89
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h Executable file
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@ -0,0 +1,89 @@
#ifndef __RADIO_HAL_H
#define __RADIO_HAL_H
//#include "stm8l15x.h"
#include "gd32w51x.h"
#include "ebyte_port.h"
//<2F><><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5>ֻ<EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
#define CM2310A_410MHZ 0
#define CM2310A_433MHZ 1
#define CM2310A_868MHZ 2
#define CM2310A_915MHZ 3
#define PRODUCT_FREQUENCY CM2310A_410MHZ//ѡ<><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5>
#include "radio_spi.h"
#include "CMT2310A_def.h"
#include "CMT2310A_reg.h"
#define RADIO_CGU_DIV1 0
#define RADIO_CGU_DIV4 1
#define RADIO_CGU_DIV8 2
#ifndef TRUE
/** Value is true (boolean_t type) */
#define TRUE ((boolean_t) 1u)
#endif
#ifndef FALSE
/** Value is false (boolean_t type) */
#define FALSE ((boolean_t) 0u)
#endif
typedef uint8_t boolean_t;
typedef uint8_t byte;
extern void vRadioGpioInit( void );
extern uint8_t bRadioReadReg( uint8_t addr );
extern uint8_t bRadioWriteReg( uint8_t addr, uint8_t reg_dat );
extern uint8_t bRadioSetReg( uint8_t addr, uint8_t set_bits, uint8_t mask_bits );
extern void vRadioLoadRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length );
extern void vRadioStoreRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length );
extern void vRadioBurstReadRegs( uint8_t* ptr_buf, uint8_t length );
extern void vRadioBurstWriteRegs( uint8_t* ptr_buf, uint8_t length );
extern void vRadioReadFifo( uint8_t* ptr_fifo, uint8_t length );
extern void vRadioWriteFifo( uint8_t* ptr_fifo, uint8_t length );
extern void vRadioReadTxFifo( uint8_t* ptr_fifo, uint8_t length );
extern void vRadioSpiModeSel( boolean_t spi_mod );
extern void vRadioSetTxDin( boolean_t cfg_din, uint8_t pin_sel );
extern void vRadioSetDigClkOut( boolean_t cfg_out );
extern void vRadioSetLfxoPad( boolean_t cfg_lfxo );
extern void vRadioSetGpio0( uint8_t gpio0_sel );
extern void vRadioSetGpio1( uint8_t gpio1_sel );
extern void vRadioSetGpio2( uint8_t gpio2_sel );
extern void vRadioSetGpio3( uint8_t gpio3_sel );
extern void vRadioSetGpio4( uint8_t gpio4_sel );
extern void vRadioSetGpio5( uint8_t gpio5_sel );
extern void vRadioSetNirq( uint8_t nirq_sel );
extern void vRadioTcxoDrvSel( uint8_t drv_sel );
extern void vRadioRegPageSel( uint8_t page_sel );
extern void vRadioPowerUp( void );
extern void vRadioPowerUpBoot( void );
extern void vRadioHardReset( void );
extern void vRadioSoftReset( void );
extern void vRadioSetPaOutputMode( boolean_t cfg_en );
extern void vRadioSetTxDataInverse( boolean_t cfg_en );
extern void vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar );
extern void vRadioDcdcCfg( boolean_t on_off );
extern void vRadioCapLoad( uint8_t cap_value );
extern void vRadioLfoscCfg( boolean_t on_off );
extern void vRadioXoWaitCfg( uint8_t div_sel );
extern void delay1ms(uint16_t cnt);
extern void delay10us(uint32_t cnt);
#endif

482
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.c Executable file
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#include "radio_mac.h"
/******************************
**Name: bRadioGetCurrentChannl
**Func: Radio get current active channl number
**Input: None
*Output: channl number
********************************/
uint8_t bRadioGetCurrentChannl( void )
{
return( bRadioReadReg( CMT2310A_FREQ_CHANL_ACT_REG ) );
}
/******************************
**Name: vRadioSetTxSeqNumber
**Func: Radio set transmit sequence number
**Input: transmit init sequence number
*Output: None
********************************/
void vRadioSetTxSeqNumberInitValue( FRAME_CFG* frm_cfg )
{
bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_L_REG, ( uint8_t )( ( *frm_cfg ).SEQNUM_TX_IN ) );
bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_H_REG, ( uint8_t )( ( ( *frm_cfg ).SEQNUM_TX_IN ) >> 8 ) );
}
/******************************
**Name: wRadioGetTxSeqNumber
**Func: Radio get current transmit sequence number
**Input: None
*Output: current transmit sequence number
********************************/
uint16_t wRadioGetTxSeqNumberCurrent( FRAME_CFG* frm_cfg )
{
uint16_t seq_num = 0;
seq_num = bRadioReadReg( CMT2310A_SEQNUM_TX_OUT_H_REG );
seq_num <<= 8;
seq_num |= bRadioReadReg( CMT2310A_SEQNUM_TX_OUT_L_REG );
( *frm_cfg ).SEQNUM_TX_CURRENT_OUT = seq_num;
return( ( *frm_cfg ).SEQNUM_TX_CURRENT_OUT = seq_num );
}
/******************************
**Name: vRadioSetTxFCS2
**Func: Radio set transmit packet FCS2 value
**Input: transmit FCS2
*Output: None
********************************/
void vRadioSetTxFCS2( FRAME_CFG* frm_cfg )
{
bRadioWriteReg( CMT2310A_FCS2_TX_IN_REG, ( *frm_cfg ).FCS2_TX_IN );
}
/******************************
**Name: vRadioGetRxFCS2
**Func: Radio get receive packet FCS2 value
**Input: None
*Output: receive FCS2
********************************/
uint8_t bRadioGetRxFCS2( FRAME_CFG* frm_cfg )
{
( *frm_cfg ).FCS2_RX_OUT = bRadioReadReg( CMT2310A_FCS2_RX_OUT_REG );
return( ( *frm_cfg ).FCS2_RX_OUT );
}
/******************************
**Name: vRadioSetPayloadLength
**Func: Radio config payload length
**Input: length
*Output: None
********************************/
void vRadioSetPayloadLength( FRAME_CFG* frm_cfg )
{
uint16_t len;
if( ( *frm_cfg ).PAYLOAD_LENGTH != 0 )
{
len = ( *frm_cfg ).PAYLOAD_LENGTH - 1;
bRadioWriteReg( CMT2310A_PAYLOAD_LENGTH_L_REG, ( byte )len );
bRadioWriteReg( CMT2310A_PAYLOAD_LENGTH_H_REG, ( byte )( len >> 8 ) );
}
}
/******************************
**Name: wRadioGetPayloadLength
**Func: Radio get payload length
**Input: None
*Output: payload length
********************************/
uint16_t vRadioGetPayloadLength( FRAME_CFG* frm_cfg )
{
uint16_t length = 0;
length = bRadioReadReg( CMT2310A_PAYLOAD_LENGTH_H_REG );
length <<= 8;
length |= bRadioReadReg( CMT2310A_PAYLOAD_LENGTH_L_REG );
( *frm_cfg ).PAYLOAD_LENGTH = length + 1;
return( length );
}
//######################################################################
// Packet config
//######################################################################
/******************************
**Name: vRadioCfgPreamble
**Func: Radio config preamble
**Input: preamble struct
*Output: None
********************************/
void vRadioCfgPreamble( PREAMBLE_CFG* prm_ptr )
{
uint8_t cfg_tmp;
cfg_tmp = bRadioReadReg( CMT2310A_CTL_REG_40 );
if( ( *prm_ptr ).PREAM_LENG_UNIT == 0 )
{
cfg_tmp &= ( ~CMT2310A_PREAM_LENG_UNIIT );
}
else
{
cfg_tmp |= CMT2310A_PREAM_LENG_UNIIT;
}
cfg_tmp &= ( ~CMT2310A_RX_PREAM_SIZE_MASK );
cfg_tmp |= ( ( ( ( *prm_ptr ).RX_PREAM_SIZE ) << 3 )&CMT2310A_RX_PREAM_SIZE_MASK );
bRadioWriteReg( CMT2310A_CTL_REG_40, cfg_tmp );
bRadioWriteReg( CMT2310A_CTL_REG_41, ( uint8_t )( ( *prm_ptr ).TX_PREAM_SIZE ) );
bRadioWriteReg( CMT2310A_CTL_REG_42, ( uint8_t )( ( *prm_ptr ).TX_PREAM_SIZE >> 8 ) );
bRadioWriteReg( CMT2310A_CTL_REG_43, ( *prm_ptr ).PREAM_VALUE );
}
/******************************
**Name: vRadioCfgSyncWord
**Func: Radio config sync word
**Input: sync word struct
*Output: None
********************************/
void vRadioCfgSyncWord( SYNC_CFG* sync_ptr )
{
uint8_t i;
uint8_t adr;
bRadioWriteReg( CMT2310A_CTL_REG_44, ( *sync_ptr ).SYN_CFG_u.SYNC_CFG_REG );
for( i = 0, adr = CMT2310A_CTL_REG_52; i < 8; i++, adr-- )
{
bRadioWriteReg( adr, ( *sync_ptr ).SYNC_VALUE[i] );
bRadioWriteReg( ( adr + 8 ), ( *sync_ptr ).SYNC_FEC_VALUE[i] );
}
if( ( *sync_ptr ).SYNC_VALUE_SEL == 0 )
{
bRadioSetReg( CMT2310A_CTL_REG_64, 0, CMT2310A_SYNC_VALUE_SEL );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_64, CMT2310A_SYNC_VALUE_SEL, CMT2310A_SYNC_VALUE_SEL );
}
}
/******************************
**Name: vRadioCfgNodeAddr
**Func: Radio config node address
**Input: node address struct
*Output: None
********************************/
void vRadioCfgNodeAddr( ADDR_CFG* node_addr_ptr )
{
uint8_t cfg_tmp;
cfg_tmp = bRadioReadReg( CMT2310A_CTL_REG_64 );
cfg_tmp &= 0x80;
cfg_tmp |= ( ( *node_addr_ptr ).ADDR_CFG_u.ADDR_CFG_REG & 0x7F );
bRadioWriteReg( CMT2310A_CTL_REG_64, cfg_tmp );
bRadioWriteReg( CMT2310A_SRC_ADDR_L_REG, ( *node_addr_ptr ).SRC_ADDR[0] );
bRadioWriteReg( CMT2310A_SRC_ADDR_H_REG, ( *node_addr_ptr ).SRC_ADDR[1] );
bRadioWriteReg( CMT2310A_DEST_ADDR_L_REG, ( *node_addr_ptr ).DEST_ADDR[0] );
bRadioWriteReg( CMT2310A_DEST_ADDR_H_REG, ( *node_addr_ptr ).DEST_ADDR[1] );
bRadioWriteReg( CMT2310A_SRC_BITMASK_L_REG, ( *node_addr_ptr ).SRC_BITMASK[0] );
bRadioWriteReg( CMT2310A_SRC_BITMASK_H_REG, ( *node_addr_ptr ).SRC_BITMASK[1] );
bRadioWriteReg( CMT2310A_DEST_BITMASK_L_REG, ( *node_addr_ptr ).DEST_BITMASK[0] );
bRadioWriteReg( CMT2310A_DEST_BITMASK_H_REG, ( *node_addr_ptr ).DEST_BITMASK[1] );
}
/******************************
**Name: vRadioCfgCrc
**Func: Radio config crc
**Input: crc struct
*Output: None
********************************/
void vRadioCfgCrc( CRC_CFG* crc_ptr )
{
uint8_t i, adr;
bRadioWriteReg( CMT2310A_CTL_REG_73, ( uint8_t )( ( *crc_ptr ).CRC_CFG_u.CRC_CFG_REG ) );
for( i = 0, adr = CMT2310A_CTL_REG_74; i < 4; i++, adr++ )
{
bRadioWriteReg( adr, ( *crc_ptr ).CRC_SEED_u.u8_SEED[i] );
bRadioWriteReg( ( adr + 4 ), ( *crc_ptr ).CRC_POLY_u.u8_POLY[i] );
}
if( ( *crc_ptr ).CRC_CFG_u._BITS.CRC_REFOUT )
{
bRadioSetReg( CMT2310A_CTL_REG_82, CMT2310A_CRC_REFOUT, CMT2310A_CRC_REFOUT );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_82, 0, CMT2310A_CRC_REFOUT );
}
if( ( *crc_ptr ).CRC_CFG_u._BITS.CRCERR_CLR_FIFO_EN )
{
bRadioSetReg( CMT2310A_CTL_REG_84, CMT2310A_CRCERR_CLR_FIFO_EN, CMT2310A_CRCERR_CLR_FIFO_EN );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_84, 0, CMT2310A_CRCERR_CLR_FIFO_EN );
}
}
/******************************
**Name: vRadioCfgCodeFormat
**Func: Radio config code format
**Input: code format struct
*Output: None
********************************/
void vRadioCfgCodeFormat( CODING_FORMAT_CFG* code_format_ptr )
{
uint8_t cfg_tmp;
cfg_tmp = bRadioReadReg( CMT2310A_CTL_REG_82 );
cfg_tmp &= 0x80;
cfg_tmp |= ( ( *code_format_ptr ).CODING_FORMAT_CFG_u.CODING_CFG_REG & 0x3F );
if( ( *code_format_ptr ).WHITEN_SEED & 0x0100 )
{
cfg_tmp |= CMT2310A_WHITEN_SEED_B8;
}
bRadioWriteReg( CMT2310A_CTL_REG_82, cfg_tmp );
bRadioWriteReg( CMT2310A_CTL_REG_83, ( uint8_t )( ( *code_format_ptr ).WHITEN_SEED ) );
cfg_tmp = ( ( *code_format_ptr ).CODING_FORMAT_CFG_u.CODING_CFG_REG >> 8 );
cfg_tmp &= ( ~CMT2310A_FEC_PAD_CODE_H_MASK );
cfg_tmp |= ( ( uint8_t )( ( ( *code_format_ptr ).FEC_PAD_CODE ) >> 6 )&CMT2310A_FEC_PAD_CODE_H_MASK );
bRadioWriteReg( CMT2310A_CTL_REG_93, cfg_tmp );
bRadioWriteReg( CMT2310A_CTL_REG_94, ( uint8_t )( ( *code_format_ptr ).FEC_PAD_CODE ) );
}
/******************************
**Name: vRadioCfgFrameFormat
**Func: Radio config frame format
**Input: frame format struct
*Output: None
********************************/
void vRadioCfgFrameFormat( FRAME_CFG* frame_format_ptr )
{
uint8_t cfg_tmp;
bRadioSetReg( CMT2310A_CTL_REG_40, ( *frame_format_ptr ).DATA_MODE, CMT2310A_DATA_MODE_MASK );
bRadioWriteReg( CMT2310A_CTL_REG_63, ( *frame_format_ptr ).FRAME_CFG1_u.FRAME_CFG1_REG );
cfg_tmp = bRadioReadReg( CMT2310A_CTL_REG_84 );
cfg_tmp &= 0x80;
cfg_tmp |= ( ( *frame_format_ptr ).FRAME_CFG2_u.FRAME_CFG2_REG & 0x7F );
bRadioWriteReg( CMT2310A_CTL_REG_84, cfg_tmp );
bRadioWriteReg( CMT2310A_TX_PKT_NUM_L_REG, ( uint8_t )( *frame_format_ptr ).TX_PKT_NUM );
bRadioWriteReg( CMT2310A_TX_PKT_NUM_H_REG, ( uint8_t )( ( *frame_format_ptr ).TX_PKT_NUM >> 8 ) );
bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_L_REG, ( uint8_t )( *frame_format_ptr ).SEQNUM_TX_IN );
bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_H_REG, ( uint8_t )( ( *frame_format_ptr ).SEQNUM_TX_IN >> 8 ) );
bRadioWriteReg( CMT2310A_TX_PKT_GAP_REG, ( *frame_format_ptr ).TX_PKT_GAP );
bRadioWriteReg( CMT2310A_FCS2_TX_IN_REG, ( *frame_format_ptr ).FCS2_TX_IN );
bRadioWriteReg( CMT2310A_FCS2_RX_OUT_REG, ( *frame_format_ptr ).FCS2_RX_OUT );
}
/******************************
**Name: vRadioCfgFrameFormat
**Func: Radio config frame format
**Input: frame format struct
*Output: None
********************************/
void vRadioCfgWiSunFormat( WI_SUN_CFG* wi_sun_ptr )
{
bRadioWriteReg( CMT2310A_CTL_REG_111, ( *wi_sun_ptr ).WI_SUN_REG );
}
/******************************
**Name: vRadioCdrTracingModeCfg
**Func: Radio config cdr tracing config
**Input: cdr tracing
*Output: None
********************************/
void vRadioCdrTracingModeCfg( CDR_TRACING_CFG* cdr_ptr )
{
vRadioRegPageSel( 1 );
bRadioWriteReg( CMT2310A_RX_CDR_REG_00, ( *cdr_ptr ).CDR_CFG0_u.CDR_CFG0_REG );
( *cdr_ptr ).CDR_CFG1_u.CDR_CFG1_REG &= 0xF8;
( *cdr_ptr ).CDR_CFG1_u.CDR_CFG1_REG |= ( ( uint8_t )( ( *cdr_ptr ).CDR_BR_TH >> 16 ) & 0x07 );
bRadioSetReg( CMT2310A_RX_CDR_REG_03, ( *cdr_ptr ).CDR_CFG1_u.CDR_CFG1_REG, 0x1F );
bRadioWriteReg( CMT2310A_RX_CDR_REG_01, ( uint8_t )( *cdr_ptr ).CDR_BR_TH );
bRadioWriteReg( CMT2310A_RX_CDR_REG_02, ( uint8_t )( ( *cdr_ptr ).CDR_BR_TH >> 8 ) );
vRadioRegPageSel( 0 );
}
//######################################################################
// System control
//######################################################################
void vRadioCfgWorkMode( WORK_MODE_CFG* run_mode_ptr )
{
bRadioWriteReg( CMT2310A_CTL_REG_03, ( *run_mode_ptr ).FREQ_CHANL_NANU );
bRadioWriteReg( CMT2310A_CTL_REG_12, ( *run_mode_ptr ).FREQ_SPACE );
bRadioWriteReg( CMT2310A_CTL_REG_13, ( *run_mode_ptr ).FREQ_TIMES );
bRadioWriteReg( CMT2310A_CTL_REG_96, ( *run_mode_ptr ).WORK_MODE_CFG1_u.WORK_MODE_CFG1_REG );
bRadioWriteReg( CMT2310A_CTL_REG_97, ( *run_mode_ptr ).WORK_MODE_CFG2_u.WORK_MODE_CFG2_REG );
bRadioWriteReg( CMT2310A_CTL_REG_98, ( *run_mode_ptr ).WORK_MODE_CFG3_u.WORK_MODE_CFG3_REG );
bRadioWriteReg( CMT2310A_CTL_REG_105, ( *run_mode_ptr ).WORK_MODE_CFG4_u.WORK_MODE_CFG4_REG );
bRadioWriteReg( CMT2310A_CTL_REG_106, ( *run_mode_ptr ).WORK_MODE_CFG5_u.WORK_MODE_CFG5_REG );
bRadioSetReg( CMT2310A_CTL_REG_22, ( *run_mode_ptr ).WORK_MODE_CFG6_u.WORK_MODE_CFG6_REG, 0xC0 );
bRadioWriteReg( CMT2310A_CTL_REG_99, ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_M ) );
bRadioWriteReg( CMT2310A_CTL_REG_100, ( ( ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).SLEEP_TIMER_R & 0x1F ) );
bRadioWriteReg( CMT2310A_CTL_REG_101, ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T1_M ) );
bRadioWriteReg( CMT2310A_CTL_REG_102, ( ( ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T1_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).RX_TIMER_T1_R & 0x1F ) );
bRadioWriteReg( CMT2310A_CTL_REG_103, ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T2_M ) );
bRadioWriteReg( CMT2310A_CTL_REG_104, ( ( ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T2_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).RX_TIMER_T2_R & 0x1F ) );
bRadioWriteReg( CMT2310A_CTL_REG_107, ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_CSMA_M ) );
bRadioWriteReg( CMT2310A_CTL_REG_108, ( ( ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_CSMA_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).RX_TIMER_CSMA_R & 0x1F ) );
bRadioWriteReg( CMT2310A_CTL_REG_110, ( *run_mode_ptr ).TX_DC_TIMES );
bRadioWriteReg( CMT2310A_CTL_REG_113, ( *run_mode_ptr ).TX_RS_TIMES );
bRadioWriteReg( CMT2310A_CTL_REG_115, ( *run_mode_ptr ).CSMA_TIMES );
bRadioWriteReg( CMT2310A_CTL_REG_118, ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_CSMA_M ) );
bRadioWriteReg( CMT2310A_CTL_REG_119, ( ( ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_CSMA_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).SLEEP_TIMER_CSMA_R & 0x1F ) );
}
void vRadioReadRunModeCfg( void )
{
bRadioReadReg( CMT2310A_CTL_REG_11 );
bRadioReadReg( CMT2310A_CTL_REG_12 );
bRadioReadReg( CMT2310A_CTL_REG_13 );
bRadioReadReg( CMT2310A_CTL_REG_96 );
bRadioReadReg( CMT2310A_CTL_REG_97 );
bRadioReadReg( CMT2310A_CTL_REG_98 );
bRadioReadReg( CMT2310A_CTL_REG_105 );
bRadioReadReg( CMT2310A_CTL_REG_106 );
bRadioReadReg( CMT2310A_CTL_REG_99 );
bRadioReadReg( CMT2310A_CTL_REG_100 );
bRadioReadReg( CMT2310A_CTL_REG_101 );
bRadioReadReg( CMT2310A_CTL_REG_102 );
bRadioReadReg( CMT2310A_CTL_REG_103 );
bRadioReadReg( CMT2310A_CTL_REG_104 );
bRadioReadReg( CMT2310A_CTL_REG_107 );
bRadioReadReg( CMT2310A_CTL_REG_108 );
bRadioReadReg( CMT2310A_CTL_REG_110 );
bRadioReadReg( CMT2310A_CTL_REG_113 );
bRadioReadReg( CMT2310A_CTL_REG_115 );
bRadioReadReg( CMT2310A_CTL_REG_118 );
bRadioReadReg( CMT2310A_CTL_REG_119 );
}
uint8_t bRadioGetTxDutyCycleDoneTimes( WORK_MODE_CFG* run_mode_ptr )
{
( *run_mode_ptr ).TX_DC_DONE_TIMES = bRadioReadReg( CMT2310A_CTL_REG_112 );
return( ( *run_mode_ptr ).TX_DC_DONE_TIMES );
}
uint8_t bRadioGetTxResendDoneTimes( WORK_MODE_CFG* run_mode_ptr )
{
( *run_mode_ptr ).TX_RS_DONE_TIMES = bRadioReadReg( CMT2310A_CTL_REG_114 );
return( ( *run_mode_ptr ).TX_RS_DONE_TIMES );
}
uint8_t bRadioGetCMSADoneTimes( WORK_MODE_CFG* run_mode_ptr )
{
( *run_mode_ptr ).CSMA_DONE_TIMES = bRadioReadReg( CMT2310A_CTL_REG_116 );
return( ( *run_mode_ptr ).CSMA_DONE_TIMES );
}
void vRadioSendWithAck( boolean_t w_ack, FRAME_CFG* frame_format_ptr )
{
uint8_t tmp;
tmp = bRadioReadReg( CMT2310A_FCS2_TX_IN_REG );
if( w_ack )
{
( *frame_format_ptr ).FCS2_TX_IN = tmp | 0x80;
}
else
{
( ( *frame_format_ptr ) ).FCS2_TX_IN = tmp & 0x7F;
}
bRadioWriteReg( CMT2310A_FCS2_TX_IN_REG, ( ( *frame_format_ptr ) ).FCS2_TX_IN );
}
void vRadioEnableTxAck( boolean_t en_flg, WORK_MODE_CFG* run_mode_ptr )
{
if( en_flg )
{
( *run_mode_ptr ).WORK_MODE_CFG1_u._BITS.TX_ACK_EN = 1; //enable TX_ACK
( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 1;
}
else
{
( *run_mode_ptr ).WORK_MODE_CFG1_u._BITS.TX_ACK_EN = 0; //disable TX_ACK
( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0;
}
vRadioCfgWorkMode( run_mode_ptr );
}
void vRadioEnableRxAck( boolean_t en_flg, WORK_MODE_CFG* run_mode_ptr )
{
if( en_flg )
{
( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 1; //enable RX_ACK
}
else
{
( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 0; //disable RX_ACK
}
vRadioCfgWorkMode( run_mode_ptr );
}
uint8_t bRadioGetFreqChanl( void )
{
return( bRadioReadReg( CMT2310A_FREQ_CHANL_ACT_REG ) );
}
uint8_t bRadioGetHopDoneTimes( void )
{
return( bRadioReadReg( CMT2310A_CTL_REG_11 ) );
}
void vRadioCsmaEnable( boolean_t on_off, WORK_MODE_CFG* run_mode_ptr )
{
if( on_off )
{
( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 1;
if( ( *run_mode_ptr ).CSMA_TIMES != 0 )
{
( *run_mode_ptr ).WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 1;
}
( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.CSMA_EN = 1;
}
else
{
( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0;
( *run_mode_ptr ).WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 0;
( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.CSMA_EN = 0;
}
vRadioCfgWorkMode( run_mode_ptr );
}
void vRadioSetRssiAbsThValue( int8_t rssi )
{
vRadioRegPageSel( 1 );
bRadioWriteReg( CMT2310A_RSSI_ABS_TH_REG, ( uint8_t )rssi );
vRadioRegPageSel( 0 );
}
void vRadioSetPjdDetWin( uint8_t pjd_win ) //0:4-jump, 1:6-jump, 2:8-jump, 3:10-jump
{
pjd_win &= 0x03;
pjd_win <<= 4;
vRadioRegPageSel( 1 ); //CMT2310A_RX_2FSK_REG_01 is in bank1
bRadioSetReg( CMT2310A_RX_2FSK_REG_01, pjd_win, 0x30 );
vRadioRegPageSel( 0 );
}
//
//void vRadioSetFreq(const byte *ptr)
//{
// byte i;
// byte adr;
// vRadioRegPageSel(1);
// adr = CMT2310A_TX_FREQ_REG_00;
// for(i=0; i<4; i++)
// bSpiWriteByte(adr++, ptr[i]);
//
// adr = CMT2310A_RX_FREQ_REG_01;
// for( ; i<8; i++)
// bSpiWriteByte(adr++, ptr[i]);
// vRadioRegPageSel(0);
//}
//

49
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.h Executable file
View File

@ -0,0 +1,49 @@
#ifndef __RADIO_MAC_H
#define __RADIO_MAC_H
#include "radio_hal.h"
#include "CMT2310A_def.h"
#include "CMT2310A_reg.h"
extern uint8_t bRadioGetCurrentChannl(void);
extern void vRadioSetTxSeqNumberInitValue(FRAME_CFG *frm_cfg);
extern uint16_t wRadioGetTxSeqNumberCurrent(FRAME_CFG *frm_cfg);
extern void vRadioSetTxFCS2(FRAME_CFG *frm_cfg);
extern uint8_t bRadioGetRxFCS2(FRAME_CFG *frm_cfg);
extern void vRadioSetPayloadLength(FRAME_CFG *frm_cfg);
extern uint16_t vRadioGetPayloadLength(FRAME_CFG *frm_cfg);
extern void vRadioCfgPreamble(PREAMBLE_CFG *prm_ptr);
extern void vRadioCfgSyncWord(SYNC_CFG *sync_ptr);
extern void vRadioCfgNodeAddr(ADDR_CFG *node_addr_ptr);
extern void vRadioCfgCrc(CRC_CFG *crc_ptr);
extern void vRadioCfgCodeFormat(CODING_FORMAT_CFG *code_format_ptr);
extern void vRadioCfgFrameFormat(FRAME_CFG *frame_format_ptr);
extern void vRadioCfgWiSunFormat(WI_SUN_CFG *wi_sun_ptr);
extern void vRadioCdrTracingModeCfg(CDR_TRACING_CFG *cdr_ptr);
extern void vRadioCfgWorkMode(WORK_MODE_CFG *run_mode_ptr);
extern void vRadioReadRunModeCfg(void);
extern uint8_t bRadioGetTxDutyCycleDoneTimes(WORK_MODE_CFG *run_mode_ptr);
extern uint8_t bRadioGetTxResendDoneTimes(WORK_MODE_CFG *run_mode_ptr);
extern uint8_t bRadioGetCMSADoneTimes(WORK_MODE_CFG *run_mode_ptr);
extern void vRadioSendWithAck(boolean_t w_ack, FRAME_CFG *frame_format_ptr);
extern void vRadioEnableTxAck(boolean_t en_flg, WORK_MODE_CFG *run_mode_ptr);
extern void vRadioEnableRxAck(boolean_t en_flg, WORK_MODE_CFG *run_mode_ptr);
extern uint8_t bRadioGetFreqChanl(void);
extern uint8_t bRadioGetHopDoneTimes(void);
extern void vRadioCsmaEnable(boolean_t on_off, WORK_MODE_CFG *run_mode_ptr);
extern void vRadioSetRssiAbsThValue(int8_t rssi);
extern void vRadioSetPjdDetWin(uint8_t pjd_win);
#endif

645
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.c Executable file
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@ -0,0 +1,645 @@
#include "radio_phy.h"
/******************************
**Name: vRadioSetInterruptSel
**Func: Radio config INT1 & INT2 pin seleciton
**Input: int1_sel, int2_sel,
**
** CMT2310A_INT_MIX (0<<0) // all interrupt mixed together
** CMT2310A_INT_ANT_LOCK (1<<0) // antenna locked
** CMT2310A_INT_RSSI_PJD_VALID (2<<0) // rssi and/or pjd valid
** CMT2310A_INT_PREAM_PASS (3<<0) // preamble detected
** CMT2310A_INT_SYNC_PASS (4<<0) // sync word detected
** CMT2310A_INT_ADDR_PASS (5<<0) // node address detected
** CMT2310A_INT_CRC_PASS (6<<0) // crc ok detected
** CMT2310A_INT_PKT_OK (7<<0) // packet received detected
** CMT2310A_INT_PKT_DONE (8<<0) // packet received detected, even wrong packet or collision
** CMT2310A_INT_SLEEP_TMO (9<<0) // sleep timer time-out
** CMT2310A_INT_RX_TMO (10<<0) // rx timer time-out
** CMT2310A_INT_RX_FIFO_NMTY (11<<0) // rx fifo non-empty
** CMT2310A_INT_RX_FIFO_TH (12<<0) // rx fifo threshold
** CMT2310A_INT_RX_FIFO_FULL (13<<0) // rx fifo full
** CMT2310A_INT_RX_FIFO_WBYTE (14<<0) // rx fifo write byte trigger
** CMT2310A_INT_RX_FIFO_OVF (15<<0) // rx fifo overflow
** CMT2310A_INT_TX_DONE (16<<0) // tx done
** CMT2310A_INT_TX_FIFO_NMTY (17<<0) // tx fifo non-empty
** CMT2310A_INT_TX_FIFO_TH (18<<0) // tx fifo threshold
** CMT2310A_INT_TX_FIFO_FULL (19<<0) // tx fifo full
** CMT2310A_INT_STATE_IS_READY (20<<0) // state is ready
** CMT2310A_INT_STATE_IS_FS (21<<0) // state is FS
** CMT2310A_INT_STATE_IS_RX (22<<0) // state is rx
** CMT2310A_INT_STATE_IS_TX (23<<0) // state is tx
** CMT2310A_INT_LBD_STATUS (24<<0) // LBD status
** CMT2310A_INT_API_CMD_FAILED (25<<0) // API Command failed
** CMT2310A_INT_API_DONE (26<<0) // API execute finish
** CMT2310A_INT_TX_DC_DONE (27<<0) // ??
** CMT2310A_INT_ACK_RECV_FAILED (28<<0) // ack recieve failed
** CMT2310A_INT_TX_RESEND_DONE (29<<0) // tx re-send done
** CMT2310A_INT_NACK_RECV (30<<0) // non-ack received
** CMT2310A_INT_SEQ_MATCH (31<<0) // sequence number match
** CMT2310A_INT_CSMA_DONE (32<<0) // CSMA done
** CMT2310A_INT_CCA_STATUS (33<<0) // CCA status match
**
*Output: None
********************************/
void vRadioSetInt1Sel( uint8_t int1_sel )
{
bRadioSetReg( CMT2310A_INT1_SEL_REG, int1_sel, CMT2310A_INT1_SEL_MASK );
}
void vRadioSetInt2Sel( uint8_t int2_sel )
{
bRadioSetReg( CMT2310A_INT2_SEL_REG, int2_sel, CMT2310A_INT2_SEL_MASK );
}
/******************************
**Name: vRadioSetInterruptPolar
**Func: Radio config INT pin out polar mode
**Input: int1_polar, FALSE: ative-high, normal-low
* TRUE: ative-low, normal-high
* int2_polar, FALSE: ative-high, normal-low
* TRUE: ative-low, normal-high
* int3_polar, FALSE: ative-high, normal-low
* TRUE: ative-low, normal-high
*Output: None
********************************/
void vRadioSetInt1Polar( boolean_t int1_polar )
{
if( int1_polar )
{
bRadioSetReg( CMT2310A_CTL_REG_17, CMT2310A_INT1_POLAR, CMT2310A_INT1_POLAR );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_17, 0, CMT2310A_INT1_POLAR );
}
}
void vRadioSetInt2Polar( boolean_t int2_polar )
{
if( int2_polar )
{
bRadioSetReg( CMT2310A_CTL_REG_17, CMT2310A_INT2_POLAR, CMT2310A_INT2_POLAR );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_17, 0, CMT2310A_INT2_POLAR );
}
}
void vRadioSetInt3Polar( boolean_t int3_polar )
{
if( int3_polar )
{
bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_INT3_POLAR, CMT2310A_INT3_POLAR );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_INT3_POLAR );
}
}
//######################################################################
// RSSI
//######################################################################
/******************************
**Name: vRadioRssiUpdateSel
**Func: Radio rssi update select
**Input: CMT2310A_RSSI_UPDATE_ALWAYS ---- always
** CMT2310A_RSSI_UPDATE_PREAM_OK ---- when preamble ok
** CMT2310A_RSSI_UPDATE_SYNC_OK ---- when sync ok
** CMT2310A_RSSI_UPDATE_PKT_DONE ---- when pkt done
*Output: None
********************************/
void vRadioRssiUpdateSel( uint8_t sel )
{
vRadioRegPageSel( 1 ); //CMT2310A_RX_RSSI_REG_00 is in page1
bRadioSetReg( CMT2310A_RX_RSSI_REG_00, sel, CMT2310A_RSSI_UPDATE_SEL_MASK );
vRadioRegPageSel( 0 );
}
/******************************
**Name: bRadioGetRssi
**Func: Radio get rssi value
**Input: None
*Output: rssi with sign
********************************/
uint8_t bRadioGetRssi( void )
{
return( bRadioReadReg( CMT2310A_CTL_REG_34 ) );
}
/******************************
**Name: vRadioRssiConfig
**Func: Radio config Rssi
**Input: None
*Output: None
********************************/
void vRadioRssiConfig( RSSI_CFG rssi_cfg )
{
vRadioRegPageSel( 1 );
bRadioSetReg( CMT2310A_RX_RSSI_REG_00, rssi_cfg.FRAME_CFG1_u.RSSI_CFG_REG, ( CMT2310A_COLL_STEP_SEL_MASK | CMT2310A_RSSI_UPDATE_SEL_MASK | CMT2310A_COLL_DET_EN ) );
bRadioWriteReg( CMT2310A_RSSI_ABS_TH_REG, rssi_cfg.RSSI_ABS_TH );
vRadioRegPageSel( 0 );
}
/******************************
**Name: vRadioRssiCalOffset
**Func: Radio config Rssi calibrate offset
**Input: None
*Output: None
********************************/
void vRadioRssiCalOffset( uint8_t cal_offset )
{
vRadioRegPageSel( 0 );
bRadioWriteReg( CMT2310A_RSSI_CAL_OFFSET_REG, cal_offset );
}
//######################################################################
// Misc
//######################################################################
/******************************
**Name: bRadioGetLbdValue
**Func: Radio get LBD value
**Input: None
*Output: LBD value
********************************/
uint8_t bRadioGetLbdValue( void )
{
return( bRadioReadReg( CMT2310A_LBD_REG ) );
}
/******************************
**Name: vRadioSetLbdTH
**Func: Radio get LBD threshold value
**Input: LBD threshold value
*Output: None
********************************/
void vRadioSetLbdTH( uint8_t lbd_th )
{
bRadioWriteReg( CMT2310A_LBD_TH_REG, lbd_th );
}
/******************************
**Name: bRadioGetTemperature
**Func: Radio get Temperature value
**Input: None
*Output:
********************************/
uint8_t bRadioGetTemperature( void )
{
return( bRadioReadReg( CMT2310A_TEMP_REG ) );
}
/******************************
**Name: bRadioApiCommand
**Func: Radio get Temperature value
**Input: api_cmd, API command code
*Output:
* note: only support 0x01 command code
********************************/
boolean_t bRadioApiCommand( uint8_t api_cmd )
{
uint16_t i;
bRadioWriteReg( CMT2310A_API_CMD_REG, api_cmd );
api_cmd |= CMT2310A_API_CMD_FLAG;
for( i = 0; i < 500; i++ )
{
delay1ms( 2 );
if( bRadioReadReg( CMT2310A_CTL_REG_09 ) == api_cmd )
{
return( TRUE );
}
}
return( FALSE );
}
/******************************
**Name: vRadioCdrModeCfg
**Func: Radio set CDR mode
**Input: enum CDR_MODE
*Output:
********************************/
void vRadioCdrModeCfg( enum CDR_MODE cdr_mode )
{
vRadioRegPageSel( 1 );
bRadioSetReg( CMT2310A_RX_CDR_REG_00, cdr_mode, 0x03 );
vRadioRegPageSel( 0 );
}
/******************************
**Name: vRadioTxRampCfg
**Func: Radio set tx ramp
**Input:
** tx_ramp_en: TRUE = enable; FALSE = disable
** tx_ramp_step: ramp value, about 1.9us/step
*Output:
********************************/
void vRadioTxRampCfg( boolean_t tx_ramp_en, uint16_t tx_ramp_step )
{
vRadioRegPageSel( 1 );
if( tx_ramp_en )
{
bRadioSetReg( CMT2310A_TX_MODE_REG_00, ( 1 << 2 ), ( 1 << 2 ) );
bRadioWriteReg( CMT2310A_TX_PWR_REG_03, ( uint8_t )tx_ramp_step );
bRadioSetReg( CMT2310A_TX_PWR_REG_05, ( uint8_t )( ( tx_ramp_step >> 4 ) & 0xF0 ), 0xF0 );
}
else
{
bRadioSetReg( CMT2310A_TX_MODE_REG_00, ( 0 << 2 ), ( 1 << 2 ) );
}
vRadioRegPageSel( 0 );
}
/******************************
**Name: vRadioTxGaussianCfg
**Func: Radio set tx with Gaussian
**Input:
** tx_gaus_en: TRUE = enable; FALSE = disable
** tx_gaus_bt: 0=0.3, 1=0.5, 2=0.8, 3=1.0
*Output:
********************************/
void vRadioTxGaussianCfg( boolean_t tx_gaus_en, uint8_t tx_gaus_bt )
{
uint8_t tmp = 0;
tmp = ( tx_gaus_bt & 0x03 );
tmp <<= 5;
if( tx_gaus_en )
{
tmp |= 0x10;
}
vRadioRegPageSel( 1 );
bRadioSetReg( CMT2310A_TX_MODE_REG_00, tmp, 0x70 );
vRadioRegPageSel( 0 );
}
/******************************
**Name: vRadioAfcCfg
**Func: Radio set afc
**Input:
** afc_en: TRUE = enable; FALSE = disable
*Output:
********************************/
void vRadioAfcCfg( boolean_t afc_en )
{
vRadioRegPageSel( 1 );
if( afc_en )
{
bRadioSetReg( CMT2310A_RX_AFC_REG_00, 0x01, 0x01 );
}
else
{
bRadioSetReg( CMT2310A_RX_AFC_REG_00, 0x00, 0x01 );
}
vRadioRegPageSel( 0 );
}
//######################################################################
// Work State
//######################################################################
/******************************
**Name: bRadioGetState
**Func: Radio state
**Input: None
*Output: Radio State
* CMT2310A_STATE_IS_IDLE | CMT2310A_STATE_IS_SLEEP | CMT2310A_STATE_IS_READY | CMT2310A_STATE_IS_RFS | CMT2310A_STATE_IS_TFS | CMT2310A_STATE_IS_RX | CMT2310A_STATE_IS_TX
* note: page0
********************************/
uint8_t bRadioGetState( void )
{
return( bRadioReadReg( CMT2310A_CHIP_MODE_STA_REG ) );
}
uint8_t bRadioSwitchWaiting( uint8_t targ_state )
{
uint8_t i = 0;
do
{
delay10us( 2 ); //Լ26us<75><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPI<50><49><EFBFBD><EFBFBD>Լ8us<75><73><EFBFBD>ϼ<EFBFBD>33us<75><73>ѯһ<D1AF><D2BB>
if( bRadioGetState() == targ_state )
{
break;
}
i++;
}
while( i < 60 );
return( i );
}
uint8_t bRadioGoSleep( void )
{
bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_SLEEP );
return( bRadioSwitchWaiting( CMT2310A_STATE_IS_SLEEP ) );
}
uint8_t bRadioGoStandby( void )
{
bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_READY );
delay10us( 3 );
bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_READY );
return( bRadioSwitchWaiting( CMT2310A_STATE_IS_READY ) );
}
uint8_t bRadioGoTx( void )
{
bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_TX );
return( bRadioSwitchWaiting( CMT2310A_STATE_IS_TX ) );
}
uint8_t bRadioGoRx( void )
{
bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_RX );
return( bRadioSwitchWaiting( CMT2310A_STATE_IS_RX ) );
}
uint8_t bRadioGoTxFS( void )
{
bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_TFS );
return( bRadioSwitchWaiting( CMT2310A_STATE_IS_TFS ) );
}
uint8_t bRadioGoRxFS( void )
{
bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_RFS );
return( bRadioSwitchWaiting( CMT2310A_STATE_IS_RFS ) );
}
//######################################################################
// FIFO Control
//######################################################################
/******************************
**Name: vRadioSetFifoTH
**Func: Radio set fifo threshold value
**Input: fifo_th
*Output: None
********************************/
void vRadioSetFifoTH( uint16_t fifo_th )
{
if( fifo_th >= 256 )
{
bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_TH_BIT8, CMT2310A_FIFO_TH_BIT8 );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_TH_BIT8 );
}
bRadioWriteReg( CMT2310A_CTL_REG_20, ( uint8_t )fifo_th );
}
/******************************
**Name: vRadioFifoRetent
**Func: Radio set fifo retent
**Input: cfg_en, FALSE: disable fifo retention
* TRUE: enable fifo retention
*Output: None
* note: fifo retention function active in sleep
********************************/
void vRadioFifoRetent( boolean_t cfg_en )
{
if( cfg_en )
{
bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_PD_FIFO );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_PD_FIFO, CMT2310A_PD_FIFO );
}
}
/******************************
**Name: vRadioFifoAutoClearBeforeRx
**Func: Radio set fifo auto clear when entry to Rx
**Input: cfg_en, FALSE: disable fifo auto clear
* TRUE: enable fifo auto clear
*Output: None
********************************/
void vRadioFifoAutoClearGoRx( boolean_t cfg_en )
{
if( cfg_en )
{
bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_AUTO_CLR_RX_EN, CMT2310A_FIFO_AUTO_CLR_RX_EN );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_AUTO_CLR_RX_EN );
}
}
/******************************
**Name: vRadioFifoAutoRestoreWhenTxDone
**Func: Radio set fifo auto re-store when after Tx
**Input: cfg_en, FALSE: disable fifo auto re-store
* TRUE: enable fifo auto re-store
*Output: None
* none: if need repeat send packet, this function should be enable
********************************/
void vRadioFifoAutoRestoreWhenTxDone( boolean_t cfg_en )
{
if( cfg_en )
{
bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_AUTO_RES_TX_EN, CMT2310A_FIFO_AUTO_RES_TX_EN );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_AUTO_RES_TX_EN );
}
}
/******************************
**Name: vRadioFifoMerge
**Func: Radio set fifo merge together
**Input: cfg_en, FALSE: disable fifo merge, 128B for Tx, and 128B for Rx
* TRUE: enable fifo merge, 256B for Tx or Rx
*Output: None
********************************/
void vRadioFifoMerge( boolean_t cfg_en )
{
if( cfg_en )
{
bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_MERGE_EN, CMT2310A_FIFO_MERGE_EN );
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_MERGE_EN );
}
}
/******************************
**Name: vRadioFifoTRxUsageSel
**Func: Radio set fifo used for Tx or Rx
**Input: cfg_tx, FALSE: used for Rx
* TRUE: used for Tx
*Output: None
* note: when FIFO merge together active
********************************/
void vRadioFifoTRxUsageSel( boolean_t cfg_tx )
{
if( cfg_tx )
{
bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_TX_RX_SEL, CMT2310A_FIFO_TX_RX_SEL ); //for rx
}
else
{
bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_TX_RX_SEL ); //for tx
}
}
/******************************
**Name: vRadioFifoGetStatus
**Func: Radio get fifo status
**Input: fifo_status
*Output: None
********************************/
void vRadioFifoGetStatus( FIFO_STATUS_FLG* fifo_status )
{
( *fifo_status ).FIFO_FLG_REG = bRadioReadReg( CMT2310A_CTL_REG_28 );
}
/******************************
**Name: vRadioClearTxFifo
**Func: Radio clear tx fifo
**Input: None
*Output: None
********************************/
void vRadioClearTxFifo( void )
{
bRadioSetReg( CMT2310A_CTL_REG_27, CMT2310A_TX_FIFO_CLR, CMT2310A_TX_FIFO_CLR );
}
/******************************
**Name: vRadioClearRxFifo
**Func: Radio clear rx fifo
**Input: None
*Output: None
********************************/
void vRadioClearRxFifo( void )
{
bRadioSetReg( CMT2310A_CTL_REG_27, CMT2310A_RX_FIFO_CLR, CMT2310A_RX_FIFO_CLR );
}
/******************************
**Name: vRadioManualResetTxFifoPointer
**Func: Radio manual store tx fifo, tx fifo pointer reset
* can be resend the same message
**Input: None
*Output: None
********************************/
void vRadioManualResetTxFifoPointer( void )
{
bRadioSetReg( CMT2310A_CTL_REG_27, CMT2310A_TX_FIFO_RESTORE, CMT2310A_TX_FIFO_RESTORE );
}
//######################################################################
// Interrupt Control
//######################################################################
/******************************
**Name: vRadioInterruptSoucreCfg
**Func: Radio set interrupt source config
**Input: int_src_ctrl
*Output: None
********************************/
void vRadioInterruptSoucreCfg( INT_SRC_CFG* int_src_ctrl )
{
bRadioWriteReg( CMT2310A_CTL_REG_18, ( *int_src_ctrl )._BYTE.INT_CTL1_REG );
bRadioWriteReg( CMT2310A_CTL_REG_21, ( *int_src_ctrl )._BYTE.INT_CTL2_REG );
bRadioWriteReg( CMT2310A_CTL_REG_23, ( *int_src_ctrl )._BYTE.INT_CTL3_REG );
bRadioWriteReg( CMT2310A_CTL_REG_14, ( *int_src_ctrl )._BYTE.INT_CTL4_REG );
}
/******************************
**Name: vRadioInterruptSoucreFlag
**Func: Radio get interrupt source flag
**Input: int_src_flag
*Output: None
********************************/
void vRadioInterruptSoucreFlag( INT_SRC_FLG* int_src_flag )
{
( *int_src_flag )._BYTE.INT_FLAG1_REG = bRadioReadReg( CMT2310A_CTL_REG_24 );
( *int_src_flag )._BYTE.INT_FLAG2_REG = bRadioReadReg( CMT2310A_CTL_REG_26 );
( *int_src_flag )._BYTE.INT_FLAG3_REG = bRadioReadReg( CMT2310A_CTL_REG_30 );
( *int_src_flag )._BYTE.INT_FLAG4_REG = bRadioReadReg( CMT2310A_CTL_REG_32 );
}
/******************************
**Name: vRadioInterruptSoucreClear
**Func: Radio clear interrupt source
**Input: int_src_clr
*Output: None
********************************/
void vRadioInterruptSoucreClear( INT_SRC_CLR* int_src_clr )
{
bRadioWriteReg( CMT2310A_CTL_REG_24, ( *int_src_clr )._BYTE.INT_CLR1_REG );
bRadioWriteReg( CMT2310A_CTL_REG_25, ( *int_src_clr )._BYTE.INT_CLR2_REG );
bRadioWriteReg( CMT2310A_CTL_REG_29, ( *int_src_clr )._BYTE.INT_CLR3_REG );
bRadioWriteReg( CMT2310A_CTL_REG_31, ( *int_src_clr )._BYTE.INT_CLR4_REG );
}
//######################################################################
// Config
//######################################################################
/******************************
**Name: vRadioConfigPageReg
**Func: Radio config page 0/1 regsisters
* page0, start address from 0x28
* page1, start address from 0x00
**Input: page_sel: Page0, Page1
* reg_ptr:
* reg_len:
*Output: None
* note: Page2 is not support burst mode
********************************/
void vRadioConfigPageReg( byte page_sel, uint8_t const reg_ptr[], uint8_t reg_len )
{
vRadioRegPageSel( page_sel );
vRadioBurstWriteRegs( ( byte* )reg_ptr, reg_len );
vRadioRegPageSel( 0 );
}
void vRadioReadPageReg( byte page_sel, uint8_t reg_ptr[], uint8_t reg_len )
{
vRadioRegPageSel( page_sel );
vRadioBurstReadRegs( reg_ptr, reg_len );
vRadioRegPageSel( 0 );
}
boolean_t bRadioIsExist( void )
{
uint8_t back, dat;
back = bRadioReadReg( CMT2310A_CTL_REG_12 );
bRadioWriteReg( CMT2310A_CTL_REG_12, 0xAA );
dat = bRadioReadReg( CMT2310A_CTL_REG_12 );
bRadioWriteReg( CMT2310A_CTL_REG_12, back );
if( 0xAA == dat )
{
return( TRUE );
}
else
{
return( FALSE );
}
}
//0x00231000
uint32_t lRadioChipVersion( void )
{
uint32_t chip_ver = 0;
vRadioRegPageSel( 2 );
chip_ver = bRadioReadReg( CMT2310A_CHIP_VERSION_00 );
chip_ver <<= 8;
chip_ver |= bRadioReadReg( CMT2310A_CHIP_VERSION_01 );
chip_ver <<= 8;
chip_ver |= bRadioReadReg( CMT2310A_CHIP_VERSION_02 );
vRadioRegPageSel( 0 );
return( chip_ver );
}

65
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.h Executable file
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@ -0,0 +1,65 @@
#ifndef __RADIO_PHY_H
#define __RADIO_PHY_H
//#include "stm8l15x.h"
#include "gd32w51x.h"
#include "radio_hal.h"
#include "CMT2310A_def.h"
#include "CMT2310A_reg.h"
extern void vRadioSetInt1Sel( uint8_t int1_sel );
extern void vRadioSetInt2Sel( uint8_t int2_sel );
extern void vRadioSetInt1Polar( boolean_t int1_polar );
extern void vRadioSetInt2Polar( boolean_t int2_polar );
extern void vRadioSetInt3Polar( boolean_t int3_polar );
extern void vRadioRssiUpdateSel( uint8_t sel );
extern uint8_t bRadioGetRssi( void );
extern void vRadioRssiConfig( RSSI_CFG rssi_cfg );
extern void vRadioRssiCalOffset( uint8_t cal_offset );
extern uint8_t bRadioGetLbdValue( void );
extern void vRadioSetLbdTH( uint8_t lbd_th );
extern uint8_t bRadioGetTemperature( void );
extern boolean_t bRadioApiCommand( uint8_t api_cmd );
extern void vRadioCdrModeCfg( enum CDR_MODE cdr_mode );
extern void vRadioTxRampCfg( boolean_t tx_ramp_en, uint16_t tx_ramp_step );
extern void vRadioTxGaussianCfg( boolean_t tx_gaus_en, uint8_t tx_gaus_bt );
extern void vRadioAfcCfg( boolean_t afc_en );
extern uint8_t bRadioGetState( void );
extern uint8_t bRadioGoSleep( void );
extern uint8_t bRadioGoStandby( void );
extern uint8_t bRadioGoTx( void );
extern uint8_t bRadioGoRx( void );
extern uint8_t bRadioGoTxFS( void );
extern uint8_t bRadioGoRxFS( void );
extern void vRadioSetFifoTH( uint16_t fifo_th );
extern void vRadioFifoRetent( boolean_t cfg_en );
extern void vRadioFifoAutoClearGoRx( boolean_t cfg_en );
extern void vRadioFifoAutoRestoreWhenTxDone( boolean_t cfg_en );
extern void vRadioFifoMerge( boolean_t cfg_en );
extern void vRadioFifoTRxUsageSel( boolean_t cfg_tx );
extern void vRadioFifoGetStatus( FIFO_STATUS_FLG* fifo_status );
extern void vRadioClearTxFifo( void );
extern void vRadioClearRxFifo( void );
extern void vRadioManualResetTxFifoPointer( void );
extern void vRadioInterruptSoucreCfg( INT_SRC_CFG* int_src_ctrl );
extern void vRadioInterruptSoucreFlag( INT_SRC_FLG* int_src_flag );
extern void vRadioInterruptSoucreClear( INT_SRC_CLR* int_src_clr );
extern void vRadioConfigPageReg( byte page_sel, uint8_t const reg_ptr[], uint8_t reg_len );
extern void vRadioReadPageReg( byte page_sel, uint8_t reg_ptr[], uint8_t reg_len );
extern boolean_t bRadioIsExist( void );
extern uint32_t lRadioChipVersion( void );
#endif

108
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.c Executable file
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@ -0,0 +1,108 @@
#include "radio_spi.h"
/******************************
**Name: vSpiMasterInit
**Func: SPI Master
**Input: None
*Output: None
********************************/
void vSpiMasterInit( void )
{
/* <20>Ѿ<EFBFBD><D1BE><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>SPI <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
}
uint8_t bSpiWriteByte( uint8_t spi_adr, uint8_t spi_dat )
{
uint8_t ret;
spi_adr &= 0x7F;
/* SPI Ƭѡ CS */
#if EBYTE_PORT_SPI_CS_SOFTWARE
Ebyte_Port_SpiCsIoControl( 0 );
#endif
Ebyte_Port_SpiTransmitAndReceivce(spi_adr);
ret = Ebyte_Port_SpiTransmitAndReceivce(spi_dat);
/* SPI Ƭѡ CS */
#if EBYTE_PORT_SPI_CS_SOFTWARE
Ebyte_Port_SpiCsIoControl( 1 );
#endif
return ret;
}
uint8_t bSpiReadByte( uint8_t spi_adr )
{
uint8_t ret;
spi_adr |= 0x80;
/* SPI Ƭѡ CS */
#if EBYTE_PORT_SPI_CS_SOFTWARE
Ebyte_Port_SpiCsIoControl( 0 );
#endif
Ebyte_Port_SpiTransmitAndReceivce(spi_adr);
ret = Ebyte_Port_SpiTransmitAndReceivce(0x00);
/* SPI Ƭѡ CS */
#if EBYTE_PORT_SPI_CS_SOFTWARE
Ebyte_Port_SpiCsIoControl( 1 );
#endif
return ret;
}
void vSpiBurstWrite( uint8_t spi_adr, uint8_t spi_dat[], uint8_t spi_length )
{
uint8_t i;
spi_adr &= 0x7F;
/* SPI Ƭѡ CS */
#if EBYTE_PORT_SPI_CS_SOFTWARE
Ebyte_Port_SpiCsIoControl( 0 );
#endif
Ebyte_Port_SpiTransmitAndReceivce(spi_adr);
for(i=0; i<spi_length; i++)
{
Ebyte_Port_SpiTransmitAndReceivce(spi_dat[i]);
}
/* SPI Ƭѡ CS */
#if EBYTE_PORT_SPI_CS_SOFTWARE
Ebyte_Port_SpiCsIoControl( 1 );
#endif
}
void vSpiBurstRead( uint8_t spi_adr, uint8_t spi_dat[], uint8_t spi_length )
{
uint8_t i;
spi_adr |= 0x80;
/* SPI Ƭѡ CS */
#if EBYTE_PORT_SPI_CS_SOFTWARE
Ebyte_Port_SpiCsIoControl( 0 );
#endif
Ebyte_Port_SpiTransmitAndReceivce(spi_adr);
for(i=0; i<spi_length; i++)
{
spi_dat[i] = Ebyte_Port_SpiTransmitAndReceivce(0x00);
}
/* SPI Ƭѡ CS */
#if EBYTE_PORT_SPI_CS_SOFTWARE
Ebyte_Port_SpiCsIoControl( 1 );
#endif
}

17
MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.h Executable file
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@ -0,0 +1,17 @@
#ifndef __RADIO_SPI_H
#define __RADIO_SPI_H
//#include "stm8l15x.h"
#include "gd32w51x.h"
#include "ebyte_port.h"
extern void vSpiMasterInit( void );
extern uint8_t bSpiWriteByte( uint8_t spi_adr, uint8_t spi_dat );
extern uint8_t bSpiReadByte( uint8_t spi_adr );
extern void vSpiBurstWrite( uint8_t spi_adr, uint8_t spi_dat[], uint8_t spi_length );
extern void vSpiBurstRead( uint8_t spi_adr, uint8_t spi_dat[], uint8_t spi_length );
#endif

55
MBL/source_ns/drivers/CMT2310/CMakeLists.txt Normal file
View File

@ -0,0 +1,55 @@
cmake_minimum_required(VERSION 3.15)
add_library(cmt2310)
add_library(cmt2310_api INTERFACE)
target_sources(cmt2310
PRIVATE
0_Project/Uart_PingPong/main.c
0_Project/Uart_PingPong/ebyte/ebyte_callback.c
0_Project/Uart_PingPong/ebyte/ebyte_core.c
0_Project/Uart_PingPong/ebyte/ebyte_port.c
0_Project/Uart_PingPong/irq_handle.c
1_Middleware/Kfifo/ebyte_kfifo.c
1_Middleware/Produce/ebyte_debug.c
2_Ebyte_Board_Support/E15-EVB02/board_button.c
2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.c
2_Ebyte_Board_Support/E15-EVB02/board.c
3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_433mhz.c
3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c
3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_868mhz.c
3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_915mhz.c
3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.c
3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c
3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_410mhz.c
3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.c
3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.c
3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c
)
target_include_directories(cmt2310
PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/0_Project/Uart_PingPong/
${CMAKE_CURRENT_SOURCE_DIR}/0_Project/Uart_PingPong/ebyte/
${CMAKE_CURRENT_SOURCE_DIR}/1_Middleware/Kfifo/
${CMAKE_CURRENT_SOURCE_DIR}/1_Middleware/Produce/
${CMAKE_CURRENT_SOURCE_DIR}/2_Ebyte_Board_Support/E15-EVB02/
${CMAKE_CURRENT_SOURCE_DIR}/3_Ebyte_WirelessModule_Drivers/E48xMx/
# ${CMAKE_CURRENT_SOURCE_DIR}/4_STM8_L15x_StdPeriph_Drivers/
# ${CMAKE_CURRENT_SOURCE_DIR}/4_STM8_L15x_StdPeriph_Drivers/inc/
)
target_include_directories(cmt2310_api
INTERFACE
${CMAKE_CURRENT_SOURCE_DIR}/0_Project/Uart_PingPong/
${CMAKE_CURRENT_SOURCE_DIR}/0_Project/Uart_PingPong/ebyte/
${CMAKE_CURRENT_SOURCE_DIR}/1_Middleware/Kfifo/
${CMAKE_CURRENT_SOURCE_DIR}/1_Middleware/Produce/
${CMAKE_CURRENT_SOURCE_DIR}/2_Ebyte_Board_Support/E15-EVB02/
${CMAKE_CURRENT_SOURCE_DIR}/3_Ebyte_WirelessModule_Drivers/E48xMx/
)
target_link_libraries(cmt2310
os_api
gd32w51x_peripheral_api
)

22
MBL/source_ns/drivers/CMT2310/readme.md Executable file
View File

@ -0,0 +1,22 @@
## Ŀ¼<C4BF>ṹ
```shell
|-E15-EVB02-E48-DEMO //<2F><><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD>
| |
| |-0_Project
| |_IAR_for_Stm8 //<2F><><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>У<EFBFBD><D0A3><EFBFBD>IAR<41><52><EFBFBD><EFBFBD>
|
| |-1_Middleware
| |<EFBFBD><EFBFBD>Kfifo //ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
| |_Produce //PC<50><43><EFBFBD><EFBFBD>
|
| |-2_Ebyte_Board_Support
| |_E15-EVB02 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>ʼ<EFBFBD><CABC>
|
| |-3_Ebyte_WirelessModule_Drivers
| |_E48xMx //E48<34><38><EFBFBD><EFBFBD>
|
| |-4_STM8_L15x_StdPeriph_Drivers
```

10
MBL/source_ns/mbl_ns.c
View File

@ -39,10 +39,13 @@ OF SUCH DAMAGE.
#include "mbl_sys.h" #include "mbl_sys.h"
#include "mbl_uart.h" #include "mbl_uart.h"
#include "mbl_flash.h" #include "mbl_flash.h"
#include "ebyte_e48.h"
#include "rom_region.h"
typedef void (*img_fptr_t) (void); typedef void (*img_fptr_t) (void);
int32_t mbl_err_process = ERR_PROCESS_ENDLESS_LOOP; int32_t mbl_err_process = ERR_PROCESS_ENDLESS_LOOP;
int32_t mbl_trace_level = MBL_WARN; int32_t mbl_trace_level = MBL_WARN;
struct rom_api_s_t *p_rom_api_s = (struct rom_api_s_t *)ROM_API_ARRAY_BASE;
#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) #if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
/* Macros to pick linker symbols */ /* Macros to pick linker symbols */
@ -72,6 +75,7 @@ static void jump_to_main_image(uint32_t msp, uint32_t reset)
img_reset = (img_fptr_t)reset; img_reset = (img_fptr_t)reset;
// __disable_irq();
#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) #if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
/* Restore the Main Stack Pointer Limit register's reset value /* Restore the Main Stack Pointer Limit register's reset value
* before passing execution to runtime firmware to make the * before passing execution to runtime firmware to make the
@ -95,12 +99,13 @@ static void jump_to_main_image(uint32_t msp, uint32_t reset)
*/ */
int main(void) int main(void)
{ {
int ret;
struct image_header hdr; struct image_header hdr;
uint32_t boot_idx = 0, image_offset = 0, version; uint32_t boot_idx = 0, image_offset = 0, version;
uint32_t arm_vector[2]; uint32_t arm_vector[2];
int ret;
#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) #if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
uint32_t msp_stack_bottom = 0; uint32_t msp_stack_bottom = 0;
#if defined (__ICCARM__) #if defined (__ICCARM__)
msp_stack_bottom = (uint32_t)&REGION_NAME(CSTACK, $$Base); msp_stack_bottom = (uint32_t)&REGION_NAME(CSTACK, $$Base);
#else #else
@ -119,6 +124,9 @@ int main(void)
/* Initialize flash for reading system info */ /* Initialize flash for reading system info */
flash_init(); flash_init();
/* Init Systick */
ebyte_main();
/* Initialize system status if empty or validate system status */ /* Initialize system status if empty or validate system status */
ret = sys_status_check(); ret = sys_status_check();
if (ret < 0) { if (ret < 0) {

5
Makefile
View File

@ -4,7 +4,7 @@
#==============================================================================# #==============================================================================#
LOCAL_DIR := $(strip $(shell pwd)) LOCAL_DIR := $(strip $(shell pwd))
SDK_TOP := $(LOCAL_DIR) SDK_TOP := $(LOCAL_DIR)
CMAKE_DIR := $(LOCAL_DIR)/.cmake CMAKE_DIR := $(LOCAL_DIR)/output/.cmake
OUTPUT_DIR ?= $(LOCAL_DIR)/output OUTPUT_DIR ?= $(LOCAL_DIR)/output
INSTALL_DIR ?= $(LOCAL_DIR)/__install INSTALL_DIR ?= $(LOCAL_DIR)/__install
@ -39,7 +39,8 @@ check_env:
mkdir -p $(CMAKE_DIR); \ mkdir -p $(CMAKE_DIR); \
cmake -G "Unix Makefiles" \ cmake -G "Unix Makefiles" \
-S $(LOCAL_DIR) -B $(CMAKE_DIR) \ -S $(LOCAL_DIR) -B $(CMAKE_DIR) \
-DCMAKE_TOOLCHAIN_FILE:PATH=$(SDK_TOP)/scripts/cmake/toolchain.cmake; \ -DCMAKE_TOOLCHAIN_FILE:PATH=$(SDK_TOP)/scripts/cmake/toolchain.cmake \
-DCMAKE_EXPORT_COMPILE_COMMANDS=1;\
fi; fi;
clean: check_env $(CLEAN_ALL) clean: check_env $(CLEAN_ALL)

35
MultiProject_NS.uvmpw
View File

@ -1,15 +1,20 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd"> <ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header> <SchemaVersion>1.0</SchemaVersion>
<WorkspaceName>WorkSpace</WorkspaceName>
<project> <Header>### uVision Project, (C) Keil Software</Header>
<PathAndName>.\MBL\project\KEIL\Project_MBL_NS.uvprojx</PathAndName>
<NodeIsActive>1</NodeIsActive> <WorkspaceName>WorkSpace</WorkspaceName>
<NodeIsExpanded>1</NodeIsExpanded>
</project> <project>
<project> <PathAndName>.\MBL\project\KEIL\Project_MBL_NS.uvprojx</PathAndName>
<PathAndName>.\NSPE\Project\WIFI_IOT\KEIL\Project_WIFI_IOT.uvprojx</PathAndName> </project>
<NodeIsExpanded>1</NodeIsExpanded>
</project> <project>
</ProjectWorkspace> <PathAndName>.\NSPE\Project\WIFI_IOT\KEIL\Project_WIFI_IOT.uvprojx</PathAndName>
<NodeIsActive>1</NodeIsActive>
<NodeIsExpanded>1</NodeIsExpanded>
</project>
</ProjectWorkspace>

1
NSPE/CMakeLists.txt
View File

@ -48,6 +48,7 @@ target_link_libraries(${TARGET_EXE}
wifi wifi
os os
cmsis cmsis
cmt2310
) )
target_link_options(${TARGET_EXE} target_link_options(${TARGET_EXE}

34
NSPE/Example/TIMER/TIMER2_timebase/main.c
View File

@ -1,34 +1,34 @@
/*! /*!
\file main.c \file main.c
\brief TIMER2 oc timebase demo for gd32w51x \brief TIMER2 oc timebase demo for gd32w51x
\version 2021-10-30, V1.0.0, firmware for GD32W51x \version 2021-10-30, V1.0.0, firmware for GD32W51x
*/ */
/* /*
Copyright (c) 2021, GigaDevice Semiconductor Inc. Copyright (c) 2021, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -61,7 +61,7 @@ void nvic_config(void)
void timer_config(void) void timer_config(void)
{ {
/* ---------------------------------------------------------------------------- /* ----------------------------------------------------------------------------
TIMER2 Configuration: TIMER2 Configuration:
TIMER2CLK = SystemCoreClock/9000 = 20KHz. TIMER2CLK = SystemCoreClock/9000 = 20KHz.
TIMER2 configuration is timing mode, and the timing is 0.2s(4000/20000 = 0.2s). TIMER2 configuration is timing mode, and the timing is 0.2s(4000/20000 = 0.2s).
---------------------------------------------------------------------------- */ ---------------------------------------------------------------------------- */

24
NSPE/Firmware/CMSIS/ARM/cmsis/cmsis_gcc.h
View File

@ -46,9 +46,9 @@
#ifndef __STATIC_INLINE #ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#endif #endif
#ifndef __STATIC_FORCEINLINE #ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif #endif
#ifndef __NO_RETURN #ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__)) #define __NO_RETURN __attribute__((__noreturn__))
#endif #endif
@ -126,23 +126,23 @@
\details This default implementations initialized all data and additional bss \details This default implementations initialized all data and additional bss
sections relying on .copy.table and .zero.table specified properly sections relying on .copy.table and .zero.table specified properly
in the used linker script. in the used linker script.
*/ */
__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
{ {
extern void _start(void) __NO_RETURN; extern void _start(void) __NO_RETURN;
typedef struct { typedef struct {
uint32_t const* src; uint32_t const* src;
uint32_t* dest; uint32_t* dest;
uint32_t wlen; uint32_t wlen;
} __copy_table_t; } __copy_table_t;
typedef struct { typedef struct {
uint32_t* dest; uint32_t* dest;
uint32_t wlen; uint32_t wlen;
} __zero_table_t; } __zero_table_t;
extern const __copy_table_t __copy_table_start__; extern const __copy_table_t __copy_table_start__;
extern const __copy_table_t __copy_table_end__; extern const __copy_table_t __copy_table_end__;
extern const __zero_table_t __zero_table_start__; extern const __zero_table_t __zero_table_start__;
@ -153,16 +153,16 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
pTable->dest[i] = pTable->src[i]; pTable->dest[i] = pTable->src[i];
} }
} }
for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
for(uint32_t i=0u; i<(pTable->wlen/sizeof(pTable->dest)); ++i) { for(uint32_t i=0u; i<(pTable->wlen/sizeof(pTable->dest)); ++i) {
pTable->dest[i] = 0u; pTable->dest[i] = 0u;
} }
} }
_start(); _start();
} }
#define __PROGRAM_START __cmsis_start #define __PROGRAM_START __cmsis_start
#endif #endif
@ -652,7 +652,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure Stack Pointer Limit register hence zero is returned always in non-secure
mode. mode.
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value \return PSPLIM Register value
*/ */
@ -697,7 +697,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure
mode. mode.
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/ */
@ -834,7 +834,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
{ {
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ) (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_get_fpscr) #if __has_builtin(__builtin_arm_get_fpscr)
// Re-enable using built-in when GCC has been fixed // Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

2
NSPE/Firmware/CMSIS/GD/GD32W51x/Include/gd32w51x.h
View File

@ -194,7 +194,7 @@ typedef enum IRQn
/* enum definitions */ /* enum definitions */
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus; typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
/* bit operations */ /* bit operations */

5616
NSPE/Project/WIFI_IOT/KEIL/Project_WIFI_IOT.uvoptx
View File

File diff suppressed because it is too large Load Diff

6283
NSPE/Project/WIFI_IOT/KEIL/Project_WIFI_IOT.uvprojx
View File

File diff suppressed because it is too large Load Diff

0
NSPE/Project/WIFI_IOT/build_date.bat Normal file → Executable file
View File

20
NSPE/Project/WIFI_IOT/nspe_afterbuild.bat Normal file → Executable file
View File

@ -15,12 +15,22 @@ set OUTPUT_FILE=nspe
IF EXIST %OUTPUT_PATH%\..\nspe* del %OUTPUT_PATH%\..\nspe* IF EXIST %OUTPUT_PATH%\..\nspe* del %OUTPUT_PATH%\..\nspe*
if "%TOOLKIT%" == "KEIL" ( for /f "tokens=1,2 delims=\" %%a in ("%TOOLKIT_PATH%") do set driver=%%a &set version=%%b
:: Generate txt for debug
%TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --text -c -d --output=%OUTPUT_PATH%\..\%OUTPUT_FILE%.txt %OUTPUT_PATH%\%OUTPUT_FILE%.axf
:: Generate binary image if "%TOOLKIT%" == "KEIL" (
%TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --bin --8x1 --bincombined --output=%OUTPUT_PATH%\..\nspe.bin %OUTPUT_PATH%\%OUTPUT_FILE%.axf if "%version%" == "Keil_v5" (
:: Generate txt for debug
%TOOLKIT_PATH%\ARM\ARMCLANG\bin\fromelf.exe --text -c -d --output=%OUTPUT_PATH%\..\%OUTPUT_FILE%.txt %OUTPUT_PATH%\%OUTPUT_FILE%.axf
:: Generate binary image
%TOOLKIT_PATH%\ARM\ARMCLANG\bin\fromelf.exe --bin --8x1 --bincombined --output=%OUTPUT_PATH%\..\%OUTPUT_FILE%.bin %OUTPUT_PATH%\%OUTPUT_FILE%.axf
) else (
:: Generate txt for debug
%TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --text -c -d --output=%OUTPUT_PATH%\..\%OUTPUT_FILE%.txt %OUTPUT_PATH%\%OUTPUT_FILE%.axf
:: Generate binary image
%TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --bin --8x1 --bincombined --output=%OUTPUT_PATH%\..\%OUTPUT_FILE%.bin %OUTPUT_PATH%\%OUTPUT_FILE%.axf
)
) )
if "%TOOLKIT%" == "IAR" ( if "%TOOLKIT%" == "IAR" (
:: Generate ASM file :: Generate ASM file

0
NSPE/Project/WIFI_IOT/wifi_version.bat Normal file → Executable file
View File

6
NSPE/Utilities/gd32w515p_eval.h
View File

@ -71,9 +71,9 @@ typedef enum
#define LED2_GPIO_PORT GPIOA #define LED2_GPIO_PORT GPIOA
#define LED2_GPIO_CLK RCU_GPIOA #define LED2_GPIO_CLK RCU_GPIOA
#define LED3_PIN GPIO_PIN_8 #define LED3_PIN GPIO_PIN_6
#define LED3_GPIO_PORT GPIOB #define LED3_GPIO_PORT GPIOA
#define LED3_GPIO_CLK RCU_GPIOB #define LED3_GPIO_CLK RCU_GPIOA
#define COMn 1U #define COMn 1U
#define EVAL_COM0 USART2 #define EVAL_COM0 USART2

8
NSPE/WIFI_IOT/app/CMakeLists.txt
View File

@ -32,6 +32,13 @@ target_sources(app
../demo/cmsis_os_demo.c ../demo/cmsis_os_demo.c
) )
if(CONFIG_GY3513)
target_sources(app
PRIVATE
../../Utilities/gd32w515p_eval.c
)
endif(CONFIG_GY3513)
target_link_libraries(app target_link_libraries(app
gd32w51x_peripheral_api gd32w51x_peripheral_api
gd32w51x_wifi_api gd32w51x_wifi_api
@ -42,6 +49,7 @@ target_link_libraries(app
wifi_api wifi_api
os_api os_api
cmsis_api cmsis_api
cmt2310_api
$<$<BOOL:${CONFIG_ALICLOUD_SUPPORT}>:alicloud> $<$<BOOL:${CONFIG_ALICLOUD_SUPPORT}>:alicloud>
$<$<BOOL:${CONFIG_IPERF_TEST}>:iperf3> $<$<BOOL:${CONFIG_IPERF_TEST}>:iperf3>
$<$<BOOL:${CONFIG_IPERF_TEST}>:iperf3_api> $<$<BOOL:${CONFIG_IPERF_TEST}>:iperf3_api>

5
NSPE/WIFI_IOT/app/app_cfg.h
View File

@ -114,8 +114,13 @@ OF SUCH DAMAGE.
#define ALICLOUD_TASK_PRIO TASK_PRIO_APP_BASE #define ALICLOUD_TASK_PRIO TASK_PRIO_APP_BASE
#endif #endif
//#define CONFIG_TASK_LED
#ifdef CONFIG_IPERF_TEST #ifdef CONFIG_IPERF_TEST
#define IPERF_TASK_MAX 1 #define IPERF_TASK_MAX 1
#define CONFIG_PRINT_IN_SEQUENCE
#ifdef CONFIG_PRINT_IN_SEQUENCE #ifdef CONFIG_PRINT_IN_SEQUENCE
#define IPERF_STACK_SIZE 1024 #define IPERF_STACK_SIZE 1024
#else #else

62
NSPE/WIFI_IOT/app/cmd_shell.c
View File

@ -58,6 +58,7 @@ OF SUCH DAMAGE.
#include "wifi_management.h" #include "wifi_management.h"
#include "uart.h" #include "uart.h"
#include "console.h" #include "console.h"
#include "flash_api.h"
#ifdef CONFIG_TELNET_SERVER #ifdef CONFIG_TELNET_SERVER
#include "telnet_main.h" #include "telnet_main.h"
@ -1076,6 +1077,66 @@ Usage:
DEBUGPRINT(" 1 # support 20/40MHz\r\n"); DEBUGPRINT(" 1 # support 20/40MHz\r\n");
} }
typedef void (*img_fptr_t) (void);
#define IMAGE_HEADER_SIZE 0
/*!
\brief set bw to support 20MHz only or 20/40MHz
\param[in] argc: number of parameters
\param[in] argv: the pointer to the array that holds the parameters
\param[out] none
\retval none
*/
static void cmd_boot(int argc, char **argv)
{
static img_fptr_t img_reset;
uint32_t arm_vector[2] = {0};
uint32_t boot_idx = 0, image_offset = 0, version;
if (argc > 2) {
DEBUGPRINT("jump_bml: command format error!\r\n");
goto Usage;
}
/* Read the MSP and Reset_Handler of the main image */
flash_read((image_offset + IMAGE_HEADER_SIZE), arm_vector, 8);
if (!is_valid_flash_addr(arm_vector[1])) {
DEBUGPRINT("Error, image vector reset is invalid (%08x).\r\n", arm_vector[1]);
goto BootFailed;
}
for (int i = 0; i < sizeof(NVIC->ICER) / 4; i++)
NVIC->ICER[i] = ~(0UL);
/* Jump to main image */
img_reset = (img_fptr_t)arm_vector[1];
#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
/* Restore the Main Stack Pointer Limit register's reset value
* before passing execution to runtime firmware to make the
* bootloader transparent to it.
*/
__set_MSPLIM(0);
#endif
__set_MSP(arm_vector[0]);
__DSB();
__ISB();
img_reset();
BootFailed:
DEBUGPRINT("\r[%s|%u] Jump to MBL failed.\r\n", __FUNCTION__, __LINE__);
while(1);
Usage:
DEBUGPRINT("\rUsage:\r\n");
DEBUGPRINT(" jm [0/1]\r\n");
DEBUGPRINT(" 0 # dry run.\r\n");
DEBUGPRINT(" 1 # show the verbosity of messages.\r\n");
}
static const cmd_entry cmd_table[] = { static const cmd_entry cmd_table[] = {
#ifdef CONFIG_BASECMD #ifdef CONFIG_BASECMD
{"wifi_open", cmd_wifi_open}, {"wifi_open", cmd_wifi_open},
@ -1121,6 +1182,7 @@ static const cmd_entry cmd_table[] = {
{"wifi_set_bw", cmd_bw_set}, {"wifi_set_bw", cmd_bw_set},
#endif #endif
{"reboot", cmd_reboot}, {"reboot", cmd_reboot},
{"bootm", cmd_boot},
{"help", cmd_help} {"help", cmd_help}
}; };

83
NSPE/WIFI_IOT/app/main.c
View File

@ -33,6 +33,7 @@ OF SUCH DAMAGE.
*/ */
/*============================ INCLUDES ======================================*/ /*============================ INCLUDES ======================================*/
#include "wrapper_freertos.h"
#include "wrapper_os.h" #include "wrapper_os.h"
#include "debug_print.h" #include "debug_print.h"
#include "bsp_inc.h" #include "bsp_inc.h"
@ -45,9 +46,16 @@ OF SUCH DAMAGE.
#include "main.h" #include "main.h"
#include "wifi_version.h" #include "wifi_version.h"
#include "nspe_region.h" #include "nspe_region.h"
#include <stdint.h>
#include <stdio.h>
#ifdef CONFIG_FATFS_SUPPORT #ifdef CONFIG_FATFS_SUPPORT
#include "fatfs.h" #include "fatfs.h"
#endif #endif
#if defined (CONFIG_GY3513)
#include <gd32w515p_eval.h>
#endif // CONFIG_GY3513
#include "ebyte_e48.h"
/*============================ MACROS ========================================*/ /*============================ MACROS ========================================*/
/*============================ MACRO FUNCTIONS ===============================*/ /*============================ MACRO FUNCTIONS ===============================*/
/*============================ TYPES =========================================*/ /*============================ TYPES =========================================*/
@ -74,6 +82,30 @@ void do_ram_code_copy(void)
} }
#endif #endif
#if defined (CONFIG_TASK_LED)
static int32_t led_init(void)
{
gd_eval_led_init(LED1);
gd_eval_led_init(LED2);
gd_eval_led_init(LED3);
return 0;
}
void led_task(void *p_arg)
{
uint32_t count = 0;
while (1) {
gd_eval_led_toggle(((int32_t)(count % 12) - 6) < 0 ? count % 3 : (2 - count % 3));
sys_ms_sleep(200);
count++;
}
sys_task_delete(NULL);
}
#endif // CONFIG_TASK_LED
/*! /*!
\brief initialize application \brief initialize application
\param[in] none \param[in] none
@ -85,6 +117,19 @@ __WEAK void app_init(void)
/* User application entry */ /* User application entry */
} }
/*!
\brief start task
\param[in] p_arg: the pointer of parameters
\param[out] none
\retval none
*/
void sub1g_task(void *p_arg)
{
ebyte_main();
sys_task_delete(NULL);
}
/*! /*!
\brief start task \brief start task
\param[in] p_arg: the pointer of parameters \param[in] p_arg: the pointer of parameters
@ -94,16 +139,18 @@ __WEAK void app_init(void)
void start_task(void *p_arg) void start_task(void *p_arg)
{ {
(void)p_arg; (void)p_arg;
#if defined (CONFIG_GY3513)
sys_reset_flag_check(); size_t len;
sys_os_misc_init(); uint8_t read_buf[2000];
systick_delay_init(); const char *filename;
#endif // CONFIG_GY3513
wifi_management_init(); wifi_management_init();
#ifdef CONFIG_FATFS_SUPPORT #ifdef CONFIG_FATFS_SUPPORT
rcu_periph_clock_enable(RCU_CRC); rcu_periph_clock_enable(RCU_CRC);
fatfs_mk_mount(); fatfs_mk_mount();
#endif #endif
#ifdef CONFIG_CONSOLE_ENABLE #ifdef CONFIG_CONSOLE_ENABLE
console_init(); console_init();
#else #else
@ -121,16 +168,40 @@ void start_task(void *p_arg)
*/ */
int main(void) int main(void)
{ {
#if defined (CONFIG_TASK_LED)
TaskHandle_t *stTaskHndl_led = NULL;
#endif // CONFIG_TASK_LED
platform_init(); platform_init();
#if defined (CONFIG_TASK_LED)
led_init();
#endif // CONFIG_TASK_LED
DEBUGPRINT("SDK git revision: "WIFI_GIT_REVISION" \r\n"); DEBUGPRINT("SDK git revision: "WIFI_GIT_REVISION" \r\n");
DEBUGPRINT("SDK version: V%d.%d.%d\r\n", (RE_NSPE_VERSION >> 24), ((RE_NSPE_VERSION & 0xFF0000) >> 16), (RE_NSPE_VERSION & 0xFFFF)); DEBUGPRINT("SDK version: V%d.%d.%d\r\n", (RE_NSPE_VERSION >> 24), ((RE_NSPE_VERSION & 0xFF0000) >> 16), (RE_NSPE_VERSION & 0xFFFF));
DEBUGPRINT("SDK build date: "BUILD_DATE" \r\n"); DEBUGPRINT("SDK build date: "BUILD_DATE" \r\n");
sys_reset_flag_check();
sys_os_init(); sys_os_init();
sys_os_misc_init();
if (NULL == sys_task_create(NULL, (const uint8_t *)"start_task", NULL, START_TASK_STK_SIZE, 0, systick_delay_init();
START_TASK_PRIO, start_task, NULL)) {
#if defined (CONFIG_TASK_LED)
#define LED_TASK_STK_SIZE 256
#define LED_TASK_PRIO (TASK_PRIO_APP_BASE + TASK_PRIO_HIGHER(1))
stTaskHndl_led = sys_task_create(NULL, (const uint8_t *)"led_task", NULL, LED_TASK_STK_SIZE, 0, LED_TASK_PRIO, led_task, NULL);
if (stTaskHndl_led == NULL) {
DEBUG_ERROR("Error, task create failed.\r\n");
}
#endif // CONFIG_TASK_LED
if (NULL == sys_task_create(NULL, (const uint8_t *)"start_task", NULL, START_TASK_STK_SIZE, 0, START_TASK_PRIO, start_task, NULL)) {
DEBUGPRINT("ERROR: create start task failed\r\n");
}
if (NULL == sys_task_create(NULL, (const uint8_t *)"sub1g_task", NULL, START_TASK_STK_SIZE, 0, START_TASK_PRIO, sub1g_task, NULL)) {
DEBUGPRINT("ERROR: create start task failed\r\n"); DEBUGPRINT("ERROR: create start task failed\r\n");
} }

3
NSPE/WIFI_IOT/bsp/CMakeLists.txt
View File

@ -30,4 +30,7 @@ target_link_libraries(bsp
bsp_api bsp_api
os_api os_api
wifi_api wifi_api
cmt2310_api
) )
add_subdirectory(drivers/CMT2310)

12
NSPE/WIFI_IOT/bsp/drivers/.editorconfig Normal file
View File

@ -0,0 +1,12 @@
# EditorConfig is awesome: https://EditorConfig.org
# top-most EditorConfig file
root = true
[*]
indent_style = tab
indent_size = 8
end_of_line = lf
charset = utf-8
trim_trailing_whitespace = true
insert_final_newline = false

155
NSPE/WIFI_IOT/bsp/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.c Executable file
View File

@ -0,0 +1,155 @@
/**
**********************************************************************************
* @file ebyte_callback.h
* @brief EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>շ<EFBFBD><D5B7><EFBFBD><EFBFBD>ɻص<C9BB><D8B5><EFBFBD><EFBFBD><EFBFBD> <20>ɿͻ<C9BF>ʵ<EFBFBD><CAB5><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD>߼<EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-13
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "ebyte_callback.h"
/*= !!!<21><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨ͷ<CCA8>ļ<EFBFBD> =======================================*/
#include "board.h" //E15-EVB02 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#include "ebyte_debug.h" //E15-EVB02 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
/*= !!!<21><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD> =======================================*/
extern uint8_t RxBuffer[64];
extern uint8_t BufferPing[5];
extern uint8_t BufferPong[5];
extern uint8_t Callback_isPingCheckReady;
extern uint8_t PC_isConnected;
extern uint8_t PcEchoBuffer[20];
/*==================================================================*/
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɻص<C9BB><D8B5>ӿ<EFBFBD> <20>ɿͻ<C9BF>ʵ<EFBFBD><CAB5><EFBFBD>Լ<EFBFBD><D4BC>ķ<EFBFBD><C4B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD>
*
* @param state <20>ϲ<EFBFBD><CFB2>ص<EFBFBD><D8B5>ṩ<EFBFBD><E1B9A9>״̬<D7B4><CCAC> <20>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE>ע<EFBFBD><D7A2><EFBFBD>ҵ<EFBFBD><D2B5><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD>
*
*/
void Ebyte_Port_TransmitCallback( uint16e_t state )
{
/* <20><><EFBFBD><EFBFBD>: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if( state &= 0x0001 )
{
//To-do ʵ<><CAB5><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD>߼<EFBFBD>
}
/* <20><><EFBFBD><EFBFBD>: <20>쳣<EFBFBD><ECB3A3>ʱ */
else if ( state &= 0x0200 )
{
//To-do ʵ<><CAB5><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD>߼<EFBFBD>
}
/* <20><><EFBFBD><EFBFBD>: δ֪<CEB4><D6AA><EFBFBD><EFBFBD> */
else
{
/* <20><><EFBFBD><EFBFBD>״̬<D7B4><CCAC>ʶ<EFBFBD><CAB6><EFBFBD><EFBFBD>ȷ<EFBFBD><C8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2>
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1:SPIͨ<49>Ų<EFBFBD><C5B2><EFBFBD>ȷ 2:ģ<>鹩<EFBFBD>粻<EFBFBD><E7B2BB> */
while(1);
}
}
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɻص<C9BB><D8B5>ӿ<EFBFBD> <20>ɿͻ<C9BF>ʵ<EFBFBD><CAB5><EFBFBD>Լ<EFBFBD><D4BC>ķ<EFBFBD><C4B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD>
*
* @param state <20>ϲ<EFBFBD><CFB2>ص<EFBFBD><D8B5>ṩ<EFBFBD><E1B9A9>״̬<D7B4><CCAC> <20>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE>ע<EFBFBD><D7A2><EFBFBD>ҵ<EFBFBD><D2B5><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD>
*
*/
void Ebyte_Port_ReceiveCallback( uint16_t state, uint8_t *buffer, uint8_t length )
{
uint8_t j, pcEchoLength;
uint8_t *p;
/* <20><><EFBFBD><EFBFBD>: <20><><EFBFBD><EFBFBD> */
if( state &= 0x0002 )
{
//To-do ʵ<><CAB5><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD>߼<EFBFBD>
/* ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD>ping pongָ<67><D6B8> */
if( length == 4 || length == 5 )
{
p = buffer;
for( j = 0; j < 4; j++ )
{
if( BufferPing[j] != *p++ )
{
break;
}
}
//<2F>Ƚϵ<C8BD><CFB5><EFBFBD>ĩβ<C4A9><CEB2>ʾ<EFBFBD><CABE>ȫƥ<C8AB><C6A5>ping
if( j == 4 )
{
Callback_isPingCheckReady = 1;//֪ͨ<CDA8>ظ<EFBFBD>Pong
if( length == 5 && PC_isConnected )
{
BufferPong[4] = buffer[4];//<2F><>5<EFBFBD>ֽ<EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʶ
}
}
if( j!=4 && length == 5 && PC_isConnected )
{
p = buffer;
for( j = 0; j < 4; j++ )
{
if( BufferPong[j] != *p++ )
{
break;
}
}
if( j == 4 )//<2F><>ȫƥ<C8AB><C6A5>pong
{
if( 0x01 == buffer[4] )
{
Ebyte_DEBUG_CommandEcho( ( uint8_t* )SimulatedCommandsWireless1, EBYTE_CMD_PACKAGE_LENGTH, PcEchoBuffer, &pcEchoLength );
}
else
{
Ebyte_DEBUG_CommandEcho( ( uint8_t* )SimulatedCommandsWireless2, EBYTE_CMD_PACKAGE_LENGTH, PcEchoBuffer, &pcEchoLength );
}
Ebyte_BSP_UartTransmit( PcEchoBuffer, pcEchoLength );
}
}
}
Ebyte_BSP_LedControl( BSP_LED_1, ON );
if( ! PC_isConnected )
{
DEBUGPRINT("\r\n Receive Data:");
Ebyte_BSP_UartTransmit ( buffer, length );
}
Ebyte_BSP_LedControl( BSP_LED_1, OFF );
}
/* <20><><EFBFBD><EFBFBD>: <20>쳣<EFBFBD><ECB3A3>ʱ */
else if ( state &= 0x0200 )
{
//To-do ʵ<><CAB5><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD>߼<EFBFBD>
}
/* <20><><EFBFBD><EFBFBD>: δ֪<CEB4><D6AA><EFBFBD><EFBFBD> */
else
{
/* <20><><EFBFBD><EFBFBD>״̬<D7B4><CCAC>ʶ<EFBFBD><CAB6><EFBFBD><EFBFBD>ȷ<EFBFBD><C8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2>
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1:SPIͨ<49>Ų<EFBFBD><C5B2><EFBFBD>ȷ 2:ģ<>鹩<EFBFBD>粻<EFBFBD><E7B2BB> */
while(1);
}
}

8
NSPE/WIFI_IOT/bsp/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.h Executable file
View File

@ -0,0 +1,8 @@
#ifndef _EBYTE_CALLBACK_H_
#define _EBYTE_CALLBACK_H_
#include "ebyte_port.h"
void Ebyte_Port_TransmitCallback( uint16e_t state );
void Ebyte_Port_ReceiveCallback( uint16e_t state ,uint8e_t *buffer, uint8e_t length);
#endif

34
NSPE/WIFI_IOT/bsp/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_conf.h Executable file
View File

@ -0,0 +1,34 @@
/**
**********************************************************************************
* @file ebyte_conf.h
* @brief EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-13
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
/*= !!!<21><><EFBFBD>ò<EFBFBD>Ʒ<EFBFBD>ͺ<EFBFBD> <20><>ѡ ============================================*/
#define EBYTE_E48_433M20S
//#define EBYTE_E48_900M20S
/*==================================================================*/
/* SPIͨ<49><CDA8> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CS(NSS)<29>ź<EFBFBD> 0:<3A><><EFBFBD><EFBFBD> 1:<3A><><EFBFBD><EFBFBD> */
#define EBYTE_PORT_SPI_CS_SOFTWARE 1
/* <20><><EFBFBD>μ<EFBFBD><CEBC><EFBFBD>ģ<EFBFBD>鷢<EFBFBD><E9B7A2>ʱ<EFBFBD><CAB1>״̬ 0:<3A>첽<EFBFBD>ж<EFBFBD>֪ͨ 1:ͬ<><CDAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define EBYTE_RF_TRANSMIT_CHECK_MODE 1

48
NSPE/WIFI_IOT/bsp/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.c Executable file
View File

@ -0,0 +1,48 @@
/**
**********************************************************************************
* @file ebyte_core.c
* @brief EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϲ<EFBFBD>API<50><49>װ<EFBFBD><D7B0> <20><><EFBFBD><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ײ<EFBFBD><D7B2>߼<EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-13
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "ebyte_core.h"
/* ָ<><D6B8> E48x <20>ײ<EFBFBD><D7B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#if defined(EBYTE_E48_433M20S)||defined(EBYTE_E48_900M20S)
const Ebyte_RF_t Ebyte_RF =
{
Ebyte_E48x_Init,
Ebyte_E48x_SendPayload,
Ebyte_E48x_SetSleep,
Ebyte_E48x_SetRx,
Ebyte_E48x_IntOrPollTask,
Ebyte_E48x_InterruptTrigger,
Ebyte_E48x_GetName,
Ebyte_E48x_GetDriverVersion
};
#else
/* ebyte_conf.h <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD>IJ<EFBFBD>Ʒ<EFBFBD>ͺŲ<CDBA><C5B2><EFBFBD>ȷ */
#error No product selected !
#endif

46
NSPE/WIFI_IOT/bsp/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.h Executable file
View File

@ -0,0 +1,46 @@
/**
**********************************************************************************
* @file ebyte_core.h
* @brief EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϲ<EFBFBD>API<50><49>װ<EFBFBD><D7B0> <20><><EFBFBD><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ײ<EFBFBD><D7B2>߼<EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-13
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include <stdint.h>
#include "ebyte_conf.h"
#if defined(EBYTE_E48_433M20S)||defined(EBYTE_E48_900M20S)
#include "ebyte_e48x.h"
#else
#error No product selected !
#endif
typedef struct
{
void ( *Init )( void );
void ( *Send )( uint8e_t *buffer, uint8e_t size , uint32e_t timeout);
void ( *EnterSleepMode )( uint8e_t command);
void ( *EnterReceiveMode )( uint32e_t timeout );
void ( *StartPollTask)( void );
void ( *InterruptTrigger)( void );
uint32e_t ( *GetName ) (void );
uint8e_t ( *GetDriverVersion ) (void );
}Ebyte_RF_t;
extern const Ebyte_RF_t Ebyte_RF;

97
NSPE/WIFI_IOT/bsp/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.c Executable file
View File

@ -0,0 +1,97 @@
/**
**********************************************************************************
* @file ebyte_port.h
* @brief EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD>ӿڲ<D3BF> <20>ɿͻ<C9BF><CDBB>Լ<EFBFBD><D4BC>ṩIO<49>ӿ<EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-13
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "ebyte_port.h"
/*= !!!<21><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨ͷ<CCA8>ļ<EFBFBD> =======================================*/
#include "board.h" //E15-EVB02 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#include "wrapper_os.h"
/*==================================================================*/
/* !
* @brief <20><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨SPI<50>ӿ<EFBFBD><D3BF>շ<EFBFBD><D5B7><EFBFBD><EFBFBD><EFBFBD>
*
* @param send EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 Byte
* @return SPI<50><49><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD> 1 Byte
* @note <20><>Ŀ<EFBFBD><C4BF>ƽ̨<C6BD><CCA8><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2>SPI_NSSʱ<53><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ebyte_conf.h<>ļ<EFBFBD> <20>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPI_CS(NSS)
* <20><>Ŀ<EFBFBD><C4BF>ƽ̨<C6BD><CCA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPI_NSSʱ<53><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ebyte_Port_SpiCsIoControl() <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĺ<EFBFBD><C4BA><EFBFBD>˵<EFBFBD><CBB5>
*/
uint8e_t Ebyte_Port_SpiTransmitAndReceivce( uint8e_t send )
{
uint8e_t result = 0;
/* !<21><><EFBFBD><EFBFBD><EFBFBD>ṩ: SPI<50>ӿ<EFBFBD> */
result = Ebyte_BSP_SpiTransAndRecv( send );
return result;
}
/* !
* @brief (<28><>ѡ)<29><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨SPI_CS(NSS)<29><><EFBFBD><EFBFBD>
*
* @param cmd EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD>ָ<EFBFBD><D6B8>
* @arg 0: <20><><EFBFBD><EFBFBD>CS(NSS)<29><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>ƽ<EFBFBD>߼<EFBFBD><DFBC>ź<EFBFBD> EBYTEģ<45><C4A3>SPI<50>ӿ<EFBFBD>Ϊ<EFBFBD>͵<EFBFBD>ƽѡ<C6BD><D1A1>
* @arg 1: <20><><EFBFBD><EFBFBD>CS(NSS)<29><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD>ƽ<EFBFBD>߼<EFBFBD><DFBC>ź<EFBFBD>
* @note <20><>Ŀ<EFBFBD><C4BF>ƽ̨<C6BD><CCA8><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2>SPI_NSSʱ<53><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> <20>˺<EFBFBD><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
* <20><>Ŀ<EFBFBD><C4BF>ƽ̨<C6BD><CCA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPI_NSSʱ<53><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ô˺<C3B4><CBBA><EFBFBD>
*/
void Ebyte_Port_SpiCsIoControl( uint8e_t cmd )
{
if ( cmd == 1 )
{
/* !<21><>ѡ: SPI CS<43><53><EFBFBD><EFBFBD> <20>ߵ<EFBFBD>ƽδѡ<CEB4><D1A1> */
Ebyte_BSP_RfSpiUnselected();
}
else
{
/* !<21><>ѡ: SPI CS<43><53><EFBFBD><EFBFBD> <20>͵<EFBFBD>ƽѡ<C6BD><D1A1> */
Ebyte_BSP_RfSpiSelected( );
}
}
/* !
* @brief <20><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨<C6BD><CCA8>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
*
* @param time <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
* @note <20><>ע<EFBFBD><D7A2>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ô˺<C3B4><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD>Ӱ<EFBFBD>쵽<EFBFBD>˺<EFBFBD><CBBA><EFBFBD>
*/
void Ebyte_Port_DelayMs( uint16e_t time )
{
/* !<21><><EFBFBD><EFBFBD><EFBFBD>ṩ: <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> */
sys_ms_sleep(time);
}
/* !
* @brief <20><><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>Ӳ<EFBFBD><D3B2>ƽ̨<C6BD><CCA8>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
*
* @param time <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
* @note <20><>ע<EFBFBD><D7A2>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ô˺<C3B4><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD>Ӱ<EFBFBD>쵽<EFBFBD>˺<EFBFBD><CBBA><EFBFBD>
*/
void Ebyte_Port_DelayUs( uint16e_t time )
{
/* !<21><><EFBFBD><EFBFBD><EFBFBD>ṩ: <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> */
sys_us_delay(time);
}

33
NSPE/WIFI_IOT/bsp/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.h Executable file
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#ifndef __EBYTE_PORT_H
#define __EBYTE_PORT_H
#include <stdio.h>
#include "ebyte_conf.h"
//#include "stm8l15x.h"
//typedef unsigned char uint8e_t;
//typedef unsigned short uint16e_t;
//typedef unsigned long uint32e_t;
//
//typedef signed char int8e_t;
//typedef signed short int16e_t;
//typedef signed long int32e_t;
#define uint8e_t uint8_t
#define uint16e_t uint16_t
#define uint32e_t uint32_t
#define int8e_t int8_t
#define int16e_t int16_t
#define int32e_t int32_t
void Ebyte_Port_RstIoControl( uint8e_t cmd );
void Ebyte_Port_TxenIoControl( uint8e_t cmd );
void Ebyte_Port_RxenIoControl( uint8e_t cmd );
void Ebyte_Port_DelayMs( uint16e_t time );
void Ebyte_Port_DelayUs( uint16e_t time );
void Ebyte_Port_SpiCsIoControl( uint8e_t cmd );
uint8e_t Ebyte_Port_BusyIoRead( void );
uint8e_t Ebyte_Port_SpiTransmitAndReceivce( uint8e_t send );
#endif /* __EBYTE_PORT_H */

6
NSPE/WIFI_IOT/bsp/drivers/CMT2310/0_Project/Uart_PingPong/ebyte_e48.h Normal file
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#ifndef __EBYTE_E48_H__
#define __EBYTE_E48_H__
int ebyte_main( void );
#endif /* __EBYTE_E48_H__ */

211
NSPE/WIFI_IOT/bsp/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.c Executable file
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/**
******************************************************************************
* @file stm8l15x_it.c
* @author MCD Application Team
* @version V1.0.0
* @date 09/28/2010
* @brief Main Interrupt Service Routines.
* This file provides template for all peripherals interrupt service routine.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32_it.h"
#include "ebyte_kfifo.h"
#include "ebyte_core.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
static uint8_t Uart_isInRecvState = 0;
static uint8_t Uart_isContinuousRecv = 0;
static uint32_t Uart_TickCounter = 0;
extern uint8_t Uart_isRecvReady;
static uint16_t Button1_TickCounter = 0;
static uint16_t Button2_TickCounter = 0;
extern Ebyte_FIFO_t hfifo;
extern uint8_t FIFO_isTimeCheckReady;
static uint32_t FIFO_TickCounter = 0;
/* Private function prototypes -----------------------------------------------*/
void IT_Timer_ButtonCheck(void);
void IT_Timer_UartCheck(void);
/* Private functions ---------------------------------------------------------*/
/** @addtogroup IT_Functions
* @{
*/
#ifdef _COSMIC_
/**
* @brief Dummy interrupt routine
* @par Parameters:
* None
* @retval
* None
*/
INTERRUPT_HANDLER(NonHandledInterrupt, 0)
{
/* In order to detect unexpected events during development,
it is recommended to set a breakpoint on the following instruction.
*/
}
#endif
/*!
\brief This function handles TIMER2 interrupt request.
\param[in] none
\param[out] none
\retval none
*/
void __TIMER2_IRQHandler(void)
{
if(SET == timer_interrupt_flag_get(TIMER2, TIMER_INT_UP)){
/* clear channel 0 interrupt bit */
timer_interrupt_flag_clear(TIMER2, TIMER_INT_UP);
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
IT_Timer_ButtonCheck();
/* <20><><EFBFBD><EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD> */
// IT_Timer_UartCheck();
/* <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
Ebyte_BSP_TimerDecrement();
}
}
#if 0 // GY3513
/**
* @brief USART1 RX / Timer5 Capture/Compare Interrupt routine.
* @param None
* @retval None
*/
INTERRUPT_HANDLER(USART1_RX_TIM5_CC_IRQHandler, 28)
{
/* <20><>֡<EFBFBD>ж<EFBFBD> ״̬<D7B4><CCAC> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʱ 10ms<6D><73>δ<EFBFBD>յ<EFBFBD><D5B5><EFBFBD>һ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>֡ */
if( !Uart_isInRecvState )
{
Uart_isInRecvState = 1;
}
Uart_isContinuousRecv = 1;
/* <20><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 Byte */
uint8_t temp = USART_ReceiveData8(USART1) ;
/* д<>뻺<EFBFBD><EBBBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 Byte */
Ebyte_FIFO_Write( &hfifo, &temp, 1 );
/* <20><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>ʶ */
USART_ClearITPendingBit( USART1, USART_IT_RXNE );
}
/* !
* @brief <20><>ʱ<EFBFBD><CAB1><EFBFBD>ж<EFBFBD> ״̬<D7B4><CCAC> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
void IT_Timer_ButtonCheck(void)
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if( !Ebyte_BSP_ReadButton( BSP_BUTTON_1 ) )
{
Button1_TickCounter++;
}
else
{
if( Button1_TickCounter > 1000 ) // 1<><31> <20><><EFBFBD><EFBFBD>
{
Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_1_LONG);
}
else if( Button1_TickCounter > 50 ) //50<35><30><EFBFBD><EFBFBD> <20>̰<EFBFBD>
{
Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_1_SHORT);
}
else {} //50<35><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ϊ<EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
Button1_TickCounter=0;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if( !Ebyte_BSP_ReadButton( BSP_BUTTON_2 ) )
{
Button2_TickCounter++;
}
else
{
if( Button2_TickCounter > 1000 ) // 1<><31> <20><><EFBFBD><EFBFBD>
{
Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_2_LONG);
}
else if( Button2_TickCounter > 50 ) //50<35><30><EFBFBD><EFBFBD> <20>̰<EFBFBD>
{
Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_2_SHORT);
}
else {} //50<35><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ϊ<EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
Button2_TickCounter=0;
}
}
/* !
* @brief <20><>ʱ<EFBFBD><CAB1><EFBFBD>ж<EFBFBD> ״̬<D7B4><CCAC> <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>֡
*/
void IT_Timer_UartCheck(void)
{
/* <20><><EFBFBD>ڽ<EFBFBD><DABD>յ<EFBFBD><D5B5><EFBFBD>һ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD>Ϳ<EFBFBD>ʼ<EFBFBD><CABC>ʱ */
if( Uart_isInRecvState )
{
Uart_TickCounter++;
/* <20><><EFBFBD><EFBFBD>10msû<73>н<EFBFBD><D0BD>յ<EFBFBD><D5B5>ڶ<EFBFBD><DAB6>ֽ<EFBFBD> <20><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>֡ */
if( Uart_TickCounter > 10 )
{
/* ֪ͨ<CDA8><D6AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD>һ֡ */
Uart_isRecvReady ++;
/* ֹͣ<CDA3><D6B9>ʱ */
Uart_isInRecvState = 0;
Uart_TickCounter = 0;
}
/* <20><>λFIFO<46><4F>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> */
FIFO_TickCounter = 0;
}
else
{
/* <20><><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD>û<EFBFBD>н<EFBFBD><D0BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡ 500ms<6D><73><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>FIFO<46>е<EFBFBD><D0B5><EFBFBD><EFBFBD><EFBFBD> */
if( (!Uart_isInRecvState) && Uart_isRecvReady )
{
FIFO_TickCounter++;
if( FIFO_TickCounter > 500)
{
FIFO_isTimeCheckReady=1;
Uart_isRecvReady = 0;
FIFO_TickCounter = 0;
}
}
}
/* <20><><EFBFBD><EFBFBD>ÿ<EFBFBD><C3BF><EFBFBD>յ<EFBFBD>1<EFBFBD><31><EFBFBD>ֽھ<D6BD><DABE><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD> */
if( Uart_isInRecvState && Uart_isContinuousRecv )
{
Uart_TickCounter = 0;
Uart_isContinuousRecv = 0;
}
}
#endif // GY3513
/**
* @}
*/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

38
NSPE/WIFI_IOT/bsp/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.h Executable file
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/**
******************************************************************************
* @file stm8l15x_it.h
* @author MCD Application Team
* @version V1.0.0
* @date 09/28/2010
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_IT_H
#define __STM8L15x_IT_H
/* Includes ------------------------------------------------------------------*/
//#include "stm8l15x.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void __TIMER2_IRQHandler(void);
#endif /* __STM8L15x_IT_H */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

227
NSPE/WIFI_IOT/bsp/drivers/CMT2310/0_Project/Uart_PingPong/main.c Executable file
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/**
**********************************************************************************
* @file main.c
* @brief E15-EVB02 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̼<EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͸<EFBFBD><CDB8>ʾ<EFBFBD><CABE> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author yxw
* @date 2023-12-25
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "ebyte_core.h"
#include "ebyte_kfifo.h"
#include "ebyte_debug.h"
#include "wrapper_os.h"
#include "debug_print.h"
void Task_Transmit( void );
void Task_Button( void );
/* <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ݴ洢<DDB4><E6B4A2><EFBFBD><EFBFBD> */
Ebyte_FIFO_t hfifo;
/* <20><><EFBFBD><EFBFBD> ֡<><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD>ʶ */
uint8_t Uart_isRecvReady = 0;
/* <20><><EFBFBD><EFBFBD> FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʶ */
uint8_t FIFO_isTimeCheckReady = 0;
/* <20><><EFBFBD><EFBFBD> <20>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
uint8_t TxBuffer[64] = {0};
uint8_t RxBuffer[64] = {0};
uint8_t PcEchoBuffer[20] = {0};
uint8_t BufferPing[5] = {'p', 'i', 'n', 'g'};
uint8_t BufferPong[5] = {'p', 'o', 'n', 'g'};
/* <20><><EFBFBD><EFBFBD> FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʶ */
uint8_t Callback_isPingCheckReady = 0;
/* <20>Լ<EFBFBD>ģʽ <20><>ʶ */
uint8_t PC_isConnected = 0;
static BSP_BTN_EVENT_t BTN_Event;
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
int ebyte_main( void )
{
/* <20><><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>Դ <20><>ʼ<EFBFBD><CABC> */
Ebyte_BSP_Init();
/* (<28><>ѡ) <20><><EFBFBD><EFBFBD><EFBFBD>жϽ<D0B6><CFBD><EFBFBD>FIFO <20>ɸ<EFBFBD><C9B8><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>д<EFBFBD><D0B4><EFBFBD> */
Ebyte_FIFO_Init( &hfifo, EBYTE_FIFO_SIZE );
/* EBYTE <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC> */
Ebyte_RF.Init();
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
Ebyte_RF.EnterReceiveMode( 0 );
/* MCU <20><>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD> */
Ebyte_BSP_GlobalIntEnable();
DEBUGPRINT( "Start PingPong.....\r\n" );
DEBUGPRINT( "Please push button1 or button2.....\r\n" );
while( 1 ) {
/* <20><><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD>Ӧ */
Task_Button();
/* <20><><EFBFBD><EFBFBD>:<3A><><EFBFBD>⴮<EFBFBD><E2B4AE><EFBFBD><EFBFBD><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD>߷<EFBFBD><DFB7><EFBFBD> <20>ͻ<EFBFBD><CDBB>밴<EFBFBD><EBB0B4><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD> */
Task_Transmit();
/* <20><><EFBFBD><EFBFBD>:EBYTE<54><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>޸<EFBFBD> */
Ebyte_RF.StartPollTask();
sys_ms_sleep(100);
}
}
/* !
* @brief <20><>ѯ<EFBFBD><D1AF><EFBFBD><EFBFBD> <20><><EFBFBD>ڽ<EFBFBD><DABD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>ģ<EFBFBD>鷢<EFBFBD><E9B7A2>
*
* @note <20><><EFBFBD><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>͵<EFBFBD><CDB5><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߴ<EFBFBD><DFB4>俪<EFBFBD><E4BFAA>
* ע<><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ģʽ<C4A3>л<EFBFBD><D0BB><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¿<EFBFBD><C2BF>Դ<EFBFBD><D4B4>ڽ<EFBFBD><DABD><EFBFBD>/<2F><><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ: <20><><EFBFBD><EFBFBD>ģʽ-><3E><><EFBFBD><EFBFBD>ģʽ-><3E><><EFBFBD><EFBFBD>ģʽ
*/
void Task_Transmit( void )
{
uint16_t length = 0;
uint8_t pcEchoLength = 0;
uint8_t pongLength = 0;
/* <20>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>ߴ<EFBFBD><DFB4><EFBFBD> (<28><><EFBFBD>Դ<EFBFBD><D4B4>ڽ<EFBFBD><DABD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD>) */
Ebyte_FIFO_GetDataLength( &hfifo, &length );
/* <20>漰<EFBFBD><E6BCB0><EFBFBD>첽<EFBFBD>ж<EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE> <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
1; <20><><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ѿ<EFBFBD><D1BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD>֡<EFBFBD><D6A1><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߷<EFBFBD><DFB7><EFBFBD>( <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>֡<EFBFBD><D6A1>ʽ,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ᵼ<EFBFBD><E1B5BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ճ<EFBFBD><D5B3> <20><><EFBFBD><EFBFBD><EFBFBD>ݾ<EFBFBD><DDBE><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD>п<EFBFBD><D0BF><EFBFBD>֡<EFBFBD>ж<EFBFBD> )
2: <20><><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD><DDB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ѿ<EFBFBD><D1BE>˳<EFBFBD><CBB3>˽<EFBFBD><CBBD><EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ( <20>ᵼ<EFBFBD><E1B5BC>FIFOʣ<4F><CAA3>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߷<EFBFBD><DFB7><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ݾ<EFBFBD><DDBE><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD>п<EFBFBD><D0BF><EFBFBD>֡<EFBFBD>ж<EFBFBD> )*/
if( ( length != 0 && Uart_isRecvReady ) || ( length != 0 && FIFO_isTimeCheckReady ) )
{
Ebyte_BSP_LedControl( BSP_LED_1, ON );
/* <20><>ȡFIFO <20><><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD>TxBuffer */
Ebyte_FIFO_Read( &hfifo, TxBuffer, length );
/* PC<50><43><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>Ӧ */
if( Ebyte_DEBUG_CommandEcho( TxBuffer,length, PcEchoBuffer, &pcEchoLength ) )
{
Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength);
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͸<EFBFBD><CDB8> */
else
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD>з<EFBFBD><D0B7><EFBFBD> */
Ebyte_RF.Send( TxBuffer, length, 0 );
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
Ebyte_RF.EnterReceiveMode( 0 );
}
/* ÿ<><C3BF><EFBFBD><EFBFBD>һ֡<D2BB>ͼ<EFBFBD><CDBC><EFBFBD>֡<EFBFBD><D6A1><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>жϿ<D0B6><CFBF><EFBFBD><EFBFBD>Ѿ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>˶<EFBFBD>֡ */
if( Uart_isRecvReady ) Uart_isRecvReady --;
if( FIFO_isTimeCheckReady ) FIFO_isTimeCheckReady = 0;
Ebyte_BSP_LedControl( BSP_LED_1, OFF );
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɻص<C9BB><D8B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>⵽<EFBFBD><E2B5BD> ping <20><><EFBFBD><EFBFBD> <20>ظ<EFBFBD> pong */
if( Callback_isPingCheckReady )
{
if( PC_isConnected )
{
pongLength = 5;
}else{
DEBUGPRINT( "\r\n Echo : pong \r\n" );
pongLength = 4;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD>з<EFBFBD><D0B7><EFBFBD> */
Ebyte_RF.Send( BufferPong, pongLength, 0 );
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
Ebyte_RF.EnterReceiveMode( 0 );
Callback_isPingCheckReady = 0;
}
}
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD>Ӧ
*/
void Task_Button( void )
{
uint8_t pcEchoLength = 0;
uint8_t pingLength = 0;
if( ! Ebyte_BTN_FIFO_Pop( &BSP_BTN_FIFO, &BTN_Event ) )
{
switch( BTN_Event )
{
/* <20><><EFBFBD><EFBFBD>1 <20>̰<EFBFBD> */
case BTN_1_SHORT:
Ebyte_BSP_LedControl( BSP_LED_1, ON );
if( PC_isConnected )
{
/* ֪ͨPC */
Ebyte_DEBUG_CommandEcho( (uint8_t*)SimulatedCommandsButton1, EBYTE_CMD_PACKAGE_LENGTH , PcEchoBuffer, &pcEchoLength );
Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength);
BufferPing[4] = 0x01;
pingLength = 5;
}else
{
DEBUGPRINT( "\r\n Send Command : ping \r\n" );
pingLength = 4;
}
/* <20><><EFBFBD><EFBFBD> ping */
Ebyte_RF.Send( BufferPing, pingLength, 0 );
Ebyte_RF.EnterReceiveMode( 0 );
Ebyte_BSP_LedControl( BSP_LED_1, OFF );
break;
/* <20><><EFBFBD><EFBFBD>1 <20><><EFBFBD><EFBFBD> */
case BTN_1_LONG:
Ebyte_BSP_LedControl( BSP_LED_1, TOGGLE );
break;
/* <20><><EFBFBD><EFBFBD>2 <20>̰<EFBFBD> */
case BTN_2_SHORT:
Ebyte_BSP_LedControl( BSP_LED_2, ON );
if( PC_isConnected )
{
/* ֪ͨPC */
Ebyte_DEBUG_CommandEcho( (uint8_t*)SimulatedCommandsButton2, EBYTE_CMD_PACKAGE_LENGTH , PcEchoBuffer, &pcEchoLength );
Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength);
BufferPing[4] = 0x02;
pingLength = 5;
}else
{
DEBUGPRINT( "\r\n Send Command : ping \r\n" );
pingLength = 4;
}
/* <20><><EFBFBD><EFBFBD> ping */
Ebyte_RF.Send( BufferPing, pingLength, 0 );
Ebyte_RF.EnterReceiveMode( 0 );
Ebyte_BSP_LedControl( BSP_LED_2, OFF );
break;
/* <20><><EFBFBD><EFBFBD>2 <20><><EFBFBD><EFBFBD> */
case BTN_2_LONG:
Ebyte_BSP_LedControl( BSP_LED_2, TOGGLE );
break;
default :
break;
}
}
}

107
NSPE/WIFI_IOT/bsp/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.c Executable file
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/* Includes ------------------------------------------------------------------*/
#include "ebyte_kfifo.h"
uint8_t Ebyte_FIFO_Init( Ebyte_FIFO_t *fifo, uint16_t size )
{
uint8_t result = 0;
if( ( size & ( size - 1 ) ) != 0 ) //Warning ! Size must be 2^n ! Please view linux kfifo
{
result = 1;
}
fifo->size = size;
fifo->in = 0;
fifo->out = 0;
return result;
}
uint8_t Ebyte_FIFO_Write( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length )
{
uint8_t result = 0;
uint32_t i, j;
uint16_t endLength, orgLength;
uint8_t *pFifoBuffer;
orgLength = length;
/* calculate the length of data that can be written */
length = MIN( length, fifo->size - fifo->in + fifo->out );
/* first put the data starting from fifo->in to buffer end */
endLength = MIN( length, fifo->size - ( fifo->in & ( fifo->size - 1 ) ) );
pFifoBuffer = fifo->buffer + ( fifo->in & ( fifo->size - 1 ) );
for( i = 0; i < endLength; i++ )
{
*( pFifoBuffer++ ) = *( pData++ );
}
/* then put the rest (if any) at the beginning of the buffer */
j = length - endLength;
if ( j > 0 )
{
pFifoBuffer = fifo->buffer;
for( i = 0; i < j; i++ )
{
*( pFifoBuffer++ ) = *( pData++ );
}
}
fifo->in += length;
if( length < orgLength )
{
result = 1; // Means fifo is full , some data can not be written in
}
return result;
}
uint8_t Ebyte_FIFO_Read( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length )
{
uint8_t result = 0;
uint16_t i, j;
uint16_t endLength, orgLength;
uint8_t *pFifoBuffer;
orgLength = length;
length = MIN( length, fifo->in - fifo->out );
/* first get the data from fifo->out until the end of the buffer */
endLength = MIN( length, fifo->size - ( fifo->out & ( fifo->size - 1 ) ) );
pFifoBuffer = fifo->buffer + ( fifo->out & ( fifo->size - 1 ) );
for( i = 0; i < endLength; i++ )
{
*( pData++ ) = *( pFifoBuffer++ );
}
/* then get the rest (if any) from the beginning of the buffer */
j = length - endLength;
if ( j > 0 )
{
pFifoBuffer = fifo->buffer;
for( i = 0; i < j; i++ )
{
*( pData++ ) = *( pFifoBuffer++ ) ;
}
}
fifo->out += length;
if( length < orgLength )
{
result = 1; // not enough data
}
return result;
}
uint8_t Ebyte_FIFO_GetDataLength( Ebyte_FIFO_t *fifo, uint16_t *pLength )
{
uint8_t result = 0;
*pLength = ( fifo->in - fifo->out );
return result;
}
uint8_t Ebyte_FIFO_Clear( Ebyte_FIFO_t *fifo )
{
uint8_t result = 0;
fifo->in = 0;
fifo->out = 0;
return result;
}

19
NSPE/WIFI_IOT/bsp/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.h Executable file
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#include "board.h"
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#define EBYTE_FIFO_SIZE 64 // Warning ! Size must be 2^n ! Please view linux kfifo
typedef struct
{
uint32_t in;
uint32_t out;
uint32_t size;
uint8_t buffer[EBYTE_FIFO_SIZE];
} Ebyte_FIFO_t;
uint8_t Ebyte_FIFO_Init( Ebyte_FIFO_t *fifo, uint16_t size );
uint8_t Ebyte_FIFO_Write( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length );
uint8_t Ebyte_FIFO_GetDataLength( Ebyte_FIFO_t *fifo, uint16_t *pLength );
uint8_t Ebyte_FIFO_Read( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length );
uint8_t Ebyte_FIFO_Clear( Ebyte_FIFO_t *fifo );

122
NSPE/WIFI_IOT/bsp/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.c Executable file
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/**
**********************************************************************************
* @file board.c
* @brief E15-EVB02 <20><><EFBFBD><EFBFBD>ģʽ
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-20
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "ebyte_core.h"
#include "ebyte_debug.h"
extern unsigned char PC_isConnected;
const unsigned char SimulatedCommandsButton1[5] = { EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_TEST_BUTTON,
0x01
};
const unsigned char SimulatedCommandsButton2[5] = { EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_TEST_BUTTON,
0x02
};
const unsigned char SimulatedCommandsWireless1[5] = { EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_TEST_WIRELESS,
0x01
};
const unsigned char SimulatedCommandsWireless2[5] = { EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_PACKAGE_START,
EBYTE_CMD_TEST_WIRELESS,
0x02
};
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* @param rxBuffer <20><><EFBFBD>ܺ<EFBFBD><DCBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>
* @param length rxBuffer<65><72><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
* @param txBuffer <20><>Ӧ<EFBFBD><D3A6><EFBFBD>ݰ<EFBFBD> <20><><EFBFBD><EFBFBD>>10
* @param tLength <20><>Ӧ<EFBFBD><D3A6><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>
* @return 0:δ<><CEB4><EFBFBD>⵽<EFBFBD><E2B5BD><EFBFBD><EFBFBD> 1:<3A><><EFBFBD>⵽<EFBFBD><E2B5BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
unsigned char Ebyte_DEBUG_CommandEcho( unsigned char *rxBuffer , unsigned char length, unsigned char *txBuffer, unsigned char *tLength)
{
unsigned char result = 0;
unsigned char *p;
unsigned char tmp,version;
unsigned long name;
/* ֻ<><D6BB><EFBFBD>Ĺ̶<C4B9><CCB6><EFBFBD><EFBFBD><EFBFBD>Ϊ10<31><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡ <20><><EFBFBD><EFBFBD>ʱ<EFBFBD>䳤 ճ<><D5B3><EFBFBD><EFBFBD><EFBFBD>ʺ<EFBFBD>С*/
if( length == EBYTE_CMD_PACKAGE_LENGTH )
{
p = rxBuffer;
if( *p++== EBYTE_CMD_PACKAGE_START && *p++== EBYTE_CMD_PACKAGE_START && *p++== EBYTE_CMD_PACKAGE_START)
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>ֽ<EFBFBD> ָ<><D6B8><EFBFBD><EFBFBD> */
tmp = *p;
switch( tmp )
{
case EBYTE_CMD_TEST_MODE:
name = Ebyte_RF.GetName();
version = Ebyte_RF.GetDriverVersion();
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_TEST_MODE;
*txBuffer++ = (unsigned char)(name>>24);
*txBuffer++ = (unsigned char)(name>>16);
*txBuffer++ = (unsigned char)(name>>8);
*txBuffer++ = (unsigned char)(name);
*txBuffer++ = version;
*tLength = EBYTE_CMD_PACKAGE_LENGTH;
PC_isConnected = 1; //ģʽ<C4A3><CABD><EFBFBD><EFBFBD>
break;
case EBYTE_CMD_TEST_BUTTON:
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_TEST_BUTTON;
*txBuffer = *++p;
*tLength = EBYTE_CMD_PACKAGE_LENGTH;
break;
case EBYTE_CMD_TEST_WIRELESS:
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_PACKAGE_START;
*txBuffer++ = EBYTE_CMD_TEST_WIRELESS;
*txBuffer = *++p;
*tLength = EBYTE_CMD_PACKAGE_LENGTH;
break;
}
result = 1;
}
}
return result;
}

14
NSPE/WIFI_IOT/bsp/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.h Executable file
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#define EBYTE_CMD_PACKAGE_START 0xC5
#define EBYTE_CMD_PACKAGE_LENGTH 0x0A
#define EBYTE_CMD_TEST_MODE 0x01
#define EBYTE_CMD_TEST_BUTTON 0x02
#define EBYTE_CMD_TEST_WIRELESS 0x03
extern const unsigned char SimulatedCommandsButton1[5];
extern const unsigned char SimulatedCommandsButton2[5];
extern const unsigned char SimulatedCommandsWireless1[5];
extern const unsigned char SimulatedCommandsWireless2[5];
unsigned char Ebyte_DEBUG_CommandEcho( unsigned char *rxBuffer , unsigned char length, unsigned char *txBuffer, unsigned char *tLength);

340
NSPE/WIFI_IOT/bsp/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.c Executable file
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/**
**********************************************************************************
* @file board.c
* @brief E15-EVB02 <20>弶<EFBFBD><E5BCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-06
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "board.h"
#include "ebyte_port.h"
#include "ebyte_conf.h"
#include "gd32w51x_gpio.h"
#include "platform_def.h"
BSP_BTN_FIFO_t BSP_BTN_FIFO;
/*!< @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> <20><><EFBFBD>ڶ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ж<EFBFBD> <20>ݼ<EFBFBD> */
volatile uint32_t Ebyte_TimerDelayCounter = 0;
/* !
* @brief <20>ڲ<EFBFBD>ʱ<EFBFBD>ӳ<EFBFBD>ʼ<EFBFBD><CABC>
*/
void Ebyte_BSP_HSI_Init(void)
{
// /* <20>ڲ<EFBFBD> 16M HSI ʱ<><CAB1> */
// CLK_SYSCLKSourceConfig( CLK_SYSCLKSource_HSI );
//
// /* 1<><31>Ƶ 16M/1 */
// CLK_SYSCLKDivConfig( CLK_SYSCLKDiv_1 );
}
void Ebyte_BSP_E48xGPIO_Init(void)
{
rcu_periph_clock_enable(BSP_GPIO_RCU_E48_GPIO);
gpio_mode_set( BSP_GPIO_PORT_E48_GP0, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_GP0);
gpio_mode_set( BSP_GPIO_PORT_E48_NIRQ, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_NIRQ);
gpio_mode_set( BSP_GPIO_PORT_E48_GP3, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_GP3);
gpio_mode_set( BSP_GPIO_PORT_E48_GP4, GPIO_MODE_INPUT, GPIO_PUPD_NONE, BSP_GPIO_PIN_E48_GP4);
gpio_mode_set( BSP_GPIO_PORT_E48_GP5, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_GP5);
}
/* !
* @brief <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO
*
* @note Ŀ<><C4BF>Ӳ<EFBFBD><D3B2>: EBYTE E15-EVB02
*/
void Ebyte_BSP_GPIO_Init(void)
{
/* <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>״̬<D7B4><CCAC><EFBFBD><EFBFBD> */
Ebyte_BSP_E48xGPIO_Init();
/* LED */
rcu_periph_clock_enable(BSP_GPIO_RCU_E48_LED);
gpio_mode_set( BSP_GPIO_PORT_LED_1, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_LED_1 );
gpio_mode_set( BSP_GPIO_PORT_LED_2, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_LED_2 );
gpio_output_options_set(BSP_GPIO_PORT_LED_1, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, BSP_GPIO_PIN_LED_1);
gpio_output_options_set(BSP_GPIO_PORT_LED_2, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, BSP_GPIO_PIN_LED_2);
/* Button */
rcu_periph_clock_enable(BSP_GPIO_RCU_E48_BUTTON);
gpio_mode_set( BSP_GPIO_PORT_BUTTON_1, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_BUTTON_1);
// GPIO_Init( BSP_GPIO_PORT_BUTTON_2, BSP_GPIO_PIN_BUTTON_2, GPIO_Mode_In_PU_No_IT );
}
/* !
* @brief ͨ<>Ŵ<EFBFBD><C5B4>ڳ<EFBFBD>ʼ<EFBFBD><CABC>
*
* @note <20><>ע<EFBFBD>⣬<EFBFBD><E2A3AC>ͬ<EFBFBD><CDAC>MCU<43><55><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD>ӳ<EFBFBD><D3B3>
*/
void Ebyte_BSP_UART_Init( void )
{
// /* ʱ<><CAB1> */
// CLK_PeripheralClockConfig( BSP_USER_UART_CLOCK, ENABLE);
//
// /* GPIO */
// GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_UART_TX, BSP_GPIO_PIN_UART_TX, ENABLE );
// GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_UART_RX, BSP_GPIO_PIN_UART_RX, ENABLE );
//
// /* <20>˿<EFBFBD><CBBF><EFBFBD>ӳ<EFBFBD><D3B3> */
// SYSCFG_REMAPPinConfig( REMAP_Pin_USART1TxRxPortA, ENABLE );
//
// /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> E15-EVB02Ĭ<32>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD>9600 8N1 */
// USART_Init( BSP_USER_UART, BSP_USER_UART_BAUDRATE, USART_WordLength_8b, USART_StopBits_1, BSP_USER_UART_PARITY, (USART_Mode_TypeDef)(USART_Mode_Rx | USART_Mode_Tx ));//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>պͷ<D5BA><CDB7><EFBFBD>
//
// /* <20>򿪽<EFBFBD><F2BFAABD><EFBFBD><EFBFBD>ж<EFBFBD> */;
// USART_ITConfig( BSP_USER_UART, USART_IT_RXNE, ENABLE );
//
// /* <20><><EFBFBD><EFBFBD> ʹ<><CAB9> */
// USART_Cmd( BSP_USER_UART, ENABLE);
}
void Ebyte_BSP_ThreeLinesSPI_Init()
{
/* <20>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD>E49 GPIO<49><4F>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD> */
}
/* !
* @brief <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>ͨ<EFBFBD><CDA8>SPI<50>ӿڳ<D3BF>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
void Ebyte_BSP_SPI_Init( void )
{
spi_parameter_struct spi_init_struct;
/* ʱ<><CAB1> */
rcu_periph_clock_enable(BSP_RF_SPI_CLOCK);
rcu_periph_clock_enable(BSP_GPIO_RCU_E48_SPI);
/* SPI1 GPIO config: SCK/PB13, MISO/PB14, MOSI/PB15 */
gpio_af_set(BSP_GPIO_PORT_SPI, GPIO_AF_5, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_mode_set(BSP_GPIO_PORT_SPI, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_output_options_set(BSP_GPIO_PORT_SPI, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
/* SPI0_NSS */
gpio_mode_set(BSP_GPIO_PORT_SPI, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_SPI_NSS); //Ƭѡ CS
gpio_output_options_set(BSP_GPIO_PORT_SPI, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, BSP_GPIO_PIN_SPI_NSS);
// GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_SPI_SCK, BSP_GPIO_PIN_SPI_MOSI | BSP_GPIO_PIN_SPI_MISO | BSP_GPIO_PIN_SPI_SCK, ENABLE); // MOSI MISO SCK
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
spi_init_struct.device_mode = SPI_MASTER; //<2F><><EFBFBD><EFBFBD>ģʽ
spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; // Mode0 {CPOL=0, CPHA=0}
spi_init_struct.nss = SPI_NSS_SOFT; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƴӻ<C6B4>CSƬѡ
spi_init_struct.prescale = SPI_PSC_8; //16M/2 SCK<43><4B><EFBFBD><EFBFBD>
spi_init_struct.endian = SPI_ENDIAN_MSB; //<2F>Ӹ<EFBFBD>λ<EFBFBD><CEBB>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
spi_init(BSP_RF_SPI, &spi_init_struct);
/* ʹ<><CAB9> */
/* SPI enable */
spi_enable(BSP_RF_SPI);
}
/* !
* @brief RFģ<46><C4A3>SPIͨ<49><CDA8><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* @param data <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @return <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @note stm8l SPI<50>⺯<EFBFBD><E2BAAF><EFBFBD>е<EFBFBD>SPI_SendData()/SPI_ReceiveData() <20><><EFBFBD><EFBFBD>ֱ<EFBFBD><D6B1>ʹ<EFBFBD><CAB9>
*/
uint8_t Ebyte_BSP_SpiTransAndRecv( uint8_t data )
{
while(RESET == spi_i2s_flag_get(BSP_RF_SPI, SPI_FLAG_TBE));
spi_i2s_data_transmit(BSP_RF_SPI, data);
while(RESET == spi_i2s_flag_get(BSP_RF_SPI, SPI_FLAG_RBNE));
return spi_i2s_data_receive(BSP_RF_SPI);
// BSP_RF_SPI->DR = data;
// while ((BSP_RF_SPI->SR & SPI_FLAG_TXE) == RESET);
//
// while ((BSP_RF_SPI->SR & SPI_FLAG_RXNE) == RESET);
// return BSP_RF_SPI->DR;
}
/* !
* @brief <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>
*
* @note ʹ<><CAB9><EFBFBD><EFBFBD>TIM3<4D><33><EFBFBD><EFBFBD>1ms<6D><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
* TIM3<4D><33><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ΪHSI 16MHz, 128<32><38>Ƶ<EFBFBD><C6B5>Ϊ 16 MHz / 128 = 125 000 Hz
* Ŀ<>궨ʱ1ms <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڼ<EFBFBD>Ϊ ( 0.001 x 125000 - 1) = 124
*/
void Ebyte_BSP_TIMER_Init( void )
{
timer_parameter_struct timer_initpara;
/**
TIMER2 Configuration:
TIMER2CLK = SystemCoreClock/180 = 1MHz.
TIMER2 configuration is timing mode, and the timing is 1ms(1000/1 = 1ms).
*/
/* enable the peripherals clock */
rcu_timer_clock_prescaler_config(RCU_TIMER_PSC_MUL4);
rcu_periph_clock_enable(BSP_RF_TIMER_RCU);
/* deinit a TIMER */
timer_deinit(BSP_RF_TIMER);
/* initialize TIMER init parameter struct */
timer_struct_para_init(&timer_initpara);
/* TIMER2 configuration */
timer_initpara.prescaler = 179;
timer_initpara.alignedmode = TIMER_COUNTER_EDGE;
timer_initpara.counterdirection = TIMER_COUNTER_UP;
timer_initpara.period = 1000;
timer_initpara.clockdivision = TIMER_CKDIV_DIV1;
timer_init(BSP_RF_TIMER, &timer_initpara);
/* clear interrupt bit */
timer_interrupt_flag_clear(BSP_RF_TIMER, TIMER_INT_FLAG_UP);
/* enable the TIMER interrupt */
timer_interrupt_enable(BSP_RF_TIMER, TIMER_INT_UP);
/* enable a TIMER */
timer_enable(BSP_RF_TIMER);
nvic_irq_enable(TIMER2_IRQn, 0, 0);
}
/* !
* @brief E15-EVB02 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>ʼ<EFBFBD><CABC>
*
* @note <20>ڲ<EFBFBD>ʱ<EFBFBD><CAB1>HSI x 16MHz
* <20>û<EFBFBD>ͨ<EFBFBD>Ŵ<EFBFBD><C5B4><EFBFBD> x USART1
* <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>ͨ<EFBFBD>Žӿ<C5BD> x SPI1
* <20><>ʱ<EFBFBD><CAB1> x TIM3
* <20><><EFBFBD><EFBFBD> x 2
* ָʾ<D6B8><CABE> x 2
*/
void Ebyte_BSP_Init( void )
{
/* ʱ<><CAB1> <20><>ʼ<EFBFBD><CABC> */
// Ebyte_BSP_HSI_Init();
/* IO <20><>ʼ<EFBFBD><CABC> */
Ebyte_BSP_GPIO_Init();
/* <20><><EFBFBD><EFBFBD> <20><>ʼ<EFBFBD><CABC> */
// Ebyte_BSP_UART_Init();
/* SPI<50>ӿ<EFBFBD> <20><>ʼ<EFBFBD><CABC> */
Ebyte_BSP_SPI_Init();
/* <20><>ʱ<EFBFBD><CAB1> <20><>ʼ<EFBFBD><CABC> */
Ebyte_BSP_TIMER_Init();
/* <20><><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD> <20><>ʼ<EFBFBD><CABC> */
Ebyte_BTN_FIFO_Init( &BSP_BTN_FIFO );
}
/* !
* @brief <20><><EFBFBD><EFBFBD>LED <20><>/<2F><>/<2F><>ת
*
* @param LEDx <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ŷ<EFBFBD><C5B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg BSP_LED_1 : LED1
* @arg BSP_LED_2 : LED2
*
* @param ctl <20><> / <20><>
* @arg OFF : <20><>
* @arg ON : <20><>
* @arg TOGGLE : <20><>ת
*/
void Ebyte_BSP_LedControl( BSP_LED_t LEDx , BSP_LED_Ctl_t ctl)
{
if( TOGGLE == ctl )
{
switch( LEDx )
{
case BSP_LED_1 : gpio_bit_toggle( BSP_GPIO_PORT_LED_1, BSP_GPIO_PIN_LED_1); break;
case BSP_LED_2 : gpio_bit_toggle( BSP_GPIO_PORT_LED_2, BSP_GPIO_PIN_LED_2); break;
default: break;
}
}
else
{
switch( LEDx )
{
case BSP_LED_1 : gpio_bit_write( BSP_GPIO_PORT_LED_1, BSP_GPIO_PIN_LED_1, (BitAction)ctl); break;
case BSP_LED_2 : gpio_bit_write( BSP_GPIO_PORT_LED_2, BSP_GPIO_PIN_LED_2, (BitAction)ctl); break;
default: break;
}
}
}
/* !
* @brief <20><><EFBFBD>ڶ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ĺ<EFBFBD><C4BA><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
*
* @param nTime <20><>λ:<3A><><EFBFBD><EFBFBD>
*/
void Ebyte_BSP_DelayMs( volatile uint32_t nTime )
{
Ebyte_TimerDelayCounter = nTime;
while( Ebyte_TimerDelayCounter !=0 );
}
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> <20><>ʱ<EFBFBD><CAB1><EFBFBD>жϵ<D0B6><CFB5><EFBFBD>
*/
void Ebyte_BSP_TimerDecrement(void)
{
if( Ebyte_TimerDelayCounter != 0 )
{
Ebyte_TimerDelayCounter--;
}
}
/* !
* @brief <20><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>״̬
*
* @param btn <20><>Ӧ<EFBFBD>İ<EFBFBD><C4B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg BSP_BUTTON_1 :<3A><><EFBFBD><EFBFBD>1
* @arg BSP_BUTTON_2 :<3A><><EFBFBD><EFBFBD>2
* @return 0:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>0:<3A><><EFBFBD><EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD>
* @note <20><><EFBFBD>ذ<EFBFBD><D8B0><EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD>ʱ IO<49><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬ <20><>Ϊ1<CEAA><31><EFBFBD><EFBFBD><EFBFBD>º<EFBFBD>IO<49>ӵ<EFBFBD> <20><>Ϊ0
*/
uint8_t Ebyte_BSP_ReadButton( BSP_BUTTON_t btn )
{
BitStatus result = RESET;
switch ( btn )
{
case BSP_BUTTON_1: result = gpio_input_bit_get( BSP_GPIO_PORT_BUTTON_1 , BSP_GPIO_PIN_BUTTON_1); break;
// case BSP_BUTTON_2: result = GPIO_ReadInputDataBit( BSP_GPIO_PORT_BUTTON_2 , BSP_GPIO_PIN_BUTTON_2); break;
default : break;
}
return result;
}
/* !
* @brief <20><><EFBFBD>ڷ<EFBFBD><DAB7>ͺ<EFBFBD><CDBA><EFBFBD>
*/
void Ebyte_BSP_UartTransmit( uint8_t *buffer , uint16_t length )
{
uint8_t i;
for( i = 0; i < length; i++ ) {
while(RESET == usart_flag_get(LOG_UART, USART_FLAG_TBE));
usart_data_transmit(LOG_UART, *buffer);
}
}

181
NSPE/WIFI_IOT/bsp/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.h Executable file
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@ -0,0 +1,181 @@
/**
**********************************************************************************
* @file board.h
* @brief E15-EVB02 <20>弶<EFBFBD><E5BCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @details <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> https://www.ebyte.com/
* @author JiangHeng
* @date 2021-05-06
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#ifndef __EBYTE_BOARD_H__
#define __EBYTE_BOARD_H__
#include <stdint.h>
//#include "stm8l15x_conf.h"
#include "gd32w51x.h"
#include "debug_print.h"
#include "board_mini_printf.h"
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> LED */
#define BSP_GPIO_RCU_E48_LED RCU_GPIOB
#define BSP_GPIO_PORT_LED_1 GPIOB
#define BSP_GPIO_PIN_LED_1 GPIO_PIN_6
#define BSP_GPIO_PORT_LED_2 GPIOA
#define BSP_GPIO_PIN_LED_2 GPIO_PIN_15
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> */
#define BSP_GPIO_RCU_E48_BUTTON RCU_GPIOA
#define BSP_GPIO_PORT_BUTTON_1 GPIOA
#define BSP_GPIO_PIN_BUTTON_1 GPIO_PIN_2
//#define BSP_GPIO_PORT_BUTTON_2 GPIOA
//#define BSP_GPIO_PIN_BUTTON_2 GPIO_PIN_5
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SPIͨ<49>Žӿ<C5BD> */
#define BSP_GPIO_RCU_E48_SPI RCU_GPIOB
#define BSP_GPIO_PORT_SPI GPIOB
#define BSP_GPIO_PIN_SPI_NSS GPIO_PIN_12
#define BSP_GPIO_PIN_SPI_SCK GPIO_PIN_13
#define BSP_GPIO_PIN_SPI_MISO GPIO_PIN_14
#define BSP_GPIO_PIN_SPI_MOSI GPIO_PIN_15
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ͨ<>Ŵ<EFBFBD><C5B4><EFBFBD> */
#define BSP_GPIO_PORT_UART_TX GPIOA
#define BSP_GPIO_PIN_UART_TX GPIO_PIN_2
#define BSP_GPIO_PORT_UART_RX GPIOA
#define BSP_GPIO_PIN_UART_RX GPIO_PIN_3
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> EBYTE<54><45><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/* E48 */
#define BSP_GPIO_RCU_E48_GPIO RCU_GPIOC
#define BSP_GPIO_PORT_E48_GP0 GPIOC
#define BSP_GPIO_PIN_E48_GP0 GPIO_PIN_0
#define BSP_GPIO_PORT_E48_NIRQ GPIOC
#define BSP_GPIO_PIN_E48_NIRQ GPIO_PIN_1
#define BSP_GPIO_PORT_E48_GP3 GPIOC
#define BSP_GPIO_PIN_E48_GP3 GPIO_PIN_3
#define BSP_GPIO_PORT_E48_GP4 GPIOC
#define BSP_GPIO_PIN_E48_GP4 GPIO_PIN_4
#define BSP_GPIO_PORT_E48_GP5 GPIOC
#define BSP_GPIO_PIN_E48_GP5 GPIO_PIN_5
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SPI */
#define BSP_RF_SPI SPI1
#define BSP_RF_SPI_CLOCK RCU_SPI1
#define Ebyte_BSP_RfSpiSelected() gpio_bit_write( BSP_GPIO_PORT_SPI, BSP_GPIO_PIN_SPI_NSS, RESET )
#define Ebyte_BSP_RfSpiUnselected() gpio_bit_write( BSP_GPIO_PORT_SPI, BSP_GPIO_PIN_SPI_NSS, SET )
/* <20><><EFBFBD><EFBFBD> Timer */
#define BSP_RF_TIMER TIMER2
#define BSP_RF_TIMER_RCU RCU_TIMER2
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO */
///* E07 */
//#define Ebyte_BSP_RfBusyIoRead() gpio_input_bit_get( BSP_GPIO_PORT_BUSY , BSP_GPIO_PIN_BUSY)
//#define Ebyte_BSP_RfGdo0IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E07_GDO0 , BSP_GPIO_PIN_E07_GDO0)
//#define Ebyte_BSP_RfGdo1IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E07_GDO1 , BSP_GPIO_PIN_E07_GDO1)
///* E10 */
//#define Ebyte_BSP_E10IrqIoRead() gpio_input_bit_get( BSP_GPIO_PORT_E10_IRQ , BSP_GPIO_PIN_E10_IRQ)
//#define Ebyte_BSP_E10Dio2Read() gpio_input_bit_get( BSP_GPIO_PORT_E10_DIO2 , BSP_GPIO_PIN_E10_DIO2)
//#define Ebyte_BSP_E10Dio3Read() gpio_input_bit_get( BSP_GPIO_PORT_E10_DIO3 , BSP_GPIO_PIN_E10_DIO3)
//#define Ebyte_BSP_E10SdnIoLow() gpio_bit_write( BSP_GPIO_PORT_E10_SDN , BSP_GPIO_PIN_E10_SDN, RESET )
//#define Ebyte_BSP_E10SdnIoHigh() gpio_bit_write( BSP_GPIO_PORT_E10_SDN , BSP_GPIO_PIN_E10_SDN, SET )
///* E49 */
//#define Ebyte_BSP_E49Dio1IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E49_DIO1 , BSP_GPIO_PIN_E49_DIO1)
//#define Ebyte_BSP_E49Dio2IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E49_DIO2 , BSP_GPIO_PIN_E49_DIO2)
//#define Ebyte_BSP_E49FcsbIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_FCSB , BSP_GPIO_PIN_E49_FCSB, RESET )
//#define Ebyte_BSP_E49FcsbIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_FCSB , BSP_GPIO_PIN_E49_FCSB, SET )
//#define Ebyte_BSP_E49CsbIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_CSB , BSP_GPIO_PIN_E49_CSB, RESET )
//#define Ebyte_BSP_E49CsbIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_CSB , BSP_GPIO_PIN_E49_CSB, SET )
//#define Ebyte_BSP_E49SlckIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_SLCK , BSP_GPIO_PIN_E49_SLCK, RESET )
//#define Ebyte_BSP_E49SlckIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_SLCK , BSP_GPIO_PIN_E49_SLCK, SET )
//#define Ebyte_BSP_E49SdioIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO, RESET )
//#define Ebyte_BSP_E49SdioIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO, SET )
//#define Ebyte_BSP_E49SdioIoOutput() gpio_mode_set( BSP_GPIO_PORT_E49_SDIO, BSP_GPIO_PIN_E49_SDIO, GPIO_Mode_Out_PP_High_Fast )
//#define Ebyte_BSP_E49SdioIoInput() GPIO_Init( BSP_GPIO_PORT_E49_SDIO, BSP_GPIO_PIN_E49_SDIO, GPIO_Mode_In_FL_No_IT )
//#define Ebyte_BSP_E49SdioIoRead() GPIO_ReadInputDataBit( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO)
/* E48 */
#define Ebyte_BSP_E48GPIO4Read() gpio_input_bit_get( BSP_GPIO_PORT_E48_GP4 , BSP_GPIO_PIN_E48_GP4)
/* ȫ<><C8AB><EFBFBD>ж<EFBFBD> */
#define Ebyte_BSP_GlobalIntEnable() __enable_irq()
#define Ebyte_BSP_GlobalIntDisable() __disable_irq()
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> UART */
#define BSP_USER_UART USART1
#define BSP_USER_UART_CLOCK CLK_Peripheral_USART1
#define BSP_USER_UART_BAUDRATE 9600 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define BSP_USER_UART_PARITY USART_Parity_No //USART_Parity_No:<3A><>У<EFBFBD><D0A3> USART_Parity_Even:<3A><>У<EFBFBD><D0A3> USART_Parity_Odd:żУ<C5BC><D0A3>
#define BSP_USER_UART_IRQ USART1_RX_IRQn //<2F>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>
#define BSP_USER_UART_IRQ_LEVEL ITC_PriorityLevel_2 //<2F><><EFBFBD>ȼ<EFBFBD>
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD> */
#define BSP_BTN_FIFO_LENGTH 16
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>Դ<EFBFBD>ӡ<EFBFBD><D3A1>Ϣ <20>رմ<D8B1>ӡ<EFBFBD><D3A1>Ҫע<D2AA>͵<EFBFBD><CDB5>궨<EFBFBD><EAB6A8> EBYTE_DEBUG */
#define EBYTE_DEBUG
#ifdef EBYTE_DEBUG
#define DEBUG(format, ...) mprintf(format, ##__VA_ARGS__)
#else
#define DEBUG(...)
#endif
typedef enum { BSP_LED_1 = 0, BSP_LED_2 } BSP_LED_t;
typedef enum { OFF = 0, ON , TOGGLE} BSP_LED_Ctl_t;
typedef enum { UART_8N1 = 0, UART_8O1, UART_8E1 } BSP_UART_Parity_t;
typedef enum { BSP_BUTTON_1 = 0, BSP_BUTTON_2 } BSP_BUTTON_t;
typedef enum
{
BTN_1_SHORT, //<2F><><EFBFBD><EFBFBD>1 <20>̰<EFBFBD>
BTN_1_LONG, //<2F><><EFBFBD><EFBFBD>1 <20><><EFBFBD><EFBFBD>
BTN_2_SHORT, //<2F><><EFBFBD><EFBFBD>2 <20>̰<EFBFBD>
BTN_2_LONG, //<2F><><EFBFBD><EFBFBD>2 <20><><EFBFBD><EFBFBD>
}BSP_BTN_EVENT_t;
typedef struct
{
uint8_t fifoLen ;
uint8_t fifoRead ;
uint8_t fifoWrite ;
uint8_t buff[BSP_BTN_FIFO_LENGTH];
}BSP_BTN_FIFO_t;
extern BSP_BTN_FIFO_t BSP_BTN_FIFO;
void Ebyte_BSP_Init( void );
void Ebyte_BTN_FIFO_Init(BSP_BTN_FIFO_t *fifo);
void Ebyte_BSP_DelayMs( volatile uint32_t nTime );
void Ebyte_BSP_TimerDecrement(void);
void Ebyte_BSP_LedControl( BSP_LED_t LEDx , BSP_LED_Ctl_t ctl);
void Ebyte_BSP_UartTransmit( uint8_t *buffer , uint16_t length );
uint8_t Ebyte_BSP_ReadButton( BSP_BUTTON_t btn );
uint8_t Ebyte_BSP_SpiTransAndRecv( uint8_t data );
uint8_t Ebyte_BTN_FIFO_Push(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t event);
uint8_t Ebyte_BTN_FIFO_Pop(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t *event);
uint32_t Ebyte_BSP_TimerGetTick(void);
#endif // !__EBYTE_BOARD_H__

147
NSPE/WIFI_IOT/bsp/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.c Executable file
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@ -0,0 +1,147 @@
/**
**********************************************************************************
* @file board_button.c
* @brief ͨ<><CDA8> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @author JiangHeng
* @date 2021-05-06
* @version 1.0.0
**********************************************************************************
* @copyright BSD License
* <20>ɶ<EFBFBD><C9B6>ڰ<EFBFBD><DAB0>ص<EFBFBD><D8B5>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* ______ ____ __ __ _______ ______
* | ____| | _ \ \ \ / / |__ __| | ____|
* | |__ | |_) | \ \_/ / | | | |__
* | __| | _ < \ / | | | __|
* | |____ | |_) | | | | | | |____
* |______| |____/ |_| |_| |______|
*
**********************************************************************************
*/
#include "board.h"
#include "ebyte_kfifo.h"
#include "ebyte_core.h"
static uint16_t Button1_TickCounter = 0;
static uint16_t Button2_TickCounter = 0;
extern Ebyte_FIFO_t hfifo;
extern uint8_t FIFO_isTimeCheckReady;
static uint32_t FIFO_TickCounter = 0;
/* Private function prototypes -----------------------------------------------*/
void IT_Timer_ButtonCheck(void);
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>г<EFBFBD>ʼ<EFBFBD><CABC>
*
* @param fifo ָ<>򰴼<EFBFBD><F2B0B4BC>¼<EFBFBD><C2BC><EFBFBD><EFBFBD>нṹ<D0BD><E1B9B9><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
*/
void Ebyte_BTN_FIFO_Init(BSP_BTN_FIFO_t *fifo)
{
fifo->fifoLen = 0;
fifo->fifoRead = 0;
fifo->fifoWrite = 0;
}
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* @param fifo ָ<>򰴼<EFBFBD><F2B0B4BC>¼<EFBFBD><C2BC><EFBFBD><EFBFBD>нṹ<D0BD><E1B9B9><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
* @param event <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD> <20><>ҪΪ<D2AA><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ķ̰<C4B6>/<2F><><EFBFBD><EFBFBD>
* @return 0:<3A><><EFBFBD><EFBFBD> 1:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @note <20><><EFBFBD><EFBFBD>λ<EFBFBD>ÿ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ḳ<EFBFBD><E1B8B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ᵼ<EFBFBD><E1B5BC><EFBFBD><EFBFBD><EFBFBD>ݶ<EFBFBD>ʧ<EFBFBD><CAA7>
*/
uint8_t Ebyte_BTN_FIFO_Push(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t event)
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
fifo->fifoLen++;
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӳ<EFBFBD><D3B3>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD> */
if(fifo->fifoLen > BSP_BTN_FIFO_LENGTH)
{
fifo->fifoLen = BSP_BTN_FIFO_LENGTH;//<2F><><EFBFBD>ӳ<EFBFBD><D3B3>Ȳ<EFBFBD><C8B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
return 1;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
fifo->buff[fifo->fifoWrite] = event;
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD>Ѿ<EFBFBD><D1BE><EFBFBD><EFBFBD>˶<EFBFBD>β */
if(++fifo->fifoWrite >= BSP_BTN_FIFO_LENGTH)
{
fifo->fifoWrite = 0; //<2F><>ô<EFBFBD><C3B4>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>׿<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
}
return 0;
}
/* !
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>г<EFBFBD><D0B3><EFBFBD>
*
* @param fifo ָ<>򰴼<EFBFBD><F2B0B4BC>¼<EFBFBD><C2BC><EFBFBD><EFBFBD>нṹ<D0BD><E1B9B9><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
* @param event <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD> <20><>ҪΪ<D2AA><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ķ̰<C4B6>/<2F><><EFBFBD><EFBFBD>
* @return 0:<3A><><EFBFBD><EFBFBD> 1:<3A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>
*/
uint8_t Ebyte_BTN_FIFO_Pop(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t *event)
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӳ<EFBFBD><D3B3><EFBFBD>Ϊ0 <20><><EFBFBD>ն<EFBFBD><D5B6><EFBFBD> */
if(fifo->fifoLen == 0)
{
return 1;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD><EFBFBD>Լ<EFBFBD> */
fifo->fifoLen--;
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
*event = (BSP_BTN_EVENT_t )(fifo->buff[fifo->fifoRead]);
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD>Ѿ<EFBFBD><D1BE><EFBFBD><EFBFBD>˶<EFBFBD>β */
if(++fifo->fifoRead >= BSP_BTN_FIFO_LENGTH)
{
fifo->fifoRead = 0;//<2F><>ô<EFBFBD><C3B4>һ<EFBFBD>ν<EFBFBD><CEBD>Ӷ<EFBFBD><D3B6>׿<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
}
return 0;
}
/* !
* @brief <20><>ʱ<EFBFBD><CAB1><EFBFBD>ж<EFBFBD> ״̬<D7B4><CCAC> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
void IT_Timer_ButtonCheck(void)
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if (!Ebyte_BSP_ReadButton(BSP_BUTTON_1)) {
Button1_TickCounter++;
} else {
if (Button1_TickCounter > 1000) // 1<><31> <20><><EFBFBD><EFBFBD>
{
Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_1_LONG);
} else if (Button1_TickCounter > 50) // 50<35><30><EFBFBD><EFBFBD> <20>̰<EFBFBD>
{
Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_1_SHORT);
} else {
} // 50<35><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ϊ<EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
Button1_TickCounter = 0;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if (!Ebyte_BSP_ReadButton(BSP_BUTTON_2)) {
Button2_TickCounter++;
} else {
if (Button2_TickCounter > 1000) // 1<><31> <20><><EFBFBD><EFBFBD>
{
Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_2_LONG);
} else if (Button2_TickCounter > 50) // 50<35><30><EFBFBD><EFBFBD> <20>̰<EFBFBD>
{
Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_2_SHORT);
} else {
} // 50<35><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ϊ<EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
Button2_TickCounter = 0;
}
}

6
NSPE/WIFI_IOT/bsp/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.h Executable file
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#ifndef __BOARD_BUTTON_H__
#define __BOARD_BUTTON_H__
void IT_Timer_ButtonCheck(void);
#endif // !__BOARD_BUTTON_H__

203
NSPE/WIFI_IOT/bsp/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.c Executable file
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#include <stdio.h>
#include "stdarg.h"
#include "gd32w51x.h"
//#include "stm8l15x_usart.h"
#include "board_mini_printf.h"
#include "platform_def.h"
/* !
* @brief Ŀ<><C4BF>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD>Žӿ<C5BD>
*
* @param data д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 Byte
*/
static void send_uart_data(uint8_t data)
{
while(RESET == usart_flag_get(LOG_UART, USART_FLAG_TBE));
usart_data_transmit(LOG_UART, data);
}
/*
<20><><EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD>int<6E><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD>תΪ2<CEAA><32>8<EFBFBD><38>10<31><30>16<31><36><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>value --- <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>int<6E><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
str --- <20>洢ת<E6B4A2><D7AA><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
radix --- <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
ע<>⣺8λ<38><CEBB>Ƭ<EFBFBD><C6AC>int<6E>ֽ<EFBFBD>ֻռ2<D5BC><32><EFBFBD>ֽ<EFBFBD>
*/
static char *sky_itoa(int value, char *str, unsigned int radix)
{
char list[] = "0123456789ABCDEF";
unsigned int tmp_value;
int i = 0, j, k = 0;
// if (NULL == str) {
if (0 == str) {
// return NULL;
return 0;
}
if (2 != radix && 8 != radix && 10 != radix && 16 != radix) {
// return NULL;
return 0;
}
if (radix == 10 && value < 0) {
//ʮ<><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
tmp_value = (unsigned int)(0 - value);
str[i++] = '-';
k = 1;
} else {
tmp_value = (unsigned int)value;
}
//<2F><><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>洢
do {
str[i ++] = list[tmp_value%radix];
tmp_value /= radix;
} while(tmp_value);
str[i] = '\0';
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
char tmp;
for (j = k; j < (i+k)/2; j++) {
tmp = str[j];
str[j] = str[i-j-1+k];
str[i-j-1+k] = tmp;
}
return str;
}
/*
<20><><EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD>double<6C><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>תΪ<D7AA>ַ<EFBFBD><D6B7><EFBFBD>
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>value --- <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>double<6C><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
str --- <20>洢ת<E6B4A2><D7AA><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
eps --- <20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1>λѡ<CEBB><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٱ<EFBFBD><D9B1><EFBFBD>һ<EFBFBD><D2BB>С<EFBFBD><D0A1>λ,<2C><><EFBFBD>ౣ<EFBFBD><E0B1A3>4<EFBFBD><34>С<EFBFBD><D0A1>λ
ע<>⣺8λ<38><CEBB>Ƭ<EFBFBD><C6AC>int<6E>ֽ<EFBFBD>ֻռ2<D5BC><32><EFBFBD>ֽ<EFBFBD>
*/
static void sky_ftoa(double value, char *str, unsigned int eps)
{
unsigned int integer;
double decimal;
char list[] = "0123456789";
int i = 0, j, k = 0;
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
if (value < 0) {
decimal = (double)(((int)value) - value);
integer = (unsigned int)(0 - value);
str[i ++] = '-';
k = 1;
} else {
integer = (unsigned int)(value);
decimal = (double)(value - integer);
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>洢
do {
str[i ++] = list[integer%10];
integer /= 10;
} while(integer);
str[i] = '\0';
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
char tmp;
for (j = k; j < (i+k)/2; j++) {
tmp = str[j];
str[j] = str[i-j-1+k];
str[i-j-1+k] = tmp;
}
//<2F><><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
if (eps < 1 || eps > 4) {
eps = 4;
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>⣬<EFBFBD><E2A3AC>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>1.2<EFBFBD><EFBFBD><EFBFBD><EFBFBD>1.19<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
double pp = 0.1;
for (j = 0; j <= eps; j++) {
pp *= 0.1;
}
decimal += pp;
while (eps) {
decimal *= 10;
eps --;
}
int tmp_decimal = (int)decimal;
str[i ++] = '.';
k = i;
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>洢
do {
str[i ++] = list[tmp_decimal%10];
tmp_decimal /= 10;
} while(tmp_decimal);
str[i] = '\0';
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ת<EFBFBD><D7AA>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
for (j = k; j < (i+k)/2; j++) {
tmp = str[j];
str[j] = str[i-j-1+k];
str[i-j-1+k] = tmp;
}
str[i] = '\0';
}
void mprintf(char * Data, ...)
{
const char *s;
int d;
char buf[16];
uint8_t txdata;
va_list ap;
va_start(ap, Data);
while ( * Data != 0 ) {
if ( * Data == 0x5c ) {
switch ( *++Data ) {
case 'r':
txdata = 0x0d;
send_uart_data(txdata);
Data ++;
break;
case 'n':
txdata = 0x0a;
send_uart_data(txdata);
Data ++;
break;
default:
Data ++;
break;
}
} else if ( * Data == '%') {
switch ( *++Data ) {
case 's':
s = va_arg(ap, const char *);
for ( ; *s; s++) {
send_uart_data(*((uint8_t *)s));
}
Data++;
break;
case 'd':
d = va_arg(ap, int);
sky_itoa(d, buf, 10);
for (s = buf; *s; s++) {
send_uart_data(*((uint8_t *)s));
}
Data++;
break;
case 'x': {
d = va_arg(ap, int);
sky_itoa(d, buf, 16);
for (s = buf; *s; s++) {
send_uart_data(*((uint8_t *)s));
}
Data++;
break;
}
case 'f': {
double num = va_arg(ap, double);
sky_ftoa(num, buf, 4);
for (s = buf; *s; s++) {
send_uart_data(*((uint8_t *)s));
}
Data++;
break;
}
default:
Data++;
break;
}
} else {
send_uart_data(*((uint8_t *)Data));
Data++;
}
}
}

6
NSPE/WIFI_IOT/bsp/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.h Executable file
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@ -0,0 +1,6 @@
#ifndef __BOARD_PRINTF_H__
#define __BOARD_PRINTF_H__
void mprintf(char * Data, ...);
#endif // !__BOARD_PRINTF_H__

578
NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h Executable file
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@ -0,0 +1,578 @@
/*
* THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND
* (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
* CONSEQUENTLY, CMOSTEK SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* Copyright (C) CMOSTEK SZ.
*/
/*!
* @file CMT2310A_def.h
* @brief CMT2310A transceiver RF chip driver
*
* @version 1.0
* @date Dec 7 2021
* @author CMOSTEK R&D
*/
#ifndef __CMT2310A_DEF_H
#define __CMT2310A_DEF_H
//Exit State
#define EXIT_TO_SLEEP 1
#define EXIT_TO_READY 2
#define EXIT_TO_TFS 3
#define EXIT_TO_TX 4
#define EXIT_TO_RFS 5
#define EXIT_TO_RX 6
//Prefxi select
#define TX_PREFIX_SEL_0 0
#define TX_PREFIX_SEL_1 1
#define TX_PREFIX_SEL_PREAMBLE 2
//## interrupt source config
typedef union
{
struct
{
uint8_t PKT_DONE_EN: 1; //pkt_done_en //bit0
uint8_t CRC_PASS_EN: 1; //crc_pass_en //bit1
uint8_t ADDR_PASS_EN: 1; //node_address_pass_en //bit2
uint8_t SYNC_PASS_EN: 1; //sync_pass_en //bit3
uint8_t PREAM_PASS_EN: 1; //preamble_pass_en //bit4
uint8_t TX_DONE_EN: 1; //tx_done_en //bit5
uint8_t RX_TOUT_EN: 1; //rx_timeout_en //bit6
uint8_t SLP_TOUT_EN: 1; //sleep_timeout_en //bit7
uint8_t LD_STOP_EN: 1; //ld_stop_en(PLL lock detect)//bit0
uint8_t LBD_STOP_EN: 1; //lbd_stop_en //bit1
uint8_t LBD_STAT_EN: 1; //lbd_status_en //bit2
uint8_t PKT_ERR_EN: 1; //pkt_err_en //bit3
uint8_t RSSI_COLL_EN: 1; //rssi_collision_en //bit4
uint8_t OP_CMD_FAILED_EN: 1; //op_cmd_failed_en //bit5
uint8_t RSSI_PJD_EN: 1; //rssi_pjd_valid_en //bit6
uint8_t RESV_2_1: 1; //reserve, don't used //bit7
uint8_t SEQ_MATCH_EN: 1; //seq_match_en //bit0
uint8_t NACK_RECV_EN: 1; //nack_recv_en //bit1
uint8_t TX_RESEND_DONE_EN: 1; //tx_resend_done_en //bit2
uint8_t ACK_RECV_FAILED_EN: 1; //ack_recv_failed_en //bit3
uint8_t TX_DC_DONE_EN: 1; //tx_dc_done_en //bit4
uint8_t CSMA_DONE_EN: 1; //csma_max_en //bit5
uint8_t CCA_STAT_EN: 1; //cca_status_en //bit6
uint8_t API_DONE_EN: 1; //api_done_en //bit7
uint8_t TX_FIFO_TH_EN: 1; //tx_fifo_threshold_en //bit0
uint8_t TX_FIFO_NMTY_EN: 1; //tx_fifo_non_empty_en //bit1
uint8_t TX_FIFO_FULL_EN: 1; //tx_fifo_full_en //bit2
uint8_t RX_FIFO_OVF_EN: 1; //rx_fifo_overflow_en //bit3
uint8_t RESV_4_1: 1; //reserve, don't used //bit4
uint8_t RX_FIFO_TH_EN: 1; //rx_fifo_threshold_en //bit5
uint8_t RX_FIFO_NMTY_EN: 1; //rx_fifo_non_empty_en //bit6
uint8_t RX_FIFO_FULL_EN: 1; //rx_fifo_full_en //bit7
} _BITS;
struct
{
uint8_t INT_CTL1_REG; //CTL_REG_18, 0x12
uint8_t INT_CTL2_REG; //CTL_REG_21, 0x15
uint8_t INT_CTL3_REG; //CTL_REG_23, 0x17
uint8_t INT_CTL4_REG; //CTL_REG_14, 0x0E
} _BYTE;
} INT_SRC_CFG;
//## interrupt flag
typedef union
{
struct
{
uint8_t RESV_3: 3; //reserve, don't used //bit0/1/2
uint8_t TX_DONE_FLG: 1; //tx_done_flag //bit3
uint8_t RX_TMO_FLG: 1; //rx_timer_timeout_flag //bit4
uint8_t SLEEP_TMO_FLG: 1; //sleep_timer_timeout_flag //bit5
uint8_t RESV_2: 2; //reserve, don't used //bit6/7
uint8_t PKT_DONE_FLG: 1; //pkt_done_flag //bit0
uint8_t CRC_PASS_FLG: 1; //crc_pass_flag //bit1
uint8_t ADDR_PASS_FLG: 1; //addr_pass_flag //bit2
uint8_t SYNC_PASS_FLG: 1; //sync_pass_flag //bit3
uint8_t PREAM_PASS_FLG: 1; //preamble_pass_flag //bit4
uint8_t SYNC1_PASS_FLG: 1; //sync1_pass_flag //bit5
uint8_t RESV_2_2: 2; //reserve, don't used //bit6/7
uint8_t LBD_STATUS_FLG: 1; //lbd_status_flag //bit0
uint8_t PKT_ERR_FLG: 1; //pkt_err_flag //bit1
uint8_t RSSI_COLL_FLG: 1; //rssi_collision_flag //bit2
uint8_t OP_CMD_FAILED_FLG: 1; //op_cmd_failed_flag //bit3
uint8_t ANT_LOCK_FLG: 1; //ant_lock_flag //bit4
uint8_t RESV_3_3: 3; //reserve, don't used //bit5/6/7
uint8_t SEQ_MATCH_FLG: 1; //seq_match_flag //bit0
uint8_t NACK_RECV_FLG: 1; //nack_recv_flag //bit1
uint8_t TX_RESEND_DONE_FLG: 1; //tx_resend_max_flag //bit2
uint8_t ACK_RECV_FAILED_FLG: 1; //ack_recv_failed_flag //bit3
uint8_t TX_DC_DONE_FLG: 1; //tx_dc_done_flag //bit4
uint8_t CSMA_DONE_FLG: 1; //csma_done_flag //bit5
uint8_t CCA_STATUS_FLG: 1; //cca_status_flag //bit6
uint8_t API_DONE_FLG: 1; //api_done_flag //bit7
} _BITS;
struct
{
uint8_t INT_FLAG1_REG; //CTL_REG_24, 0x18
uint8_t INT_FLAG2_REG; //CTL_REG_26, 0x1A
uint8_t INT_FLAG3_REG; //CTL_REG_30, 0x1E
uint8_t INT_FLAG4_REG; //CTL_REG_32, 0x20
} _BYTE;
} INT_SRC_FLG;
//## interrupt clear
typedef union
{
struct
{
uint8_t TX_DONE_CLR: 1; //tx_done_clr //bit0
uint8_t RX_TMO_CLR: 1; //rx_timer_timeout_clr //bit1
uint8_t SLEEP_TMO_CLR: 1; //sleep_timer_timeout_clr //bit2
uint8_t RESV_5: 5; //reserve, don't used //bit3-7
uint8_t PKT_DONE_CLR: 1; //pkt_done_clr //bit0
uint8_t CRC_PASS_CLR: 1; //crc_pass_clr //bit1
uint8_t ADDR_PASS_CLR: 1; //addr_pass_clr //bit2
uint8_t SYNC_PASS_CLR: 1; //sync_pass_clr //bit3
uint8_t PREAM_PASS_CLR: 1; //preamble_pass_clr //bit4
uint8_t RESV_3: 3; //reserve, don't used //bit5/6/7
uint8_t LBD_STAT_CLR: 1; //lbd_status_clr //bit0
uint8_t PKT_ERR_CLR: 1; //packet_err_clr //bit1
uint8_t RSSI_COLL_CLR: 1; //rssi_collision_clr //bit2
uint8_t OP_CMD_FAILED_CLR: 1; //op_cmd_failed_clr //bit3
uint8_t ANT_LOCK_CLR: 1; //antenna_lock_clr //bit4
uint8_t RESV_2_3: 3; //reserve, don't used //bit5/6/7
uint8_t SEQ_MATCH_CLR: 1; //seq_match_clr //bit0
uint8_t NACK_RECV_CLR: 1; //nack_recv_clr //bit1
uint8_t TX_RESEND_DONE_CLR: 1; //tx_resend_done_clr //bit2
uint8_t ACK_RECV_FAILED_CLR: 1; //ack_recv_failed_clr //bit3
uint8_t TX_DC_DONE_CLR: 1; //tx_dc_done_clr //bit4
uint8_t CSMA_DONE_CLR: 1; //csma_done_clr //bit5
uint8_t CCA_STATUS_CLR: 1; //cca_status_clr //bit6
uint8_t API_DONE_CLR: 1; //api_done_clr //bit7
} _BITS;
struct
{
uint8_t INT_CLR1_REG; //CTL_REG_24, 0x18
uint8_t INT_CLR2_REG; //CTL_REG_25, 0x19
uint8_t INT_CLR3_REG; //CTL_REG_29, 0x1D
uint8_t INT_CLR4_REG; //CTL_REG_31, 0x1F
} _BYTE;
} INT_SRC_CLR;
//## fifo status flag
typedef union
{
struct
{
uint8_t TX_FIFO_TH_FLG: 1; //tx_fifo_threshold_flag //bit0
uint8_t TX_FIFO_NMTY_FLG: 1; //tx_fifo_non_empty_flag //bit1
uint8_t TX_FIFO_FULL_FLG: 1; //tx_fifo_full_flag //bit2
uint8_t RX_FIFO_OVF_FLG: 1; //rx_fifo_overflow_flag //bit3
uint8_t RESV_1: 1; //reserve, don't used //bit4
uint8_t RX_FIFO_TH_FLG: 1; //rx_fifo_threshold_flag //bit5
uint8_t RX_FIFO_NMTY_FLG: 1; //rx_fifo_non_empty_flag //bit6
uint8_t RX_FIFO_FULL_FLG: 1; //rx_fifo_full_flag //bit7
} _BITS;
uint8_t FIFO_FLG_REG; //CTL_REG_28, 0x1c
} FIFO_STATUS_FLG;
//## packet preamble config
typedef struct //Packet Preamble
{
uint8_t PREAM_LENG_UNIT; //0=preamble unit as 8bits, !0=preamble unit as 4bits (nibble mode)
uint8_t PREAM_VALUE; //preamble value
uint8_t RX_PREAM_SIZE; //rx preamble length, range: 0-31, 0==disable rx preamble detect
uint16_t TX_PREAM_SIZE; //tx preamble length //## note: for arm mcu uint16_t is 16bits
} PREAMBLE_CFG;
//## packet syncword config
typedef struct
{
union
{
struct
{
uint8_t SYNC_MAN_EN: 1; //sync word manchester coding enable
uint8_t SYNC_SIZE: 3; // n+1 bytes
uint8_t SYNC_TOL: 3; // n bits tolerence error
uint8_t SYNC_MODE_SEL: 1; // 0: compatible S2LP; 1: compatible 802.15.4
} _BITS;
uint8_t SYNC_CFG_REG; //CTL_REG_44, 0x2c
} SYN_CFG_u;
uint8_t SYNC_VALUE[8]; //CTL_REG_45-CTL_REG_53, 0x2D-0x34
uint8_t SYNC_FEC_VALUE[8]; //CTL_REG_53-CTL_REG_60, 0x35-0x3C
uint8_t SYNC_VALUE_SEL; // 0: select SYN_VAL; !0: select SYN_FEC_VAL
} SYNC_CFG;
//## packet node address config
typedef struct
{
union
{
struct
{
uint8_t ADDR_DET_MODE: 2; //node address mode: 0,disable; 1,only match; 2,add all 0; 3,add all 1 & 0
uint8_t ADDR_SIZE: 2; // n+1 bytes
uint8_t ADDR_ERR_MASK: 1; // 0: trigger PKT_ERR flag, when node address not match, and reset decode; 1: non-reset decode, when node address not match
uint8_t ADDR_FREE_EN: 1; // 0: disable; 1: enable node address match as stand-alone working
uint8_t ADDR_SPLIT_MODE: 1; // 0: disable, dest_addr==node_addr; 1: enable, node_addr==src_addr+des_addr
uint8_t RESV_1: 1;
} _BITS;
uint8_t ADDR_CFG_REG; //CTL_REG_64, 0x40
} ADDR_CFG_u;
uint8_t SRC_ADDR[2]; //CTL_REG_65, CTL_REG_66
uint8_t DEST_ADDR[2]; //CTL_REG_67, CTL_REG_68
uint8_t SRC_BITMASK[2]; //CTL_REG_69, CTL_REG_70
uint8_t DEST_BITMASK[2]; //CTL_REG_71, CTL_REG_72
} ADDR_CFG;
//## packet crc config
typedef struct
{
union
{
struct
{
uint8_t CRC_EN: 1; // 0:disable CRC; 1:enable CRC
uint8_t CRC_BIT_ORDER: 1; // 0:crc result MSB output first; 1:crc result LSB output first; active unit is byte
uint8_t CRC_REFIN: 1; // 0:normal input; 1:inverse input;
uint8_t CRC_RANGE: 1; // 0:whole payload; 1:only data
uint8_t CRC_BIT_INV: 1; // 0:crc result non-invert; 1:crc result all bits invert
uint8_t CRC_BYTE_SWAP: 1; // 0:crc result HighByte output first; 1:crc result LowByte output first
uint8_t CRC_SIZE: 2; // 0:crc8; 1:crc16; 2:crc24; 3:crc32
uint8_t CRC_REFOUT: 1; // 0:result whole bit MSB->LSB 1:result whole bit LSB->MSB
uint8_t CRCERR_CLR_FIFO_EN: 1; // 0:disable 1:enable when crc error, clear fifo function
uint8_t RESV_6: 6;
} _BITS;
uint16_t CRC_CFG_REG; //CTL_REG_73, 0x49 & CTL_REG_82[7] & CTL_REG_84[7]
} CRC_CFG_u;
union //CTL_REG_74-CTL_REG_77, 0x4A-0x4D //## note: for arm mcu uint32_t is 32bits
{
uint8_t u8_SEED[4];
uint32_t u32_SEED;
} CRC_SEED_u;
union //CTL_REG_78-CTL_REG_81, 0x4E-0x51 //## note: for arm mcu uint32_t is 32bits
{
uint8_t u8_POLY[4];
uint32_t u32_POLY;
} CRC_POLY_u;
} CRC_CFG;
//## packet encode/decode format config
typedef struct
{
union
{
struct
{
uint8_t MANCH_EN: 1; // 0:disable manchester coding; 1:enable manchester coding
uint8_t MANCH_TYPE: 1; // 0: 2'b01=1, 2'b10=0; 1: 2'b01=0, 2'b10=1
uint8_t WHITEN_EN: 1; // 0:disable whiten coding; 1:enable whiten coding
uint8_t WHITEN_TYPE: 2; // 0:PN9-CCITT, 1:PN9-IBM, 2:PN7, 3:NA
uint8_t WHITEN_SEED_TYP: 1; // 0:compatible A7139; 1:customer seed; note: when select PN7 active
uint8_t RESV_2: 2;
uint8_t FEC_EN: 1; // 0:disable FEC Coding; 1:enable FEC Coding
uint8_t FEC_RSC_NRNSC_SEL: 1; // 0:RSC Mode; 1:NRNSC Mode
uint8_t RESV_5: 5;
uint8_t FEC_TICC: 1; // 0:ui invert ouput in FEC calucate; 1:ui non-invert ouput in FEC calucate
} _BITS;
uint16_t CODING_CFG_REG; // CTL_REG_82, 0x52 & CTL_REG_93, 0x5D
} CODING_FORMAT_CFG_u;
uint16_t WHITEN_SEED; // CTL_REG_83, 0x53 & CTL_REG_82[6]
uint16_t FEC_PAD_CODE; // CTL_REG_94, 0x5E & CTL_REG_93[6:2], 0x5D
} CODING_FORMAT_CFG;
//## frame struct config
typedef struct
{
uint8_t DATA_MODE; //0: direct mode; 2: packet mode; 1&3: na
union
{
struct
{
uint8_t PKT_TYPE: 1; //0: fixed length; 1: variable length
uint8_t PAYLOAD_BIT_ORDER: 1; //0: MSB output first; 1: LSB output first
uint8_t ADDR_LEN_CONF: 1; //0: node_addr+length; 1: length+node_addr
uint8_t ADDR_FIELD_EN: 1; //0: disable; 1: enable address field
uint8_t PAGGYBACKING_EN: 1; //0: disable 1: enable
uint8_t LENGTH_SIZE: 1; //0: length range 1 byte; 1: length range 2 bytes
uint8_t RESV_1_2: 1;
uint8_t INTERLEAVE_EN: 1; //0: disable interleave 1: enable interleave
} _BITS;
uint8_t FRAME_CFG1_REG; //CTL_REG_63, 0x3F
} FRAME_CFG1_u;
union
{
struct
{
uint8_t TX_PREFIX_TYPE: 2; //0:transmit_0; 1:transmit_1; 2:transmit_preamble 3:NA
uint8_t SEQNUM_EN: 1; //0:disable; 1:enable; note: SEQ_NUM is the same with FCS1
uint8_t SEQNUM_AUTO_INC: 1; //0:disable SEQNUM increase; 1:enable
uint8_t SEQNUM_SIZE: 1; //0:1byte for SEQNUM; 1:2bytes for SEQNUM
uint8_t SEQNUM_MACH_EN: 1; //0:disable; 1:enable compare with local SEQNUM, when TX_ACK enable
uint8_t FCS2_EN: 1; //0:not include FCS2 filed; 1:include FCS2 filed
uint8_t RESV_1: 1;
} _BITS;
uint8_t FRAME_CFG2_REG; //CTL_REG_84, 0x54
} FRAME_CFG2_u;
uint16_t TX_PKT_NUM; //CTL_REG_85, 0x55[7:0] & CTL_REG_86, 0x56[15:8]
uint16_t SEQNUM_TX_IN; //CTL_REG_88/87, 0x58[15:8], 0x57[7:0]
uint16_t SEQNUM_TX_CURRENT_OUT; //CTL_REG_39/38, 0x27[15:8]/0x26[7:0]
uint8_t TX_PKT_GAP; //CTL_REG_89, 0x59
uint8_t FCS2_TX_IN; //CTL_REG_91, 0x5B
uint8_t FCS2_RX_OUT; //CTL_REG_92, 0x5C
uint16_t PAYLOAD_LENGTH; //CTL_REG_62/61, 0x3E[15:8], 0x3D[7:0]
} FRAME_CFG;
//## Wi-SUN V1.0 packet format compatible
typedef union
{
struct
{
uint8_t WISUN_DW: 1; // 0:not whiten, 1: whiten
uint8_t WISUN_FCS: 1; // 0:CRC-32 for PSDU, 1: CRC-16 for PSDU
uint8_t RESV_2: 2; //
uint8_t WISUN_MS: 1; // default for 0
uint8_t WHITEN_WISUN: 1; // 0: for normal used, 1: for Wi-SUN whitenning
uint8_t WISUN_ALLIN: 1; // 0: WISUN_FCS & WISUN_DW not active, 1: FCS & DW depend on WISUN_FCS & WISUN_DW,
uint8_t LENGTH_MODE: 1; // 0: for normal used, 1: for Wi-SUN used, PSDU length filed is 11bits
} _BITS;
uint8_t WI_SUN_REG; //CTL_REG_111, 0x6F
} WI_SUN_CFG;
//## working mode
typedef struct
{
union
{
struct
{
uint8_t TX_DC_EN: 1; //0:disable TxDutyCycle; 1:enable
uint8_t TX_DC_PERSIST_EN: 1; //0:run TX_DC_TIMES; 1:always run until this bit set 0
uint8_t TX_ACK_EN: 1; //0:disable 1:enable
uint8_t TX_AUTO_HOP_EN: 1; //0:disable 1:enable tx frequency auto hopping
uint8_t TX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
uint8_t RESV: 1;
} _BITS;
uint8_t WORK_MODE_CFG1_REG; //CTL_REG_96, 0x60
} WORK_MODE_CFG1_u;
union
{
struct
{
uint8_t RX_DC_EN: 1; //0:disable RxDutyCycle; 1:enable
uint8_t RX_AUTO_HOP_EN: 1; //0:disable RxAutoHop; 1:enable
uint8_t RX_ACK_EN: 1; //0:disable 1:enable
uint8_t RX_TIMER_EN: 1; //0:disable 1:enable
uint8_t RX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
uint8_t CSMA_EN: 1; //0:disable 1:enable
} _BITS;
uint8_t WORK_MODE_CFG2_REG; //CTL_REG_97, 0x61
} WORK_MODE_CFG2_u;
union
{
struct
{
uint8_t SLP_MODE: 4; //14 items for select
uint8_t RX_HOP_SLP_MODE: 3; //7 items for select
uint8_t PKT_DONE_EXIT_EN: 1; //0:keep on current state; 1:depends on RX_EXIT_STATE
} _BITS;
uint8_t WORK_MODE_CFG3_REG; //CTL_REG_98, 0x62
} WORK_MODE_CFG3_u;
union
{
struct
{
uint8_t LFCLK_OUT_EN: 1; //0:disable; 1:enable LFCLK output to GPIO4
uint8_t LFCLK_SEL: 1; //0:LFOSC; 1:LFXO (32768Hz)
uint8_t RESV_1: 1; //
uint8_t SLEEP_TIMER_EN: 1; //0:disable 1:enable
uint8_t TIMER_RAND_MODE: 2; //00:random R, 01:random M, 10:both M&R random, 11:depends on config value
uint8_t RESV_2: 2;
} _BITS;
uint8_t WORK_MODE_CFG4_REG; //CTL_REG_105, 0x69
} WORK_MODE_CFG4_u;
union
{
struct
{
uint8_t CSMA_CCA_WIN_SEL: 2; //00:32symbol, 01:64symbol, 10:128symbol, 11:256symbol
uint8_t CSMA_CCA_INT_SEL: 2; //00:PJD, 01:RSSI, 10:PJD & RSSI, 11:NA
uint8_t CSMA_PERSIST_EN: 1; //0:auto exit when reach max & channel still busy, 1:keep on work until send out
uint8_t CSMA_CCA_MODE: 3; //000:idle, 001:>=1 RSSI, 010:>=1 PJD, 011:>=1 RSSI or PJD,
//100:>=1 SYNC, 101:>=1 SYNC or RSSI, 110:>=1 SYNC or PJD, 111:>=1 SYNC or PJD or RSSI
} _BITS;
uint8_t WORK_MODE_CFG5_REG; //CTL_REG_106, 0x6A
} WORK_MODE_CFG5_u;
union
{
struct
{
uint8_t RESV_5: 5;
uint8_t FREQ_SW_STATE: 1; //0:switch to RFS/TFS, and then to the next channel; 1:switch to RDY, and then to the next channel;
uint8_t RX_HOP_PERSIST: 1; //0:depend on TX/RX_EXIT_STATE, 1:go on next cycle from 0 label
uint8_t FREQ_HOP_MANU_EN: 1; //0:auto hopping mode; 1:hopping by manual
} _BITS;
uint8_t WORK_MODE_CFG6_REG;
} WORK_MODE_CFG6_u; //CTL_REG_22, 0x16
uint8_t FREQ_CHANL_NANU; //CTL_REG_3, 0x03, frequency hopping by manual, set channel number
uint8_t FREQ_DONE_TIMES; //CTL_REG_11, 0x0B, auto frequency hopping times have done
uint8_t FREQ_SPACE; //CTL_REG_12, 0x0C, auto frequency channel interval
uint8_t FREQ_TIMES; //CTL_REG_13, 0x0D, auto frequency hopping set range, 1-64
uint16_t SLEEP_TIMER_M; //CTL_REG_100[7:5]|CLT_REG_99, 11bits, 0x64,0x63
uint8_t SLEEP_TIMER_R; //CTL_REG_100[4:0], 0x64
uint16_t RX_TIMER_T1_M; //CTL_REG_102[7:5]|CLT_REG_101, 11bits, 0x66, 0x65
uint8_t RX_TIMER_T1_R; //CTL_REG_102[4:0], 0x66
uint16_t RX_TIMER_T2_M; //CTL_REG_104[7:5]|CLT_REG_103, 11bits, 0x68, 0x67
uint8_t RX_TIMER_T2_R; //CTL_REG_104[4:0], 0x68
uint16_t RX_TIMER_CSMA_M; //CTL_REG_108[7:5]|CLT_REG_107, 11bits, 0x6C,0x6B
uint8_t RX_TIMER_CSMA_R; //CTL_REG_108[4:0], 0x6C
uint8_t TX_DC_TIMES; //CTL_REG_110, 0x6E, tx duty cycle, set maximum times
uint8_t TX_DC_DONE_TIMES; //CTL_REG_112, 0x70, tx duty cycle, times have done
uint8_t TX_RS_TIMES; //CTL_REG_113, 0x71, tx ack mode, set maximum times
uint8_t TX_RS_DONE_TIMES; //CLT_REG_114, 0x72, tx ack mode, times have done
uint8_t CSMA_TIMES; //CTL_REG_115, 0x73, csma, set maximum times
uint8_t CSMA_DONE_TIMES; //CTL_REG_116, 0x74, csma, times have done
uint16_t SLEEP_TIMER_CSMA_M; //CTL_REG_119[7:5]|CTL_REG_118, 11bits
uint8_t SLEEP_TIMER_CSMA_R; //CTL_REG_119, 0x77[4:0]
} WORK_MODE_CFG;
//## RSSI config (in page1)
typedef struct
{
union
{
struct
{
uint8_t COLL_DET_EN: 1; //0: disable, 1: enable collision detect;
uint8_t RESV_1: 1;
uint8_t RSSI_UPDATE_SEL: 2; //0:always update, 1:when PREAM_OK, 2:when SYNC_OK, 3:when PKT_DONE
uint8_t COLL_STEP_SEL: 2; //0:6dB, 1:10dB, 2:16dB 3:20dB
uint8_t RESV_2: 2;
} _BITS;
uint8_t RSSI_CFG_REG; //RX_RSSI_REG_00, 0x62, page1
} FRAME_CFG1_u;
uint8_t RSSI_ABS_TH; //RX_RSSI_REG_01, 0x63, page1
} RSSI_CFG;
//## Antenna config (in page0 & page1)
typedef struct
{
union
{
struct
{
uint8_t ANT_SELECT: 1; //0: antenna1, 1: antenna2, for antenna diversity manual mode
uint8_t ANT_DIV_MANU: 1; //0: auto antenna diversity, 1: manual antenna diversity
uint8_t RESV_6: 6;
} _BITS;
uint8_t ANT_CFG1_REG; // CTL_REG_02, 0x02, page0
} ANT_CFG1_u;
union
{
struct
{
uint8_t ANT_INSTR: 1; //0: antenna1 was used, 1: antenna2 was used, for indicate which antenna was used in antenna diversity auto mode
uint8_t RESV_7: 6;
} _BITS;
uint8_t ANT_CFG2_REG; // CTL_REG_14, 0x0E, page0
} ANT_CFG2_u;
union
{
struct
{
uint8_t ANT_DIV_EN: 1; //0: disable, 1: enable antenna diversity
uint8_t ANT_SW_DIS: 1; //0: enable, 1: disable antenna diversity switch
uint8_t ANT_WAIT_PMB: 2; //0: RX_PREAM_SIZE x1.5, 1: RX_PREAM_SIZE x2, 2: RX_PREAM_SIZE x2.5, 3: RX_PREAM_SIZE x3
uint8_t RESV_4: 4;
} _BITS;
uint8_t RX_ANTD_REG; //RX_ANTD_REG_00, 0x67, page1
} ANT_CFG3_u;
} ANT_DIV_CFG;
//## CDR Tracing (in page1)
typedef struct
{
union
{
struct
{
uint8_t CDR_MODE: 2; //0:tracing, 1:counting, 2:manchester, 3:no_cdr
uint8_t CDR_RANGE_SEL: 2; //0:+/-6.3%, 1:+/-9.4%, 2:+/-12.5%, 3:+/-15.6%
uint8_t CDR_AVG_SEL: 3; //0:48/64, 1:32/64 2:24/64 3:16/64, 4:11/64 5:8/64 6:6/64 7:4/64
uint8_t CDR_DET_SEL: 1; //0:mode0, 1:mode1(recommand)
} _BITS;
uint8_t CDR_CFG0_REG; //RX_CDR_REG_00, 0x44, page1
} CDR_CFG0_u;
union
{
struct
{
uint8_t RESV_3: 3; //CDR_BR_TH<18:16>
uint8_t CDR_3RD_EN: 1; //0:disable, 1:enable
uint8_t CDR_4TH_EN: 1; //0:disable, 1:enable
uint8_t RESV_3_2: 3; //0:mode0, 1:mode1(recommend)
} _BITS;
uint8_t CDR_CFG1_REG; //RX_CDR_REG_00, 0x44, page1
} CDR_CFG1_u;
uint32_t CDR_BR_TH; //RX_CDR_REG_03<18:16> & RX_CDR_REG_02<15:8> & RX_CDR_REG_01<7:0>, page1(0x47,0x45,0x46)
} CDR_TRACING_CFG;
enum CDR_MODE
{
CDR_SEL_TRACING = 0,
CDR_SEL_COUNTING = 1,
CDR_SEL_MANCHESTER = 2,
CDR_SEL_RAW = 3,
};
typedef struct
{
INT_SRC_CFG int_src_en;
INT_SRC_FLG int_src_flag;
INT_SRC_CLR int_src_clear;
FIFO_STATUS_FLG fifo_status_flag;
PREAMBLE_CFG preamble_cfg;
SYNC_CFG sync_cfg;
ADDR_CFG addr_cfg;
CRC_CFG crc_cfg;
CODING_FORMAT_CFG coding_format_cfg;
FRAME_CFG frame_cfg;
WI_SUN_CFG wi_sun_cfg;
WORK_MODE_CFG word_mode_cfg;
RSSI_CFG rssi_cfg;
ANT_DIV_CFG antenna_cfg;
CDR_TRACING_CFG cdr_tracing_cfg;
} CMT2310A_CFG;
#endif
//******************************************************************************
//* EOF (not truncated)
//******************************************************************************

578
NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h.orig Executable file
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@ -0,0 +1,578 @@
/*
* THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND
* (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
* CONSEQUENTLY, CMOSTEK SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* Copyright (C) CMOSTEK SZ.
*/
/*!
* @file CMT2310A_def.h
* @brief CMT2310A transceiver RF chip driver
*
* @version 1.0
* @date Dec 7 2021
* @author CMOSTEK R&D
*/
#ifndef __CMT2310A_DEF_H
#define __CMT2310A_DEF_H
//Exit State
#define EXIT_TO_SLEEP 1
#define EXIT_TO_READY 2
#define EXIT_TO_TFS 3
#define EXIT_TO_TX 4
#define EXIT_TO_RFS 5
#define EXIT_TO_RX 6
//Prefxi select
#define TX_PREFIX_SEL_0 0
#define TX_PREFIX_SEL_1 1
#define TX_PREFIX_SEL_PREAMBLE 2
//## interrupt source config
typedef union
{
struct
{
uint8_t PKT_DONE_EN: 1; //pkt_done_en //bit0
uint8_t CRC_PASS_EN: 1; //crc_pass_en //bit1
uint8_t ADDR_PASS_EN: 1; //node_address_pass_en //bit2
uint8_t SYNC_PASS_EN: 1; //sync_pass_en //bit3
uint8_t PREAM_PASS_EN: 1; //preamble_pass_en //bit4
uint8_t TX_DONE_EN: 1; //tx_done_en //bit5
uint8_t RX_TOUT_EN: 1; //rx_timeout_en //bit6
uint8_t SLP_TOUT_EN: 1; //sleep_timeout_en //bit7
uint8_t LD_STOP_EN: 1; //ld_stop_en(PLL lock detect)//bit0
uint8_t LBD_STOP_EN: 1; //lbd_stop_en //bit1
uint8_t LBD_STAT_EN: 1; //lbd_status_en //bit2
uint8_t PKT_ERR_EN: 1; //pkt_err_en //bit3
uint8_t RSSI_COLL_EN: 1; //rssi_collision_en //bit4
uint8_t OP_CMD_FAILED_EN: 1; //op_cmd_failed_en //bit5
uint8_t RSSI_PJD_EN: 1; //rssi_pjd_valid_en //bit6
uint8_t RESV_2_1: 1; //reserve, don't used //bit7
uint8_t SEQ_MATCH_EN: 1; //seq_match_en //bit0
uint8_t NACK_RECV_EN: 1; //nack_recv_en //bit1
uint8_t TX_RESEND_DONE_EN: 1; //tx_resend_done_en //bit2
uint8_t ACK_RECV_FAILED_EN: 1; //ack_recv_failed_en //bit3
uint8_t TX_DC_DONE_EN: 1; //tx_dc_done_en //bit4
uint8_t CSMA_DONE_EN: 1; //csma_max_en //bit5
uint8_t CCA_STAT_EN: 1; //cca_status_en //bit6
uint8_t API_DONE_EN: 1; //api_done_en //bit7
uint8_t TX_FIFO_TH_EN: 1; //tx_fifo_threshold_en //bit0
uint8_t TX_FIFO_NMTY_EN: 1; //tx_fifo_non_empty_en //bit1
uint8_t TX_FIFO_FULL_EN: 1; //tx_fifo_full_en //bit2
uint8_t RX_FIFO_OVF_EN: 1; //rx_fifo_overflow_en //bit3
uint8_t RESV_4_1: 1; //reserve, don't used //bit4
uint8_t RX_FIFO_TH_EN: 1; //rx_fifo_threshold_en //bit5
uint8_t RX_FIFO_NMTY_EN: 1; //rx_fifo_non_empty_en //bit6
uint8_t RX_FIFO_FULL_EN: 1; //rx_fifo_full_en //bit7
}_BITS;
struct
{
uint8_t INT_CTL1_REG; //CTL_REG_18, 0x12
uint8_t INT_CTL2_REG; //CTL_REG_21, 0x15
uint8_t INT_CTL3_REG; //CTL_REG_23, 0x17
uint8_t INT_CTL4_REG; //CTL_REG_14, 0x0E
}_BYTE;
}INT_SRC_CFG;
//## interrupt flag
typedef union
{
struct
{
uint8_t RESV_3: 3; //reserve, don't used //bit0/1/2
uint8_t TX_DONE_FLG: 1; //tx_done_flag //bit3
uint8_t RX_TMO_FLG: 1; //rx_timer_timeout_flag //bit4
uint8_t SLEEP_TMO_FLG: 1; //sleep_timer_timeout_flag //bit5
uint8_t RESV_2: 2; //reserve, don't used //bit6/7
uint8_t PKT_DONE_FLG: 1; //pkt_done_flag //bit0
uint8_t CRC_PASS_FLG: 1; //crc_pass_flag //bit1
uint8_t ADDR_PASS_FLG: 1; //addr_pass_flag //bit2
uint8_t SYNC_PASS_FLG: 1; //sync_pass_flag //bit3
uint8_t PREAM_PASS_FLG: 1; //preamble_pass_flag //bit4
uint8_t SYNC1_PASS_FLG: 1; //sync1_pass_flag //bit5
uint8_t RESV_2_2: 2; //reserve, don't used //bit6/7
uint8_t LBD_STATUS_FLG: 1; //lbd_status_flag //bit0
uint8_t PKT_ERR_FLG: 1; //pkt_err_flag //bit1
uint8_t RSSI_COLL_FLG: 1; //rssi_collision_flag //bit2
uint8_t OP_CMD_FAILED_FLG: 1; //op_cmd_failed_flag //bit3
uint8_t ANT_LOCK_FLG: 1; //ant_lock_flag //bit4
uint8_t RESV_3_3: 3; //reserve, don't used //bit5/6/7
uint8_t SEQ_MATCH_FLG: 1; //seq_match_flag //bit0
uint8_t NACK_RECV_FLG: 1; //nack_recv_flag //bit1
uint8_t TX_RESEND_DONE_FLG: 1; //tx_resend_max_flag //bit2
uint8_t ACK_RECV_FAILED_FLG: 1; //ack_recv_failed_flag //bit3
uint8_t TX_DC_DONE_FLG: 1; //tx_dc_done_flag //bit4
uint8_t CSMA_DONE_FLG: 1; //csma_done_flag //bit5
uint8_t CCA_STATUS_FLG: 1; //cca_status_flag //bit6
uint8_t API_DONE_FLG: 1; //api_done_flag //bit7
}_BITS;
struct
{
uint8_t INT_FLAG1_REG; //CTL_REG_24, 0x18
uint8_t INT_FLAG2_REG; //CTL_REG_26, 0x1A
uint8_t INT_FLAG3_REG; //CTL_REG_30, 0x1E
uint8_t INT_FLAG4_REG; //CTL_REG_32, 0x20
}_BYTE;
}INT_SRC_FLG;
//## interrupt clear
typedef union
{
struct
{
uint8_t TX_DONE_CLR: 1; //tx_done_clr //bit0
uint8_t RX_TMO_CLR: 1; //rx_timer_timeout_clr //bit1
uint8_t SLEEP_TMO_CLR: 1; //sleep_timer_timeout_clr //bit2
uint8_t RESV_5: 5; //reserve, don't used //bit3-7
uint8_t PKT_DONE_CLR: 1; //pkt_done_clr //bit0
uint8_t CRC_PASS_CLR: 1; //crc_pass_clr //bit1
uint8_t ADDR_PASS_CLR: 1; //addr_pass_clr //bit2
uint8_t SYNC_PASS_CLR: 1; //sync_pass_clr //bit3
uint8_t PREAM_PASS_CLR: 1; //preamble_pass_clr //bit4
uint8_t RESV_3: 3; //reserve, don't used //bit5/6/7
uint8_t LBD_STAT_CLR: 1; //lbd_status_clr //bit0
uint8_t PKT_ERR_CLR: 1; //packet_err_clr //bit1
uint8_t RSSI_COLL_CLR: 1; //rssi_collision_clr //bit2
uint8_t OP_CMD_FAILED_CLR: 1; //op_cmd_failed_clr //bit3
uint8_t ANT_LOCK_CLR: 1; //antenna_lock_clr //bit4
uint8_t RESV_2_3: 3; //reserve, don't used //bit5/6/7
uint8_t SEQ_MATCH_CLR: 1; //seq_match_clr //bit0
uint8_t NACK_RECV_CLR: 1; //nack_recv_clr //bit1
uint8_t TX_RESEND_DONE_CLR: 1; //tx_resend_done_clr //bit2
uint8_t ACK_RECV_FAILED_CLR: 1; //ack_recv_failed_clr //bit3
uint8_t TX_DC_DONE_CLR: 1; //tx_dc_done_clr //bit4
uint8_t CSMA_DONE_CLR: 1; //csma_done_clr //bit5
uint8_t CCA_STATUS_CLR: 1; //cca_status_clr //bit6
uint8_t API_DONE_CLR: 1; //api_done_clr //bit7
}_BITS;
struct
{
uint8_t INT_CLR1_REG; //CTL_REG_24, 0x18
uint8_t INT_CLR2_REG; //CTL_REG_25, 0x19
uint8_t INT_CLR3_REG; //CTL_REG_29, 0x1D
uint8_t INT_CLR4_REG; //CTL_REG_31, 0x1F
}_BYTE;
}INT_SRC_CLR;
//## fifo status flag
typedef union
{
struct
{
uint8_t TX_FIFO_TH_FLG: 1; //tx_fifo_threshold_flag //bit0
uint8_t TX_FIFO_NMTY_FLG: 1; //tx_fifo_non_empty_flag //bit1
uint8_t TX_FIFO_FULL_FLG: 1; //tx_fifo_full_flag //bit2
uint8_t RX_FIFO_OVF_FLG: 1; //rx_fifo_overflow_flag //bit3
uint8_t RESV_1: 1; //reserve, don't used //bit4
uint8_t RX_FIFO_TH_FLG: 1; //rx_fifo_threshold_flag //bit5
uint8_t RX_FIFO_NMTY_FLG: 1; //rx_fifo_non_empty_flag //bit6
uint8_t RX_FIFO_FULL_FLG: 1; //rx_fifo_full_flag //bit7
}_BITS;
uint8_t FIFO_FLG_REG; //CTL_REG_28, 0x1c
}FIFO_STATUS_FLG;
//## packet preamble config
typedef struct //Packet Preamble
{
uint8_t PREAM_LENG_UNIT; //0=preamble unit as 8bits, !0=preamble unit as 4bits (nibble mode)
uint8_t PREAM_VALUE; //preamble value
uint8_t RX_PREAM_SIZE; //rx preamble length, range: 0-31, 0==disable rx preamble detect
uint16_t TX_PREAM_SIZE; //tx preamble length //## note: for arm mcu uint16_t is 16bits
}PREAMBLE_CFG;
//## packet syncword config
typedef struct
{
union
{
struct
{
uint8_t SYNC_MAN_EN: 1; //sync word manchester coding enable
uint8_t SYNC_SIZE: 3; // n+1 bytes
uint8_t SYNC_TOL: 3; // n bits tolerence error
uint8_t SYNC_MODE_SEL: 1; // 0: compatible S2LP; 1: compatible 802.15.4
}_BITS;
uint8_t SYNC_CFG_REG; //CTL_REG_44, 0x2c
}SYN_CFG_u;
uint8_t SYNC_VALUE[8]; //CTL_REG_45-CTL_REG_53, 0x2D-0x34
uint8_t SYNC_FEC_VALUE[8]; //CTL_REG_53-CTL_REG_60, 0x35-0x3C
uint8_t SYNC_VALUE_SEL; // 0: select SYN_VAL; !0: select SYN_FEC_VAL
}SYNC_CFG;
//## packet node address config
typedef struct
{
union
{
struct
{
uint8_t ADDR_DET_MODE: 2; //node address mode: 0,disable; 1,only match; 2,add all 0; 3,add all 1 & 0
uint8_t ADDR_SIZE: 2; // n+1 bytes
uint8_t ADDR_ERR_MASK: 1; // 0: trigger PKT_ERR flag, when node address not match, and reset decode; 1: non-reset decode, when node address not match
uint8_t ADDR_FREE_EN: 1; // 0: disable; 1: enable node address match as stand-alone working
uint8_t ADDR_SPLIT_MODE: 1; // 0: disable, dest_addr==node_addr; 1: enable, node_addr==src_addr+des_addr
uint8_t RESV_1: 1;
}_BITS;
uint8_t ADDR_CFG_REG; //CTL_REG_64, 0x40
}ADDR_CFG_u;
uint8_t SRC_ADDR[2]; //CTL_REG_65, CTL_REG_66
uint8_t DEST_ADDR[2]; //CTL_REG_67, CTL_REG_68
uint8_t SRC_BITMASK[2]; //CTL_REG_69, CTL_REG_70
uint8_t DEST_BITMASK[2]; //CTL_REG_71, CTL_REG_72
}ADDR_CFG;
//## packet crc config
typedef struct
{
union
{
struct
{
uint8_t CRC_EN: 1; // 0:disable CRC; 1:enable CRC
uint8_t CRC_BIT_ORDER: 1; // 0:crc result MSB output first; 1:crc result LSB output first; active unit is byte
uint8_t CRC_REFIN: 1; // 0:normal input; 1:inverse input;
uint8_t CRC_RANGE: 1; // 0:whole payload; 1:only data
uint8_t CRC_BIT_INV: 1; // 0:crc result non-invert; 1:crc result all bits invert
uint8_t CRC_BYTE_SWAP: 1; // 0:crc result HighByte output first; 1:crc result LowByte output first
uint8_t CRC_SIZE: 2; // 0:crc8; 1:crc16; 2:crc24; 3:crc32
uint8_t CRC_REFOUT: 1; // 0:result whole bit MSB->LSB 1:result whole bit LSB->MSB
uint8_t CRCERR_CLR_FIFO_EN: 1; // 0:disable 1:enable when crc error, clear fifo function
uint8_t RESV_6: 6;
}_BITS;
uint16_t CRC_CFG_REG; //CTL_REG_73, 0x49 & CTL_REG_82[7] & CTL_REG_84[7]
}CRC_CFG_u;
union //CTL_REG_74-CTL_REG_77, 0x4A-0x4D //## note: for arm mcu uint32_t is 32bits
{
uint8_t u8_SEED[4];
uint32_t u32_SEED;
}CRC_SEED_u;
union //CTL_REG_78-CTL_REG_81, 0x4E-0x51 //## note: for arm mcu uint32_t is 32bits
{
uint8_t u8_POLY[4];
uint32_t u32_POLY;
}CRC_POLY_u;
}CRC_CFG;
//## packet encode/decode format config
typedef struct
{
union
{
struct
{
uint8_t MANCH_EN: 1; // 0:disable manchester coding; 1:enable manchester coding
uint8_t MANCH_TYPE: 1; // 0: 2'b01=1, 2'b10=0; 1: 2'b01=0, 2'b10=1
uint8_t WHITEN_EN: 1; // 0:disable whiten coding; 1:enable whiten coding
uint8_t WHITEN_TYPE: 2; // 0:PN9-CCITT, 1:PN9-IBM, 2:PN7, 3:NA
uint8_t WHITEN_SEED_TYP: 1; // 0:compatible A7139; 1:customer seed; note: when select PN7 active
uint8_t RESV_2: 2;
uint8_t FEC_EN: 1; // 0:disable FEC Coding; 1:enable FEC Coding
uint8_t FEC_RSC_NRNSC_SEL: 1; // 0:RSC Mode; 1:NRNSC Mode
uint8_t RESV_5: 5;
uint8_t FEC_TICC: 1; // 0:ui invert ouput in FEC calucate; 1:ui non-invert ouput in FEC calucate
}_BITS;
uint16_t CODING_CFG_REG; // CTL_REG_82, 0x52 & CTL_REG_93, 0x5D
}CODING_FORMAT_CFG_u;
uint16_t WHITEN_SEED; // CTL_REG_83, 0x53 & CTL_REG_82[6]
uint16_t FEC_PAD_CODE; // CTL_REG_94, 0x5E & CTL_REG_93[6:2], 0x5D
}CODING_FORMAT_CFG;
//## frame struct config
typedef struct
{
uint8_t DATA_MODE; //0: direct mode; 2: packet mode; 1&3: na
union
{
struct
{
uint8_t PKT_TYPE: 1; //0: fixed length; 1: variable length
uint8_t PAYLOAD_BIT_ORDER: 1; //0: MSB output first; 1: LSB output first
uint8_t ADDR_LEN_CONF: 1; //0: node_addr+length; 1: length+node_addr
uint8_t ADDR_FIELD_EN: 1; //0: disable; 1: enable address field
uint8_t PAGGYBACKING_EN: 1; //0: disable 1: enable
uint8_t LENGTH_SIZE: 1; //0: length range 1 byte; 1: length range 2 bytes
uint8_t RESV_1_2: 1;
uint8_t INTERLEAVE_EN: 1; //0: disable interleave 1: enable interleave
}_BITS;
uint8_t FRAME_CFG1_REG; //CTL_REG_63, 0x3F
}FRAME_CFG1_u;
union
{
struct
{
uint8_t TX_PREFIX_TYPE: 2; //0:transmit_0; 1:transmit_1; 2:transmit_preamble 3:NA
uint8_t SEQNUM_EN: 1; //0:disable; 1:enable; note: SEQ_NUM is the same with FCS1
uint8_t SEQNUM_AUTO_INC: 1; //0:disable SEQNUM increase; 1:enable
uint8_t SEQNUM_SIZE: 1; //0:1byte for SEQNUM; 1:2bytes for SEQNUM
uint8_t SEQNUM_MACH_EN: 1; //0:disable; 1:enable compare with local SEQNUM, when TX_ACK enable
uint8_t FCS2_EN: 1; //0:not include FCS2 filed; 1:include FCS2 filed
uint8_t RESV_1: 1;
}_BITS;
uint8_t FRAME_CFG2_REG; //CTL_REG_84, 0x54
}FRAME_CFG2_u;
uint16_t TX_PKT_NUM; //CTL_REG_85, 0x55[7:0] & CTL_REG_86, 0x56[15:8]
uint16_t SEQNUM_TX_IN; //CTL_REG_88/87, 0x58[15:8], 0x57[7:0]
uint16_t SEQNUM_TX_CURRENT_OUT; //CTL_REG_39/38, 0x27[15:8]/0x26[7:0]
uint8_t TX_PKT_GAP; //CTL_REG_89, 0x59
uint8_t FCS2_TX_IN; //CTL_REG_91, 0x5B
uint8_t FCS2_RX_OUT; //CTL_REG_92, 0x5C
uint16_t PAYLOAD_LENGTH; //CTL_REG_62/61, 0x3E[15:8], 0x3D[7:0]
}FRAME_CFG;
//## Wi-SUN V1.0 packet format compatible
typedef union
{
struct
{
uint8_t WISUN_DW: 1; // 0:not whiten, 1: whiten
uint8_t WISUN_FCS: 1; // 0:CRC-32 for PSDU, 1: CRC-16 for PSDU
uint8_t RESV_2: 2; //
uint8_t WISUN_MS: 1; // default for 0
uint8_t WHITEN_WISUN: 1; // 0: for normal used, 1: for Wi-SUN whitenning
uint8_t WISUN_ALLIN: 1; // 0: WISUN_FCS & WISUN_DW not active, 1: FCS & DW depend on WISUN_FCS & WISUN_DW,
uint8_t LENGTH_MODE: 1; // 0: for normal used, 1: for Wi-SUN used, PSDU length filed is 11bits
}_BITS;
uint8_t WI_SUN_REG; //CTL_REG_111, 0x6F
}WI_SUN_CFG;
//## working mode
typedef struct
{
union
{
struct
{
uint8_t TX_DC_EN: 1; //0:disable TxDutyCycle; 1:enable
uint8_t TX_DC_PERSIST_EN: 1; //0:run TX_DC_TIMES; 1:always run until this bit set 0
uint8_t TX_ACK_EN: 1; //0:disable 1:enable
uint8_t TX_AUTO_HOP_EN: 1; //0:disable 1:enable tx frequency auto hopping
uint8_t TX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
uint8_t RESV: 1;
}_BITS;
uint8_t WORK_MODE_CFG1_REG; //CTL_REG_96, 0x60
}WORK_MODE_CFG1_u;
union
{
struct
{
uint8_t RX_DC_EN: 1; //0:disable RxDutyCycle; 1:enable
uint8_t RX_AUTO_HOP_EN: 1; //0:disable RxAutoHop; 1:enable
uint8_t RX_ACK_EN: 1; //0:disable 1:enable
uint8_t RX_TIMER_EN: 1; //0:disable 1:enable
uint8_t RX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
uint8_t CSMA_EN: 1; //0:disable 1:enable
}_BITS;
uint8_t WORK_MODE_CFG2_REG; //CTL_REG_97, 0x61
}WORK_MODE_CFG2_u;
union
{
struct
{
uint8_t SLP_MODE: 4; //14 items for select
uint8_t RX_HOP_SLP_MODE: 3; //7 items for select
uint8_t PKT_DONE_EXIT_EN: 1; //0:keep on current state; 1:depends on RX_EXIT_STATE
}_BITS;
uint8_t WORK_MODE_CFG3_REG; //CTL_REG_98, 0x62
}WORK_MODE_CFG3_u;
union
{
struct
{
uint8_t LFCLK_OUT_EN: 1; //0:disable; 1:enable LFCLK output to GPIO4
uint8_t LFCLK_SEL: 1; //0:LFOSC; 1:LFXO (32768Hz)
uint8_t RESV_1: 1; //
uint8_t SLEEP_TIMER_EN: 1; //0:disable 1:enable
uint8_t TIMER_RAND_MODE: 2; //00:random R, 01:random M, 10:both M&R random, 11:depends on config value
uint8_t RESV_2: 2;
}_BITS;
uint8_t WORK_MODE_CFG4_REG; //CTL_REG_105, 0x69
}WORK_MODE_CFG4_u;
union
{
struct
{
uint8_t CSMA_CCA_WIN_SEL: 2; //00:32symbol, 01:64symbol, 10:128symbol, 11:256symbol
uint8_t CSMA_CCA_INT_SEL: 2; //00:PJD, 01:RSSI, 10:PJD & RSSI, 11:NA
uint8_t CSMA_PERSIST_EN: 1; //0:auto exit when reach max & channel still busy, 1:keep on work until send out
uint8_t CSMA_CCA_MODE: 3; //000:idle, 001:>=1 RSSI, 010:>=1 PJD, 011:>=1 RSSI or PJD,
//100:>=1 SYNC, 101:>=1 SYNC or RSSI, 110:>=1 SYNC or PJD, 111:>=1 SYNC or PJD or RSSI
}_BITS;
uint8_t WORK_MODE_CFG5_REG; //CTL_REG_106, 0x6A
}WORK_MODE_CFG5_u;
union
{
struct
{
uint8_t RESV_5: 5;
uint8_t FREQ_SW_STATE: 1; //0:switch to RFS/TFS, and then to the next channel; 1:switch to RDY, and then to the next channel;
uint8_t RX_HOP_PERSIST: 1; //0:depend on TX/RX_EXIT_STATE, 1:go on next cycle from 0 label
uint8_t FREQ_HOP_MANU_EN: 1; //0:auto hopping mode; 1:hopping by manual
}_BITS;
uint8_t WORK_MODE_CFG6_REG;
}WORK_MODE_CFG6_u; //CTL_REG_22, 0x16
uint8_t FREQ_CHANL_NANU; //CTL_REG_3, 0x03, frequency hopping by manual, set channel number
uint8_t FREQ_DONE_TIMES; //CTL_REG_11, 0x0B, auto frequency hopping times have done
uint8_t FREQ_SPACE; //CTL_REG_12, 0x0C, auto frequency channel interval
uint8_t FREQ_TIMES; //CTL_REG_13, 0x0D, auto frequency hopping set range, 1-64
uint16_t SLEEP_TIMER_M; //CTL_REG_100[7:5]|CLT_REG_99, 11bits, 0x64,0x63
uint8_t SLEEP_TIMER_R; //CTL_REG_100[4:0], 0x64
uint16_t RX_TIMER_T1_M; //CTL_REG_102[7:5]|CLT_REG_101, 11bits, 0x66, 0x65
uint8_t RX_TIMER_T1_R; //CTL_REG_102[4:0], 0x66
uint16_t RX_TIMER_T2_M; //CTL_REG_104[7:5]|CLT_REG_103, 11bits, 0x68, 0x67
uint8_t RX_TIMER_T2_R; //CTL_REG_104[4:0], 0x68
uint16_t RX_TIMER_CSMA_M; //CTL_REG_108[7:5]|CLT_REG_107, 11bits, 0x6C,0x6B
uint8_t RX_TIMER_CSMA_R; //CTL_REG_108[4:0], 0x6C
uint8_t TX_DC_TIMES; //CTL_REG_110, 0x6E, tx duty cycle, set maximum times
uint8_t TX_DC_DONE_TIMES; //CTL_REG_112, 0x70, tx duty cycle, times have done
uint8_t TX_RS_TIMES; //CTL_REG_113, 0x71, tx ack mode, set maximum times
uint8_t TX_RS_DONE_TIMES; //CLT_REG_114, 0x72, tx ack mode, times have done
uint8_t CSMA_TIMES; //CTL_REG_115, 0x73, csma, set maximum times
uint8_t CSMA_DONE_TIMES; //CTL_REG_116, 0x74, csma, times have done
uint16_t SLEEP_TIMER_CSMA_M; //CTL_REG_119[7:5]|CTL_REG_118, 11bits
uint8_t SLEEP_TIMER_CSMA_R; //CTL_REG_119, 0x77[4:0]
}WORK_MODE_CFG;
//## RSSI config (in page1)
typedef struct
{
union
{
struct
{
uint8_t COLL_DET_EN: 1; //0: disable, 1: enable collision detect;
uint8_t RESV_1: 1;
uint8_t RSSI_UPDATE_SEL: 2; //0:always update, 1:when PREAM_OK, 2:when SYNC_OK, 3:when PKT_DONE
uint8_t COLL_STEP_SEL: 2; //0:6dB, 1:10dB, 2:16dB 3:20dB
uint8_t RESV_2: 2;
}_BITS;
uint8_t RSSI_CFG_REG; //RX_RSSI_REG_00, 0x62, page1
}FRAME_CFG1_u;
uint8_t RSSI_ABS_TH; //RX_RSSI_REG_01, 0x63, page1
}RSSI_CFG;
//## Antenna config (in page0 & page1)
typedef struct
{
union
{
struct
{
uint8_t ANT_SELECT: 1; //0: antenna1, 1: antenna2, for antenna diversity manual mode
uint8_t ANT_DIV_MANU: 1; //0: auto antenna diversity, 1: manual antenna diversity
uint8_t RESV_6: 6;
}_BITS;
uint8_t ANT_CFG1_REG; // CTL_REG_02, 0x02, page0
}ANT_CFG1_u;
union
{
struct
{
uint8_t ANT_INSTR: 1; //0: antenna1 was used, 1: antenna2 was used, for indicate which antenna was used in antenna diversity auto mode
uint8_t RESV_7: 6;
}_BITS;
uint8_t ANT_CFG2_REG; // CTL_REG_14, 0x0E, page0
}ANT_CFG2_u;
union
{
struct
{
uint8_t ANT_DIV_EN: 1; //0: disable, 1: enable antenna diversity
uint8_t ANT_SW_DIS: 1; //0: enable, 1: disable antenna diversity switch
uint8_t ANT_WAIT_PMB: 2; //0: RX_PREAM_SIZE x1.5, 1: RX_PREAM_SIZE x2, 2: RX_PREAM_SIZE x2.5, 3: RX_PREAM_SIZE x3
uint8_t RESV_4: 4;
}_BITS;
uint8_t RX_ANTD_REG; //RX_ANTD_REG_00, 0x67, page1
}ANT_CFG3_u;
}ANT_DIV_CFG;
//## CDR Tracing (in page1)
typedef struct
{
union
{
struct
{
uint8_t CDR_MODE: 2; //0:tracing, 1:counting, 2:manchester, 3:no_cdr
uint8_t CDR_RANGE_SEL: 2; //0:+/-6.3%, 1:+/-9.4%, 2:+/-12.5%, 3:+/-15.6%
uint8_t CDR_AVG_SEL: 3; //0:48/64, 1:32/64 2:24/64 3:16/64, 4:11/64 5:8/64 6:6/64 7:4/64
uint8_t CDR_DET_SEL: 1; //0:mode0, 1:mode1(recommand)
}_BITS;
uint8_t CDR_CFG0_REG; //RX_CDR_REG_00, 0x44, page1
}CDR_CFG0_u;
union
{
struct
{
uint8_t RESV_3: 3; //CDR_BR_TH<18:16>
uint8_t CDR_3RD_EN: 1; //0:disable, 1:enable
uint8_t CDR_4TH_EN: 1; //0:disable, 1:enable
uint8_t RESV_3_2: 3; //0:mode0, 1:mode1(recommend)
}_BITS;
uint8_t CDR_CFG1_REG; //RX_CDR_REG_00, 0x44, page1
}CDR_CFG1_u;
uint32_t CDR_BR_TH; //RX_CDR_REG_03<18:16> & RX_CDR_REG_02<15:8> & RX_CDR_REG_01<7:0>, page1(0x47,0x45,0x46)
}CDR_TRACING_CFG;
enum CDR_MODE
{
CDR_SEL_TRACING = 0,
CDR_SEL_COUNTING = 1,
CDR_SEL_MANCHESTER = 2,
CDR_SEL_RAW = 3,
};
typedef struct
{
INT_SRC_CFG int_src_en;
INT_SRC_FLG int_src_flag;
INT_SRC_CLR int_src_clear;
FIFO_STATUS_FLG fifo_status_flag;
PREAMBLE_CFG preamble_cfg;
SYNC_CFG sync_cfg;
ADDR_CFG addr_cfg;
CRC_CFG crc_cfg;
CODING_FORMAT_CFG coding_format_cfg;
FRAME_CFG frame_cfg;
WI_SUN_CFG wi_sun_cfg;
WORK_MODE_CFG word_mode_cfg;
RSSI_CFG rssi_cfg;
ANT_DIV_CFG antenna_cfg;
CDR_TRACING_CFG cdr_tracing_cfg;
}CMT2310A_CFG;
#endif
//******************************************************************************
//* EOF (not truncated)
//******************************************************************************

1229
NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h Executable file
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428
NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_410mhz.c Executable file
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@ -0,0 +1,428 @@
#include "radio_hal.h"
#include "CMT2310A_reg.h"
#include "CMT2310A_def.h"
/****************************************************************************
;---------------------------------------
; CMT2310A Configuration File
; Generated by CMOSTEK RFPDK 1.54
; 2023.12.07 13:35
;---------------------------------------
; Mode = Advanced
; Part Number = CMT2310A
; Frequency = 410.000 MHz
; DC-DC = Off
; Demodulation = GFSK
; Xtal Cap Load = 2
; Data Rate = 2.400 kbps
; Deviation = 4.800 kHz
; Tx Xtal Tol. = 10 ppm
; Rx Xtal Tol. = 10 ppm
; TRx Matching Network Type = 20 dBm
; Tx Power = +20 dBm
; Gaussian BT = 0.5
; PA Ramp = On-Autosel Rampstep
; PA Ramp Step = NA
; RF Performance = NA
; Output Drive Capability = 0.5mA
; Rx Duty-Cycle = Off
; Tx Duty-Cycle = Off
; Sleep Timer = Off
; Sleep Time = NA
; Rx Timer = Off
; Rx Time T1 = NA
; Rx Time T2 = NA
; Rx Exit State = STBY
; Tx Exit State = STBY
; TX Duty Cycle Persist = Off
; Packet Done Exit = Off
; TX Duty-Cycle Times = 0
; SLP Mode = Mode 0
; RSSI Valid Source = RSSI Compare
; PJD Window = NA
; RSSI Compare TH = -127 dBm
; CDR Type = Counting
; AFC = autosel
; FSK2 Data Map = 0:F-low 1:F-high
; FSK4 Data Map = NA
; FSK4 RX Data Map = NA
; CDR Type = Counting
; CDR Range Sel FSK = NA
; Channel BW = autosel
; Baseband BW FSK = autosel
; Data Mode = Packet
; Packet Mode = Normal
; PiggyBacking = Disable
; Manchester = Disable
; Manchester Type = NA
; Whitening = Disable
; Whiten Type = NA
; Whiten Seed Type = NA
; Whiten Seed = NA
; FEC = Disable
; FEC Type = NA
; FEC Padding Code = NA
; crc err clear fifo = Not Clear
; Tx Packet Gap = 32 symbol(s)
; Tx Packet Number = 1 packet(s)
; Tx Prefix Type = 0
; Packet Type = Fixed Length
; Address-Length Position = NA
; Length Size = 1-byte
; Payload Bit Order = Start from msb
; Address Field = Disable
; Preamble Rx Size = 2
; Preamble Tx Size = 8
; Preamble Value = 170
; Preamble Unit = 8-bit
; Sync Size = 3-byte
; Sync Format = S2LP
; Sync Value = 3003605
; Sync Manchester = Disable
; Sync Value Selection = Sync Value
; Sync FEC Value = 3003605
; Sync Tolerance = None
; Address Detect Mode = None
; Address Split Mode = NA
; Address Size = NA
; Address Err Mask = NA
; Address Free = NA
; Dest Addr Value = NA
; Src Addr Value = NA
; Dest Addr Bit Mask = NA
; Src Addr Bit Mask = NA
; Sequence Num = None
; Sequence Num Match = off
; Sequence Num Mode = NA
; Sequence Num Value = NA
; FCS2 = None
; FCS2 Value = NA
; Payload Length = 32
; CRC Options = None
; CRC Swap = NA
; CRC Seed = NA
; CRC Bit Invert = NA
; CRC Range = NA
; CRC Polynomial = NA
; CRC Bit Order = NA
; CRC Refin = NA
; CRC_Refout = NA
; Frequency Hopping Mode = Mode 2
; Freq Hopping Space = 10 kHz
; Hopping Channels = 10
; CSMA Mode = Disable
; CSMA RSSI Detection = NA
; Hopping Persist = Disable
; Hopping Intermediate State = TRFS
; CSMA Sleep Timer Random = NA
; CSMA Rx Time = NA
; CSMA Sleep Time M = NA
; CSMA Sleep Time R = NA
; CSMA Persist = NA
; CSMA Detect Times = NA
; Tx Auto Hopping = Disable
; Rx Auto Hopping = Disable
; Auto Acknowledge = off
; Auto Resend = off
; Maximum Resend Times = 1
; RSSI Detect Mode = always
; LFOSC LFXO Sel = LFOSC(32kHz)
; LF Clock Out = off
; Dout Mute = disable
; Dout Mute Sel = NA
; dout adjust mode = disable
; Dout Adjust Percentage = NA
; LBD Threshold = 2.4 v
; Antenna Diversity = off
; Antenna Switch Mode = NA
; Collision Detect = off
; Collision Step = NA
; RSSI Offset dB = NA
; RSSI Offset Sel = autosel
; i_fir_bb_bw_for_cal_freq = 1
;---------------------------------------
; The following are the Register contents
;---------------------------------------
*****************************************************************************/
#if (PRODUCT_FREQUENCY == CM2310A_410MHZ)
/* [CMT page0] */
const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = {
0x12,
0x08,
0x00,
0xAA,
0x04,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0x45,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x08,
0x00,
0x00,
0x00,
0x00,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x00,
0xE4,
0x20,
0x20,
0x20,
0x01,
0x00,
0xD0,
0xE0,
0xE2,
0x84,
0x30,
0x04,
0xD0,
0xE0,
0x80,
0x00,
0x41,
0x00,
0x01,
0x00,
0x02,
0x00,
0x00,
0x03,
0x04,
};
/* [CMT page1] */
const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = {
0x10,
0x06,
0x00,
0xFF,
0x00,
0xCD,
0x02,
0x28,
0x50,
0x87,
0x31,
0x5B,
0x08,
0x00,
0xFF,
0x00,
0x66,
0x00,
0x00,
0x08,
0xB4,
0xEA,
0x04,
0xE0,
0x20,
0x08,
0x05,
0x8D,
0x06,
0x00,
0xA0,
0x7F,
0x00,
0x18,
0x00,
0x00,
0x1F,
0xE4,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0xCA,
0x66,
0x00,
0x80,
0xD8,
0x63,
0x00,
0x80,
0x0F,
0x64,
0x06,
0x02,
0xEA,
0x04,
0x00,
0x36,
0x01,
0x20,
0xC8,
0x63,
0xA1,
0x15,
0x34,
0x58,
0x40,
0xD2,
0x74,
0xF0,
0x0F,
0x01,
0x17,
0xE6,
0x54,
0x08,
0x39,
0xE6,
0x27,
0x0C,
0x01,
0xB4,
0x06,
0x0F,
0x00,
0x4C,
0x00,
0x00,
0xF6,
0x00,
0x00,
0x00,
0x10,
0x81,
0x00,
0x00,
0x47,
0x12,
0x25,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
//#define CMT2310A_AUTO_HOP_ENABLE
#ifdef CMT2310A_AUTO_HOP_ENABLE
#define freq_space_val 0x0A
#define freq_times_val 0x0A
#define freq_switch_state_val 0x01
#define freq_hop_persist_val 0x00
/* [CMT page2] */
const uint8_t g_cmt2310a_page2[CMT2310A_PAGE2_SIZE] = {
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
#endif
#endif

351
NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_433mhz.c Executable file
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#include "radio_hal.h"
#include "CMT2310A_reg.h"
#include "CMT2310A_def.h"
/****************************************************************************
;---------------------------------------
; CMT2310A Configuration File
; Generated by CMOSTEK RFPDK 1.53_Update4
; 2023.01.14 10:34
;---------------------------------------
; Mode = Advanced
; Part Number = CMT2310A
; Frequency = 433.920 MHz
; DC-DC = Off
; Demodulation = GFSK
; Xtal Cap Load = 2
; Data Rate = 2.400 kbps
; Deviation = 4.800 kHz
; Tx Xtal Tol. = 10 ppm
; Rx Xtal Tol. = 10 ppm
; TRx Matching Network Type = 20 dBm
; Tx Power = +20 dBm
; Gaussian BT = 0.5
; PA Ramp = On-Autosel Rampstep
; PA Ramp Step = NA
; RF Performance = NA
; Output Drive Capability = 0.5mA
; Rx Duty-Cycle = Off
; Tx Duty-Cycle = Off
; Sleep Timer = Off
; Sleep Time = NA
; Rx Timer = Off
; Rx Time T1 = NA
; Rx Time T2 = NA
; Rx Exit State = STBY
; Tx Exit State = STBY
; TX Duty Cycle Persist = Off
; Packet Done Exit = Off
; TX Duty-Cycle Times = 0
; SLP Mode = Mode 0
; RSSI Valid Source = RSSI Compare
; PJD Window = NA
; RSSI Compare TH = -127 dBm
; CDR Type = Counting
; AFC = autosel
; FSK2 Data Map = 0:F-low 1:F-high
; FSK4 Data Map = NA
; FSK4 RX Data Map = NA
; CDR Type = Counting
; CDR Range Sel FSK = NA
; Channel BW = autosel
; Baseband BW FSK = autosel
; Data Mode = Packet
; Packet Mode = Normal
; PiggyBacking = Disable
; Manchester = Disable
; Manchester Type = NA
; Whitening = Disable
; Whiten Type = NA
; Whiten Seed Type = NA
; Whiten Seed = NA
; FEC = Disable
; FEC Type = NA
; FEC Padding Code = NA
; crc err clear fifo = Not Clear
; Tx Packet Gap = 32 symbol(s)
; Tx Packet Number = 1 packet(s)
; Tx Prefix Type = 0
; Packet Type = Fixed Length
; Address-Length Position = NA
; Length Size = 1-byte
; Payload Bit Order = Start from msb
; Address Field = Disable
; Preamble Rx Size = 2
; Preamble Tx Size = 8
; Preamble Value = 170
; Preamble Unit = 8-bit
; Sync Size = 3-byte
; Sync Format = S2LP
; Sync Value = 3003605
; Sync Manchester = Disable
; Sync Value Selection = Sync Value
; Sync FEC Value = 3003605
; Sync Tolerance = None
; Address Detect Mode = None
; Address Split Mode = NA
; Address Size = NA
; Address Err Mask = NA
; Address Free = NA
; Dest Addr Value = NA
; Src Addr Value = NA
; Dest Addr Bit Mask = NA
; Src Addr Bit Mask = NA
; Sequence Num = None
; Sequence Num Match = off
; Sequence Num Mode = NA
; Sequence Num Value = NA
; FCS2 = None
; FCS2 Value = NA
; Payload Length = 32
; CRC Options = None
; CRC Swap = NA
; CRC Seed = NA
; CRC Bit Invert = NA
; CRC Range = NA
; CRC Polynomial = NA
; CRC Bit Order = NA
; CRC Refin = NA
; CRC_Refout = NA
; Frequency Hopping Mode = Mode 2
; Freq Hopping Space = 10 kHz
; Hopping Channels = 10
; CSMA Mode = Disable
; CSMA RSSI Detection = NA
; Hopping Persist = Disable
; Hopping Intermediate State = TRFS
; CSMA Sleep Timer Random = NA
; CSMA Rx Time = NA
; CSMA Sleep Time M = NA
; CSMA Sleep Time R = NA
; CSMA Persist = NA
; CSMA Detect Times = NA
; Tx Auto Hopping = Disable
; Rx Auto Hopping = Disable
; Auto Acknowledge = off
; Auto Resend = off
; Maximum Resend Times = 1
; RSSI Detect Mode = always
; LFOSC LFXO Sel = LFOSC(32kHz)
; LF Clock Out = off
; Dout Mute = disable
; Dout Mute Sel = NA
; dout adjust mode = disable
; Dout Adjust Percentage = NA
; LBD Threshold = 2.4 v
; Antenna Diversity = off
; Antenna Switch Mode = NA
; Collision Detect = off
; Collision Step = NA
; RSSI Offset dB = NA
; RSSI Offset Sel = autosel
;---------------------------------------
; The following are the Register contents
;---------------------------------------
*****************************************************************************/
#if (PRODUCT_FREQUENCY == CM2310A_433MHZ)
/* [CMT page0] */
const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = {
0x12,
0x08,
0x00,
0xAA,
0x04,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0xD5,
0xD4,
0x2D,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x2D,
0x00,
0x00,
0x00,
0x00,
0x00,
0x45,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x08,
0x00,
0x00,
0x00,
0x00,
0x1F,
0x00,
0x00,
0x00,
0x00,
0x00,
0xE4,
0x20,
0x20,
0x20,
0x01,
0x00,
0xD0,
0xE0,
0xE2,
0x84,
0x30,
0x04,
0xD0,
0xE0,
0x80,
0x00,
0x41,
0x00,
0x01,
0x00,
0x02,
0x00,
0x00,
0x03,
0x04,
};
/* [CMT page1] */
const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = {
0x10,
0x06,
0x00,
0xFF,
0x00,
0xCD,
0x02,
0x28,
0x50,
0x87,
0x31,
0x5B,
0x08,
0x00,
0xFF,
0x00,
0x6C,
0x14,
0xAE,
0x07,
0xB4,
0xEA,
0x04,
0xE0,
0x20,
0x08,
0x05,
0x8D,
0x06,
0x00,
0xA0,
0x7F,
0x00,
0x18,
0x00,
0x00,
0x1F,
0xE4,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0xCA,
0x6C,
0x14,
0x2E,
0xD8,
0x6B,
0x00,
0x80,
0x0F,
0x64,
0x06,
0x02,
0xEA,
0x04,
0x00,
0x36,
0x01,
0x20,
0xC8,
0x63,
0xA1,
0x15,
0x34,
0x58,
0x40,
0xD2,
0x74,
0xF0,
0x0F,
0x01,
0x17,
0xE6,
0x54,
0x08,
0x39,
0xE2,
0x27,
0x0C,
0x01,
0xB4,
0x06,
0x0F,
0x0E,
0x4C,
0x00,
0x00,
0xF6,
0x00,
0x00,
0x00,
0x10,
0x81,
0x00,
0x00,
0x47,
0x12,
0x25,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
#endif

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