RTOS/SDK_GD32W51x
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[Mod] 按优化方案修改，完整初始化正常

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This commit is contained in:
gaoyang3513
2024-08-01 10:17:12 +08:00
parent 2ea3d7e844
commit eacd045dfd
7 changed files with 528 additions and 459 deletions
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4
NSPE/WIFI_IOT/app/main.c
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@ -197,11 +197,11 @@ int main(void)
}
#endif // CONFIG_TASK_LED
if (NULL == sys_task_create(NULL, (const uint8_t *)"sub1g_task", NULL, START_TASK_STK_SIZE, 0, START_TASK_PRIO, sub1g_task, NULL)) {
if (NULL == sys_task_create(NULL, (const uint8_t *)"start_task", NULL, START_TASK_STK_SIZE, 0, START_TASK_PRIO, start_task, NULL)) {
DEBUGPRINT("ERROR: create start task failed\r\n");
}
if (NULL == sys_task_create(NULL, (const uint8_t *)"start_task", NULL, START_TASK_STK_SIZE, 0, START_TASK_PRIO, start_task, NULL)) {
if (NULL == sys_task_create(NULL, (const uint8_t *)"sub1g_task", NULL, START_TASK_STK_SIZE, 0, START_TASK_PRIO, sub1g_task, NULL)) {
DEBUGPRINT("ERROR: create start task failed\r\n");
}

12
NSPE/WIFI_IOT/bsp/drivers/.editorconfig Normal file
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@ -0,0 +1,12 @@
# EditorConfig is awesome: https://EditorConfig.org
# top-most EditorConfig file
root = true
[*]
indent_style = tab
indent_size = 8
end_of_line = lf
charset = utf-8
trim_trailing_whitespace = true
insert_final_newline = false

466
NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h
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File diff suppressed because it is too large Load Diff

25
NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c
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@ -25,11 +25,32 @@ uint8_t rf_rxbuffer[200];
uint8_t rf_rxsize;
uint8_t radio_rece_data_flag;
extern uint32_t g_chip_id;
void Ebyte_E48x_Init( void )
{
vRadioCheckLink();
vRadioInit();
/* Step1 */
vRadioPowerUp(); // Release RST(GPIO5)
vRadioSetAntSwitch(FALSE, FALSE); // Disable GPIO0 & GPIO1 as antenna switch control
vRadioSpiModeSel(FALSE); // SPI 4-Wire mode
/* Step2 */
g_chip_id = lRadioChipVersion();
if(0x00231000 != (g_chip_id & 0x00FFFF00)) {
DEBUGPRINT("[%s|%u] Error, dismatch Chip-ID[%#x](!=0x231000).\r\n", __FUNCTION__, __LINE__, g_chip_id);
return;
}
DEBUGPRINT("[%s|%u] Info, Link Device:E48-XXXM20S.\r\n", __FUNCTION__, __LINE__);
/* Step3 */
if (bRadioGetState() == CMT2310A_STATE_IS_READY) {
DEBUGPRINT("[%s|%u] Infor, CMT2310 already in State[READY], so skip initialization.\r\n", __FUNCTION__, __LINE__);
return;
}
DEBUGPRINT("[%s|%u] Info, goto initialize E48-XXXM20S.\r\n", __FUNCTION__, __LINE__);
/* Step4 */
vRadioInit();
}
void Ebyte_E48x_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout )

372
NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c
View File

@ -71,191 +71,201 @@ const uint8_t cmt2310a_power[55][7] = {
********************************/
void vRadioInit( void )
{
byte fw_rev;
vRadioSoftReset();
vRadioConfigPageReg( 0, g_cmt2310a_page0, CMT2310A_PAGE0_SIZE ); //config page 0
vRadioConfigPageReg( 1, g_cmt2310a_page1, CMT2310A_PAGE1_SIZE ); //config page 1
vRadioSetNirq( CMT2310A_nIRQ_TCXO ); //for TCXO need cofig as nIRQ pin at first
vRadioTcxoDrvSel( 0 ); //drive power
byte fw_rev;
fw_rev = (byte)g_chip_id; //dealwith Xtal
switch(fw_rev)
{
case 0xC0:
vRadioXoWaitCfg(RADIO_CGU_DIV4);
break;
default:
break;
}
/* Step4 */
vRadioHardReset();
vRadioPowerUpBoot();
delay1ms( 10 );
bRadioGoStandby();
delay1ms( 2 );
bRadioApiCommand( 0x02 ); //
delay1ms( 10 );
bRadioApiCommand( 0x01 ); //IR Calibration, need some times
vRadioCapLoad( 2 ); //Xo Cap
//GPIOn default setting
vRadioSetGpio0( CMT2310A_GPIO0_INT3 );
vRadioSetGpio1( CMT2310A_GPIO1_INT2 );
vRadioSetGpio2( CMT2310A_GPIO2_DCLK );
vRadioSetGpio3( CMT2310A_GPIO3_DOUT );
vRadioSetGpio4( CMT2310A_GPIO4_INT1 );
vRadioSetGpio5( CMT2310A_GPIO5_nRST );
//INT1 = RX_FIFO_WBYTE, INT2 = PKT_DONE
vRadioSetInt1Sel( INT_SRC_RX_FIFO_WBYTE );
vRadioSetInt2Sel( INT_SRC_PKT_DONE );
vRadioSetInt1Polar( FALSE );
vRadioSetInt2Polar( FALSE );
vRadioSetInt3Polar( FALSE );
//interrupt source enable config
g_radio.int_src_en._BITS.PKT_DONE_EN = 1;
g_radio.int_src_en._BITS.CRC_PASS_EN = 1;
g_radio.int_src_en._BITS.ADDR_PASS_EN = 0;
g_radio.int_src_en._BITS.SYNC_PASS_EN = 1;
g_radio.int_src_en._BITS.PREAM_PASS_EN = 1;
g_radio.int_src_en._BITS.TX_DONE_EN = 1;
g_radio.int_src_en._BITS.RX_TOUT_EN = 1;
g_radio.int_src_en._BITS.LD_STOP_EN = 0;
g_radio.int_src_en._BITS.LBD_STOP_EN = 0;
g_radio.int_src_en._BITS.LBD_STAT_EN = 0;
g_radio.int_src_en._BITS.PKT_ERR_EN = 0;
g_radio.int_src_en._BITS.RSSI_COLL_EN = 0;
g_radio.int_src_en._BITS.OP_CMD_FAILED_EN = 0;
g_radio.int_src_en._BITS.RSSI_PJD_EN = 0;
g_radio.int_src_en._BITS.SEQ_MATCH_EN = 0;
g_radio.int_src_en._BITS.NACK_RECV_EN = 0;
g_radio.int_src_en._BITS.TX_RESEND_DONE_EN = 0;
g_radio.int_src_en._BITS.ACK_RECV_FAILED_EN = 0;
g_radio.int_src_en._BITS.TX_DC_DONE_EN = 0;
g_radio.int_src_en._BITS.CSMA_DONE_EN = 0;
g_radio.int_src_en._BITS.CCA_STAT_EN = 0;
g_radio.int_src_en._BITS.API_DONE_EN = 0;
g_radio.int_src_en._BITS.TX_FIFO_TH_EN = 1;
g_radio.int_src_en._BITS.TX_FIFO_NMTY_EN = 1;
g_radio.int_src_en._BITS.TX_FIFO_FULL_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_OVF_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_TH_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_NMTY_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_FULL_EN = 1;
vRadioInterruptSoucreCfg( &g_radio.int_src_en );
//packet preamble config
g_radio.preamble_cfg.PREAM_LENG_UNIT = 0; //8-bits mode
g_radio.preamble_cfg.PREAM_VALUE = 0xAA; //
g_radio.preamble_cfg.RX_PREAM_SIZE = 2; //
g_radio.preamble_cfg.TX_PREAM_SIZE = 16;
vRadioCfgPreamble( &g_radio.preamble_cfg );
//packet syncword config
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MAN_EN = 0; //disable syncword manchester coding
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_SIZE = 2; //enable 3 bytes for syncword
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_TOL = 0;
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MODE_SEL = 0; //normal packet
g_radio.sync_cfg.SYNC_VALUE[0] = 0xAA;
g_radio.sync_cfg.SYNC_VALUE[1] = 0x2D;
g_radio.sync_cfg.SYNC_VALUE[2] = 0xD4;
g_radio.sync_cfg.SYNC_VALUE_SEL = 0; //select SYN_VAL
vRadioCfgSyncWord( &g_radio.sync_cfg );
//packet node address config
g_radio.addr_cfg.ADDR_CFG_u._BITS.ADDR_DET_MODE = 0; //disable Node Address
vRadioCfgNodeAddr( &g_radio.addr_cfg );
//packet crc config
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_EN = 1; //enable crc
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_ORDER = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFIN = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_RANGE = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_INV = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BYTE_SWAP = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFOUT = 0; //whole payload
g_radio.crc_cfg.CRC_CFG_u._BITS.CRCERR_CLR_FIFO_EN = 0; //note: need ative FIFO_AUTO_CLR_RX_EN = 1 or call vRadioFifoAutoClearGoRx(1)
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_SIZE = 1; //crc-16 mode
g_radio.crc_cfg.CRC_POLY_u.u32_POLY = 0x10210000;
g_radio.crc_cfg.CRC_SEED_u.u32_SEED = 0x00000000;
vRadioCfgCrc( &g_radio.crc_cfg );
//packet coding format
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_EN = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_TYPE = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_EN = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_TYPE = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_SEED_TYP = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_EN = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_RSC_NRNSC_SEL = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_TICC = 0;
g_radio.coding_format_cfg.WHITEN_SEED = 0x01FF;
g_radio.coding_format_cfg.FEC_PAD_CODE = 0;
vRadioCfgCodeFormat( &g_radio.coding_format_cfg );
//packet frame format
g_radio.frame_cfg.DATA_MODE = 2; //0=direct mode, 2=packet mode
g_radio.frame_cfg.FRAME_CFG1_u._BITS.PKT_TYPE = 1; //0=fixd-length packet mode 1=<3D>ɱ䳤
g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAYLOAD_BIT_ORDER = 0; //msb first
g_radio.frame_cfg.FRAME_CFG1_u._BITS.ADDR_LEN_CONF = 0;
g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAGGYBACKING_EN = 0;
g_radio.frame_cfg.FRAME_CFG1_u._BITS.LENGTH_SIZE = 0;
g_radio.frame_cfg.FRAME_CFG1_u._BITS.INTERLEAVE_EN = 0; //note: when FEC enable, INTERLEAVE_EN should be set 1
g_radio.frame_cfg.FRAME_CFG2_u._BITS.TX_PREFIX_TYPE = TX_PREFIX_SEL_PREAMBLE; //transmit preamble
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_EN = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_AUTO_INC = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_SIZE = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_MACH_EN = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.FCS2_EN = 0;
g_radio.frame_cfg.TX_PKT_NUM = 0;
g_radio.frame_cfg.TX_PKT_GAP = 0;
g_radio.frame_cfg.FCS2_TX_IN = 0;
g_radio.frame_cfg.PAYLOAD_LENGTH = UHF_LEN;
vRadioCfgFrameFormat( &g_radio.frame_cfg );
//Run Mode Config
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_ACK_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_PERSIST_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_AUTO_HOP_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_EXIT_STATE = EXIT_TO_READY;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_DC_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_AUTO_HOP_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_EXIT_STATE = EXIT_TO_READY;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.CSMA_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.PKT_DONE_EXIT_EN = 0; //depend on RX_EXIT_STATE
g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.RX_HOP_SLP_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.SLP_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_OUT_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_SEL = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.TIMER_RAND_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_WIN_SEL = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_INT_SEL = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_PERSIST_EN = 0;
/* Step5 */
vRadioConfigPageReg( 0, g_cmt2310a_page0, CMT2310A_PAGE0_SIZE ); //config page 0
vRadioConfigPageReg( 1, g_cmt2310a_page1, CMT2310A_PAGE1_SIZE ); //config page 1
vRadioSetNirq( CMT2310A_nIRQ_TCXO ); //for TCXO need cofig as nIRQ pin at first
vRadioTcxoDrvSel( 0 ); //drive power
g_radio.word_mode_cfg.WORK_MODE_CFG6_u._BITS.FREQ_HOP_MANU_EN = 1;//ʹ<><CAB9><EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD>Ƶ<EFBFBD>޷<EFBFBD>ʹ<EFBFBD><CAB9>
fw_rev = (byte)g_chip_id; //dealwith Xtal
switch(fw_rev)
{
case 0xC0:
vRadioXoWaitCfg(RADIO_CGU_DIV4);
break;
default:
break;
}
g_radio.word_mode_cfg.FREQ_CHANL_NANU = 92;//<2F>ֶ<EFBFBD><D6B6><EFBFBD>Ƶ<EFBFBD>ŵ<EFBFBD>0~255
g_radio.word_mode_cfg.FREQ_DONE_TIMES = 0;
g_radio.word_mode_cfg.FREQ_SPACE = 250;//<2F><>Ƶ<EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>0~255 KHz
g_radio.word_mode_cfg.FREQ_TIMES = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_M = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_R = 0;
g_radio.word_mode_cfg.RX_TIMER_T1_M = 0; //M*2^(R+1)*5us=M*2^R*10us,
g_radio.word_mode_cfg.RX_TIMER_T1_R = 0; //R=7, unit=0.64ms
g_radio.word_mode_cfg.RX_TIMER_T2_M = 0;
g_radio.word_mode_cfg.RX_TIMER_T2_R = 0;
g_radio.word_mode_cfg.RX_TIMER_CSMA_M = 0;
g_radio.word_mode_cfg.RX_TIMER_CSMA_R = 0;
g_radio.word_mode_cfg.TX_DC_TIMES = 0;
g_radio.word_mode_cfg.TX_RS_TIMES = 0;
g_radio.word_mode_cfg.CSMA_TIMES = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_M = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_R = 0;
vRadioCfgWorkMode( &g_radio.word_mode_cfg );
//FIFO Init
vRadioFifoMerge( FALSE );
vRadioSetFifoTH( 30 );
vRadioClearRxFifo(); //reset & clear fifo
vRadioClearTxFifo();
vRadioFifoAutoClearGoRx( TRUE ); //when crc error, need to auto clear fifo, should enable
vRadioRssiUpdateSel( CMT2310A_RSSI_UPDATE_ALWAYS );
vRadioSetAntSwitch( FALSE, FALSE ); //
vRadioDcdcCfg( TRUE ); //dc-dc off
/* Step6 */
vRadioPowerUpBoot();
delay1ms( 10 );
/* Step7 */
bRadioGoStandby();
delay1ms( 2 );
bRadioApiCommand( 0x02 ); //
delay1ms( 10 );
/* Step8 */
bRadioApiCommand( 0x01 ); //IR Calibration, need some times
vRadioCapLoad( 2 ); //Xo Cap
/* Step9, GPIOn and interrupt setting */
vRadioSetGpio0( CMT2310A_GPIO0_INT3 );
vRadioSetGpio1( CMT2310A_GPIO1_INT2 );
vRadioSetGpio2( CMT2310A_GPIO2_DCLK );
vRadioSetGpio3( CMT2310A_GPIO3_DOUT );
vRadioSetGpio4( CMT2310A_GPIO4_INT1 );
vRadioSetGpio5( CMT2310A_GPIO5_nRST );
//INT1 = RX_FIFO_WBYTE, INT2 = PKT_DONE
vRadioSetInt1Sel( INT_SRC_RX_FIFO_WBYTE );
vRadioSetInt2Sel( INT_SRC_PKT_DONE );
vRadioSetInt1Polar( FALSE );
vRadioSetInt2Polar( FALSE );
vRadioSetInt3Polar( FALSE );
//interrupt source enable config
g_radio.int_src_en._BITS.PKT_DONE_EN = 1;
g_radio.int_src_en._BITS.CRC_PASS_EN = 1;
g_radio.int_src_en._BITS.ADDR_PASS_EN = 0;
g_radio.int_src_en._BITS.SYNC_PASS_EN = 1;
g_radio.int_src_en._BITS.PREAM_PASS_EN = 1;
g_radio.int_src_en._BITS.TX_DONE_EN = 1;
g_radio.int_src_en._BITS.RX_TOUT_EN = 1;
g_radio.int_src_en._BITS.LD_STOP_EN = 0;
g_radio.int_src_en._BITS.LBD_STOP_EN = 0;
g_radio.int_src_en._BITS.LBD_STAT_EN = 0;
g_radio.int_src_en._BITS.PKT_ERR_EN = 0;
g_radio.int_src_en._BITS.RSSI_COLL_EN = 0;
g_radio.int_src_en._BITS.OP_CMD_FAILED_EN = 0;
g_radio.int_src_en._BITS.RSSI_PJD_EN = 0;
g_radio.int_src_en._BITS.SEQ_MATCH_EN = 0;
g_radio.int_src_en._BITS.NACK_RECV_EN = 0;
g_radio.int_src_en._BITS.TX_RESEND_DONE_EN = 0;
g_radio.int_src_en._BITS.ACK_RECV_FAILED_EN = 0;
g_radio.int_src_en._BITS.TX_DC_DONE_EN = 0;
g_radio.int_src_en._BITS.CSMA_DONE_EN = 0;
g_radio.int_src_en._BITS.CCA_STAT_EN = 0;
g_radio.int_src_en._BITS.API_DONE_EN = 0;
g_radio.int_src_en._BITS.TX_FIFO_TH_EN = 1;
g_radio.int_src_en._BITS.TX_FIFO_NMTY_EN = 1;
g_radio.int_src_en._BITS.TX_FIFO_FULL_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_OVF_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_TH_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_NMTY_EN = 1;
g_radio.int_src_en._BITS.RX_FIFO_FULL_EN = 1;
vRadioInterruptSoucreCfg( &g_radio.int_src_en );
//packet preamble config
g_radio.preamble_cfg.PREAM_LENG_UNIT = 0; //8-bits mode
g_radio.preamble_cfg.PREAM_VALUE = 0xAA; //
g_radio.preamble_cfg.RX_PREAM_SIZE = 2; //
g_radio.preamble_cfg.TX_PREAM_SIZE = 16;
vRadioCfgPreamble( &g_radio.preamble_cfg );
//packet syncword config
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MAN_EN = 0; //disable syncword manchester coding
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_SIZE = 2; //enable 3 bytes for syncword
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_TOL = 0;
g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MODE_SEL = 0; //normal packet
g_radio.sync_cfg.SYNC_VALUE[0] = 0xAA;
g_radio.sync_cfg.SYNC_VALUE[1] = 0x2D;
g_radio.sync_cfg.SYNC_VALUE[2] = 0xD4;
g_radio.sync_cfg.SYNC_VALUE_SEL = 0; //select SYN_VAL
vRadioCfgSyncWord( &g_radio.sync_cfg );
//packet node address config
g_radio.addr_cfg.ADDR_CFG_u._BITS.ADDR_DET_MODE = 0; //disable Node Address
vRadioCfgNodeAddr( &g_radio.addr_cfg );
//packet crc config
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_EN = 1; //enable crc
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_ORDER = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFIN = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_RANGE = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_INV = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BYTE_SWAP = 0;
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFOUT = 0; //whole payload
g_radio.crc_cfg.CRC_CFG_u._BITS.CRCERR_CLR_FIFO_EN = 0; //note: need ative FIFO_AUTO_CLR_RX_EN = 1 or call vRadioFifoAutoClearGoRx(1)
g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_SIZE = 1; //crc-16 mode
g_radio.crc_cfg.CRC_POLY_u.u32_POLY = 0x10210000;
g_radio.crc_cfg.CRC_SEED_u.u32_SEED = 0x00000000;
vRadioCfgCrc( &g_radio.crc_cfg );
//packet coding format
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_EN = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_TYPE = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_EN = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_TYPE = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_SEED_TYP = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_EN = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_RSC_NRNSC_SEL = 0;
g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_TICC = 0;
g_radio.coding_format_cfg.WHITEN_SEED = 0x01FF;
g_radio.coding_format_cfg.FEC_PAD_CODE = 0;
vRadioCfgCodeFormat( &g_radio.coding_format_cfg );
//packet frame format
g_radio.frame_cfg.DATA_MODE = 2; //0=direct mode, 2=packet mode
g_radio.frame_cfg.FRAME_CFG1_u._BITS.PKT_TYPE = 1; //0=fixd-length packet mode 1=<3D>ɱ䳤
g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAYLOAD_BIT_ORDER = 0; //msb first
g_radio.frame_cfg.FRAME_CFG1_u._BITS.ADDR_LEN_CONF = 0;
g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAGGYBACKING_EN = 0;
g_radio.frame_cfg.FRAME_CFG1_u._BITS.LENGTH_SIZE = 0;
g_radio.frame_cfg.FRAME_CFG1_u._BITS.INTERLEAVE_EN = 0; //note: when FEC enable, INTERLEAVE_EN should be set 1
g_radio.frame_cfg.FRAME_CFG2_u._BITS.TX_PREFIX_TYPE = TX_PREFIX_SEL_PREAMBLE; //transmit preamble
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_EN = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_AUTO_INC = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_SIZE = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_MACH_EN = 0;
g_radio.frame_cfg.FRAME_CFG2_u._BITS.FCS2_EN = 0;
g_radio.frame_cfg.TX_PKT_NUM = 0;
g_radio.frame_cfg.TX_PKT_GAP = 0;
g_radio.frame_cfg.FCS2_TX_IN = 0;
g_radio.frame_cfg.PAYLOAD_LENGTH = UHF_LEN;
vRadioCfgFrameFormat( &g_radio.frame_cfg );
//Run Mode Config
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_ACK_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_PERSIST_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_AUTO_HOP_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_EXIT_STATE = EXIT_TO_READY;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_DC_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_AUTO_HOP_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_EXIT_STATE = EXIT_TO_READY;
g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.CSMA_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.PKT_DONE_EXIT_EN = 0; //depend on RX_EXIT_STATE
g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.RX_HOP_SLP_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.SLP_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_OUT_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_SEL = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.TIMER_RAND_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_MODE = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_WIN_SEL = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_INT_SEL = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_PERSIST_EN = 0;
g_radio.word_mode_cfg.WORK_MODE_CFG6_u._BITS.FREQ_HOP_MANU_EN = 1;//ʹ<><CAB9><EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD>Ƶ<EFBFBD>޷<EFBFBD>ʹ<EFBFBD><CAB9>
g_radio.word_mode_cfg.FREQ_CHANL_NANU = 92;//<2F>ֶ<EFBFBD><D6B6><EFBFBD>Ƶ<EFBFBD>ŵ<EFBFBD>0~255
g_radio.word_mode_cfg.FREQ_DONE_TIMES = 0;
g_radio.word_mode_cfg.FREQ_SPACE = 250;//<2F><>Ƶ<EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>0~255 KHz
g_radio.word_mode_cfg.FREQ_TIMES = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_M = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_R = 0;
g_radio.word_mode_cfg.RX_TIMER_T1_M = 0; //M*2^(R+1)*5us=M*2^R*10us,
g_radio.word_mode_cfg.RX_TIMER_T1_R = 0; //R=7, unit=0.64ms
g_radio.word_mode_cfg.RX_TIMER_T2_M = 0;
g_radio.word_mode_cfg.RX_TIMER_T2_R = 0;
g_radio.word_mode_cfg.RX_TIMER_CSMA_M = 0;
g_radio.word_mode_cfg.RX_TIMER_CSMA_R = 0;
g_radio.word_mode_cfg.TX_DC_TIMES = 0;
g_radio.word_mode_cfg.TX_RS_TIMES = 0;
g_radio.word_mode_cfg.CSMA_TIMES = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_M = 0;
g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_R = 0;
vRadioCfgWorkMode( &g_radio.word_mode_cfg );
//FIFO Init
vRadioFifoMerge( FALSE );
vRadioSetFifoTH( 30 );
vRadioClearRxFifo(); //reset & clear fifo
vRadioClearTxFifo();
vRadioFifoAutoClearGoRx( TRUE ); //when crc error, need to auto clear fifo, should enable
vRadioRssiUpdateSel( CMT2310A_RSSI_UPDATE_ALWAYS );
vRadioSetAntSwitch( FALSE, FALSE ); //
vRadioDcdcCfg( TRUE ); //dc-dc off
}
void vRadioClearInterrupt( void )

44
NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c
View File

@ -1,4 +1,5 @@
#include "radio_hal.h"
#include "board.h"
void delay1ms(uint16_t cnt)
{
@ -440,6 +441,18 @@ void vRadioPowerUpBoot( void )
bSpiWriteByte( CMT2310A_CTL_REG_00, CMT2310A_REBOOT );
}
/******************************
**Name: vRadioPowerUpBoot
**Func: Radio power up boot start
**Input: None
*Output: None
********************************/
void vRadioPowerUp( void )
{
gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, RESET);
delay1ms(10);
}
/******************************
**Name: vRadioSoftReset
**Func: Radio soft reset
@ -455,6 +468,20 @@ void vRadioSoftReset( void )
delay10us( 100 );
}
/******************************
**Name: vRadioSoftReset
**Func: Radio soft reset
**Input: None
*Output: None
********************************/
void vRadioHardReset( void )
{
gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, SET);
delay10us(10);
gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, RESET);
delay1ms(10);
}
/******************************
**Name: vRadioSetPaOutputMode
**Func: Radio config PA output mode
@ -512,16 +539,13 @@ void vRadioSetTxDataInverse( boolean_t cfg_en )
********************************/
void vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar )
{
uint8_t cfg_tmp = 0;
if( cfg_en )
{
cfg_tmp |= CMT2310A_TRX_SWT_EN;
}
if( cfg_polar )
{
cfg_tmp |= CMT2310A_TRX_SWT_INV;
}
bRadioSetReg( CMT2310A_CTL_REG_22, cfg_tmp, ( CMT2310A_TRX_SWT_EN | CMT2310A_TRX_SWT_INV ) );
uint8_t cfg_tmp = 0;
if( cfg_en )
cfg_tmp |= CMT2310A_TRX_SWT_EN;
if( cfg_polar )
cfg_tmp |= CMT2310A_TRX_SWT_INV;
bRadioSetReg( CMT2310A_CTL_REG_22, cfg_tmp, ( CMT2310A_TRX_SWT_EN | CMT2310A_TRX_SWT_INV ) );
}
/******************************

64
NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h
View File

@ -43,44 +43,46 @@ extern uint8_t bRadioReadReg( uint8_t addr );
extern uint8_t bRadioWriteReg( uint8_t addr, uint8_t reg_dat );
extern uint8_t bRadioSetReg( uint8_t addr, uint8_t set_bits, uint8_t mask_bits );
extern void vRadioLoadRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length );
extern void vRadioStoreRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length );
extern void vRadioLoadRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length );
extern void vRadioStoreRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length );
extern void vRadioBurstReadRegs( uint8_t* ptr_buf, uint8_t length );
extern void vRadioBurstWriteRegs( uint8_t* ptr_buf, uint8_t length );
extern void vRadioBurstReadRegs( uint8_t* ptr_buf, uint8_t length );
extern void vRadioBurstWriteRegs( uint8_t* ptr_buf, uint8_t length );
extern void vRadioReadFifo( uint8_t* ptr_fifo, uint8_t length );
extern void vRadioWriteFifo( uint8_t* ptr_fifo, uint8_t length );
extern void vRadioReadTxFifo( uint8_t* ptr_fifo, uint8_t length );
extern void vRadioReadFifo( uint8_t* ptr_fifo, uint8_t length );
extern void vRadioWriteFifo( uint8_t* ptr_fifo, uint8_t length );
extern void vRadioReadTxFifo( uint8_t* ptr_fifo, uint8_t length );
extern void vRadioSpiModeSel( boolean_t spi_mod );
extern void vRadioSetTxDin( boolean_t cfg_din, uint8_t pin_sel );
extern void vRadioSetDigClkOut( boolean_t cfg_out );
extern void vRadioSetLfxoPad( boolean_t cfg_lfxo );
extern void vRadioSetGpio0( uint8_t gpio0_sel );
extern void vRadioSetGpio1( uint8_t gpio1_sel );
extern void vRadioSetGpio2( uint8_t gpio2_sel );
extern void vRadioSetGpio3( uint8_t gpio3_sel );
extern void vRadioSetGpio4( uint8_t gpio4_sel );
extern void vRadioSetGpio5( uint8_t gpio5_sel );
extern void vRadioSetNirq( uint8_t nirq_sel );
extern void vRadioTcxoDrvSel( uint8_t drv_sel );
extern void vRadioSpiModeSel( boolean_t spi_mod );
extern void vRadioSetTxDin( boolean_t cfg_din, uint8_t pin_sel );
extern void vRadioSetDigClkOut( boolean_t cfg_out );
extern void vRadioSetLfxoPad( boolean_t cfg_lfxo );
extern void vRadioSetGpio0( uint8_t gpio0_sel );
extern void vRadioSetGpio1( uint8_t gpio1_sel );
extern void vRadioSetGpio2( uint8_t gpio2_sel );
extern void vRadioSetGpio3( uint8_t gpio3_sel );
extern void vRadioSetGpio4( uint8_t gpio4_sel );
extern void vRadioSetGpio5( uint8_t gpio5_sel );
extern void vRadioSetNirq( uint8_t nirq_sel );
extern void vRadioTcxoDrvSel( uint8_t drv_sel );
extern void vRadioRegPageSel( uint8_t page_sel );
extern void vRadioPowerUpBoot( void );
extern void vRadioSoftReset( void );
extern void vRadioSetPaOutputMode( boolean_t cfg_en );
extern void vRadioSetTxDataInverse( boolean_t cfg_en );
extern void vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar );
extern void vRadioRegPageSel( uint8_t page_sel );
extern void vRadioPowerUp( void );
extern void vRadioPowerUpBoot( void );
extern void vRadioHardReset( void );
extern void vRadioSoftReset( void );
extern void vRadioSetPaOutputMode( boolean_t cfg_en );
extern void vRadioSetTxDataInverse( boolean_t cfg_en );
extern void vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar );
extern void vRadioDcdcCfg( boolean_t on_off );
extern void vRadioCapLoad( uint8_t cap_value );
extern void vRadioLfoscCfg( boolean_t on_off );
extern void vRadioXoWaitCfg( uint8_t div_sel );
extern void vRadioDcdcCfg( boolean_t on_off );
extern void vRadioCapLoad( uint8_t cap_value );
extern void vRadioLfoscCfg( boolean_t on_off );
extern void vRadioXoWaitCfg( uint8_t div_sel );
extern void delay1ms(uint16_t cnt);
extern void delay10us(uint32_t cnt);
extern void delay1ms(uint16_t cnt);
extern void delay10us(uint32_t cnt);
#endif