[Init] First commit

Makefile

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+
+# This is the top-level Makefile for all source packages.
+# It makes all the code in the "src" directory, then installs it
+# in the "install" directory, then makes the images in
+# the images directory (if present).
+
+ROOT_DIR := $(notdir $(CURDIR))
+ifndef QCONFIG
+QCONFIG=qconfig.mk
+endif
+include $(QCONFIG)
+unexport ROOT_DIR
+
+.PHONY: all install clean links make_links dummy images prebuilt binaries
+
+# Expands to a single newline character
+define NEWLINE
+
+
+endef
+
+SUFFIXES := .mk
+
+all: install links $(if $(wildcard images/*),images)
+	@echo done
+
+subdirs:=$(subst /Makefile,,$(wildcard */[Mm]akefile))
+
+clean:
+	$(foreach dir,$(subdirs), $(MAKE) -C$(dir) clean $(NEWLINE))
+	-$(RM_HOST) -r install/*
+
+install: $(if $(wildcard prebuilt/*),prebuilt)
+	$(MAKE) -Csrc hinstall
+	$(MAKE) -Csrc
+
+
+#
+# Have to invoke "make_links" target because the first make expands
+# the $(wildcard ...) too soon - we might not have copied things into
+# the "install" tree yet.
+#
+links:
+	$(MAKE) make_links
+
+make_links:
+	$(foreach file,$(wildcard install/*/boot/build/*),cd images;$(LN_HOST) ../$(file) $(notdir $(file));cd ..; )
+
+images:
+	$(MAKE) -Cimages
+
+prebuilt:
+	cp -rf prebuilt/* install
+

images/Makefile

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+ROOT_DIR := $(notdir $(CURDIR))
+ifndef QCONFIG
+QCONFIG=qconfig.mk
+endif
+include $(QCONFIG)
+
+HOST_MKIFS := mkifs
+HOST_MKI := mki
+HOST_SED := sed
+SUFFIXES := .build .bin .raw .ui
+
+# NOTE: This value must match the '[image=<start_addr>]' value in the build file.
+IMAGE_LOAD_ADDR = 0x80000
+
+PROCESSOR = aarch64
+BUILD_TEMPLATE = $(CURDIR)/../../Templates_build_sdp800
+BOARD=rpi4
+INSTALL=../install
+
+.PHONY: all clean
+
+#all: ifs-$(BOARD).bin ifs-$(BOARD).ui
+all: ifs-$(BOARD).bin
+
+# to boot QNX ifs-rpi4.bin IFS image, add "kernel=ifs-rpi4.bin" to bootable microSD card config.txt file.
+ifs-$(BOARD).bin: $(BOARD).build
+	$(HOST_MKIFS) -v -r$(INSTALL) $(MKIFSFLAGS) $^ $@
+
+# To boot from U-boot "go" command:
+#  - load ifs-rpi4.raw IFS image to 0x80000
+#  - load bcm2711-rpi-4-b.dtb to ${fdt_addr}
+#  - run "go 0x80000 ${fdt_addr}"
+ifs-$(BOARD).raw: $(BOARD).build
+	$(CP_HOST) $(BOARD).build $(BOARD)-go.build
+	$(HOST_SED) -i 's/u reg/u arg/' $(BOARD)-go.build
+	$(HOST_MKIFS) -v -r$(INSTALL) $(MKIFSFLAGS)  $(BOARD)-go.build $@
+	$(RM_HOST) $(BOARD)-go.build
+
+# To boot from U-boot "bootm" command:
+#  - load ifs-rpi4.ui IFS image to 0x80000
+#  - load bcm2711-rpi-4-b.dtb to ${fdt_addr}
+#  - run "bootm 0x80000 - ${fdt_addr}"
+ifs-$(BOARD).ui: ifs-$(BOARD).bin
+	$(HOST_MKI) -a $(IMAGE_LOAD_ADDR) -A arm64 $^ $@
+
+clean:
+	$(RM_HOST) ifs-$(BOARD).* *.sym
+
+-include $(BUILD_TEMPLATE)/template.mk

images/definitions.m4

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+## Boot parameters
+define(`__LD_QNX__',            `ldqnx-64.so.2')
+define(`__BOOT_ADDR__',         `0x80000')
+define(`__ARCH__',              `aarch64le')
+define(`__TYPE__',              `raw')
+define(`__COMPRESS_ATTR__',     `-compress')
+define(`__PROCNTO_MODULES__',   `')
+define(`__STARTUP__',           `startup-bcm2711-rpi4')
+define(`__STARTUP_OPTS__',      `-v -D miniuart -W 2500 -u reg')
+define(`__PROCNTO__',           `procnto-smp-instr')
+define(`__PROCNTO_OPTS__',      `-v')
+
+## Console
+define(`__CONSOLE__',           `__DEVC_SER1_DEV__')
+
+## ENV profile, use to overwrite the common /etc/profile
+#define(`__ENV_PROFILE_FILE__',  `etc/profile')
+#define(`__PROFILE_CFG__',       `/__ENV_PROFILE_FILE__ = {
+#export HOME=/
+#export SYSNAME=nto
+#export TERM=qansi
+#export PATH=/proc/boot:/sbin:/bin:/usr/bin:/usr/sbin:/usr/libexec
+#export LD_LIBRARY_PATH=/proc/boot:/lib:/usr/lib:/lib/dll:/lib/dll/pci
+#}')
+
+## Audio driver
+
+## Block driver
+define(`__BLOCK_DRVR__', `devb-sdmmc-bcm2711')
+
+#define(`__DEVB_AHCI_START__', `')
+
+#define(`__DEVB_EIDE_DRVR__', `')
+#define(`__DEVB_EIDE_OPTS__', `')
+#define(`__DEVB_EIDE_DEV__', `')
+
+#define(`__DEVB_NVME_DRVR__', `')
+#define(`__DEVB_NVME_OPTS__', `')
+#define(`__DEVB_NVME_DEV__', `')
+
+#define(`__DEVB_RAM_DRVR__', `')
+#define(`__DEVB_RAM_OPTS__', `')
+#define(`__DEVB_RAM_DEV__', `')
+
+define(`__DEVB_SDMMC_DRVR__', `devb-sdmmc-bcm2711')
+define(`__DEVB_SDMMC_OPTS__', `mem name=below1G sdio addr=0xfe340000,irq=158 disk name=sd')
+define(`__DEVB_SDMMC_DEV__', `/dev/sd0')
+
+define(`__DEVB_SDMMC_START__', `
+    #######################################################################
+    ## SD memory card / eMMC driver
+    ## Note: "bmstr_base" option is required for busmaster memory
+    ## address translation
+    #######################################################################
+    display_msg "Starting SDMMC driver (/dev/sd0)"
+    __DEVB_SDMMC_DRVR__ __DEVB_SDMMC_OPTS__
+    waitfor __DEVB_SDMMC_DEV__
+')
+
+define(`__DEVB_DRVR_START__', `
+__DEVB_SDMMC_START__
+')
+
+## Network driver
+define(`__NET_DRVR__', `devs-genet.so')
+define(`__NET_OPTS__', `-m fdt -m phy_fdt -d genet')
+define(`__NET_DEV__', `genet0')
+
+## The io-sock use dhcpcd utility by default, uncomment the line below to use dhclient utility
+#define(`__NET_DHCLIENT_SUPPORT__', `')
+
+## WIFI Network driver(BCM4339)
+#define(`__WIFI_START__', `
+    #######################################################################
+    ## WIFI Network driver(BCM4339)
+    #######################################################################
+    #display_msg Starting WIFI Network driver...
+    #mount -T io-pkt -o fw=/etc/hotspot/firmware.bin,clm_blob=/etc/hotspot/firmware.clm_blob /lib/dll/devnp-qwdi-2.5_bcm4339-rpi4.so
+    #create a wpa_supplicant.conf file in /tmp directory
+    #wpa_supplicant -D qwdi -i bcm0 -c /tmp/wpa_supplicant.conf -C /tmp/ &
+    #dhclient -m -lf /dev/shmem/dhclient.leases -pf /dev/shmem/dhclient.pid -nw bcm0
+#')
+
+## USB host driver
+define(`__USB_HOST_DRVR__', `devu-hcd-bcm2711-xhci.so')
+
+define(`__USB_START__', `
+    #######################################################################
+    ## USB OTG Host Controller driver
+    #######################################################################
+    sh /proc/boot/usb_start.sh
+')
+
+## Persistent storge
+#define(`__PERSISTENT_STORAGE_DEVICE__', `/dev/sd0t179')
+#define(`__PERSISTENT_STORAGE_MOUNT_POINT__', `')
+#define(`__PERSISTENT_STORAGE_MOUNT_OPTS__', `-o sync=optional')
+#define(`__PERSISTENT_STORAGE_START__', `')
+#define(`__PERSISTENT_STORAGE_FILES__', `')
+
+## Serial driver
+define(`__DEVC_DRVR__', `__DEVC_SER1_DRVR__, __DEVC_SER3_DRVR__')
+
+define(`__DEVC_SER1_DRVR__', `devc-serminiuart')
+define(`__DEVC_SER1_OPTS__', `-b115200 -c500000000 -e -F -u1 0xfe215000,125')
+define(`__DEVC_SER1_DEV__', `/dev/ser1')
+define(`__DEVC_SER3_DRVR__', `devc-serpl011')
+define(`__DEVC_SER3_OPTS__', `-b115200 -c48000000 -e -F -u3 0xfe201600,153')
+define(`__DEVC_SER3_DEV__', `/dev/ser3')
+
+define(`__DEVC_START__', `
+    #######################################################################
+    ## Console SERIAL driver
+    #######################################################################
+    display_msg "Starting serial driver (__DEVC_SER1_DEV__)"
+    __DEVC_SER1_DRVR__ __DEVC_SER1_OPTS__
+
+    `#'display_msg "Starting serial driver (__DEVC_SER3_DEV__)"
+    `#'__DEVC_SER3_DRVR__ __DEVC_SER3_OPTS__
+')
+
+## I2C driver
+define(`__I2C_DRVR__', `i2c-bcm2711')
+define(`__I2C_OPTS__', `-p0xfe804000 --b100000 --u1')
+define(`__I2C_DEV__', `/dev/i2c1')
+
+## SPI driver
+define(`__IO_SPI_DRVR__', `spi-bcm2711')
+
+define(`__IO_SPI_CFG_CONTENTS__', `
+[globals]
+verbose=5
+
+[bus]
+busno=0
+name=spi0
+base=0xfe204000
+irq=150
+input_clock=500000000
+bs=rpanic=48,tpanic=16
+dma_attach_opts=num_cbs=256,range_min=0,range_max=14,typed_mem=sysram&below1G
+dma_thld=4
+
+[dev]
+parent_busno=0
+devno=0
+name=dev0
+clock_rate=5000000
+cpha=1
+cpol=0
+bit_order=msb
+word_width=32
+idle_insert=1
+
+[dev]
+parent_busno=0
+devno=1
+name=dev1
+cpha=0
+cpol=1
+word_width=32
+clock_rate=5000000
+
+[bus]
+busno=3
+name=spi3
+base=0xfe204600
+irq=151
+input_clock=500000000
+
+[dev]
+parent_busno=3
+devno=0
+name=dev0
+cpha=0
+cpol=1
+word_width=8
+clock_rate=5000000
+')
+
+## Random
+#define(`__RANDOM_DRVR__', `')
+#define(`__RANDOM_DRVR_OPTS__', `')
+
+## WDT kick
+define(`__WDT_DRVR__', `wdtkick')
+define(`__WDT_OPTS__', `-W0x24:0x5A028E4C -W0x1c:0x5A000020')
+
+define(`__WDT_START__', `
+    ############################################################################################
+    ## WatchDog utility
+    ## If startup is given -W parameter then the wdtkick utility MUST be uncommented below
+    ############################################################################################
+    display_msg "Starting wdtkick ..."
+    __WDT_DRVR__ __WDT_OPTS__
+')
+
+## Customize script
+define(`__CUSTOMIZE_SCRIPT_NAME__', `/scripts/board_startup.sh')
+#define(`__CUSTOMIZE_SCRIPT_START__', `')
+#define(`__CUSTOMIZE_SCRIPT_FILES__', `')
+
+## PCI driver
+define(`__PCI_HW_DRVR__', `pci_hw-bcm2711-rpi4.so')
+define(`__PCI_HW_MODULE__', `pci_hw-bcm2711-rpi4.so')
+define(`__PCI_BUS_SCAN_LIMIT__', `1')
+#define(`__PCI_MODULE_BLACKLIST__', `')
+define(`__PCI_OPTS__', `--bus-scan-limit=__PCI_BUS_SCAN_LIMIT__ -c')
+
+define(`__PCI_START__', `
+    ############################################################################################
+    ## PCIe driver
+    ############################################################################################
+    display_msg "Starting PCI Server ..."
+    PCI_HW_MODULE=/lib/dll/pci/pci_hw-bcm2711-rpi4.so
+    PCI_BKWD_COMPAT_MODULE=/lib/dll/pci/pci_bkwd_compat.so
+    PCI_SLOG_MODULE=/lib/dll/pci/pci_slog2.so
+    PCI_DEBUG_MODULE=/lib/dll/pci/pci_debug2.so
+
+    pci-server __PCI_OPTS__ &
+    waitfor /dev/pci
+')
+
+
+## Board specific files
+#define(`__BOARD_EARLY_START__', `')
+#define(`__BOARD_LATE_START__', `')
+
+define(`__BOARD_FILES__', `
+
+################################################################################################
+## Script for launching the io-usb-otg
+################################################################################################
+usb_start.sh = {
+#!/bin/sh
+    VL805_VERSION=/dev/shmem/vl805_version.txt
+    pci-tool -d 1:0:0 --read="CFG:0x50" > $VL805_VERSION
+    if grep "50] 00000000" $VL805_VERSION > /dev/null; then
+        echo "Inform vc to load vl805 firmware"
+        mbox-bcm2711 notifyxhcireset=0x100000 > /dev/null 2>&1
+    fi
+    echo "Starting USB xHCI controller in the host mode (/dev/usb/*)..."
+    io-usb-otg -t memory=below1G -d bcm2711-xhci pindex=0,memory=below1G
+    waitfor /dev/usb/io-usb-otg
+    waitfor /dev/usb/devu-hcd-bcm2711-xhci.so
+}
+
+################################################################################################
+## GPIO utility
+################################################################################################
+/bin/gpio-bcm2711=gpio-bcm2711
+
+################################################################################################
+## Mailbox utility
+################################################################################################
+/bin/mbox-bcm2711=mbox-bcm2711
+
+################################################################################################
+## WIFI firmware and WPA utilities
+################################################################################################
+#[search=../install/etc/firmware] /etc/hotspot/firmware.bin=brcmfmac43455-sdio.bin
+#[search=../install/etc/firmware] /etc/hotspot/nvram.txt=brcmfmac43455-sdio.txt
+#[search=../install/etc/firmware] /etc/hotspot/firmware.clm_blob=brcmfmac43455-sdio.clm_blob
+#/usr/sbin/wpa_cli=wpa_cli
+#/usr/sbin/wpa_passphrase=wpa_passphrase
+#/usr/sbin/wpa_supplicant=wpa_supplicant
+
+#[perms=0555] /etc/wpa_act={
+#!/bin/sh
+#case $2 in
+#CONNECTED) echo $0 $1 $2 ID=$WPA_ID STR=$WPA_ID_STR >/dev/console; dhcp.$1 -D rpi4 -i $1 ;;
+#DISCONNECTED) echo $0 $1 $2 >/dev/console; slay -f dhcp.$1; ifconfig $1 delete ;;
+#esac
+#}
+')
+

images/rpi4.build

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+################################################################################################
+##
+## Build file for a QNX operating system
+##
+################################################################################################
+
+[-optional]
+[+keeplinked]
+[image=0x80000]
+[virtual=aarch64le,raw -compress] boot = {
+    startup-bcm2711-rpi4 -v -D miniuart -W 2500 -u reg 
+    PATH=/proc/boot:/sbin:/bin:/usr/bin:/usr/sbin:/usr/libexec LD_LIBRARY_PATH=/proc/boot:/lib:/usr/lib:/lib/dll:/lib/dll/pci procnto-smp-instr -v
+}
+
+[+script] startup-script = {
+    SYSNAME=nto
+    TERM=qansi
+    ENV=/etc/profile
+
+    procmgr_symlink ../../proc/boot/ldqnx-64.so.2 /usr/lib/ldqnx-64.so.2
+
+    ## Needed for ksh to run the echo command below
+    pipe
+
+    display_msg " "
+    ksh -c "echo Welcome to QNX $(uname -r) on $(uname -m) !"
+    display_msg " "
+
+    slogger2
+    dumper
+    mqueue
+    random 
+
+
+    ############################################################################################
+    ## WatchDog utility
+    ## If startup is given -W parameter then the wdtkick utility MUST be uncommented below
+    ############################################################################################
+    display_msg "Starting wdtkick ..."
+    wdtkick -W0x24:0x5A028E4C -W0x1c:0x5A000020
+
+
+    ############################################################################################
+    ## I2C driver
+    ############################################################################################
+    display_msg "Starting I2C driver ..."
+    i2c-bcm2711 -p0xfe804000 --b100000 --u1
+
+
+    ############################################################################################
+    ## PCIe driver
+    ############################################################################################
+    display_msg "Starting PCI Server ..."
+    PCI_HW_MODULE=/lib/dll/pci/pci_hw-bcm2711-rpi4.so
+    PCI_BKWD_COMPAT_MODULE=/lib/dll/pci/pci_bkwd_compat.so
+    PCI_SLOG_MODULE=/lib/dll/pci/pci_slog2.so
+    PCI_DEBUG_MODULE=/lib/dll/pci/pci_debug2.so
+
+    pci-server --bus-scan-limit=1 -c &
+    waitfor /dev/pci
+
+
+    #######################################################################
+    ## Console SERIAL driver
+    #######################################################################
+    display_msg "Starting serial driver (/dev/ser1)"
+    devc-serminiuart -b115200 -c500000000 -e -F -u1 0xfe215000,125
+
+    #display_msg "Starting serial driver (/dev/ser3)"
+    #devc-serpl011 -b115200 -c48000000 -e -F -u3 0xfe201600,153
+
+
+    ############################################################################################
+    ## SPI driver
+    ############################################################################################
+    display_msg "Starting SPI master driver ..."
+    spi-bcm2711 
+    waitfor /dev/io-spi
+
+
+
+    #######################################################################
+    ## SD memory card / eMMC driver
+    ## Note: "bmstr_base" option is required for busmaster memory
+    ## address translation
+    #######################################################################
+    display_msg "Starting SDMMC driver (/dev/sd0)"
+    devb-sdmmc-bcm2711 mem name=below1G sdio addr=0xfe340000,irq=158 disk name=sd
+    waitfor /dev/sd0
+
+
+
+    #######################################################################
+    ## USB OTG Host Controller driver
+    #######################################################################
+    sh /proc/boot/usb_start.sh
+
+
+    ############################################################################################
+    ## Storage service
+    ############################################################################################
+    /proc/boot/.storage-server.sh
+
+
+    ############################################################################################
+    ## Network driver
+    ############################################################################################
+    display_msg "Starting networking ..."
+    io-sock  -m phy -m fdt -m phy_fdt -d genet -m pci -d em -d ix -d re -m usb -d axe -d axge -d cdce -d smsc 
+
+
+    ############################################################################################
+    ## DHCP client
+    ############################################################################################
+    display_msg "Starting DHCP client ..."
+    dhcpcd -bqq
+
+    ############################################################################################
+    ## SSH daemon
+    ############################################################################################
+    /proc/boot/.ssh-server.sh
+
+    ############################################################################################
+    ## REMOTE_DEBUG: gdb or Momentics
+    ##  - refer to the help documentation for the gdb, qconn and the IDE
+    ##    for more information on remote debugging
+    ##  - the commands shown require that NETWORK is enabled too
+    ############################################################################################
+    display_msg "Starting devc-pty manager ..."
+    devc-pty
+
+    display_msg "Starting qconn daemon ..."
+    qconn
+
+
+    ############################################################################################
+    ## Customize startup components
+    ############################################################################################
+    ksh /proc/boot/customize_startup.sh
+
+
+    ############################################################################################
+    ## Start the main shell
+    ############################################################################################
+    reopen /dev/ser1
+    display_msg "Starting shell ..."
+    [+session] ksh &
+}
+
+
+[uid=0 gid=0]
+
+[type=link] /bin/sh=/bin/ksh
+[type=link] /tmp=/dev/shmem
+[type=link] /dev/console=/dev/ser1
+[type=link] /var/log=/tmp
+[type=link] /usr/tmp=/tmp
+
+
+################################################################################################
+## WDT driver
+################################################################################################
+/bin/wdtkick=wdtkick
+
+
+################################################################################################
+## Serial drivers
+################################################################################################
+/sbin/devc-serminiuart=devc-serminiuart
+/sbin/devc-serpl011=devc-serpl011
+
+
+################################################################################################
+## NOR flash driver files
+################################################################################################
+/sbin/devf-ram=devf-ram
+
+/usr/bin/flashctl=flashctl
+
+
+################################################################################################
+## Block drivers
+################################################################################################
+/sbin/devb-sdmmc-bcm2711=devb-sdmmc-bcm2711
+
+################################################################################################
+## Block driver support libraries
+################################################################################################
+/lib/libcam.so=libcam.so
+
+/lib/dll/io-blk.so=io-blk.so
+/lib/dll/cam-disk.so=cam-disk.so
+/lib/dll/cam-cdrom.so=cam-cdrom.so
+/lib/dll/fs-qnx6.so=fs-qnx6.so
+/lib/dll/fs-dos.so=fs-dos.so
+
+
+################################################################################################
+## Storage script
+################################################################################################
+[perms=0744] .storage-server.sh = {
+#!/bin/ksh
+
+## Check if the /var/run directory exists
+if [ ! -d /var/run ]
+then
+    ## Use devf-ram file system for dhcpcd service
+    echo "Starting devf-ram filesystem ..."
+    devf-ram -i 9,0 -s0,16m
+    waitfor /dev/fs9p0
+
+    flashctl -p /dev/fs9p0 -e -f -n /var -m
+    mkdir -m 755 /var/run
+    mkdir -m 755 /var/db
+fi
+}
+
+
+
+################################################################################################
+## Network driver files
+################################################################################################
+/lib/dll/devs-genet.so=devs-genet.so
+
+/lib/dll/devs-em.so=devs-em.so
+/lib/dll/devs-ix.so=devs-ix.so
+/lib/dll/devs-re.so=devs-re.so
+
+/lib/dll/devs-axe.so=devs-axe.so
+/lib/dll/devs-axge.so=devs-axge.so
+/lib/dll/devs-cdce.so=devs-cdce.so
+/lib/dll/devs-smsc.so=devs-smsc.so
+
+################################################################################################
+## Network driver shared libraries
+################################################################################################
+/usr/lib/libedit.so=libedit.so
+/usr/lib/libexpat.so=libexpat.so
+/usr/lib/libfdt.so=libfdt.so
+/usr/lib/librpc.so.2=librpc.so.2
+/usr/lib/libxo.so.0=libxo.so.0
+
+/lib/libsocket.so=libsocket.so
+/lib/libjail.so=libjail.so
+
+/lib/dll/mods-phy.so=mods-phy.so
+/lib/dll/mods-pci.so=mods-pci.so
+/lib/dll/mods-usb.so=mods-usb.so
+/lib/dll/mods-fdt.so=mods-fdt.so
+/lib/dll/mods-phy_fdt.so=mods-phy_fdt.so
+
+################################################################################################
+## Network driver and support
+################################################################################################
+/sbin/dhcpcd=dhcpcd
+/sbin/dhcpcd-run-hooks=${QNX_TARGET}/sbin/dhcpcd-run-hooks
+/sbin/dhcpcd-hooks/20-resolv.conf=${QNX_TARGET}/sbin/dhcpcd-hooks/20-resolv.conf
+/sbin/ifconfig=ifconfig
+/sbin/io-sock=io-sock
+/sbin/pfctl=pfctl
+[uid=0 gid=0 perms=4755] /sbin/ping=ping
+/sbin/route=route
+/sbin/sysctl=sysctl
+
+/usr/bin/netstat=netstat
+/usr/bin/sockstat=sockstat
+/usr/bin/vmstat=vmstat
+
+/usr/sbin/arp=arp
+/usr/sbin/devctl=devctl
+/usr/sbin/devinfo=devinfo
+/usr/sbin/fs-nfs3=fs-nfs3
+/usr/sbin/if_up=if_up
+/usr/sbin/ifmcstat=ifmcstat
+/usr/sbin/ifwatchd=ifwatchd
+/usr/sbin/ip6addrctl=ip6addrctl
+/usr/sbin/ndp=ndp
+/usr/sbin/tcpdump=tcpdump
+[uid=0 gid=0 perms=4755] /usr/sbin/traceroute=traceroute
+[uid=0 gid=0 perms=4755] /usr/sbin/traceroute6=traceroute6
+
+/etc/dhcpcd.conf=${QNX_TARGET}/etc/dhcpcd.conf
+/etc/hosts=${QNX_TARGET}/etc/hosts
+/etc/netconfig=${QNX_TARGET}/etc/netconfig
+/etc/protocols=${QNX_TARGET}/etc/protocols
+/etc/services=${QNX_TARGET}/etc/services
+
+################################################################################################
+## Remote_debug
+################################################################################################
+/sbin/devc-pty=devc-pty
+
+/usr/bin/pdebug=pdebug
+
+/usr/sbin/qconn=qconn
+
+################################################################################################
+## Network services (ssh and dhcpcd) support
+################################################################################################
+[uid=0 gid=0 perms=0755] /usr/sbin/sshd=sshd
+
+[uid=0 gid=0 perms=0755] /usr/libexec/sftp-server=${QNX_TARGET}/${PROCESSOR}/usr/libexec/sftp-server
+
+[uid=0 gid=0 perms=0755] /usr/bin/scp=scp
+[uid=0 gid=0 perms=0755] /usr/bin/ssh=ssh
+[uid=0 gid=0 perms=0755] /usr/bin/ssh-keygen=ssh-keygen
+
+[type=link] /etc/ssh = /dev/shmem
+/dev/shmem/sshd_config=${QNX_TARGET}/etc/ssh/sshd_config
+
+/etc/esh = {
+}
+
+[perms=0744] .ssh-server.sh={
+#!/bin/ksh
+
+## Create the ssh keys if they do not exist
+if [ ! -f /etc/ssh/ssh_host_rsa_key ]
+then
+    ssh-keygen -q -t rsa -N "" -f /etc/ssh/ssh_host_rsa_key
+fi
+
+if [ ! -f /etc/ssh/ssh_host_ecdsa_key ]
+then
+    ssh-keygen -q -t ecdsa -N "" -f /etc/ssh/ssh_host_ecdsa_key
+fi
+
+if [ ! -f /etc/ssh/ssh_host_ed25519_key ]
+then
+    ssh-keygen -q -t ed25519 -N "" -f /etc/ssh/ssh_host_ed25519_key
+fi
+
+## Start SSH daemon
+    echo "Starting SSH daemon ..."
+    /usr/sbin/sshd
+}
+
+
+
+################################################################################################
+## USB host drivers
+################################################################################################
+/lib/dll/devu-hcd-bcm2711-xhci.so=devu-hcd-bcm2711-xhci.so
+
+################################################################################################
+## USB host shared libraries
+################################################################################################
+/lib/libhiddi.so=libhiddi.so
+/lib/libusbdi.so=libusbdi.so
+
+################################################################################################
+## USB host driver and support
+################################################################################################
+/sbin/io-usb-otg=io-usb-otg
+/sbin/usb=usb
+/sbin/devb-umass=devb-umass
+
+################################################################################################
+## USB device shared libraries
+################################################################################################
+/lib/libusbdci.so=libusbdci.so
+
+
+################################################################################################
+## I2C drivers
+################################################################################################
+/sbin/i2c-bcm2711=i2c-bcm2711
+
+################################################################################################
+## I2C support
+################################################################################################
+/bin/isendrecv=isendrecv
+/bin/isend=isend
+
+
+################################################################################################
+## PCI driver HW Modules and configuration file
+################################################################################################
+/lib/dll/pci/pci_hw-bcm2711-rpi4.so=pci/pci_hw-bcm2711-rpi4.so
+
+
+################################################################################################
+## PCIe driver shared libraries
+################################################################################################
+/lib/libpci.so=libpci.so
+
+/lib/dll/pci/pci_bkwd_compat.so=pci/pci_bkwd_compat.so
+/lib/dll/pci/pci_cap-0x01.so=pci/pci_cap-0x01.so
+/lib/dll/pci/pci_cap-0x04.so=pci/pci_cap-0x04.so
+/lib/dll/pci/pci_cap-0x05.so=pci/pci_cap-0x05.so
+/lib/dll/pci/pci_cap-0x07.so=pci/pci_cap-0x07.so
+/lib/dll/pci/pci_cap-0x09-ffffffff.so=pci/pci_cap-0x09-ffffffff.so
+/lib/dll/pci/pci_cap-0x0d.so=pci/pci_cap-0x0d.so
+/lib/dll/pci/pci_cap-0x10-16c3abcd.so=pci/pci_cap-0x10-16c3abcd.so
+/lib/dll/pci/pci_cap-0x10-19570400.so=pci/pci_cap-0x10-19570400.so
+/lib/dll/pci/pci_cap-0x10.so=pci/pci_cap-0x10.so
+/lib/dll/pci/pci_cap-0x11-ffffffff.so=pci/pci_cap-0x11-ffffffff.so
+/lib/dll/pci/pci_cap-0x11.so=pci/pci_cap-0x11.so
+/lib/dll/pci/pci_cap-0x12.so=pci/pci_cap-0x12.so
+/lib/dll/pci/pci_cap-0x13.so=pci/pci_cap-0x13.so
+/lib/dll/pci/pci_debug.so=pci/pci_debug.so
+/lib/dll/pci/pci_debug2.so=pci/pci_debug2.so
+/lib/dll/pci/pci_server-buscfg-generic.so=pci/pci_server-buscfg-generic.so
+/lib/dll/pci/pci_server-buscfg-hotplug.so=pci/pci_server-buscfg-hotplug.so
+/lib/dll/pci/pci_server-buscfg2-generic.so=pci/pci_server-buscfg2-generic.so
+/lib/dll/pci/pci_server-buscfg2-hotplug.so=pci/pci_server-buscfg2-hotplug.so
+/lib/dll/pci/pci_server-enable_features.so=pci/pci_server-enable_features.so
+/lib/dll/pci/pci_server-event_handler.so=pci/pci_server-event_handler.so
+/lib/dll/pci/pci_server-namespace.so=pci/pci_server-namespace.so
+/lib/dll/pci/pci_slog.so=pci/pci_slog.so
+/lib/dll/pci/pci_slog2.so=pci/pci_slog2.so
+/lib/dll/pci/pci_strings.so=pci/pci_strings.so
+/lib/dll/pci/pcie_xcap-0x0001.so=pci/pcie_xcap-0x0001.so
+/lib/dll/pci/pcie_xcap-0x0003.so=pci/pcie_xcap-0x0003.so
+/lib/dll/pci/pcie_xcap-0x000b-ffffffff.so=pci/pcie_xcap-0x000b-ffffffff.so
+/lib/dll/pci/pcie_xcap-0x0015.so=pci/pcie_xcap-0x0015.so
+
+################################################################################################
+## PCIe driver and support
+################################################################################################
+/sbin/pci-server=pci-server
+
+/usr/sbin/pci-tool=pci-tool
+/usr/sbin/rsrcdb_query=rsrcdb_query
+
+/etc/system/config/pci/pcidatabase.com-tab_delimited.txt=${QNX_TARGET}/etc/system/config/pci/pcidatabase.com-tab_delimited.txt
+
+
+################################################################################################
+## SPI driver
+################################################################################################
+/sbin/spi-bcm2711=spi-bcm2711
+
+/etc/system/config/spi/spi.conf = {
+# See spi-template.conf or SDP docs for a full description of the configuration fields.
+
+[globals]
+verbose=5
+
+[bus]
+busno=0
+name=spi0
+base=0xfe204000
+irq=150
+input_clock=500000000
+bs=rpanic=48,tpanic=16
+dma_attach_opts=num_cbs=256,range_min=0,range_max=14,typed_mem=sysram&below1G
+dma_thld=4
+
+[dev]
+parent_busno=0
+devno=0
+name=dev0
+clock_rate=5000000
+cpha=1
+cpol=0
+bit_order=msb
+word_width=32
+idle_insert=1
+
+[dev]
+parent_busno=0
+devno=1
+name=dev1
+cpha=0
+cpol=1
+word_width=32
+clock_rate=5000000
+
+[bus]
+busno=3
+name=spi3
+base=0xfe204600
+irq=151
+input_clock=500000000
+
+[dev]
+parent_busno=3
+devno=0
+name=dev0
+cpha=0
+cpol=1
+word_width=8
+clock_rate=5000000
+
+}
+
+
+################################################################################################
+## Shared libraries for security
+################################################################################################
+/lib/libqh.so=libqh.so
+/lib/libregex.so=libregex.so
+/lib/libsecpol.so=libsecpol.so
+/lib/libslog2parse.so=libslog2parse.so
+/lib/libslog2shim.so=libslog2shim.so
+/lib/libslog2.so=libslog2.so
+/lib/libtracelog.so=libtracelog.so
+
+/lib/dll/qcrypto-openssl-3.so=qcrypto-openssl-3.so
+
+/usr/lib/libcrypto.so=libcrypto.so
+/usr/lib/libncursesw.so=libncursesw.so
+/usr/lib/libqcrypto.so=libqcrypto.so
+/usr/lib/libssl.so=libssl.so
+
+################################################################################################
+## libqcrypto support
+################################################################################################
+[uid=0 gid=0 perms=0644] /etc/qcrypto.conf = {
+openssl-3     tags=*
+}
+
+################################################################################################
+## Security files
+################################################################################################
+[uid=0 gid=0 perms=4755] /bin/login=login
+[uid=0 gid=0 perms=4755] /bin/su=su
+
+[uid=0 gid=0 perms=4755] /usr/bin/passwd=passwd
+
+[uid=0 gid=0 perms=0644] /etc/passwd = {
+root:x:0:0:Superuser:/root:/bin/sh
+sshd:x:15:6:sshd:/var/chroot/sshd:/bin/false
+qnxuser:x:1000:1000:QNX User:/home/qnxuser:/bin/sh
+}
+
+## Enabled Username/Password: root/root, qnxuser/qnxuser
+[uid=0 gid=0 perms=0644] /etc/shadow = {
+root:@S@NKlWES1quMp1wmqugkUSnFEpPGn58kIs4wQOgDDNs06vimR+bbGPUKM+9P6jbFUzo3Rm+Qe5MS+17xKhwaeJEg==@Mjg5ZTJiMTM0YTRjYTE2ZGFjMDdhZTFlY2NlMDVmNmE=:1468494669:0:0
+sshd:*:1231323780:0:0
+qnxuser:@S@HZERXjgixvb3157FFeraShhvTVw+10ccUtVUVZbi0fUwpzlzBZFw5gHiFd1XHKit8D39Whe749XAY8fV4P5ANQ==@Y2ZlOTg3M2RhNTM4Y2M2ODY0OWZhODdiNDRkMmU5Nzg=:1468488235:0:0
+}
+
+[uid=0 gid=0 perms=0644] /etc/group = {
+root:x:0:root
+sshd:x:6:
+qnxuser:x:1000
+}
+
+
+################################################################################################
+## PAM configurations addon build file
+################################################################################################
+[uid=0 gid=0 type=dir dperms=0755] /
+[uid=0 gid=0 type=dir dperms=0755] /etc
+[uid=0 gid=0 type=dir dperms=0755] /etc/pam.d
+[uid=0 gid=0 type=dir dperms=0755] /home
+[uid=1000 gid=1000 type=dir dperms=0755] /home/qnxuser
+[uid=0 gid=0 type=dir dperms=0755] /lib
+[uid=0 gid=0 type=dir dperms=0700] /root
+[uid=0 gid=0 type=dir dperms=0755] /usr
+[uid=0 gid=0 type=dir dperms=0755] /usr/lib
+[uid=0 gid=0 type=dir dperms=0755] /var
+[uid=0 gid=0 type=dir dperms=0755] /var/chroot
+[uid=0 gid=0 type=dir dperms=0755] /var/chroot/sshd
+
+[uid=0 gid=0 perms=0644] /etc/pam.d/login=${QNX_TARGET}/etc/pam.d/login
+[uid=0 gid=0 perms=0644] /etc/pam.d/passwd=${QNX_TARGET}/etc/pam.d/passwd
+[uid=0 gid=0 perms=0644] /etc/pam.d/su=${QNX_TARGET}/etc/pam.d/su
+
+[uid=0 gid=0 perms=0755] /usr/lib/libpam.so=libpam.so
+[uid=0 gid=0 perms=0755] /usr/lib/pam_deny.so=pam_deny.so
+[uid=0 gid=0 perms=0755] /usr/lib/pam_echo.so=pam_echo.so
+[uid=0 gid=0 perms=0755] /usr/lib/pam_exec.so=pam_exec.so
+[uid=0 gid=0 perms=0755] /usr/lib/pam_group.so=pam_group.so
+[uid=0 gid=0 perms=0755] /usr/lib/pam_permit.so=pam_permit.so
+[uid=0 gid=0 perms=0755] /usr/lib/pam_qnx.so=pam_qnx.so
+[uid=0 gid=0 perms=0755] /usr/lib/pam_rootok.so=pam_rootok.so
+[uid=0 gid=0 perms=0755] /usr/lib/pam_secpol.so=pam_secpol.so
+[uid=0 gid=0 perms=0755] /usr/lib/pam_self.so=pam_self.so
+
+
+################################################################################################
+## General shared libraries
+################################################################################################
+ldqnx-64.so.2=ldqnx-64.so.2
+
+/lib/libc.so=libc.so
+/lib/libcatalog.so=libcatalog.so
+/lib/libdevice-publisher.so=libdevice-publisher.so
+/lib/libgcc_s.so=libgcc_s.so
+/lib/libm.so=libm.so
+[+optional] /lib/libfsnotify.so=libfsnotify.so
+
+/usr/lib/libbacktrace.so=libbacktrace.so
+/usr/lib/libc++.so=libc++.so
+/usr/lib/libiconv.so=libiconv.so
+/usr/lib/libintl.so=libintl.so
+/usr/lib/libpanelw.so=libpanelw.so
+/usr/lib/libz.so=libz.so
+
+
+################################################################################################
+## General commands
+################################################################################################
+/bin/confstr=confstr
+/bin/df=df
+/bin/hostname=hostname
+/bin/kill=kill
+/bin/ksh=ksh
+/bin/mount=mount
+/bin/on=on
+/bin/pidin=pidin
+/bin/slay=slay
+/bin/slog2info=slog2info
+/bin/slogger2=slogger2
+/bin/sync=sync
+/bin/umount=umount
+/bin/waitfor=waitfor
+
+/sbin/mqueue=mqueue
+/sbin/pipe=pipe
+/sbin/shutdown=shutdown
+
+/usr/bin/getconf=getconf
+/usr/bin/hd=hd
+/usr/bin/ldd=ldd
+/usr/bin/setconf=setconf
+/usr/bin/top=top
+/usr/bin/use=use
+
+/usr/sbin/dumper=dumper
+/usr/sbin/random=random
+/usr/sbin/tracelogger=tracelogger
+
+
+################################################################################################
+## Toybox commands
+## Note: The toybox package combines many common Linux command line utilities together into
+##       a single, BSD-licensed executable. The following toybox commands are supported.
+##       Use one of the following commands to access help for a toybox command:
+##         toybox command_name --help
+##         command_name --help
+################################################################################################
+/usr/bin/toybox=toybox
+
+[type=link] /bin/cat=/usr/bin/toybox
+[type=link] /bin/chmod=/usr/bin/toybox
+[type=link] /bin/cp=/usr/bin/toybox
+[type=link] /bin/dd=/usr/bin/toybox
+[type=link] /bin/echo=/usr/bin/toybox
+[type=link] /bin/ln=/usr/bin/toybox
+[type=link] /bin/ls=/usr/bin/toybox
+[type=link] /bin/mkdir=/usr/bin/toybox
+[type=link] /bin/mv=/usr/bin/toybox
+[type=link] /bin/pwd=/usr/bin/toybox
+[type=link] /bin/rm=/usr/bin/toybox
+[type=link] /bin/sed=/usr/bin/toybox
+[type=link] /bin/uname=/usr/bin/toybox
+
+[type=link] /usr/bin/ascii=/usr/bin/toybox
+[type=link] /usr/bin/base64=/usr/bin/toybox
+[type=link] /usr/bin/basename=/usr/bin/toybox
+[type=link] /usr/bin/bc=/usr/bin/toybox
+[type=link] /usr/bin/bunzip2=/usr/bin/toybox
+[type=link] /usr/bin/bzcat=/usr/bin/toybox
+[type=link] /usr/bin/cal=/usr/bin/toybox
+[type=link] /usr/bin/chgrp=/usr/bin/toybox
+[type=link] /usr/bin/chown=/usr/bin/toybox
+[type=link] /usr/bin/cksum=/usr/bin/toybox
+[type=link] /usr/bin/clear=/usr/bin/toybox
+[type=link] /usr/bin/cmp=/usr/bin/toybox
+[type=link] /usr/bin/comm=/usr/bin/toybox
+[type=link] /usr/bin/cpio=/usr/bin/toybox
+[type=link] /usr/bin/crc32=/usr/bin/toybox
+[type=link] /usr/bin/cut=/usr/bin/toybox
+[type=link] /usr/bin/date=/usr/bin/toybox
+[type=link] /usr/bin/diff=/usr/bin/toybox
+[type=link] /usr/bin/dirname=/usr/bin/toybox
+[type=link] /usr/bin/dos2unix=/usr/bin/toybox
+[type=link] /usr/bin/du=/usr/bin/toybox
+[type=link] /usr/bin/egrep=/usr/bin/toybox
+[type=link] /usr/bin/env=/usr/bin/toybox
+[type=link] /usr/bin/expand=/usr/bin/toybox
+[type=link] /usr/bin/expr=/usr/bin/toybox
+[type=link] /usr/bin/false=/usr/bin/toybox
+[type=link] /usr/bin/fgrep=/usr/bin/toybox
+[type=link] /usr/bin/file=/usr/bin/toybox
+[type=link] /usr/bin/find=/usr/bin/toybox
+[type=link] /usr/bin/grep=/usr/bin/toybox
+[type=link] /usr/bin/groups=/usr/bin/toybox
+[type=link] /usr/bin/gunzip=/usr/bin/toybox
+[type=link] /usr/bin/gzip=/usr/bin/toybox
+[type=link] /usr/bin/head=/usr/bin/toybox
+[type=link] /usr/bin/id=/usr/bin/toybox
+[type=link] /usr/bin/install=/usr/bin/toybox
+[type=link] /usr/bin/link=/usr/bin/toybox
+[type=link] /usr/bin/logname=/usr/bin/toybox
+[type=link] /usr/bin/md5sum=/usr/bin/toybox
+[type=link] /usr/bin/mkfifo=/usr/bin/toybox
+[type=link] /usr/bin/mktemp=/usr/bin/toybox
+[type=link] /usr/bin/more=/usr/bin/toybox
+[type=link] /usr/bin/nl=/usr/bin/toybox
+[type=link] /usr/bin/nohup=/usr/bin/toybox
+[type=link] /usr/bin/od=/usr/bin/toybox
+[type=link] /usr/bin/paste=/usr/bin/toybox
+[type=link] /usr/bin/patch=/usr/bin/toybox
+[type=link] /usr/bin/printenv=/usr/bin/toybox
+[type=link] /usr/bin/printf=/usr/bin/toybox
+[type=link] /usr/bin/readlink=/usr/bin/toybox
+[type=link] /usr/bin/realpath=/usr/bin/toybox
+[type=link] /usr/bin/rmdir=/usr/bin/toybox
+[type=link] /usr/bin/seq=/usr/bin/toybox
+[type=link] /usr/bin/sha1sum=/usr/bin/toybox
+[type=link] /usr/bin/sleep=/usr/bin/toybox
+[type=link] /usr/bin/sort=/usr/bin/toybox
+[type=link] /usr/bin/split=/usr/bin/toybox
+[type=link] /usr/bin/stat=/usr/bin/toybox
+[type=link] /usr/bin/strings=/usr/bin/toybox
+[type=link] /usr/bin/tail=/usr/bin/toybox
+[type=link] /usr/bin/tar=/usr/bin/toybox
+[type=link] /usr/bin/tee=/usr/bin/toybox
+[type=link] /usr/bin/test=/usr/bin/toybox
+[type=link] /usr/bin/time=/usr/bin/toybox
+[type=link] /usr/bin/timeout=/usr/bin/toybox
+[type=link] /usr/bin/touch=/usr/bin/toybox
+[type=link] /usr/bin/true=/usr/bin/toybox
+[type=link] /usr/bin/truncate=/usr/bin/toybox
+[type=link] /usr/bin/tty=/usr/bin/toybox
+[type=link] /usr/bin/uniq=/usr/bin/toybox
+[type=link] /usr/bin/unix2dos=/usr/bin/toybox
+[type=link] /usr/bin/unlink=/usr/bin/toybox
+[type=link] /usr/bin/uudecode=/usr/bin/toybox
+[type=link] /usr/bin/uuencode=/usr/bin/toybox
+[type=link] /usr/bin/uuidgen=/usr/bin/toybox
+[type=link] /usr/bin/wc=/usr/bin/toybox
+[type=link] /usr/bin/which=/usr/bin/toybox
+[type=link] /usr/bin/whoami=/usr/bin/toybox
+[type=link] /usr/bin/xargs=/usr/bin/toybox
+[type=link] /usr/bin/xxd=/usr/bin/toybox
+[type=link] /usr/bin/yes=/usr/bin/toybox
+[type=link] /usr/bin/zcat=/usr/bin/toybox
+
+
+################################################################################################
+## ENV profile
+################################################################################################
+/etc/profile = {
+export HOME=/
+export SYSNAME=nto
+export TERM=qansi
+export PATH=/proc/boot:/sbin:/bin:/usr/bin:/usr/sbin:/usr/libexec
+export LD_LIBRARY_PATH=/proc/boot:/lib:/usr/lib:/lib/dll:/lib/dll/pci
+
+export PCI_HW_MODULE=/lib/dll/pci/pci_hw-bcm2711-rpi4.so
+export PCI_DEBUG_MODULE=/lib/dll/pci/pci_debug2.so
+export PCI_SLOG_MODULE=/lib/dll/pci/pci_slog2.so
+export PCI_BKWD_COMPAT_MODULE=/lib/dll/pci/pci_bkwd_compat.so
+}
+
+
+################################################################################################
+## Customize startup
+################################################################################################
+customize_startup.sh = {
+#!/bin/ksh
+
+if [ -e /scripts/board_startup.sh ]; then
+    echo "Starting board customize script ..."
+    ksh /scripts/board_startup.sh
+fi
+}
+
+
+
+################################################################################################
+## Script for launching the io-usb-otg
+################################################################################################
+usb_start.sh = {
+#!/bin/sh
+    VL805_VERSION=/dev/shmem/vl805_version.txt
+    pci-tool -d 1:0:0 --read="CFG:0x50" > $VL805_VERSION
+    if grep "50] 00000000" $VL805_VERSION > /dev/null; then
+        echo "Inform vc to load vl805 firmware"
+        mbox-bcm2711 notifyxhcireset=0x100000 > /dev/null 2>&1
+    fi
+    echo "Starting USB xHCI controller in the host mode (/dev/usb/*)..."
+    io-usb-otg -t memory=below1G -d bcm2711-xhci pindex=0,memory=below1G
+    waitfor /dev/usb/io-usb-otg
+    waitfor /dev/usb/devu-hcd-bcm2711-xhci.so
+}
+
+################################################################################################
+## GPIO utility
+################################################################################################
+/bin/gpio-bcm2711=gpio-bcm2711
+
+################################################################################################
+## Mailbox utility
+################################################################################################
+/bin/mbox-bcm2711=mbox-bcm2711
+
+################################################################################################
+## WIFI firmware and WPA utilities
+################################################################################################
+#[search=../install/etc/firmware] /etc/hotspot/firmware.bin=brcmfmac43455-sdio.bin
+#[search=../install/etc/firmware] /etc/hotspot/nvram.txt=brcmfmac43455-sdio.txt
+#[search=../install/etc/firmware] /etc/hotspot/firmware.clm_blob=brcmfmac43455-sdio.clm_blob
+#/usr/sbin/wpa_cli=wpa_cli
+#/usr/sbin/wpa_passphrase=wpa_passphrase
+#/usr/sbin/wpa_supplicant=wpa_supplicant
+
+#[perms=0555] /etc/wpa_act={
+#!/bin/sh
+#case  in
+#CONNECTED) echo __BOARD_FILES__   ID=$WPA_ID STR=$WPA_ID_STR >/dev/console; dhcp. -D rpi4 -i  ;;
+#DISCONNECTED) echo __BOARD_FILES__   >/dev/console; slay -f dhcp.; ifconfig  delete ;;
+#esac
+#}
+

manifest

@@ -0,0 +1,564 @@
+1223966828 124 ./readme.txt
+2113231072 1044 ./source.xml
+213522871 40856 ./binary_files_with_symbols/aarch64le/bin/mbox-bcm2711.sym
+906237257 53104 ./binary_files_with_symbols/aarch64le/bin/gpio-bcm2711.sym
+1092950936 87232 ./binary_files_with_symbols/aarch64le/bin/wdtkick.sym
+570794052 295024 ./binary_files_with_symbols/aarch64le/sbin/i2c-bcm2711.sym
+1083506325 554016 ./binary_files_with_symbols/aarch64le/sbin/spi-bcm2711.sym
+953237396 645744 ./binary_files_with_symbols/aarch64le/sbin/devb-sdmmc-bcm2711.sym
+2436827761 658160 ./binary_files_with_symbols/aarch64le/sbin/devc-serminiuart.sym
+2497171569 671592 ./binary_files_with_symbols/aarch64le/sbin/devc-serpl011.sym
+1302586966 2091080 ./binary_files_with_symbols/aarch64le/boot/sys/startup-bcm2711-rpi4.sym
+3860791860 507512 ./binary_files_with_symbols/aarch64le/lib/dll/devu-hcd-bcm2711-xhci.so.sym
+3968166381 10850360 ./binary_files_with_symbols/images/procnto-smp-instr.sym
+3434638065 328064 ./binary_files_with_symbols/images/startup-bcm2711-rpi4.sym
+2797307573 1173 ./Makefile
+543021542 4445 ./prebuilt/etc/system/config/spi/spi-template.conf
+2496184566 28104 ./prebuilt/aarch64le/bin/gpio-bcm2711
+289152483 24304 ./prebuilt/aarch64le/bin/wdtkick
+3703716546 18848 ./prebuilt/aarch64le/bin/mbox-bcm2711
+3233021932 39224 ./prebuilt/aarch64le/sbin/i2c-bcm2711
+3302914069 156056 ./prebuilt/aarch64le/sbin/devb-sdmmc-bcm2711
+4185420508 86544 ./prebuilt/aarch64le/sbin/devc-serpl011
+3611387251 86776 ./prebuilt/aarch64le/sbin/devc-serminiuart
+3975386084 69800 ./prebuilt/aarch64le/sbin/spi-bcm2711
+25307865 178658 ./prebuilt/aarch64le/usr/lib/libdma-bcm2711.a
+2435288929 3493030 ./prebuilt/aarch64le/usr/lib/libstartup.a
+1103996358 231072 ./prebuilt/aarch64le/boot/sys/startup-bcm2711-rpi4
+3444891627 127504 ./prebuilt/aarch64le/lib/dll/devu-hcd-bcm2711-xhci.so
+204381681 1162 ./prebuilt/usr/include/aarch64/asmoff.def
+2463176679 15844 ./prebuilt/usr/include/sys/syspage.h
+1912741675 9003 ./images/definitions.m4
+3543263991 29558 ./images/rpi4.build
+1493468848 33345576 ./images/ifs-rpi4.bin
+1963356823 1383 ./images/Makefile
+1834914161 54 ./src/Makefile
+2933640710 1365 ./src/hardware/spi/common.mk
+2960116141 12534 ./src/hardware/spi/bcm2711/dma.c
+2901773791 224 ./src/hardware/spi/bcm2711/bcm2711.use
+1969875143 5218 ./src/hardware/spi/bcm2711/config.c
+2671326944 3548 ./src/hardware/spi/bcm2711/intr.c
+4084978781 1634 ./src/hardware/spi/bcm2711/fini.c
+1355144110 32 ./src/hardware/spi/bcm2711/aarch64/Makefile
+2415649356 27 ./src/hardware/spi/bcm2711/aarch64/le/Makefile
+2381521787 1487 ./src/hardware/spi/bcm2711/setcfg.c
+3139110083 20 ./src/hardware/spi/bcm2711/extra.mk
+3520380892 65 ./src/hardware/spi/bcm2711/pinfo.mk
+565940646 28 ./src/hardware/spi/bcm2711/Makefile
+2179366834 7234 ./src/hardware/spi/bcm2711/init.c
+2504383616 8258 ./src/hardware/spi/bcm2711/bcm2711spi.h
+2408515793 4921 ./src/hardware/spi/bcm2711/xfer.c
+722256454 1443 ./src/hardware/spi/bcm2711/devinfo.c
+2685465194 1719 ./src/hardware/spi/bcm2711/drvinfo.c
+2226332934 3696 ./src/hardware/spi/bcm2711/wait.c
+502855156 28 ./src/hardware/spi/Makefile
+1051738244 466 ./src/hardware/spi/spi.use
+3452896705 3684 ./src/hardware/startup/boards/common.mk
+2201420220 3875 ./src/hardware/startup/boards/public/hw/omap_i2c.h
+490793546 1790 ./src/hardware/startup/boards/public/hw/hwinfo_bcm2711.h
+2847723544 4745 ./src/hardware/startup/boards/public/hw/hwinfo_p40xx.h
+501769411 3715 ./src/hardware/startup/boards/public/hw/hwinfo_imx6x.h
+596603103 3795 ./src/hardware/startup/boards/public/hw/mini_driver.h
+1158624598 2171 ./src/hardware/startup/boards/public/hw/hwinfo_rockchip.h
+1324397123 4238 ./src/hardware/startup/boards/public/hw/hwinfo_imx8x.h
+3250551216 6733 ./src/hardware/startup/boards/public/hw/hwinfo_rcar.h
+3482963167 6245 ./src/hardware/startup/boards/public/aarch64/imx8mn/imx_ocotp.h
+3266416315 52847 ./src/hardware/startup/boards/public/aarch64/imx8mn/imx_ccm.h
+2395836708 3552 ./src/hardware/startup/boards/public/aarch64/imx8mn/imx_iomuxc_gpr.h
+4214520187 12277 ./src/hardware/startup/boards/public/aarch64/imx8mn/imx_ddrc.h
+574450565 15348 ./src/hardware/startup/boards/public/aarch64/imx8mn/imx_gpc.h
+3908661867 80994 ./src/hardware/startup/boards/public/aarch64/imx8mn/imx_ccm_analog.h
+1722950789 4092 ./src/hardware/startup/boards/public/aarch64/imx8mn/imx_src.h
+45507904 8377 ./src/hardware/startup/boards/public/aarch64/ls1012a.h
+2376329652 17298 ./src/hardware/startup/boards/public/aarch64/bcm2711.h
+1677733904 9842 ./src/hardware/startup/boards/public/aarch64/mx8mq.h
+2354504524 9652 ./src/hardware/startup/boards/public/aarch64/mx8mm.h
+502566485 25022 ./src/hardware/startup/boards/public/aarch64/mx8mq_iomux.h
+504319201 11158 ./src/hardware/startup/boards/public/aarch64/s32v.h
+3578035594 24253 ./src/hardware/startup/boards/public/aarch64/mx8mm_iomux.h
+3101101013 4544 ./src/hardware/startup/boards/public/aarch64/ls20xx.h
+1620144433 19172 ./src/hardware/startup/boards/public/aarch64/a1000.h
+1362979416 3262 ./src/hardware/startup/boards/public/aarch64/rzg2l.h
+27280671 147924 ./src/hardware/startup/boards/public/aarch64/r-car-gen4.h
+2319539368 11346 ./src/hardware/startup/boards/public/aarch64/rk3588.h
+88725542 304957 ./src/hardware/startup/boards/public/aarch64/r-car-gen3.h
+1894296458 9001 ./src/hardware/startup/boards/public/aarch64/mx8mn.h
+1232781631 16628 ./src/hardware/startup/boards/public/aarch64/ls1043a.h
+4261244298 18095 ./src/hardware/startup/boards/public/aarch64/ls10x6a.h
+425223479 26176 ./src/hardware/startup/boards/public/aarch64/mx8mn_iomux.h
+847826579 3523 ./src/hardware/startup/boards/public/aarch64/ls10xx.h
+3370931345 18493 ./src/hardware/startup/boards/public/aarch64/s32g.h
+3132966059 6227 ./src/hardware/startup/boards/public/aarch64/imx8mm/imx_ocotp.h
+620100125 53626 ./src/hardware/startup/boards/public/aarch64/imx8mm/imx_ccm.h
+2449823572 5289 ./src/hardware/startup/boards/public/aarch64/imx8mm/imx_iomuxc_gpr.h
+1689339612 12259 ./src/hardware/startup/boards/public/aarch64/imx8mm/imx_ddrc.h
+3038574669 17536 ./src/hardware/startup/boards/public/aarch64/imx8mm/imx_gpc.h
+2686546141 80990 ./src/hardware/startup/boards/public/aarch64/imx8mm/imx_ccm_analog.h
+1952177521 7673 ./src/hardware/startup/boards/public/aarch64/imx8mm/imx_src.h
+232447405 62997 ./src/hardware/startup/boards/public/arm/mx6x.h
+3956752181 16832 ./src/hardware/startup/boards/public/arm/scif.h
+3871859230 9632 ./src/hardware/startup/boards/public/arm/dm6446.h
+2409082825 24199 ./src/hardware/startup/boards/public/arm/omap3530.h
+913053256 106020 ./src/hardware/startup/boards/public/arm/dra74x.h
+2828052979 59965 ./src/hardware/startup/boards/public/arm/renesas_reg.h
+2211700398 38816 ./src/hardware/startup/boards/public/arm/r-car.h
+2020378785 15507 ./src/hardware/startup/boards/public/arm/ls102x.h
+2803099864 16603 ./src/hardware/startup/boards/public/arm/imx7/imx7_flexcan.h
+2210330901 17104 ./src/hardware/startup/boards/public/arm/imx7/imx7_usdhc.h
+927011506 48326 ./src/hardware/startup/boards/public/arm/r-car-gen2.h
+2302476323 19748 ./src/hardware/startup/boards/public/arm/mx1.h
+2720636889 28630 ./src/hardware/startup/boards/public/arm/omap.h
+3579847901 33317 ./src/hardware/startup/boards/public/arm/dm816x.h
+2762800815 2598 ./src/hardware/startup/boards/bcm2711/init_wdt.c
+207613152 2856 ./src/hardware/startup/boards/bcm2711/callout_reboot_bcm2711.S
+3666883248 3291 ./src/hardware/startup/boards/bcm2711/callout_debug_miniuart.S
+2287550680 7909 ./src/hardware/startup/boards/bcm2711/main.c
+644757961 2855 ./src/hardware/startup/boards/bcm2711/init_intrinfo.c
+2202262298 13846 ./src/hardware/startup/boards/bcm2711/mbox.c
+1714757285 2255 ./src/hardware/startup/boards/bcm2711/mbox.h
+3724137018 1422 ./src/hardware/startup/boards/bcm2711/init_intrinfo.h
+1462639939 2292 ./src/hardware/startup/boards/bcm2711/board_smp.c
+2879654062 5273 ./src/hardware/startup/boards/bcm2711/bcm2711_init_board.c
+3592104529 30 ./src/hardware/startup/boards/bcm2711/Makefile
+1648784588 4472 ./src/hardware/startup/boards/bcm2711/init_board_type.c
+2196782113 3071 ./src/hardware/startup/boards/bcm2711/rpi4/rpi4_board_config.h
+372596184 127 ./src/hardware/startup/boards/bcm2711/rpi4/aarch64/Makefile
+1699826315 30 ./src/hardware/startup/boards/bcm2711/rpi4/aarch64/le/Makefile
+2643514024 1528 ./src/hardware/startup/boards/bcm2711/rpi4/rpi4_board_config.c
+3183640485 1373 ./src/hardware/startup/boards/bcm2711/rpi4/board.h
+4138597930 91 ./src/hardware/startup/boards/bcm2711/rpi4/pinfo.mk
+565940646 28 ./src/hardware/startup/boards/bcm2711/rpi4/Makefile
+2857984782 4808 ./src/hardware/startup/boards/bcm2711/rpi4/init_hwinfo.c
+3913658519 7278 ./src/hardware/startup/boards/bcm2711/callout_interrupt_bcm2711_msi.S
+1156723936 2115 ./src/hardware/startup/boards/bcm2711/_start.S
+3628510411 3324 ./src/hardware/startup/boards/bcm2711/bcm2711_init_raminfo.c
+1471714310 2698 ./src/hardware/startup/boards/bcm2711/bcm2711_startup.h
+3829216143 1254 ./src/hardware/startup/boards/bcm2711/init_asinfo.c
+3029709762 3180 ./src/hardware/startup/boards/bcm2711/hw_ser_miniuart.c
+3592104529 30 ./src/hardware/startup/boards/Makefile
+86901714 36 ./src/hardware/startup/Makefile
+2728789610 3191 ./src/hardware/startup/lib/fdt_smp_spin_start.c
+1286625930 1709 ./src/hardware/startup/lib/fdt_get_num64.c
+3584578949 1043 ./src/hardware/startup/lib/board_init.c
+2368749883 1711 ./src/hardware/startup/lib/hwitag_add_location.c
+999854222 1552 ./src/hardware/startup/lib/hwi_add_device.c
+2534535156 1036 ./src/hardware/startup/lib/ap_fail.c
+630464349 7126 ./src/hardware/startup/lib/common_options.c
+2769439412 1622 ./src/hardware/startup/lib/alloc_qtime.c
+1020393656 2820 ./src/hardware/startup/lib/fdt_tweak_cmdline.c
+1027989413 1140 ./src/hardware/startup/lib/hwi_add_location.c
+2736195269 2285 ./src/hardware/startup/lib/bootstrap_cmdline.c
+2447602827 1682 ./src/hardware/startup/lib/as_add64.c
+3016559746 1737 ./src/hardware/startup/lib/hwitag_set_nicaddr.c
+1169957083 1789 ./src/hardware/startup/lib/hwitag_set_ivecrange.c
+1550037134 1363 ./src/hardware/startup/lib/callout_memory_map_indirect.c
+3254417422 1734 ./src/hardware/startup/lib/hwibus_add_can.c
+3784531041 2906 ./src/hardware/startup/lib/fdt_get_intr_cells.c
+1272559150 1727 ./src/hardware/startup/lib/hwibus_add_i2c.c
+1891145104 1770 ./src/hardware/startup/lib/pci_write_cfg16.c
+3083047466 1649 ./src/hardware/startup/lib/hwitag_set_inputclk.c
+4262233005 1733 ./src/hardware/startup/lib/hwibus_add_sdio.c
+1278102906 1040 ./src/hardware/startup/lib/hwi_add_nicphyaddr.c
+1679362474 1584 ./src/hardware/startup/lib/hwitag_add_inputclk.c
+1142154631 1216 ./src/hardware/startup/lib/board_cpuconfig2.c
+1488708166 1594 ./src/hardware/startup/lib/fdt_get_str.c
+2700103440 1630 ./src/hardware/startup/lib/pci_read_cfg16.c
+2138740334 1322 ./src/hardware/startup/lib/startup_info.c
+615247655 3684 ./src/hardware/startup/lib/uefi.c
+3999930305 2386 ./src/hardware/startup/lib/hw_rtc_ds1386.c
+989852479 5897 ./src/hardware/startup/lib/init_raminfo_uefi.c
+2454055519 3606 ./src/hardware/startup/lib/hw_ser8250_pci.c
+1247119012 1195 ./src/hardware/startup/lib/ultoa_end.c
+91354316 1733 ./src/hardware/startup/lib/hwidev_add_uart.c
+3919718311 1073 ./src/hardware/startup/lib/ssp.c
+2900444296 1027 ./src/hardware/startup/lib/hwi_add_irq.c
+1737084732 5979 ./src/hardware/startup/lib/efi_entry_point.c
+730444565 1331 ./src/hardware/startup/lib/aarch64/elf_map.c
+410810675 980 ./src/hardware/startup/lib/aarch64/cpuid_a57.c
+2295361520 1444 ./src/hardware/startup/lib/aarch64/psci_call.S
+10295697 7421 ./src/hardware/startup/lib/aarch64/callout_interrupt_t18x_pcie.S
+1782334703 976 ./src/hardware/startup/lib/aarch64/boot_regs.c
+3283916094 4922 ./src/hardware/startup/lib/aarch64/init_mmu.c
+38822313 12115 ./src/hardware/startup/lib/aarch64/init_cpuinfo.c
+963857674 5731 ./src/hardware/startup/lib/aarch64/callout_interrupt_t18x_msi.S
+737846531 710 ./src/hardware/startup/lib/aarch64/cpuid_v1.c
+1780216540 1292 ./src/hardware/startup/lib/aarch64/cpu_startnext.c
+596555345 1140 ./src/hardware/startup/lib/aarch64/spin_shim_rtn.S
+2210083846 2237 ./src/hardware/startup/lib/aarch64/cstart.S
+2599276185 6157 ./src/hardware/startup/lib/aarch64/gic_v2.c
+3365910756 1219 ./src/hardware/startup/lib/aarch64/cpuid_d20.c
+1116895197 982 ./src/hardware/startup/lib/aarch64/cpuid_v8_aem.c
+2934709063 8800 ./src/hardware/startup/lib/aarch64/aarch64_map.c
+2502550452 8848 ./src/hardware/startup/lib/aarch64/callout_interrupt_t18x_pcie_ic6.S
+3851855227 2261 ./src/hardware/startup/lib/aarch64/vstart.S
+1554391673 1028 ./src/hardware/startup/lib/aarch64/cpuid_d15.c
+518227287 8448 ./src/hardware/startup/lib/aarch64/_start_el1.S
+1332246480 1071 ./src/hardware/startup/lib/aarch64/cpuid_a76.c
+2288526993 4199 ./src/hardware/startup/lib/aarch64/callout_debug_8250.S
+147857082 1413 ./src/hardware/startup/lib/aarch64/as_default.c
+468729212 2168 ./src/hardware/startup/lib/aarch64/spin_smp_init.S
+1993693449 1558 ./src/hardware/startup/lib/aarch64/board_find_acpi_rsdp_uefi.c
+2818527098 9995 ./src/hardware/startup/lib/aarch64/board_find_efi_smbios.c
+809469457 710 ./src/hardware/startup/lib/aarch64/cpuid_n1.c
+1677951254 2136 ./src/hardware/startup/lib/aarch64/is_uefi_boot.c
+630876363 8245 ./src/hardware/startup/lib/aarch64/callout_interrupt_qoriq_lsx_msi_v2.S
+3896112805 24 ./src/hardware/startup/lib/aarch64/a.le/Makefile
+3208845782 1877 ./src/hardware/startup/lib/aarch64/init_qtime_v8gt.c
+841981353 1076 ./src/hardware/startup/lib/aarch64/asmoff.c
+2389096052 2623 ./src/hardware/startup/lib/aarch64/smp_start.S
+3207006393 984 ./src/hardware/startup/lib/aarch64/cpuid_a78ae.c
+1741733505 3382 ./src/hardware/startup/lib/aarch64/callout_debug_pl011.S
+1070743729 1575 ./src/hardware/startup/lib/aarch64/init_mitigation_mem.c
+3351513777 3298 ./src/hardware/startup/lib/aarch64/callout_sendipi_gic_v3.S
+2933827253 2021 ./src/hardware/startup/lib/aarch64/callout_reboot_psci.S
+515753640 1705 ./src/hardware/startup/lib/aarch64/gic.c
+3524944394 1049 ./src/hardware/startup/lib/aarch64/map_callout_mem.c
+537228759 1054 ./src/hardware/startup/lib/aarch64/map_callout_io.c
+3293057210 748 ./src/hardware/startup/lib/aarch64/board_find_acpi_rsdp.c
+3520570448 1057 ./src/hardware/startup/lib/aarch64/cpuid_a35.c
+3413036182 7597 ./src/hardware/startup/lib/aarch64/callout_interrupt_qoriq_lsx_msi_v1.S
+1543411233 1234 ./src/hardware/startup/lib/aarch64/aarch64_cpuid.c
+1490150329 980 ./src/hardware/startup/lib/aarch64/cpuid_a72.c
+2489042231 5586 ./src/hardware/startup/lib/aarch64/aarch64_sysctl.S
+1413803830 3327 ./src/hardware/startup/lib/aarch64/cpu_syspage_memory.c
+779761952 1028 ./src/hardware/startup/lib/aarch64/map_startup_io.c
+399539680 2088 ./src/hardware/startup/lib/aarch64/uefi_init.c
+1379415251 2155 ./src/hardware/startup/lib/aarch64/callout_sendipi_gic_v2.S
+2264425208 33125 ./src/hardware/startup/lib/aarch64/callout_interrupt_gic_v3.S
+4178572109 1588 ./src/hardware/startup/lib/aarch64/hypervisor_enable.S
+445109814 980 ./src/hardware/startup/lib/aarch64/cpuid_v8_fm.c
+3915149935 33955 ./src/hardware/startup/lib/aarch64/gic_v3_its.c
+1061183959 1159 ./src/hardware/startup/lib/aarch64/cpuid_a75.c
+234473201 1021 ./src/hardware/startup/lib/aarch64/init_qtime.c
+1355144110 32 ./src/hardware/startup/lib/aarch64/Makefile
+3843385179 59334 ./src/hardware/startup/lib/aarch64/gic_v3.c
+3339753241 1905 ./src/hardware/startup/lib/aarch64/callout_debug_dummy.S
+134540270 1535 ./src/hardware/startup/lib/aarch64/gic_v3_dcache_flush_for_its.c
+1785568510 1729 ./src/hardware/startup/lib/aarch64/aarch64_cache_flush.S
+3288821544 1370 ./src/hardware/startup/lib/aarch64/aarch64_hwi_add_ppi.c
+2669231884 1357 ./src/hardware/startup/lib/aarch64/_start.S
+3733605173 981 ./src/hardware/startup/lib/aarch64/cpuid_a55.c
+3205765858 1081 ./src/hardware/startup/lib/aarch64/init_hwinfo.c
+3760231170 3344 ./src/hardware/startup/lib/aarch64/callout_debug_tegra.S
+2686212097 3884 ./src/hardware/startup/lib/aarch64/callout_debug_linflexd.S
+3114210564 2201 ./src/hardware/startup/lib/aarch64/callout_smp_spin.S
+2976495756 4816 ./src/hardware/startup/lib/aarch64/callout_debug_8250_32b.S
+572769012 1376 ./src/hardware/startup/lib/aarch64/board_sysctl.c
+112603831 1474 ./src/hardware/startup/lib/aarch64/vbar_default.S
+2194598857 2470 ./src/hardware/startup/lib/aarch64/callout_cache_armv8.S
+653283685 1055 ./src/hardware/startup/lib/aarch64/map_startup_mem.c
+2862953494 1083 ./src/hardware/startup/lib/aarch64/aarch64_cpuspeed.c
+1677254109 2916 ./src/hardware/startup/lib/aarch64/cpu_common_options.c
+3429373965 5515 ./src/hardware/startup/lib/aarch64/callout_interrupt_gic_v2.S
+3204188922 4187 ./src/hardware/startup/lib/aarch64/hypervisor.c
+3130816884 1119 ./src/hardware/startup/lib/aarch64/rtc_time.c
+1405003281 4405 ./src/hardware/startup/lib/aarch64/cpu_print_sysp.ci
+3775258238 1070 ./src/hardware/startup/lib/aarch64/crash_done.c
+4150833655 980 ./src/hardware/startup/lib/aarch64/cpuid_a53.c
+1451233731 1866 ./src/hardware/startup/lib/aarch64/cpu_startup.c
+1895379879 1639 ./src/hardware/startup/lib/pci_write_cfg8.c
+2297142963 1601 ./src/hardware/startup/lib/hwitag_add_regname.c
+2513919039 1200 ./src/hardware/startup/lib/tweak_cmdline.c
+4009252565 2105 ./src/hardware/startup/lib/fdt_get_int.c
+302938137 1609 ./src/hardware/startup/lib/hwitag_add_irqrange.c
+1078811813 1250 ./src/hardware/startup/lib/debug.c
+2896126298 1503 ./src/hardware/startup/lib/pci_read_cfg8.c
+1265982621 2762 ./src/hardware/startup/lib/common.mk
+1133867528 2521 ./src/hardware/startup/lib/fdt_init_bootopt.c
+4110881801 1033 ./src/hardware/startup/lib/as_off2info.c
+345722037 1498 ./src/hardware/startup/lib/memfuncs.c
+1381579637 1256 ./src/hardware/startup/lib/common_arm/psci_smp.c
+3836343879 1172 ./src/hardware/startup/lib/common_arm/cpu_tweak_cmdline.c
+3585800892 2158 ./src/hardware/startup/lib/common_arm/fdt_qtime.c
+1961215341 1457 ./src/hardware/startup/lib/common_arm/gicv_asinfo.c
+4292884072 778 ./src/hardware/startup/lib/common_arm/psci_cpu_id.c
+1678209057 1773 ./src/hardware/startup/lib/common_arm/spin_smp.c
+416819215 2329 ./src/hardware/startup/lib/common_arm/hw_serscif.c
+3455431200 1069 ./src/hardware/startup/lib/common_arm/spin_bootstrap_id.c
+4222941287 2747 ./src/hardware/startup/lib/common_arm/hw_serpl011.c
+4108005660 1844 ./src/hardware/startup/lib/common_arm/fdt_psci_configure.c
+4148533049 2501 ./src/hardware/startup/lib/add_cache.c
+1649484848 1605 ./src/hardware/startup/lib/hwidev_add_dma.c
+2475210304 2543 ./src/hardware/startup/lib/load_ifs.c
+3726635334 1097 ./src/hardware/startup/lib/hw_rtc_none.c
+1309574163 4488 ./src/hardware/startup/lib/acpi.c
+507102391 1790 ./src/hardware/startup/lib/public/hw/mc146818.h
+3565831342 3707 ./src/hardware/startup/lib/public/hw/pcal6524.h
+925821029 1143 ./src/hardware/startup/lib/public/hw/iplversion.h
+3457385230 19230 ./src/hardware/startup/lib/public/hw/acpi.h
+2443843520 18025 ./src/hardware/startup/lib/public/hw/uefi.h
+2522625688 3330 ./src/hardware/startup/lib/public/hw/adp5585.h
+3058586150 6164 ./src/hardware/startup/lib/public/hw/uefi_smbios.h
+3612958404 2713 ./src/hardware/startup/lib/public/hw/pca9450.h
+2978028035 21397 ./src/hardware/startup/lib/public/hw/hwinfo_private.h
+2292335503 8892 ./src/hardware/startup/lib/public/aarch64/cpu_startup.h
+1636484160 4992 ./src/hardware/startup/lib/public/aarch64/gic_its.h
+699652186 18761 ./src/hardware/startup/lib/public/aarch64/gic.h
+1457724610 13737 ./src/hardware/startup/lib/public/aarch64/gic_v3.h
+1257862056 3068 ./src/hardware/startup/lib/public/aarch64/gic_v2.h
+3324660220 5555 ./src/hardware/startup/lib/public/aarch64/psci.h
+2258370255 6894 ./src/hardware/startup/lib/public/aarch64/cci400.h
+665592178 2997 ./src/hardware/startup/lib/public/aarch64/aarch64_tlb.h
+2479320129 3610 ./src/hardware/startup/lib/public/aarch64/callout.ah
+203131225 1022 ./src/hardware/startup/lib/public/aarch64/intr.h
+417828369 1012 ./src/hardware/startup/lib/public/aarch64/priv.h
+133357814 26710 ./src/hardware/startup/lib/public/startup.h
+1579143879 3038 ./src/hardware/startup/lib/public/arm/gic.h
+1880005329 5052 ./src/hardware/startup/lib/public/arm/mpcore.h
+1170885971 4966 ./src/hardware/startup/lib/public/arm/psci.h
+3241899211 2360 ./src/hardware/startup/lib/public/arm/armboth_startup.h
+291923643 3780 ./src/hardware/startup/lib/public/arm/inout.h
+2775425086 13136 ./src/hardware/startup/lib/public/sys/hwinfo.h
+2429401380 3466 ./src/hardware/startup/lib/public/sys/restore_ifs.h
+67389493 13914 ./src/hardware/startup/lib/public/sys/startup.h
+1558012855 2439 ./src/hardware/startup/lib/public/sys/libfdt_private.h
+1390462278 5573 ./src/hardware/startup/lib/_main.c
+2767319330 1703 ./src/hardware/startup/lib/gmtime.c
+2631323809 1412 ./src/hardware/startup/lib/timer_tick2ns.c
+3424457125 3112 ./src/hardware/startup/lib/hw_rtc_rtc72423.c
+2472089111 3655 ./src/hardware/startup/lib/hw_ser8250.c
+1427243970 2035 ./src/hardware/startup/lib/jtag.c
+1846423562 1874 ./src/hardware/startup/lib/as_find_containing.c
+860412907 2029 ./src/hardware/startup/lib/strtoul.c
+2409709439 1325 ./src/hardware/startup/lib/callout_io_map_indirect.c
+2553793548 1074 ./src/hardware/startup/lib/timer_ns2tick.c
+418487286 1662 ./src/hardware/startup/lib/hwitag_set_busattr.c
+849553015 1759 ./src/hardware/startup/lib/invert_timer_freq.c
+4129550738 1471 ./src/hardware/startup/lib/getsize.c
+2090819139 2317 ./src/hardware/startup/lib/as_find.c
+2547454493 1514 ./src/hardware/startup/lib/hwitag_add_irq.c
+437554884 1051 ./src/hardware/startup/lib/fdt_vars.c
+3435865524 2090 ./src/hardware/startup/lib/fdt_get_u64.c
+4167221715 3723 ./src/hardware/startup/lib/add_interrupt.c
+1149657400 1306 ./src/hardware/startup/lib/memmove.c
+2366682174 2281 ./src/hardware/startup/lib/hw_rtc_m48t37.c
+2719591516 1459 ./src/hardware/startup/lib/hwitag_set_errata.c
+2882637283 1023 ./src/hardware/startup/lib/hw_serdummy.c
+3006557864 2038 ./src/hardware/startup/lib/hwidev_add_enet.c
+2965584407 1747 ./src/hardware/startup/lib/fdt_get_reg_int.c
+1926984332 1496 ./src/hardware/startup/lib/hwibus_add_usb.c
+3572477511 1578 ./src/hardware/startup/lib/hwitag_set_dma.c
+2052157382 12779 ./src/hardware/startup/lib/ram.c
+3997023347 2159 ./src/hardware/startup/lib/fdt_get_reg32.c
+3621050964 1830 ./src/hardware/startup/lib/acpi_spcr_parse.c
+4244668720 1882 ./src/hardware/startup/lib/hwidev_add.c
+3876957010 1200 ./src/hardware/startup/lib/print_sysp.h
+286330696 52 ./src/hardware/startup/lib/.srcinfo
+3340646836 1353 ./src/hardware/startup/lib/interrupt_valid.c
+964282156 2790 ./src/hardware/startup/lib/hwi_alloc.c
+3187602569 1878 ./src/hardware/startup/lib/calc_time_t.c
+1794678194 2875 ./src/hardware/startup/lib/hw_rtc_mc146818.c
+95963711 1056 ./src/hardware/startup/lib/hwi_add_nicaddr.c
+1617733805 1784 ./src/hardware/startup/lib/fdt_node_offset_by_nodename.c
+1104905061 1108 ./src/hardware/startup/lib/board_find_acpi_rsdp.c
+4111815854 2657 ./src/hardware/startup/lib/fdt_get_intr.c
+3578932083 2296 ./src/hardware/startup/lib/fdt_find_node.c
+773586320 2322 ./src/hardware/startup/lib/hw_rtc_m48t5x.c
+2924604953 1977 ./src/hardware/startup/lib/elf.c
+130053414 1916 ./src/hardware/startup/lib/uncompress.c
+994185927 1696 ./src/hardware/startup/lib/hwidev_add_rtc.c
+840951497 2379 ./src/hardware/startup/lib/memcpy.c
+3719217974 1368 ./src/hardware/startup/lib/startnext.c
+3410877077 1957 ./src/hardware/startup/lib/getopt.c
+1145456827 1664 ./src/hardware/startup/lib/hwidev_add_timer.c
+2909163170 2089 ./src/hardware/startup/lib/fdt_get_u32.c
+2421554480 3749 ./src/hardware/startup/lib/as_add_containing.c
+3824560013 13372 ./src/hardware/startup/lib/print_sysp.c
+1935565216 2623 ./src/hardware/startup/lib/efi_tweak_cmdline.c
+1834424921 1550 ./src/hardware/startup/lib/hwitag_add_nicphyaddr.c
+978307699 1166 ./src/hardware/startup/lib/fdt_num_cpu.c
+1799901574 1246 ./src/hardware/startup/lib/fdt_init.c
+1680757452 3253 ./src/hardware/startup/lib/kprintf.c
+566971394 1044 ./src/hardware/startup/lib/hwi_find_as.c
+2392384443 1698 ./src/hardware/startup/lib/hwitag_add_busattr.c
+1174453810 2422 ./src/hardware/startup/lib/hw_serlinflex.c
+117372267 1727 ./src/hardware/startup/lib/hwibus_add_spi.c
+1318057383 3610 ./src/hardware/startup/lib/uefi_io.c
+219382369 1022 ./src/hardware/startup/lib/as_info2off.c
+1875376052 1315 ./src/hardware/startup/lib/uncompress_lzo.c
+565940646 28 ./src/hardware/startup/lib/Makefile
+2069453561 1850 ./src/hardware/startup/lib/hwibus_add.c
+2688793128 2718 ./src/hardware/startup/lib/chip_access.c
+3452931002 1236 ./src/hardware/startup/lib/hwi_add_nanospin.c
+1381474780 973 ./src/hardware/startup/lib/dummy_print_char.c
+1591148150 3298 ./src/hardware/startup/lib/hw_rtc_ds1743.c
+3312590598 9443 ./src/hardware/startup/lib/init_system_private.c
+3863883597 2665 ./src/hardware/startup/lib/strings.c
+1097655108 1039 ./src/hardware/startup/lib/__main.c
+2448396071 1050 ./src/hardware/startup/lib/bcd2bin.c
+1736376533 1581 ./src/hardware/startup/lib/hwi_add_synonym.c
+759462569 5489 ./src/hardware/startup/lib/init_raminfo_efi.c
+2792767565 6030 ./src/hardware/startup/lib/callouts.c
+2900496658 2311 ./src/hardware/startup/lib/hwitag_set_avail_ivec.c
+1297818953 1711 ./src/hardware/startup/lib/hwibus_add_pci.c
+998685315 1116 ./src/hardware/startup/lib/as_set_priority.c
+2942425547 3927 ./src/hardware/startup/lib/hw_ser8250_32b.c
+3394258635 2980 ./src/hardware/startup/lib/asmoff.h
+679160342 1731 ./src/hardware/startup/lib/hwitag_add_nicaddr.c
+2187916782 4240 ./src/hardware/startup/lib/fdt_get_reg64_cells.c
+3557540873 1257 ./src/hardware/startup/lib/uncompress_ucl.c
+1436887486 1968 ./src/hardware/startup/lib/fdt_get_cpu_freq.c
+1967634666 4587 ./src/hardware/startup/lib/elf64.c
+1213991743 4713 ./src/hardware/startup/lib/elf32.c
+3803808112 1328 ./src/hardware/startup/lib/hwi_add_rtc.c
+3750873887 2713 ./src/hardware/startup/lib/hypervisor_setup.c
+3604119289 1695 ./src/hardware/startup/lib/hwitag_set_phyaddr.c
+2421928832 1216 ./src/hardware/startup/lib/board_cpuconfig1.c
+2215842283 1243 ./src/hardware/startup/lib/init_cacheattr.c
+4192995542 6693 ./src/hardware/startup/lib/syspage_memory.c
+987897048 16283 ./src/hardware/startup/lib/restore_ifs.c
+2467445882 2123 ./src/hardware/startup/lib/fdt_get_reg_addr.c
+2954023274 1050 ./src/hardware/startup/lib/hwi_add_inputclk.c
+3598557883 1872 ./src/hardware/startup/lib/fdt_get_reg64.c
+1102519675 3063 ./src/hardware/startup/lib/hwitag_add_common.c
+3105551352 1811 ./src/hardware/startup/lib/hwitag_set_ivec.c
+3441082354 1063 ./src/hardware/startup/lib/as_add.c
+257989559 2035 ./src/hardware/startup/lib/init_raminfo_fdt.c
+3408793314 2357 ./src/hardware/startup/lib/cpu_cluster_add.c
+761991769 2871 ./src/hardware/startup/lib/init_smp.c
+1004561460 1130 ./src/hardware/startup/lib/calc_cksum.c
+3794048393 976 ./src/hardware/startup/lib/crash_done.c
+1313680730 2205 ./src/hardware/startup/lib/hw_rtc_ds15x1.c
+482179400 1109 ./src/hardware/startup/lib/hwi_default.c
+2058985273 1587 ./src/hardware/support/wdtkick/wdtkick.use
+716219665 23025 ./src/hardware/support/wdtkick/main.c
+372596184 127 ./src/hardware/support/wdtkick/aarch64/Makefile
+3896112805 24 ./src/hardware/support/wdtkick/aarch64/le/Makefile
+2242694999 503 ./src/hardware/support/wdtkick/common.mk
+3689217311 67 ./src/hardware/support/wdtkick/pinfo.mk
+565940646 28 ./src/hardware/support/wdtkick/Makefile
+1115073814 126 ./src/hardware/support/bcm2711/gpio/aarch64/Makefile
+3896112805 24 ./src/hardware/support/bcm2711/gpio/aarch64/le/Makefile
+2527941546 2178 ./src/hardware/support/bcm2711/gpio/gpio-bcm2711.use
+2883139574 529 ./src/hardware/support/bcm2711/gpio/common.mk
+565940646 28 ./src/hardware/support/bcm2711/gpio/Makefile
+2338478389 20815 ./src/hardware/support/bcm2711/gpio/gpio.c
+372596184 127 ./src/hardware/support/bcm2711/mbox/aarch64/Makefile
+3896112805 24 ./src/hardware/support/bcm2711/mbox/aarch64/le/Makefile
+3879393039 529 ./src/hardware/support/bcm2711/mbox/common.mk
+320914644 11300 ./src/hardware/support/bcm2711/mbox/mbox.c
+565940646 28 ./src/hardware/support/bcm2711/mbox/Makefile
+1264792460 836 ./src/hardware/support/bcm2711/mbox/mbox-bcm2711.use
+3299543874 19 ./src/hardware/support/bcm2711/Makefile
+3649923259 32 ./src/hardware/support/Makefile
+2221984677 2132 ./src/hardware/devc/common.mk
+620653094 2006 ./src/hardware/devc/devc.use
+2861564346 2738 ./src/hardware/devc/serminiuart/mini_uart.h
+4046080939 4012 ./src/hardware/devc/serminiuart/intr.c
+1399713845 1688 ./src/hardware/devc/serminiuart/main.c
+1355144110 32 ./src/hardware/devc/serminiuart/aarch64/Makefile
+2415649356 27 ./src/hardware/devc/serminiuart/aarch64/le/Makefile
+252718924 6766 ./src/hardware/devc/serminiuart/tto.c
+2062187683 89 ./src/hardware/devc/serminiuart/pinfo.mk
+565940646 28 ./src/hardware/devc/serminiuart/Makefile
+941186129 3951 ./src/hardware/devc/serminiuart/init.c
+1977634570 1804 ./src/hardware/devc/serminiuart/proto.h
+3787259489 62 ./src/hardware/devc/serminiuart/serminiuart.use
+2943572674 2619 ./src/hardware/devc/serminiuart/options.c
+1481345493 2168 ./src/hardware/devc/serminiuart/externs.h
+2112349775 1132 ./src/hardware/devc/serminiuart/externs.c
+1509057807 29 ./src/hardware/devc/Makefile
+2080367687 10127 ./src/hardware/devc/serpl011/intr.c
+100591885 1381 ./src/hardware/devc/serpl011/main.c
+1355144110 32 ./src/hardware/devc/serpl011/aarch64/Makefile
+2415649356 27 ./src/hardware/devc/serpl011/aarch64/le/Makefile
+1892655464 305 ./src/hardware/devc/serpl011/serpl011.use
+3885543487 1321 ./src/hardware/devc/serpl011/variant.h
+2516929097 12128 ./src/hardware/devc/serpl011/tto.c
+2682246210 77 ./src/hardware/devc/serpl011/pinfo.mk
+565940646 28 ./src/hardware/devc/serpl011/Makefile
+1547273156 9727 ./src/hardware/devc/serpl011/init.c
+4257162244 1598 ./src/hardware/devc/serpl011/proto.h
+805685287 3435 ./src/hardware/devc/serpl011/options.c
+933156033 2984 ./src/hardware/devc/serpl011/externs.h
+311749951 1134 ./src/hardware/devc/serpl011/externs.c
+509375503 600 ./src/hardware/i2c/common.mk
+1606158728 1338 ./src/hardware/i2c/bcm2711/version.c
+2799222305 2310 ./src/hardware/i2c/bcm2711/bus_speed.c
+1211719062 1989 ./src/hardware/i2c/bcm2711/lib.c
+1804018481 1346 ./src/hardware/i2c/bcm2711/fini.c
+1231216344 34 ./src/hardware/i2c/bcm2711/aarch64/Makefile
+2768768086 28 ./src/hardware/i2c/bcm2711/aarch64/le/Makefile
+743985106 2680 ./src/hardware/i2c/bcm2711/recv.c
+3048093092 2572 ./src/hardware/i2c/bcm2711/send.c
+3290199945 1391 ./src/hardware/i2c/bcm2711/info.c
+597978126 1424 ./src/hardware/i2c/bcm2711/slave_addr.c
+1089230884 56 ./src/hardware/i2c/bcm2711/pinfo.mk
+3002801104 30 ./src/hardware/i2c/bcm2711/Makefile
+3572732535 6214 ./src/hardware/i2c/bcm2711/init.c
+2414980158 537 ./src/hardware/i2c/bcm2711/Usemsg
+534486595 5275 ./src/hardware/i2c/bcm2711/proto.h
+3572344756 4016 ./src/hardware/i2c/bcm2711/options.c
+1923311025 3342 ./src/hardware/i2c/bcm2711/wait.c
+3592104529 30 ./src/hardware/i2c/Makefile
+294821459 52 ./src/hardware/Makefile
+1764603626 2813 ./src/hardware/devb/common.mk
+2720432213 5312 ./src/hardware/devb/sdmmc/devb-sdmmc.use
+1285561704 1595 ./src/hardware/devb/sdmmc/aarch64/bcm2711.le/sim_bs.c
+3488143997 3871 ./src/hardware/devb/sdmmc/aarch64/bcm2711.le/bs.c
+157013790 417 ./src/hardware/devb/sdmmc/aarch64/bcm2711.le/bcm2711.use
+1362637790 52 ./src/hardware/devb/sdmmc/aarch64/bcm2711.le/Makefile
+823974647 1307 ./src/hardware/devb/sdmmc/aarch64/bcm2711.le/sim_bs.h
+535411437 1359 ./src/hardware/devb/sdmmc/aarch64/bcm2711.le/bs.h
+127972479 140 ./src/hardware/devb/sdmmc/aarch64/Makefile
+2529708659 17120 ./src/hardware/devb/sdmmc/public/hw/dcmd_sim_sdmmc.h
+3355484224 11350 ./src/hardware/devb/sdmmc/public/hw/dcmd_sim_mmcsd.h
+1649492157 16268 ./src/hardware/devb/sdmmc/sim_assd.c
+2138136990 67596 ./src/hardware/devb/sdmmc/sdiodi/base.c
+1155423217 36930 ./src/hardware/devb/sdmmc/sdiodi/sd.c
+1585854810 13480 ./src/hardware/devb/sdmmc/sdiodi/pci.c
+1461755374 47223 ./src/hardware/devb/sdmmc/sdiodi/mmc.c
+2075794128 14465 ./src/hardware/devb/sdmmc/sdiodi/hc/sdhci.h
+1981656338 4103 ./src/hardware/devb/sdmmc/sdiodi/hc/sdhci_pci.c
+116771841 35318 ./src/hardware/devb/sdmmc/sdiodi/hc/sdhci.c
+565242695 10384 ./src/hardware/devb/sdmmc/sdiodi/hc/dwmshc.h
+730835270 4883 ./src/hardware/devb/sdmmc/sdiodi/hc/imx8_hc.h
+3144723706 47385 ./src/hardware/devb/sdmmc/sdiodi/hc/sdhci_dwc.c
+3497664035 34227 ./src/hardware/devb/sdmmc/sdiodi/hc/dwmshc.c
+3748762220 1606 ./src/hardware/devb/sdmmc/sdiodi/hc/sdhci_pci.h
+1417714063 68852 ./src/hardware/devb/sdmmc/sdiodi/hc/imx8_hc.c
+3044227798 17410 ./src/hardware/devb/sdmmc/sdiodi/hc/ls10xx.h
+1156977355 42465 ./src/hardware/devb/sdmmc/sdiodi/hc/ls10xx.c
+2135359242 5024 ./src/hardware/devb/sdmmc/sdiodi/hc/sdhci_dwc.h
+2301517774 17368 ./src/hardware/devb/sdmmc/sdiodi/card.c
+1751232088 17740 ./src/hardware/devb/sdmmc/sdiodi/internal.h
+2731577126 14866 ./src/hardware/devb/sdmmc/sdiodi/include/mmc.h
+2600002935 11623 ./src/hardware/devb/sdmmc/sdiodi/include/sd.h
+3638843882 18457 ./src/hardware/devb/sdmmc/sdiodi/include/sdiodi.h
+1500787301 3937 ./src/hardware/devb/sdmmc/sdiodi/soc.c
+3607069590 259 ./src/hardware/devb/sdmmc/extra.mk
+660093666 112067 ./src/hardware/devb/sdmmc/sim_sdmmc.c
+1407115741 1100 ./src/hardware/devb/sdmmc/pinfo.mk
+565940646 28 ./src/hardware/devb/sdmmc/Makefile
+4261392762 8031 ./src/hardware/devb/sdmmc/sim_sdmmc.h
+1680808891 284969 ./src/hardware/devb/cam.txt
+1890958493 551 ./src/hardware/devb/NDA_DRIVERS
+3119901036 1985 ./src/hardware/devb/dl.c
+1037764311 44 ./src/hardware/devb/Makefile
+1044188879 1700 ./src/hardware/devb/include/dl_disk.h
+2811277482 1581 ./src/hardware/devb/include/dl_sa.h
+2845732993 12319 ./src/hardware/devb/include/xpt.h
+3949502623 17082 ./src/hardware/devb/include/ntocam.h
+1189395774 26052 ./src/hardware/devb/include/cam.h
+464443270 1861 ./src/hardware/devb/include/module.h
+3912544110 66040 ./src/hardware/devb/include/ntoscsi.h
+2939881551 52357 ./src/hardware/devb/include/pci_devices.h
+2945690885 1735 ./src/hardware/devb/include/dl_optical.h
+1074922416 1712 ./src/hardware/devb/include/dl_cdrom.h
+431877853 13384 ./src/hardware/devb/include/sim.h
+3883579873 3023 ./src/hardware/devb/include/dl.h
+719729305 1528 ./src/hardware/devb/include/dl_cam.h
+3919499052 26454 ./src/lib/dma/dma_api.README
+1561678621 884 ./src/lib/dma/common.mk
+114395066 7955 ./src/lib/dma/public/hw/dma.h
+1829597944 2522 ./src/lib/dma/public/hw/edma.h
+2415649356 27 ./src/lib/dma/bcm2711/aarch64/a.le/Makefile
+1355144110 32 ./src/lib/dma/bcm2711/aarch64/Makefile
+1736476369 92 ./src/lib/dma/bcm2711/dma.use
+3050021233 2356 ./src/lib/dma/bcm2711/slogf.c
+2193183466 48661 ./src/lib/dma/bcm2711/bcm2711_dmac.c
+2800581790 4226 ./src/lib/dma/bcm2711/sync.c
+796878427 18372 ./src/lib/dma/bcm2711/bcm2711_dmac.h
+565940646 28 ./src/lib/dma/bcm2711/Makefile
+657349549 38 ./src/lib/dma/Makefile
+3524740290 69 ./src/lib/Makefile

prebuilt/etc/system/config/spi/spi-template.conf

@@ -0,0 +1,134 @@
+################################################################################
+#
+# SPI configuration file
+#
+# This file (or one similar) can be used to configure the SPI bus and devices
+# for SPI driver. It is utilized by specifying it as the parameter to the '-c='
+# command line option.
+#
+# Parameters and their acceptable values are described below. Parameter names
+# are (typically) case invariant.
+#
+# The file is separated into sections. Each section describes the parameters
+# which can be set. Each section is started with a [<section type>] declaration.
+# All parameters after the [<section type>] declaration and upto the next
+# [<section type>] declaration (or end-of-file) will be treated as belonging to
+# the section. The [] character sequence should not be used in any non-commented
+# section elsewhere in the file.
+#
+# For the purpose of documentation, all parameters are included in this file
+# along with their default values. These are left commented out with '##'.
+# Changes should be made by copying the line and changing the value. That way
+# the default value is always known.
+#
+# All text following a '#' until the end-of-line will be treated as a comment.
+#
+# White space is ignored unless otherwise stated.
+#
+# Rules for the config file:
+#
+# 1. Only alphanumeric characters are allowed for section name
+# 2. Only alphanumeric characters and '_' are allowed for parameter name
+# 3. Must have at least one bus section in each config file
+# 4. Must have at least one device section under each bus
+# 5. In each bus section, all the mandatory parameters must be set
+# 6. In each bus section, bus number and bus name can not duplicate
+# 7. In each dev section, all the mandatory parameters must be set
+# 8. Under the same parent bus, dev number and dev name can not duplicate
+# 9. In each dev section, the parent_busno has to be a existing busno in previous bus sections
+#
+#
+# The following known sections are currently defined:
+#
+# [globals]
+# [bus]
+# [dev]
+#
+#############################  S E C T I O N  ##################################
+# Section globals
+# Parameters:
+# verbose: verbosity. Default 2.(Optional)
+#          The "-v" command-line option will override the "verbose" value in the config file.
+[globals]
+
+
+#############################  S E C T I O N  ##################################
+# Section bus
+# Parameters:
+# busno:       bus no. (Mandatory)
+# name:        bus name. (Mandatory)
+# base:        bus base address. (Mandatory)
+# irq:         bus irq num. (Mandatory)
+# input_clock: bus input clock. (Mandatory)
+# bs:          board/controller specific parameters. (Optional)
+# dma_init_opts:    DMA init options. Used by dma_funcs.init. Default NULL. (Optional)
+# dma_attach_opts:  DMA attach options. Used by dma_funcs.channel_attach. Default NULL. (Optional)
+# dma_thld:         DMA threshold. Default 0. (Optional)
+#
+[bus]
+busno=0
+name=spi0
+base=0xfe204000
+irq=150
+input_clock=500000000
+bs=rpanic=48,tpanic=16
+dma_attach_opts=num_cbs=256,range_min=0,range_max=14,typed_mem=sysram&below1G
+dma_thld=4
+
+#############################  S E C T I O N  ##################################
+# Section dev
+# Parameters:
+# parent_busno: parent bus no. (Mandatory)
+# devno:        device no. (Mandatory)
+# name:         device name. (Mandatory)
+# clock_rate:   bus speed for this device. (Mandatory)
+# cpha:         SPI CPHA. 0 or 1. Default 0.(Optional)
+# cpol:         SPI CPOL. 0 or 1. Default 0.(Optional)
+# bit_order:    SPI bit order. MSB or LSB. Case insensitive. Default MSB.(Optional)
+# word_width:   SPI transfer word width in bits. 8, 16 or 32. Default 8.(Optional)
+# idle_insert:  SPI idle insertion support. 0 or 1. Default 0. (Optional)
+#
+# NOTE:
+# Section dev has to be after its parent bus section and has to provide its
+# parent_busno. Otherwise this dev section won't be added to devlist.
+#
+[dev]
+parent_busno=0
+devno=0
+name=dev0
+clock_rate=5000000
+cpha=1
+word_width=32
+idle_insert=1
+
+#############################  S E C T I O N  ##################################
+# Section dev
+#
+[dev]
+parent_busno=0
+devno=1
+name=dev1
+clock_rate=5000000
+cpol=1
+word_width=32
+
+#############################  S E C T I O N  ##################################
+# Section bus
+#
+[bus]
+busno=3
+name=spi3
+base=0xfe204600
+irq=151
+input_clock=500000000
+
+#############################  S E C T I O N  ##################################
+# Section dev
+#
+[dev]
+parent_busno=3
+devno=0
+name=dev0
+clock_rate=5000000
+cpol=1
+

prebuilt/usr/include/aarch64/asmoff.def

@@ -0,0 +1,37 @@
+#  This file was produced by:
+#     mkasmoff -fgas asmoff.o asmoff.def
+#     (machine type is 183)
+# 
+.set QT_TIMER_PERIOD, 0x00000020
+.set MS_SYNC, 0x00000002
+.set MS_ASYNC, 0x00000001
+.set MS_INVALIDATE, 0x00000004
+.set MS_INVALIDATE_ICACHE, 0x01000000
+.set CA_LINE_SIZE, 0x00000004
+.set CA_NUM_LINES, 0x00000008
+.set REG_LS, 0x00000005
+.set LSR_RXRDY, 0x00000001
+.set LSR_TXRDY, 0x00000020
+.set LSR_BI, 0x00000010
+.set DDI_BASE, 0x00000000
+.set DDI_SHIFT, 0x00000008
+.set SIZEOF_DDI, 0x00000010
+.set INTR_CONFIG_FLAG_IPI, 0x00000004
+.set INTR_CONFIG_FLAG_DISALLOWED, 0x00000002
+.set INTR_CONFIG_FLAG_PREATTACH, 0x00000001
+.set INTR_CONFIG_FLAG_SYS, 0x00000008
+.set SYSPAGE_SYSTEM_PRIVATE, 0x00000008
+.set SP_PRIVATE_FLAGS, 0x00000004
+.set SYSTEM_PRIVATE_FLAG_ABNORMAL_REBOOT, 0x00000001
+.set SYSPAGE_NUM_CPU, 0x00000006
+.set SYSPAGE_SMP, 0x00000024
+.set SMP_START_ADDR, 0x00000010
+.set SMP_PENDING, 0x00000000
+.set SIGBUS, 0x0000000a
+.set BUS_ADRERR, 0x00000002
+.set BUS_OBJERR, 0x00000003
+.set FLTACCESS, 0x00000005
+.set FLTBOUNDS, 0x00000006
+.set DEBUG_WATCHDOG_STOP, 0x00000000
+.set DEBUG_WATCHDOG_CONTINUE, 0x00000001
+.set DEBUG_WATCHDOG_FEED, 0x00000002

prebuilt/usr/include/sys/syspage.h

@@ -0,0 +1,543 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2009, QNX Software Systems. All Rights Reserved.
+ *
+ * You must obtain a written license from and pay applicable license fees to QNX
+ * Software Systems before you may reproduce, modify or distribute this software,
+ * or any work that includes all or part of this software.   Free development
+ * licenses are available for evaluation and non-commercial purposes.  For more
+ * information visit http://licensing.qnx.com or email licensing@qnx.com.
+ *
+ * This file may contain contributions from others.  Please review this entire
+ * file for other proprietary rights or license notices, as well as the QNX
+ * Development Suite License Guide at http://licensing.qnx.com/license-guide/
+ * for other information.
+ * $
+ */
+
+#ifndef __SYSPAGE_H_INCLUDED
+#define __SYSPAGE_H_INCLUDED
+
+#ifndef __PLATFORM_H_INCLUDED
+#include <sys/platform.h>
+#endif
+
+#define SYSPAGE_VERSION_MAJOR   2
+#define SYSPAGE_VERSION_MINOR   0
+
+__BEGIN_DECLS
+
+#if defined(__CLOCKADJUST)
+struct _clockadjust __CLOCKADJUST;
+#undef __CLOCKADJUST
+#endif
+
+struct _process_local_storage;
+struct syspage_entry;
+
+extern struct syspage_entry				*_syspage_ptr;
+
+typedef struct {
+	_Uint16t		entry_off;
+	_Uint16t		entry_size;
+} syspage_entry_info;
+
+typedef struct {
+	_Uint16t		entry_off;
+	_Uint16t		entry_size;
+	_Uint16t		element_size;
+} syspage_array_info;
+
+/*
+ * Include CPU specific definition for network queries.
+ */
+#if	!defined(SYSPAGE_TARGET_ALL)				\
+	&& !defined(SYSPAGE_TARGET_X86_64)			\
+	&& !defined(SYSPAGE_TARGET_AARCH64)
+#if defined(__X86_64__)
+#define SYSPAGE_TARGET_X86_64
+#elif defined(__aarch64__)
+#define SYSPAGE_TARGET_AARCH64
+#else
+#error not configured for system
+#endif
+#endif
+
+#if defined(SYSPAGE_TARGET_ALL) || defined(SYSPAGE_TARGET_X86_64)
+#include _NTO_HDR_(x86_64/syspage.h)
+#endif
+#if defined(SYSPAGE_TARGET_ALL) || defined(SYSPAGE_TARGET_AARCH64)
+#include _NTO_HDR_(aarch64/syspage.h)
+#endif
+
+struct cpupage_entry {
+	_Uint32t								cpu;
+	_Uint32t								state;
+	union {
+#if defined(SYSPAGE_TARGET_ALL) || defined(SYSPAGE_TARGET_AARCH64)
+		struct aarch64_cpupage_entry		aarch64;
+#endif
+		struct {
+			_Uint32t	dummy[8];
+		}									dummy;
+	} un;
+	struct _process_local_storage			*pls;
+
+	_Uint32t								spare[8];
+};
+
+enum {
+	CPUPAGE_ADDR = -1,	/* R */
+	CPUPAGE_TLS = 0,	/* R */
+	CPUPAGE_PLS,		/* RW */
+	CPUPAGE_SYSPAGE,	/* R */
+	CPUPAGE_CPU,		/* R */
+	CPUPAGE_STATE,		/* R */
+	CPUPAGE_MAX
+};
+
+/*
+ *  Architecture independent system page definitions
+ */
+
+/*
+ *	System page types
+ */
+enum {
+    /* technically not needed */
+    SYSPAGE_64BIT = 0x100,
+    /* syspage now has a version field */
+    SYSPAGE_VERSIONED = 0x1000,
+    SYSPAGE_X86_64 = (_Uint16t)SYSPAGE_VERSIONED | (_Uint16t)SYSPAGE_64BIT,
+    SYSPAGE_AARCH64,
+};
+
+#define QTIME_FLAG_CHECK_STABLE			0x00000002u
+#define QTIME_FLAG_TICKLESS				0x00000004u
+#define QTIME_FLAG_GLOBAL_CLOCKCYCLES	0x00000008u /* ClockCycles() is synchronized between all processors */
+
+struct qtime_entry {
+    /**
+     * Cycles-per-second, for ClockCycles()
+     */
+    _Uint64t                    cycles_per_sec;
+
+    /**
+     * Time-of-day adjustment for CLOCK_REALTIME/CLOCK_SOFTTIME and their timers.
+     */
+    _Uint64t volatile           nsec_tod_adjust;
+
+    /**
+     * Number of nanoseconds-per-tick: the tick period.
+     */
+    _Uint32t                    nsec_inc;
+
+    /**
+     * UTC seconds when machine booted.
+     */
+    _Uint32t                    boot_time;
+
+    /**
+     * Incremental CLOCK_REALTIME adjustment in progress (ClockAdjust()).
+     */
+    struct _clockadjust         adjust;
+
+    /**
+     * times 10^timer_scale
+     */
+    _Uint32t                    timer_period;
+
+    /**
+     * Exponent for timer_period.
+     */
+    _Int32t                     timer_scale;
+
+    /**
+     * Interrupt number for CPU0.
+     */
+    _Int32t                     intr;
+
+    /**
+     * 1970.
+     */
+    _Uint32t                    epoch;
+
+    /**
+     * QTIME_FLAG_* flags.
+     */
+    _Uint32t                    flags;
+
+    /**
+     * Round-robin interval in ticks.
+     */
+    _Uint32t                    rr_interval_mul;
+
+    /**
+     * The max absolute value that can be written in the the hardware timer's
+     * comparator. For correct operation, this value must never be reached
+     * during the system's lifetime.
+     */
+    _Uint64t                    timer_load_max;
+
+    /**
+     * Boot time in clock cycles. This is the epoch for all calculations done
+     * on time in clock cycles.
+     */
+    _Uint64t                    boot_cc;
+
+    /**
+     * Exact tick period used by the kernel, in clock cycles.
+     *
+     * The kernel computes the closest tick period value that can be
+     * represented in clock cycles from the tick frequency passed to procnto.
+     * Depending on the frequency requested and the hardware CPS, it is
+     * possible that corresponding value in nanoseconds cannot be represented
+     * as an integer number of nanoseconds. When that is the case, 'nsec_inc'
+     * is only an approximation in nanoseconds of tick_period_cc.
+     * This can happen if the kernel is configured with a weird tick frequency
+     * (e.g. the system configuration passing -C 347 to procnto) that is not a
+     * factor of a sensible CPS, or if the CPS itself is weird (e.g.
+     * startup-x86 calibration finding the CPS to be 1.804807028 GHz).
+     */
+    _Uint64t                    tick_period_cc;
+
+    _Uint64t                    spare[3];
+};
+
+struct intrspin;
+
+struct debug_callout {
+	void	(*display_char)(struct syspage_entry *__syspage, char __char);
+	int		(*poll_key)(struct syspage_entry *__syspage);
+	int		(*break_detect)(struct syspage_entry *__syspage);
+	void	*spare;
+};
+
+typedef enum {
+	DEBUG_WATCHDOG_STOP = 0,
+	DEBUG_WATCHDOG_CONTINUE,
+	DEBUG_WATCHDOG_FEED
+} debug_watchdog_cmd;
+
+struct callout_entry {
+	void					(*reboot)(struct syspage_entry *__syspage, int __flags);
+	struct debug_callout	debug[2];
+	void					(*debug_watchdog)(struct syspage_entry *__syspage, debug_watchdog_cmd __cmd);
+
+	_Uint64t 				(*custom)(struct syspage_entry *__syspage, _Uint32t __type_id, _Uint64t *__regs);
+
+	_Uint64t	spare[2];
+};
+
+#define AS_NULL_OFF			((_Uint16t)-1)
+
+#define AS_ATTR_KIDS		0x0010u
+#define AS_ATTR_CONTINUED	0x0020u
+
+#define AS_PRIORITY_DEFAULT	100
+
+struct asinfo_entry {
+	_Uint64t			start;
+	_Uint64t			end;
+	_Uint16t			owner;
+	_Uint16t			name;
+	_Uint16t			attr;
+	_Uint16t			priority;
+};
+
+struct hwinfo_entry {
+	__FLEXARY(_Uint32t, data); /* data[] variable sized, see <hw/sysinfo.h> */
+};
+
+/**
+ * Reboot in case of an abnormal shutdown.
+ * This flag is set by passing the -A option to startup.
+ * While not the default behaviour of startup, it should be
+ * used for safe systems.
+ */
+#define SYSTEM_PRIVATE_FLAG_ABNORMAL_REBOOT	0x00000001u
+#define SYSTEM_PRIVATE_FLAG_TRACE_ACTIVE	0x00000004u
+#define SYSTEM_PRIVATE_FLAG_ETB_RUNNING		0x00000008u
+
+struct system_private_entry {
+	_Uint32t						cpupage_spacing;
+	_Uint32t						private_flags;
+	_Uint32t						pagesize;
+	_Uint32t						num_ready;
+    _Uint32t                        traced_classes;
+	_Uint32t						spare;
+	_Paddr64t						kdump_info;
+	struct cpupage_entry			*user_cpupageptr;
+	struct syspage_entry			*user_syspageptr;
+	struct cpupage_entry			*kern_cpupageptr;
+	struct syspage_entry			*kern_syspageptr;
+	struct kdebug_info				*kdebug_info;
+	struct kdebug_callback			*kdebug_call;
+    _Uint64t						entropy[2];
+};
+
+/*
+ * System independent CPU flags (system dependent grow from bottom up)
+ */
+#define CPU_FLAG_FPU		(1U <<  31)  /* CPU has floating point support */
+#define CPU_FLAG_MMU		(1U <<  30)  /* MMU is active */
+
+struct cpuinfo_entry {
+	_Uint32t		cpu;
+	_Uint32t		speed;
+	_Uint64t		flags;
+	_Uint64t		smp_hwcoreid;
+	_Uint32t		spare;
+	_Uint16t		name;
+	_Uint8t			ins_cache;
+	_Uint8t			data_cache;
+};
+
+#define CACHE_LIST_END		0xffU	/* terminate a cache hierarchy list */
+
+/*
+ * Cache flags
+ */
+#define CACHE_FLAG_INSTR	0x0001U	/* cache holds instructions */
+#define CACHE_FLAG_DATA		0x0002U	/* cache holds data */
+#define CACHE_FLAG_UNIFIED	0x0003U	/* cache holds both ins & data */
+#define CACHE_FLAG_SHARED	0x0004U	/* cache is shared between multiple  */
+									/* processors in an SMP system */
+#define CACHE_FLAG_SNOOPED	0x0008U	/* cache implements a bus snooping */
+									/* protocol */
+#define CACHE_FLAG_VIRT_TAG	0x0010U	/* cache is virtually tagged */
+#define CACHE_FLAG_VIRTUAL	0x0010U	/* backwards compatability flag for above */
+#define CACHE_FLAG_WRITEBACK 0x0020U/* cache does writeback, not writethru */
+#define CACHE_FLAG_CTRL_PHYS 0x0040U/* control function takes 32-bit paddrs */
+#define CACHE_FLAG_SUBSET	0x0080U	/* this cache obeys the 'subset' property */
+#define CACHE_FLAG_NONCOHERENT 0x0100U /* cache is non-coherent on SMP */
+#define CACHE_FLAG_NONISA	0x0200U /* cache doesn't obey ISA cache instr */
+#define CACHE_FLAG_NOBROADCAST 0x0400U /* cache ops aren't broadcast on bus for SMP */
+#define CACHE_FLAG_VIRT_IDX	0x0800U	/* cache is virtually indexed */
+#define CACHE_FLAG_CTRL_PHYS64 0x1000U /* control function takes 64-bit paddrs */
+
+struct cacheattr_entry;
+typedef unsigned __cache_rtn(_Paddr64t, unsigned, int, struct cacheattr_entry *, volatile struct syspage_entry *);
+struct cacheattr_entry {
+	_Uint32t	next;
+	_Uint32t	line_size;
+	_Uint32t	num_lines;
+	_Uint32t	flags;
+	_Uint16t	ways;
+	_Uint16t	spare0[3];
+	__cache_rtn	*control;
+};
+
+struct typed_strings_entry {
+	char				data[4]; /* variable size */
+};
+
+struct strings_entry {
+	char				data[4]; /* variable size */
+};
+
+/*
+ * System independent interrupt flags
+ * (system dependent grow from bottom up).
+ */
+#define INTR_FLAG_CPU_FAULT				0x2000U
+/* INTR_FLAG_MSI allows a range of vectors to be flagged for use as MSI vectors */
+#define INTR_FLAG_MSI                   0x0400U
+
+/*
+ * System independent interrupt code gen flags
+ * (system dependent grow from bottom up).
+ */
+#define INTR_GENFLAG_LOAD_SYSPAGE		0x8000U
+#define INTR_GENFLAG_LOAD_INTRINFO		0x4000U
+#define INTR_GENFLAG_LOAD_LEVEL			0x2000U
+#define INTR_GENFLAG_LOAD_INTRMASK		0x1000U
+#define INTR_GENFLAG_NOGLITCH			0x0800U
+#define INTR_GENFLAG_LOAD_CPUNUM		0x0400U
+#define INTR_GENFLAG_ID_LOOP			0x0200U
+
+struct __intrgen_data {
+	_Uint16t	genflags;
+	_Uint16t	size;
+	_Uint32t	spare;
+	void		(*rtn)(void);
+};
+
+#define INTR_CONFIG_FLAG_PREATTACH	0x0001U
+#define INTR_CONFIG_FLAG_DISALLOWED	0x0002U
+#define INTR_CONFIG_FLAG_IPI		0x0004U
+/* system wide interrupt, not per-cpu*/
+#define INTR_CONFIG_FLAG_SYS		0x0008U
+
+/**
+ * Describes an interrupt controller and its relationship to other interrupt
+ * controllers. Controllers may be cascaded and form a tree-like structure.
+ *
+ * An instance of this structure is initialized by startup for every interrupt
+ * controller attached to the system.
+ */
+struct intrinfo_entry {
+	/**
+	 * Logical interrupt vector used as the lower bound for the set of
+	 * interrupts handled by this controller.
+	 */
+	_Uint32t				vector_base;
+
+	/**
+	 * Number of logical interrupt vectors handled by this controller. The upper
+	 * bound of interrupts handled by this controller is `vector_base +
+	 * num_vectors`.
+	 */
+	_Uint32t				num_vectors;
+
+	/**
+	 * Logical interupt vector that this controller cascades into, i.e. the
+	 * logical interrupt vector that this controller is a child of.
+	 */
+	_Uint32t				cascade_vector;
+
+	/**
+	 * Base hardware interrupt vector for this controller. The meaning of this
+	 * value is architecture dependent; for example, on x86-64 it corresponds to
+	 * the base IDT entry for this controller while on aarch64 it is unused.
+	 */
+	_Uint32t				cpu_intr_base;
+
+	/**
+	 * Spacing between interrupt vector entries when using autovectoring.
+	 */
+	_Uint16t				cpu_intr_stride;
+
+	/**
+	 * An OR of `INTR_FLAG_*` values.
+	 */
+	_Uint16t				flags;
+
+	/**
+	 * Code fragment that identifies the source of this interrupt.
+	 */
+	struct __intrgen_data	id;
+
+	/**
+	 * Code fragment that signals the end of interrupt handling.
+	 */
+	struct __intrgen_data	eoi;
+
+	/**
+	 * A kernel callout to mask the interrupt source at the controller.
+	 */
+	int (*mask)(struct syspage_entry * spp, int id);
+
+	/**
+	 * A kernel callout to unmask the interrupt source at the controller.
+	 */
+	int (*unmask)(struct syspage_entry * spp, int id);
+
+	/**
+	 * A kernel callout to query the configuration of  the interrupt source at the controller.
+	 */
+	unsigned (*config)(struct syspage_entry * spp, struct intrinfo_entry * iip, int id);
+
+	/**
+	 * The per-CPU stride of this interrupt controller. If set to zero then this
+	 * controller does not describe per-CPU interrupts. If non-zero then this
+	 * controller does describe per-CPU interrupts and the value is the stride
+	 * to be added to `vector_base` per-CPU. Example: a system with four CPU's, a
+	 * `vector_base` of 0x300, and `local_stride` set to 0x100 would have the
+	 * per-CPU interrupts for CPU3 start at logical interrupt vector 0x600.
+	 */
+	_Uint32t				local_stride;
+
+	/**
+	 * Reserved.
+	 */
+	_Uint32t				spare[3];
+};
+
+struct smp_entry {
+	_Uint32t			pending;
+	_Uint32t			spare;
+	void                (*send_ipi)(struct syspage_entry * __syspage,
+                                _Uint64t __target, unsigned __cmd, unsigned *__cmdsp);
+	void                *start_addr;
+};
+
+struct hypinfo_entry {
+    _Uint64t            flags;
+};
+#define HYPINFO_ENABLED 0x1UL
+
+struct cluster_entry {
+	_Uint64t			cpumask; /* bitmask of the CPUs included in a cluster */
+	_Uint16t			name;
+	_Uint16t			spare[3];
+};
+#define SYSTEM_CLUSTER_NAME_PREFIX '_'
+
+
+struct syspage_entry {
+	_Uint16t			size;		/* size of syspage_entry */
+	_Uint16t			total_size;	/* size of system page */
+	_Uint16t			type;
+	_Uint16t			num_cpu;
+	syspage_entry_info	system_private;
+	struct {
+		_Uint16t    major;
+		_Uint16t    minor;
+	}					version;
+	syspage_entry_info	hwinfo;
+	syspage_entry_info	qtime;
+	syspage_entry_info	callout;
+	syspage_entry_info	typed_strings;
+	syspage_entry_info	strings;
+	syspage_entry_info	smp;
+	union {
+#if defined(SYSPAGE_TARGET_ALL) || defined(SYSPAGE_TARGET_X86_64)
+		struct x86_64_syspage_entry	x86_64;
+#endif
+#if defined(SYSPAGE_TARGET_ALL) || defined(SYSPAGE_TARGET_AARCH64)
+		struct aarch64_syspage_entry	aarch64;
+#endif
+		_Uint64t					filler[20];
+	} un;
+	syspage_array_info  asinfo;
+	syspage_array_info  cpuinfo;
+	syspage_array_info  cacheattr;
+	syspage_array_info  intrinfo;
+	syspage_entry_info  hypinfo;
+	syspage_array_info	cluster;
+};
+
+/* <STAN_MACRO5> */
+#define _SYSPAGE_ENTRY_SIZE( __base, __field )	\
+	((__base)->__field.entry_size)
+#define _SYSPAGE_ELEMENT_SIZE( __base, __field )	\
+    ((__base)->__field.element_size)
+
+#define SYSPAGE_ENTRY_SIZE( __field )       (_SYSPAGE_ENTRY_SIZE( _syspage_ptr, __field ))
+
+#define SYSPAGE_ELEMENT_SIZE(__field)		(_SYSPAGE_ELEMENT_SIZE(_syspage_ptr, __field))
+
+#define _SYSPAGE_ENTRY( __base, __field )								\
+	((struct __field##_entry *)(void *)((char *)(__base) + (__base)->__field.entry_off))
+
+#define _SYSPAGE_CPU_ENTRY_SIZE( __base, __cpu, __field )					\
+	((__base)->un.__cpu.__field.entry_size)
+#define _SYSPAGE_CPU_ENTRY( __base, __cpu, __field )					\
+	((struct __cpu##_##__field##_entry *)(void *)((char *)(__base) + (__base)->un.__cpu.__field.entry_off))
+
+#define SYSPAGE_ENTRY( __field )			(_SYSPAGE_ENTRY( _syspage_ptr, __field ))
+#define SYSPAGE_CPU_ENTRY( __cpu, __field )	(_SYSPAGE_CPU_ENTRY( _syspage_ptr, __cpu, __field ))
+
+#define SYSPAGE_CPU_ENTRY_SIZE(__cpu, __field) (_SYSPAGE_CPU_ENTRY_SIZE(_syspage_ptr, __cpu, __field))
+
+#define SYSPAGE_ARRAY_ADJ_OFFSET(__field, __p, __adj_off)	\
+				((struct __field##_entry *)((_Uintptrt)(__p) + (__adj_off)))
+#define _SYSPAGE_ARRAY_IDX(__base, __field, __idx)	\
+				(SYSPAGE_ARRAY_ADJ_OFFSET(__field, _SYSPAGE_ENTRY((__base), __field), (__idx) * _SYSPAGE_ELEMENT_SIZE((__base), __field)))
+#define SYSPAGE_ARRAY_IDX(__field, __idx)	(_SYSPAGE_ARRAY_IDX(_syspage_ptr, __field,( __idx)))
+/* </STAN_MACRO5> */
+
+__END_DECLS
+
+#endif /* __SYSPAGE_H_INCLUDED */

readme.txt

@@ -0,0 +1,4 @@
+
+QNX Neutrino for:     BSP_raspberrypi-bcm2711-rpi4_br-hw-rel_be-800
+SVN Revision Number:  999745
+Build Number:         198

source.xml

@@ -0,0 +1,19 @@
+<!-- Unless otherwise specified, values/attributes are free-form strings -->
+    <!-- type is currently either BSP or SourceOnly -->
+<sourcePackage type="BSP" id="hw.raspberrypi-bcm2711-rpi4">
+    <title>Raspberry Pi BCM2711 R-PI4</title>
+    <release>BSP_raspberrypi-bcm2711-rpi4_br-hw-rel_be-800-BN198</release>
+    <maturity>Development Build</maturity>
+    <license>QDL and Apache II</license>
+    <startup>startup-bcm2711-rpi4</startup>
+    <requires>package: com.qnx.${baselineId}.target.pci.hw.bcm2711</requires>
+    <description> This package contains the source and build files for targeting QNX/Muon on the Raspberry Pi 4 board.</description>
+    <vendor>BlackBerry Limited</vendor>
+    <qnxTargetVersion>SDP8.0</qnxTargetVersion>
+    <qnxTargetCPU variant="aarch64le">AARCH64</qnxTargetCPU>
+    <property key="f.swtype" value="I"/>
+    <!-- type is currently only import, will be extended in the future. -->
+    <bsp type="import">
+        <import id="raspberrypi-bcm2711-rpi4">images/rpi4.build</import>
+    </bsp>
+</sourcePackage>

src/Makefile

@@ -0,0 +1,4 @@
+LIST=ALL
+EARLY_DIRS=lib
+LATE_DIRS=
+include recurse.mk

src/hardware/Makefile

@@ -0,0 +1,3 @@
+LIST=hardware
+LATE_DIRS=can devu
+include recurse.mk

src/hardware/devb/Makefile

@@ -0,0 +1,3 @@
+EARLY_DIRS=cam
+LIST=DEVB
+include recurse.mk

src/hardware/devb/NDA_DRIVERS

@@ -0,0 +1,17 @@
+The devb drivers have the following source status:
+
+libs               source status
+cam                  clean
+cdrom                clean
+disk                 clean
+optical              clean
+sa                   do not release
+
+driver             source status
+eide                 NDA's with VIA, SiS, AcerLabs, Promise, ServerWorks, ATI
+                       JMicron, Intel, Renesas
+ahci                 clean
+umass                clean
+ram                  clean
+sercd                NDA with TI/HB - do not release
+sdmmc                unknown

src/hardware/devb/common.mk

@@ -0,0 +1,91 @@
+ifndef QCONFIG
+QCONFIG=qconfig.mk
+endif
+include $(QCONFIG)
+
+BIND = $(strip $(FBIND) $(CBIND))
+FBBIND = $(filter io-blk, $(FBIND))
+FSBIND = $(filter-out io-blk, $(FBIND))
+
+ifndef NAME
+NAME=devb-$(SECTION)
+EXTRA_SILENT_VARIANTS+=$(SECTION)
+endif
+
+SERVICES_ROOT=$(PRODUCT_ROOT)/../services
+
+EXTRA_INCVPATH += $(SERVICES_ROOT)/blk/lib/include
+EXTRA_INCVPATH += $(SERVICES_ROOT)/blk
+EXTRA_INCVPATH += $(PROJECT_ROOT)/include
+EXTRA_INCVPATH += $(PROJECT_ROOT)/$(SECTION)/public
+USEFILE=$(PROJECT_ROOT)/$(SECTION)/$(NAME).use
+INSTALLDIR=sbin
+EXCLUDE_OBJS = dl.o
+CCFLAGS += -D__DEVB_NAME__=$(BUILDNAME)
+CCFLAGS += -DCAM_PTHREAD_SETNAME
+
+# Set stack size to 64K
+LDFLAGS += -N64K
+
+ifneq ($(BIND),)
+#
+# Static link some stuff into devb.*
+#
+DEFLIB_VARIANT = $(patsubst a.,a,$(subst $(space),.,a $(filter wcc be le v7,$(VARIANTS))))
+
+LIB_VARIANT = $(firstword $(subst ./,,$(dir $(bind))) $(DEFLIB_VARIANT))
+
+CCFLAGS += -Ddlopen=bound_dlopen -Ddlsym=bound_dlsym -Ddlclose=bound_dlclose -Ddlerror=bound_dlerror
+CCFLAGS += $(foreach var,$(FBIND), -DDLL_$(subst -,_,$(notdir $(var)))) $(foreach var,$(CBIND), -DDLL_cam_$(notdir $(var))) -DDLL_cam
+EXTRA_LIBVPATH += $(foreach bind,$(FBBIND),$(SERVICES_ROOT)/blk/$(notdir $(bind))/$(CPU)/$(LIB_VARIANT))
+EXTRA_LIBVPATH += $(foreach bind,$(FSBIND),$(SERVICES_ROOT)/blk/fs/$(notdir $(bind))/$(CPU)/$(LIB_VARIANT))
+EXTRA_LIBVPATH += $(foreach bind,$(CBIND),$(PROJECT_ROOT)/cam/drivers/$(notdir $(bind))/$(CPU)/$(LIB_VARIANT))
+EXTRA_OBJS += dl.o
+
+LIBS += $(notdir $(FBBIND)) $(addprefix fs-, $(notdir $(FSBIND))) $(addprefix cam-,$(notdir $(CBIND)))
+ifneq ($(CBIND),)
+EXTRA_LIBVPATH += $(PROJECT_ROOT)/cam/cam/$(CPU)/$(DEFLIB_VARIANT)
+EXTRA_LIBVPATH += $(SERVICES_ROOT)/../lib/usbdi/$(CPU)/$(DEFLIB_VARIANT)
+LIBS += cam cache smmu
+endif
+endif
+ifeq ($(CBIND),)
+LDOPTS += -lcam -M
+endif
+LIBS += drvr cache smmu secpol slog2
+
+# static link LIBS+=fsshared gpt usbdi qcrypto
+
+ifeq ($(BIND),)
+EXTRA_LIBVPATH+=$(PROJECT_ROOT)/cam/cam/$(subst x86/so.,x86/so,$(CPU)/so.$(filter le be,$(subst ., ,$(VARIANTS))))
+
+# static link EXTRA_LIBVPATH+=$(SERVICES_ROOT)/../lib/usbdi/$(subst x86/so.,x86/so,$(CPU)/so.$(filter le be,$(subst ., ,$(VARIANTS))))
+endif
+
+define PINFO
+PINFO DESCRIPTION=
+endef
+
+include $(MKFILES_ROOT)/qmacros.mk
+-include $(SECTION_ROOT)/pinfo.mk
+-include $(SECTION_ROOT)/extra_libs.mk
+-include $(SECTION_ROOT)/$(CPU)/extra_libs.mk
+
+-include $(PROJECT_ROOT)/roots.mk
+
+
+#####AUTO-GENERATED by packaging script... do not checkin#####
+   INSTALL_ROOT_nto = $(PROJECT_ROOT)/../../../install
+   USE_INSTALL_ROOT=1
+##############################################################
+
+include $(MKFILES_ROOT)/qtargets.mk
+
+
+#
+# So that it recompiles if the BIND list is changed.
+#
+dl.o : Makefile ../../../common.mk
+
+nda:
+	$(foreach f, $(NDAS), $(CP_HOST) $(patsubst %.o-nda, %.o, $(f)) $(f);)

src/hardware/devb/dl.c

@@ -0,0 +1,93 @@
+/*
+*
+* Copyright (c) 2013, QNX Software Systems.
+*
+* Licensed under the Apache License, Version 2.0 (the "License"). You
+* may not reproduce, modify or distribute this software except in
+* compliance with the License. You may obtain a copy of the License
+* at: http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" basis,
+* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+*
+*/
+
+
+
+#undef dlopen
+#undef dlclose
+#undef dlerror
+#undef dlsym
+
+#include <dlfcn.h>
+#include <errno.h>
+#include <malloc.h>
+#include <string.h>
+#include "dl.h"
+
+static int
+is_bound(const struct dll_entry *test) {
+	const struct dll_entry	*l;
+
+	for (l = dll_list; l->fname != NULL; ++l) {
+		if (l == test) {
+			return(1);
+		}
+	}
+	return(0);
+}
+
+void *
+bound_dlopen(const char *pathname, int mode) {
+	const struct dll_entry	*l;
+
+	for (l = dll_list; l->fname != NULL; ++l) {
+		if ((pathname != NULL) && (strcmp(l->fname, pathname) == 0)) {
+			return((void *)l);
+		}
+	}
+	return(dlopen(pathname, mode));
+}
+
+void *
+bound_dlsym(void *handle, const char *name) {
+	const struct dll_entry	*l;
+	const struct dll_syms	*s;
+
+	if (handle == RTLD_DEFAULT) {
+		for (l = dll_list; l->fname != NULL; ++l) {
+			for (s = l->syms; s->symname != NULL; ++s) {
+				if (strcmp(name, s->symname) == 0) {
+					return(s->addr);
+				}
+			}
+		}
+	}
+
+	if (!is_bound(handle)) return(dlsym(handle, name));
+
+	for (s = ((struct dll_entry *)handle)->syms; s->symname != NULL; ++s) {
+		if (strcmp(name, s->symname) == 0) {
+			return(s->addr);
+		}
+	}
+	return(NULL);
+}
+
+int
+bound_dlclose(void *handle) {
+	if (!is_bound(handle)) return(dlclose(handle));
+
+	return(0);
+}
+
+char *
+bound_dlerror(void) {
+	return(dlerror());
+}
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/dl.c $ $Rev: 982571 $")
+#endif

src/hardware/devb/include/cam.h

@@ -0,0 +1,578 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at  
+ * http://licensing.qnx.com/license-guide/ for other information. 
+ * $ 
+ */
+
+/*
+ * CAM def from ANSI X3T9.2 spec
+ */
+#ifndef _CAM_H_INCLUDED
+#define _CAM_H_INCLUDED
+
+#ifndef _STDINT_H_INCLUDED
+#include <stdint.h>
+#endif
+
+#ifndef __TYPES_H_INCLUDED
+#include <sys/types.h>
+#endif
+
+#ifndef	__QUEUE_H_INCLUDED
+#include <sys/queue.h>
+#endif
+
+struct _sim_hba;
+struct _resmgr_context;
+
+typedef void		CCB;
+typedef void		*CAM_VOID_OFFSET;
+typedef void		*CAM_VM_OFFSET;
+typedef paddr64_t	CAM_PM_OFFSET;
+typedef _Uint64t	CAM_U64;
+typedef _Uint32t	CAM_U32;
+typedef _Uint16t	CAM_U16;
+typedef _Uint8t		CAM_U8;
+typedef _Int64t		CAM_I64;
+typedef _Int32t		CAM_I32;
+typedef _Int16t		CAM_I16;
+typedef _Int8t		CAM_I8;
+
+/* ---------------------------------------------------------------------- */
+
+/* Defines for the XPT function codes, Table 8-2 in the CAM spec. */
+
+/* Common function commands, 0x00 - 0x0F */
+#define XPT_NOOP        0x00    /* Execute Nothing */
+#define XPT_SCSI_IO     0x01    /* Execute the requested SCSI IO */
+#define XPT_GDEV_TYPE   0x02    /* Get the device type information */
+#define XPT_PATH_INQ    0x03    /* Path Inquiry */
+#define XPT_REL_SIMQ    0x04    /* Release the SIM queue that is frozen */
+#define XPT_SASYNC_CB   0x05    /* Set Async callback parameters */
+#define XPT_SDEV_TYPE   0x06    /* Set the device type information */
+#define XPT_SCAN_BUS    0x07    /* Scan SCSI bus */
+
+/* XPT SCSI control functions, 0x10 - 0x1F */
+#define XPT_ABORT       0x10    /* Abort the selected CCB */
+#define XPT_RESET_BUS   0x11    /* Reset the SCSI bus */
+#define XPT_RESET_DEV   0x12    /* Reset the SCSI device, BDR */
+#define XPT_TERM_IO     0x13    /* Terminate the I/O process */
+#define XPT_SCAN_LUN    0x14    /* Scan LUN */
+
+/* HBA engine commands, 0x20 - 0x2F */
+#define XPT_ENG_INQ     0x20    /* HBA engine inquiry */
+#define XPT_ENG_EXEC    0x21    /* HBA execute engine request */
+
+/* Target mode commands, 0x30 - 0x3F */
+#define XPT_EN_LUN      0x30    /* Enable LUN, Target mode support */
+#define XPT_TARGET_IO   0x31    /* Execute the target IO request */
+
+#define XPT_FUNC        0x7F    /* TEMPLATE */
+#define XPT_VUNIQUE     0x80    /* All the rest are vendor unique commands */
+#define XPT_DEVCTL      0x81    /* devctl */
+
+/* ---------------------------------------------------------------------- */
+
+/* General allocation length defines for the CCB structures. */
+
+#define IOCDBLEN        16      /* Space for the CDB bytes/pointer */
+#define VUHBA           14      /* Vendor Unique HBA length */
+#define SIM_ID          16      /* ASCII string len for SIM ID */
+#define HBA_ID          16      /* ASCII string len for HBA ID */
+#define SIM_PRIV        100     /* Length of SIM private data area */
+
+/* Structure definitions for the CAM control blocks, CCB's for the
+subsystem. */
+
+typedef _Int32t path_id_t;
+typedef _Uint32t target_id_t;
+typedef _Uint64t lun_id_t;
+
+/* Common CCB header definition. */
+typedef struct ccb_header
+{
+    struct ccb_header *my_addr;       /* The address of this CCB */
+    u_short           cam_ccb_len;    /* Length of the entire CCB */
+    u_char            cam_func_code;  /* XPT function code */
+    volatile u_char   cam_status;     /* Returned CAM subsystem status */
+    _Uint32t          cam_flags;      /* Flags for operation of the subsystem */
+    path_id_t         cam_path_id;    /* Path ID for the request */
+    target_id_t       cam_target_id;  /* Target device ID */
+    lun_id_t          cam_target_lun; /* Target LUN number */
+    u_char            cam_priority;   /* NTO extension */
+    u_char            cam_rsvd[7];
+} CCB_HEADER;
+
+/* Common SCSI functions. */
+
+/* Union definition for the CDB space in the SCSI I/O request CCB */
+typedef union cdb_un
+{
+    u_char *cam_cdb_ptr;                /* Pointer to the CDB bytes to send */
+    u_char cam_cdb_bytes[ IOCDBLEN ];   /* Area for the CDB to send */
+} CDB_UN;
+
+#ifndef _CAM_SG_ELEM_DEFINED
+#define _CAM_SG_ELEM_DEFINED
+/* Typedef for a scatter/gather list element. */
+typedef struct sg_elem
+{
+    _Uint64t cam_sg_address;            /* Scatter/Gather address */
+    _Uint32t cam_sg_count;              /* Scatter/Gather count */
+    _Uint32t rsvd;
+} SG_ELEM;
+#endif
+
+#define CAM_DATA_PTR_V( _p )	((void *)(uintptr_t)(_p))
+#define CAM_DATA_PTR_P( _p )	((uintptr_t)(_p))
+typedef union cam_data_un
+{
+    _Uint64t cam_data_ptr;              /* Pointer to the data buf */
+    SG_ELEM *cam_sg_ptr;                /* Pointer to the data SG list */
+} CAM_DATA_UN;
+
+/* Get device type CCB */
+typedef struct ccb_getdev
+{
+    CCB_HEADER cam_ch;                  /* Header information fields */
+    char *cam_inq_data;                 /* Ptr to the inquiry data space */
+    u_char cam_pd_type;                 /* Periph device type from the TLUN */
+} CCB_GETDEV;
+
+/* Path inquiry CCB */
+typedef struct ccb_pathinq
+{
+    CCB_HEADER cam_ch;                  /* Header information fields */
+    u_char cam_version_num;             /* Version number for the SIM/HBA */
+    u_char cam_hba_inquiry;             /* Mimic of INQ byte 7 for the HBA */
+    u_char cam_target_sprt;             /* Flags for target mode support */
+    u_char cam_hba_misc;                /* Misc HBA feature flags */
+    u_short cam_hba_eng_cnt;            /* HBA engine count */
+    u_char cam_vuhba_flags[ VUHBA ];    /* Vendor unique capabilities */
+    uint32_t cam_sim_priv;              /* Size of SIM private data area */
+    uint32_t cam_async_flags;           /* Event cap. for Async Callback */
+ 
+    target_id_t cam_initiator_id;       /* ID of the HBA on the SCSI bus */
+    path_id_t   cam_hpath_id;           /* Highest path ID in the subsystem */
+ 
+    char cam_sim_vid[ SIM_ID ];         /* Vendor ID of the SIM */
+    char cam_hba_vid[ HBA_ID ];         /* Vendor ID of the HBA */
+    u_char *cam_osd_usage;              /* Ptr for the OSD specific area */
+} CCB_PATHINQ;
+
+/* Release SIM Queue CCB */
+typedef struct ccb_relsim
+{
+    CCB_HEADER cam_ch;                  /* Header information fields */
+	uint32_t     cam_frozen_count;      /* SIM queue frozen count    */
+} CCB_RELSIM, CCB_FRZSIM;
+
+/* SCSI I/O Request CCB */
+typedef struct ccb_scsiio CCB_SCSIIO;
+struct ccb_scsiio
+{
+    CCB_HEADER cam_ch;               /* Header information fields */
+    u_char *cam_pdrv_ptr;            /* Ptr used by the Peripheral driver */
+    CCB_HEADER *cam_next_ccb;        /* Ptr to the next CCB for action */
+    u_char *cam_req_map;             /* Ptr for mapping info on the Req. */
+    void (*cam_cbfcnp)(CCB_SCSIIO *);/* Callback on completion function */
+    CAM_DATA_UN cam_data;            /* Pointer to the data buf/SG list */
+    uint32_t cam_dxfer_len;          /* Data xfer length */
+    u_char *cam_sense_ptr;           /* Pointer to the sense data buffer */
+    u_char cam_sense_len;            /* Num of bytes in the Autosense buf */
+    u_char cam_cdb_len;              /* Number of bytes for the CDB */
+    u_short cam_sglist_cnt;          /* Num of scatter gather list entries */
+    uint32_t cam_osd_rsvd0;          /* OSD Reserved field, for alignment */
+    u_char cam_scsi_status;          /* Returned scsi device status */
+    u_char cam_sense_resid;          /* Autosense resid length: 2's comp */
+    u_char cam_osd_rsvd1[2];         /* OSD Reserved field, for alignment */
+    int cam_resid;                   /* Transfer residual length: 2's comp */
+    CDB_UN cam_cdb_io;               /* Union for CDB bytes/pointer */
+    uint32_t cam_timeout;            /* Timeout value */
+    u_char *cam_msg_ptr;             /* Pointer to the message buffer */
+    u_short cam_msgb_len;            /* Num of bytes in the message buf */
+    u_short cam_vu_flags;            /* Vendor unique flags */
+    u_char cam_tag_action;           /* What to do for tag queuing */
+    u_char cam_iorsvd0[3];           /* Reserved field, for alignment */
+    union {
+		TAILQ_ENTRY(ccb_scsiio)	clink;
+	    u_char cam_sim_priv[ SIM_PRIV ]; /* SIM private data area */
+	};
+};
+
+/* Set Async Callback CCB */
+typedef struct ccb_setasync
+{
+    CCB_HEADER cam_ch;               /* Header information fields */
+    uint32_t cam_async_flags;        /* Event enables for Callback resp */
+    void (*cam_async_func)(int opcode, path_id_t path_id, target_id_t target_id, lun_id_t lun,
+                           void *buffer_ptr, int data_cnt);
+                                     /* Async Callback function address */
+    u_char *pdrv_buf;                /* Buffer set aside by the Per. drv */
+    u_char pdrv_buf_len;             /* The size of the buffer */
+} CCB_SETASYNC;
+
+/* Set device type CCB */
+typedef struct ccb_setdev
+{
+    CCB_HEADER cam_ch;               /* Header information fields */
+    u_char cam_dev_type;             /* Val for the dev type field in EDT */
+} CCB_SETDEV;
+
+/* SCSI Control Functions. */
+
+/* Abort XPT Request CCB */
+typedef struct ccb_abort
+{
+    CCB_HEADER cam_ch;                  /* Header information fields */
+    CCB_HEADER *cam_abort_ch;           /* Pointer to the CCB to abort */
+} CCB_ABORT;
+
+/* Reset SCSI Bus CCB */
+typedef struct ccb_resetbus
+{
+    CCB_HEADER cam_ch;                  /* Header information fields */
+} CCB_RESETBUS;
+
+/* Reset SCSI Device CCB */
+typedef struct ccb_resetdev
+{
+    CCB_HEADER cam_ch;                  /* Header information fields */
+} CCB_RESETDEV;
+
+/* Terminate I/O Process Request CCB */
+typedef struct ccb_termio
+{
+    CCB_HEADER cam_ch;                  /* Header information fields */
+    CCB_HEADER *cam_termio_ch;          /* Pointer to the CCB to terminate */
+} CCB_TERMIO;
+
+/* Target mode structures. */
+
+typedef struct ccb_en_lun
+{
+    CCB_HEADER cam_ch;                  /* Header information fields */
+    u_short cam_grp6_len;               /* Group 6 VU CDB length */
+    u_short cam_grp7_len;               /* Group 7 VU CDB length */
+    u_char *cam_ccb_listptr;            /* Pointer to the target CCB list */
+    u_short cam_ccb_listcnt;            /* Count of Target CCBs in the list */
+} CCB_EN_LUN;
+
+/* HBA engine structures. */
+
+typedef struct ccb_eng_inq
+{
+    CCB_HEADER cam_ch;                  /* Header information fields */
+    u_short cam_eng_num;                /* The number for this inquiry */
+    u_char cam_eng_type;                /* Returned engine type */
+    u_char cam_eng_algo;                /* Returned algorithm type */
+    uint32_t cam_eng_memory;            /* Returned engine memory size */
+} CCB_ENG_INQ;
+
+typedef struct ccb_eng_exec CCB_ENG_EXEC;
+struct ccb_eng_exec     /* NOTE: must match SCSIIO size */
+{
+    CCB_HEADER cam_ch;               /* Header information fields */
+    u_char *cam_pdrv_ptr;            /* Ptr used by the Peripheral driver */
+    uint32_t cam_engrsvd0;           /* Reserved field, for alignment */
+    u_char *cam_req_map;             /* Ptr for mapping info on the Req. */
+    void (*cam_cbfcnp)(CCB_ENG_EXEC *);/* Callback on completion function */
+    CAM_DATA_UN cam_data;            /* Pointer to the data buf/SG list */
+    uint32_t cam_dxfer_len;          /* Data xfer length */
+    u_char *cam_engdata_ptr;         /* Pointer to the engine buffer data */
+    u_char cam_engrsvd1;             /* Reserved field, for alignment */
+    u_char cam_engrsvd2;             /* Reserved field, for alignment */
+    u_short cam_sglist_cnt;          /* Num of scatter gather list entries */
+    uint32_t cam_dmax_len;           /* Destination data maximum length */
+    uint32_t cam_dest_len;           /* Destination data length */
+    int cam_src_resid;               /* Source residual length: 2's comp */
+    u_char cam_engrsvd3[12];         /* Reserved field, for alignment */
+    uint32_t cam_timeout;            /* Timeout value */
+    uint32_t cam_engrsvd4;           /* Reserved field, for alignment */
+    u_short cam_eng_num;             /* Engine number for this request */
+    u_short cam_vu_flags;            /* Vendor unique flags */
+    u_char cam_engrsvd5;             /* Reserved field, for alignment */
+    u_char cam_engrsvd6[3];          /* Reserved field, for alignment */
+    u_char cam_sim_priv[ SIM_PRIV ]; /* SIM private data area */
+};
+
+typedef struct ccb_devctl CCB_DEVCTL;
+struct ccb_devctl
+{
+    CCB_HEADER cam_ch;               /* Header information fields */
+    u_char *cam_pdrv_ptr;            /* Ptr used by the Peripheral driver */
+    CCB_HEADER *cam_next_ccb;        /* Ptr to the next CCB for action */
+    u_char *cam_req_map;             /* Ptr for mapping info on the Req. */
+    void (*cam_cbfcnp)(CCB_DEVCTL *);      /* Callback on completion function */
+	struct _resmgr_context *cam_devctl_ctp;
+	uint32_t cam_devctl_dcmd;
+	int    cam_devctl_status;
+	int    cam_devctl_ioflag;
+	void   *cam_devctl_data;
+	size_t cam_devctl_size;
+	int    *cam_devctl_ret;
+    uint32_t cam_iorsvd0[8];         /* Reserved field, for alignment */
+    u_char cam_sim_priv[ SIM_PRIV ]; /* SIM private data area */
+};
+
+/* The CAM_SIM_ENTRY definition is used to define the entry points for
+the SIMs contained in the SCSI CAM subsystem.  Each SIM file will
+contain a declaration for it's entry.  The address for this entry will
+be stored in the cam_conftbl[] array aint will all the other SIM
+entries. */
+
+typedef struct cam_sim_entry
+{
+    int (*sim_init)(struct _sim_hba *, int);     /* Pointer to the SIM init routine */
+    int (*sim_action)(struct _sim_hba *, CCB *); /* Pointer to the SIM CCB go routine */
+} CAM_SIM_ENTRY;
+
+/* ---------------------------------------------------------------------- */
+
+/* Defines for the CAM status field in the CCB header. */
+
+#define CAM_REQ_INPROG          0x00  /* CCB request is in progress */
+#define CAM_REQ_CMP             0x01  /* CCB request completed w/out error */
+#define CAM_REQ_ABORTED         0x02  /* CCB request aborted by the host */
+#define CAM_UA_ABORT            0x03  /* Unable to Abort CCB request */
+#define CAM_REQ_CMP_ERR         0x04  /* CCB request completed with an err */
+#define CAM_BUSY                0x05  /* CAM subsystem is busy */
+#define CAM_REQ_INVALID         0x06  /* CCB request is invalid */
+#define CAM_PATH_INVALID        0x07  /* Path ID supplied is invalid */
+#define CAM_DEV_NOT_THERE       0x08  /* SCSI device not installed/there */
+#define CAM_UA_TERMIO           0x09  /* Unable to Terminate I/O CCB req */
+#define CAM_SEL_TIMEOUT         0x0A  /* Target selection timeout */
+#define CAM_CMD_TIMEOUT         0x0B  /* Command timeout */
+#define CAM_MSG_REJECT_REC      0x0D  /* Message reject received */
+#define CAM_SCSI_BUS_RESET      0x0E  /* SCSI bus reset sent/received */
+#define CAM_UNCOR_PARITY        0x0F  /* Uncorrectable parity err occurred */
+#define CAM_AUTOSENSE_FAIL      0x10  /* Autosense: Request sense cmd fail */
+#define CAM_NO_HBA              0x11  /* No HBA detected Error */
+#define CAM_DATA_RUN_ERR        0x12  /* Data overrun/underrun error */
+#define CAM_UNEXP_BUSFREE       0x13  /* Unexpected BUS free */
+#define CAM_SEQUENCE_FAIL       0x14  /* Target bus phase sequence failure */
+#define CAM_CCB_LEN_ERR         0x15  /* CCB length supplied is inadequate */
+#define CAM_PROVIDE_FAIL        0x16  /* Unable to provide requ. capability */
+#define CAM_BDR_SENT            0x17  /* A SCSI BDR msg was sent to target */
+#define CAM_REQ_TERMIO          0x18  /* CCB request terminated by the host */
+
+#define CAM_LUN_INVALID         0x38  /* LUN supplied is invalid */
+#define CAM_TID_INVALID         0x39  /* Target ID supplied is invalid */
+#define CAM_FUNC_NOTAVAIL       0x3A  /* The requ. func is not available */
+#define CAM_NO_NEXUS            0x3B  /* Nexus is not established */
+#define CAM_IID_INVALID         0x3C  /* The initiator ID is invalid */
+#define CAM_CDB_RECVD           0x3E  /* The SCSI CDB has been received */
+#define CAM_SCSI_BUSY           0x3F  /* SCSI bus busy */
+
+#define CAM_SIM_QFRZN           0x40  /* The SIM queue is frozen w/this err */
+#define CAM_AUTOSNS_VALID       0x80  /* Autosense data valid for target */
+
+#define CAM_STATUS_MASK         0x3F  /* Mask bits for just the status # */
+
+/* ---------------------------------------------------------------------- */
+
+/* Defines for the CAM flags field in the CCB header. */
+
+#define CAM_DIR_RESV       0x00000000 /* Data direction (00: reserved) */
+#define CAM_DIR_IN         0x00000040 /* Data direction (01: DATA IN) */
+#define CAM_DIR_OUT        0x00000080 /* Data direction (10: DATA OUT) */
+#define CAM_DIR_NONE       0x000000C0 /* Data direction (11: no data) */
+#define CAM_DIS_AUTOSENSE  0x00000020 /* Disable autosense feature */
+#define CAM_SCATTER_VALID  0x00000010 /* Scatter/gather list is valid */
+#define CAM_DIS_CALLBACK   0x00000008 /* Disable callback feature */
+#define CAM_CDB_LINKED     0x00000004 /* The CCB contains a linked CDB */
+#define CAM_QUEUE_ENABLE   0x00000002 /* SIM queue actions are enabled */
+#define CAM_CDB_POINTER    0x00000001 /* The CDB field contains a pointer */
+
+#define CAM_DIS_DISCONNECT 0x00008000 /* Disable disconnect */
+#define CAM_INITIATE_SYNC  0x00004000 /* Attempt Sync data xfer, and SDTR */
+#define CAM_DIS_SYNC       0x00002000 /* Disable sync, go to async */
+#define CAM_SIM_QIMMED     0x00010000 /* Place CCB at the head of SIM Q/immediate */
+#define CAM_SIM_QHEAD      0x00001000 /* Place CCB at the head of SIM Q */
+#define CAM_SIM_QFREEZE    0x00000800 /* Return the SIM Q to frozen state */
+#define CAM_SIM_QFRZDIS    0x00000400 /* Disable the SIM Q frozen state */
+#define CAM_ENG_SYNC       0x00000200 /* Flush resid bytes before cmplt */
+
+#define CAM_ENG_SGLIST     0x00800000 /* The SG list is for the HBA engine */
+#define CAM_CDB_PHYS       0x00400000 /* CDB pointer is physical */
+#define CAM_DATA_PHYS      0x00200000 /* SG/Buffer data ptrs are physical */
+#define CAM_SNS_BUF_PHYS   0x00100000 /* Autosense data ptr is physical */
+#define CAM_MSG_BUF_PHYS   0x00080000 /* Message buffer ptr is physical */
+#define CAM_NXT_CCB_PHYS   0x00040000 /* Next CCB pointer is physical */
+#define CAM_CALLBCK_PHYS   0x00020000 /* Callback func ptr is physical */
+#define CAM_FLAGS_PHYS     0x007e0000 
+
+#define CAM_DATAB_VALID    0x80000000 /* Data buffer valid */
+#define CAM_STATUS_VALID   0x40000000 /* Status buffer valid */
+#define CAM_MSGB_VALID     0x20000000 /* Message buffer valid */
+#define CAM_TGT_PHASE_MODE 0x08000000 /* The SIM will run in phase mode */
+#define CAM_TGT_CCB_AVAIL  0x04000000 /* Target CCB available */
+#define CAM_DIS_AUTODISC   0x02000000 /* Disable autodisconnect */
+#define CAM_DIS_AUTOSRP    0x01000000 /* Disable autosave/restore ptrs */
+
+/* Defines for the CAM vu flags field. */
+#define CAM_VUF_TIME_G1		0x01
+#define CAM_VUF_TIME_G2		0x02
+#define CAM_VUF_TIME_G3		0x04
+#define CAM_VUF_DECRYPT		0x08
+
+/* ---------------------------------------------------------------------- */
+
+/* Defines for the SIM/HBA queue actions.  These value are used in the
+SCSI I/O CCB, for the queue action field. [These values should match the
+defines from some other include file for the SCSI message phases.  We may
+not need these definitions here. ] */
+
+#define CAM_SIMPLE_QTAG         0x20            /* Tag for a simple queue */
+#define CAM_HEAD_QTAG           0x21            /* Tag for head of queue */
+#define CAM_ORDERED_QTAG        0x22            /* Tag for ordered queue */
+
+/* ---------------------------------------------------------------------- */
+
+/* Defines for the timeout field in the SCSI I/O CCB.  At this time a value
+of 0xF-F indicates a infinite timeout.  A value of 0x0-0 indicates that the
+SIM's default timeout can take effect. */
+
+#define CAM_TIME_DEFAULT        0x00000000      /* Use SIM default value */
+#define CAM_TIME_INFINITY       0xFFFFFFFF      /* Infinite timeout for I/O */
+
+/* ---------------------------------------------------------------------- */
+
+/* Defines for the Path Inquiry CCB fields. */
+
+#define CAM_VERSION             0x25  /* Binary value for the current ver */
+
+#define PI_MDP_ABLE             0x80  /* Supports MDP message */
+#define PI_WIDE_32              0x40  /* Supports 32 bit wide SCSI */
+#define PI_WIDE_16              0x20  /* Supports 16 bit wide SCSI */
+#define PI_SDTR_ABLE            0x10  /* Supports SDTR message */
+#define PI_LINKED_CDB           0x08  /* Supports linked CDBs */
+#define PI_TAG_ABLE             0x02  /* Supports tag queue message */
+#define PI_SOFT_RST             0x01  /* Supports soft reset */
+
+#define PIT_PROCESSOR           0x80  /* Target mode processor mode */
+#define PIT_PHASE               0x40  /* Target mode phase cog. mode */
+
+#define PIM_SCANHILO            0x80  /* Bus scans from ID 7 to ID 0 */
+#define PIM_NOREMOVE            0x40  /* Removable dev not included in scan */
+#define PIM_NOINQUIRY           0x20  /* Inquiry data not kept by XPT */
+
+/* ---------------------------------------------------------------------- */
+
+/* Defines for Asynchronous Callback CCB fields. */
+
+#define AC_BUFFER_SIZE			50
+#define AC_OS_SIGNAL			0x80000000
+#define AC_OS_PWR_SIGNAL		0x40000000
+#define AC_LOST_DEVICE          0x100  /* Lost device during a rescan */
+#define AC_FOUND_DEVICES        0x080  /* During a rescan new device found */
+#define AC_SIM_DEREGISTER       0x040  /* A loaded SIM has de-registered */
+#define AC_SIM_REGISTER         0x020  /* A loaded SIM has registered */
+#define AC_SENT_BDR             0x010  /* A BDR message was sent to target */
+#define AC_SCSI_AEN             0x008  /* A SCSI AEN has been received */
+#define AC_UNSOL_RESEL          0x002  /* A unsolicited reselection occurred */
+#define AC_BUS_RESET            0x001  /* A SCSI bus RESET occurred */
+
+/* ---------------------------------------------------------------------- */
+
+/* Defines for the HBA engine inquiry CCB fields. */
+
+#define EIT_BUFFER              0x00  /* Engine type: Buffer memory */
+#define EIT_LOSSLESS            0x01  /* Engine type: Lossless compression */
+#define EIT_LOSSLY              0x02  /* Engine type: Lossly compression */
+#define EIT_ENCRYPT             0x03  /* Engine type: Encryption */
+
+#define EAD_VUNIQUE             0x00  /* Eng algorithm ID: vendor unique */
+#define EAD_LZ1V1               0x00  /* Eng algorithm ID: LZ1 var. 1*/
+#define EAD_LZ2V1               0x00  /* Eng algorithm ID: LZ2 var. 1*/
+#define EAD_LZ2V2               0x00  /* Eng algorithm ID: LZ2 var. 2*/
+
+/* ---------------------------------------------------------------------- */
+/* ---------------------------------------------------------------------- */
+
+/* UNIVOS OSD defines and data structures. */
+
+#define INQLEN  96              /* Inquiry string length to store. */
+
+#define CAM_SUCCESS     0       /* For signaling general success */
+#define CAM_FAILURE     1       /* For signaling general failure */
+
+#define CAM_FALSE       0       /* General purpose flag value */
+#define CAM_TRUE        1       /* General purpose flag value */
+
+#define XPT_CCB_INVALID (-1)    /* for signaling a bad CCB to free */
+
+/* General Union for Kernel Space allocation.  Contains all the possible CCB
+structures.  This union should never be used for manipulating CCB's its only
+use is for the allocation and deallocation of raw CCB space. */
+
+typedef union ccb_size_union
+{
+    CCB_SCSIIO    csio;    /* Please keep this first, for debug/print */
+    CCB_GETDEV    cgd;
+    CCB_PATHINQ   cpi;
+    CCB_RELSIM    crs;
+    CCB_SETASYNC  csa;
+    CCB_SETDEV    csd;
+    CCB_ABORT     cab;
+    CCB_RESETBUS  crb;
+    CCB_RESETDEV  crd;
+    CCB_TERMIO    ctio;
+    CCB_EN_LUN    cel;
+    CCB_ENG_INQ   cei;
+    CCB_ENG_EXEC  cee;
+} CCB_SIZE_UNION;
+
+/* The typedef for the Async callback information.  This structure is used to
+store the supplied info from the Set Async Callback CCB, in the EDT table
+in a linked list structure. */
+
+typedef struct async_info
+{
+    struct async_info *cam_async_next;  /* pointer to the next structure */
+    uint32_t cam_event_enable;          /* Event enables for Callback resp */
+    void (*cam_async_func)(int opcode, path_id_t path_id, target_id_t target_id, lun_id_t lun,
+                           void *buffer_ptr, int data_cnt);
+                                        /* Async Callback function address */
+    uint32_t cam_async_blen;            /* Length of "information" buffer */
+    u_char *cam_async_ptr;              /* Address for the "information */
+} ASYNC_INFO;
+
+/* The CAM EDT table contains the device information for all the
+devices, SCSI ID and LUN, for all the SCSI busses in the system.  The
+table contains a CAM_EDT_ENTRY structure for each device on the bus.
+*/
+
+typedef struct cam_edt_entry
+{
+    int cam_tlun_found;         /* Flag for the existence of the target/LUN */
+    ASYNC_INFO *cam_ainfo;      /* Async callback list info for this B/T/L */
+    uint32_t cam_owner_tag;     /* Tag for peripheral driver's ownership */
+	void *dobj;                 /* NTO extension */
+	void *resmgr;               /* NTO extension */
+    char cam_inq_data[ INQLEN ];/* storage for the inquiry data */
+} CAM_EDT_ENTRY;
+
+/* ---------------------------------------------------------------------- */
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/include/cam.h $ $Rev: 973833 $")
+#endif

src/hardware/devb/include/dl.h

@@ -0,0 +1,159 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef _DL_H_INCLUDED
+#define _DL_H_INCLUDED
+
+#include <dlfcn.h>
+
+struct dll_syms {
+	char	*symname;
+	void	*addr;
+};
+
+#ifdef DLL_cam
+#include "dl_cam.h"
+#endif
+
+#ifdef DLL_cam_optical
+#include "dl_optical.h"
+#endif
+
+#ifdef DLL_cam_disk
+#include "dl_disk.h"
+#endif
+
+#ifdef DLL_cam_cdrom
+#include "dl_cdrom.h"
+#endif
+
+#ifdef DLL_io_blk
+#include "io-blk/dl_io_blk.h"
+#endif
+
+#ifdef DLL_cd
+#include "fs/cd/dl_cdfs.h"
+#endif
+
+#ifdef DLL_dos
+#include "fs/dos/dl_dosfs.h"
+#endif
+
+#ifdef DLL_ext2
+#include "fs/ext2/dl_ext2fs.h"
+#endif
+
+#ifdef DLL_udf
+#include "fs/udf/dl_udf.h"
+#endif
+
+#ifdef DLL_qnx6
+#include "fs/qnx6/dl_qnx6fs.h"
+#endif
+
+#ifdef DLL_nt
+#include "fs/nt/dl_ntfs.h"
+#endif
+
+#ifdef DLL_mac
+#include "fs/mac/dl_macfs.h"
+#endif
+
+#ifdef DLL_exfat
+#include "fs/exfat/dl_exfatfs.h"
+#endif
+
+struct dll_entry {
+	char					*fname;
+	const struct dll_syms	*syms;
+};
+
+static const struct dll_entry	dll_list[] = {
+#ifdef DLL_IO_BLK_LIST
+									{ DLL_IO_BLK_LIST },
+#endif
+
+#ifdef CAM_LIST
+									CAM_LIST,
+#endif
+
+#ifdef CAM_OPTICAL_LIST
+									CAM_OPTICAL_LIST,
+#endif
+
+#ifdef CAM_DISK_LIST
+									CAM_DISK_LIST,
+#endif
+
+#ifdef CAM_CDROM_LIST
+									CAM_CDROM_LIST,
+#endif
+
+#ifdef DLL_QNX4_LIST
+									{ DLL_QNX4_LIST },
+#endif
+
+#ifdef DLL_CD_LIST
+									{ DLL_CD_LIST },
+#endif
+
+#ifdef DLL_DOS_LIST
+									{ DLL_DOS_LIST },
+#endif
+
+#ifdef DLL_EXT2_LIST
+									{ DLL_EXT2_LIST },
+#endif
+
+#ifdef DLL_UDF_LIST
+									{ DLL_UDF_LIST },
+#endif
+
+#ifdef DLL_QNX6_LIST
+									{ DLL_QNX6_LIST },
+#endif
+
+#ifdef DLL_NTFS_LIST
+									{ DLL_NTFS_LIST },
+#endif
+
+#ifdef DLL_MAC_LIST
+									{ DLL_MAC_LIST },
+#endif
+
+#ifdef DLL_EXFAT_LIST
+									{ DLL_EXFAT_LIST },
+#endif
+
+									{ .fname = NULL, .syms = NULL }
+								};
+
+void *bound_dlopen(const char *pathname, int mode);
+void *bound_dlsym(void *handle, const char *name);
+int bound_dlclose(void *handle);
+char *bound_dlerror(void);
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/include/dl.h $ $Rev: 982571 $")
+#endif

src/hardware/devb/include/dl_cam.h

@@ -0,0 +1,47 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef DL_CAM_H_INCLUDED
+#define DL_CAM_H_INCLUDED
+
+#include <ntocam.h>
+
+extern int cam_version;
+
+/*
+ * This list is matched with the exported symbol list.
+ */
+static const struct dll_syms cam_syms[] = {
+	{ .symname = "cam_version", .addr  = &cam_version },
+	{ .symname = NULL, .addr  = NULL }
+};
+
+/*
+ * This matched the dll file name
+ */
+#define CAM_LIST		{ .fname = "libcam.so", .syms = cam_syms }
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/include/dl_cam.h $ $Rev: 982571 $")
+#endif

src/hardware/devb/include/dl_cdrom.h

@@ -0,0 +1,48 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+#ifndef DL_CDROM_H_INCLUDED
+#define DL_CDROM_H_INCLUDED
+
+#include <ntocam.h>
+
+extern int dll_pdrvr_init_cdrom( cam_entry_t *cam_funcs, char *argv[] );
+extern int cam_pdrv_version_cdrom;
+
+/*
+ * This list is matched with the exported symbol list.
+ */
+static const struct dll_syms cdrom_syms[] = {
+	{ .symname = "dll_pdrvr_init", .addr  = &dll_pdrvr_init_cdrom },
+	{ .symname = "cam_pdrv_version", .addr  = &cam_pdrv_version_cdrom },
+	{ .symname = NULL, .addr  = NULL }
+};
+
+/*
+ * This matched the dll file name
+ */
+#define CAM_CDROM_LIST		{ .fname = "cam-cdrom.so", .syms = cdrom_syms }
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/include/dl_cdrom.h $ $Rev: 982571 $")
+#endif

src/hardware/devb/include/dl_disk.h

@@ -0,0 +1,47 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+#ifndef DL_DISK_H_INCLUDED
+#define DL_DISK_H_INCLUDED
+
+#include <ntocam.h>
+
+extern int dll_pdrvr_init_disk( cam_entry_t *cam_funcs, char *argv[] );
+extern int cam_pdrv_version_disk;
+
+/*
+ * This list is matched with the exported symbol list.
+ */
+static const struct dll_syms disk_syms[] = {
+	{ .symname = "dll_pdrvr_init", .addr  = &dll_pdrvr_init_disk },
+	{ .symname = "cam_pdrv_version", .addr  = &cam_pdrv_version_disk },
+	{ .symname = NULL, .addr  = NULL }
+};
+
+/*
+ * This matched the dll file name
+ */
+#define CAM_DISK_LIST		{ .fname = "cam-disk.so", .syms = disk_syms }
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/include/dl_disk.h $ $Rev: 982571 $")
+#endif

src/hardware/devb/include/dl_optical.h

@@ -0,0 +1,49 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef DL_OPTICAL_H_INCLUDED
+#define DL_OPTICAL_H_INCLUDED
+
+#include <ntocam.h>
+
+extern int dll_pdrvr_init_optical( cam_entry_t *cam_funcs, char *argv[] );
+extern int cam_pdrv_version_optical;
+
+/*
+ * This list is matched with the exported symbol list.
+ */
+static const struct dll_syms optical_syms[] = {
+	{ .symname = "dll_pdrvr_init", .addr  = &dll_pdrvr_init_optical },
+	{ .symname = "cam_pdrv_version", .addr  = &cam_pdrv_version_optical },
+	{ .symname = NULL, .addr  = NULL }
+};
+
+/*
+ * This matched the dll file name
+ */
+#define CAM_OPTICAL_LIST		{ .fname = "cam-optical.so", .syms = optical_syms }
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/include/dl_optical.h $ $Rev: 982571 $")
+#endif

src/hardware/devb/include/dl_sa.h

@@ -0,0 +1,47 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef DL_SA_H_INCLUDED
+#define DL_SA_H_INCLUDED
+
+#include <ntocam.h>
+
+extern int dll_pdrvr_init_sa( cam_entry_t *cam_funcs, char *argv[] );
+
+/*
+ * This list is matched with the exported symbol list.
+ */
+static const struct dll_syms sa_syms[] = {
+	{ .symname = "dll_pdrvr_init", .addr  = &dll_pdrvr_init_sa },
+	{ .symname = NULL, .addr  = NULL }
+};
+
+/*
+ * This matched the dll file name
+ */
+#define CAM_SA_LIST		{ .fname = "cam-sa.so", .syms = sa_syms }
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/include/dl_sa.h $ $Rev: 982571 $")
+#endif

src/hardware/devb/include/module.h

@@ -0,0 +1,53 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at  
+ * http://licensing.qnx.com/license-guide/ for other information. 
+ * $ 
+ */
+
+#ifndef _MODULE_H_INCLUDED
+#define _MODULE_H_INCLUDED
+
+
+
+/*
+ * args				Process args for this module (only called every
+ *					time the module name appears on the command line.
+ * attach			The "config driver" attach is called first, to initialize
+ *					the xpt subsystem. It then calles all the MODULE_SIM
+ *					attach entries to initalize the hardware. Lastly, the
+ *					MODULE_DRIVER attach are called to initialize the
+ *					connection to the OS.
+ * detach			Used to tell all modules to cleanup as the driver will
+ *					be terminating.
+ */
+
+struct _cam_entry;
+
+typedef struct module_entry {
+	char			*name;
+	int				(*args)(char *options);
+	int				(*attach)(struct _cam_entry *data);
+	int				(*detach)(void);
+} MODULE_ENTRY;
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/include/module.h $ $Rev: 680332 $")
+#endif

src/hardware/devb/include/ntocam.h

@@ -0,0 +1,438 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at  
+ * http://licensing.qnx.com/license-guide/ for other information. 
+ * $ 
+ */
+
+#ifndef __NTO_CAM_H_INCLUDED
+#define __NTO_CAM_H_INCLUDED
+
+#include <stddef.h>
+#include <sys/io.h>
+#include <sys/mman.h>
+#include <sys/types.h>
+#include <sys/iomsg.h>
+#include <sys/resmgr.h>
+#include <sys/queue.h>
+#include <sys/syspage.h>
+#include <sys/dcmd_cam.h>
+#include <sys/slogcodes.h>
+#include <sys/cam_device.h>
+
+#include <cam.h>
+#include <xpt.h>
+#include <ntoscsi.h>
+
+#define _NTO_CAM_VERSION					100
+
+#define XSTR(x)								#x
+#define CAM_STRINGIZE(x)					XSTR((x))
+#define CAM_ARRAY_SIZE( _x )				( sizeof( (_x) ) / sizeof( (_x)[0] ) )
+
+#define CAM_PDRV_VERSION					0x4
+#define CAM_INVALID_NUM						(-0xBAD1)
+#define CAM_INVALID_NUM64					(-0xBAD1LL)
+
+#define CAM_ALIGN( _val, _align )			CAM_ALIGN_MASK( (_val), ( typeof( (_val) ) )(_align) - 1 )
+#define CAM_ALIGN_MASK( _val, _mask )		( ( (_val) + (_mask) ) & ~(_mask) )
+
+#define CAM_ENDIAN_SWAP32( _d, _c )			do { ENDIAN_SWAP32( (_d) ); (_d)++; } while( --(_c) )
+
+#define CAM_L32_BITS( _b )					((_Uint32t)(_b))
+#define CAM_U32_BITS( _b )					((_Uint32t)((_b) >> 32))
+
+#define CAM_BITMASK_LE64( _hbit, _lbit )	( ( ( ~0ULL ) << ( _lbit ) ) & ( ~0ULL >> ( 64 - ( _lbit ) - (_hbit) ) ) )
+#define CAM_BITMASK_LE32( _hbit, _lbit )	( ( ( ~0UL ) << ( _lbit ) ) & ( ~0UL >> ( 32 - ( _lbit ) - (_hbit) ) ) )
+#define CAM_BIT_LE64( _bit )				_ONEBIT64L( (_bit) )
+#define CAM_BIT_LE32( _bit )				_ONEBIT32L( (_bit) )
+#define CAM_BIT_BE64( _bit )				_ONEBIT64B( (_bit) )
+#define CAM_BIT_BE32( _bit )				_ONEBIT32B( (_bit) )
+
+#define CAM_STACK_SIZE						16384
+#define CAM_TSTATE_CREATING					0x00
+#define CAM_TSTATE_INITIALIZED				0x01
+#define CAM_TSTATE_INIT_FAILURE				0x02
+
+#define CAM_SLOG_PAGES						16			// 16 4k pages
+
+#define SCSI_IO_CBF_PULSE_CODE				0x73
+
+
+// Useful TAILQ manifests possibly not in sys/queue.h
+#ifndef TAILQ_EMPTY
+	#define	TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
+#endif
+#ifndef TAILQ_FIRST
+	#define	TAILQ_FIRST(head) ((head)->tqh_first)
+#endif
+#ifndef TAILQ_LAST
+	#define	TAILQ_LAST(head) ((head)->tqh_last)
+#endif
+#ifndef TAILQ_NEXT
+	#define	TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
+#endif
+#ifndef TAILQ_PREV
+	#define TAILQ_PREV(elm, field) ((elm)->field.tqe_prev)
+#endif
+
+typedef struct _devobj_extension			DEVEXT;
+typedef struct _devobj						DEVOBJ;
+typedef struct _pdrvr						PDRVR;
+typedef struct _peripheral_driver_extension	PDRVR_EXT;
+typedef struct _scsi_req_block				SRB;
+
+#define MAX_RETRIES					10
+#define SCSI_START_UNIT_TIMEOUT		30
+#define SCSI_LOAD_TIMEOUT			30
+#define BLOCK_SIZE					512
+#define BOUNCE_BUF_SIZE				32768
+#define BOUNCE_X64_BUF_SIZE			65536	// Max cross 64k bounce buffer size
+#define UNLOCK_MEDIA				0
+#define LOCK_MEDIA					1
+#define LOAD_MEDIA					1
+#define EJECT_MEDIA					0
+#define MAX_TARGET					16		// Max number of SCSI targets
+#define MAX_WIDE_TARGET				16		// Max number of wide SCSI targets
+#define MAX_NARROW_TARGET			8		// Max number of narrow SCSI targets
+#define MAX_LUN						8		// Max number of LUNs per target
+#define CMD_6_BYTE					0
+#define CMD_10_BYTE					1
+#define MAX_IO_BLKS					4096
+#define MAX_SG						256
+#define MAX_SG_EXP					31
+#define MAX_QDEPTH_EXP				31
+#define QDEPTH_DFLT					4
+
+static inline paddr64_t cam_mphys( const void *addr )
+{
+	off64_t offset;
+
+	if( mem_offset64( addr, -1, 1, &offset, NULL ) == -1 ) {
+		return( (paddr64_t) -1LL );
+	}
+
+	return( offset );
+}
+
+int cam_cdb( CCB *);
+#define cam_cdb( ccb )				( (CDB *)(ccb)->cam_cdb_io.cam_cdb_bytes )
+
+int cam_cdb_lun( DEVEXT *);				// only set lun in the cdb when SCSI version < 2
+#define cam_cdb_lun( dext )			( ( (dext)->version & INQ_VANSI ) < 2 ? SC_LUN_CDB( (dext)->lun ) : 0 )
+
+void cam_set_pdrvr( CCB *, void *);
+#define cam_set_pdrvr( ccb, pdrv )	( (ccb)->cam_pdrv_ptr = (void *)(pdrv) )
+
+void cam_set_cbf( CCB *, void *);
+#define cam_set_cbf( ccb, cbf )		( (ccb)->cam_cbfcnp = (void *)(cbf) )
+
+void cam_data_ptr( CCB_SCSIIO *, void *);
+#define cam_data_ptr( ccb, data )	(ccb)->cam_data.cam_data_ptr = 					\
+									( (ccb)->cam_ch.cam_flags & CAM_DATA_PHYS ) ?		\
+									cam_mphys( (void *)(uintptr_t)(data) ) : (uintptr_t)(data)
+
+
+#define cam_clear_ccb(_x)			( memset( ((char *)(_x)) +							\
+									offsetof(struct ccb_header, cam_func_code), 0x00,	\
+									(_x)->cam_ch.cam_ccb_len -							\
+									offsetof(struct ccb_header, cam_func_code)) )
+
+void cam_set_sense(CCB *, void *);
+#define cam_set_sense(ccb, sense)	( ((CCB_SCSIIO *)(ccb))->cam_sense_ptr =	\
+									(unsigned char *)(sense),				\
+									(((CCB_SCSIIO *)(ccb))->cam_sense_len =	\
+									sizeof(*(sense))) )
+
+void cam_target( CCB_SCSIIO *, DEVEXT * );
+#define cam_target( ccb, dext )		( (ccb)->cam_ch.cam_path_id		= (dext)->path_id,	\
+									  (ccb)->cam_ch.cam_target_id	= (dext)->target,	\
+									  (ccb)->cam_ch.cam_target_lun	= (dext)->lun,		\
+									  (ccb)->cam_vu_flags			= CAM_VUF_OTHER )
+
+typedef struct _cam_entry CAM_ENTRY;
+
+typedef struct _cam_entry {
+	int		nfuncs;
+	int		(*scsi_scan_bus)( int path );
+	int		(*scsi_scan_devs)( int type, int (*func)( CCB_PATHINQ *, CCB_GETDEV *));
+	int		(*scsi_setasync_cb)( ASYNC_INFO **alist, CCB_SETASYNC *ccb );
+	void	*(*scsi_ccb_alloc)(void);
+	void	(*scsi_ccb_free)(CCB *);
+	void	*(*scsi_malloc)( int size, int mapf );
+	void	(*scsi_free)( void *addr, int size );
+	DEVOBJ	*(*scsi_create_device)( CCB_PATHINQ *ccb_path, CCB_GETDEV *ccb_gd, int ext_size, int max_io );
+	int		(*scsi_io)( void *hdl, ioreq_t *ioreq );
+	int		(*scsi_abort)( void *hdl, ioreq_t *ioreq, unsigned flags );
+	int		(*scsi_devctl)(void *hdl, resmgr_context_t *ctp, int ioflag, ioreq_t *tag, unsigned dcmd, void *data, size_t size, int *ret );
+	int		(*scsi_iomsg)( void *hdl, resmgr_context_t *ctp, int ioflag, ioreq_t *tag, io_msg_t *msg );
+	int		(*scsi_interpret_sense)( DEVOBJ *dobj, CCB_SCSIIO *ccb, int *status, int rcount );
+
+	int		(*scsi_action)( DEVOBJ *dobj, CCB_SCSIIO *ccb );
+	int		(*scsi_action_wait)( DEVOBJ *dobj, CCB_SCSIIO *ccb, int retries );
+	int		(*scsi_release_simq)( DEVOBJ *dobj );
+	int		(*scsi_read_capacity)( DEVOBJ *dobj );
+	int		(*scsi_mode_sense)( DEVOBJ *dobj, int page, char *mdata, int len );
+	int		(*scsi_mode_select)( DEVOBJ *dobj, char *pdata, int len, int save );
+	void	*(*scsi_mode_page)( char *msdata, int page, int len, int type );
+	int		(*scsi_reserve)( DEVOBJ *dobj );
+	int		(*scsi_release)( DEVOBJ *dobj );
+	int		(*scsi_prevent)( DEVOBJ *dobj, int prevent );
+	int		(*scsi_synchronize_cache)( DEVOBJ *dobj, baddr_t *lba );
+	int		(*scsi_set_timeout)( DEVOBJ *dobj, int g1, int g2, int g3 );
+} cam_entry_t;
+
+#define _CAM_ENTRY_NFUNCS	((sizeof(cam_entry_t) - offsetof(cam_entry_t, scsi_scan_bus)) / sizeof(void *))
+
+#define SRB_FLG_BOUNCE		0x01		// bounce data to/from cache blocks
+#define SRB_FLG_CACHE		0x02		// cache needs to be flushed/invalidated
+struct _scsi_req_block {
+	DEVOBJ			*dobj;
+	ioreq_t			*ioreq;
+ 	CCB_SCSIIO		ccb;
+	int				flags;
+	int				nblks;
+	mdl_t			*mdl;
+
+	mdl_t			*mdl_nxt;
+	int				mdl_off;		// current mdl offset
+	int				mdl_noff;		// next mdl offset
+
+	unsigned		rcount;			// retry count
+	unsigned		b_blkoff;		// block offset in ioreq
+	SG_ELEM			*sg_list;
+	SCSI_SENSE		sense;
+	ioreq_t			bioreq;
+	mdl_t			bmdl;
+	int				bmd_size;
+	void			*bmd_vaddr;
+};
+
+// This extension structure is specific to each peripheral driver.
+// Peripheral drivers that use blkio can use the following structure.
+struct _peripheral_driver_extension {
+	PDRVR					*pdrv;
+	char					*prefix;
+	uint8_t					*async_buffer;	// requires 22 bytes for AEN
+	const io_entry_t		*io_funcs;
+	cam_entry_t				*cam_funcs;
+	void					*dll;			// io-blk dll handle
+	int						dcount;			// device count
+	int						argc;
+	char					**argv;
+	int						rsvd[4];
+};
+
+// This structure is common to all peripheral drivers.  It must
+// contain at least the following members at the start of the
+// structure.
+struct _pdrvr
+{
+	PDRVR_EXT				*pext;
+	TAILQ_HEAD(,_devobj)	dlist;			// linked list of devices
+	int						pflags;			// various flags
+	int						rsvd[4];
+};
+#define PDRVR_FLG_MEDIA_CHECK		0x01
+
+struct _devobj {
+	PDRVR					*pdrvr;			// pointer to peripheral driver
+	TAILQ_ENTRY(_devobj)	dlink;			// pointer to next device
+	void					*dext;			// device extension
+	void					*dentry;
+	int						verbosity;
+	int						vflags;
+	int						rsvd[3];
+};
+
+// This structure may be different for each peripheral type.
+// Devices that require io-blk can use the following structure.
+// Note:  Device extenstions must include at least the common
+// members at the start of the structure.
+#define DEXT_EFLG_INITIALIZING		0x01
+#define DEXT_EFLG_NOSYNC			0x02	// don't enable sync/wide transfers
+#define DEXT_EFLG_NOBIOS			0x04	// don't use BIOS for translation
+#define DEXT_EFLG_NOPTAB			0x08	// don't use partition table for translation
+#define DEXT_EFLG_TP_SUP			0x20	// timeout and protect mode page support
+#define DEXT_EFLG_GET_EVENT_SUP		0x40    // get event/status notification
+#define DEXT_EFLG_BUS_RESET			0x80
+#define DEXT_EFLG_MP_FLEX_DSK_SUP	0x100	// mode sense flexible page support
+#define DEXT_EFLG_NO_FLUSH			0x200
+#define DEXT_EFLG_VERIFY			0x400
+#define DEXT_EFLG_VERIFY_BYTCHK		0x800
+#define DEXT_EFLG_TRIM_SUP			0x1000
+#define DEXT_EFLG_RDCAP16_SUP		0x2000
+#define DEXT_EFLG_TRIM_UNMAP		0x4000
+
+struct _devobj_extension {
+	DEVOBJ					*dobj;			// Device object
+	void					*mext;			// Model extension
+	void					*mentry;		// Model extension
+	int						eflags;			// extension flags
+	path_id_t				path_id;		// Cam path id to device
+	target_id_t				target;			// SCSI target id of device
+	lun_id_t				lun;			// SCSI logical unit number
+	int						dtype;			// Peripherial Device Type
+	int						dflags;			// Device flags ie read only, no media
+	int						cflags;			// CAM flags ie CAM_DIS_DISCONNECT, CAM_DIS_SYNC
+	int						mflags;			// Memory allocation flags
+	uint64_t				paddr_msk;		// paddr msk used to determine bounce buffer usage
+											// (derived from hc_paddr_msk, bounce buffer command line, memory attributes)
+
+#define CAM_G1_TIMEOUT_DFLT		60
+#define CAM_G2_TIMEOUT_DFLT		90
+#define CAM_G3_TIMEOUT_DFLT		10
+#define CAM_RW_TIMEOUT_DFLT		10
+	int						g1_timeout;		// Current group 1 timeout (in seconds)
+	int						g2_timeout;		// Current group 2 timeout (in seconds)
+	int						g3_timeout;		// Current group 3 timeout (in seconds)
+	int						rw_timeout;		// read/write timeout
+
+	int						max_sg;			// Maximum scatter/gather hba can handle
+	int						max_io_blks;	// Maximum blocks device can handle (Obsolete)
+	int						max_active;		// Maximum number of active srbs
+	int						max_speed;
+
+	int						locks;			// Number of media locks
+	int						media_changes;	// Number of media changes
+	int						retries;
+	int						starvation;
+
+	ioque_t					queue;			// Request queue
+	ioque_t					aqueue;			// Active request queue
+	void					*srb_pool;		// IO request pool
+
+	cam_devinfo_t			dinfo;			// Device info (geometry)
+
+	int						(*error)( DEVOBJ *, CCB_SCSIIO *, int *, int * );
+
+	void					*handle;		// handle (ie io-blk handle from mount)
+
+	int						b_shift;
+	int						version;		// Inquiry Version
+	int						max_unmap_lba;
+	int						max_unmap_desc_count;
+	char					*prefix;
+	uint64_t				hc_paddr_msk;	// host cntrl paddr msk (derived from CAM_VUHBA_EFLAG_DMA_XXX)
+
+	uint32_t				max_io_rd;		// Maximum read blocks device can handle
+	uint32_t				max_io_wr;		// Maximum write blocks device can handle
+};
+
+typedef struct _device_defect {
+	char		*product_id;				// product and vendor ids
+#define DEFECT_FLG_TAGGED		0x20U	// disable tagged queuing
+#define DEFECT_FLG_SYNC			0x10U	// disable synchronous transfers
+#define DEFECT_FLG_DISC			0x08U	// disable disconnect
+#define DEFECT_FLG_WCE			0x04U	// disable write cache
+#define DEFECT_FLG_LUN			0x02U	// disable LUN scan
+#define DEFECT_FLG_AUTO_SRP		0x01U	// disable auto save/restore
+	uint32_t	dflags;					// defect flags
+} DEVICE_DEFECT;
+
+int		scsi_init( void );
+int		scsi_dinit( void );
+CCB		*scsi_ccb_alloc( void );
+void	scsi_ccb_free( CCB *ccb );
+int		scsi_scan_devs( int type, int (*func)( CCB_PATHINQ *, CCB_GETDEV *) );
+int		scsi_scan_bus( int path );
+int		scsi_setasync_cb( ASYNC_INFO **alist, CCB_SETASYNC *ccb );
+void	*scsi_malloc( int size, int mapf );
+void	scsi_free( void *addr, int size );
+int		scsi_io( void *hdl, ioreq_t *ioreq );
+int		scsi_iomsg( void *hdl, resmgr_context_t *ctp, int ioflag, ioreq_t *tag, io_msg_t *msg );
+int		scsi_abort( void *hdl, ioreq_t *ioreq, unsigned flags );
+int		scsi_devctl( void *hdl, resmgr_context_t *ctp, int ioflag, ioreq_t *tag, unsigned dcmd, void *data, size_t size, int *ret );
+int		scsi_action( DEVOBJ *dobj, CCB_SCSIIO *ccb );
+int		scsi_action_wait( DEVOBJ *dobj, CCB_SCSIIO *ccb, int rcount );
+int		scsi_release_simq( DEVOBJ *dobj );
+int		scsi_read_capacity( DEVOBJ *dobj );
+int 	scsi_log_sense( DEVOBJ *dobj, int page, char *ldata, int opt, int pc, int parm_ptr, int len );
+int		scsi_log_select( DEVOBJ *dobj, char *pdata, int len, int pc, int opt );
+int		scsi_mode_sense( DEVOBJ *dobj, int page, char *mdata, int len );
+int		scsi_mode_select( DEVOBJ *dobj, char *pdata, int len, int save );
+void	*scsi_mode_page( char *msdata, int page, int len, int type );
+int		scsi_reserve( DEVOBJ *dobj );
+int		scsi_release( DEVOBJ *dobj );
+int		scsi_synchronize_cache( DEVOBJ *dobj, baddr_t *r_lba );
+int		scsi_test_ready( DEVOBJ *dobj );
+int		scsi_error( DEVOBJ *dobj, CCB_SCSIIO *ccb, int *status, int rcount );
+int		scsi_interpret_sense( DEVOBJ *dobj, CCB_SCSIIO *ccb, int *status, int rcount );
+int		scsi_inquiry( DEVOBJ *dobj, int opt, int pc, void *inq, int inq_len );
+int		scsi_unit_ready( DEVOBJ *dobj );
+int		scsi_removal( DEVOBJ *dobj, int prevent );
+DEVOBJ	*scsi_create_device( CCB_PATHINQ *ccb_path, CCB_GETDEV *ccb_gd, int ext_size, int max_io );
+int		scsi_set_timeout( DEVOBJ *dobj, int g1, int g2, int g3 );
+int		scsi_destroy_device( DEVOBJ *dobj );
+int		scsi_negotiate( DEVOBJ *dobj );
+int		scsi_sense_data( void *sdata, int *error, int *key, int *asc, int *ascq );
+void	scsi_display_ccb( CCB *ccb_ptr, int verbosity );
+void	scsi_action_wait_cbf( CCB_SCSIIO *ccb );
+paddr64_t scsi_mphys( void *vaddr );
+void	* scsi_virt( paddr64_t paddr );
+void	*_scsi_malloc( int size, uint32_t protf, uint32_t mapf );
+IO_VU_DATA	*scsi_ccb_vdata( CCB *vccb );
+
+const char *typetostr( int type );
+
+ssize_t __attribute__((__format__(__printf__, 5, 6))) cam_slogf( int opcode, int severity, int verbosity, int vlevel, const char *fmt, ... );
+void	cam_strip_spaces( char *src, char *dst, int len );
+void	cam_dump( char *buffer, int cnt );
+int		cam_parse_size( const char *str );
+int		cam_parse_number( const char *str );
+int64_t	cam_parse_number64( const char *str );
+int		cam_strtol( const char *str, char **cp );
+int64_t	cam_strtoll( const char *str, char **cp );
+int		cam_parse_tuple( char *string, char separator, char **entry, ... );
+int		cam_device_opt( path_id_t path, target_id_t target, lun_id_t lun, char *value );
+char	*cam_module_args( int argc, char *argv[], char *mname );
+int		cam_blk_shift( unsigned blen );
+int		cam_pdrvr_options( PDRVR_EXT *pext, DEVOBJ *dobj, char *options );
+int		cam_set_thread_state( uint32_t *tstate, int state );
+int		cam_create_thread( pthread_t *tid, pthread_attr_t *aattr, void *(*func)(void *), void *arg, int priority, uint32_t *tstate, char *name );
+
+#ifdef CAM_MEM_DEBUG
+extern void _cam_free( void *p, char *f, int l );
+extern void *_cam_calloc( size_t n, size_t sz, char *f, int l );
+extern void *_cam_realloc( void *p, size_t sz, char *f, int l );
+
+#define cam_free( _p )			_cam_free( (_p), __FILE__, __LINE__ )
+#define cam_calloc( _n, _sz )	_cam_calloc( (_n), (_sz), __FILE__, __LINE__ )
+#define cam_realloc( _p, _sz )	_cam_realloc( (_p), (_sz), __FILE__, __LINE__ )
+#else
+#define cam_free	(free)
+#define cam_calloc	(calloc)
+#define cam_realloc	(realloc)
+
+#endif
+
+int cam_configure( const MODULE_ENTRY *sim_entry, int nsims, int argc, char *argv[] );
+
+int xpt_configure( const MODULE_ENTRY *sim_entry, int nsims, int argc, char *argv[] );
+
+int dll_pdrvr_init( cam_entry_t *cfuncs, int argc, char *argv[] );
+
+void *scsi_start_resmgr( DEVEXT *dext );
+int scsi_destroy_resmgr( void *hdl );
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/include/ntocam.h $ $Rev: 982571 $")
+#endif
+

src/hardware/devb/include/sim.h

@@ -0,0 +1,376 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at  
+ * http://licensing.qnx.com/license-guide/ for other information. 
+ * $ 
+ */
+
+#ifndef SIM_H_INCLUDED
+#define SIM_H_INCLUDED
+
+#include <pthread.h>
+#include <sys/queue.h>
+#include <sys/resmgr.h>
+#include <sys/syspage.h>
+
+#include <cam.h>
+
+// Useful TAILQ manifests possibly not in sys/queue.h
+#ifndef TAILQ_EMPTY
+	#define	TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
+#endif
+#ifndef TAILQ_FIRST
+	#define	TAILQ_FIRST(head) ((head)->tqh_first)
+#endif
+#ifndef TAILQ_LAST
+	#define	TAILQ_LAST(head) ((head)->tqh_last)
+#endif
+#ifndef TAILQ_NEXT
+	#define	TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
+#endif
+#ifndef TAILQ_PREV
+	#define TAILQ_PREV(elm, field) ((elm)->field.tqe_prev)
+#endif
+
+typedef struct _sim_hba_stats		SIM_HBA_STATS;
+typedef struct _sim_hba_extension	SIM_HBA_EXT;
+typedef struct _sim_hba				SIM_HBA;
+
+// NOTES:
+//
+//  An initiator may not mix the use of tagged and untagged queuing for I/O
+//  processes to a logical unit, except during a contingent allegiance or
+//  extended contingent allegiance condition when only untagged initial
+//  connections are allowed.
+//
+//  If the disconnect privilege is not granted in the IDENTIFY message for
+//  a tagged I/O process, the target will return BUSY status.
+//
+//  A series of linked commands constitue a single I/O process.  These
+//  commands are assigned the queue tag established in the initial
+//  connection.
+//
+//  The cam_status is | with CAM_SIM_QFRZN.
+
+// state defines
+#define SIM_CCB_READY			0x0000		// CCB is not active
+#define SIM_CCB_NEXUS			0x0001		// CCB has been dequeued/started
+#define SIM_CCB_ARB				0x0002		// CCB is currently arbitrating
+#define SIM_CCB_SEL				0x0004		// CCB is currently selecting
+#define SIM_CCB_CMD				0x0008		// CCB is in command in phase
+#define SIM_CCB_MSGI			0x0010		// CCB is in message in phase
+#define SIM_CCB_MSGO			0x0020		// CCB is in message out phase
+#define SIM_CCB_DIN				0x0040		// CCB is in data in phase
+#define SIM_CCB_DOUT			0x0080		// CCB is in data out phase
+#define SIM_CCB_STAT			0x0100		// CCB is in status phase
+#define SIM_CCB_DISC			0x0200		// CCB is disconnected
+#define SIM_CCB_DONE			0x0400		// CCB has completed
+#define SIM_CCB_ABORT			0x8000		// CCB is to be aborted
+#define SIM_CCB_RESET			0x4000		// CCB is to be aborted
+#define SIM_CCB_MASK			0x3fff		// CCB state mask
+#define SIM_CCB_QUERY			0xFFFF		// Query ccb state
+
+typedef struct sim_lun_queue {
+	_uint32					frzn_cnt;
+	TAILQ_HEAD(sim_ccb_tq,ccb_scsiio)			clist;	// linked list of ccbs
+	TAILQ_HEAD(sim_active_ccb_tq,ccb_scsiio)	alist;	// linked list of active ccbs (nexus)
+	_uint32					ltag_id;					// last tag id given out
+	_uint32					tag;						// count of active tagged ccbs
+	_uint32					nontag;						// count of active non tagged ccbs
+	_uint32					max_tagged;					// maximum tagged per lun
+} SIM_LUN_QUEUE;
+
+typedef struct sim_target_queue {
+	SIM_LUN_QUEUE		*lque;				// array of lun queues
+} SIM_TARGET_QUEUE;
+
+typedef struct sim_queue {
+	pthread_mutex_t		mutex;				// sim queue mutex
+	timer_t				timerid;			// timer id
+	_uint32				ntargs;				// number of targets
+	_uint32				nluns;				// number of logical units
+	_uint32				max_tagged;			// maximum tagged per lun
+	_uint32				max_non_tagged;		// maximum non tagged per lun
+	_uint32				mactive;			// maximum active ccbs
+	_uint32				actcnt;				// number of active ccbs
+	_uint32				qcnt;				// number of ccbs queued
+	_uint32				tindx;				// used for round-robin scheduling
+	_uint32				lindx;				// used for round-robin scheduling
+	_uint32				timeout;
+	SIM_HBA 			*hba;				// pointer to hba structure
+	SIM_TARGET_QUEUE	*tque;				// variable length array of targets
+	struct qtime_entry	*systime;			// fast access to current time
+} SIM_QUEUE;
+
+// This structure must be the first entry in the private data
+typedef struct sim_que_data {
+	TAILQ_ENTRY(ccb_scsiio)	clink;			// tailq entry for prev/next ccb
+	_uint16					state;			// SCSI state of ccb
+	_uint8					rsvd;
+	_uint8					tag_id;			// tag id for this ccb
+	_uint32					timeout;		// timeout
+} SIMQ_DATA;
+
+#define SIMQ_TIMER_DISABLE	0x00
+#define SIMQ_TIMER_ENABLE	0x01
+
+#define SIM_TIME_DEFAULT	0x02			// default to a 2 second timeout
+
+#define SIM_TAG_INVALID		0xff
+
+#define SIM_ENQUEUE			0x01
+#define SIM_INTERRUPT		0x02
+#define SIM_TIMER			0x03
+#define SIM_DRVR_TIMER		0x04
+#define SIM_DMA_INTERRUPT	0x05
+#define SIM_RESET			0x06
+
+#define SIM_PRIORITY		21
+
+#define HBA_FLAG_NORESET			0x0001
+#define HBA_FLAG_NOPARITY			0x0002
+#define HBA_FLAG_TERMLO				0x0004
+#define HBA_FLAG_TERMHI				0x0008
+#define HBA_FLAG_SCAM				0x0010
+
+#define HBA_FLAG_ACCESS8			0x0020
+#define HBA_FLAG_ACCESS16			0x0040
+#define HBA_FLAG_ACCESS32			0x0080
+
+#define HBA_STATE_FAILURE			0x01
+#define HBA_STATE_INITIALIZING		0x02
+#define HBA_STATE_INITIALIZED		0x04
+#define HBA_STATE_RESETING			0x08
+#define HBA_STATE_EXPECT_INTR		0x10
+
+struct _sim_hba_stats {
+	_uint32				stat_irqs;
+	_uint32				stat_timeouts;
+	_uint32				stat_selections;
+	_uint32				stat_disconnects;
+	_uint32				stat_reselections;
+	_uint32				stat_bus_resets;
+	_uint8				rsvd[36];
+};
+
+// sim extentions must include the following members
+struct _sim_hba_extension {
+	SIM_HBA				*hba;
+	_uint32				eflags;
+};
+
+#define ISADEVICE		0x00000001
+#define EISADEVICE		0x00000002
+#define PCIDEVICE		0x00000004
+#define PCMCIADEVICE	0x00000008
+#define PNPISADEVICE	0x00000010
+#define MCADEVICE		0x00000020
+
+typedef struct _sim_device_id
+{
+	_uint32	BusID;		/* bus type, 0 is undefined */
+	_uint32	DevID;		/* physical device ID, 0xffffffff is undefined */
+	_uint32	CompID;		/* compatibility ID */
+	_uint32	SerialNum;	/* device instance or serial number, 0 is undefined */
+	_uint32	LogicalID;	/* Logical device ID for Plug and Play ISA, Class code for */
+						/* PCI, 0xffffffff is undefined */
+	_uint32	Flags;		/* Bit 0: device has been intialized (1) */
+						/* Bit 1: device is enabled (1) */
+						/* Bit 2: device config has been locked (1) */
+						/* Bit 3: device has temporary config resources assigned (1) */
+						/* Bit 4: device is re-configurable (1) */
+						/* Bit 31: device id is a QNX defined ID */
+} SIM_DEVICE_ID;
+
+typedef union _sim_bus_access
+{
+	struct	PCIAccess {
+		_uint8 	BusNumber;			/* Bus number 0-255 */
+		_uint8 	DevFuncNumber;		/* Device (bits 7:3) and function (in bits 2:0) IDs */
+		_uint16 PCIreserved;			
+	} PCIAccess;
+	struct	EISAAccess {
+		_uint8 	SlotNumber;			/* Card slot number */
+		_uint8	FunctionNumber;		/* (E)ISA sub-function number on multi function card */
+		_uint16	EISAreserved;		
+	} EISAAccess;
+	struct	PnPAccess {
+		_uint8 	CSN;				/* Card slot number determined during ISA isolation */
+		_uint8	LogicalDevNumber;	/* Logical device number */
+		_uint16	Read_data_port;		/* Read data I/O port determined during ISA isolation */
+	} PnPAccess;
+	struct	PCMCIAAccess {
+		_uint16 	LogicalSocket;		/* Card logical socket # */
+		_uint16 	PCMCIAReserved1;	/* Reserved */
+	} PCMCIAAccess;
+} SIM_BUS_ACCESS;
+
+#define	SIM_MAX_MEM_REGISTERS		6
+#define	SIM_MAX_IO_PORTS			6
+#define	SIM_MAX_IRQS				6
+#define	SIM_MAX_DMA_CHANNELS		6
+
+typedef struct _sim_config_info {
+	SIM_DEVICE_ID	Device_ID;							/* Device ID information */
+	SIM_BUS_ACCESS	BusAccess;							/* Info to allow config. access */
+
+	_uint32			NumMemWindows;						/* Num memory windows */
+	_uint64			MemBase[SIM_MAX_MEM_REGISTERS];  	/* Memory window base */
+	_uint32			MemLength[SIM_MAX_MEM_REGISTERS];	/* Memory window length */
+	_uint32			MemAttrib[SIM_MAX_MEM_REGISTERS];	/* Memory window Attrib */
+
+	_uint64			IOPort_Base[SIM_MAX_IO_PORTS];		/* I/O port base */
+	_uint32			IOPort_Length[SIM_MAX_IO_PORTS];	/* I/O port length */
+	_uint32			NumIOPorts;							/* Num IO ports */
+
+	_uint32			NumIRQs;							/* Num IRQ info */
+	_uint32			IRQRegisters[SIM_MAX_IRQS];			/* IRQ list */
+	_uint32			IRQAttrib[SIM_MAX_IRQS];			/* IRQ Attrib list */
+
+	_uint32			NumDMAs;							/* Num DMA channels */
+	_uint32			DMALst[SIM_MAX_DMA_CHANNELS];	 	/* DMA list */
+	_uint32			DMAAttrib[SIM_MAX_DMA_CHANNELS];	/* DMA Attrib list */
+
+	char			Description[40];					/* Device specific desc */
+	_uint8			Reserved1[16];						/* Reserved */
+} SIM_CONFIG_INFO;
+
+/* IO attributes */
+#define ATTR_IO_EXCL				0x00
+#define ATTR_IO_SHARED				0x01
+
+/* Memory Range Attributes */
+#define ATTR_MEM_RANGE_DECODE		0x01	/* Use memory range length for decoding */
+#define ATTR_MEM_8_BIT				0x00	/* 8-bit memory */
+#define ATTR_MEM_16_BIT				0x02	/* 16-bit memory */
+#define ATTR_MEM_8_16_BIT			0x04	/* 8 and 16-bit memory */
+#define ATTR_MEM_32_BIT				0x00	/* 32-bit memory */
+#define ATTR_MEM_16_32_BIT			0x08	/* 16 and 32-bit memory */
+#define ATTR_MEM_ROM				0x00	/* Read Only (ROM) */
+#define ATTR_MEM_RAM				0x20	/* Read/Write (RAM) */
+#define ATTR_MEM_SHARED				0x40	/* Shared Memory */
+
+/* IRQ Attributes */
+#define ATTR_IRQ_EDGE_TRIGGERED		0x00	/* Edge Triggered */
+#define ATTR_IRQ_LEVEL_TRIGGERED	0x01	/* Level Triggered */
+#define ATTR_IRQ_LEVEL_LOW			0x00	/* Level Low */
+#define ATTR_IRQ_LEVEL_HIGH			0x02	/* Level High */
+#define ATTR_IRQ_SHARED				0x04	/* Shared */
+
+#define ATTR_IRQ_DEFAULT			0x80	/* IRQ default */
+
+/* DMA Attributes */
+#define ATTR_DMA_8_BIT				0x0000	/* 8-bit transfers */
+#define ATTR_DMA_8_16_BIT			0x0001	/* 8 and 16-bit transfers */
+#define ATTR_DMA_16_BIT				0x0002	/* 16-bit transfers */
+#define ATTR_DMA_32_BIT				0x0003	/* 32-bit transfers */
+#define ATTR_DMA_BUS_MASTER			0x0004	/* logical device is a bus master */
+#define ATTR_DMA_COUNT_BYTE_MODE	0x0008	/* DMA may execute in count by byte mode */
+#define ATTR_DMA_COUNT_WORD_MODE	0x0010	/* DMA may execute in count by word mode */
+/* DMA channel speed support */
+#define ATTR_DMA_ISA				0x0000	/* ISA compatible timing */
+#define ATTR_DMA_TYPE_A				0x0020	/* type A timing */
+#define ATTR_DMA_TYPE_B				0x0040	/* type B timing */
+#define ATTR_DMA_TYPE_F				0x0060	/* type F timing */
+#define ATTR_DMA_SHARED				0x0100	/* Shared DMA */
+#define ATTR_DMA_TYPE_C				0x0200	/* C type timing supported */
+
+#define ATTR_DMA_DEFAULT			0x8000	/* DMA default */
+
+struct _sim_hba {
+	TAILQ_ENTRY( _sim_hba )	hlink;
+	SIM_HBA_EXT			*ext;
+	SIM_QUEUE			*simq;
+	CAM_ENTRY			*cam_funcs;
+	SIM_CONFIG_INFO		cfg;
+	int					verbosity;
+	_uint32				hflags;				// see HBA_FLAGS_...
+	_uint32				state;				// see HBA_STATE_...
+	int					coid;
+	int					chid;
+	int					iid;
+	pthread_t			tid;				// id of event handling thread
+	void				*dhdl;				// device handle (pci)
+	path_id_t			pathid;
+	int					priority;
+
+	_uint32				rsvd[7];
+
+	_uint8				stride;				// I/O stride
+	_uint8				decode;				// I/O decode
+
+	_uint8				scsiid;
+	_uint8				seltimo;			// selection timeout;
+
+	_uint8				ntargets;
+	_uint8				nluns;
+
+	_uint8				speed;
+	_uint8				rsvd1[3];
+
+	_uint16				nsgelm;				// number of scatter gather elements
+
+	_uint16				tag_mask;
+	_uint16				disc_mask;
+
+	_uint16				sync_mask;
+	_uint16				fast_mask;
+
+	_uint16				wide_mask;
+	_uint16				ultra_mask;
+
+	_uint16				ultra2_mask;
+	_uint16				ultra160_mask;
+
+	_uint16				ultra320_mask;
+	_uint16				ultra640_mask;
+
+	_uint32				timeout;			// command completion timeout
+	_uint32				rst_settle;			// reset settle time
+	SIM_HBA_STATS		stats;
+};
+
+int simq_ccb_enqueue( SIM_QUEUE *simq, CCB_SCSIIO *ccb );
+CCB_SCSIIO *simq_ccb_dequeue( SIM_QUEUE *simq );
+CCB_SCSIIO *simq_ccb_locate( SIM_QUEUE *simq, target_id_t target, lun_id_t lun, int tag );
+SIM_QUEUE *simq_init( int coid, void *hba, int ntargs, int nluns, int max_non_tagged, int max_tagged, int mactive, int timeout );
+int simq_dinit( SIM_QUEUE *simq );
+void simq_set_qdepth( SIM_QUEUE *simq, target_id_t target, lun_id_t lun, int qdepth );
+void simq_set_max_tag( SIM_QUEUE *simq, target_id_t target, lun_id_t lun, int mtag );
+int simq_get_tag( CCB_SCSIIO *ccb );
+int simq_ccb_state( CCB_SCSIIO *ccb, int state );
+void simq_post_ccb( SIM_QUEUE *simq, CCB_SCSIIO *ccb );
+void simq_scsi_reset( SIM_QUEUE *simq );
+void simq_reset_bus( SIM_QUEUE *simq, CCB_RESETBUS *ccb );
+void simq_reset_dev( SIM_QUEUE *simq, CCB_RESETDEV *ccb );
+int simq_ccb_abort( SIM_QUEUE *simq, CCB_ABORT *ccb );
+int simq_rel_simq( SIM_QUEUE *simq, CCB_RELSIM *ccb );
+int simq_frz_simq( SIM_QUEUE *simq, CCB_FRZSIM *ccb );
+int simq_timer_settime( SIM_QUEUE *simq, int seconds );
+void simq_clock_gettime( SIM_QUEUE *simq, struct timespec *ts );
+
+SIM_HBA *sim_alloc_hba( int ext_size );
+void sim_free_hba( SIM_HBA *sim );
+int sim_drvr_options( SIM_HBA *sim, char *options );
+int sim_display_config( SIM_HBA *sim );
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/include/sim.h $ $Rev: 982571 $")
+#endif

src/hardware/devb/include/xpt.h

@@ -0,0 +1,350 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at  
+ * http://licensing.qnx.com/license-guide/ for other information. 
+ * $ 
+ */
+
+// This is for all the transport layer prototypes and defines
+
+#ifndef __XPT_H_INCLUDED
+#define __XPT_H_INCLUDED
+
+#include <cam.h>
+#include <module.h>
+#include <sys/cache.h>
+#include <sys/resmgr.h>
+
+struct _sim_hba;
+
+#define XPT_XFLAG_BOUNCE				0x0001
+#define XPT_XFLAG_CACHE					0x0002
+#define XPT_XFLAG_VERIFY				0x0004
+#define XPT_XFLAG_VERIFY_BYTCHK			0x0008
+#define XPT_XFLAG_PNP					0x0010
+#define XPT_XFLAG_ENUMERATING			0x0020
+#define XPT_XFLAG_MATTR_SNOOPED			0x0040
+#define XPT_XFLAG_RESMGR				0x0080
+#define XPT_XFLAG_DISP_CCB_INTERNAL		0x0100
+#define XPT_XFLAG_DISP_CCB_EXTERNAL		0x0200
+#define XPT_XFLAG_IO_DONE				0x0400
+#define XPT_XFLAG_COALESCE				0x0800
+#define XPT_XFLAG_ASYNC					0x01000
+#define XPT_XFLAG_IO					0x02000
+#define XPT_XFLAG_IO_PRIV				0x04000
+#define XPT_XFLAG_SMMU					0x08000
+#define XPT_XFLAG_SMMU_EXT				0x10000		// external smmu ie usb stack
+
+#define XPT_MAX_20BIT_ADDR				0xfffffUL
+#define XPT_MAX_24BIT_ADDR				0xffffffUL
+#define XPT_MAX_32BIT_ADDR				0xffffffffUL
+
+#define XPT_MEM_FREE_SIZE_THRES			8192
+#define XPT_MEM_POOL_HIWATER			4
+
+#define XPT_TYPED_MEM_DFLT				"sysram&below4G"
+
+#define XPT_PRIORITY					21
+
+struct _cam_smmu_map;
+
+typedef struct _xpt_mlist	XPT_MEM_LIST;
+
+TAILQ_HEAD(_xpt_mlist,_xpt_mem_hdr);
+
+typedef struct _xpt_mem_hdr {
+	TAILQ_ENTRY(_xpt_mem_hdr)	hlink;
+	int							mfd;
+	int							size;
+	int							mapf;
+	int							protf;
+	void						*vaddr;
+	paddr64_t					paddr;
+} XPT_MEM_HDR;
+
+typedef struct _xpt_mem {
+	int							vfd;			// virtual alloc fd
+	int							cfd;			// contig alloc fd
+	int							flags;
+	int							thres;
+	int							hiwater;
+	int							flist_cnt;
+	XPT_MEM_LIST				flist;
+	XPT_MEM_LIST				ulist;
+	pthread_mutex_t				mutex;
+	uint64_t					min_paddr;
+	uint64_t					max_paddr;
+	uint64_t					align_paddr;
+} XPT_MEM;
+
+typedef struct _xpt {
+	uint32_t			xflags;
+	int					verbosity;
+	uint32_t			vflags;
+	uint32_t			lun_scan;
+	uint32_t			xpt_max_ccb;
+	uint32_t			xpt_max_edt;
+	path_id_t			xpt_max_path;
+	path_id_t			xpt_last_path;
+	pthread_mutex_t		mutex;
+	CCB_HEADER			*xpt_ccb_list;
+	CAM_SIM_ENTRY		**cam_conftbl;
+	CAM_EDT_ENTRY		*cam_edt;
+	CAM_EDT_ENTRY		**cam_map;
+	ASYNC_INFO			*async;				// XPT async callback list
+
+	char				**argv;
+	uint32_t			argc;
+
+	uint32_t			nsims;
+	const MODULE_ENTRY	*sim_module;
+
+	void				**sim_data;
+	struct cache_ctrl	cachectl;
+	int					pagesize;
+	int					bounce_size;
+	paddr64_t			max_paddr;
+	uint32_t			retries;
+	dev_t				devno; 
+	uint32_t			rsmgr_lo_water;
+	uint32_t			rsmgr_hi_water;
+	uint32_t			rsmgr_maximum;
+	int					g1_timeout;		// default group 1 timeout (in seconds)
+	int					g2_timeout;		// default group 2 timeout (in seconds)
+	int					g3_timeout;		// default group 3 timeout (in seconds)
+	int					rw_timeout;		// default read/write timeout (in seconds)
+
+	uid_t				uid;
+	gid_t				gid;
+	int					chid;
+	int					coid;
+	int					tid;				// thread id
+	char				*user;
+	XPT_MEM				mem;
+
+	void				*ioblk_dll;
+	struct _io_entry	*ioblk_funcs;
+
+	uint32_t			max_io_rd;
+	uint32_t			max_io_wr;
+
+	int					priority;
+
+	int					rsvd[9];
+} XPT;
+
+// QNX specific cam_vu_flags in CCB_SCSIIO
+#define CAM_VUF_RW                  0x01    /* flag says read/write ccb */
+#define CAM_VUF_DIO                 0x02    /* flag says direct I/O ccb */
+#define CAM_VUF_PTHRU               0x04    /* flag says pass through ccb */
+#define CAM_VUF_OTHER               0x08    /* flag says internal ccb */
+#define CAM_VUF_SIM                 0x10    /* flag says internal SIM ccb */
+#define CAM_VUF_VDATA               0x20    /* flag says vendor data valid (call xpt_ccb_vdata) */
+#define CAM_VUF_RETRY               0x80
+
+// QNX specific cam_vuhba_flags in CCB_PATHINQ (14 bytes)
+#define CAM_VUHBA_MAX_VAL			0xff
+
+#define CAM_VUHBA_FLAGS				0		/* offset for flags */
+#define CAM_VUHBA_FLAG_PHYS			0x01	/* flag says physical address supported */
+#define CAM_VUHBA_FLAG_PTR			0x02	/* flag says ptr address is suported */
+#define CAM_VUHBA_FLAG_DMA			0x04	/* flag says HBA uses DMA for transfering */
+#define CAM_VUHBA_FLAG_DMA_LOW		0x08	/* flag says HBA uses ISA DMA for transfering */
+#define CAM_VUHBA_FLAG_DMA_NOX64K	0x10	/* flag says HBA can't handle X 64K buffers */
+#define CAM_VUHBA_FLAG_ATAPI		0x20	/* flag says HBA is an ATAPI device ( use 10 byte commands ) */
+#define CAM_VUHBA_FLAG_BMSTR		0x40	/* flag says HBA busmasters */
+#define CAM_VUHBA_FLAG_MLUN         0x80    /* flag says HBA can handle multi-lun devices */
+#define CAM_VUHBA_EFLAGS			1		/* offset for extended flags */
+#define CAM_VUHBA_EFLAG_PNP			0x01	/* flag says plug and play driver */
+#define CAM_VUHBA_EFLAG_DMA_20		0x02	/* flag says HBA supports 20 Bit physical addresses */
+#define CAM_VUHBA_EFLAG_DMA_24		0x04	/* flag says HBA supports 24 Bit physical addresses */
+#define CAM_VUHBA_EFLAG_DMA_32		0x08	/* flag says HBA supports 32 Bit physical addresses */
+#define CAM_VUHBA_EFLAG_DMA_64		0x10	/* flag says HBA supports 64 Bit physical addresses */
+#define CAM_VUHBA_EFLAG_DEVNAME		0x20	/* flag says set device name using INQ vend_spc */
+#define CAM_VUHBA_EFLAG_SG_2N		0x40	/* flag says MAX_SG in 2^N format */
+#define CAM_VUHBA_EFLAG_QD_2N		0x80	/* flag says QDEPTH field in 2^N format */
+
+#define CAM_VUHBA_MAX_SG			2		/* Maximun # of sg elements on this path */
+#define CAM_VUHBA_MAX_LINKED		3		/* Maximun # of linked in a chain 0=unlimited */
+#define CAM_VUHBA_HEADS				4		/* Number of Heads BIOS presents for fdisk disk 0, 0=default */
+#define CAM_VUHBA_HEADS1			5		/* Number of Heads BIOS presents for fdisk disk 1, 0=default */
+#define CAM_VUHBA_SECTS				6		/* Number of Sectors/Trk BIOS presents for fdisk disk 0, 0=default */
+#define CAM_VUHBA_SECTS1			7		/* Number of Sectors/Trk BIOS presents for fdisk disk 1, 0=default */
+#define CAM_VUHBA_MAX_IO			8
+#define CAM_VUHBA_MAX_IO1			9
+#define CAM_VUHBA_QDEPTH			10
+
+
+/*
+ * The SIM calls this routine to inform the XPT that an async event has occured
+ * and that there may be peripheral drivers which need to be informed.
+ *
+ *  - The opcode, path_id, target_id, lun, and data_cnt arguments are 32-bit
+ *    values.
+ *  - The path_id, target_id, and lun define a nexus for the Async Callback.
+ *  - The opcode contains the value for what has happened.
+ *  - The buffer_ptr and data_cnt are used to inform the XPT where and how much
+ *    data is associated with the opcode.
+ */
+void xpt_async(int opcode, path_id_t path_id, target_id_t target_id, lun_id_t lun,
+                            void *buffer_ptr, int data_cnt);
+
+
+/*
+ * The SIM shall call the XPT once for each supported bus in order to obtain the
+ * Path ID for that bus.
+ *
+ * The argument is the pointer for the data structure defining the entry points
+ * for the SIM. The value returned is the assigned Path ID; a value of -1
+ * indicates that registration was not successful.
+ */
+path_id_t xpt_bus_register(CAM_SIM_ENTRY *sim_entry, struct _sim_hba *sim_data);
+
+
+/*
+ * The argument is the Path ID for the bus being de-registered. A return value of
+ * zero indicates the bus is no longer registered, any other value indicates the
+ * call was unsuccessful.
+ */
+int xpt_bus_deregister(path_id_t path);
+
+
+/*
+ * This routine is called by the peripheral driver to request that the XPT and
+ * sub-layers be initialized. Once the sub-layers are initialized any subsequent
+ * calls by other peripheral drivers shall quickly return.
+ *
+ * There are no arguments and the CAM Status is either CAM_SUCCESS of CAM_FAILURE.
+ */
+int xpt_init(void);
+
+
+/*
+ * This routine is used whenever a peripheral driver needs a CCB (the common data
+ * structure for processing SCSI requests). It returns a pointer to the allocated
+ * CCB which the peripheral driver can now use as the CCB for it's SCSI/XPT
+ * requests. The returned CCB shall be properly initialized for use as a SCSI I/O
+ * Request CCB. The SIM Private Data area shall have been already set up to be
+ * used by the XPT and SIM, and shall not be modified by the peripheral driver.
+ *
+ * There are no arguments and the return value is a pointer to an initialized
+ * CCB.
+ */
+void *xpt_ccb_alloc(void);
+
+
+/*
+ * This routine takes a pointer to the CCB that the peripheral driver has
+ * finished with so it can be returned to the CAM subsystem CCB pool.
+ *
+ * The argument is the pointer to the CCB to be freed, there is no CAM Status.
+ */
+void xpt_ccb_free(CCB *freeccb);
+
+/*
+ * This routine returns vendor unique associated data (CCB_SCSIIO cam_vu_flags & CAM_VUF_VDATA)
+ *
+ * The arguments are a pointer to the CCB, and returns a pointer to vdata.
+ */
+IO_VU_DATA	*xpt_ccb_vdata( CCB *ccb );
+
+/*
+ * All CAM/SCSI CCB requests to the XPT/SIM are placed through this function
+ * call. All returned CAM status information is obtained at the callback point
+ * via the CAM and SCSI status fields.
+ *
+ * The argument is a pointer to the CCB, and the CAM Status is either Success or
+ * Failure.
+ */
+int xpt_action(CCB *ccbp);
+
+int xpt_setasync_cb( ASYNC_INFO **alist, CCB_SETASYNC *ccb );
+
+int xpt_scan_bus(int path);
+
+int xpt_scan_devs(int type, int (*func)( CCB_PATHINQ *, CCB_GETDEV *));
+
+CAM_EDT_ENTRY *xpt_nexus( path_id_t path, target_id_t target, lun_id_t lun, int create );
+
+int xpt_smart_cache( void );
+
+/* virtual to physical address translation routines */
+CAM_PM_OFFSET xpt_vtop( CAM_VM_OFFSET addr, CAM_VM_OFFSET cam_map );
+int xpt_vtop_sg( SG_ELEM *vsg, SG_ELEM *psg, int nsg, CAM_VM_OFFSET cam_map );
+
+/* physical to virtual address tranalation */
+CAM_VM_OFFSET xpt_ptov( CAM_PM_OFFSET paddr, CAM_VM_OFFSET cam_map );
+int xpt_ptov_sg( SG_ELEM *psg, SG_ELEM *vsg, int nsg, CAM_VM_OFFSET cam_map );
+
+#define XPT_ALLOC_CONTIG		0x01
+#define XPT_ALLOC_NOCACHE		0x02
+void *xpt_alloc( int aflg, size_t size, paddr64_t *paddr );
+int xpt_free( CAM_VM_OFFSET addr, size_t size );
+
+void xpt_cache_inval( void *vaddr, paddr64_t paddr, size_t count );
+void xpt_cache_flush( void *vaddr, paddr64_t paddr, size_t count );
+
+void xpt_display_ccb( CCB *ccb_ptr, int verbosity );
+
+int xpt_args( int argc, char *argv[] );
+
+#define XPT_SMMU_MAP_INIT( _map, _flgs, _phys, _len )	do {									\
+															(_map)->flags = (_flgs);				\
+															(_map)->nentries = 1;				\
+															(_map)->entries->phys = (_phys);	\
+															(_map)->entries->len = (_len);		\
+														} while(0)
+
+int xpt_smmu_map( struct _cam_smmu_map *map );
+
+#define XPT_PCI_BDF_FUNC(_bdf)		( ( ( (_Uint32t)(_bdf ) ) >> 0 ) & 0x7u )
+#define XPT_PCI_BDF_DEV(_bdf)		( ( ( (_Uint32t)(_bdf) ) >> 3 ) & 0x1Fu )
+#define XPT_PCI_BDF_BUS(_bdf)		( ( ( (_Uint32t)(_bdf) ) >> 8 ) & 0xFFu )
+#define XPT_PCI_BDF(_b, _d, _f)		( (_Uint32t)( ( ( (_b) & 0xFFu ) << 8 ) | ( ( (_d) & 0x1Fu ) << 3 ) | ( ( (_f) & 0x7u) << 0 ) ) )
+
+typedef struct _xpt_device_pci {
+	_Uint32t	type;
+	_Uint32t	bdf;
+} XPT_DEVICE_PCI;
+
+typedef struct _xpt_device_mmio {
+	_Uint32t	type;
+	_Uint32t	rsvd;
+	_Uint64t	phys;
+	_Uint64t	len;
+} XPT_DEVICE_MMIO;
+
+#define XPT_DEVICE_TYPE_PCI		0
+#define XPT_DEVICE_TYPE_MMIO	1
+typedef union _xpt_device {
+	_Uint32t		type;
+	XPT_DEVICE_PCI	pci;
+	XPT_DEVICE_MMIO	mmio;
+	_Uint64t		_rsvd[6];
+} XPT_DEVICE;
+
+typedef void		XPT_DEVICE_EVENT;
+
+int xpt_device_deregister( XPT_DEVICE *dev );
+int xpt_device_register( XPT_DEVICE *dev, unsigned flgs, int (*evcbf)( XPT_DEVICE *dev, XPT_DEVICE_EVENT *ev ) );
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/include/xpt.h $ $Rev: 982571 $")
+#endif

src/hardware/devb/sdmmc/Makefile

@@ -0,0 +1,2 @@
+LIST=CPU
+include recurse.mk

src/hardware/devb/sdmmc/aarch64/Makefile

@@ -0,0 +1,9 @@
+CHECKFORCE=1
+LIST=VARIANT
+ifndef QRECURSE
+QRECURSE=recurse.mk
+ifdef QCONFIG
+QRDIR=$(dir $(QCONFIG))
+endif
+endif
+include $(QRDIR)$(QRECURSE)

src/hardware/devb/sdmmc/aarch64/bcm2711.le/Makefile

@@ -0,0 +1,2 @@
+include ../../extra.mk
+include ../../../common.mk

src/hardware/devb/sdmmc/aarch64/bcm2711.le/bcm2711.use

@@ -0,0 +1,20 @@
+bcm2711 options:
+
+Notes for board-specific options:
+-----------------------------------
+BS Options: All options are separated by colons
+
+'bmstr_base'    : ram base address from busmaster view
+
+
+Example:
+-----------------------------------
+For raspberry pi4:
+
+#SD
+devb-sdmmc-bcm2711 cam pnp,verbose blk rw,cache=2M dos umask=077 mem name=below1G sdio addr=0xfe340000,irq=158,bs=bmstr_base=0xc0000000 disk name=sd
+
+
+
+
+

src/hardware/devb/sdmmc/aarch64/bcm2711.le/bs.c

@@ -0,0 +1,128 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2020 QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+/* Module Description:  board specific interface */
+
+#include <internal.h>
+#include <errno.h>
+#include <string.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <hw/inout.h>
+#include <sys/mman.h>
+#include <drvr/hwinfo.h>
+#include <sdhci.h>
+
+static void bcm2711_get_sdmmc_dma_range(sdio_hc_t * const hc)
+{
+	sdio_hc_cfg_t * const cfg = &hc->cfg;
+	unsigned const hwioff = hwi_find_device("bcm2711-sdmmc", 0);
+	if (hwioff != HWI_NULL_OFF) {
+		hwi_tag * const tag = hwi_tag_find(hwioff, HWI_TAG_NAME_location, NULL);
+		if (tag != NULL) {
+			cfg->bmstr_xlat = tag->location.base;
+			sdio_slogf(_SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 0,
+					   "%s: found SDMMC DMA range in syspage %lx", __func__, cfg->bmstr_xlat);
+		} else {
+			sdio_slogf(_SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 0,
+					   "%s: did not find bcm2711-sdmmc location tag", __func__);
+		}
+	} else {
+		sdio_slogf(_SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 0,
+				   "%s: did not find bcm2711-sdmmc tag", __func__);
+	}
+}
+
+static int bcm2711_bs_args(sdio_hc_t *hc, char *options)
+{
+	char	*value;
+	int		opt;
+	sdio_hc_cfg_t	*cfg = &hc->cfg;
+
+	static char     *opts[] = {
+#define BUSMASTER_BASE		0
+	"bmstr_base",
+	NULL};
+
+	while (options && *options != '\0') {
+		if ((opt = sdio_hc_getsubopt( &options, opts, &value)) == -1) {
+			sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 0, "%s: invalid BS options %s", __func__, options);
+			return EINVAL;
+		}
+
+		switch (opt) {
+			case BUSMASTER_BASE:
+				if (value == NULL) {
+					sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 0, "%s(%d): invalid BS options %s",
+						__func__, __LINE__,  options);
+					return EINVAL;
+				}
+				cfg->bmstr_xlat = strtoull(value, NULL, 0);
+				break;
+			default:
+				break;
+		}
+	}
+
+	return EOK;
+}
+
+static int bcm2711_bs_init(sdio_hc_t *hc)
+{
+	int    status = EOK;
+	sdio_hc_cfg_t  *cfg = &hc->cfg;
+
+	bcm2711_get_sdmmc_dma_range(hc);
+
+	if (bcm2711_bs_args(hc, cfg->options)) {
+		return EINVAL;
+	}
+
+	if(hc->caps & HC_CAP_SLOT_TYPE_EMBEDDED) {
+		hc->caps |= HC_CAP_HS200;
+	}
+
+	status = sdhci_init(hc);
+	if( status != EOK ) {
+		return status;
+	}
+
+	if(!(hc->caps & HC_CAP_SLOT_TYPE_EMBEDDED)) {
+		/* Overwrite some of the capabilities that are set by sdhci_init() */
+		hc->caps &= ~HC_CAP_CD_INTR;
+		hc->caps &= ~HC_CAP_SV_1_8V;
+	}
+	return status;
+}
+
+sdio_product_t  sdio_fs_products[] = {
+	{ .did = SDIO_DEVICE_ID_WILDCARD, .class = 0, .aflags = 0, .name = "bcm2711", .init = bcm2711_bs_init },
+};
+
+sdio_vendor_t   sdio_vendors[] = {
+	{ .vid = SDIO_VENDOR_ID_WILDCARD, .name = "Broadcom", .chipsets = sdio_fs_products },
+    { .vid = 0, .name = NULL, .chipsets = NULL }
+};
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/aarch64/bcm2711.le/bs.c $ $Rev: 992620 $")
+#endif

src/hardware/devb/sdmmc/aarch64/bcm2711.le/bs.h

@@ -0,0 +1,39 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2020, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+/* Module Description:  board specific header file */
+
+#ifndef _BS_H_INCLUDED
+#define _BS_H_INCLUDED
+
+// Add new chipset externs here
+#define SDIO_HC_SDHCI
+
+#undef  SDIO_SOC_SUPPORT
+#define SDIO_HWI_NAME "sdmmc"
+
+#endif
+
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/aarch64/bcm2711.le/bs.h $ $Rev: 918656 $")
+#endif

src/hardware/devb/sdmmc/aarch64/bcm2711.le/sim_bs.c

@@ -0,0 +1,49 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2020, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+/* Module Description:  board specific interface */
+
+#include <sim_sdmmc.h>
+
+int sim_bs_args( SIM_HBA *hba, char *options )
+{
+    char          *value;
+    int           opt;
+    static char   *opts[] = { NULL };
+
+    while( options && *options != '\0' ) {
+        if( ( opt = getsubopt( &options, opts, &value ) ) == -1 ) {
+        }
+
+        switch( opt ) {
+            default:
+                break;
+        }
+    }
+
+    return( EOK );
+}
+
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/aarch64/bcm2711.le/sim_bs.c $ $Rev: 918656 $")
+#endif

src/hardware/devb/sdmmc/aarch64/bcm2711.le/sim_bs.h

@@ -0,0 +1,34 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2020, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+// Module Description:  board specific header file
+
+#ifndef _SIM_BS_H_INCLUDED
+#define _SIM_BS_H_INCLUDED
+
+extern int sim_bs_args( SIM_HBA *hba, char *options );
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/aarch64/bcm2711.le/sim_bs.h $ $Rev: 918656 $")
+#endif

src/hardware/devb/sdmmc/devb-sdmmc.use

@@ -0,0 +1,94 @@
+%C SDMMC Driver.
+
+Syntax:
+devb-sdmmc-<variant> [cam cam_options][sdmmc sdmmc_options...][sdio sdio_options...][blk io-blk_options...] &
+
+Options:  All options are separated by commas.
+
+cam options:
+    async=[priority]  Perform CPU cache invalidation after an I/O operation in
+                   a thread at "priority". In some cases, and on some boards,
+                   this can provide a performance boost.  Default off,
+                   priority 21.
+    bounce=[size]  This option specifies the size of bounce buffer to use.
+                   The bounce buffer acts as an intermediate buffer for doing
+                   transfers to/from the media. Bounce buffers are useful for
+                   devices which cannot access the full range of memory
+                   available to the CPU (32 vs 64-bit architecture etc).  When
+                   used, size should be sufficiently large such that the CAM
+                   library doesn't fragment the I/O requests from io-blk, this
+                   will show markedly better performance. This option will
+                   automatically be enabled when cached memory buffer usage
+                   is disabled or when the hw doesn't support snooping.  The
+                   size argument can include a case-insensitve suffix that
+                   indicates the units: B (bytes; the default), K (kilobytes),
+                   M (megabytes), or P (pages).  The default size=32k.
+    cache=[on|off] Turn on/off usage of cached memory buffers.  Default on.
+    lun=mask       Enable Logical Unit Number (LUN) scan for the devices
+                   specified in mask. The mask is a hex bitmask specifying
+                   which IDs to scan for; the default is 0x00.
+    maxio=wr:rd    Set max I/O write, read blocks.  Default 4096, limited by device.
+    noio           Completely remove the IO ability.  Both ThreadCtl(_NTO_TCTL_IO)
+                   and ThreadCtl(_NTO_TCTL_IO_PRIV) won't be called.
+    nopriv         Don't call ThreadCtl(_NTO_TCTL_IO_PRIV).
+    pnp            Enable CAM plug and play (i.e. don't exit at startup when
+                   no devices are found).  Default off.
+    resmgr=m:l:h:d Enable /dev/camX/XXX interface and set max/lo/hi/devno
+                   thread pool parameters (default: "5:1:2:-1")
+    user=UID:GID   Operate as the specified user and group IDs. The driver
+                   retains the necessary process-manager abilities.
+    smmu=[on|off]  Turn on/off (1/0) the use of IO MMU protection services.
+                   Default off.
+    verbose        Be verbose: display full information about SCSI units
+                   (devices) on startup.
+
+mem options:
+    name=name      Typed memory name to use.  Default sysram&below4G).
+                   See also blk layer option for typed memory.
+
+sdmmc options:
+   The sdmmc options control the driver's interface to the SD/MMC device.
+   If there are multiple SD/MMC devices, you can repeat these options
+   for each controller. Remember, however, to specify the sdmmc keyword
+   before each controller's set of options.
+
+   bkops=[on/auto]   Value 'on' = Manual background operations (WARNING: permanent setting)
+                     Value 'auto' = Device background operations.
+   busno=bus         The bus number of the SDIO controller.
+   bs=[options]      Set board specific options
+   cache=on          Enable eMMC/SD volatile cache
+   partitions=on     Enable eMMC partitions
+   powman=[name]     Connect to powerman.  Dflts: No connect, [name]=devb-sdmmc-<variant>.
+   priority=prio     Set the priority of the processing thread. Dflt 21.
+   pwroff_notify=[short/long] Set power off notification mode for emmc [short/long].
+   relwr=on          Enable eMMc reliable write. Dflt off.
+   verbose=[level]   Set the sdmmc verbosity level.
+
+sdio options:
+   The sdio options control the driver's interface to the SD/MMC host
+   controller.  If there are multiple host controllers, you can repeat
+   these options for each controller. Remember, however, to specify
+   the sdio keyword before each controller's set of options.
+
+   verbose=[level]   Set the sdio verbosity level.
+   hc=name           Name of host controller.
+   vid=vid           The vendor id of the controller.
+   did=did           The device id of the controller.
+   idx=idx           The index of the controller in the machine, where
+                     idx is a value between 0 and the number of adapters.
+   addr=addr         The address of the interface.
+   irq=req           The interrupt used by the controller.
+   dma=chnl          The DMA channel to use.
+   clk=clk           Set the operational clock.
+   ~bmstr            Disable DMA.
+   ~ac12             Disable AC12.  Dflt on.
+   ~ac23             Disable AC23.  Dflt on.
+   bw=[~]bw          Set/Clear bus widths (4, 8).
+   timing=[~]timing  Set/Clear timings (hs, ddr, sdr12, sdr25, sdr50, sdr104, hs200, hs400, hs400es).
+   pm=idle:sleep     Set the pwr mgnt idle/sleep time in ms. Dflt 100:10000 ms.
+   emmc              eMMC device is connected to the interface
+   hs=options        Host specific options.
+   bs=options        Board specific options.
+   nowp              Disable write protect detection.
+   drv_type=drv_type Driver strength value for the HS_TIMING register (0, 1, 2, 3, 4). Dflt 0.
+

src/hardware/devb/sdmmc/extra.mk

@@ -0,0 +1,6 @@
+EXTRA_INCVPATH += $(PROJECT_ROOT)/sdmmc/sdiodi/hc
+EXTRA_SRCVPATH += $(PROJECT_ROOT)/sdmmc/sdiodi/hc
+EXTRA_SRCVPATH += $(PROJECT_ROOT)/sdmmc/sdiodi
+EXTRA_INCVPATH += $(PROJECT_ROOT)/sdmmc/sdiodi/include
+PUBLIC_INCVPATH += $(wildcard $(VARIANT1_ROOT)/public )
+

src/hardware/devb/sdmmc/pinfo.mk

@@ -0,0 +1,33 @@
+define PINFO
+PINFO DESCRIPTION=sd/mmc disk driver
+endef
+# Generate a new variant use file if board specific use file is presented.
+VARIANT_NAME=$(basename $(VARIANT1))
+ifneq ($(wildcard $(PWD)/$(VARIANT_NAME).use),)
+GENERIC_USEFILE=$(PROJECT_ROOT)/$(SECTION)/$(NAME).use
+SOC_USEFILE=$(PROJECT_ROOT)/$(SECTION)/$(CPU)/$(VARIANT1)/$(VARIANT_NAME).use
+USEFILE=$(PROJECT_ROOT)/$(SECTION)/$(CPU)/$(VARIANT1)/$(NAME)-$(VARIANT_NAME).use
+
+$(shell cat $(GENERIC_USEFILE) > $(USEFILE))
+$(shell cat $(SOC_USEFILE) >> $(USEFILE))
+$(shell sed -i 's/<variant>/$(VARIANT_NAME)/' $(USEFILE))
+
+EXTRA_CLEAN += $(NAME)-$(VARIANT_NAME).use
+endif
+PUBLIC_INCVPATH += $(wildcard $(PROJECT_ROOT)/$(SECTION)/public )
+
+# Uncomment when powman is enabled on all variants
+#LIBS += powman slog2
+
+NDAS := $(wildcard *.o-nda)
+
+ifeq ($(filter $(basename $(NDAS)), $(basename $(notdir $(SRCS)))),)
+# we don't have the NDA source, have to use pre-compiled binaries
+SRCS += $(NDAS)
+else
+# We don't need the following lines if we're willing to manually update
+# the *.?-nda files.
+#UPDATE_NDA_OBJECTS = 1
+#POST_TARGET = $(NDAS)
+endif
+

src/hardware/devb/sdmmc/public/hw/dcmd_sim_mmcsd.h

@@ -0,0 +1,327 @@
+/*
+ * $QNXLicenseC: 
+ * Copyright 2008, QNX Software Systems.  
+ *  
+ * Licensed under the Apache License, Version 2.0 (the "License"). You  
+ * may not reproduce, modify or distribute this software except in  
+ * compliance with the License. You may obtain a copy of the License  
+ * at: http://www.apache.org/licenses/LICENSE-2.0  
+ *  
+ * Unless required by applicable law or agreed to in writing, software  
+ * distributed under the License is distributed on an "AS IS" basis,  
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
+ * 
+ * This file may contain contributions from others, either as  
+ * contributors under the License or as licensors under other terms.   
+ * Please review this entire file for other proprietary rights or license  
+ * notices, as well as the QNX Development Suite License Guide at  
+ * http://licensing.qnx.com/license-guide/ for other information. 
+ * $ 
+ */
+
+/*
+ *  dcmd_sim_mmcsd.h   Non-portable low-level devctl definitions
+ *
+*/
+
+#ifndef __DCMD_SIM_MMCSD_H_INCLUDED
+#define __DCMD_SIM_MMCSD_H_INCLUDED
+
+#ifndef _DEVCTL_H_INCLUDED
+ #include <devctl.h>
+#endif
+
+#include <_pack64.h>
+
+#define MMCSD_MAX_SLOTNAME_LEN	32
+/* CID reg values of the card */
+typedef struct _mmcsd_cid {
+	_Uint32t		flags;	/*set MMCSD_FULL_CID flag t0 return raw/full cid contents */
+	_Uint8t         rsvd[4];
+	union{
+		struct{
+			_Uint32t            cid[4];
+		}full_cid;
+		union{
+			struct{
+				uint8_t 	mid;		/* Manufacture ID */
+				uint8_t 	oid[3]; 	/* OEM/Application ID */
+				uint8_t 	pnm[6]; 	/* Product name */
+				uint8_t 	prv;		/* Product revision */
+				uint32_t	psn;		/* Product serial number */
+				uint16_t	mdt;		/* Manufacture date */
+			}sd_cid;
+			struct{
+				uint32_t	mid;		/* Manufacture ID */
+				uint16_t	oid;		/* OEM ID */
+				uint8_t 	pnm[8]; 	/* Product name */
+				uint8_t 	hwr;		/* HW revision */
+				uint8_t 	fwr;		/* FW revision */
+				uint32_t	psn;		/* Product serial number */
+				uint8_t 	mcd;		/* Month code */
+				uint16_t	ycd;		/* Year code */
+			}mmc_cid;
+		}parsed_cid;
+	}cid;
+	pid_t		pid;    			/* Store PID of driver process for this device */
+	_Uint32t	speed; 				/*  Card speed currently working at */
+	_Uint32t	media_change; 		/* Media change counter */
+	_Uint8t		hwspec_version;		/* physical layer spec */
+	_Uint8t		csd_version;		/* CSD structure version */
+	_Uint8t		mmcprot_version;	/* MMC proto version */
+	_Uint8t	type;				/* card type, MMC or SD for now */
+	char		slotname[MMCSD_MAX_SLOTNAME_LEN];		/* slot name */
+} MMCSD_CID;
+
+typedef struct _mmc_csd_ext {
+	uint32_t	hs_max_dtr;
+	uint32_t	sectors;
+	uint8_t		erase_grp_def;
+	uint8_t		hc_erase_group_size;
+	uint8_t		hc_wp_grp_size;
+	uint8_t		user_wp;
+} MMC_CSD_EXT;
+
+typedef struct _mmcsd_csd {
+	_Uint32t	flags;
+	_Uint8t		rsvd[4];
+	union {
+		struct {
+			uint8_t		csd_structure;  /* CSD structure */
+			uint8_t		taac;
+			uint8_t		nsac;
+			uint8_t		tran_speed;
+			uint16_t	ccc;
+			uint8_t		read_bl_len;
+			uint8_t		read_bl_partial;
+			uint8_t		write_blk_misalign;
+			uint8_t		read_blk_misalign;
+			uint8_t		dsr_imp;
+			union {
+				struct {
+					uint16_t	c_size;
+					uint8_t		vdd_r_curr_min;
+					uint8_t		vdd_r_curr_max;
+					uint8_t		vdd_w_curr_min;
+					uint8_t		vdd_w_curr_max;
+					uint8_t		c_size_mult;
+				} csd_ver1;
+				struct {
+					uint32_t	c_size;
+				} csd_ver2;
+			}csd;
+			uint8_t		erase_blk_en;
+			uint8_t		sector_size;
+			uint8_t		wp_grp_size;
+			uint8_t		wp_grp_enable;
+			uint8_t		r2w_factor;
+			uint8_t		write_bl_len;
+			uint8_t		write_bl_partial;
+			uint8_t		file_format_grp;
+			uint8_t		copy;
+			uint8_t		perm_write_protect;
+			uint8_t		tmp_write_protect;
+			uint8_t		file_format;
+		} sd_csd;
+		struct {
+			uint8_t		csd_structure;  /* CSD structure */
+			uint8_t		mmc_prot;
+			uint8_t		taac;
+			uint8_t		nsac;
+			uint8_t		tran_speed;
+			uint16_t	ccc;
+			uint8_t		read_bl_len;
+			uint8_t		read_bl_partial;
+			uint8_t		write_blk_misalign;
+			uint8_t		read_blk_misalign;
+			uint8_t		dsr_imp;
+			uint16_t	c_size;
+			uint8_t		vdd_r_curr_min;
+			uint8_t		vdd_r_curr_max;
+			uint8_t		vdd_w_curr_min;
+			uint8_t		vdd_w_curr_max;
+			uint8_t		c_size_mult;
+			union {
+				struct {	/* MMC system specification version 3.1 */
+					uint8_t erase_grp_size;
+					uint8_t erase_grp_mult;
+				} mmc_v31;
+				struct {	/* MMC system specification version 2.2 */
+					uint8_t sector_size;
+					uint8_t erase_grp_size;
+				} mmc_v22;
+			} erase;
+			MMC_CSD_EXT	ext_csd;
+			uint8_t		wp_grp_size;
+			uint8_t		wp_grp_enable;
+			uint8_t		r2w_factor;
+			uint8_t		write_bl_len;
+			uint8_t		write_bl_partial;
+	/*      uint8_t		file_format_grp; */
+			uint8_t		copy;
+			uint8_t		perm_write_protect;
+			uint8_t		tmp_write_protect;
+			uint8_t		ecc;
+		} mmc_csd;
+	} csd;
+	pid_t		pid;				/* Store PID of driver process for this device */
+	_Uint8t		csd_version;		/* CSD structure version */
+	_Uint8t		mmcprot_version;	/* MMC proto version */
+	_Uint8t		type;				/* card type, MMC or SD for now */
+} MMCSD_CSD;
+
+/*flags definition */
+#define MMCSD_FULL_CID			0x80000000 /* The client request a raw/full CID instead of parsed CID */
+#define MMCSD_ECC_INFO			0x40000000 /* The client request ECC error information */
+#define MMCSD_CARD_STATUS       0x20000000 /* The client request MMC_SEND_STATUS command to check card is alive */
+#define MMCSD_DEV_RDONLY        0x00000001 /* write protected */
+#define MMCSD_DEV_NO_MEDIA      0x00000002 /* no media inserted */
+#define MMCSD_DEV_RDY      		0x00000004 /* Media is ready to accept IO */
+#define MMCSD_DEV_PRELOAD      	0x00000008 /* device is in the slot before the driver started */
+#define MMCSD_DEV_LOCKED        0x00000010 /* device is locked */
+#define MMCSD_DEV_MEDIA_ERROR   0x00000020 /* device inserted but there are error when identify it */
+#define MMCSD_DEV_ECC           0x00000040 /* device has ECC error */
+
+#define MMCSD_CARD_TYPE_UNKNOWN	0x0
+#define MMCSD_CARD_TYPE_MMC		0x1
+#define MMCSD_CARD_TYPE_SD		0x2
+
+typedef struct _mmcsd_write_protect {
+#define MMCSD_WP_ACTION_CLR		0x00
+#define MMCSD_WP_ACTION_SET		0x01
+	_Uint32t		action;
+#define MMCSD_WP_MODE_PWR_WP_EN		0x01  /* Apply Power-On Period Protection */
+	_Uint32t		mode;
+	_Uint64t		lba;
+	_Uint64t		nlba;
+	_Uint64t		rsvd2;
+} MMCSD_WRITE_PROTECT;
+
+#define MMCSD_VUC_END			0x80000000	/*flag indicate that this is the last command in the array */
+#define MMCSD_VUC_DATA_MSK		0x00000003	/*data present and direction bits (1-0) */
+#define MMCSD_VUC_DATA_NONE		0x00000000
+#define MMCSD_VUC_DATA_IN		0x00000001
+#define MMCSD_VUC_DATA_OUT		0x00000002
+#define MMCSD_VUC_DATA_PHYS		0x00000004	/*data_ptr is physical address */
+#define MMCSD_VUC_RCA			0x00000008	/*is RCA valid in the rca field */
+#define MMCSD_VUC_ACMD			0x00000010	/*Application Specific command needed */
+#define MMCSD_VUC_NOAC12		0x00000020	/*By default auto CMD12 is enabled */
+
+#define MMCSD_VUC_RESP_MSK		0x0000ff00	/* response type (15-8) */
+#define MMCSD_VUC_RESP_OFF		8			/*bit offset */
+#define MMCSD_VUC_RESP_NONE		0x00000000
+#define MMCSD_VUC_RESP_R1		0x00001500
+#define MMCSD_VUC_RESP_R1B		0x00001d00
+#define MMCSD_VUC_RESP_R2		0x00000700
+#define MMCSD_VUC_RESP_R3		0x00000100
+#define MMCSD_VUC_RESP_R6		0x00001500
+#define MMCSD_VUC_RESP_R7		0x00001500
+
+/*
+ * for performance,
+ * we assume that the RESP bits is the same as internal driver define
+ * if any of the internal define changed(which i doubt it), we will need to add a pasring code to
+ * do the translation
+#define	MMC_RSP_PRESENT	(1 << 0)
+#define	MMC_RSP_136		(1 << 1)	// 136 bit response
+#define	MMC_RSP_CRC		(1 << 2)	// expect valid crc
+#define	MMC_RSP_BUSY	(1 << 3)	// card may send busy
+#define	MMC_RSP_OPCODE	(1 << 4)	// response contains opcode
+ */
+
+/*return code */
+#define MMC_VUC_SUCCESS			0
+#define MMC_VUC_FAILED			1
+#define MMC_VUC_NOTISSUED		2
+#define MMC_VUC_NODEV			3
+
+typedef struct _mmcsd_vuc_cmd {
+	int				result;
+	_Uint16t		opcode;
+	_Uint16t        rsvd2;
+	_Uint32t		flags;
+	_Uint32t		arg;
+	_Uint32t		resp[4];
+	_Uint32t		blk_sz;
+	paddr64_t		data_ptr;	/*the buffer is a physical addr that need to be provided by client, */
+								/*and assume it's non cacheable dma-able(contiguous). */
+	_Uint32t		buf_off;	/*for PIO mode (MMCSD_VUC_DATA_PHYS not set), this is the offset of the */
+								/*buffer for this command in the array, starting from the first command structure */
+	_Uint32t		data_len;
+	_Uint32t		timeout;	/*timeout value for command in ms (default will be 5 sec if set to 0) */
+	_Uint32t		postdelay_us;
+	_Uint32t		rsvd[2];
+} MMCSD_VUC_CMD;
+
+#define MMCSD_ERASE_ACTION_NORMAL	0x00
+#define MMCSD_ERASE_ACTION_SECURE	0x01
+typedef struct _mmcsd_erase {
+	_Uint32t		action;
+	_Uint32t		rsvd;
+	_Uint64t		lba;
+	_Uint64t		nlba;
+	_Uint64t		rsvd2;
+} MMCSD_ERASE;
+
+typedef struct _mmcsd_card_register {
+#define MMCSD_CR_ACTION_READ	0x00
+	_Uint32t		action;
+#define MMCSD_REG_TYPE_CID		0x00
+#define MMCSD_REG_TYPE_CSD		0x01
+#define MMCSD_REG_TYPE_EXT_CSD	0x02
+#define MMCSD_REG_TYPE_SCR		0x03
+	_Uint32t		type;      /* REG_TYPE_XXX on entry, CARD_TYPE_XXX on return */
+	_Uint32t		address;
+	_Uint32t		length;
+	_Uint32t		rsvd[2];
+/*	_Uint8t			data[ length ];	variable length data */
+} MMCSD_CARD_REGISTER;
+
+#define RPMB_KEY_MAC_FIELD_LEN      32
+#define RPMB_DATA_FIELD_LEN         256
+#define RPMB_HASH_DATA_LEN          32
+#define RPMB_USABLE_DATA_LEN        (RPMB_DATA_FIELD_LEN - RPMB_HASH_DATA_LEN)
+#define RPMB_NONCE_FIELD_LEN        16
+#define RPMB_ONE_BLK_MAC_LEN        (RPMB_DATA_FIELD_LEN + RPMB_NONCE_FIELD_LEN + 4 + 2 + 2 + 2 + 2) /*(write_cntr +  address + block_cnt + result + req_resp) */
+
+typedef struct _mmcsd_rpmb_frame {
+    _Uint8t         stuff[196];
+    _Uint8t         key_mac[RPMB_KEY_MAC_FIELD_LEN];
+    _Uint8t         data[RPMB_DATA_FIELD_LEN];
+    _Uint8t         nonce[RPMB_NONCE_FIELD_LEN];
+    _Uint32t        write_cntr;
+    _Uint16t        address;
+    _Uint16t        block_cnt;
+    _Uint16t        result;
+    _Uint16t        req_resp;
+} MMCSD_RPMB_FRAME;
+
+typedef struct _mmcsd_rpmb_req {
+    _Uint16t            req_type;
+//    MMCSD_RPMB_FRAME    *rpmb_frame_paddr;
+    paddr64_t			rpmb_frame_paddr;
+} MMCSD_RPMB_REQ;
+
+#define DCMD_MMCSD_GET_CID				(__DIOTF(_DCMD_CAM, _SIM_MMCSD + 0, struct _mmcsd_cid))
+#define DCMD_MMCSD_WRITE_PROTECT		(__DIOTF(_DCMD_CAM, _SIM_MMCSD + 1, struct _mmcsd_write_protect))
+#define DCMD_MMCSD_GET_CSD				(__DIOTF(_DCMD_CAM, _SIM_MMCSD + 2, struct _mmcsd_csd))
+#define DCMD_MMCSD_ERASE				(__DIOTF(_DCMD_CAM, _SIM_MMCSD + 3, struct _mmcsd_erase))
+#define DCMD_MMCSD_CARD_REGISTER		(__DIOTF(_DCMD_CAM, _SIM_MMCSD + 4, struct _mmcsd_card_register))
+#define DCMD_MMCSD_GET_ECCERR_ADDR		(__DIOTF(_DCMD_CAM, _SIM_MMCSD + 5, int32_t))
+#define DCMD_MMCSD_VUC_CMD				(__DIOTF(_DCMD_CAM, _SIM_MMCSD + 6, struct _mmcsd_vuc_cmd))
+
+/*RPMB devctls */
+#define DCMD_MMCSD_RPMB_RW_FRAME        (__DIOTF(_DCMD_CAM, _SIM_MMCSD + 50, struct _mmcsd_rpmb_req))
+/*_SIM_MMCSD + 51 was RPMB_READ_RESPONSE, now rolled into the above. */
+#define DCMD_MMCSD_GET_CID_RAW			(__DIOF(_DCMD_CAM, _SIM_MMCSD + 52, uint32_t[4]))
+#define DCMD_MMCSD_ERASED_VAL			(__DIOF(_DCMD_CAM, _SIM_MMCSD + 53, uint8_t))
+#define DCMD_MMCSD_RPMB_SIZE			(__DIOF(_DCMD_CAM, _SIM_MMCSD + 54, uint8_t))
+
+#include <_packpop.h>
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/public/hw/dcmd_sim_mmcsd.h $ $Rev: 969525 $")
+#endif

src/hardware/devb/sdmmc/public/hw/dcmd_sim_sdmmc.h

@@ -0,0 +1,498 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2008, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+/*
+ *  dcmd_sim_sdmmc.h   Non-portable low-level devctl definitions
+ *
+*/
+
+#ifndef __DCMD_SIM_SDMMC_H_INCLUDED
+#define __DCMD_SIM_SDMMC_H_INCLUDED
+
+#ifndef _DEVCTL_H_INCLUDED
+ #include <devctl.h>
+#endif
+
+#include <_pack64.h>
+
+typedef struct _sdmmc_write_protect {
+#define SDMMC_WP_ACTION_CLR			0x00
+#define SDMMC_WP_ACTION_SET			0x01
+#define SDMMC_WP_ACTION_PROT		0x02
+ /* 32 write protection bits (representing 32 write protect groups) */
+#define SDMMC_WP_ACTION_PROT_TYPE	0x03
+ /* 64 write protection bits (representing 32 write protect groups) where:
+     0x0 WPG not protected
+     0x1 WPG temporary WP
+     0x2 WPG power-on WP
+     0x3 WPG permanent WP */
+
+	_Uint32t		action;
+
+#define SDMMC_WP_MODE_PWR_WP_EN		0x01  /* Apply Power-On Period Protection */
+	_Uint32t		mode;
+	_Uint64t		lba;
+	_Uint64t		nlba;
+	_Uint64t		prot;
+	_Uint32t		rsvd[4];
+} SDMMC_WRITE_PROTECT;
+
+#define SDMMC_ERASE_ACTION_NORMAL			0x00
+#define SDMMC_ERASE_ACTION_SECURE			0x01
+#define SDMMC_ERASE_ACTION_TRIM				0x02
+#define SDMMC_ERASE_ACTION_SECURE_TRIM		0x03
+#define SDMMC_ERASE_ACTION_SECURE_PURGE		0x04
+#define SDMMC_ERASE_ACTION_DISCARD			0x05
+#define SDMMC_ERASE_ACTION_SANITIZE			0x06
+typedef struct _sdmmc_erase {
+	_Uint32t		action;
+	_Uint32t		rsvd;
+	_Uint64t		lba;
+	_Uint64t		nlba;
+	_Uint64t		rsvd2;
+} SDMMC_ERASE;
+
+typedef struct _sdmmc_card_register {
+#define SDMMC_CR_ACTION_READ	0x00
+#define SDMMC_CR_ACTION_WRITE	0x01
+	_Uint32t		action;
+
+#define SDMMC_REG_TYPE_CID		0x00
+#define SDMMC_REG_TYPE_CSD		0x01
+#define SDMMC_REG_TYPE_EXT_CSD	0x02
+#define SDMMC_REG_TYPE_SCR		0x03
+#define SDMMC_CARD_TYPE_UNKNOWN	0x0
+#define SDMMC_CARD_TYPE_MMC		0x1
+#define SDMMC_CARD_TYPE_SD		0x2
+	_Uint32t		type;      /* REG_TYPE_XXX on entry, CARD_TYPE_XXX on return */
+	_Uint32t		address;
+	_Uint32t		length;
+	_Uint32t		rsvd[2];
+#define SDMMC_REG_SIZE_CID		16
+#define SDMMC_REG_SIZE_CSD		16
+#define SDMMC_REG_SIZE_EXT_CSD_READ	512
+#define SDMMC_REG_SIZE_EXT_CSD_WRITE	1
+#define SDMMC_REG_SIZE_SCR		8
+/*	_Uint8t			data[ length ];	variable length data */
+} SDMMC_CARD_REGISTER;
+
+typedef struct _sandisk_health {
+	_Uint32t		mid;				/* Manufacture ID */
+	_Uint8t			lifetime;
+	_Uint8t			nv_avg_pe;			/* NV Cache avg P/E cycle */
+	_Uint8t			eua_avg_pe;			/* Enhanced User Area avg P/E cycle */
+	_Uint8t			mlc_avg_pe;			/* MLC avg P/E cycle */
+} SANDISK_HEALTH;
+
+typedef struct _sandisk_emmc_health {
+	_Uint32t		mid;				/* Manufacture ID */
+	_Uint32t		avg_ec;				/* Avg Erase Count System */
+	_Uint32t		res4;
+	_Uint32t		mlc_avg_ec;			/* Avg Erase Count MLC */
+	_Uint32t		read_reclaim;		/* Read Reclaim Count System */
+	_Uint32t		res16;
+	_Uint32t		mlc_read_reclaim;	/* Read Reclaim Count MLC */
+	_Uint32t		init_bad_blocks;
+	_Uint32t		runtime_bad_blocks;
+	_Uint32t		res32;
+	_Uint32t		mlc_runtime_bad_blocks;
+	_Uint32t		patch_trial_cnt;
+	_Uint32t		patch_rel_date[3];
+	_Uint32t		patch_rel_time[2];
+	_Uint32t		cum_wr_data_sz;
+	_Uint32t		vcc_vltg_drop_occ;
+	_Uint32t		vcc_vltg_droop_occ;
+	_Uint32t		fail_rec_after_pwr_loss;
+	_Uint32t		rec_op_after_vltg_droop;
+	_Uint32t		res84[4];
+	_Uint32t		cum_init_cnt;
+	_Uint32t		max_ec;				/* Max Erase Count System */
+	_Uint32t		res108;
+	_Uint32t		mlc_max_ec;
+	_Uint32t		min_ec;
+	_Uint32t		res120;
+	_Uint32t		mlc_min_ec;
+	_Uint32t		euda_max_ec;		/* Max Erase Count EUDA */
+	_Uint32t		euda_min_ec;		/* Min Erase Count EUDA */
+	_Uint32t		euda_avg_ec;		/* Avg Erase Count EUDA */
+	_Uint32t		euda_read_reclaim;
+	_Uint32t		euda_runtime_bad_blocks;
+	_Uint32t		euda_pre_eol_state;
+	_Uint32t		pre_eol_state;
+	_Uint32t		mlc_pre_eol_state;
+	_Uint32t		uncorrectable_ecc;
+	_Uint32t		cur_temp;			/* Current Temperature */
+	_Uint32t		min_temp;			/* Min Temperature */
+	_Uint32t		max_temp;			/* Max Temperature */
+	_Uint32t		euda_health_status;
+	_Uint32t		health_status;
+	_Uint32t		mlc_health_status;
+} SANDISK_EMMC_HEALTH;
+
+typedef struct _samsung_health {
+	_Uint32t		mid;				/* Manufacture ID */
+	_Uint32t		bank0_rsvd_blocks;
+	_Uint32t		bank1_rsvd_blocks;
+	_Uint32t		bank2_rsvd_blocks;
+	_Uint32t		bank3_rsvd_blocks;
+	_Uint32t		init_bad_blocks;
+	_Uint32t		runtime_bad_blocks;
+	_Uint32t		slc_max_ec;			/* SLC Maximum Erase Count */
+	_Uint32t		slc_min_ec;			/* SLC Minimum Erase Count */
+	_Uint32t		slc_avg_ec;			/* SLC Average Erase Count */
+	_Uint32t		mlc_max_ec;			/* MLC Maximum Erase Count */
+	_Uint32t		mlc_min_ec;			/* MLC Minimum Erase Count */
+	_Uint32t		mlc_avg_ec;			/* MLC Average Erase Count */
+	_Uint32t		max_ec;				/* Overall Maximum Erase Count */
+	_Uint32t		min_ec;				/* Overall Minimum Erase Count */
+	_Uint32t		avg_ec;				/* Overall Average Erase Count */
+	_Uint32t		read_reclaim;
+	_Uint32t		num_banks;
+	_Uint32t		bank4_rsvd_blocks;
+	_Uint32t		bank5_rsvd_blocks;
+	_Uint32t		bank6_rsvd_blocks;
+	_Uint32t		bank7_rsvd_blocks;
+} SAMSUNG_HEALTH;
+
+typedef struct _toshiba_health {		/* supported from v4.41 onwards */
+	_Uint32t		mid;				/* Manufacture ID */
+	_Uint32t		lifetime_total;
+	_Uint32t		lifetime_rsvd_blk;
+	_Uint32t		lifetime_avg_pe;
+	_Uint32t		mlc_max_pe;			/* MLC Maximum P/E cycle range */
+	_Uint32t		mlc_avg_pe;			/* MLC Average P/E cycle range */
+	_Uint32t		slc_max_pe;			/* SLC Maximum P/E cycle range */
+	_Uint32t		slc_avg_pe;			/* SLC Average P/E cycle range */
+} TOSHIBA_HEALTH;
+
+typedef struct _toshiba_emmc_health {
+	_Uint32t		mid;				/* Manufacture ID */
+	_Uint8t			patrol_progress;
+	_Uint32t		patrol_round_count;
+	_Uint16t		runtime_bad_blocks;
+	_Uint32t		mlc_max_ec;			/* MLC Maximum Erase Count */
+	_Uint32t		mlc_avg_ec;			/* MLC Average Erase Count */
+	_Uint32t		slc_max_ec;			/* SLC Maximum Erase Count */
+	_Uint32t		slc_avg_ec;			/* SLC Average Erase Count */
+} TOSHIBA_EMMC_HEALTH;
+
+typedef struct _micron_health {
+	_Uint32t		mid;				/* Manufacture ID */
+	_Uint16t		init_bad_blocks;
+	_Uint16t		runtime_bad_blocks;
+	_Uint16t		spare_blocks;
+	_Uint16t		slc_min_ec;			/* SLC Minimum Erase Count */
+	_Uint16t		slc_max_ec;			/* SLC Maximum Erase Count */
+	_Uint16t		slc_avg_ec;			/* SLC Average Erase Count */
+	_Uint16t		mlc_min_ec;			/* MLC Minimum Erase Count */
+	_Uint16t		mlc_max_ec;			/* MLC Maximum Erase Count */
+	_Uint16t		mlc_avg_ec;			/* MLC Average Erase Count */
+	_Uint16t		min_ec;				/* Overall Minimum Erase Count */
+	_Uint16t		max_ec;				/* Overall Maximum Erase Count */
+	_Uint16t		avg_ec;				/* Overall Average Erase Count */
+} MICRON_HEALTH;
+
+typedef union _sdmmc_device_health {
+	_Uint32t			mid;				/* Manufacture ID */
+	SANDISK_HEALTH		sandisk;
+	SANDISK_EMMC_HEALTH	sandisk_emmc;
+	SAMSUNG_HEALTH		samsung;
+	TOSHIBA_HEALTH		toshiba;
+	TOSHIBA_EMMC_HEALTH	toshiba_emmc;
+	MICRON_HEALTH		micron;
+	_Uint8t				bytes[512];
+} SDMMC_DEVICE_HEALTH;
+
+typedef struct _sdmmc_device_info {
+#define DEV_TYPE_MMC			1
+#define DEV_TYPE_SD				2
+	_Uint32t			dtype;
+
+#define DEV_FLAG_CARD_LOCKED	0x02
+#define DEV_FLAG_WP				0x01
+	_Uint32t			flags;
+
+#define MID_MMC_SANDISK			0x02
+#define MID_MMC_SANDISK_2		0x45
+#define MID_MMC_TOSHIBA			0x11
+#define MID_MMC_MICRON			0x13
+#define MID_MMC_SAMSUNG			0x15
+#define MID_MMC_KINGSTON		0x70
+#define MID_MMC_HYNIX			0x90
+#define MID_MMC_NUMONYX			0xFE
+	_Uint32t			mid;			/* Manufacture ID */
+	_Uint32t			oid;			/* OEM ID */
+	_Uint8t				pnm[8];			/* Product name */
+	_Uint32t			prv;			/* Product revision */
+	_Uint32t			psn;			/* Product serial number */
+	_Uint32t			month;			/* Month */
+	_Uint32t			year;			/* Year */
+	_Uint8t				vu[8];			/* Vendor Unique ie SanDisk fw revision */
+
+	_Uint32t			rca;
+	_Uint32t			spec_vers;
+	_Uint32t			spec_rev;
+	_Uint32t			security;
+
+#define DEV_CAP_HC				(1ULL << 0)	/* high capacity */
+#define DEV_CAP_HS				(1ULL << 1)	/* high speed */
+#define DEV_CAP_HS200			(1ULL << 2)	/* high speed 200 */
+#define DEV_CAP_DDR50			(1ULL << 3)	/* DDR */
+#define DEV_CAP_UHS				(1ULL << 4)	/* UHS */
+#define DEV_CAP_TRIM			(1ULL << 5)	/* TRIM supported */
+#define DEV_CAP_SECURE			(1ULL << 6)	/* Secure Purge supported */
+#define DEV_CAP_SANITIZE		(1ULL << 7)	/* SANITIZE supported */
+#define DEV_CAP_BKOPS			(1ULL << 8)	/* Background Operations supported */
+#define DEV_CAP_CMD23			(1ULL << 9)	/* CMD23 supported */
+#define DEV_CAP_SLEEP			(1ULL << 10)	/* SLEEP/AWAKE supported */
+#define DEV_CAP_ASSD			(1ULL << 11)	/* ASSD */
+#define DEV_CAP_HPI_CMD12		(1ULL << 12)
+#define DEV_CAP_HPI_CMD13		(1ULL << 13)
+#define DEV_CAP_DISCARD			(1ULL << 14)	/* Discard supported */
+#define DEV_CAP_CACHE			(1ULL << 15)
+#define DEV_CAP_HS400			(1ULL << 16)	/* high speed 400 */
+#define DEV_CAP_PWROFF_NOTIFY	(1ULL << 17)	/* power off notify supported */
+#define DEV_CAP_HS400ES			(1ULL << 18)	/* high speed 400 enhanced strobe */
+#define DEV_CAP_BKOPS_AUTO		(1ULL << 19)	/* Auto Background Operations supported */
+#define DEV_CAP_UC				(1ULL << 20)	/* ultra capacity (2TB - 128TB) */
+	_Uint64t			caps;
+
+	_Uint32t			dtr;			/* current data transfer rate */
+
+#define TIMING_HS400			9
+#define TIMING_HS200			8
+#define TIMING_SDR104			7
+#define TIMING_SDR50			6
+#define TIMING_SDR25			5
+#define TIMING_SDR12			4
+#define TIMING_DDR50			3
+#define TIMING_HS				2
+#define TIMING_LS				1
+	_Uint32t			timing;			/* current timing */
+	_Uint32t			bus_width;		/* current bus width */
+	_Uint32t			sectors;
+	_Uint32t			sector_size;
+	_Uint32t			super_page_size;
+	_Uint32t			native_sector_size;
+	_Uint32t			wp_size;
+	_Uint32t			erase_size;
+	_Uint32t			optimal_trim_size;
+	_Uint32t			optimal_read_size;
+	_Uint32t			optimal_write_size;
+
+#define SPEED_CLASS_0			0x00	/* Legacy/Non Compliant */
+#define SPEED_CLASS_2			0x01	/* Approximately 2MB/sec */
+#define SPEED_CLASS_4			0x02	/* Approximately 4MB/sec */
+#define SPEED_CLASS_6			0x03	/* Approximately 6MB/sec */
+#define SPEED_CLASS_10			0x04	/* Approximately 10MB/sec */
+	_Uint32t			speed_class;
+
+	_Uint32t			start_sector;	/* Physical Start Sector */
+
+	_Uint64t			sectors64;
+	_Uint64t			start_sector64;	/* Physical Start Sector */
+
+	_Uint32t			rsvd[30];
+} SDMMC_DEVICE_INFO;
+
+typedef struct _sdmmc_assd_status {
+#define ASSD_STATE_SCP			1		/* Secure Command in Progress */
+#define ASSD_STATE_SCC			2		/* Secure Command Complete */
+#define ASSD_STATE_SCA			3		/* Secure Command Aborted */
+	_Uint8t		assd_state;
+
+#define ASSD_ERR_STATE_NE		0		/* No Error */
+#define ASSD_ERR_STATE_AE		1		/* Auth Error */
+#define ASSD_ERR_STATE_ANF		2		/* Area Not Found */
+#define ASSD_ERR_STATE_RO		3		/* Range Over */
+#define ASSD_ERR_STATE_CE		4		/* Condition Error */
+	_Uint8t		assd_err_state;
+	_Uint8t		assd_sec_sys_err;
+	_Uint8t		pmem_state;
+	_Uint8t		auth_alg;
+	_Uint8t		enc_alg;
+	_Uint8t		active_sec_system;
+	_Uint8t		sec_token_prot;
+	_Uint16t	read_block_count;
+	_Uint16t	suspended_sec_sys;
+	_Uint32t	rsvd[6];
+} SDMMC_ASSD_STATUS;
+
+typedef struct _sdmmc_assd_properties {
+	_Uint8t		assd_version;
+	_Uint8t		assd_sec_sys_vendor_id;
+	_Uint16t	assd_sec_sys;
+
+	_Uint16t	suspendible_sec_sys;
+	_Uint16t	sup_auth_alg;
+	_Uint16t	sup_enc_alg;
+	_Uint16t	cl_support;
+
+	_Uint8t		sec_read_latency;		/* 250ms units */
+	_Uint8t		sec_write_latency;		/* 250ms units */
+	_Uint8t		wr_sec_bus_busy;		/* 250ms units */
+	_Uint8t		ctrl_sys_bus_busy;		/* 250ms units */
+
+	_Uint8t		pmem_support;
+	_Uint8t		pmem_rd_time;			/* 100ms units */
+	_Uint8t		pmem_wr_time;			/* 250ms units */
+
+	_Uint8t		rsvd[17];
+} SDMMC_ASSD_PROPERTIES;
+
+typedef struct _sdmmc_assd_control {
+#define SDMMC_AC_OP_START_SUSPEND	0x3
+#define SDMMC_AC_OP_CLEAR_SUSPEND	0x2
+#define SDMMC_AC_OP_SELECT_RESET	0x1
+	_Uint8t		operation;
+
+#define SDMMC_AC_SSI_MAX			0xf
+	_Uint8t		sec_sys_idx;
+	_Uint16t	rsvd[11];
+} SDMMC_ASSD_CONTROL;
+
+typedef struct _sdmmc_assd_apdu {
+	_Uint32t	length;
+	_Uint32t	rsvd[7];
+/*	_Uint8t		data[ length ];		variable length data */
+} SDMMC_ASSD_APDU;
+
+typedef struct _sdmmc_lock_unlock {
+#define SDMMC_LU_ACTION_ERASE		0x08
+#define SDMMC_LU_ACTION_LOCK		0x04
+#define SDMMC_LU_ACTION_CLR			0x02
+#define SDMMC_LU_ACTION_SET			0x01
+#define SDMMC_LU_ACTION_UNLOCK		0x00
+	_Uint32t	action;
+	_Uint32t	pwd_len;
+#define SDMMC_LU_PWD_SIZE			16
+	_Uint8t		pwd[SDMMC_LU_PWD_SIZE];
+	_Uint32t	rsvd[8];
+} SDMMC_LOCK_UNLOCK;
+
+typedef struct _sdmmc_partition_info {
+#define SDMMC_PI_ACTION_GET		0x00
+#define SDMMC_PI_ACTION_CLR		0x01
+	_Uint32t		action;
+	_Uint32t		rsvd;
+
+#define SDMMC_PTYPE_USER		0
+#define SDMMC_PTYPE_BOOT1		1
+#define SDMMC_PTYPE_BOOT2		2
+#define SDMMC_PTYPE_RPMB		3
+#define SDMMC_PTYPE_GP1			4
+#define SDMMC_PTYPE_GP2			5
+#define SDMMC_PTYPE_GP3			6
+#define SDMMC_PTYPE_GP4			7
+	_Uint32t		ptype;
+#define SDMMC_PFLAG_WP			0x01
+#define SDMMC_PFLAG_ENH			0x02
+#define SDMMC_PFLAG_VIRTUAL		0x04
+	_Uint32t		pflags;
+	_Uint64t		start_lba;			/* Starting lba */
+	_Uint64t		num_lba;			/* Num lba */
+	_Uint64t		rc;					/* Read Count (sectors) */
+	_Uint64t		wc;					/* Written Count (sectors) */
+	_Uint64t		tc;					/* TRIM Count (sectors) */
+	_Uint64t		ec;					/* Erase Count (sectors) */
+	_Uint64t		dc;					/* Discard Count (sectors) */
+	_Uint32t		rsvd1[64];
+} SDMMC_PARTITION_INFO;
+
+typedef struct _sdmmc_pwr_mgnt {
+#define SDMMC_PM_ACTION_GET		0x00
+#define SDMMC_PM_ACTION_SET		0x01
+	_Uint32t		action;
+	_Uint32t		rsvd;
+
+	_Uint64t		idle_time;			/* time in ms til device enters idle */
+	_Uint64t		sleep_time;			/* time in ms til device enters sleep */
+	_Uint32t		rsvd1[16];
+} SDMMC_PWR_MGNT;
+
+typedef struct _sdmmc_drvr_state {
+#define SDMMC_DRVR_PAUSE	0
+#define SDMMC_DRVR_RUN		1
+	_Uint32t		state;
+	_Uint32t		flags;
+	_Uint32t		rsvd1[4];
+} SDMMC_DRVR_STATE;
+
+typedef struct _sdmmc_gen_cmd {
+	_Uint32t		arg;
+#define	SDMMC_GENCMD_DIR	(1 << 0)	/* data direction mask */
+#define	SDMMC_GENCMD_WRITE	(0 << 0)
+#define	SDMMC_GENCMD_READ	(1 << 0)
+#define	SDMMC_GENCMD_NEXT	(1 << 15)	/* next command available */
+	_Uint16t		flags;
+
+	_Uint16t		blklen;
+/*	_Uint8t			data[0];			variable length data */
+} SDMMC_GEN_CMD;
+
+typedef struct _sdmmc_man_cmd {
+#define	SDMMC_MANCMD_TYPE	(1 << 16)	/* command type mask */
+#define	SDMMC_MANCMD_AC		(0 << 16)	/* command only */
+#define	SDMMC_MANCMD_ADTC	(1 << 16)	/* command with data */
+#define	SDMMC_MANCMD_DIR	(1 << 17)	/* data direction mask */
+#define	SDMMC_MANCMD_READ	(0 << 17)	/* read command */
+#define	SDMMC_MANCMD_WRITE	(1 << 17)	/* write command */
+#define	SDMMC_MANCMD_RSP	(1 << 18)	/* response type mask */
+#define	SDMMC_MANCMD_R1		(0 << 18)	/* response type R1 */
+#define	SDMMC_MANCMD_R1b	(1 << 18)	/* response type R1b */
+#define	SDMMC_MANCMD_NEXT	(1 << 31)	/* next command available */
+#define	SDMMC_MANCMD_CMD	(0xFF)		/* command opcode mask */
+#define	SDMMC_MANCMD_CMD1	(60)		/* CMD1 */
+#define	SDMMC_MANCMD_CMD2	(61)		/* CMD2 */
+#define	SDMMC_MANCMD_CMD3	(62)		/* CMD3 */
+#define	SDMMC_MANCMD_CMD4	(63)		/* CMD4 */
+	_Uint32t		flags;
+	_Uint32t		arg;
+	_Uint16t		blklen;
+	_Uint16t		blkcnt;
+/*	_Uint8t			data[0];			variable length data */
+} SDMMC_MAN_CMD;
+
+#define DCMD_SDMMC_DEVICE_INFO			(__DIOF(_DCMD_CAM, _SIM_SDMMC + 0, struct _sdmmc_device_info))
+#define DCMD_SDMMC_DEVICE_HEALTH		(__DIOF(_DCMD_CAM, _SIM_SDMMC + 1, union _sdmmc_device_health))
+#define DCMD_SDMMC_ERASE				(__DIOTF(_DCMD_CAM, _SIM_SDMMC + 2, struct _sdmmc_erase))
+#define DCMD_SDMMC_WRITE_PROTECT		(__DIOTF(_DCMD_CAM, _SIM_SDMMC + 3, struct _sdmmc_write_protect))
+#define DCMD_SDMMC_CARD_REGISTER		(__DIOTF(_DCMD_CAM, _SIM_SDMMC + 4, struct _sdmmc_card_register))
+#define DCMD_SDMMC_ASSD_STATUS			(__DIOF(_DCMD_CAM, _SIM_SDMMC + 5, struct _sdmmc_assd_status))
+#define DCMD_SDMMC_ASSD_PROPERTIES		(__DIOF(_DCMD_CAM, _SIM_SDMMC + 6, struct _sdmmc_assd_properties))
+#define DCMD_SDMMC_ASSD_CONTROL			(__DIOT(_DCMD_CAM, _SIM_SDMMC + 7, struct _sdmmc_assd_control))
+#define DCMD_SDMMC_ASSD_APDU			(__DIOTF(_DCMD_CAM, _SIM_SDMMC + 8, struct _sdmmc_assd_apdu))
+#define DCMD_SDMMC_LOCK_UNLOCK			(__DIOT(_DCMD_CAM, _SIM_SDMMC + 9, struct _sdmmc_lock_unlock))
+#define DCMD_SDMMC_PART_INFO			(__DIOTF(_DCMD_CAM, _SIM_SDMMC + 10, struct _sdmmc_partition_info))
+#define DCMD_SDMMC_PWR_MGNT				(__DIOTF(_DCMD_CAM, _SIM_SDMMC + 11, struct _sdmmc_pwr_mgnt))
+#define DCMD_SDMMC_GEN_CMD				(__DIOTF(_DCMD_CAM, _SIM_SDMMC + 12, struct _sdmmc_gen_cmd))
+#define DCMD_SDMMC_MAN_CMD				(__DIOTF(_DCMD_CAM, _SIM_SDMMC + 13, struct _sdmmc_man_cmd))
+#define DCMD_SDMMC_DRVR_STATE			(__DIOTF(_DCMD_CAM, _SIM_SDMMC + 14, struct _sdmmc_drvr_state))
+
+#include <_packpop.h>
+
+#endif
+
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/public/hw/dcmd_sim_sdmmc.h $ $Rev: 993509 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/card.c

@@ -0,0 +1,785 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2008, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#include <errno.h>
+#include <atomic.h>
+#include <string.h>
+#include <malloc.h>
+
+#include <internal.h>
+
+static int _sdio_synchronize( struct sdio_device *device, int io, int ncmds )
+{
+	pthread_mutex_lock( &sdio_ctrl.mutex );
+	if( !io ) {
+		atomic_set( &device->flags, DEV_FLAG_RMV_PENDING );
+		if( device->usage != 0 ) {
+			pthread_mutex_unlock( &sdio_ctrl.mutex );
+			return( EBUSY );
+		}
+	}
+	else if( ncmds >= 0 ) {
+		if( ( device->flags & DEV_FLAG_RMV_PENDING ) || ( device->dev->flags & DEV_FLAG_MEDIA_CHANGE ) ) {
+			pthread_mutex_unlock( &sdio_ctrl.mutex );
+			return( ENXIO );
+		}
+		device->usage += ncmds;
+	}
+	else {
+		device->usage += ncmds;		// Note:  add since ncmds is negative
+		if( ( device->usage == 0 ) && ( device->flags & DEV_FLAG_RMV_PENDING ) ) {
+			pthread_cond_signal( &sdio_ctrl.cd_cond );
+		}
+	}
+	pthread_mutex_unlock( &sdio_ctrl.mutex );
+	return( EOK );
+}
+
+struct sdio_device *sdio_device_lookup( struct sdio_connection *connection,
+		sdio_device_instance_t *instance )
+{
+	struct sdio_device		*device;
+
+	device = NULL;
+	pthread_mutex_lock( &sdio_ctrl.mutex );
+	for( device = TAILQ_FIRST( &sdio_ctrl.dlist ); device != NULL; device = TAILQ_NEXT( device, dlink ) ) {
+		if( !memcmp( &device->instance, instance, sizeof( sdio_device_instance_t ) ) ) {
+			break;
+		}
+	}
+	pthread_mutex_unlock( &sdio_ctrl.mutex );
+
+	return( device );
+}
+
+void *sdio_client_hdl( struct sdio_device *device )
+{
+	return( device->user );
+}
+
+void *sdio_bs_hdl( struct sdio_device *device )
+{
+	return( device->dev->hc->bs_hdl );
+}
+
+sdio_cid_t *sdio_get_cid( struct sdio_device *device )
+{
+	return( &device->dev->cid );
+}
+
+void *sdio_get_raw_cid( struct sdio_device *device )
+{
+	return( &device->dev->raw_cid );
+}
+
+sdio_csd_t *sdio_get_csd( struct sdio_device *device )
+{
+	return( &device->dev->csd );
+}
+
+void *sdio_get_raw_csd( struct sdio_device *device )
+{
+	return( &device->dev->raw_csd );
+}
+
+sdio_ecsd_t *sdio_get_ecsd( struct sdio_device *device )
+{
+	return( &device->dev->ecsd );
+}
+
+void *sdio_get_raw_ecsd( struct sdio_device *device )
+{
+	return( &device->dev->raw_ecsd );
+}
+
+void *sdio_get_raw_scr( struct sdio_device *device )
+{
+	return( &device->dev->raw_scr );
+}
+
+int sdio_verbosity( struct sdio_device *device, uint32_t flags, int verbosity )
+{
+	sdio_hc_t		*hc;
+
+	hc					= device->dev->hc;
+	hc->cfg.flags		= flags;
+	hc->cfg.verbosity	= verbosity;
+	return( EOK );
+}
+
+struct sdio_cmd *sdio_alloc_cmd( void )
+{
+	struct sdio_cmd		*cmd;
+
+	pthread_mutex_lock( &sdio_ctrl.mutex );
+	if( ( cmd = TAILQ_FIRST( &sdio_ctrl.clist ) ) ) {
+		TAILQ_REMOVE( &sdio_ctrl.clist, cmd, clink );
+		memset( cmd, 0, sizeof( struct sdio_cmd ) );
+	}
+	else {
+		cmd = calloc( 1, sizeof( struct sdio_cmd ) );
+	}
+	pthread_mutex_unlock( &sdio_ctrl.mutex );
+	return( cmd );
+}
+
+void sdio_free_cmd( struct sdio_cmd *cmd )
+{
+	pthread_mutex_lock( &sdio_ctrl.mutex );
+	TAILQ_INSERT_TAIL( &sdio_ctrl.clist, cmd, clink );
+	pthread_mutex_unlock( &sdio_ctrl.mutex );
+}
+
+int	sdio_cmd_status( struct sdio_cmd *cmd, uint32_t *status, uint32_t *rsp )
+{
+	if( status ) {
+		*status = cmd->status;
+	}
+
+	if( rsp ) {
+		memcpy( rsp, cmd->rsp, sizeof( cmd->rsp ) );
+	}
+
+	return( EOK );
+}
+
+int sdio_setup_cmd_ext( struct sdio_cmd *cmd, uint32_t flgs, uint32_t op, uint32_t arg, uint32_t earg )
+{
+	cmd->opcode		= op;
+	cmd->arg		= arg;
+	cmd->earg		= earg;
+	cmd->flags		= flgs;
+
+	return( EOK );
+}
+
+int sdio_setup_cmd( struct sdio_cmd *cmd, uint32_t flgs, uint32_t op, uint32_t arg )
+{
+	return( sdio_setup_cmd_ext( cmd, flgs, op, arg, 0 ) );
+}
+
+int sdio_setup_cmd_io( struct sdio_cmd *cmd, uint32_t flgs, uint32_t blks, uint32_t blksz, void *sgl, uint32_t sgc, void *mhdl )
+{
+	cmd->mhdl		= mhdl;
+	cmd->flags		|= flgs;
+	cmd->blks		= blks;
+	cmd->blksz		= blksz;
+	cmd->sgl		= sgl;
+	cmd->sgc		= sgc;
+
+	return( EOK );
+}
+
+int sdio_send_cmd( struct sdio_device *device, struct sdio_cmd *cmd,
+		void (*func)( struct sdio_device *, struct sdio_cmd *, void *),
+		uint32_t timeout, int retries )
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status =_sdio_send_cmd( device->dev, cmd, func, timeout, retries );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_stop_transmission( struct sdio_device *device, int hpi )
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = _sdio_stop_transmission( device->dev, hpi );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_set_partition( struct sdio_device *device, uint32_t partition )
+{
+	sdio_dev_t	*dev;
+	int			status;
+
+	dev = device->dev;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = ( dev->dtype == DEV_TYPE_MMC ) ? mmc_set_partition( dev, partition ) : EOK;
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_set_block_count( struct sdio_device *device, int blkcnt, uint32_t flgs )
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = _sdio_set_block_count( device->dev, blkcnt, flgs );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_set_block_length( struct sdio_device *device, int blklen )
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = _sdio_set_block_length( device->dev, blklen );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_sd_switch( struct sdio_device *device, int mode, int grp, uint8_t val, uint8_t *switch_status )
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = sd_switch( device->dev, mode, grp, val, switch_status );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_mmc_switch( struct sdio_device *device, uint32_t cmdset, uint32_t mode, uint32_t index, uint32_t value, uint32_t timeout )
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = mmc_switch( device->dev, cmdset, mode, index, value, timeout );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_mmc_rpmb_rw( struct sdio_device *device, void *pf, int nf, int flgs )
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = mmc_rpmb_rw( device->dev, pf, nf, flgs );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_mmc_gen_man( struct sdio_device *device, uint8_t op, void *buf, int blklen, int blkcnt, uint32_t arg, uint32_t flgs)
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = mmc_gen_man_cmd( device->dev, op, buf, blklen, blkcnt, arg, flgs );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_send_ext_csd( struct sdio_device *device, uint8_t *csd )
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = mmc_send_ext_csd( device->dev, csd );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_wait_card_status( struct sdio_device *device, uint32_t *rsp, uint32_t mask, uint32_t val, uint32_t msec )
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = _sdio_wait_card_status( device->dev, rsp, mask, val, msec );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_send_status( struct sdio_device *device, uint32_t *rsp, int hpi )
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = _sdio_send_status( device->dev, rsp, hpi );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_retune( struct sdio_device *device )
+{
+	sdio_hc_t	*hc;
+	int			status;
+
+	hc	= device->hc;
+
+	if( !( hc->flags & HC_FLAG_TUNE ) ) {
+		return( EOK );
+	}
+
+	if( !( hc->device.flags & DEV_FLAG_PRESENT ) || ( hc->flags & HC_FLAG_RST ) ) {
+		atomic_clr( &hc->flags, HC_FLAG_TUNE );
+		return( EOK );
+	}
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = _sdio_retune( hc );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_hpi( struct sdio_device *device, uint32_t timeout )
+{
+	int			status;
+	uint32_t	rsp[4];
+
+	status = sdio_wait_card_status( device, rsp, CDS_READY_FOR_DATA | CDS_CUR_STATE_MSK, CDS_READY_FOR_DATA | CDS_CUR_STATE_TRAN, timeout );
+	if( status == ETIMEDOUT ) {
+		if( ( device->dev->caps & DEV_CAP_HPI_CMD12 ) ) {
+			status = sdio_stop_transmission( device, SDIO_TRUE );
+		}
+		else {
+			status = sdio_send_status( device, rsp, SDIO_TRUE );
+		}
+		if( status == EOK ) {
+			status = sdio_wait_card_status( device, rsp, CDS_READY_FOR_DATA | CDS_CUR_STATE_MSK, CDS_READY_FOR_DATA | CDS_CUR_STATE_TRAN, MMC_OUT_OF_INTERRUPT_TIMEOUT * device->dev->raw_ecsd[ECSD_OUT_OF_INTERRUPT_TIME] );
+		}
+	}
+	return( status );
+}
+
+int sdio_hc_info( struct sdio_device *device, sdio_hc_info_t *info )
+{
+	sdio_hc_t		*hc;
+
+	hc					= device->dev->hc;
+
+	info->caps			= hc->caps & 0xffffffffULL;
+	info->sg_max		= hc->cfg.sg_max;
+	info->dtr_max		= hc->clk_max;
+	info->dtr			= hc->clk;
+	info->timing		= hc->timing;
+	info->bus_width		= hc->bus_width;
+	info->idle_time		= hc->cfg.idle_time;
+	info->sleep_time	= hc->cfg.sleep_time;
+	strlcpy( info->name, hc->cfg.name, sizeof( info->name ) );
+
+	return( EOK );
+}
+
+int sdio_dev_info( struct sdio_device *device, sdio_dev_info_t *info )
+{
+	sdio_hc_t		*hc;
+	sdio_dev_t		*dev;
+	sdio_cid_t		*cid;
+	sdio_csd_t		*csd;
+	sdio_ecsd_t		*ecsd;
+
+	dev				= device->dev;
+	hc				= dev->hc;
+	cid				= &dev->cid;
+	csd				= &dev->csd;
+	ecsd			= &dev->ecsd;
+
+	memset( info, 0, sizeof( sdio_dev_info_t ) );
+
+	info->dtype		= dev->dtype;
+	info->rca		= dev->rca;
+
+	if( csd->write_protect || !( csd->ccc & CCC_BLOCK_WRITE ) || ( dev->flags & DEV_FLAG_WRITE_PROTECT ) ) {
+		info->flags |= DEV_FLAG_WP;
+	}
+
+	if( ( dev->flags & DEV_FLAG_LOCKED ) ) {
+		info->flags |= DEV_FLAG_CARD_LOCKED;
+	}
+
+	info->mid		= cid->mid;
+	info->oid		= cid->oid;
+	info->prv		= cid->prv;
+	info->psn		= cid->psn;
+	info->month		= cid->month;
+	info->year		= cid->year;
+	memcpy( info->pnm, cid->pnm, sizeof( cid->pnm ) );
+
+	info->caps					= dev->caps;
+
+	info->sector_size			= csd->blksz;
+	info->native_sector_size	= SDIO_BLKSZ_4K;
+	info->sectors				= csd->sectors;
+	info->super_page_size		= SDIO_BLKSZ_4K;
+
+	if( dev->dtype == DEV_TYPE_MMC ) {
+		if( ( csd->spec_vers >= CSD_SPEC_VER_4 ) && ecsd->sectors ) {
+			info->sectors			= ecsd->sectors;
+			info->sector_size		= ecsd->blksz;
+			info->super_page_size	= ecsd->acc_size;
+		}
+		info->spec_vers			= dev->csd.spec_vers;
+		info->spec_rev			= ecsd->ext_csd_rev;
+	}
+	else {
+		info->spec_vers			= dev->scr.sd_spec;
+		info->security			= dev->scr.sd_security;
+		info->speed_class		= dev->sds.speed_class;
+	}
+
+	info->wp_size				= dev->wp_size;
+	info->erase_size			= dev->erase_size;
+
+	info->rel_wr_sec_c			= dev->rel_wr_sec_c;
+
+	info->optimal_trim_size		= info->super_page_size;
+	info->optimal_read_size		= info->super_page_size;
+	info->optimal_write_size	= info->super_page_size;
+
+	info->dtr					= hc->clk;
+	info->timing				= hc->timing;
+	info->bus_width				= hc->bus_width;
+
+	return( EOK );
+}
+
+int sdio_cache( struct sdio_device *device, int op, uint32_t timeout )
+{
+	sdio_dev_t	*dev;
+	int			status;
+
+	dev = device->dev;
+
+	if( !( dev->caps & DEV_CAP_CACHE ) ) {
+		return( ENOTSUP );
+	}
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = _sdio_cache( dev, op, timeout );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_pwroff_notify( struct sdio_device *device, int op, int timeout )
+{
+	sdio_dev_t	*dev;
+	int			status;
+
+	dev = device->dev;
+
+	if( !( dev->caps & DEV_CAP_PWROFF_NOTIFY ) ) {
+		return( EOK );
+	}
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	if( ( dev->dtype == DEV_TYPE_MMC ) ) {
+		status = mmc_pwroff_notify( dev, op, timeout );
+	}
+	else {
+		status = sd_pwroff_notify( dev, op, timeout );
+	}
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_erase( struct sdio_device *device, int partition, int flgs, uint64_t lba, int nlba )
+{
+	sdio_dev_t	*dev;
+	int			status;
+
+	dev = device->dev;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	if( ( dev->dtype == DEV_TYPE_MMC ) ) {
+		status = mmc_erase( dev, partition, flgs, lba, nlba );
+	}
+	else {
+		status = sd_erase( dev, flgs, lba, nlba );
+	}
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_lock_unlock( struct sdio_device *device, int action, uint8_t *pwd, int pwd_len )
+{
+	sdio_dev_t	*dev;
+	int			status;
+
+	dev = device->dev;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	if( ( dev->dtype == DEV_TYPE_MMC ) ) {
+		status = EINVAL;
+	}
+	else {
+		status = sd_lock_unlock( dev, action, pwd, pwd_len );
+	}
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_bus_error( struct sdio_device *device )
+{
+	int				status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	_sdio_bus_error( device->dev );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_reset( struct sdio_device *device )
+{
+	sdio_dev_t		*dev;
+	int				status;
+
+	dev		= device->dev;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	_sdio_reset( dev );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_idle( struct sdio_device *device )
+{
+	int		status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+//	status = _sdio_idle( device->dev );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_pwrmgnt( struct sdio_device *device, int action )
+{
+	int		status;
+
+	status = _sdio_synchronize( device, !0, 1 );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	status = _sdio_pwrmgnt( device->dev, action );
+
+	_sdio_synchronize( device, !0, -1 );
+
+	return( status );
+}
+
+int sdio_detach( struct sdio_device *device )
+{
+	if( device->usage ) {
+		return( EBUSY );
+	}
+
+	pthread_mutex_lock( &sdio_ctrl.mutex );
+	TAILQ_REMOVE( &sdio_ctrl.dlist, device, dlink );
+	pthread_mutex_unlock( &sdio_ctrl.mutex );
+
+	free( device );
+
+	return( EOK );
+}
+
+int sdio_attach( struct sdio_connection *connection,
+					sdio_device_instance_t *instance,
+					struct sdio_device **hdl,
+					void *client_hdl )
+{
+	sdio_hc_t				*hc;
+	struct sdio_device		*device;
+
+	device = NULL;
+	pthread_mutex_lock( &sdio_ctrl.mutex );
+	for( hc = TAILQ_FIRST( &sdio_ctrl.hlist ); hc; hc = TAILQ_NEXT( hc, hlink ) ) {
+		if( ( hc->path == instance->path ) && ( hc->device.flags & DEV_FLAG_PRESENT ) ) {
+			if( ( instance->generation == SDIO_CONNECT_WILDCARD ) ||
+					( instance->generation == hc->generation ) ) {
+				break;
+			}
+		}
+	}
+
+	if( hc != NULL ) {
+		device = calloc( 1, sizeof( struct sdio_device ) );
+		if( device != NULL ) {
+			TAILQ_INSERT_TAIL( &sdio_ctrl.dlist, device, dlink );
+			instance->path			= hc->path;
+			instance->func			= 0;
+			instance->generation	= hc->generation;
+			instance->ident.vid		= 0;
+			instance->ident.did		= 0;
+			instance->ident.ccd		= 0;
+			instance->ident.dtype	= (uint16_t)hc->device.dtype;
+
+			memcpy( &device->instance, instance, sizeof( sdio_device_instance_t ) );
+			device->user	= client_hdl;
+			device->hc		= hc;
+			device->dev		= &hc->device;
+			*hdl			= device;
+		}
+	}
+
+	pthread_mutex_unlock( &sdio_ctrl.mutex );
+
+	return( device ? EOK : ENODEV );
+}
+
+int sdio_enum( struct sdio_connection *connection, int action )
+{
+	connection = connection;
+
+	pthread_sleepon_lock( );
+	sdio_ctrl.cd_enum = action;
+	pthread_sleepon_signal( &sdio_ctrl.cd_enum );
+	pthread_sleepon_unlock( );
+
+	return( EOK );
+}
+
+int sdio_disconnect( struct sdio_connection *connection )
+{
+	connection = connection;
+
+	return( _sdio_disconnect( ) );
+}
+
+int sdio_connect( sdio_connect_parm_t *parm, struct sdio_connection **connection )
+{
+	*connection		= (void *)&sdio_ctrl;
+
+	memcpy( &sdio_ctrl.connect_parm, parm, sizeof( sdio_connect_parm_t ) );
+
+	return( _sdio_connect( parm, connection ) );
+}
+
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/card.c $ $Rev: 982571 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/hc/dwmshc.h

@@ -0,0 +1,338 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2008, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef _DW_MSHC_H_
+#define _DW_MSHC_H_
+
+#include <internal.h>
+
+#define DW_MSH_SIZE				0x4000
+
+#define DW_MS_ITER				8
+#define DW_ROR8( _w, _s )		( ( (_w) >> (_s) ) | ( (_w) << (8 - (_s) ) ) )
+
+#define DW_TUNING_RETRIES		40
+#define DW_TUNING_TIMEOUT		150
+
+#define DW_CLKGEN_DIVRATIO		2
+
+#define DW_CTRL					0x000			// Control Register
+	#define DW_CTRL_USE_IDMAC		(1 << 25)
+	#define DW_CTRL_CEATA_INT_EN	(1 << 11)
+	#define DW_CTRL_SEND_AS_CCSD	(1 << 10)
+	#define DW_CTRL_SEND_CCSD		(1 << 9)
+	#define DW_CTRL_ABRT_READ_DATA	(1 << 8)
+	#define DW_CTRL_SEND_IRQ_RESP	(1 << 7)
+	#define DW_CTRL_READ_WAIT		(1 << 6)
+	#define DW_CTRL_DMA_ENABLE		(1 << 5)
+	#define DW_CTRL_INT_ENABLE		(1 << 4)
+	#define DW_CTRL_DMA_RESET		(1 << 2)
+	#define DW_CTRL_FIFO_RESET		(1 << 1)
+	#define DW_CTRL_RESET			(1 << 0)
+	#define DW_CTRL_RESET_ALL		( DW_CTRL_RESET | DW_CTRL_FIFO_RESET | DW_CTRL_DMA_RESET )
+
+#define DW_PWREN				0x004
+	#define DW_PWREN_POWER_ENABLE	( 1 << 0 )
+
+#define DW_CLKDIV				0x008
+#define DW_CLKSRC				0x00c
+
+#define DW_CLKENA				0x010
+	#define DW_CLKEN_LOW_PWR		(1 << 16)
+	#define DW_CLKEN_ENABLE			(1 << 0)
+
+#define DW_TMOUT				0x014
+	#define DW_TMOUT_DATA(n)		((n) << 8)
+	#define DW_TMOUT_DATA_MSK		0xFFFFFF00
+	#define DW_TMOUT_DATA_MAX		0xFFFFFF00
+	#define DW_TMOUT_RESP(n)		((n) & 0xFF)
+	#define DW_TMOUT_RESP_MSK		0xFF
+	#define DW_TMOUT_RESP_MAX		0xFF
+
+#define DW_CTYPE				0x018
+	#define DW_CTYPE_8BIT			(1 << 16)
+	#define DW_CTYPE_4BIT			(1 << 0)
+	#define DW_CTYPE_1BIT			0
+
+#define DW_BLKSIZ				0x01c
+#define DW_BYTCNT				0x020
+#define DW_INTMASK				0x024
+#define DW_CMDARG				0x028
+#define DW_CMD					0x02c
+	#define DW_CMD_START			(1 << 31)
+	#define DW_CMD_USE_HOLD_REG		(1 << 29)
+	#define DW_CMD_VOLT_SWITCH		(1 << 28)
+	#define DW_CMD_CCS_EXP			(1 << 23)
+	#define DW_CMD_CEATA_RD			(1 << 22)
+	#define DW_CMD_UPD_CLK			(1 << 21)
+	#define DW_CMD_INIT				(1 << 15)
+	#define DW_CMD_STOP				(1 << 14)
+	#define DW_CMD_PRV_DAT_WAIT		(1 << 13)
+	#define DW_CMD_SEND_STOP		(1 << 12)
+	#define DW_CMD_STRM_MODE		(1 << 11)
+	#define DW_CMD_DAT_WR			(1 << 10)
+	#define DW_CMD_DAT_EXP			(1 << 9)
+	#define DW_CMD_RESP_CRC			(1 << 8)
+	#define DW_CMD_RESP_LONG		(1 << 7)
+	#define DW_CMD_RESP_EXP			(1 << 6)
+	#define DW_CMD_INDX(n)			((n) & 0x1F)
+
+#define DW_RESP0				0x030
+#define DW_RESP1				0x034
+#define DW_RESP2				0x038
+#define DW_RESP3				0x03c
+
+#define DW_MINTSTS				0x040
+#define DW_RINTSTS				0x044
+	#define DW_INT_SDIO(n)		((1 << 16) + (n))
+	#define DW_INT_EBE			(1 << 15)		// End Bit Error
+	#define DW_INT_ACD			(1 << 14)		// Auto Command Done
+	#define DW_INT_SBE			(1 << 13)		// Start Bit Error
+	#define DW_INT_HLE			(1 << 12)		// Hardware Locked Write Error
+	#define DW_INT_FRUN			(1 << 11)		// FIFO underrun/overrun error
+	#define DW_INT_HTO			(1 << 10)		// Data starvation by Host Timeout
+	#define DW_INT_VOLT_SWITCH	(1 << 10)		// Voltage Switch (same as HTO)
+	#define DW_INT_DRTO			(1 << 9)		// Data Read Timeout
+	#define DW_INT_RTO			(1 << 8)		// Response Timeout
+	#define DW_INT_DCRC			(1 << 7)		// Data CRC Error
+	#define DW_INT_RCRC			(1 << 6)		// Response CRC Error
+	#define DW_INT_RXDR			(1 << 5)		// Receive FIFO Data Request
+	#define DW_INT_TXDR			(1 << 4)		// Transmit FIFO Data Request
+	#define DW_INT_DTO			(1 << 3)		// Data Transfer Over
+	#define DW_INT_CD			(1 << 2)		// Command Done
+	#define DW_INT_RE			(1 << 1)		// Response Error
+	#define DW_INT_CDET			(1 << 0)		// Card Detect
+	#define DW_INT_ERRORS		( DW_INT_RCRC | DW_INT_DCRC |	\
+									DW_INT_RTO | DW_INT_DRTO | DW_INT_HTO |		\
+									DW_INT_FRUN | DW_INT_HLE | DW_INT_SBE |		\
+									DW_INT_EBE )
+	#define DW_INT_DFLTS		( DW_INT_ERRORS | DW_INT_CDET )
+
+
+#define DW_STATUS					0x048
+	#define DW_STATUS_FIFO_COUNT( _x )	( ( ( _x ) >> 17 ) & 0x1FFF )
+	#define DW_STATUS_FIFO_FULL			(1 << 3)
+	#define DW_STATUS_FIFO_EMPTY		(1 << 2)
+
+#define DW_FIFOTH					0x04c
+      	#define DW_FIFOTH_RX_WMARK( _fifoth )	( ( ( _fifoth ) >> 16 ) & 0xfff )
+	#define DW_FIFOTH_RX_WMARK_SHFT			16
+	#define DW_FIFOTH_MSIZE_1				(0<<28)
+	#define DW_FIFOTH_MSIZE_4				(1<<28)
+	#define DW_FIFOTH_MSIZE_8				(2<<28)
+	#define DW_FIFOTH_MSIZE_16				(3<<28)
+	#define DW_FIFOTH_MSIZE_32				(4<<28)
+	#define DW_FIFOTH_MSIZE_64				(5<<28)
+	#define DW_FIFOTH_MSIZE_128				(6<<28)
+	#define DW_FIFOTH_MSIZE_256				(7<<28)
+	#define DW_FIFO_SZ_128					0x80
+	#define DW_FIFO_SZ_32					0x20
+
+#define DW_CDETECT					0x050
+#define DW_WRTPRT					0x054
+#define DW_GPIO						0x058
+#define DW_TCBCNT					0x05c
+#define DW_TBBCNT					0x060
+#define DW_DEBNCE					0x064
+	#define DW_DEBNCE_25MS			0xffffff
+
+#define DW_USRID					0x068
+#define DW_VERID					0x06c
+	#define DW_VERID_CID(_x)		( (_x) >> 16 )
+	#define DW_VERID_CREV(_x)		( (_x) & 0xffff )
+	#define DW_VERID_CREV_240A		0x240a
+
+#define DW_HCON						0x070
+	#define DW_HCON_DATA_WIDTH( _hcon )		( ( ( _hcon ) >> 7 ) & 0x7 )
+	#define DW_HCON_DATA_WIDTH16			0x00
+	#define DW_HCON_DATA_WIDTH32			0x01
+	#define DW_HCON_DATA_WIDTH64			0x02
+
+#define DW_HCON_NUM_CARD( _hcon )		( ( ( _hcon ) >> 1 ) & 0x1f )
+
+#define DW_UHS_REG					0x074
+	#define DW_DDR(_x)				( ( 1 << ((_x) + 16) ) )
+	#define DW_DDR_REG_MSK(_x)		( ~( 1 << ((_x) + 16) ) )
+	#define DW_VOLT_1_8(_x)			( ( 1 << (_x) ) )
+	#define DW_VOLT_REG_MSK(_x)		( ~( 1 << (_x) ) )
+
+#define DW_RST						0x078
+	#define DW_RST_ACTIVE			0x01
+
+#define DW_BMOD						0x080			// Bus Mode
+	#define DW_IDMAC_ENABLE			(1 << 7)
+	#define DW_IDMAC_FB				(1 << 1)
+	#define DW_IDMAC_SWRESET		(1 << 0)
+
+#define DW_PLDMND					0x084
+	#define DW_PLDMND_PD			1
+
+#define DW_DBADDR					0x088
+
+#define DW_IDSTS					0x08c
+	#define DW_IDSTS_FSM_MSK			(0xf << 13)
+	#define DMAC_FSM_DMA_IDLE			(0 << 13)
+	#define DMAC_FSM_DMA_SUSPEND		(1 << 13)
+	#define DMAC_FSM_DESC_RD			(2 << 13)
+	#define DMAC_FSM_DESC_CHK			(3 << 13)
+	#define DMAC_FSM_DMA_RD_REQ_WAIT	(4 << 13)
+	#define DMAC_FSM_DMA_WR_REQ_WAIT	(5 << 13)
+	#define DMAC_FSM_DMA_RD				(6 << 13)
+	#define DMAC_FSM_DMA_WR				(7 << 13)
+	#define DMAC_FSM_DESC_CLOSE			(8 << 13)
+
+#define DW_IDINTEN					0x090	// Internal DMAC Interrupt Enable
+	#define DW_IDMAC_INT_AI			(1 << 9)
+	#define DW_IDMAC_INT_NI			(1 << 8)
+	#define DW_IDMAC_INT_CES		(1 << 5)
+	#define DW_IDMAC_INT_DU			(1 << 4)
+	#define DW_IDMAC_INT_FBE		(1 << 2)
+	#define DW_IDMAC_INT_RI			(1 << 1)
+	#define DW_IDMAC_INT_TI			(1 << 0)
+	#define DW_IDMAC_INT_MSK		(	DW_IDMAC_INT_TI | DW_IDMAC_INT_RI |	\
+										DW_IDMAC_INT_FBE | DW_IDMAC_INT_DU	| \
+										DW_IDMAC_INT_CES | DW_IDMAC_INT_NI	| \
+										DW_IDMAC_INT_AI )
+
+#define DW_DSCADDR					0x094
+#define DW_BUFADDR					0x098
+#define DW_CLKSEL					0x09c
+	#define DW_DIVRATIO_MSK			0x07
+	#define DW_DIVRATIO_SHFT		24
+	#define DW_CLK_SMPL_MSK			0x07
+	#define DW_CLK_SMPL_MAX			0x07
+
+#define DW_CARDTHRCTL				0x100
+	#define DW_CARDTHRCTL_EN		(1 << 0)
+	#define DW_CARDTHRCTL_THRES(_x)	( (_x) << 16 )
+
+#define DW_BACK_END_POWER			0x104
+#define DW_EMMC_DDR_REG				0x10c
+#define DW_DDR200_RDDQS_EN			0x110
+#define DW_DDR200_ASYNC_FIFO_CTRL	0x114
+#define DW_DDR200_DLINE_CTRL		0x118
+
+//#define DW_DATA_220A				0x100
+#define DW_DATA_240A				0x200
+#define DW_DATA				(DW_DATA_240A)
+
+typedef struct _dw_idmac_desc {
+	uint32_t		des0;				// Control Descriptor
+#define IDMAC_DES0_DIC	(1 << 1)		// Disable Interrupt on Completion
+#define IDMAC_DES0_LD	(1 << 2)		// Last Descriptor
+#define IDMAC_DES0_FD	(1 << 3)		// First Descriptor
+#define IDMAC_DES0_CH	(1 << 4)		// Second Address Chained
+#define IDMAC_DES0_ER	(1 << 5)		// End of Ring
+#define IDMAC_DES0_CES	(1 << 30)		// Card Error Summary
+#define IDMAC_DES0_OWN	(1 << 31)		// IDMAC Descriptor Owned
+
+	uint32_t		des1;				// Buffer Sizes 1 & 2
+
+	uint32_t		des2;				// Buffer Address Pointer 1
+
+	uint32_t		des3;				// Buffer Address Pointer 2
+} dw_idmac_desc_t;
+
+
+typedef	struct _dw_hc_msh {
+	void			*bshdl;
+
+#define MF_SEND_INIT_STREAM			0x01
+#define MF_XFER_DMA					0x02
+	uint32_t		flags;
+
+	uint32_t		ncards;
+	uint32_t		cardno;
+
+	uint32_t		fifo_size;
+	uint32_t		divratio;
+	uint32_t		dshft;
+
+	uint64_t		sclk;
+
+	uint32_t		sdr;				// CLKSEL values sdr/ddr
+	uint32_t		ddr;
+
+	uintptr_t		base;
+	uintptr_t		pbase;
+
+	uint32_t		xlen;
+
+#define DW_DMA_DESC_MAX		256
+	sdio_sge_t		sgl[DW_DMA_DESC_MAX];
+
+#define IDMA_MAX_XFER    0x1000				// 4k max
+	dw_idmac_desc_t	*idma;
+	uint32_t		idmap;
+
+// PIO data ins/outs fcns (depends on data width)
+	void			*(*dins)( void *__buff, unsigned __len, _Uintptrt __addr );
+	void			*(*douts)( const void *__buff, unsigned __len, _Uintptrt __addr );
+} dw_hc_msh_t;
+
+static __inline__ _Uint64t __attribute__((__unused__))
+dw_in64(_Uintptrt __addr)
+{
+	_Uint64t        __data;
+
+	__data = *(volatile _Uint64t *)__addr;
+	return(__data);
+}
+
+static __inline__ void __attribute__((__unused__))
+dw_out64(_Uintptrt __addr, _Uint64t __data)
+{
+	*(volatile _Uint64t *)__addr = __data;
+}
+
+static __inline__ void * __attribute__((__unused__))
+dw_out64s(const void *__buff, unsigned __len, _Uintptrt __addr)
+{
+	_Uint64t        *__p = (_Uint64t *)__buff;
+
+	while(__len > 0) {
+		*(volatile _Uint64t *)__addr = *__p++;
+		--__len;
+	}
+	return(__p);
+}
+
+static __inline__ void * __attribute__((__unused__))
+dw_in64s(void *__buff, unsigned __len, _Uintptrt __addr)
+{
+	_Uint64t	*__p = __buff;
+
+	while(__len > 0) {
+		*__p++ = *(volatile _Uint64t *)__addr;
+		--__len;
+	}
+	return(__p);
+}
+
+extern int dw_init( sdio_hc_t *hc );
+extern int dw_dinit( sdio_hc_t *hc );
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/hc/dwmshc.h $ $Rev: 993163 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/hc/imx8_hc.h

@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2013, 2023, BlackBerry Limited.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2017, 2019-2021, NXP.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ *
+ */
+
+#ifndef IMX_HC_H_
+#define IMX_HC_H_
+
+#include <internal.h>
+
+/**
+ * Host controller interface
+ *
+ * @file       hc/imx8_hc.h
+ * @addtogroup sdmmc_hc
+ * @{
+ */
+
+/* A0 Detection code enums - will be removed in production code. */
+enum imx_chip_type_list {
+    IMX_CHIP_TYPE_QUAD_MAX = 0x01,
+    IMX_CHIP_TYPE_QUAD_X_PLUS = 0x02,
+};
+enum imx_chip_rev_list {
+    IMX_CHIP_REV_A = 0x00,
+    IMX_CHIP_REV_B = 0x01,
+};
+
+/** USDHC peripheral input clock */
+#define IMX_USDHC_CLOCK_DEFAULT         198000000
+
+#ifndef IMX_USDHC_SIZE
+    #define IMX_USDHC_SIZE              0x10000
+#endif
+
+/** USDHC driver common defines */
+#define IMX_USDHC_TUNING_RETRIES        40
+#define IMX_USDHC_TUNING_TIMEOUT        150
+#define IMX_USDHC_CLOCK_TIMEOUT         10000
+#define IMX_USDHC_COMMAND_TIMEOUT       1000000  /* The card could take very long time to process the transfered data */
+#define IMX_USDHC_TRANSFER_TIMEOUT      1000000
+
+/** 32 bit ADMA descriptor definition */
+typedef struct _imx_usdhc_adma32_t {
+    uint16_t    attr;
+    uint16_t    len;
+    uint32_t    addr;
+} imx_usdhc_adma32_t;
+
+/** ADMA2 defines */
+#define IMX_USDHC_ADMA2_MAX_XFER        (1024 * 60)
+#define IMX_USDHC_ADMA2_VALID           (1 << 0)        /* Valid */
+#define IMX_USDHC_ADMA2_END             (1 << 1)        /* End of descriptor, transfer complete interrupt will be generated */
+#define IMX_USDHC_ADMA2_INT             (1 << 2)        /* Generate DMA interrupt, will not be used */
+#define IMX_USDHC_ADMA2_NOP             (0 << 4)        /* No OP, go to the next descriptor */
+#define IMX_USDHC_ADMA2_SET             (1 << 4)        /* No OP, go to the next descriptor */
+#define IMX_USDHC_ADMA2_TRAN            (2 << 4)        /* Transfer data */
+#define IMX_USDHC_ADMA2_LINK            (3 << 4)        /* Link to another descriptor */
+#define ADMA_DESC_MAX                   256
+
+/* Defines for flags field from 'Processor specific structure' */
+#define SF_USE_SDMA     0x01
+#define SF_USE_ADMA     0x02
+#define SF_TUNE_SDR50   0x04
+#define SF_SDMA_ACTIVE  0x10
+
+/* Define for common initialization delay
+ * Setting the lower delay will reduce driver startup
+ * time. Side effects have been observed on certain SD
+ * cards from the lower initialization delay,
+ * so we recommend leaving the full delay in unless you
+ * know you need a quicker startup. Ongoing (runtime) performance
+ * is unaffected. */
+#define FULL_DELAY 1
+#ifdef FULL_DELAY
+#define IMX_INIT_DELAY (delay(1))
+#else
+#define IMX_INIT_DELAY (nanospin_ns(100000L))
+#endif
+
+/** Processor specific structure */
+typedef struct _imx_usdhcx_hc {
+    void                *bshdl;
+    uintptr_t           base;
+    int                 fd;
+    imx_usdhc_adma32_t* adma;
+    uint32_t            admap;
+    sdio_sge_t          sgl[ADMA_DESC_MAX];
+    uint32_t            flags;
+    int                 sdma_iid;       /**< SDMA interrupt id */
+    uintptr_t           sdma_irq;
+    uintptr_t           sdma_base;
+    uint32_t            mix_ctrl;
+    uint32_t            intmask;
+    _Uint64t            usdhc_addr;     /**< Used to determine which controller it belongs to */
+    int                 sdll;           /**< Value to be used in STROBE_DLL_CTRL_SLV_DLY_TARGET field. See RM. for details */
+    imx_usdhc_tuning_t  tuning_mode;    /**< STD or Manual tuning mode */
+    uint16_t            std_step;       /**< STD tuning configuration. Tuning step. */
+    uint16_t            std_start_tap;  /**< STD tuning configuration. Tuning start position. */
+} imx_sdhcx_hc_t;
+
+extern int imx_sdhcx_init(sdio_hc_t *hc);
+extern int imx_sdhcx_dinit(sdio_hc_t *hc);
+
+int imx_sdhcx_host_sdll(sdio_hc_t *hc, unsigned val);
+
+/** @} */ /* End of sdmmc_hc */
+
+#endif /* IMX_HC_H_ */
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/hc/imx8_hc.h $ $Rev: 993066 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/hc/ls10xx.h

@@ -0,0 +1,350 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2017, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef _LS10XX_H_INCLUDED
+#define _LS10XX_H_INCLUDED
+
+#include <internal.h>
+#include <aarch64/ls10xx.h>
+
+#define LS10XX_LOG(hc, severity, fmt, ...)  \
+        sdio_slogf( _SLOGC_SDIODI, (severity), (hc)->cfg.verbosity, (severity) -_SLOG_ERROR,  \
+                            "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
+
+
+// These should be only used for transfereing from/to the data buffer register, and since we set
+// the Endian mode in LS10XX_PCTL to Little Endian, we have to use the LE in/out functions.
+#define ls10xx_sdhcx_data_in32s         (in32s)
+#define ls10xx_sdhcx_data_out32s        (out32s)
+
+#define LS10XX_TUNING_RETRIES           40
+#define LS10XX_CLOCK_TIMEOUT            20000
+#define LS10XX_COMMAND_TIMEOUT          1000000  /* The card could take very long time to process the transfered data */
+#define LS10XX_TRANSFER_TIMEOUT         1000000
+
+#define LS10XX_SIZE                     4096
+#define LS10XX_CLOCK_DEFAULT            250000000
+
+#define LS10XX_DS_ADDR           0x00
+
+#define LS10XX_BLK_ATT           0x04
+    #define LS10XX_BLK_SDMA_BNDRY_512K  ( 3 << 8 )
+    #define LS10XX_BLK_BLKSIZE_MASK     0x00001fff
+    #define LS10XX_BLK_BLKCNT_MASK      0xffff0000
+    #define LS10XX_BLK_BLKCNT_SHIFT     16
+
+#define LS10XX_ARG               0x08
+
+#define LS10XX_CMD               0x0C        // Command and transfer mode register
+    #define LS10XX_CMD_DMAEN             (1 << 0)
+    #define LS10XX_CMD_BCEN              (1 << 1)
+    #define LS10XX_CMD_ACEN_ACMD12       (1 << 2)
+    #define LS10XX_CMD_ACEN_ACMD23       (2 << 2)
+    #define LS10XX_CMD_DTDSEL            (1 << 4)
+    #define LS10XX_CMD_MSBSEL            (1 << 5)
+    #define LS10XX_CMD_RSP_TYPE_136      (1 << 16)    // Response length 136 bit
+    #define LS10XX_CMD_RSP_TYPE_48       (2 << 16)    // Response length 48 bit
+    #define LS10XX_CMD_RSP_TYPE_48b      (3 << 16)    // Response length 48 bit with busy after response
+    #define LS10XX_CMD_CCCE              (1 << 19)    // Comamnd CRC Check Enable
+    #define LS10XX_CMD_CICE              (1 << 20)    // Comamnd Index Check Enable
+    #define LS10XX_CMD_DP                (1 << 21)    // Data Present
+    #define LS10XX_CMD_TYPE_CMD12        (3 << 22)    // CMD12 or CMD52 "I/O Abort"
+
+#define LS10XX_RESP0             0x10
+#define LS10XX_RESP1             0x14
+#define LS10XX_RESP2             0x18
+#define LS10XX_RESP3             0x1C
+
+#define LS10XX_DATA              0x20
+
+#define LS10XX_PSTATE            0x24    // Present State
+    #define LS10XX_PSTATE_DLSL_MSK       (0xFF << 24)
+    //Data line 0 level. Checked for card's busy state after write transaction
+    #define LS10XX_PSTATE_DL3SL          (1 << 27)
+    #define LS10XX_PSTATE_DL2SL          (1 << 26)
+    #define LS10XX_PSTATE_DL1SL          (1 << 25)
+    #define LS10XX_PSTATE_DL0SL          (1 << 24)
+    #define LS10XX_PSTATE_CLSL           (1 << 23)
+    #define LS10XX_PSTATE_WP             (1 << 19)
+    #define LS10XX_PSTATE_CD             (1 << 18)
+    #define LS10XX_PSTATE_CI             (1 << 16)
+    #define LS10XX_PSTATE_BRE            (1 << 11)    // Buffer Read Ready
+    #define LS10XX_PSTATE_BWE            (1 << 10)    // Buffer Write Ready
+    #define LS10XX_PSTATE_RTA            (1 <<  9)    // Read Transfer Active
+    #define LS10XX_PSTATE_WTA            (1 <<  8)    // Write Transfer Active
+    #define LS10XX_PSTATE_SDOFF          (1 <<  7)    // SD clock gated off
+    #define LS10XX_PSTATE_SDSTB          (1 <<  3)    // SD clock stable
+    #define LS10XX_PSTATE_DLA            (1 <<  2)    // data line active
+    #define LS10XX_PSTATE_DATI           (1 <<  1)    // Command inhibit
+    #define LS10XX_PSTATE_CMDI           (1 <<  0)    // Command inhibit
+
+    #define LS10XX_CARD_STABLE           (LS10XX_PSTATE_CD | \
+                                          LS10XX_PSTATE_SDSTB | \
+                                          LS10XX_PSTATE_CI)
+    #define LS10XX_DMA_IDLE              (LS10XX_PSTATE_DL0SL | \
+                                          LS10XX_PSTATE_CLSL_MSK | \
+                                          LS10XX_PSTATE_DATI | \
+                                          LS10XX_PSTATE_CMDI)
+
+
+#define LS10XX_PCTL              0x28    // Protocol Control
+    #define LS10XX_PCTL_DTW1              (0 << 1)    // Data Bus Width 1 bit
+    #define LS10XX_PCTL_DTW4              (1 << 1)    // Data Bus Width 4 bit
+    #define LS10XX_PCTL_DTW8              (2 << 1)    // Data Bus Width 8 bit
+    #define LS10XX_PCTL_BEM               (0 << 4)    // Big endian mode
+    #define LS10XX_PCTL_LEM               (2 << 4)    // little endian mode
+    #define LS10XX_PCTL_CDTL              (1 << 6)    // card detect test level
+    #define LS10XX_PCTL_CDSS              (1 << 7)    // card detect signal sel
+    #define LS10XX_PCTL_DMA_MSK           (3 << 8)    // DMA select mask
+    #define LS10XX_PCTL_SDMA              (0 << 8)    // simple DMA select
+    #define LS10XX_PCTL_ADMA1             (1 << 8)    // ADMA1 select
+    #define LS10XX_PCTL_ADMA2             (2 << 8)    // ADMA2 select
+    #define LS10XX_PCTL_VOLSEL_18V        (1 << 10)    //
+    #define LS10XX_PCTL_SABGREQ           (1 << 16)   // stop at block gap request
+    #define LS10XX_PCTL_CREQ              (1 << 17)   // Continue request
+    #define LS10XX_PCTL_RWCTL             (1 << 18)   // read wait control
+    #define LS10XX_PCTL_IABG              (1 << 19)   // interrupt at block gap
+    #define LS10XX_PCTL_WECINT            (1 << 24)   // wake event enable on interrupt
+    #define LS10XX_PCTL_WECINS            (1 << 25)   // wake event enable on insertion
+    #define LS10XX_PCTL_WECRM             (1 << 26)   // wake event enable on removal
+
+#define LS10XX_SYSCTL            0x2C    // Clock Control/Timeout/Software reset
+    #define LS10XX_SYSCTL_SDCLK_IPGEN     (1 << 0)
+    #define LS10XX_SYSCTL_SDCLK_HCKEN     (1 << 1)
+    #define LS10XX_SYSCTL_SDCLK_PEREN     (1 << 2)
+    #define LS10XX_SYSCTL_SDCLKEN         (1 << 3)
+    #define LS10XX_SYSCTL_DVS_SHIFT       (4)    // clock divisor shift
+    #define LS10XX_SYSCTL_DVS_MSK         (0xf << 4)    // clock divisor
+    #define LS10XX_SYSCTL_SDCLKFS_SHIFT   (8)
+    #define LS10XX_SYSCTL_SDCLKFS_MSK     (0xff << 8)
+    #define LS10XX_SYSCTL_DTO_SHIFT       (16)    // Data timeout counter shift
+    #define LS10XX_SYSCTL_DTO_MSK         (0xf << 16)    // Data timeout counter
+    #define LS10XX_SYSCTL_DTO_MAX         (0xf << 16)    // Timeout = TCF x 2^27
+    #define LS10XX_SYSCTL_SRA             (1 << 24)    // Software reset for all
+    #define LS10XX_SYSCTL_SRC             (1 << 25)    // Software reset for mmci_cmd line
+    #define LS10XX_SYSCTL_SRD             (1 << 26)    // Software reset for mmci_dat line
+    #define LS10XX_SYSCTL_INITA           (1 << 27)    // Initialization active
+
+
+#define LS10XX_IS                0x30    // Interrupt status register
+#define LS10XX_IE                0x34    // Interrupt SD enable register
+#define LS10XX_ISE               0x38    // Interrupt signal enable register
+    #define LS10XX_INTR_CC                (1 <<  0)    // Command Complete
+    #define LS10XX_INTR_TC                (1 <<  1)    // Transfer Complete
+    #define LS10XX_INTR_BGE               (1 <<  2)    // Block Gap Event
+    #define LS10XX_INTR_DMA               (1 <<  3)    // DMA interupt
+    #define LS10XX_INTR_BWR               (1 <<  4)    // Buffer Write Ready interrupt
+    #define LS10XX_INTR_BRR               (1 <<  5)    // Buffer Read Ready interrupt
+    #define LS10XX_INTR_CINS              (1 <<  6)    // Card Insertion
+    #define LS10XX_INTR_CREM              (1 <<  7)    // Card Removal
+    #define LS10XX_INTR_CIRQ              (1 <<  8)    // Card interrupt
+    #define LS10XX_SDCHX_INTR_RETUNE      (1 << 12)    // Re-Tuning
+    #define LS10XX_INTR_CTO               (1 << 16)    // Command Timeout error
+    #define LS10XX_INTR_CCRC              (1 << 17)    // Command CRC error
+    #define LS10XX_INTR_CEB               (1 << 18)    // Command End Bit error
+    #define LS10XX_INTR_CIE               (1 << 19)    // Command Index error
+    #define LS10XX_INTR_DTO               (1 << 20)    // Data Timeout error
+    #define LS10XX_INTR_DCRC              (1 << 21)    // Data CRC error
+    #define LS10XX_INTR_DEB               (1 << 22)    // Data End Bit error
+    #define LS10XX_INTR_ACE               (1 << 24)    // ACMD12 error
+    #define LS10XX_INTR_TNE               (1 << 26)    // Tuning  Error
+    #define LS10XX_INTR_DMAE              (1 << 28)    // DMA Error
+
+    #define LS10XX_IE_DFLTS            (LS10XX_INTR_CTO | LS10XX_INTR_CCRC \
+                                        | LS10XX_INTR_CEB | LS10XX_INTR_CIE \
+                                        | LS10XX_INTR_ACE)
+
+    #define LS10XX_IS_ERRI            (LS10XX_INTR_DMAE \
+                                        | LS10XX_INTR_CCRC | LS10XX_INTR_CTO \
+                                        | LS10XX_INTR_CEB | LS10XX_INTR_CIE \
+                                        | LS10XX_INTR_DTO | LS10XX_INTR_DCRC \
+                                        | LS10XX_INTR_DEB | LS10XX_INTR_ACE)
+    #define LS10XX_ISE_DFLTS           0x117F11FF
+    #define LS10XX_INTR_CLR_ALL        0xffffffff
+
+#define LS10XX_AC12_SYSCTL2      0x3C
+    #define LS10XX_AC12_NE                (1 << 0)
+    #define LS10XX_AC12_TOE               (1 << 1)
+    #define LS10XX_AC12_CE                (1 << 2)
+    #define LS10XX_AC12_EBE               (1 << 3)
+    #define LS10XX_AC12_IE                (1 << 4)
+    #define LS10XX_AC12_CNIB              (1 << 7)
+    #define LS10XX_SYSCTL2_UHSM_MASK      (7 << 16)
+    #define LS10XX_SYSCTL2_UHSM_SDR12     (0 << 16)
+    #define LS10XX_SYSCTL2_UHSM_SDR25     (1 << 16)
+    #define LS10XX_SYSCTL2_UHSM_SDR50     (2 << 16)
+    #define LS10XX_SYSCTL2_UHSM_SDR104    (3 << 16)
+    #define LS10XX_SYSCTL2_UHSM_DDR       (4 << 16)
+    #define LS10XX_SYSCTL2_EXTN           (1 << 22)
+    #define LS10XX_SYSCTL2_SMPCLKSEL      (1 << 23)
+    #define LS10XX_SYSCTL2_AIE            (1 << 30)
+
+
+#define LS10XX_CAP               0x40    // Capability Registers bits 0 to 31
+    #define LS10XX_CAP_S18                (1 << 26)    // 1.8V support
+    #define LS10XX_CAP_S30                (1 << 25)    // 3.0V support
+    #define LS10XX_CAP_S33                (1 << 24)    // 3.3V support
+    #define LS10XX_CAP_SRS                (1 << 23)    // Suspend/Resume support
+    #define LS10XX_CAP_DMA                (1 << 22)    // DMA support
+    #define LS10XX_CAP_HS                 (1 << 21)    // High-Speed support
+    #define LS10XX_CAP_ADMAS              (1 << 20)    // ADMA support
+    #define LS10XX_CAP_MBL512             (0 << 16)    // Max block length 512
+    #define LS10XX_CAP_MBL1024            (1 << 16)    // Max block length 1024
+    #define LS10XX_CAP_MBL2048            (2 << 16)    // Max block length 2048
+
+#define LS10XX_CAP_BASE_CLK( _c, _v )    ( ( ( _v ) >= LS10XX_SPEC_VER_3 ? \
+                                            ( ( ( _c ) >> 8 ) & 0xff ) :            \
+                                            ( ( ( _c ) >> 8 ) & 0x3f ) ) * 1000 * 1000 )
+
+#define LS10XX_WATML             0x44
+  #define LS10XX_WATML_WRBRSTLENSHIFT      24
+  #define LS10XX_WATML_WRBRSTLENMASK       (0x1F << LS10XX_WATML_WRBRSTLENSHIFT)
+  #define LS10XX_WATML_WRWMLSHIFT          16
+  #define LS10XX_WATML_WRWMLMASK           (0xFF << LS10XX_WATML_WRWMLSHIFT)
+  #define LS10XX_WATML_RDBRSTLENSHIFT      8
+  #define LS10XX_WATML_RDBRSTLENMASK       (0x1F << LS10XX_WATML_RDBRSTLENSHIFT)
+  #define LS10XX_WATML_RDWMLSHIFT          0
+  #define LS10XX_WATML_RDWMLMASK           (0xFF << LS10XX_WATML_RDWMLSHIFT)
+  #define LS10XX_WATML_WR                  (16)
+  #define LS10XX_WATML_RD                  (LS10XX_WATML_WR)
+
+#define LS10XX_FORCE_EVENT       0x50
+#define LS10XX_ADMA_ES           0x54
+#define LS10XX_ADMA_ADDR         0x58
+
+#define LS10XX_HOSTVER           0xFC
+    #define LS10XX_HOSTVER_VENDVER_MSK    (0xff << 8)
+    #define LS10XX_HOSTVER_SPECVER_MSK    0xff
+    #define LS10XX_HOSTVER_SPECVER_3      0x2
+    #define LS10XX_HOSTVER_SPECVER_2      0x1
+    #define LS10XX_HOSTVER_SPECVER_1      0x0
+
+#define LS10XX_CAP2              0x114    // Capability Registers bits 0 to 31
+    #define LS10XX_CAP2_RTM               (1 << 14)   // 2 bits
+    #define LS10XX_CAP2_UTSDR50           (1 << 13)
+    #define LS10XX_CAP2_TCRT              (1 << 8)    // 4 bits
+    #define LS10XX_CAP2_DTDS              (1 << 6)
+    #define LS10XX_CAP2_DTCS              (1 << 5)
+    #define LS10XX_CAP2_DTAS              (1 << 4)
+    #define LS10XX_CAP2_DDR50             (1 << 2)
+    #define LS10XX_CAP2_SDR104            (1 << 1)
+    #define LS10XX_CAP2_SDR50             (1 << 0)
+
+#define LS10XX_TUNE_CTRL         0x120
+    #define LS10XX_TUNE_CTRL_ENABLE            (1 << 2)
+    #define LS10XX_TUNE_CTRL_MODE_SW_TUNE      (3 << 0)
+    #define LS10XX_TUNE_CTRL_MODE3_SWT_AUTO    (2 << 0)
+    #define LS10XX_TUNE_CTRL_MODE2_SWT_RETUNE  (1 << 0)
+    #define LS10XX_TUNE_CTRL_MODE1_SWT         (0 << 0)
+    #define LS10XX_TUNE_CTRL_MODE_MASK         (0x3 << 0)
+
+#define LS10XX_TUNE_STAT        0x124
+
+#define LS10XX_TUNE_PTR         0x128
+    #define LS10XX_TUNE_PTR_START_SHIFT        8
+    #define LS10XX_TUNE_PTR_START_MASK         (0x7f << 8)
+    #define LS10XX_TUNE_PTR_END_SHIFT          0
+    #define LS10XX_TUNE_PTR_END_MASK           0x7f
+
+#define LS10XX_CLKCTRL           0x144
+    #define LS10XX_CLKCTRL_CMD_CLKCRTRL        (1 << 15)
+    #define LS10XX_CLKCTRL_LPBK_CLK_DLY_DIR    (1 << 30)
+    #define LS10XX_CLKCTRL_LPBK_CLKSEL         (1 << 31)
+
+
+#define LS10XX_ESDHC_CTRL        0x40C
+    #define LS10XX_ESDHC_CTRL_PCS              (1 << 19)
+    #define LS10XX_ESDHC_CTRL_FAF              (1 << 18)
+    #define LS10XX_ESDHC_CTRL_RTR              (1 << 17)
+    #define LS10XX_ESDHC_CTRL_CRS              (1 << 16)
+    #define LS10XX_ESDHC_CTRL_RD_PREFETCH_CNT_SHIFT 8
+    #define LS10XX_ESDHC_CTRL_PAD_DIS          (1 << 7)
+    #define LS10XX_ESDHC_CTRL_SNOOP            (1 << 6)
+    #define LS10XX_ESDHC_CTRL_WR_BUF           (1 << 3)
+    #define LS10XX_ESDHC_CTRL_RD_SAFE          (1 << 2)
+
+
+#define LS10XX_ADMA2_MAX_XFER    (1024 * 60)
+
+// 32 bit ADMA descriptor defination
+typedef struct _ls10xx_adma32_t {
+    uint16_t    attr;
+    uint16_t    len;
+    uint32_t    addr;
+} ls10xx_adma32_t;
+
+#define LS10XX_ADMA2_VALID                (1 << 0)    // valid
+#define LS10XX_ADMA2_END                  (1 << 1)    // end of descriptor, transfer complete interrupt will be generated
+#define LS10XX_ADMA2_INT                  (1 << 2)    // generate DMA interrupt, will not be used
+#define LS10XX_ADMA2_NOP                  (0 << 4)    // no OP, go to the next desctiptor
+#define LS10XX_ADMA2_SET                  (1 << 4)    // no OP, go to the next desctiptor
+#define LS10XX_ADMA2_TRAN                 (2 << 4)    // transfer data
+#define LS10XX_ADMA2_LINK                 (3 << 4)    // link to another descriptor
+
+
+typedef struct _ls10xx_usdhcx_hc {
+    void            *bshdl;
+    uintptr_t        base;
+    ls10xx_adma32_t *adma;
+    uint32_t         admap;
+#define SF_USE_SDMA            0x01
+#define SF_USE_ADMA            0x02
+#define SF_TUNE_SDR50          0x04
+#define SF_SDMA_ACTIVE         0x10
+#define ADMA_DESC_MAX          256
+    sdio_sge_t       sgl[ADMA_DESC_MAX];
+    uint32_t         flags;
+    int              sdma_iid;    // SDMA interrupt id
+    uintptr_t        sdma_irq;
+    uintptr_t        sdma_base;
+    uint32_t         per_clk;
+    uint32_t         clk_div;
+}ls10xx_hc_t;
+
+static inline uint32_t ls10xx_in32(sdio_hc_t *hc, uint32_t regoff) {
+    ls10xx_hc_t *sdhc = (ls10xx_hc_t *) hc->cs_hdl;
+#ifdef LS10XX_ESDHC_ACCESSES_BE
+    return inbe32(sdhc->base + regoff);
+#else
+    return in32(sdhc->base + regoff);
+#endif
+}
+
+static inline void ls10xx_out32(sdio_hc_t *hc, uint32_t regoff, uint32_t value) {
+    ls10xx_hc_t *sdhc = (ls10xx_hc_t *) hc->cs_hdl;
+#ifdef LS10XX_ESDHC_ACCESSES_BE
+    outbe32(sdhc->base + regoff, value);
+#else
+    out32(sdhc->base + regoff, value);
+#endif
+}
+
+extern int ls10xx_dataLines_wait(sdio_hc_t *hc, uint32_t high);
+extern int ls10xx_clock_set(sdio_hc_t *hc, uint32_t on);
+extern int ls10xx_sdhcx_init( sdio_hc_t *hc );
+extern int ls10xx_sdhcx_dinit( sdio_hc_t *hc );
+
+#endif // _LS10XX_H_INCLUDED
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/hc/ls10xx.h $ $Rev: 970776 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/hc/sdhci.h

@@ -0,0 +1,392 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2008, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef	_SDHCI_H_INCLUDED
+#define	_SDHCI_H_INCLUDED
+
+#include <gulliver.h>
+#include <internal.h>
+
+#if !defined(__X86__) && !defined(__X86_64__)
+
+#define sdhci_in8			(in8)
+#define sdhci_in16			(in16)
+#define sdhci_in32			(in32)
+#define sdhci_in32s			(in32s)
+#define sdhci_out8			(out8)
+#define sdhci_out16			(out16)
+#define sdhci_out32			(out32)
+#define sdhci_out32s		(out32s)
+
+#else
+
+static __inline__ _Uint8t __attribute__((__unused__))
+sdhci_in8(_Uintptrt __addr) {
+	_Uint8t	__data;
+
+	__data = *(volatile _Uint8t *)__addr;
+	return(__data);
+}
+
+static __inline__ _Uint16t __attribute__((__unused__))
+sdhci_in16(_Uintptrt __addr) {
+	_Uint16t	__data;
+
+	__data = *(volatile _Uint16t *)__addr;
+	return( ENDIAN_LE16( __data ) );
+}
+
+static __inline__ _Uint32t __attribute__((__unused__))
+sdhci_in32(_Uintptrt __addr) {
+	_Uint32t	__data;
+
+	__data = *(volatile _Uint32t *)__addr;
+	return( ENDIAN_LE32( __data ) );
+}
+
+static __inline__ void * __attribute__((__unused__))
+sdhci_in32s(void *__buff, unsigned __len, _Uintptrt __addr) {
+	_Uint32t	*__p = (_Uint32t *)__buff;
+
+	--__p;
+	while(__len > 0) {
+		*++__p = *(volatile _Uint32t *)__addr;
+		--__len;
+	}
+	return(__p+1);
+}
+
+static __inline__ void __attribute__((__unused__))
+sdhci_out8(_Uintptrt __addr, _Uint8t __data) {
+	*(volatile _Uint8t *)__addr = __data;
+}
+
+static __inline__ void __attribute__((__unused__))
+sdhci_out16(_Uintptrt __addr, _Uint16t __data) {
+	*(volatile _Uint16t *)__addr = ENDIAN_LE16( __data );
+}
+
+static __inline__ void __attribute__((__unused__))
+sdhci_out32(_Uintptrt __addr, _Uint32t __data) {
+	*(volatile _Uint32t *)__addr = ENDIAN_LE32( __data );
+}
+
+static __inline__ void * __attribute__((__unused__))
+sdhci_out32s(const void *__buff, unsigned __len, _Uintptrt __addr) {
+	_Uint32t	*__p = (_Uint32t *)__buff;
+
+	--__p;
+	while(__len > 0) {
+		*(volatile _Uint16t *)__addr = *++__p;
+		--__len;
+	}
+	return(__p+1);
+}
+
+#endif
+
+#define SDHCI_CLK_MIN			400000
+#define SDHCI_CLK_MAX			52000000
+
+#define SDHCI_TUNING_RETRIES	40
+#define SDHCI_TUNING_TIMEOUT	150
+
+#define SDHCI_SIZE				4096
+
+#define	SDHCI_SDMA_ARG2			0x00
+#define	SDHCI_32BIT_BLK_CNT		0x00	/* >= v4 */
+
+#define	SDHCI_BLK				0x04
+	#define SDHCI_BLK_SDMA_BOUNDARY_512K	( 7 << 12 )
+	#define SDHCI_BLK_BLKSIZE_MASK			0x00000fff
+	#define SDHCI_BLK_BLKCNT_MASK			0xffff0000
+	#define SDHCI_BLK_BLKCNT_SHIFT			16
+
+#define	SDHCI_ARG				0x08
+
+#define	SDHCI_CMD				0x0C		// Command and transfer mode register
+	#define	SDHCI_CMD_DE			(1 <<  0)	// DMA Enable
+	#define	SDHCI_CMD_BCE			(1 <<  1)	// Block Count Enable
+	#define	SDHCI_CMD_ACMD12		(1 <<  2)	// Auto CMD12 Enable
+	#define	SDHCI_CMD_ACMD23		(1 <<  3)	// Auto CMD23 Enable
+	#define	SDHCI_CMD_DDIR			(1 <<  4)	// Data Transfer Direction Read
+	#define	SDHCI_CMD_MBS			(1 <<  5)	// Multi Block Select
+
+	#define	SDHCI_CMD_RSP_TYPE_136	(1 << 16)	// Response length 136 bit
+	#define	SDHCI_CMD_RSP_TYPE_48	(2 << 16)	// Response length 48 bit
+	#define	SDHCI_CMD_RSP_TYPE_48b	(3 << 16)	// Response length 48 bit with busy after response
+	#define	SDHCI_CMD_CCCE			(1 << 19)	// Comamnd CRC Check Enable
+	#define	SDHCI_CMD_CICE			(1 << 20)	// Comamnd Index Check Enable
+	#define	SDHCI_CMD_DP			(1 << 21)	// Data Present
+	#define	SDHCI_CMD_TYPE_CMD12	(3 << 22)	// CMD12 or CMD52 "I/O Abort"
+
+#define	SDHCI_RESP0				0x10
+#define	SDHCI_RESP1				0x14
+#define	SDHCI_RESP2				0x18
+#define	SDHCI_RESP3				0x1C
+
+#define	SDHCI_DATA				0x20
+
+#define	SDHCI_PSTATE			0x24	// Present State
+
+	#define SDHCI_PSTATE_CLSL_MSK	(1 << 24)
+	#define SDHCI_PSTATE_DLSL_MSK	(0xF << 20)
+	#define	SDHCI_PSTATE_WP			(1 << 19)
+	#define	SDHCI_PSTATE_CD			(1 << 18)
+	#define	SDHCI_PSTATE_CSS		(1 << 17)
+	#define	SDHCI_PSTATE_CI			(1 << 16)
+	#define	SDHCI_PSTATE_BRE		(1 << 11)	// Buffer Read Ready
+	#define	SDHCI_PSTATE_BWE		(1 << 10)	// Buffer Write Ready
+	#define	SDHCI_PSTATE_RTA		(1 <<  9)	// Read Transfer Active
+	#define	SDHCI_PSTATE_WTA		(1 <<  8)	// Write Transfer Active
+	#define	SDHCI_PSTATE_RTR		(1 <<  4)	// Re-Tuning Request
+	#define	SDHCI_PSTATE_DLA		(1 <<  2)	// mmci_dat line active
+	#define	SDHCI_PSTATE_DATI		(1 <<  1)	// Command inhibit
+	#define	SDHCI_PSTATE_CMDI		(1 <<  0)	// Command inhibit
+	#define	SDHCI_CARD_STABLE		(SDHCI_PSTATE_CD | SDHCI_PSTATE_CSS | SDHCI_PSTATE_CI)
+
+#define	SDHCI_HCTL				0x28	// Host Control
+	#define	SDHCI_HCTL_LED			(1 << 0)	// LED Control
+	#define	SDHCI_HCTL_DTW1			(0 << 1)	// Data Bus Width 1 bit
+	#define	SDHCI_HCTL_DTW4			(1 << 1)	// Data Bus Width 4 bit
+	#define	SDHCI_HCTL_HSE			(1 << 2)	// High Speed Enable
+	#define SDHCI_HCTL_DMA_MSK  	(3 << 3)    // DMA select mask
+	#define SDHCI_HCTL_SDMA      	(0 << 3)    // SDMA select
+	#define SDHCI_HCTL_ADMA32		(2 << 3)	// 32 bit ADMA select (< v4.00)
+	#define SDHCI_HCTL_ADMA64		(3 << 3)	// 64 bit ADMA select (< v4.00)
+	#define SDHCI_HCTL_ADMA2		(2 << 3)	// Enable ADMA2 (>= v4.00 and v4-mode enabled)
+	#define SDHCI_HCTL_ADMA2_ADMA3	(3 << 3)	// Enable ADMA2 and ADMA3 (>= v4.00 and v4-mode enabled)
+	#define	SDHCI_HCTL_MMC8			(1 << 3)	// Data Bus Width 8 bit (Intel)
+	#define SDHCI_HCTL_BW8			(1 << 5)	// 8 bit bus select
+	#define	SDHCI_HCTL_SDBP			(1 << 8)	// SD bus power
+	#define	SDHCI_HCTL_SDVS1V8		(5 << 9)	// SD bus voltage 1.8V
+	#define	SDHCI_HCTL_SDVS3V0		(6 << 9)	// SD bus voltage 3.0V
+	#define	SDHCI_HCTL_SDVS3V3		(7 << 9)	// SD bus voltage 3.3V
+	#define	SDHCI_HCTL_SDVS_MSK		(7 << 9)
+
+#define	SDHCI_BLKGAPCTL			0x2A
+
+#define	SDHCI_WAKECTL			0x2B
+
+#define	SDHCI_SYSCTL			0x2C	// Clock Control/Timeout/Software reset
+	#define	SDHCI_SYSCTL_ICE		(1 << 0)	// Internal Clock Enable
+	#define	SDHCI_SYSCTL_ICS		(1 << 1)	// Internal Clock Stable
+	#define	SDHCI_SYSCTL_CEN		(1 << 2)	// Clock Enable
+	#define	SDHCI_SYSCTL_PLLEN		(1 << 3)	// PLL Enable
+	#define	SDHCI_SYSCTL_CGS_PROG	(1 << 5)	// Clock Generator Select (programmable)
+	#define SDHCI_SYSCTL_CLK( _c )	( ( (_c) << 8 ) | ( ( (_c) >> 2 ) & 0xe0 ) )
+	#define SDHCI_SYSCTL_SDCLKFS_MSK	0xffe0
+	#define	SDHCI_SYSCTL_DTO_MSK	(0xF << 16)	// Data timeout counter value and busy timeout
+	#define	SDHCI_SYSCTL_DTO_MAX	(0xE << 16)	// Timeout = TCF x 2^27
+	#define	SDHCI_SYSCTL_SRA		(1 << 24)	// Software reset for all
+	#define	SDHCI_SYSCTL_SRC		(1 << 25)	// Software reset for mmci_cmd line
+	#define	SDHCI_SYSCTL_SRD		(1 << 26)	// Software reset for mmci_dat line
+
+	#define SDHCI_CLK_MAX_DIV_SPEC_VER_2	256
+	#define SDHCI_CLK_MAX_DIV_SPEC_VER_3	2046
+
+#define	SDHCI_IS				0x30	// Interrupt status register
+#define	SDHCI_IE				0x34	// Interrupt SD enable register
+#define	SDHCI_ISE				0x38	// Interrupt signal enable register
+	#define	SDHCI_INTR_CC			(1 <<  0)	// Command Complete
+	#define	SDHCI_INTR_TC			(1 <<  1)	// Transfer Complete
+	#define	SDHCI_INTR_BGE			(1 <<  2)	// Block Gap Event
+	#define SDHCI_INTR_DMA			(1 <<  3)	// DMA interupt
+	#define	SDHCI_INTR_BWR			(1 <<  4)	// Buffer Write Ready interrupt
+	#define	SDHCI_INTR_BRR			(1 <<  5)	// Buffer Read Ready interrupt
+	#define SDHCI_INTR_CINS			(1 <<  6)	// Card Insertion
+	#define SDHCI_INTR_CREM			(1 <<  7)	// Card Removal
+	#define	SDHCI_INTR_CIRQ			(1 <<  8)	// Card interrupt
+	#define	SDHCI_INTR_OBI			(1 <<  9)	// Out-Of-Band interrupt
+	#define SDHCI_INTR_BSR			(1 << 10)	// Boot Status
+	#define SDCHI_INTR_RETUNE		(1 << 12)	// Re-Tuning
+	#define	SDHCI_INTR_ERRI			(1 << 15)	// Error interrupt
+	#define	SDHCI_INTR_CTO			(1 << 16)	// Command Timeout error
+	#define	SDHCI_INTR_CCRC			(1 << 17)	// Command CRC error
+	#define	SDHCI_INTR_CEB			(1 << 18)	// Command End Bit error
+	#define	SDHCI_INTR_CIE			(1 << 19)	// Command Index error
+	#define	SDHCI_INTR_DTO			(1 << 20)	// Data Timeout error
+	#define	SDHCI_INTR_DCRC			(1 << 21)	// Data CRC error
+	#define	SDHCI_INTR_DEB			(1 << 22)	// Data End Bit error
+	#define	SDHCI_INTR_ACE			(1 << 24)	// ACMD12 error
+	#define SDHCI_INTR_ADMAE		(1 << 25)	// ADMA Error
+	#define SDHCI_INTR_SDMAE		(1 << 28)	// SDMA Error
+	#define SDHCI_INTR_DFLTS		(SDHCI_INTR_ADMAE | SDHCI_INTR_ACE | SDHCI_INTR_CIE |	\
+									 SDHCI_INTR_CEB | SDHCI_INTR_CCRC | SDHCI_INTR_CTO |		\
+									 SDHCI_INTR_ERRI /* | SDHCI_INTR_CINS | SDHCI_INTR_CREM */ )
+	#define SDHCI_INTR_ALL			0x33ff87ff
+	#define SDHCI_INTR_CLR_MSK		0x117f80f3
+
+#define	SDHCI_AC12				0x3C
+
+#define	SDHCI_HCTL2				0x3E	// Host Control 2
+	#define SDHCI_HCTL2_PRESET_VAL		(1 << 15)
+	#define SDHCI_HCTL2_ASYNC_INT		(1 << 14)
+	#define SDHCI_HCTL2_64BIT_ADDR		(1 << 13)
+	#define SDHCI_HCTL2_V4_MODE			(1 << 12)
+	#define SDHCI_HCTL2_ACMD23_EN		(1 << 11)
+	#define SDHCI_HCTL2_ADMA2_26BIT		(1 << 10)
+	#define SDHCI_HCTL2_TUNED_CLK		(1 << 7)
+	#define SDHCI_HCTL2_EXEC_TUNING		(1 << 6)
+
+	#define SDHCI_HCTL2_DRV_TYPE_MSK	(0x3 << 4)
+	#define SDHCI_HCTL2_DRV_TYPE_D		(0x3 << 4)
+	#define SDHCI_HCTL2_DRV_TYPE_C		(0x2 << 4)
+	#define SDHCI_HCTL2_DRV_TYPE_A		(0x1 << 4)
+	#define SDHCI_HCTL2_DRV_TYPE_B		(0x0 << 4)
+
+	#define SDHCI_HCTL2_SIG_1_8V		(1 << 3)
+
+	#define SDHCI_HCTL2_MODE( _c )	( (_c) & SDHCI_HCTL2_MODE_MSK )
+	#define SDHCI_HCTL2_MODE_MSK		(0x7 << 0)
+	#define SDHCI_HCTL2_MODE_HS400		(0x5 << 0)
+	#define SDHCI_HCTL2_MODE_DDR50		(0x4 << 0)
+	#define SDHCI_HCTL2_MODE_HS200		(0x3 << 0)
+	#define SDHCI_HCTL2_MODE_SDR104		(0x3 << 0)
+	#define SDHCI_HCTL2_MODE_SDR50		(0x2 << 0)
+	#define SDHCI_HCTL2_MODE_SDR25		(0x1 << 0)
+
+#define	SDHCI_CAP				0x40	// Capability Registers bits 0 to 31
+	#define	SDHCI_CAP_CS_MSK		(0x3 << 30)
+	#define	SDHCI_CAP_CS_SHARED		(0x2 << 30)	// Shared Slot
+	#define	SDHCI_CAP_CS_EMBEDDED	(0x1 << 30)	// Embedded Slot
+	#define	SDHCI_CAP_CS_RMB		(0x0 << 30)	// Removable Card Slot
+	#define	SDHCI_CAP_64BIT_ADDR	(1 << 28)	// 64 bit system address support
+	#define	SDHCI_CAP_S18			(1 << 26)	// 1.8V support
+	#define	SDHCI_CAP_S30			(1 << 25)	// 3.0V support
+	#define	SDHCI_CAP_S33			(1 << 24)	// 3.3V support
+	#define	SDHCI_CAP_SRS			(1 << 23)	// Suspend/Resume support
+	#define	SDHCI_CAP_DMA			(1 << 22)	// DMA support
+	#define	SDHCI_CAP_HS			(1 << 21)	// High-Speed support
+	#define	SDHCI_CAP_ADMA1			(1 << 20)	// ADMA1 support
+	#define	SDHCI_CAP_ADMA2			(1 << 19)	// ADMA2 support
+	#define	SDHCI_CAP_EXTMBUS		(1 << 18)	// Extended media bus support
+	#define	SDHCI_CAP_MBL512		(0 << 16)	// Max block length 512
+	#define	SDHCI_CAP_MBL2048		(2 << 16)	// Max block length 2048
+	#define SDHCI_CAP_BASE_CLK( _c, _v )	( ( ( ( _v ) >= SDHCI_SPEC_VER_3 ) ?	\
+											( ( ( _c ) >> 8 ) & 0xff ) :			\
+											( ( ( _c ) >> 8 ) & 0x3f ) ) * 1000 * 1000 )
+
+#define	SDHCI_CAP2				0x44	// bits 32 to 64
+	#define SDHCI_CAP_CLK_MULT( _cap )	( ( ( _cap ) & 0xff0000 ) >> 16 )
+	#define SDHCI_CAP_TUNING_MODE( _cap )	( ( ( _cap ) & 0xe000 ) >> 14 )
+	#define SDHCI_CAP_TUNE_SDR50	(1 << 13)
+	#define SDHCI_CAP_TIMER_COUNT( _cap )	( ( ( _cap ) & 0xf00 ) >> 8 )
+
+	#define SDHCI_CAP_DRIVE_TYPE_D	(1 << 6)
+	#define SDHCI_CAP_DRIVE_TYPE_C	(1 << 5)
+	#define SDHCI_CAP_DRIVE_TYPE_A	(1 << 4)
+	#define SDHCI_CAP_DDR50			(1 << 2)
+	#define SDHCI_CAP_SDR104		(1 << 1)
+	#define SDHCI_CAP_SDR50			(1 << 0)
+
+#define	SDHCI_MCCAP				0x48	// Maximum Current Capabilities
+	#define SDHCI_MCCAP_330( _cap )	( (_cap) & 0x0000ff )
+	#define SDHCI_MCCAP_300( _cap )	( ( (_cap) & 0x00ff00 ) >> 8 )
+	#define SDHCI_MCCAP_180( _cap )	( ( (_cap) & 0xff0000 ) >> 16 )
+	#define SDHCI_MCCAP_MULT		4	// 4mA steps
+
+#define SDHCI_ADMA_ES			0x54
+#define SDHCI_ADMA_ADDRL  		0x58
+#define SDHCI_ADMA_ADDRH	  	0x5C
+#define	SDHCI_SLOT_IS			0xFC
+
+#define	SDHCI_HCTL_VERSION		0xFE
+	#define SDHCI_SPEC_VER_MSK		0xff
+	#define SDHCI_SPEC_VER_420		0x5
+	#define SDHCI_SPEC_VER_410		0x4
+	#define SDHCI_SPEC_VER_4		0x3
+	#define SDHCI_SPEC_VER_3		0x2
+	#define SDHCI_SPEC_VER_2		0x1
+	#define SDHCI_SPEC_VER_1		0x0
+
+
+#define SDHCI_ADMA2_MAX_XFER	(1024 * 60)
+
+// 32 bit ADMA descriptor defination
+typedef struct _sdhci_adma32_t {
+	uint16_t	attr;
+	uint16_t	len;
+	uint32_t	addr;
+} sdhci_adma32_t;
+
+// 64 bit ADMA descriptor defination
+typedef struct _sdhci_adma64_t {
+	uint16_t	attr;
+	uint16_t	len;
+	uint32_t	addr_lo;
+	uint32_t	addr_hi;
+} sdhci_adma64_t;
+
+// 64 bit ADMA descriptor definition (for v4 mode)
+typedef struct _sdhci_v4_adma64_t {
+	uint16_t	attr;
+	uint16_t	len;
+	uint32_t	addr_lo;
+	uint32_t	addr_hi;
+	uint32_t	reserved; /* sbz */
+} sdhci_v4_adma64_t;
+
+#define SDHCI_ADMA2_VALID	(1 << 0)	// valid
+#define SDHCI_ADMA2_END		(1 << 1)	// end of descriptor, transfer complete interrupt will be generated
+#define SDHCI_ADMA2_INT		(1 << 2)	// generate DMA interrupt, will not be used
+#define SDHCI_ADMA2_NOP		(0 << 4)	// no OP, go to the next desctiptor
+#define SDHCI_ADMA2_TRAN	(2 << 4)	// transfer data
+#define SDHCI_ADMA2_LINK	(3 << 4)	// link to another descriptor
+
+// extra 32 bit on top of the descriptor for V4 mode
+#define SDHCI_ADMA2_64_DESC_SZ(sdhc)	\
+		(( (sdhc)->flags & SF_V4_MODE ) ? sizeof( sdhci_v4_adma64_t ) : sizeof( sdhci_adma64_t ))
+
+typedef	struct _sdhci_hc {
+	void			*bshdl;
+	uintptr_t		base;
+#define SF_USE_SDMA		0x01
+#define SF_USE_ADMA		0x02
+#define SF_TUNE_SDR50	0x04
+#define SF_USE_ADMA64	0x08
+#define SF_DIS_64BIT	0x10
+#define SF_V4_MODE		0x20
+	uint32_t		flags;
+	uint32_t		clk_mul;
+
+#define SDCHI_TUNING_MODE_1	0x0
+#define SDCHI_TUNING_MODE_2	0x1
+#define SDCHI_TUNING_MODE_3	0x2
+	int				tuning_mode;
+
+#define ADMA_DESC_MAX		256
+	sdio_sge_t		sgl[ADMA_DESC_MAX];
+	sdhci_adma64_t	*adma;
+	paddr64_t		admap;
+} sdhci_hc_t;
+
+extern int sdhci_init( sdio_hc_t *hc );
+extern int sdhci_dinit( sdio_hc_t *hc );
+extern int sdhci_getsubopt( char **optionp, char * const *tokens, char **valuep );
+extern int sdhci_reset( sdio_hc_t *hc, uint32_t rst );
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/hc/sdhci.h $ $Rev: 976677 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/hc/sdhci_dwc.h

@@ -0,0 +1,125 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2021, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef	_SDHCI_DWC_H_INCLUDED
+#define	_SDHCI_DWC_H_INCLUDED
+
+#include <internal.h>
+
+#ifdef SDIO_HC_SDHCI_DWC
+#include <sdhci.h>
+
+#ifdef  SDHCI_HCTL2_MODE_HS400
+#undef  SDHCI_HCTL2_MODE_HS400
+#endif
+#define SDHCI_HCTL2_MODE_HS400      (0x7 << 0)
+
+#ifdef  SDHCI_TUNING_RETRIES
+#undef  SDHCI_TUNING_RETRIES
+#endif
+#define SDHCI_TUNING_RETRIES        140
+
+// Vendor specific register
+#define SDHCI_VENDOR_BASE_REG       0xE8
+
+#define SDHCI_VENDER_EMMC_CTRL_REG  0x2C
+ #define    SDHCI_IS_EMMC_CARD_MASK     (1 << 0)
+
+#define SDHCI_VENDOR_AT_CTRL_REG    0x40
+ #define    SDHCI_TUNE_SWIN_TH_VAL_MASK 0xFF
+ #define    SDHCI_TUNE_SWIN_TH_VAL_LSB  24
+ #define    SDHCI_TUNE_CLK_STOP_EN_MASK (1 << 16)
+
+// DWC PHY registers
+#define DWC_MSHC_PHY_REGS           0x300
+#define DWC_MSHC_PHY_CNFG           (DWC_MSHC_PHY_REGS + 0x0)
+ #define    PAD_SN_LSB                  20
+ #define    PAD_SN_MASK                 0xF
+ #define    PAD_SN_DEFAULT              ((0x8 & PAD_SN_MASK) << PAD_SN_LSB)
+ #define    PAD_SP_LSB                  16
+ #define    PAD_SP_MASK                 0xF
+ #define    PAD_SP_DEFAULT              ((0x9 & PAD_SP_MASK) << PAD_SP_LSB)
+ #define    PHY_PWRGOOD                 (1 << 1)
+ #define    PHY_RSTN                    (1 << 0)
+
+#define DWC_MSHC_CMDPAD_CNFG        (DWC_MSHC_PHY_REGS + 0x4)
+#define DWC_MSHC_DATPAD_CNFG        (DWC_MSHC_PHY_REGS + 0x6)
+#define DWC_MSHC_CLKPAD_CNFG        (DWC_MSHC_PHY_REGS + 0x8)
+#define DWC_MSHC_STBPAD_CNFG        (DWC_MSHC_PHY_REGS + 0xA)
+#define DWC_MSHC_RSTNPAD_CNFG       (DWC_MSHC_PHY_REGS + 0xC)
+ #define    TXSLEW_N_LSB                9
+ #define    TXSLEW_N_MASK               0xF
+ #define    TXSLEW_P_LSB                5
+ #define    TXSLEW_P_MASK               0xF
+ #define    WEAKPULL_EN_LSB             3
+ #define    WEAKPULL_EN_MASK            0x3
+ #define    RXSEL_LSB                   0
+ #define    RXSEL_MASK                  0x3
+
+#define DWC_MSHC_COMMDL_CNFG        (DWC_MSHC_PHY_REGS + 0x1C)
+#define DWC_MSHC_SDCLKDL_CNFG       (DWC_MSHC_PHY_REGS + 0x1D)
+#define DWC_MSHC_SDCLKDL_DC         (DWC_MSHC_PHY_REGS + 0x1E)
+#define DWC_MSHC_SMPLDL_CNFG        (DWC_MSHC_PHY_REGS + 0x20)
+#define DWC_MSHC_ATDL_CNFG          (DWC_MSHC_PHY_REGS + 0x21)
+
+#define DWC_MSHC_DLL_CTRL           (DWC_MSHC_PHY_REGS + 0x24)
+#define DWC_MSHC_DLL_CNFG1          (DWC_MSHC_PHY_REGS + 0x25)
+#define DWC_MSHC_DLL_CNFG2          (DWC_MSHC_PHY_REGS + 0x26)
+#define DWC_MSHC_DLLDL_CNFG         (DWC_MSHC_PHY_REGS + 0x28)
+#define DWC_MSHC_DLL_OFFSET         (DWC_MSHC_PHY_REGS + 0x29)
+#define DWC_MSHC_DLLLBT_CNFG        (DWC_MSHC_PHY_REGS + 0x2C)
+#define DWC_MSHC_DLL_STATUS         (DWC_MSHC_PHY_REGS + 0x2E)
+ #define    ERROR_STS                   (1 << 17)
+ #define    LOCK_STS                    (1 << 16)
+
+#define DWC_MSHC_PHY_PAD_SD_CLK     \
+    ((1 << TXSLEW_N_LSB) | (3 << TXSLEW_P_LSB) | (0 << WEAKPULL_EN_LSB) | (1 << RXSEL_LSB))
+#define DWC_MSHC_PHY_PAD_SD_DAT     \
+    ((1 << TXSLEW_N_LSB) | (3 << TXSLEW_P_LSB) | (1 << WEAKPULL_EN_LSB) | (1 << RXSEL_LSB))
+#define DWC_MSHC_PHY_PAD_SD_STB     \
+    ((1 << TXSLEW_N_LSB) | (3 << TXSLEW_P_LSB) | (2 << WEAKPULL_EN_LSB) | (1 << RXSEL_LSB))
+
+#define DWC_MSHC_PHY_PAD_EMMC_CLK   \
+    ((2 << TXSLEW_N_LSB) | (2 << TXSLEW_P_LSB) | (0 << WEAKPULL_EN_LSB) | (0 << RXSEL_LSB))
+#define DWC_MSHC_PHY_PAD_EMMC_DAT   \
+    ((2 << TXSLEW_N_LSB) | (2 << TXSLEW_P_LSB) | (1 << WEAKPULL_EN_LSB) | (1 << RXSEL_LSB))
+#define DWC_MSHC_PHY_PAD_EMMC_STB   \
+    ((2 << TXSLEW_N_LSB) | (2 << TXSLEW_P_LSB) | (2 << WEAKPULL_EN_LSB) | (1 << RXSEL_LSB))
+
+
+typedef struct _sdhci_dwc {
+    sdhci_hc_t  sdhci;
+    uintptr_t   scr_base;
+    int         (*set_clk)(struct _sdio_hc *, int, int);
+    int         phy; //0: DWC_MSHC_LS_NO_PHY_MODE is set, skip PHY config; 1: DWC_MSHC_LS_NO_PHY_MODE is not set, do PHY config
+} sdhci_dwc_t;
+
+extern int sdhci_dwc_dinit( sdio_hc_t *hc );
+extern int sdhci_dwc_init( sdio_hc_t *hc );
+
+#endif
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/hc/sdhci_dwc.h $ $Rev: 969525 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/hc/sdhci_pci.c

@@ -0,0 +1,108 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007-2019, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#include <errno.h>
+#include <string.h>
+#include <stdlib.h>
+#include <malloc.h>
+#include <unistd.h>
+
+#include <hw/inout.h>
+
+#include <sys/mman.h>
+
+#include <internal.h>
+#include <sdhci.h>
+
+#ifdef SDIO_HC_SDHCI_PCI
+
+#include <pci/pci.h>
+#include <pci/pci_id.h>
+#include <pci/pci_ccode.h>
+#include <pci_devices.h>
+#include <sdhci_pci.h>
+
+int sdhci_pci_init( sdio_hc_t *hc )
+{
+	sdio_hc_cfg_t		*cfg;
+
+	cfg	= &hc->cfg;
+
+		// timing caps have to be set before sdhci_init() is called
+	switch( cfg->vid ) {
+		case PCI_VID_Intel_Corp:
+			if( ( cfg->did == PCI_DEVICE_ID_INTEL_BROXTON_EMMC ) || ( cfg->did == PCI_DEVICE_ID_INTEL_DENVERTON_EMMC ) ) {
+				hc->caps |= HC_CAP_HS200 | HC_CAP_HS400;
+				hc->caps |= HC_CAP_SLOT_TYPE_EMBEDDED;
+				hc->flags |= HC_FLAG_DEV_MMC;
+			}
+			break;
+
+		default:
+			break;
+	}
+
+	return sdhci_init( hc );
+}
+
+#ifdef SDHCI_PCI_VENDOR_GENERIC
+sdio_product_t	sdio_sdhci_product[] = {
+	{ .did = SDIO_DEVICE_ID_WILDCARD, .class = PCI_CCODE_PERIPHERAL_SD_HOST_CTRL, .aflags = 0, .name = "Generic SDHCI", .init = sdhci_pci_init },
+	{ .did = 0, .class = 0, .aflags = 0, .name = NULL, .init = NULL }
+};
+#endif
+
+#ifdef SDHCI_PCI_VENDOR_O2
+sdio_product_t	sdio_sdhci_o2_products[] = {
+	{ .did = PCI_DEVICE_ID_O2_8321, .class = 0, .aflags = 0, .name = "O2 Micro 8321", .init = sdhci_pci_init },
+	{ .did = 0, .class = 0, .aflags = 0, .name = NULL, .init = NULL }
+};
+#endif
+
+#ifdef SDHCI_PCI_VENDOR_CMD
+sdio_product_t	sdio_sdhci_cmd_products[] = {
+	{ .did = PCI_DEVICE_ID_CMD_670, .class = 0, .aflags = 0, .name = "Sil 670", .init = sdhci_pci_init },
+	{ .did = 0, .class = 0, .aflags = 0, .name = NULL, .init = NULL }
+};
+#endif
+
+#ifdef SDHCI_PCI_VENDOR_INTEL
+sdio_product_t	sdio_sdhci_intel_products[] = {
+	{ .did = PCI_DEVICE_ID_INTEL_SCH_SDIO1, .class = 0, .aflags = 0, .name = "Intel SCH", .init = sdhci_pci_init },
+	{ .did = PCI_DEVICE_ID_INTEL_SCH_SDIO2, .class = 0, .aflags = 0, .name = "Intel SCH", .init = sdhci_pci_init },
+	{ .did = PCI_DEVICE_ID_INTEL_SCH_SDIO3, .class = 0, .aflags = 0, .name = "Intel SCH", .init = sdhci_pci_init },
+	{ .did = PCI_DEVICE_ID_INTEL_BROXTON_SDCARD, .class = 0, .aflags = 0, .name = "Intel Broxton", .init = sdhci_pci_init },
+	{ .did = PCI_DEVICE_ID_INTEL_BROXTON_EMMC,   .class = 0, .aflags = 0, .name = "Intel Broxton", .init = sdhci_pci_init },
+	{ .did = PCI_DEVICE_ID_INTEL_BROXTON_SDIO,   .class = 0, .aflags = 0, .name = "Intel Broxton", .init = sdhci_pci_init },
+	{ .did = PCI_DEVICE_ID_INTEL_DENVERTON_EMMC, .class = 0, .aflags = 0, .name = "Intel Denverton", .init = sdhci_pci_init },
+	{ .did = PCI_DEVICE_ID_INTEL_BAYTRAIL_SDIO,  .class = 0, .aflags = 0, .name = "Intel Baytrail", .init = sdhci_pci_init },
+	{ .did = PCI_DEVICE_ID_INTEL_BAYTRAIL_SD,    .class = 0, .aflags = 0, .name = "Intel Baytrail", .init = sdhci_pci_init },
+	{ .did = PCI_DEVICE_ID_INTEL_BAYTRAIL_SDHCI, .class = 0, .aflags = 0, .name = "Intel Baytrail", .init = sdhci_pci_init },
+	{ .did = 0, .class = 0, .aflags = 0, .name = NULL, .init = NULL }
+};
+#endif
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/hc/sdhci_pci.c $ $Rev: 982571 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/hc/sdhci_pci.h

@@ -0,0 +1,54 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2017, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef	_SDHCI_PCI_H_INCLUDED
+#define	_SDHCI_PCI_H_INCLUDED
+
+#include <internal.h>
+
+#ifdef SDIO_HC_SDHCI_PCI
+
+#ifdef SDHCI_PCI_VENDOR_INTEL
+extern sdio_product_t	sdio_sdhci_intel_products[];
+#endif
+
+#ifdef SDHCI_PCI_VENDOR_O2
+extern sdio_product_t	sdio_sdhci_o2_products[];
+#endif
+
+#ifdef SDHCI_PCI_VENDOR_CMD
+extern sdio_product_t	sdio_sdhci_cmd_products[];
+#endif
+
+#ifdef SDHCI_PCI_VENDOR_GENERIC
+extern sdio_product_t	sdio_sdhci_product[];
+#endif
+
+int sdhci_pci_init( sdio_hc_t *hc );
+
+#endif
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/hc/sdhci_pci.h $ $Rev: 969525 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/include/mmc.h

@@ -0,0 +1,451 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2008, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef _MMC_H_INCLUDED
+#define _MMC_H_INCLUDED
+
+// Compile time options
+
+// Currently untested, requires older eMMC parts
+//#define MMC_REL_WR_LEGACY_SUP		// Enable Legacy Reliable Write support
+
+#define MMC_PARTITION_SWITCH_TIMEOUT	10			// 10ms
+#define MMC_OUT_OF_INTERRUPT_TIMEOUT	10			// 10ms
+#define MMC_ERASE_TIMEOUT			300			// 300ms
+#define MMC_ERASE_TIMEOUT_MIN		2000		// set min timeout to 2 seconds
+#define MMC_ERASE_GRP_512K			0x80000LL
+#define MMC_PART_USER				0
+#define MMC_PART_BOOT1				1
+#define MMC_PART_BOOT2				2
+#define MMC_PART_RPMB				3
+#define MMC_PART_GP1				4
+#define MMC_PART_GP2				5
+#define MMC_PART_GP3				6
+#define MMC_PART_GP4				7
+#define MMC_PART_MSK				0x7
+
+#define MMC_BOOT_PART_MAX			2
+#define MMC_GP_PART_MAX				4
+#define MMC_BOOT_SIZE_MULT			0x20000
+#define MMC_RPMB_SIZE_MULT			0x20000
+#define MMC_CID_SIZE				16
+#define MMC_CSD_SIZE				16
+
+#define	MMC_GO_IDLE_STATE			0
+
+#define	MMC_SEND_OP_COND			1
+	#define OCR_VDD_17_195		0x00000080	// VDD 1.7 - 1.95
+	#define OCR_VDD_20_21		0x00000100	// VDD 2.0 - 2.1
+	#define OCR_VDD_21_22		0x00000200	// VDD 2.1 - 2.2
+	#define OCR_VDD_22_23		0x00000400	// VDD 2.2 - 2.3
+	#define OCR_VDD_23_24		0x00000800	// VDD 2.3 - 2.4
+	#define OCR_VDD_24_25		0x00001000	// VDD 2.4 - 2.5
+	#define OCR_VDD_25_26		0x00002000	// VDD 2.5 - 2.6
+	#define OCR_VDD_26_27		0x00004000	// VDD 2.6 - 2.7
+	#define OCR_VDD_27_28		0x00008000	// VDD 2.7 - 2.8
+	#define OCR_VDD_28_29		0x00010000	// VDD 2.8 - 2.9
+	#define OCR_VDD_29_30		0x00020000	// VDD 2.9 - 3.0
+	#define OCR_VDD_30_31		0x00040000	// VDD 3.0 - 3.1
+	#define OCR_VDD_31_32		0x00080000	// VDD 3.1 - 3.2
+	#define OCR_VDD_32_33		0x00100000	// VDD 3.2 - 3.3
+	#define OCR_VDD_33_34		0x00200000	// VDD 3.3 - 3.4
+	#define OCR_VDD_34_35		0x00400000	// VDD 3.4 - 3.5
+	#define OCR_VDD_35_36		0x00800000	// VDD 3.5 - 3.6
+	#define OCR_S18R			0x01000000	// Switching to 1.8V Request
+	#define OCR_S18A			0x01000000	// Switching to 1.8V Accepted
+	#define OCR_HO2T			0x08000000	// Over 2TB
+	#define OCR_XPC				0x10000000	// SDXC Power Control > 150ma
+	#define OCR_UHS_II			0x20000000	// UHS-II Card
+	#define OCR_HCS				0x40000000	// Card Capacity Status
+	#define OCR_PWRUP_CMP		0x80000000
+
+	#define OCR_BUSY_RETRIES	500			// wait up to 5 seconds
+
+#define	MMC_ALL_SEND_CID			2
+	#define MDT_YEAR_1997			1997
+	#define MDT_YEAR_2010			2010
+	#define MDT_YEAR_2013			2013
+
+#define	MMC_SET_RELATIVE_ADDR		3
+#define	MMC_SET_DSR					4
+
+#define	MMC_SLEEP_AWAKE				5
+	#define MMC_SA_SLEEP			(1 << 15 )
+
+#define	MMC_SWITCH					6
+	#define MMC_SWITCH_MODE_WRITE	0x3
+	#define MMC_SWITCH_MODE_CLR		0x2
+	#define MMC_SWITCH_MODE_SET		0x1
+	#define MMC_SWITCH_MODE_CMD_SET	0x0
+	#define MMC_SWITCH_CMDSET_DFLT	0x1
+
+#define	MMC_SEL_DES_CARD			7
+#define	MMC_SEND_EXT_CSD			8
+#define	MMC_SEND_CSD				9
+#define	MMC_SEND_CID				10
+#define	MMC_READ_DAT_UNTIL_STOP		11
+
+#define	MMC_STOP_TRANSMISSION		12
+	#define MMC_STOP_TRANSMISSION_HPI	(1 << 0)
+
+#define	MMC_SEND_STATUS				13
+	#define MMC_SEND_STATUS_HPI			(1 << 0)
+
+// Card/Device Status Response Bits
+	#define	CDS_OUT_OF_RANGE			(1 << 31)
+	#define	CDS_ADDRESS_ERROR			(1 << 30)
+	#define	CDS_BLOCK_LEN_ERROR			(1 << 29)
+	#define	CDS_ERASE_SEQ_ERROR			(1 << 28)
+	#define	CDS_ERASE_PARAM				(1 << 27)
+	#define	CDS_WP_VIOLATION			(1 << 26)
+	#define	CDS_CARD_IS_LOCKED			(1 << 25)
+	#define	CDS_LOCK_UNLOCK_FAILED		(1 << 24)
+	#define	CDS_COM_CRC_ERROR			(1 << 23)
+	#define	CDS_ILLEGAL_COMMAND			(1 << 22)
+	#define	CDS_CARD_ECC_FAILED			(1 << 21)
+	#define	CDS_CC_ERROR				(1 << 20)
+	#define	CDS_ERROR					(1 << 19)
+	#define	CDS_UNDERRUN				(1 << 18)
+	#define	CDS_OVERRUN					(1 << 17)
+	#define	CDS_CID_CSD_OVERWRITE		(1 << 16)
+	#define	CDS_WP_ERASE_SKIP			(1 << 15)
+	#define	CDS_CARD_ECC_DISABLED		(1 << 14)
+	#define	CDS_ERASE_RESET				(1 << 13)
+
+	#define CDS_CUR_STATE_MSK			( 0xf << 9 )
+	#define CDS_CUR_STATE( _r )			( ( (_r) >> 9 ) & 0xf )
+	#define	CDS_CUR_STATE_IDLE			(0 << 9)
+	#define	CDS_CUR_STATE_READY			(1 << 9)
+	#define	CDS_CUR_STATE_IDENT			(2 << 9)
+	#define	CDS_CUR_STATE_STANDBY		(3 << 9)
+	#define	CDS_CUR_STATE_TRAN			(4 << 9)
+	#define	CDS_CUR_STATE_DATA			(5 << 9)
+	#define	CDS_CUR_STATE_RCV			(6 << 9)
+	#define	CDS_CUR_STATE_PRG			(7 << 9)
+	#define	CDS_CUR_STATE_DIS			(8 << 9)
+
+	#define	CDS_READY_FOR_DATA			(1 << 8)
+	#define	CDS_SWITCH_ERROR			(1 << 7)
+	#define	CDS_URGENT_BKOPS			(1 << 6)
+	#define	CDS_APP_CMD_S				(1 << 5)
+
+	#define CDS_ERROR_MSK				(	CDS_OUT_OF_RANGE		| \
+											CDS_ADDRESS_ERROR		| \
+											CDS_BLOCK_LEN_ERROR		| \
+											CDS_ERASE_SEQ_ERROR		| \
+											CDS_ERASE_PARAM			| \
+											CDS_WP_VIOLATION		| \
+											CDS_CARD_IS_LOCKED		| \
+											CDS_LOCK_UNLOCK_FAILED	| \
+											CDS_COM_CRC_ERROR		| \
+											CDS_ILLEGAL_COMMAND		| \
+											CDS_CARD_ECC_FAILED		| \
+											CDS_CC_ERROR			| \
+											CDS_ERROR				| \
+											CDS_SWITCH_ERROR 		| \
+	CDS_CID_CSD_OVERWRITE )
+
+#define	MMC_BUSTEST_R				14
+#define	MMC_GO_INACTIVE_STATE		15
+#define	MMC_SET_BLOCKLEN			16
+#define	MMC_READ_SINGLE_BLOCK		17
+#define	MMC_READ_MULTIPLE_BLOCK		18
+#define	MMC_BUSTEST_W				19
+#define	MMC_WRITE_DAT_UNTIL_STOP	20
+#define MMC_SEND_TUNING_BLOCK		21
+#define MMC_SET_BLOCK_COUNT         23
+	#define	SBC_RL_WRITE				(1 << 31)
+#define	MMC_WRITE_BLOCK				24
+#define	MMC_WRITE_MULTIPLE_BLOCK	25
+#define	MMC_PROGRAM_CID				26
+#define	MMC_PROGRAM_CSD				27
+#define	MMC_SET_WRITE_PROT			28
+#define	MMC_CLR_WRITE_PROT			29
+#define	MMC_SEND_WRITE_PROT			30
+	#define MMC_SEND_WRITE_PROT_SIZE		4
+#define	MMC_SEND_WRITE_PROT_TYPE	31
+	#define MMC_SEND_WRITE_PROT_TYPE_SIZE	8
+#define	MMC_TAG_SECTOR_START		32
+#define	MMC_TAG_SECTOR_END			33
+#define	MMC_UNTAG_SECTOR			34
+#define	MMC_TAG_ERASE_GROUP_START	35
+#define	MMC_TAG_ERASE_GROUP_END		36
+#define	MMC_UNTAG_ERASE_GROUP		37
+
+#define	MMC_ERASE					38
+	#define MMC_ERASE_SECURE_TRIM_PURGE	0x80008000
+	#define MMC_ERASE_SECURE_TRIM		0x80000001
+	#define MMC_ERASE_SECURE			0x80000000
+	#define MMC_ERASE_DISCARD			0x00000003
+	#define MMC_ERASE_TRIM				0x00000001
+	#define MMC_ERASE_NORM				0x00000000
+
+#define	MMC_FAST_IO					39
+#define	MMC_GO_IRQ_STATE			40
+#define	MMC_LOCK_UNLOCK				42
+	#define MMC_LU_ERASE				0x08
+	#define MMC_LU_LOCK					0x04
+	#define MMC_LU_UNLOCK				0x00
+	#define MMC_LU_CLR_PWD				0x02
+	#define MMC_LU_SET_PWD				0x01
+	#define MMC_LU_PWD_SIZE				16		// max password size
+
+#define	MMC_APP_CMD					55
+#define	MMC_GEN_CMD					56
+#define	MMC_READ_OCR				58
+#define	MMC_CRC_ON_OFF				59
+
+#define	MMC_MAN_CMD1				60
+#define	MMC_MAN_CMD2				61
+#define	MMC_MAN_CMD3				62
+#define	MMC_MAN_CMD4				63
+
+// EXT_CSD fields
+#define MMC_EXT_CSD_SIZE			512
+
+#define	ECSD_FFU_STATUS				26
+	#define	ECSD_FFU_SUCCESS			0x00
+	#define	ECSD_FFU_GENERAL			0x10	// General error
+	#define	ECSD_FFU_FW_INSTALL			0x11	// Firmware instrall error
+	#define	ECSD_FFU_FW_DOWNLOAD		0x12	// Firmware download error
+
+#define	ECSD_MODE_OPERATION_CODES	29
+	#define	ECSD_FFU_INSTALL			0x01
+	#define	ECSD_FFU_ABORT				0x02
+
+#define	ECSD_MODE_CONFIG			30
+	#define	ECSD_MODE_NORMAL			0x00
+	#define	ECSD_MODE_FFU				0x01
+	#define	ECSD_MODE_VSM				0x10
+
+#define ECSD_FLUSH_CACHE			32
+	#define ECSD_FLUSH_TRIGGER			0x01
+
+#define ECSD_CACHE_CTRL				33
+	#define ECSD_CACHE_CTRL_EN			0x01
+	#define ECSD_CACHE_CTRL_DIS			0x00
+
+#define ECSD_POWER_OFF_NOTIFICATION	34
+	#define ECSD_NO_POWER_NOTIFICATION	0x00
+	#define ECSD_POWERED_ON				0x01
+	#define ECSD_POWER_OFF_SHORT		0x02
+	#define ECSD_POWER_OFF_LONG			0x03
+
+#define	ECSD_DATA_SECTOR_SIZE		61
+	#define	ECSD_DATA_SECTOR_512		0
+	#define	ECSD_DATA_SECTOR_4K			1
+
+#define ECSD_USE_NATIVE_SECTOR		62
+	#define ECSD_USE_NATIVE_SECTOR_EN	0x01
+
+#define ECSD_NATIVE_SECTOR_SIZE		63
+	#define ECSD_NATIVE_SECTOR_512		0x00
+	#define ECSD_NATIVE_SECTOR_4K		0x01
+	#define ECSD_NATIVE_SECTOR_MSK		0x01
+
+#define ECSD_ENH_START_ADDR			136
+#define ECSD_ENH_SIZE_MULT			140
+#define ECSD_GP_SIZE				143
+#define ECSD_GP1_SIZE				143
+#define ECSD_GP2_SIZE				146
+#define ECSD_GP3_SIZE				149
+#define ECSD_GP4_SIZE				152
+
+#define ECSD_PARTITION_SETTING		155
+	#define ECSD_PS_CMP					0x01
+
+#define ECSD_PARTITIONS_ATTR		156
+	#define ECSD_PA_ENH_4				0x10
+	#define ECSD_PA_ENH_3				0x08
+	#define ECSD_PA_ENH_2				0x04
+	#define ECSD_PA_ENH_1				0x02
+	#define ECSD_PA_ENH_USR				0x01
+
+#define ECSD_MAX_ENH_SIZE_MULT		157
+
+#define ECSD_PARTITIONING_SUP		160
+	#define ECSD_PS_EXT_ATTR_EN			0x04
+	#define ECSD_PS_ENH_ATTR_EN			0x02
+	#define ECSD_PS_PART_EN				0x01
+
+#define ECSD_HPI_MGMT               161
+	#define ECSD_HPI_MGMT_EN            1
+
+#define ECSD_BKOPS_EN				163		// Background operation enable
+	#define ECSD_BKOPS_ENABLE			1
+	#define ECSD_BKOPS_AUTO_EN			2	// EMMC 5.1 - default value is vendor specific, Device is handling BKOPS.
+
+#define ECSD_BKOPS_START			164		// Background operation start
+	#define ECSD_BKOPS_INITIATE			1
+
+#define ECSD_SANITIZE_START			165		// Sanitize operation start
+	#define ECSD_SANITIZE_INITIATE			1
+
+#define ECSD_WR_REL_PARAM			166
+	#define ECSD_WRP_EN_RPMB_REL_WR		0x10
+	#define ECSD_WRP_EN_REL_WR			0x04
+	#define ECSD_WRP_WR_DATA_REL		0x01
+
+#define ECSD_WR_REL_SET				167
+	#define ECSD_WRS_4					0x10
+	#define ECSD_WRS_3					0x08
+	#define ECSD_WRS_2					0x04
+	#define ECSD_WRS_1					0x02
+	#define ECSD_WRS_USR				0x01
+
+#define ECSD_RPMB_SIZE_MULT			168
+
+#define	ECSD_FW_CONFIG				169
+	#define	ECSD_FWUPDATE_DISABLED		(1 << 0)
+
+#define ECSD_USER_WP				171
+	#define ECSD_USER_WP_US_PWR_WP_EN	(1<<0)
+	#define ECSD_USER_WP_US_PERM_WP_EN	(1<<2)
+	#define ECSD_USER_WP_US_PWR_WP_DIS	(1<<3)
+	#define ECSD_USER_WP_US_PERM_WP_DIS	(1<<4)
+	#define ECSD_USER_WP_CD_PERM_WP_DIS	(1<<6)
+	#define ECSD_USER_WP_PERM_PSWD_DIS	(1<<7)
+
+#define ECSD_BOOT_WP				173
+
+#define ECSD_ERASE_GRP_DEF			175
+	#define ECSD_EGD_EN					0x01
+
+#define ECSD_PART_CONFIG			179
+	#define ECSD_PC_ACCESS_MSK			0x7
+
+#define ECSD_ERASED_MEM_CONT		181
+
+#define ECSD_BUS_WIDTH				183
+	#define ECSD_BUS_WIDTH_8			2	// Card is in 8 bit mode
+	#define ECSD_BUS_WIDTH_4			1	// Card is in 4 bit mode
+	#define ECSD_BUS_WIDTH_1			0	// Card is in 1 bit mode
+	#define ECSD_BUS_WIDTH_DDR			4	// Add to width for DDR
+	#define ECSD_BUS_WIDTH_ES			0x80	// (Enhanced strobe) Strobe is provided during Data Out, CRC response and CMD Response
+
+	#define ECSD_STROBE_SUPPORT				184
+	#define ECSD_STROBE_SUPPORT_DISABLED	0	// HS400 (5.0)
+	#define ECSD_STROBE_SUPPORT_ENABLED		1	// HS400ES (5.1)
+
+#define ECSD_HS_TIMING				185
+	#define ECSD_HS_TIMING_DRV_TYPE_SHFT	4
+	#define ECSD_HS_TIMING_HS400			0x3
+	#define ECSD_HS_TIMING_HS200			0x2
+	#define ECSD_HS_TIMING_HS				0x1
+	#define ECSD_HS_TIMING_LS				0x0
+
+#define ECSD_DRIVER_STRENGTH		197
+
+#define ECSD_CARD_TYPE				196
+	#define ECSD_CARD_TYPE_HS400_1_2V	(1<<7)	// Card can run at DDR 200MHz 1.2V
+	#define ECSD_CARD_TYPE_HS400_1_8V	(1<<6)	// Card can run at DDR 200MHz 1.8V
+
+	#define ECSD_CARD_TYPE_HS200_1_2V	(1<<5)	// Card can run at SDR 200MHz 1.2V
+	#define ECSD_CARD_TYPE_HS200_1_8V	(1<<4)	// Card can run at SDR 200MHz 1.8V
+
+	#define ECSD_CARD_TYPE_DDR_1_2V		(1<<3)	// Card can run at 52MHz 1.2V
+	#define ECSD_CARD_TYPE_DDR_1_8V		(1<<2)	// Card can run at 52MHz 1.8V - 3.0V
+
+	#define ECSD_CARD_TYPE_52			(1<<1)	// Card can run at 52MHz
+	#define ECSD_CARD_TYPE_26			(1<<0)	// Card can run at 26MHz
+
+	#define ECSD_CARD_TYPE_DDR			( ECSD_CARD_TYPE_DDR_1_8V | ECSD_CARD_TYPE_DDR_1_2V )
+	#define ECSD_CARD_TYPE_HS400		( ECSD_CARD_TYPE_HS400_1_8V | ECSD_CARD_TYPE_HS400_1_2V )
+	#define ECSD_CARD_TYPE_HS200		( ECSD_CARD_TYPE_HS200_1_8V | ECSD_CARD_TYPE_HS200_1_2V )
+	#define ECSD_CARD_TYPE_52MHZ		( ECSD_CARD_TYPE_DDR_1_8V | ECSD_CARD_TYPE_DDR_1_2V | ECSD_CARD_TYPE_52 )
+	#define ECSD_CARD_TYPE_MSK			0xff
+
+#define ECSD_REV					192
+	#define ECSD_REV_V5_1				8
+	#define ECSD_REV_V5					7
+	#define ECSD_REV_V4_5				6
+	#define ECSD_REV_V4_41				5
+	#define ECSD_REV_V4_4				4
+	#define ECSD_REV_V4_3				3
+	#define ECSD_REV_V4_2				2
+	#define ECSD_REV_V4_1				1
+	#define ECSD_REV_V4					0
+
+#define ECSD_OUT_OF_INTERRUPT_TIME	198
+#define ECSD_PARTITION_SWITCH_TIME	199
+
+#define ECSD_SEC_CNT				212
+	#define ECSD_SEC_CNT_2GB			0x400000
+
+#define ECSD_S_A_TIMEOUT			217
+#define ECSD_HC_WP_GRP_SIZE			221
+#define ECSD_REL_WR_SEC_C			222
+#define ECSD_ERASE_MULT				223	// Erase Timeout Multiplier
+#define ECSD_ACC_SIZE				225
+#define ECSD_ERASE_GRP_SIZE			224
+#define ECSD_BOOT_SIZE_MULT			226
+#define ECSD_SEC_TRIM_MULT			229
+#define ECSD_SEC_ERASE_MULT			230 // Secure Erase Timeout Multiplier
+
+#define ECSD_SEC_FEATURE_SUPPORT	231
+	#define ECSD_SEC_SANITIZE			0x40 // SANITIZE support
+	#define ECSD_SEC_GB_CL_EN			0x10 // TRIM support
+	#define ECSD_SEC_BD_BLK_EN			0x04 // Secure purge Bad blk mgnt support
+	#define ECSD_SEC_ER_EN				0x01 // Secure purge support
+
+#define ECSD_TRIM_MULT				232
+
+#define ECSD_BKOPS_STATUS			246  // Background operation support
+	#define ECSD_BS_OPERATIONS_NONE			0
+	#define ECSD_BS_OPERATIONS_NON_CRITICAL	1
+	#define ECSD_BS_OPERATIONS_IMPACTED		2
+	#define ECSD_BS_OPERATIONS_CRITICAL		3
+
+#define ECSD_CACHE_SIZE				249
+
+#define ECSD_POWER_OFF_LONG_TIME	247  // Power off long switch timeout
+
+#define	ECSD_FIRMWARE_VERSION		254	// Firmware version, 8 bytes
+
+#define ECSD_PRE_EOL_INFO				267
+#define ECSD_DEVICE_LIFE_TIME_EST_TYP_A	268
+#define ECSD_DEVICE_LIFE_TIME_EST_TYP_B	269
+
+#define	ECSD_FFU_ARG				487	// FFU argument, 4 bytes
+
+#define ECSD_FFU_FEATURE			492
+	#define	ECSD_FFU_OPCODE_SUPPORTED	(1 << 0)	// Device support MODE_OPERATION_CODES field
+
+#define ECSD_SUPPORTED_MODES		493
+	#define	ECSD_FFU_SUPPORTED		(1 << 0)	// Device support FFU
+	#define	ECSD_VSM_SUPPORTED		(1 << 1)	// Device support Vendor Specific Mode
+
+#define ECSD_BKOPS_SUPPORTED		502  // Background operation support
+	#define ECSD_BKOPS_SUP				1
+
+#define ECSD_HPI_FEATURES			503
+	#define EXT_HPI_FEATURES_SUP_CMD12	0x02
+	#define EXT_HPI_FEATURES_SUPPORTED	0x01
+
+#define ECSD_S_CMD_SET				504
+
+#endif
+
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/include/mmc.h $ $Rev: 948566 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/include/sd.h

@@ -0,0 +1,352 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2008, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef _SD_H_INCLUDED
+#define _SD_H_INCLUDED
+
+#define SD_CID_SIZE					16
+#define SD_CSD_SIZE					16
+#define SD_ERASE_TIMEOUT			250			// 250ms
+
+#define	SD_GO_IDLE_STATE			0
+#define	SD_ALL_SEND_CID				2
+#define	SD_SEND_RELATIVE_ADDR				3
+	#define SD_SEND_RELATIVE_ADDR_RETRIES	255
+
+#define	SD_SET_DSR					4
+#define	SD_SLEEP_AWAKE				5
+	#define SD_SA_SLEEP				(1 << 15 )
+
+#define	SD_SWITCH_FUNC				6
+	#define SD_SF_MODE_SET			0x1
+	#define SD_SF_MODE_CHECK		0x0
+
+	#define SD_SF_GRP_DFLT			0x0
+	#define SD_SF_GRP_BUS_SPD		0x0		// Bus Speed
+	#define SD_SF_GRP_CMD_EXT		0x1		// Command System Extension
+	#define SD_SF_GRP_DRV_STR		0x2		// Driver Strength
+	#define SD_SF_GRP_CUR_LMT		0x3		// Current Limit
+
+	#define SD_SF_CUR_FCN			0xf
+
+	#define SD_SF_STATUS_SIZE		64
+
+#define	SD_SEL_DES_CARD				7
+#define	SD_SEND_IF_COND				8
+	#define SD_SIC_VHS_27_36V		1
+	#define SD_SIC_TEST_PATTERN		0xaa
+
+#define	SD_SEND_EXT_CSD				8
+#define	SD_SEND_CSD					9
+#define	SD_SEND_CID					10
+#define	SD_VOLTAGE_SWITCH			11
+#define	SD_STOP_TRANSMISSION		12
+#define	SD_SEND_STATUS				13
+// Card/Device Status Response Bits
+	#define	CDS_OUT_OF_RANGE			(1 << 31)
+	#define	CDS_ADDRESS_ERROR			(1 << 30)
+	#define	CDS_BLOCK_LEN_ERROR			(1 << 29)
+	#define	CDS_ERASE_SEQ_ERROR			(1 << 28)
+	#define	CDS_ERASE_PARAM				(1 << 27)
+	#define	CDS_WP_VIOLATION			(1 << 26)
+	#define	CDS_CARD_IS_LOCKED			(1 << 25)
+	#define	CDS_LOCK_UNLOCK_FAILED		(1 << 24)
+	#define	CDS_COM_CRC_ERROR			(1 << 23)
+	#define	CDS_ILLEGAL_COMMAND			(1 << 22)
+	#define	CDS_CARD_ECC_FAILED			(1 << 21)
+	#define	CDS_CC_ERROR				(1 << 20)
+	#define	CDS_ERROR					(1 << 19)
+	#define	CDS_UNDERRUN				(1 << 18)
+	#define	CDS_OVERRUN					(1 << 17)
+	#define	CDS_CID_CSD_OVERWRITE		(1 << 16)
+	#define	CDS_WP_ERASE_SKIP			(1 << 15)
+	#define	CDS_CARD_ECC_DISABLED		(1 << 14)
+	#define	CDS_ERASE_RESET				(1 << 13)
+
+	#define CDS_CUR_STATE_MSK			( 0xf << 9 )
+	#define	CDS_CUR_STATE_IDLE			(0 << 9)
+	#define	CDS_CUR_STATE_READY			(1 << 9)
+	#define	CDS_CUR_STATE_IDENT			(2 << 9)
+	#define	CDS_CUR_STATE_STANDBY		(3 << 9)
+	#define	CDS_CUR_STATE_TRAN			(4 << 9)
+	#define	CDS_CUR_STATE_DATA			(5 << 9)
+	#define	CDS_CUR_STATE_RCV			(6 << 9)
+	#define	CDS_CUR_STATE_PRG			(7 << 9)
+	#define	CDS_CUR_STATE_DIS			(8 << 9)
+
+	#define	CDS_READY_FOR_DATA			(1 << 8)
+	#define	CDS_SWITCH_ERROR			(1 << 7)
+	#define	CDS_URGENT_BKOPS			(1 << 6)
+	#define	CDS_APP_CMD_S				(1 << 5)
+
+	#define CDS_ERROR_MSK				(	CDS_OUT_OF_RANGE		| \
+											CDS_ADDRESS_ERROR		| \
+											CDS_BLOCK_LEN_ERROR		| \
+											CDS_ERASE_SEQ_ERROR		| \
+											CDS_ERASE_PARAM			| \
+											CDS_WP_VIOLATION		| \
+											CDS_CARD_IS_LOCKED		| \
+											CDS_LOCK_UNLOCK_FAILED	| \
+											CDS_COM_CRC_ERROR		| \
+											CDS_ILLEGAL_COMMAND		| \
+											CDS_CARD_ECC_FAILED		| \
+											CDS_CC_ERROR			| \
+											CDS_ERROR				| \
+											CDS_SWITCH_ERROR 		| \
+	CDS_CID_CSD_OVERWRITE )
+
+#define	SD_GO_INACTIVE_STATE			15
+#define	SD_SET_BLOCKLEN					16
+#define	SD_READ_SINGLE_BLOCK			17
+#define	SD_READ_MULTIPLE_BLOCK			18
+#define SD_SEND_TUNING_BLOCK			19
+#define	SD_SPEED_CLASS_CONTROL			20
+#define SD_SET_UPPER_ADDR				22
+#define SD_SET_BLOCK_COUNT				23
+#define	SD_WRITE_BLOCK					24
+#define	SD_WRITE_MULTIPLE_BLOCK			25
+#define	SD_PROGRAM_CSD					27
+#define	SD_SET_WRITE_PROT				28
+#define	SD_CLR_WRITE_PROT				29
+#define	SD_SEND_WRITE_PROT				30
+#define	SD_ERASE_WR_BLK_START			32
+#define	SD_ERASE_WR_BLK_END				33
+#define	SD_ERASE						38
+	#define SD_ERASE_NORM				0x00000000
+	#define SD_ERASE_TRIM				0x00000001
+	#define SD_ERASE_GARBAGE_COLLECT	0x80008001
+	#define SD_ERASE_SECURE_TRIM		0x80000001
+	#define SD_ERASE_SECURE				0x80000000
+#define	SD_LOCK_UNLOCK					42
+	#define SD_LU_ERASE					0x08
+	#define SD_LU_LOCK					0x04
+	#define SD_LU_UNLOCK				0x00
+	#define SD_LU_CLR_PWD				0x02
+	#define SD_LU_SET_PWD				0x01
+	#define SD_LU_PWD_SIZE				16		// max password size
+
+#define SD_READ_EXTR_SINGLE				48
+#define SD_WRITE_EXTR_SINGLE			49
+#define SD_READ_EXTR_MULTI				58
+#define SD_WRITE_EXTR_MULTI				59
+	#define SD_EXTR_SIZE				512
+	#define SD_EXTR_MIO( _t )			( (_t) & SD_EXTR_MIO_MSK )
+	#define SD_EXTR_IO					( 1 << 31 )
+	#define SD_EXTR_MEM					( 0 << 31 )
+	#define SD_EXTR_MIO_MSK				( 1 << 31 )
+	#define SD_EXTR_MW					( 1 << 26 )
+	#define SD_EXTR_MWM( _m )			( (_m) & SD_EXTR_MWM_MSK )
+	#define SD_EXTR_MWM_MSK				( 1 << 26 )
+	#define SD_EXTR_FNO( _f )			( ( (_f) & 0xf ) << 27 )
+	#define SD_EXTR_ADDR( _a )			( ( (_a) & 0x1ffff ) << 9 )
+	#define SD_EXTR_LEN_MSK( _l, _m )	( (_m) ? ( (_l) & 0xff ) : ( ( (_l) - 1 ) & 0x1ff ) )
+
+#define	SD_APP_CMD						55
+#define	SD_GEN_CMD						56
+#define	SD_READ_OCR						58
+#define	SD_CRC_ON_OFF					59
+
+// ACMDS - preceded with APP_CMD (CMD55)
+#define	SD_AC_SET_BUS_WIDTH				6
+	#define SD_BUS_WIDTH_1				0
+	#define SD_BUS_WIDTH_4				2
+
+#define SD_AC_SD_STATUS					13
+	#define SD_STATUS_SIZE				64
+#define SD_AC_SEND_NUM_WR_BLOCKS		22
+#define SD_AC_SET_WR_BLK_ERASE_COUNT	23
+#define	SD_AC_SEND_OP_COND				41
+#define SD_AC_SET_CLR_CARD_DETECT		42
+#define	SD_AC_SEND_SCR					51
+	#define	SD_SCR_SIZE					8
+
+// ASSD commands
+#define SD_READ_SEC_CMD					34
+#define SD_WRITE_SEC_CMD				35
+	#define SD_SEC_CMD_SIZE				512
+#define SD_SEND_PSI						36
+	#define SD_PSI_ASSD_SR				0	// ASSD Status Register
+	#define SD_PSI_ASSD_PR				4	// ASSD Properties Register
+	#define SD_PSI_ASSD_RNR				6	// ASSD Random Number Register
+	#define SD_PSI_SIZE					32
+#define SD_CONTROL_ASSD_SYSTEM			37
+#define SD_DIRECT_SECURE_READ			50
+#define SD_DIRECT_SECURE_WRITE			57
+
+typedef struct _sd_cid_t {
+	_Uint8t		mid;		// Manufacture ID
+	_Uint8t		oid[3];		// OEM/Application ID
+	_Uint8t		pnm[6];		// Product name
+	_Uint8t		prv;		// Product revision
+	_Uint32t	psn;		// Product serial number
+	_Uint16t	mdt;		// Manufacture date
+} sd_cid_t;
+
+typedef struct _sd_scr_t {
+	_Uint8t		scr_structure;	// SCR structure
+
+// SD version is a combination of sd_spec, sd_spec3, sd_spec4 and sd_specx. See specification.
+#define SCR_SPEC_VER_0		0	// Version 1.0 - 1.01
+#define SCR_SPEC_VER_1		1	// Version 1.10
+#define SCR_SPEC_VER_2		2	// Version 2.0 or Version 3.0X
+
+#define SCR_SPEC3_VER_3		1	// Version 3
+
+#define SCR_SPEC4_VER_4		1	// Version 4
+
+#define SCR_SPECX_VER_5		1	// Version 5
+#define SCR_SPECX_VER_6		2	// Version 6
+#define SCR_SPECX_VER_7		3	// Version 7
+#define SCR_SPECX_VER_8		4	// Version 8
+	_Uint8t		sd_spec;		// Physical layer specification
+	_Uint8t		data_stat_after_erase;
+	_Uint8t		sd_security;
+
+#define SCR_BUS_WIDTH_1		(1 << 0)
+#define SCR_BUS_WIDTH_4		(1 << 2)
+	_Uint8t		sd_bus_widths;
+	_Uint8t		sd_spec3;
+	_Uint8t		sd_spec4;
+	_Uint8t		sd_specx;
+	_Uint8t		ex_security;
+#define SCR_CMD58_59_SUP	(1 << 3)
+#define SCR_CMD48_49_SUP	(1 << 2)
+#define SCR_CMD23_SUP		(1 << 1)
+#define SCR_CMD20_SUP		(1 << 0)
+	_Uint8t		cmd_support;
+} sd_scr_t;
+
+typedef struct _sd_sds_t {		// SD Status
+	_Uint32t	speed_class;
+	_Uint32t	uhs_speed_grade;
+	_Uint32t	au_size;
+	_Uint32t	uhs_au_size;
+	_Uint32t	erase_timeout;
+	_Uint32t	erase_offset;
+#define SD_PERF_CLASS_A2		2
+	_Uint32t	perf_class;
+	_Uint32t	perf_enh;
+} sd_sds_t;
+
+typedef struct _sd_switch_cap {
+	_Uint32t		dtr_max_hs;
+
+#define SD_BUS_MODE_LS			( 1 << 0 )
+#define SD_BUS_MODE_SDR12		( 1 << 0 )
+#define SD_BUS_MODE_HS			( 1 << 1 )
+#define SD_BUS_MODE_SDR25		( 1 << 1 )
+#define SD_BUS_MODE_SDR50		( 1 << 2 )
+#define SD_BUS_MODE_SDR104		( 1 << 3 )
+#define SD_BUS_MODE_DDR50		( 1 << 4 )
+#define SD_BUS_MODE_UHS			( SD_BUS_MODE_SDR50 | SD_BUS_MODE_SDR104 | SD_BUS_MODE_DDR50 )
+#define SD_BUS_MODE_MSK			0x1f
+	_Uint32t		bus_mode;
+
+#define SD_CMD_SYS_EC			( 1 << 1 )	// eCommerce
+#define SD_CMD_SYS_OTP			( 1 << 3 )
+#define SD_CMD_SYS_ASSD			( 1 << 4 )
+	_Uint32t		cmd_sys;
+
+#define SD_DRV_TYPE_B			0x01
+#define SD_DRV_TYPE_A			0x02
+#define SD_DRV_TYPE_C			0x04
+#define SD_DRV_TYPE_D			0x08
+#define SD_DRV_TYPE_MSK			0x0f
+	_Uint32t		drv_type;
+
+#define SD_CURR_LIMIT_200		( 1 << 0 )
+#define SD_CURR_LIMIT_400		( 1 << 1 )
+#define SD_CURR_LIMIT_600		( 1 << 2 )
+#define SD_CURR_LIMIT_800		( 1 << 3 )
+#define SD_CURR_LIMIT_MSK		0xf
+	_Uint32t		curr_limit;
+} sd_switch_cap_t;
+
+#define SD_FCN_PG_SZ		512
+
+typedef struct _sd_fcn_ext_hdr {
+	uint8_t		structure_revsion[2];
+	uint8_t		gen_info_length[2];
+	uint8_t		number_extensions;
+	uint8_t		rsvd[11];
+} sd_fcn_ext_hdr;
+
+typedef struct _sd_fcn_ext {
+#define SFC_PWR_MGNT		0x01
+#define SFC_PERF_ENH		0x02
+	uint16_t		sfc;		// Standard Function Code
+	uint16_t		fcc;		// Function Capability Code
+	uint16_t		fmc;		// Function Manufacturer Code
+	uint8_t			fmn[16];	// Function Manufacturer Name
+	uint16_t		pfc;		// Particular Function Code
+	uint8_t			fn[16];		// Function Name
+	uint16_t		pne;		// Pointer to Next Extension
+	uint8_t			nrs;		// Number of Register Sets
+	uint8_t			rsvd;
+#define SD_FCN_EXT_FNO( _rsa )			( ( (_rsa) >> 18 ) & 0xf )
+#define SD_FCN_EXT_SADDR( _rsa )		( (_rsa) & 0x1ffff )
+	uint32_t		rsa[1];		// Variable length Register Set Addresses
+} sd_fcn_ext;
+
+// Power Management Function Register definitions
+#define PWR_MGNT_REV					0		// Ronly
+	#define PWR_MGNT_REV_MSK			0xf
+#define PWR_MGNT_STATUS					1		// Ronly
+	#define PWR_MGNT_STATUS_PDMS		0x40	// Power down support
+	#define PWR_MGNT_STATUS_PSUS		0x20	// Power sustenance support
+	#define PWR_MGNT_STATUS_POFS		0x10	// Power off support
+	#define PWR_MGNT_STATUS_PDMR		0x04	// Power down mode ready
+	#define PWR_MGNT_STATUS_PSUR		0x02	// Power sustenance request
+	#define PWR_MGNT_STATUS_POFR		0x01	// Power off ready
+#define PWR_MGNT_SETTING				2		// R/W
+	#define PWR_MGNT_SETTING_PDMN		0x04	// Power down mode notification
+	#define PWR_MGNT_SETTING_PSUN		0x02	// Power sustenance notification
+	#define PWR_MGNT_SETTING_POFN		0x01	// Power off notification
+
+// Performance Enhancement Function Register definitions
+#define PERF_ENH_REV					0		// Ronly
+#define PERF_ENH_EVT_SUP				1		// Ronly
+#define PERF_ENH_MAINT_SUP				2		// Ronly
+#define PERF_ENH_MAINT_URGENCY			3		// Ronly
+#define PERF_ENH_CACHE_SUP				4		// Ronly
+	#define PERF_ENH_CACHE_SUPPORTED	0x1
+#define PERF_ENH_CQ_DEPTH				6		// Ronly
+#define PERF_ENH_TASK_STATUS			8		// 8 - 15 Ronly
+#define PERF_ENH_EVT_FX					257		// R/W
+	#define PERF_ENH_EVT_FX_EN			0x1
+#define PERF_ENH_MAINT_TYP				258		// R/W
+	#define PERF_ENH_MAINT_TYP_HOST_EN		0x2
+	#define PERF_ENH_MAINT_CARD_EN		0x1
+#define PERF_ENH_MAINT					259		// R/W
+	#define PERF_ENH_MAINT_HOST_START	0x1
+#define PERF_ENH_CACHE					260		// R/W
+	#define PERF_ENH_CACHE_EN			0x01
+#define PERF_ENH_CACHE_FLUSH			261		// R/W
+	#define PERF_ENH_CACHE_FLUSH_START	0x01
+#define PERF_ENH_CQ_EN					262		// R/W
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/include/sd.h $ $Rev: 953628 $")
+#endif
+

src/hardware/devb/sdmmc/sdiodi/include/sdiodi.h

@@ -0,0 +1,489 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2008, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef _SDIODI_H_INCLUDED
+#define _SDIODI_H_INCLUDED
+
+#include <inttypes.h>
+#include <sys/types.h>
+
+#define	SDIO_SUCCESS				0
+#define	SDIO_FAILURE				1
+#define	SDIO_FALSE					0
+#define	SDIO_TRUE					1
+#define SDIO_TIME_DEFAULT			1000
+#define SDIO_BKOPS_MAX_TIMEOUT		(4 * 60 * 1000)
+
+#define SDIO_DATA_PTR_V( _p )		( (void *)(uintptr_t)(_p) )
+#define SDIO_DATA_PTR_P( _p )		( (uintptr_t)(_p) )
+
+struct sdio_cmd;
+struct sdio_device;
+struct sdio_connection;
+typedef struct _sdio_sge				sdio_sge_t;
+typedef struct _sdio_cid				sdio_cid_t;
+typedef struct _sdio_csd				sdio_csd_t;
+typedef struct _sdio_ecsd				sdio_ecsd_t;
+typedef struct _sdio_hc_info			sdio_hc_info_t;
+typedef struct _sdio_dev_info			sdio_dev_info_t;
+typedef struct _sdio_funcs				sdio_funcs_t;
+typedef struct _sdio_connect_parm		sdio_connect_parm_t;
+typedef struct _sdio_device_ident		sdio_device_ident_t;
+typedef struct _sdio_device_instance	sdio_device_instance_t;
+
+#define SDIO_RSP_SIZE					16
+#define SDIO_CID_SIZE					16
+#define SDIO_CSD_SIZE					16
+
+struct _sdio_cid {
+	_Uint32t	mid;		// Manufacture ID
+	_Uint32t	oid;		// OEM ID
+	char		pnm[8];		// Product name
+	_Uint32t	prv;		// Product revision
+	_Uint32t	psn;		// Product serial number
+	_Uint32t	month;		// Month
+	_Uint32t	year;		// Year
+};
+
+struct _sdio_csd {
+#define CSD_STRUCT_VER_10		0	// MMCA V1.0 / SD Standard Capacity
+#define CSD_STRUCT_VER_20		1	// SD High Capacity / Extended Capacity
+#define CSD_STRUCT_VER_30		2	// SD Ultra Capacity
+#define CSD_STRUCT_VER_11		1	// MMCA V1.1
+#define CSD_STRUCT_VER_12		2	// EMMC Version 4.1–4.2–4.3-4.41-4.5-4.51-5.0-5.01-5.1
+#define CSD_STRUCT_VER_EXT_CSD	3	// EMMC Version is coded in the CSD_STRUCTURE byte in EXT_CSD
+	_Uint8t		csd_structure;		// CSD structure
+
+#define	CSD_SPEC_VER_0			0   // 1.0 - 1.2
+#define	CSD_SPEC_VER_1			1   // 1.4 -
+#define	CSD_SPEC_VER_2			2   // 2.0 - 2.2
+#define	CSD_SPEC_VER_3			3   // 3.1 - 3.2 - 3.31
+#define	CSD_SPEC_VER_4			4   // 4.0 - 4.1
+	_Uint8t		spec_vers;
+
+	_Uint8t		taac;
+	_Uint8t		nsac;
+	_Uint8t		tran_speed;
+	_Uint8t		rsvd;
+
+//                                   Class
+#define CCC_BASIC		( 1 << 0 )	// 0 Basic: CMD 0-10,12-15,19
+#define CCC_BLOCK_READ	( 1 << 2 )	// 2 Block Read: CMD 16-18
+#define CCC_BLOCK_WRITE	( 1 << 4 )	// 4 Block Write: CMD 16,24-27
+#define CCC_ERASE		( 1 << 5 )	// 5 Erase:  CMD 32-39
+#define CCC_WRITE_PROT	( 1 << 6 )	// 6 Write Protection: CMD 28-31
+#define CCC_LOCK_DEVICE	( 1 << 7 )	// 7 Lock Devcie: CMD 16,40,42
+#define CCC_APP_SPEC	( 1 << 8 )	// 8 Application specific: CMD 55-57, ACMD 6,13,22,23,41,42,51
+#define CCC_IO_MODE		( 1 << 9 )	// 9 (9) I/O mode: CMD 5,39,40,52,53
+#define CCC_SWITCH		( 1 << 10 )	// 10 High speed switch: CMD 6,34-37,50
+	_Uint16t	ccc;
+
+	_Uint8t		read_bl_len;
+	_Uint8t		read_bl_partial;
+	_Uint8t		write_blk_misalign;
+	_Uint8t		read_blk_misalign;
+
+	_Uint8t		dsr_imp;
+	_Uint8t		rsvd2[3];
+
+#define CSD_VER_10_CSIZE_MAX		0xfff			// 12 bits
+#define CSD_VER_20_CSIZE_MAX		0x3fffff		// 22 bits
+#define CSD_VER_30_CSIZE_MAX		0xfffffff		// 28 bits
+	_Uint32t	c_size;
+
+	_Uint8t		vdd_r_curr_min;
+	_Uint8t		vdd_r_curr_max;
+	_Uint8t		vdd_w_curr_min;
+	_Uint8t		vdd_w_curr_max;
+
+	_Uint8t		c_size_mult;
+	_Uint8t		erase_blk_en;
+	_Uint8t		erase_grp_size;
+	_Uint8t		erase_grp_mult;
+
+	_Uint8t		sector_size;
+	_Uint8t		wp_grp_size;
+	_Uint8t		wp_grp_enable;
+	_Uint8t		r2w_factor;
+
+	_Uint8t		write_bl_len;
+	_Uint8t		write_bl_partial;
+	_Uint8t		copy;
+	_Uint8t		write_protect;
+
+	_Uint8t		ecc;
+	_Uint8t		rsvd3[3];
+
+	_Uint32t	dtr_max;
+	_Uint32t	blksz;
+	_Uint64t	sectors;
+};
+
+struct _sdio_ecsd {
+	_Uint32t		blksz;
+	_Uint32t		sectors;
+	_Uint32t		acc_size;
+	_Uint32t		dtr_max_hs;
+	_Uint32t		s_a_timeout;		// 100ns units
+
+	_Uint8t			ext_csd_rev;
+	_Uint8t			card_type;
+	_Uint8t			driver_strength;
+
+	_Uint8t			erase_grp_def;
+	_Uint8t			hc_erase_group_size;
+	_Uint8t			hc_wp_grp_size;
+	_Uint8t			user_wp;
+	_Uint8t			part_config;
+	_Uint8t			strobe;
+	_Uint8t			bkops_en;
+};
+
+struct _sdio_sge {
+	_Uint64t sg_address;				// Scatter/Gather address
+	_Uint32t sg_count;					// Scatter/Gather count
+	_Uint32t rsvd;
+};
+
+// command flags
+#define	SCF_CTYPE_BC		(1 << 0)
+#define	SCF_CTYPE_BCR		(1 << 1)
+#define	SCF_CTYPE_AC		(1 << 2)
+#define	SCF_CTYPE_ADTC		(1 << 3)
+
+#define	SCF_RSP_PRESENT		(1 << 4)
+#define	SCF_RSP_136			(1 << 5)	// 136 bit response
+#define	SCF_RSP_CRC			(1 << 6)	// expect valid crc
+#define	SCF_RSP_BUSY		(1 << 7)	// card may send busy
+#define	SCF_RSP_OPCODE		(1 << 8)	// response contains opcode
+
+#define	SCF_RSP_NONE		(0)
+#define	SCF_RSP_R1			(SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_OPCODE)
+#define	SCF_RSP_R1B			(SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_OPCODE | SCF_RSP_BUSY)
+#define	SCF_RSP_R2			(SCF_RSP_PRESENT | SCF_RSP_136 | SCF_RSP_CRC)
+#define	SCF_RSP_R3			(SCF_RSP_PRESENT)
+#define	SCF_RSP_R6			(SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_OPCODE)
+#define	SCF_RSP_R7			(SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_OPCODE)
+
+#define	SCF_DIR_IN			(1 << 9)	// data read
+#define	SCF_DIR_OUT			(1 << 10)	// data write
+#define	SCF_DATA_MSK		(SCF_DIR_IN | SCF_DIR_OUT)
+#define	SCF_APP_CMD			(1 << 11)	// app command (cmd 55)
+#define	SCF_SBC				(1 << 12)	// auto issue set block count (cmd 23)
+#define	SCF_WAIT_DRDY		(1 << 13)	// wait ready for data
+#define	SCF_SBC_RLW			(1 << 14)	// set block count (cmd 23) with reliable write bit
+#define	SCF_SUA				(1 << 15)	// set upper address
+
+// driver internal
+#define	SCF_DATA_PHYS		(1 << 24)	// data physical address
+#define	SCF_MULTIBLK		(1 << 25)
+
+// command status
+#define CS_CMD_INPROG		0x00
+#define CS_CMD_CMP			0x01
+#define CS_CMD_ABORTED		0x02
+#define CS_CMD_CMP_ERR		0x03
+#define CS_CMD_IDX_ERR		0x04
+#define CS_CMD_TO_ERR		0x05
+#define CS_CMD_CRC_ERR		0x06
+#define CS_CMD_END_ERR		0x07
+#define CS_DATA_TO_ERR		0x08
+#define CS_DATA_CRC_ERR		0x09
+#define CS_DATA_END_ERR		0x0a
+#define CS_CARD_REMOVED		0x0b
+
+#define SDIO_CONNECT_WILDCARD	(-1)
+struct _sdio_device_ident {
+	_Uint16t		vid;						// Vendor ID
+	_Uint16t		did;						// Device ID
+#define DEV_TYPE_MMC		1
+#define DEV_TYPE_SD			2
+#define DEV_TYPE_SDIO		3
+	_Uint16t		dtype;						// Device Type
+	_Uint16t		ccd;						// Class code
+};
+
+struct _sdio_device_instance {
+	_Uint32t			path;
+	_Uint32t			func;
+	_Uint32t			generation;
+	sdio_device_ident_t	ident;
+};
+
+struct _sdio_dev_info {
+#define DEV_TYPE_MMC		1
+#define DEV_TYPE_SD			2
+	_Uint32t			dtype;
+#ifndef DEV_FLAG_WP
+#define DEV_FLAG_WP				0x1
+#define DEV_FLAG_CARD_LOCKED	0x2
+#endif
+	_Uint32t			flags;
+
+	_Uint32t			mid;			// Manufacture ID
+
+	_Uint32t			oid;			// OEM ID
+	_Uint8t				pnm[8];			// Product name
+	_Uint32t			prv;			// Product revision
+	_Uint32t			psn;			// Product serial number
+	_Uint32t			month;			// Month
+	_Uint32t			year;			// Year
+	_Uint8t				vu[8];			// Vendor Unique ie SanDisk fw revision
+
+	_Uint32t			rca;
+
+	_Uint32t			spec_vers;
+	_Uint32t			spec_rev;
+
+	_Uint32t			security;
+
+#define DEV_CAP_HC				(1ULL << 0)	// high capacity
+#define DEV_CAP_HS				(1ULL << 1)	// high speed
+#define DEV_CAP_HS200			(1ULL << 2)	// high speed 200
+#define DEV_CAP_DDR50			(1ULL << 3)	// DDR
+#define DEV_CAP_UHS				(1ULL << 4)	// UHS
+#define DEV_CAP_TRIM			(1ULL << 5)	// TRIM supported
+#define DEV_CAP_SECURE			(1ULL << 6)	// Secure Purge supported
+#define DEV_CAP_SECURE_TRIM		(DEV_CAP_SECURE | DEV_CAP_TRIM)
+#define DEV_CAP_SANITIZE		(1ULL << 7)	// SANITIZE supported
+#define DEV_CAP_BKOPS			(1ULL << 8)	// Background Operations supported
+#define DEV_CAP_CMD23			(1ULL << 9)	// CMD23 supported
+#define DEV_CAP_SLEEP			(1ULL << 10)	// SLEEP/AWAKE supported
+#define DEV_CAP_ASSD			(1ULL << 11)	// ASSD
+#define DEV_CAP_HPI_CMD12		(1ULL << 12)
+#define DEV_CAP_HPI_CMD13		(1ULL << 13)
+#define DEV_CAP_DISCARD			(1ULL << 14)	// Discard supported
+#define DEV_CAP_CACHE			(1ULL << 15)
+#define DEV_CAP_HS400			(1ULL << 16)
+#define DEV_CAP_PWROFF_NOTIFY	(1ULL << 17)	// Power off notify supported
+#define DEV_CAP_HS400ES			(1ULL << 18)
+#define DEV_CAP_BKOPS_AUTO		(1ULL << 19)	// Auto Background Operations supported
+#define DEV_CAP_UC				(1ULL << 20)	// Ultra Capacity (2TB - 128TB)
+#define DEV_CAP_WR_REL			(1ULL << 21)	// Reliable Write supported
+#define DEV_CAP_WR_REL_ENH		(1ULL << 22)	// Enhanced Reliable Write supported
+	_Uint64t			caps;
+
+	_Uint32t			dtr;			// current data transfer rate
+#define TIMING_HS400ES		10
+#define TIMING_HS400		9
+#define TIMING_HS200		8
+#define TIMING_SDR104		7
+#define TIMING_SDR50		6
+#define TIMING_SDR25		5
+#define TIMING_SDR12		4
+#define TIMING_DDR50		3
+#define TIMING_HS			2
+#define TIMING_LS			1
+	_Uint32t			timing;			// current timing
+	_Uint32t			bus_width;		// current bus width
+	_Uint64t			sectors;
+	_Uint32t			sector_size;
+	_Uint32t			super_page_size;
+	_Uint32t			native_sector_size;
+	_Uint32t			wp_size;
+	_Uint32t			erase_size;
+	_Uint32t			optimal_trim_size;
+	_Uint32t			optimal_read_size;
+	_Uint32t			optimal_write_size;
+#define SPEED_CLASS_0	0x00
+#define SPEED_CLASS_2	0x01
+#define SPEED_CLASS_4	0x02
+#define SPEED_CLASS_6	0x03
+#define SPEED_CLASS_10	0x04
+	_Uint32t			speed_class;
+
+	_Uint32t			rel_wr_sec_c;
+
+	_Uint32t			rsvd[14];
+};
+
+struct _sdio_hc_info {
+#define SDIO_NAME_MAX		64
+	char			name[SDIO_NAME_MAX];
+
+#define	HC_CAP_SLOT_TYPE_EMBEDDED	(1ULL << 0)	// embedded card
+#define	HC_CAP_PIO					(1ULL << 1)	// supports PIO
+#define	HC_CAP_DMA					(1ULL << 2)	// supports DMA 32 bit address
+#define	HC_CAP_DMA64				(3ULL << 2)	// supports DMA 64 bit address
+#define	HC_CAP_DMA_MSK				(HC_CAP_DMA | HC_CAP_DMA64)
+#define	HC_CAP_BW4					(1ULL << 4)	// 4 bit bus supported
+#define	HC_CAP_BW8					(1ULL << 5)	// 8 bit bus supported
+#define HC_CAP_BW_MSK				( HC_CAP_BW4 | HC_CAP_BW8 )
+#define	HC_CAP_ACMD12				(1ULL << 6)	// auto stop cmd(12) supported
+#define	HC_CAP_ACMD23				(1ULL << 7)	// auto set block count cmd(23) supported
+#define HC_CAP_SLEEP				(1ULL << 8)
+
+#define	HC_CAP_HS					(1ULL << 9)	// High speed device supported
+#define	HC_CAP_SDR12				(1ULL << 10)
+#define	HC_CAP_SDR25				(1ULL << 11)
+#define	HC_CAP_SDR50				(1ULL << 12)
+#define	HC_CAP_SDR104				(1ULL << 13)
+#define	HC_CAP_DDR50				(1ULL << 14)	// Dual Data Rate supported
+#define HC_CAP_UHS( _caps )			( (_caps) & ( HC_CAP_SDR12 | HC_CAP_SDR25 | \
+										HC_CAP_SDR50 | HC_CAP_SDR104 | HC_CAP_DDR50) )
+#define	HC_CAP_HS200				(1ULL << 15)
+#define	HC_CAP_HS400				(1ULL << 16)
+#define HC_CAP_TIMING_MSK			( HC_CAP_HS | HC_CAP_DDR50 |		\
+										HC_CAP_SDR12 | HC_CAP_SDR25 |	\
+										HC_CAP_SDR50 | HC_CAP_SDR104 |	\
+										HC_CAP_HS200 | HC_CAP_HS400 | HC_CAP_HS400ES)
+
+#define	HC_CAP_XPC_3_3V				(1ULL << 17)	// > 150mA at 3.3V is supported
+#define	HC_CAP_XPC_3_0V				(1ULL << 18)	// > 150mA at 3.0V is supported
+#define	HC_CAP_XPC_1_8V				(1 << 19)	// > 150mA at 1.8V is supported
+#define HC_CAP_XPC( _caps )			( ( ( _caps ) >> 17 ) & 0x07 )
+
+#define	HC_CAP_200MA				(1ULL << 20)	// 200mA at 1.8V
+#define	HC_CAP_400MA				(1ULL << 21)	// 400mA at 1.8V
+#define	HC_CAP_600MA				(1ULL << 22)	// 600mA at 1.8V
+#define	HC_CAP_800MA				(1ULL << 23)	// 800mA at 1.8V
+#define HC_CAP_CURRENT( _caps )		( ( ( ( _caps ) >> 20 ) ) & 0x0f )
+
+#define	HC_CAP_DRV_TYPE_B			(1ULL << 24)
+#define	HC_CAP_DRV_TYPE_A			(1ULL << 25)
+#define	HC_CAP_DRV_TYPE_C			(1ULL << 26)
+#define	HC_CAP_DRV_TYPE_D			(1ULL << 27)
+#define	HC_CAP_DRV_TYPES( _caps )	( ( ( ( _caps ) >> 24 ) ) & 0x0f )
+
+
+#define HC_CAP_SV( _caps )			( ( ( ( _caps ) >> 28 ) ) & 0x0f )
+#define HC_CAP_SV_1_2V				(1ULL << 28)	// 1.2V signal voltage supported
+#define HC_CAP_SV_1_8V				(1ULL << 29)	// 1.8V signal voltage supported
+#define HC_CAP_SV_3_0V				(1ULL << 30)	// 3.0V signal voltage supported
+#define HC_CAP_SV_3_3V				(1ULL << 31)	// 3.3V signal voltage supported
+
+#define	HC_CAP_CD_INTR				(1ULL << 32)	// card detect interrupt supported
+#define HC_CAP_BSY					(1ULL << 33)	// card detect busy supported
+#define	HC_CAP_HS400ES				(1ULL << 34)	// hs400 enhanced strobe supported
+#define HC_CAP_CD_WP				(1ULL << 35)	// card detect write protect supported
+	_Uint64t		caps;
+	_Uint32t		version;
+	_Uint32t		sg_max;
+	_Uint32t		dtr_max;					// Maximum Data Transfer Rate
+	_Uint32t		dtr;						// Current Data Transfer Rate
+	_Uint32t		timing;						// Current Timing
+	_Uint32t		bus_width;					// Current Bus Width
+	_Uint32t		idle_time;					// PM Idle Time in ms
+	_Uint32t		sleep_time;					// PM Sleep Time in ms
+	_Uint32t		rsvd[12];
+};
+
+struct _sdio_funcs {
+	int			nfuncs;
+
+	void		(*insertion)( struct sdio_connection *, sdio_device_instance_t * );
+	void		(*removal)( struct sdio_connection *, sdio_device_instance_t * );
+#define SDIO_EVENT_RESET	1
+	int			(*event)( struct sdio_connection *, sdio_device_instance_t *, int ev );
+};
+
+struct _sdio_connect_parm {
+	const char			*path;
+#define SDIO_VERSION	0
+	_Uint32t			vsdio;
+	_Uint32t			flags;
+	_Int32t				argc;
+	char				**argv;
+	sdio_device_ident_t	ident;
+	sdio_funcs_t		funcs;
+	_Uint32t			rsvd[12];
+};
+
+extern void				*sdio_alloc( size_t size );
+extern int				sdio_free( void *ptr, size_t size );
+extern int				sdio_verbosity( struct sdio_device *device, uint32_t flags, int verbosity );
+extern int				sdio_idle( struct sdio_device *device );
+#define PM_IDLE		0
+#define PM_ACTIVE	1
+#define PM_SLEEP	2
+#define PM_SUSPEND	3
+extern int				sdio_pwrmgnt( struct sdio_device *device, int action );
+extern int				sdio_reset( struct sdio_device *device );
+extern int				sdio_bus_error( struct sdio_device *device );
+extern int				sdio_hpi( struct sdio_device *device, uint32_t timeout);
+extern int				sdio_send_status( struct sdio_device *device, _Uint32t *rsp, int hpi );
+extern int				sdio_wait_card_status( struct sdio_device *device, uint32_t *rsp, uint32_t mask, uint32_t val, uint32_t msec );
+extern int				sdio_stop_transmission( struct sdio_device *device, int hpi );
+extern int				sdio_set_block_count( struct sdio_device *device, int blkcnt, uint32_t flgs );
+extern int				sdio_set_block_length( struct sdio_device *device, int blklen );
+extern int				sdio_lock_unlock( struct sdio_device *device, int action, uint8_t *pwd, int pwd_len );
+extern int				sdio_set_partition( struct sdio_device *device, _Uint32t partition );
+extern int				sdio_erase( struct sdio_device *device, int partition, int flgs,
+							uint64_t lba, int nlba );
+extern struct sdio_cmd	*sdio_alloc_cmd( void );
+extern void				sdio_free_cmd( struct sdio_cmd *cmd );
+extern int				sdio_cmd_status( struct sdio_cmd *cmd, _Uint32t *status, _Uint32t *rsp );
+extern int				sdio_send_cmd( struct sdio_device *device, struct sdio_cmd *cmd,
+							void (*func)( struct sdio_device *, struct sdio_cmd *, void *),
+							_Uint32t timeout, int retries );
+extern int				sdio_setup_cmd( struct sdio_cmd *cmd, _Uint32t flgs,
+							_Uint32t op, _Uint32t arg );
+extern int				sdio_setup_cmd_ext( struct sdio_cmd *cmd, _Uint32t flgs,
+							_Uint32t op, _Uint32t arg, _Uint32t earg );
+extern int				sdio_setup_cmd_io( struct sdio_cmd *cmd, _Uint32t flgs,
+							uint32_t blks, uint32_t blksz, void *sgl, uint32_t sgc, void *mhdl );
+
+extern void				*sdio_client_hdl( struct sdio_device *device );
+extern void				*sdio_bs_hdl( struct sdio_device *device );
+extern sdio_cid_t		*sdio_get_cid( struct sdio_device *device );
+extern void				*sdio_get_raw_cid( struct sdio_device *device );
+extern sdio_csd_t		*sdio_get_csd( struct sdio_device *device );
+extern void				*sdio_get_raw_csd( struct sdio_device *device );
+extern sdio_ecsd_t		*sdio_get_ecsd( struct sdio_device *device );
+extern void				*sdio_get_raw_ecsd( struct sdio_device *device );
+extern void				*sdio_get_raw_scr( struct sdio_device *device );
+extern int				sdio_sd_switch( struct sdio_device *device, int mode, int grp, uint8_t val, uint8_t *switch_status );
+extern int				sdio_mmc_switch( struct sdio_device *device, uint32_t cmdset, uint32_t mode, uint32_t index, uint32_t value, uint32_t timeout );
+extern int				sdio_send_ext_csd( struct sdio_device *device, uint8_t *csd );
+extern int				sdio_mmc_rpmb_rw( struct sdio_device *device, void *pf, int nf, int flgs );
+extern int				sdio_mmc_gen_man( struct sdio_device *device, uint8_t op, void *buf, int blklen, int blkcnt, uint32_t arg, uint32_t flgs);
+extern int				sdio_hc_info( struct sdio_device *device, sdio_hc_info_t *info );
+extern int				sdio_dev_info( struct sdio_device *device, sdio_dev_info_t *info );
+extern int				sdio_retune( struct sdio_device *device );
+#define SDIO_CACHE_DISABLE	0
+#define SDIO_CACHE_ENABLE	1
+#define SDIO_CACHE_FLUSH	2
+extern int				sdio_cache( struct sdio_device *device, int op, uint32_t timeout );
+extern int				sdio_set_partition( struct sdio_device *device, _Uint32t partition );
+extern struct sdio_device *sdio_device_lookup( struct sdio_connection *connection,
+							sdio_device_instance_t *instance );
+extern int				sdio_timer_settime( int tid, uint32_t sec, uint32_t nsec, int repeat );
+extern int				sdio_connect( sdio_connect_parm_t *parm, struct sdio_connection **connection );
+#define SDIO_ENUM_DISABLE	0
+#define SDIO_ENUM_ENABLE	1
+extern int				sdio_enum( struct sdio_connection *connection, int action );
+extern int				sdio_disconnect( struct sdio_connection *connection );
+extern int				sdio_attach( struct sdio_connection *connection, sdio_device_instance_t *instance, struct sdio_device **hdl, void *client_hdl );
+extern int				sdio_detach( struct sdio_device *device );
+
+#define SDIO_POWERED_OFF		0x00
+#define SDIO_POWERED_ON			0x01
+#define SDIO_POWER_OFF_SHORT	0x02
+#define SDIO_POWER_OFF_LONG		0x03
+extern int				sdio_pwroff_notify( struct sdio_device *device, int op, int timeout );
+
+#endif
+
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/include/sdiodi.h $ $Rev: 982571 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/internal.h

@@ -0,0 +1,595 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2008, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#ifndef _INTERNAL_H_INCLUDED
+#define _INTERNAL_H_INCLUDED
+
+#include <sys/queue.h>
+#include <pthread.h>
+#include <sys/neutrino.h>
+#include <sys/slogcodes.h>
+#include <sys/rpmb.h>
+
+#include <sdiodi.h>
+#include <mmc.h>
+#include <sd.h>
+
+#include <bs.h>
+
+#include <pci/pci.h>
+
+#define _SLOGC_SDIODI					(_SLOGC_SIM_MMC)
+
+//#define SDIO_UC_SUPPORT				// enable once we get a card to test
+//#define SDIO_APP_SPEC_FCN_EXT			// enable after we get a card to test
+
+//#define SDIO_TRACE
+#define SDIO_TRACE_EVENT				1
+
+#define SDIO_VENDOR_ID_WILDCARD			0xffff
+#define SDIO_DEVICE_ID_WILDCARD			0xffff
+
+#define SDIO_PRIORITY					21
+#define SDIO_INVALID_NUM				(-0xBAD1)
+#define SDIO_STACK_SIZE					32768//16384
+#define SDIO_TSTATE_CREATING			0x00
+#define SDIO_TSTATE_INITIALIZED			0x01
+#define SDIO_TSTATE_INIT_FAILURE		0x02
+
+#define SDIO_NELEMS( _x )				( sizeof( (_x) ) / sizeof( (_x)[0] ) )
+
+#define SDIO_PWR_OFF					0
+#define SDIO_PWR_ON						1
+
+#define SDIO_LDO_VCC					0
+#define SDIO_LDO_VCC_IO					1
+
+#define SDIO_CMD_RETRIES				3
+#define SDIO_RESET_RETRIES				3
+#define SDIO_MAX_BUS_ERRS				2
+#define SDIO_DFLT_BLKSZ					512
+#define SDIO_BLKSZ_512					512
+#define SDIO_BLKSZ_4K					4096
+#define SDIO_CLK_INIT					400000
+#define SDIO_TIMEOUT_MS_TO_NS( _to )	( (uint64_t)( _to ) * 1000LL * 1000LL )
+
+#define SDIO_CHK_GEN( _d )		( (_d)->instance.generation != (_d)->hc->generation )
+
+typedef struct _sdio_hc				sdio_hc_t;
+typedef struct _sdio_hc_cfg			sdio_hc_cfg_t;
+typedef struct _sdio_hc_entry		sdio_hc_entry_t;
+typedef struct _sdio_dev			sdio_dev_t;
+typedef struct sdio_cmd				sdio_cmd_t;
+typedef struct _pulse				sdio_event_t;
+typedef struct _sdio_wspc			sdio_wspc_t;
+typedef struct _sdio_ctrl			sdio_ctrl_t;
+typedef struct _sdio_vendor			sdio_vendor_t;
+typedef struct _sdio_product		sdio_product_t;
+typedef struct _sdio_device_errata	sdio_device_errata_t;
+typedef struct _sdio_pci_dev		sdio_pci_dev_t;
+
+#define DTR_MAX_SDR104			208000000
+#define DTR_MAX_SDR50			100000000
+#define DTR_MAX_DDR50			50000000
+#define DTR_MAX_SDR25			50000000
+#define DTR_MAX_SDR12			25000000
+#define DTR_MAX_HS400			200000000
+#define DTR_MAX_HS200			200000000
+#define DTR_MAX_HS52			52000000
+#define DTR_MAX_HS26			26000000
+#define DTR_MIN_LS				100000
+#define DTR_HS_DEC				5000000
+#define DTR_LS_DEC				50000
+
+struct _sdio_product {
+	_Uint32t		did;			// device id
+	_Uint32t		class;
+	_Uint32t		aflags;
+	char			*name;
+						// chipset init (map mem, set caps etc...)
+	int				(*init)( sdio_hc_t *hc );
+};
+
+struct _sdio_vendor {
+	_Uint32t		vid;
+	char			*name;
+	sdio_product_t	*chipsets;
+};
+
+#define DEV_ERRATA_WILDCARD		(~0)
+
+struct _sdio_device_errata {
+	char		*pnm;
+	uint32_t	mid;
+	uint32_t	oid;
+	uint32_t	prv_s;
+	uint32_t	prv_e;
+	uint32_t	erev;
+
+#define DEV_ERRATA_ACMD12			0x01
+#define DEV_ERRATA_DISCARD_SUP		0x02
+	uint32_t	errata;
+	uint32_t	rsettle;
+};
+
+struct sdio_cmd {
+	TAILQ_ENTRY(sdio_cmd)	clink;
+	void					*hdl;
+	_Uint32t				flags;
+	_Uint32t				status;
+	_Uint32t				opcode;
+	_Uint32t				arg;
+	_Uint32t				earg;	// extended arg
+	_Uint32t				rsp[4];
+	_Uint32t				blks;
+	_Uint32t				blksz;
+	_Uint32t				sgc;
+	sdio_sge_t				*sgl;
+	void					*mhdl;
+	void					(*cbf)( struct sdio_device *, sdio_cmd_t *, void *);
+};
+
+struct _sdio_wspc {
+	sdio_cmd_t			*cmd;		// active command
+	sdio_sge_t			*sge;
+	_Uint8t				*sga;
+	int					nsg;
+	int					sgc;
+};
+
+#define SDIO_HC_ENTRY_NFUNCS      ( ( sizeof( sdio_hc_entry_t ) - offsetof( sdio_hc_entry_t, dinit ) ) / sizeof( void *)  )
+
+struct _sdio_hc_entry {
+	_Uint32t	nentries;
+	int			(*dinit)(sdio_hc_t *);
+
+#define PM_IDLE			0
+#define PM_ACTIVE		1
+#define PM_SLEEP		2
+#define PM_SUSPEND		3
+	int			(*pm)(sdio_hc_t *, int action);
+	int			(*cmd)(sdio_hc_t *, sdio_cmd_t *);
+	int			(*abort)(sdio_hc_t *, sdio_cmd_t *);
+
+#define HC_EV_TIMER		0
+#define HC_EV_CD		1
+#define HC_EV_TUNE		2
+#define HC_EV_INTR		3
+#define HC_EV_DMA		4
+#define HC_EV_BS		20	// board specific events start here
+	int			(*event)(sdio_hc_t *, sdio_event_t *);
+#define CD_RMV			0x00		// card removed
+#define CD_INS			0x01		// card inserted
+#define CD_WP			0x80		// card write protected
+	int			(*cd)(sdio_hc_t *);
+
+	int			(*pwr)(sdio_hc_t *, int vdd);
+	int			(*clk)(sdio_hc_t *, int clk);
+
+#define BUS_MODE_OPEN_DRAIN		0
+#define BUS_MODE_PUSH_PULL		1
+	int			(*bus_mode)(sdio_hc_t *, int mode);
+
+#define BUS_WIDTH_1				1
+#define BUS_WIDTH_4				4
+#define BUS_WIDTH_8				8
+	int			(*bus_width)(sdio_hc_t *, int width);
+
+#define TIMING_HS400			9
+#define TIMING_HS200			8
+#define TIMING_SDR104			7
+#define TIMING_SDR50			6
+#define TIMING_SDR25			5
+#define TIMING_SDR12			4
+#define TIMING_DDR50			3
+#define TIMING_HS				2
+#define TIMING_LS				1
+	int			(*timing)(sdio_hc_t *, int timing);
+
+#define SIGNAL_VOLTAGE_3_3		1
+#define SIGNAL_VOLTAGE_3_0		2
+#define SIGNAL_VOLTAGE_1_8		3
+#define SIGNAL_VOLTAGE_1_2		4
+	int			(*signal_voltage)(sdio_hc_t *, int sv);
+
+#define	DRV_TYPE_B				1
+#define	DRV_TYPE_A				2
+#define	DRV_TYPE_C				4
+#define	DRV_TYPE_D				8
+	int			(*drv_type)(sdio_hc_t *, int type);
+	int			(*driver_strength)(sdio_hc_t *, int timing, int type);
+	int			(*tune)(sdio_hc_t *, int op);
+	int			(*preset)(sdio_hc_t *, int);
+};
+
+struct _sdio_dev {
+	sdio_hc_t				*hc;
+
+	_Uint32t				dtype;			// device type
+
+#define DEV_FLAG_PRESENT		0x001		// device present
+#define DEV_FLAG_LOCKED			0x002
+#define DEV_FLAG_INVALID_CARD	0x004
+#define DEV_FLAG_MEDIA_CHANGE	0x008
+#define DEV_FLAG_IDLE			0x010
+#define DEV_FLAG_ACTIVE			0x020
+#define DEV_FLAG_SLEEP			0x040
+#define DEV_FLAG_HS				0x080		// high speed
+#define DEV_FLAG_HS200			0x100		// high speed 200
+#define DEV_FLAG_HS400			0x200		// high speed 400
+#define DEV_FLAG_DDR			0x400		// DDR
+#define DEV_FLAG_UHS			0x800		// UHS
+#define DEV_FLAG_BKOPS			0x1000		// BKOPS
+#define DEV_FLAG_SIG_ERR		0x2000		// signal switch error
+#define DEV_FLAG_WRITE_PROTECT	0x4000		// write protected
+#define DEV_FLAG_WCE			0x8000		// Write Cache Enable
+#define DEV_FLAG_HS400ES		0x10000		// high speed 400 enhanced strobe
+	_Uint32t				flags;
+
+	_Uint32t				rsettle;
+
+	_Uint32t				rsvd;
+
+	_Uint64t				caps;			// see DEV_CAP_xxx
+
+	_Uint32t				ocr;
+
+	int						pwd_len;
+	_Uint8t					pwd[MMC_LU_PWD_SIZE];
+
+	int						pactive;		// active partition
+
+	_Uint32t				rca;
+
+	sdio_cid_t				cid;
+	sdio_csd_t				csd;
+	sdio_ecsd_t				ecsd;
+	sd_scr_t				scr;
+	sd_sds_t				sds;
+	sd_switch_cap_t			swcaps;
+
+	_Uint32t				pwr_mgnt_fcn_rsa;	// power managment function regester set address
+	_Uint32t				perf_enh_fcn_rsa;	// performance enhancement function regester set address
+
+	_Uint32t				block_length;
+
+	_Uint32t				wp_size;
+	_Uint32t				erase_size;
+
+	_Uint32t				rel_wr_sec_c;
+
+	_Uint32t				raw_cid[SDIO_CID_SIZE];
+	_Uint32t				raw_csd[SDIO_CSD_SIZE];
+	_Uint32t				raw_scr[SD_SCR_SIZE / 4 ];
+	_Uint8t					raw_ecsd[MMC_EXT_CSD_SIZE];
+};
+
+struct _sdio_hc_cfg {
+#define SDIO_NAME_MAX		64
+	char				name[SDIO_NAME_MAX];
+
+	_Uint32t			flags;
+	int					verbosity;
+
+	_Uint64t			caps;
+
+	_Uint16t			vid;
+	_Uint16t			did;
+	_Uint32t			class;
+	int					idx;
+
+	int					sg_max;
+
+	int					clk;
+
+	int					bus_width;
+	int					timing;
+
+#define SDIO_MAX_IRQ		4
+	int					irqs;
+	int					irq[SDIO_MAX_IRQ];
+
+#define SDIO_MAX_DMA		4
+	int					dma_chnls;
+	int					dma_chnl[SDIO_MAX_DMA];
+
+#define SDIO_MAX_ADDR		6
+	int					base_addrs;
+	int					base_addr_size[SDIO_MAX_ADDR];
+	_Uint64t			base_addr[SDIO_MAX_ADDR];
+
+	_Uint64t			io_xlat;
+	_Uint64t			mem_xlat;
+	_Uint64t			bmstr_xlat;
+	_Uint64t			bmstr_align;
+
+#ifndef SDIO_PM_IDLE_TIME
+	#define SDIO_PM_IDLE_TIME		100		// 100ms
+#endif
+
+#ifndef SDIO_PM_SLEEP_TIME
+	#define SDIO_PM_SLEEP_TIME		10000	// 10 seconds
+#endif
+
+	_Uint32t			idle_time;		// time in ms
+	_Uint32t			sleep_time;		// time in ms
+
+	char				*options;		// board specific options
+	char				*hsoptions;		// host specific options
+};
+
+#define SDIO_PCI_INTR_MSIX						2
+#define SDIO_PCI_INTR_MSI						1
+#define SDIO_PCI_INTR_PIN						0
+
+struct _sdio_pci_dev {
+	pci_devhdl_t		dev_hdl;
+	pci_bdf_t			bdf;
+	pci_cap_t			pcie;
+	pci_cap_t			msi;
+	pci_cap_t			msix;
+ 	uint32_t			msi_nirq;
+	uint32_t			msix_nirq;
+#define SDIO_PFLG_MSI		0x01
+#define SDIO_PFLG_MSIX		0x02
+	uint32_t			pflags;
+};
+
+struct _sdio_hc {							// Host Controller
+	TAILQ_ENTRY(_sdio_hc)	hlink;
+	sdio_hc_cfg_t		cfg;
+	sdio_hc_entry_t		entry;
+	sdio_dev_t			device;
+	pthread_mutex_t		mutex;
+	pthread_cond_t		cond;
+	pthread_mutex_t		cd_mutex;
+	_Uint32t			path;
+	_Uint32t			state;
+
+	_Uint32t			usage;
+	int					priority;
+
+	_Uint32t			generation;
+
+
+#define HC_FLAG_INITIALIZED			( 1 << 1 )
+#define	HC_FLAG_RST					( 1 << 2 )
+#define	HC_FLAG_TUNE				( 1 << 3 )
+#define	HC_FLAG_DEV_SD				( 1 << 4 )
+#define	HC_FLAG_DEV_MMC				( 1 << 5 )
+#define	HC_FLAG_DEV_SDIO			( 1 << 6 )
+#define	HC_FLAG_DEV_TYPE			( HC_FLAG_DEV_SD | HC_FLAG_DEV_MMC | HC_FLAG_DEV_SDIO )
+#define	HC_FLAG_SKIP_PWRUP			( 1 << 7 )
+	_Uint32t			flags;
+
+	_Uint64t			caps;				// Capabilities, see HC_CAP_xxx
+
+	_Uint32t			version;
+
+	_Uint32t			pm_state;
+
+	_Uint64t			pm_sleep_cnt;
+
+		// hc thread
+	int					hc_chid;
+	int					hc_coid;
+	int					hc_tid;				// thread id
+	int					hc_iid;				// interrupt id
+
+	int					tuning_count;
+	int					tuning_timerid;
+
+	int					slot;
+
+	sdio_pci_dev_t		pci;
+
+	sdio_wspc_t			wspc;				// data xfer workspc
+
+	_Uint32t			clk_min;
+	_Uint32t			clk_max;
+	_Uint32t			clk_init;
+
+	_Uint32t			ocr;
+	_Uint32t			clk;
+	_Uint32t			vdd;
+	_Uint32t			timing;				// see TIMING_xxx
+	_Uint32t			drv_type;			// see DRV_TYPE_xxx
+	_Uint32t			bus_mode;			// see BUS_MODE_xxx
+	_Uint32t			bus_width;			// see BUS_WIDTH_xxx
+	_Uint32t			signal_voltage;		// see SIGNAL_VOLTAGE_xxx
+
+	_Uint32t			bus_errs;			// bus errors
+
+	void				*cs_hdl;			// Chipset specfic handle
+	void				*bs_hdl;			// Board specfic handle
+};
+
+#define SDIO_EV_TIMER		0
+#define SDIO_EV_CD			1
+
+#define SDIO_CD_INTERVAL	1
+
+struct _sdio_ctrl {
+#define SDIO_CFLAG_SCAN			0x1
+	_Uint32t					flags;
+	_Uint32t					state;
+	int							priority;
+	int							verbosity;
+
+#define SDIO_HC_MAX			8
+	int							nhc;
+	TAILQ_HEAD(,_sdio_hc)		hlist;
+	TAILQ_HEAD(,sdio_device)	dlist;
+
+	TAILQ_HEAD(,sdio_cmd)		clist;
+
+	sdio_connect_parm_t			connect_parm;
+
+	pthread_mutex_t				mutex;
+
+		// change detect thread
+	int							cd_chid;
+	int							cd_coid;
+	int							cd_tid;
+	int							cd_timerid;
+	pthread_cond_t				cd_cond;
+	int							cd_enum;
+};
+
+struct sdio_device {
+	TAILQ_ENTRY(sdio_device)	dlink;
+	sdio_device_instance_t		instance;
+#define DEV_FLAG_RMV_PENDING	0x01
+	_Uint32t					flags;
+	_Uint32t					usage;
+	void						*user;
+	sdio_hc_t					*hc;
+	sdio_dev_t					*dev;
+};
+
+
+// base.c
+extern sdio_ctrl_t			sdio_ctrl;
+extern const uint8_t		sdio_tbp_4bit[];
+extern const uint8_t		sdio_tbp_8bit[];
+extern sdio_vendor_t		sdio_vendors[];
+
+extern int fls( int val );
+extern int sdio_options( sdio_hc_t *hc, char *options );
+extern ssize_t __attribute__((__format__(__printf__, 5, 6)))sdio_slogf( int opcode, int severity, int verbosity, int vlevel, const char *fmt, ... );
+
+extern int sdio_timer_settime( int tid, uint32_t sec, uint32_t nsec, int repeat );
+extern int sdio_set_thread_state( uint32_t *tstate, int state );
+extern int sdio_create_thread( pthread_t *tid, pthread_attr_t *aattr, void *(*func)(void *), void *arg, int priority, uint32_t *tstate, char *name );
+extern int sdio_sg_start( sdio_hc_t *hc, sdio_sge_t *sge, int nsg );
+extern int sdio_sg_nxt( sdio_hc_t *hc, _Uint8t **addr, int *len, int blksz );
+extern int sdio_vtop_sg( sdio_sge_t *vsg, sdio_sge_t *psg, int sgc, void *mhdl );
+extern paddr64_t sdio_vtop( void *vaddr );
+extern uint32_t sdio_extract_bits( uint32_t *data, int bits, int start, int size );
+extern sdio_hc_t *sdio_hc_alloc( void );
+extern int sdio_hc_free( sdio_hc_t *hc );
+extern int sdio_hc_getsubopt( char **optionp, char * const *tokens, char **valuep );
+extern sdio_product_t *sdio_hc_lookup( uint16_t vid, uint16_t did, uint32_t class, char *name );
+extern int sdio_reconcile_errata( sdio_dev_t *dev, sdio_device_errata_t *errata );
+extern sdio_device_errata_t *sdio_device_errata( sdio_dev_t *dev, sdio_device_errata_t *erratas );
+
+extern int sdio_go_idle( sdio_hc_t *hc );
+extern int sdio_select_card( sdio_dev_t *dev, uint32_t rca );
+extern int sdio_send_csd( sdio_dev_t *dev, uint32_t *csd );
+extern int sdio_all_send_cid( sdio_hc_t *hc, uint32_t *cid );
+
+extern int sdio_clock( sdio_hc_t *hc, int clk );
+extern int sdio_tune( sdio_hc_t *hc, int cmd );
+extern int sdio_preset( sdio_hc_t *hc, int state );
+extern int sdio_timing( sdio_hc_t *hc, int timing );
+extern int sdio_bus_mode( sdio_hc_t *hc, int bus_mode );
+extern int sdio_bus_width( sdio_hc_t *hc, int bus_width );
+extern int sdio_drv_type( sdio_hc_t *hc, int drv_type );
+extern int sdio_select_voltage( sdio_hc_t *hc, uint32_t ocr );
+extern int sdio_signal_voltage( sdio_hc_t *hc, int voltage );
+extern int sdio_wait_cmd( sdio_hc_t *hc, struct sdio_cmd *cmd, uint64_t tms );
+extern int sdio_issue_cmd( sdio_dev_t *dev, struct sdio_cmd *cmd, uint64_t tms );
+
+extern int _sdio_disconnect( void );
+extern int _sdio_reset( sdio_dev_t *dev );
+extern int _sdio_bus_error( sdio_dev_t *dev );
+extern int _sdio_pwrmgnt( sdio_dev_t *dev, int pm );
+extern int _sdio_retune( sdio_hc_t *hc );
+extern int _sdio_set_block_count( sdio_dev_t *dev, int blkcnt, uint32_t flgs );
+extern int _sdio_set_block_length( sdio_dev_t *dev, int blklen );
+extern int _sdio_stop_transmission( sdio_dev_t *dev, int hpi );
+extern int _sdio_send_status( sdio_dev_t *dev, uint32_t *rsp, int hpi );
+extern int _sdio_send_cmd( sdio_dev_t *dev, struct sdio_cmd *cmd,
+		void (*func)( struct sdio_device *, sdio_cmd_t *, void *),
+		uint32_t timeout, int retries );
+extern int _sdio_connect( sdio_connect_parm_t *parm, struct sdio_connection **connection );
+extern int _sdio_lock_unlock( sdio_dev_t *dev, int op, uint8_t *pwd, int pwd_len );
+extern int _sdio_wait_card_status( sdio_dev_t *dev, uint32_t *rsp, uint32_t mask, uint32_t val, uint32_t msec );
+extern int _sdio_cache( sdio_dev_t *dev, int op, uint32_t timeout );
+
+	// HC callbacks for change detect and cmd completion
+extern int sdio_hc_event( sdio_hc_t *hc, int ev );
+extern int sdio_cmd_cmplt( sdio_hc_t *hc, struct sdio_cmd *cmd, int status );
+// base.c end
+
+// mmc.c
+extern int mmc_ident( sdio_hc_t *hc );
+extern int mmc_init_device( sdio_hc_t *hc, uint32_t ocr, int flgs );
+extern int mmc_bus_error( sdio_dev_t *dev );
+extern int mmc_bkops_cfg( sdio_dev_t *dev );
+extern int mmc_sleep_awake( sdio_dev_t *dev, int flgs );
+extern int mmc_send_ext_csd( sdio_dev_t *dev, uint8_t *csd );
+extern int mmc_set_partition( sdio_dev_t *dev, uint32_t partition );
+extern int mmc_cache( sdio_dev_t *dev, int op, uint32_t timeout );
+extern uint64_t mmc_erase_timeout( sdio_dev_t *dev, uint32_t etype, uint64_t nlba );
+extern int mmc_erase( sdio_dev_t *dev, int partition, int flgs, uint64_t lba, int nlba );
+extern int mmc_write_protect( sdio_dev_t *dev, int op, int ptype, int mode, uint32_t lba, uint32_t nlba );
+extern int mmc_switch( sdio_dev_t *dev, uint32_t cmdset, uint32_t mode, uint32_t index, uint32_t value, uint32_t timeout );
+extern int mmc_rpmb_rw( sdio_dev_t *dev, void *pf, int nf, int flgs );
+extern int mmc_gen_man_cmd( sdio_dev_t *dev, uint8_t op, void *buf, int blklen, int blkcnt, uint32_t arg, uint32_t flgs);
+extern int mmc_retune( sdio_hc_t *hc );
+extern int mmc_pwroff_notify( sdio_dev_t *dev, int op, int timeout );
+// mmc.c end
+
+// sd.c
+extern int sd_ident( sdio_hc_t *hc );
+extern int sd_init_device( sdio_hc_t *hc, uint32_t ocr, int flgs );
+extern int sd_bus_error( sdio_dev_t *dev );
+extern int sd_app_cmd( sdio_dev_t *dev );
+extern int sd_send_if_cond( sdio_hc_t *hc, uint32_t vhs );
+extern uint64_t sd_erase_timeout( sdio_dev_t *dev, uint32_t etype, uint32_t nlba );
+extern int sd_erase( sdio_dev_t *dev, int flgs, uint64_t lba, int nlba );
+extern int sd_switch( sdio_dev_t *dev, int mode, int grp, uint8_t val, uint8_t *switch_status );
+extern int sd_lock_unlock( sdio_dev_t *dev, int action, uint8_t *pwd, int pwd_len );
+extern int sd_cache( sdio_dev_t *dev, int op, uint32_t timeout );
+extern int sd_pwroff_notify( sdio_dev_t *dev, int op, int timeout );
+// sd.c end
+
+// bs.c
+extern int bs_powman( sdio_hc_t *hc, int state );
+extern int bs_pad_conf( sdio_hc_t *hc, int state );
+extern int bs_clock_gate( sdio_hc_t *hc, int op );
+extern int bs_event( sdio_hc_t *hc, sdio_event_t *ev );
+extern int bs_set_ldo( sdio_hc_t *hc, int ldo, int voltage );
+// bs.c end
+
+// soc.c
+extern int sdio_soc_scan( void );
+extern int sdio_soc_device( sdio_hc_t *hc );
+// soc.c end
+
+// pci.c
+extern int sdio_pci_init( void );
+extern int sdio_pci_dinit( void );
+extern int sdio_pci_scan( void );
+extern int sdio_pci_device( sdio_hc_t *hc );
+extern int sdio_pci_detach_device( sdio_hc_t *hc );
+// pci.c end
+
+// libc
+extern uint64_t _syspage_time( clockid_t clock_id );
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/internal.h $ $Rev: 982571 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/pci.c

@@ -0,0 +1,442 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2008, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+// Module Description:   PCI interface
+
+#include <errno.h>
+#include <string.h>
+
+#include <internal.h>
+
+#ifdef SDIO_PCI_SUPPORT
+
+#include <pci/pci.h>
+#include <pci/pci_id.h>
+#include <pci/pci_ccode.h>
+#include <pci/cap_pcie.h>
+#include <pci/cap_msi.h>
+#include <pci/cap_msix.h>
+
+int sdio_pci_init( void )
+{
+	return( EOK );
+}
+
+int sdio_pci_dinit( void )
+{
+	return( EOK );
+}
+
+int sdio_pci_detach_device( sdio_hc_t *hc )
+{
+	if( hc->pci.dev_hdl != NULL ) {
+		pci_err_t pci_err = pci_device_detach( hc->pci.dev_hdl );
+		if( pci_err != PCI_ERR_OK ) {
+			sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2,
+				   "%s: Failure to detach device: %s", __FUNCTION__, pci_strerror( pci_err ) );
+			return( pci_err );
+		}
+	}
+	return( EOK );
+}
+
+static int sdio_pci_enable( sdio_hc_t *hc, int cap, int max_driver_supported_interrupts )
+{
+	sdio_hc_cfg_t	*cfg;
+	sdio_pci_dev_t	*pci;
+	int				idx;
+	int				max_device_supported_interrupts;
+	pci_irq_t		irq[1];
+	int_t			nirq = NELEMENTS( irq );
+	pci_cmd_t		cmd;
+	pci_err_t		pci_err;
+
+	cfg		= &hc->cfg;
+    pci		= &hc->pci;
+	pci_err = PCI_ERR_OK;
+
+	if( cap == SDIO_PCI_INTR_MSIX ) {
+		max_device_supported_interrupts = pci->msix_nirq;
+
+			// set the disposition of all other device interrupt sources to unused
+		for( idx = max_driver_supported_interrupts; idx < max_device_supported_interrupts; idx++ ) {
+			pci_err = cap_msix_set_irq_entry( pci->dev_hdl, pci->msix, (uint_t)idx, -1 );
+			if( pci_err != PCI_ERR_OK ) {
+				sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2, "%s: Disable of MSI-X interrupt entry %u failed: %s", __FUNCTION__, idx, pci_strerror( pci_err ) );
+			}
+		}
+			// now enable the capability
+		pci_err = pci_device_cfg_cap_enable( pci->dev_hdl, pci_reqType_e_MANDATORY, pci->msix );
+		if( pci_err != PCI_ERR_OK ) {
+			free( pci->msix );
+			pci->msix = NULL;
+			sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2, "%s: Unable to enable MSI-X capabilities, %s", __FUNCTION__, pci_strerror( pci_err ) );
+			return( ENXIO );
+		}
+		else {
+			sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 2, "%s: MSI-X capabilities enabled", __FUNCTION__ );
+				// unmask the interrupts we are interested in
+			for( idx = 0; idx < max_driver_supported_interrupts; idx++ ) {
+				pci_err = cap_msix_unmask_irq_entry( pci->dev_hdl, pci->msix, (uint_t)idx );
+				if( pci_err != PCI_ERR_OK ) {
+					sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2, "%s: Unmask of MSI-X interrupt entry %d failed: %s", __FUNCTION__, idx, pci_strerror( pci_err ) );
+				}
+				else {
+//					sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 5, "%s: MSI-X interrupt entry %d unmasked", __FUNCTION__ , idx );
+				}
+			}
+			pci->pflags |=  SDIO_PFLG_MSIX;
+		}
+	}
+	else if( cap == SDIO_PCI_INTR_MSI ) {
+		max_device_supported_interrupts = pci->msi_nirq;
+
+			// before enabling the MSI capability, configure the desired number of interrupts
+		if( max_device_supported_interrupts > max_driver_supported_interrupts ) {
+			pci_err = cap_msi_set_nirq( pci->dev_hdl, pci->msi, (uint_t)max_driver_supported_interrupts );
+			if( pci_err != PCI_ERR_OK ) {
+				free( pci->msi );
+				pci->msi = NULL;
+				sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2, "%s: cap_msi_set_nirq failed, %s", __FUNCTION__, pci_strerror( pci_err ) );
+			}
+		}
+
+		if( pci_err == PCI_ERR_OK ) {
+			pci_err = pci_device_cfg_cap_enable( pci->dev_hdl, pci_reqType_e_MANDATORY, pci->msi );
+			if( pci_err != PCI_ERR_OK ) {
+				free( pci->msi );
+				pci->msi = NULL;
+				sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 5, "%s: Unable to enable MSI capabilities, %s", __FUNCTION__, pci_strerror( pci_err ) );
+			}
+			else {
+				sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 5, "%s: MSI capabilities enabled", __FUNCTION__ );
+				for( idx = 0; idx < max_driver_supported_interrupts; idx++ ) {
+					pci_err = cap_msi_unmask_irq_entry( pci->dev_hdl, pci->msi, (uint_t)idx );
+					if( pci_err == PCI_ERR_OK ) {
+						sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 5, "%s: PVM supported. MSI interrupt entry %u unmasked", __FUNCTION__, idx );
+					}
+					else if( pci_err != PCI_ERR_ENOTSUP ) {
+						sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 5, "%s: Attempt to unmask MSI interrupt entry %u failed, %s", __FUNCTION__, idx, pci_strerror( pci_err ) );
+					}
+					else {
+						// nothing
+					}
+				}
+			}
+			pci->pflags |=  SDIO_PFLG_MSI;
+		}
+	}
+	else if( cap == SDIO_PCI_INTR_PIN ) {
+
+	}
+	else {
+		// nothing
+	}
+
+	if( cfg->irqs == 0 ) {
+		pci_err = pci_device_read_irq( pci->dev_hdl, &nirq, irq );
+		if( pci_err != PCI_ERR_OK ) {
+			sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2, "%s: pci_device_read_irq failed: %s", __FUNCTION__, pci_strerror( pci_err ) );
+			return( ENXIO );
+		}
+
+		for( idx = 0; idx < nirq; idx++ ) {
+			cfg->irq[idx] = irq[idx];
+		}
+		cfg->irqs = nirq;
+	}
+	else {
+	}
+
+		// need to ensure bus master is enabled
+	sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 1, "%s: B%u:D%u:F%u, Check bus mastering is enabled", __FUNCTION__,
+			PCI_BUS( hc->pci.bdf ), PCI_DEV( hc->pci.bdf ), PCI_FUNC( hc->pci.bdf ) );
+
+	pci_err = pci_device_read_cmd( hc->pci.bdf, &cmd );
+	if( pci_err != PCI_ERR_OK ) {
+		sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2,
+				"%s: pci_device_read_cmd() failed: %s", __FUNCTION__, pci_strerror( pci_err ) );
+		return( ENXIO );
+	}
+	else if( ( cmd & ( 1u << 2 ) ) == 0 ) {
+		pci_err = pci_device_write_cmd( hc->pci.dev_hdl, cmd | ( 1u << 2 ), &cmd );
+		if( pci_err != PCI_ERR_OK ) {
+			sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2,
+					"%s: pci_device_write_cmd() failed: %s", __FUNCTION__, pci_strerror( pci_err ) );
+			return( ENXIO );
+		}
+		else if( ( cmd & ( 1u << 2 ) ) == 0 ) {
+			sdio_slogf( _SLOGC_SDIODI, _SLOG_WARNING, hc->cfg.verbosity, 2,
+					"%s: pci_device_write_cmd() ok but cmd reg is 0x%x", __FUNCTION__, cmd );
+		}
+		else {
+			sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 1, "%s: bus mastering is now enabled", __FUNCTION__ );
+		}
+	}
+	else {
+		sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 1, "%s: bus mastering already enabled", __FUNCTION__ );
+	}
+
+	return( EOK );
+}
+
+static int sdio_pci_capabilities( sdio_hc_t *hc )
+{
+	sdio_pci_dev_t	*pci;
+	int				idx;
+	pci_err_t		pci_err;
+
+	pci = &hc->pci;
+
+	idx = pci_device_find_capid( pci->bdf, CAPID_PCIe );
+	if( idx >= 0 ) {
+		pci_err = pci_device_read_cap( pci->bdf, &pci->pcie, (uint_t)idx );
+		if( pci_err != PCI_ERR_OK ) {
+			pci->pcie = NULL;
+			sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 5, "%s:  Unable to read PCIe capabilities, %s", __FUNCTION__, pci_strerror( pci_err ) );
+		}
+		else {
+			pci_err = pci_device_cfg_cap_enable( pci->dev_hdl, pci_reqType_e_MANDATORY, pci->pcie );
+			if( ( pci_err != PCI_ERR_OK ) && ( pci_err != PCI_ERR_EALREADY ) ) {
+				sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 5, "%s: Unable to enable PCIe capabilities, %s", __FUNCTION__, pci_strerror( pci_err ) );
+			}
+		}
+	}
+	else {
+		sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 5, "%s:  Unable to find PCIe capability", __FUNCTION__ );
+	}
+
+		// MSI-X capability
+	idx = pci_device_find_capid( pci->bdf, CAPID_MSIX );
+	if( idx >= 0 ) {
+		pci_err = pci_device_read_cap( pci->bdf, &pci->msix, (uint_t)idx );
+		if( pci_err != PCI_ERR_OK ) {
+			pci->msix = NULL;
+			sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2, "%s: Unable to read MSI-X capabilities, %s", __FUNCTION__, pci_strerror( pci_err ) );
+		}
+		else {
+			pci->msix_nirq = cap_msix_get_nirq( pci->msix );
+		}
+	}
+	else {
+		sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 5, "%s:  Unable to find MSI-X capability", __FUNCTION__ );
+	}
+
+		// MSI capability
+	idx = pci_device_find_capid( pci->bdf, CAPID_MSI );
+	if( idx >= 0 ) {
+		pci_err = pci_device_read_cap( pci->bdf, &pci->msi, (uint_t)idx );
+		if( pci_err != PCI_ERR_OK ) {
+			pci->msi = NULL;
+			sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2, "%s: Unable to read MSI capabilities, %s", __FUNCTION__, pci_strerror( pci_err ) );
+		}
+		else {
+			pci->msi_nirq = cap_msi_get_nirq( pci->msi );
+		}
+	}
+	else {
+		sdio_slogf( _SLOGC_SDIODI, _SLOG_INFO, hc->cfg.verbosity, 5, "%s: Unable to find MSI capability", __FUNCTION__ );
+	}
+
+	return( EOK );
+}
+
+static int sdio_pci_config( sdio_hc_t *hc, sdio_product_t *prod )
+{
+	sdio_hc_cfg_t	*cfg;
+	sdio_pci_dev_t	*pci;
+	pci_ba_t		ba[NELEMENTS(cfg->base_addr)];
+	int_t			nba = NELEMENTS(ba);
+	int_t			nirq = NELEMENTS(cfg->irq);
+	pci_err_t		pci_err;
+	int				idx;
+	int				cap;
+	int				status;
+
+	cfg = &hc->cfg;
+	pci = &hc->pci;
+
+	sdio_pci_capabilities( hc );
+
+	if( pci->msix_nirq ) {						// msix
+		nirq = ( cfg->irqs == 1 ) ? 1 : pci->msix_nirq;
+		cap = SDIO_PCI_INTR_MSIX;
+	}
+	else if( pci->msi_nirq ) {					// msi
+		nirq = ( cfg->irqs == 1 ) ? 1 : pci->msi_nirq;
+		cap = SDIO_PCI_INTR_MSI;
+	}
+	else {										// int pin
+		nirq = 1;
+		cap = SDIO_PCI_INTR_PIN;
+	}
+
+	nirq = 1;									// remove if we find a device that supports more than 1 irq
+
+	status = sdio_pci_enable( hc, cap, nirq );
+	if( status != EOK ) {
+		sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2, "%s: sdio_pci_enable() failed: %s",
+				__FUNCTION__, strerror( status ) );
+
+		return( status );
+	}
+
+	pci_err = pci_device_read_ba( hc->pci.dev_hdl, &nba, ba, pci_reqType_e_UNSPECIFIED );
+	if( pci_err != PCI_ERR_OK ) {
+		sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 2, "%s: pci_device_read_ba() failed: %s",
+				__FUNCTION__, pci_strerror( pci_err ) );
+		return( ENXIO );
+	}
+
+	for( idx = 0; idx < nba; idx++ ) {			// assign base addresses
+		switch( ba[idx].type ) {
+			case pci_asType_e_NONE:
+				break;
+
+			case pci_asType_e_MEM:
+				if( ( ba[idx].attr & pci_asAttr_e_EXPANSION_ROM ) != 0 ) {
+					sdio_slogf( _SLOGC_SDIODI, _SLOG_WARNING, hc->cfg.verbosity, 4,
+							"%s: Unxpected ROM detected on BA %d.", __FUNCTION__, idx );
+					break;
+				}
+				else {
+					cfg->base_addr[cfg->base_addrs] = ba[idx].addr;
+					cfg->base_addr_size[cfg->base_addrs] = ba[idx].size;
+					cfg->base_addrs++;
+				}
+				break;
+
+			case pci_asType_e_IO:
+				cfg->base_addr[cfg->base_addrs] = ba[idx].addr;
+				cfg->base_addr_size[cfg->base_addrs] = ba[idx].size;
+				cfg->base_addrs++;
+				break;
+
+			default:
+				sdio_slogf( _SLOGC_SDIODI, _SLOG_WARNING, hc->cfg.verbosity, 3,
+						"%s: Unknown BA type %d.", __FUNCTION__, idx );
+				break;
+		}
+	}
+
+	return( EOK );
+}
+
+int sdio_pci_device( sdio_hc_t *hc )
+{
+	sdio_hc_cfg_t		*cfg;
+	sdio_product_t		*prod;
+
+	cfg		= &hc->cfg;
+
+	prod = sdio_hc_lookup( cfg->vid, cfg->did, cfg->class, "" );
+	if( prod == NULL ) {
+		return( ENODEV );
+	}
+
+	hc->pci.bdf = pci_device_find( 0, cfg->vid, cfg->did, PCI_CCODE_ANY );
+
+	if( hc->pci.bdf == PCI_BDF_NONE ) {
+		hc->pci.dev_hdl = NULL;
+	}
+	else {
+		hc->pci.dev_hdl = pci_device_attach( hc->pci.bdf, pci_attachFlags_DEFAULT, NULL );
+	}
+
+	if( hc->pci.dev_hdl == NULL ) {
+		hc->pci.bdf = PCI_BDF_NONE;
+		return ENODEV;
+	}
+	else {
+		sdio_pci_config( hc, prod );
+		return( EOK );
+	}
+}
+
+#define PCI_CCODE_PERIPHERAL_SDHC_DMA		(PCI_CCODE( PCI_CCODE_PERIPHERAL, 0x05, 0x01 ))
+
+int sdio_pci_scan( void )
+{
+	sdio_hc_t					*hc;
+	sdio_hc_cfg_t				*cfg;
+	sdio_product_t				*prod;
+	int							i;
+	int							idx;
+	int							status;
+	pci_vid_t					vid;
+	pci_did_t					did;
+	pci_ccode_t					ccode;
+	pci_bdf_t					bdf;
+	pci_err_t					r;
+	static const pci_ccode_t	sdhc_ccode[] = { PCI_CCODE_PERIPHERAL_SD_HOST_CTRL, PCI_CCODE_PERIPHERAL_SDHC_DMA };
+
+	hc	= TAILQ_FIRST( &sdio_ctrl.hlist );
+	idx	= 0;
+
+	for( i = 0; i < sizeof( sdhc_ccode ) / sizeof( pci_ccode_t ); i++ ) {
+		while( ( bdf = pci_device_find( idx, PCI_VID_ANY, PCI_DID_ANY, sdhc_ccode[i] ) ) != PCI_BDF_NONE ) {
+			r = pci_device_read_vid( bdf, &vid );
+			if( r != PCI_ERR_OK ) {
+				continue;
+			}
+
+			r = pci_device_read_did( bdf, &did );
+			if( r != PCI_ERR_OK ) {
+				continue;
+			}
+
+			r = pci_device_read_ccode( bdf, &ccode );
+			if( r != PCI_ERR_OK ) {
+				continue;
+			}
+
+			prod = sdio_hc_lookup( vid, did, ccode, "" );
+			if( prod != NULL ) {
+				if( hc == NULL ) {
+					hc = sdio_hc_alloc( );
+					if( hc == NULL ) {
+						return( ENOMEM );
+					}
+				}
+				cfg				= &hc->cfg;
+				cfg->vid		= vid;
+				cfg->did		= did;
+				cfg->class		= ccode;
+
+				status = sdio_pci_device( hc );
+				if( status != EOK ) {
+					return( status );
+				}
+				hc = NULL;
+			}
+			++idx;
+		}
+	}
+
+	return( EOK );
+}
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/pci.c $ $Rev: 982571 $")
+#endif

src/hardware/devb/sdmmc/sdiodi/soc.c

@@ -0,0 +1,156 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2008, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#include <errno.h>
+#include <malloc.h>
+#include <string.h>
+
+#include <hw/sysinfo.h>
+#include <drvr/hwinfo.h>
+
+#include <internal.h>
+
+// Module:  scan hwi for devices
+
+#ifdef SDIO_SOC_SUPPORT
+
+static unsigned sdio_soc_hwi( int idx )
+{
+	return( hwi_find_bus( HWI_ITEM_BUS_SDIO, idx ) );
+}
+
+static int sdio_soc_config( sdio_hc_t *hc, int idx, unsigned offset )
+{
+	sdio_hc_cfg_t	*cfg;
+	hwi_tag			*tag;
+	char			*name;
+	char			*opts;
+
+	cfg			= &hc->cfg;
+	opts		= NULL;
+	cfg->idx	= idx;
+
+	while( ( offset = hwi_next_tag( offset, 1 ) ) != HWI_NULL_OFF ) {
+		tag		= hwi_off2tag( offset );
+		name	= __hwi_find_string( ((hwi_tag *)tag)->prefix.name );
+
+		if( !strcmp( name, HWI_TAG_NAME_busattr ) ) {
+			cfg->bus_width = tag->busattr.width;
+		}
+		else if( !strcmp( name, HWI_TAG_NAME_location ) ) {
+			cfg->base_addr[cfg->base_addrs]			= tag->location.base;
+			cfg->base_addr_size[cfg->base_addrs]	= tag->location.len;
+			cfg->base_addrs++;
+		}
+		else if( !strcmp( name, HWI_TAG_NAME_irq ) ) {
+			cfg->irq[cfg->irqs++] = tag->irq.vector;
+		}
+		else if( !strcmp( name, HWI_TAG_NAME_inputclk ) ) {
+			cfg->clk = tag->inputclk.clk;
+		}
+		else if( !strcmp( name, HWI_TAG_NAME_dll ) ) {
+			strlcpy( cfg->name, __hwi_find_string( tag->dll.name ), sizeof( cfg->name ) );
+		}
+		else if( !strcmp( name, HWI_TAG_NAME_optstr ) ) {
+			if( opts ) {
+				free( opts );
+			}
+			opts = strdup( __hwi_find_string( tag->optstr.string ) );
+		}
+		else if( !strcmp( name, HWI_TAG_NAME_dma ) ) {
+			cfg->dma_chnl[cfg->dma_chnls++] = tag->dma.chnl;
+		}
+		else {
+			// nothing
+		}
+	}
+
+	if( opts ) {
+		sdio_options( hc, opts );
+		free( opts );
+	}			
+
+	if( cfg->name[0] == '\0' ) {
+		sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, 1, 1, "%s:  skipping SOC %d, base 0x%"PRIx64"", __FUNCTION__, idx, cfg->base_addr[0] );
+		return( ENODEV );
+	}
+
+	return( EOK );
+}
+
+int sdio_soc_scan( void )
+{
+	sdio_hc_t	*hc;
+	unsigned	item;
+	int			occurence;
+
+	item		= HWI_NULL_OFF; 
+	occurence	= 0;
+	hc			= TAILQ_FIRST( &sdio_ctrl.hlist );
+	while( ( item = sdio_soc_hwi( occurence ) ) != HWI_NULL_OFF ) {
+		if( hc == NULL && ( hc = sdio_hc_alloc( ) ) == NULL ) {
+			return( ENOMEM );
+		}
+		if( sdio_soc_config( hc, occurence, item ) != EOK ) {
+			sdio_hc_free( hc );
+		}
+		hc = NULL;
+		occurence++;
+	}
+
+		// if we don't find any SOCs in HWI, allocate a
+		// dumby entry so we will try the default product
+	if( TAILQ_FIRST( &sdio_ctrl.hlist ) == NULL ) {
+		if( sdio_hc_alloc( ) == NULL ) {
+			return( ENOMEM );
+		}
+	}
+
+	return( EOK );
+}
+
+int sdio_soc_device( sdio_hc_t *hc )
+{
+	sdio_hc_cfg_t	*cfg;
+	unsigned		item;
+	int				status;
+
+	cfg		= &hc->cfg;
+	status	= EOK;
+
+	if( cfg->name[0] == '\0' && cfg->base_addrs ) {
+		return( ENODEV );
+	}
+
+	if( cfg->idx != -1 && ( item = sdio_soc_hwi( cfg->idx ) ) != HWI_NULL_OFF ) {
+		status = sdio_soc_config( hc, cfg->idx, item );
+	}
+
+	return( status );
+}
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/soc.c $ $Rev: 982571 $")
+#endif
+

src/hardware/devb/sdmmc/sim_assd.c

@@ -0,0 +1,671 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2014, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+#include <sim_sdmmc.h>
+
+#define ASSD_TIME_DEFAULT			5000
+
+#define ASSD_APDU_STL_SIZE			2
+#define ASSD_APDU_MIN_DLEN			4	
+#define ASSD_APDU_MAX_DLEN			512
+
+#define ASSD_STATUS_SIZE			32
+#define ASSD_STATE_IDX				0
+#define ASSD_ERROR_IDX				1
+#define ASSD_SEC_SYS_ERROR_IDX		2
+	#define ASSD_SEC_SYS_ERR		0x80
+
+#define ASSD_SPEC_A1_V1				0
+#define ASSD_SPEC_A1_V1_1			1
+#define ASSD_SPEC_A1_V2				2
+#define ASSD_SPEC_A1_V3				3
+
+#define ASSD_SS_MCEX				0
+
+static int assd_control_system( SIM_HBA *hba, int srcid, int ssi, int op )
+{
+	SIM_SDMMC_EXT		*ext;
+	struct sdio_device	*dev;
+	struct sdio_cmd		*cmd;
+	int					status;
+
+	ext		= (SIM_SDMMC_EXT *)hba->ext;
+	dev		= ext->device;
+
+	status =  sdio_set_block_length( dev, SD_SEC_CMD_SIZE );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	cmd = sdio_alloc_cmd( );
+	if( cmd == NULL ) {
+		return( ENOMEM );
+	}
+
+	sdio_setup_cmd( cmd, SCF_CTYPE_ADTC | SCF_RSP_R1B, SD_CONTROL_ASSD_SYSTEM, ( srcid << 12 ) | ( ssi << 8 ) | op );
+	status = sdio_send_cmd( dev, cmd, NULL, ASSD_TIME_DEFAULT, 0 );
+
+	sdio_free_cmd( cmd );
+
+	return( status );
+}
+
+static int assd_write_sec_cmd( SIM_HBA *hba, int len, uint8_t *data, int timeout )
+{
+	SIM_SDMMC_EXT		*ext;
+	struct sdio_device	*dev;
+	struct sdio_cmd		*cmd;
+	int					status;
+	sdio_sge_t			sge;
+
+	ext		= (SIM_SDMMC_EXT *)hba->ext;
+	dev		= ext->device;
+
+#ifdef SDMMC_ASSD_DEBUG
+	cam_slogf( _SLOGC_SIM_MMC, _SLOG_INFO, 1, 1, "%s:  ", __FUNCTION__ );
+#endif
+
+	status =  sdio_set_block_length( dev, SD_SEC_CMD_SIZE );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	cmd = sdio_alloc_cmd( );
+	if( cmd == NULL ) {
+		return( ENOMEM );
+	}
+
+	sdio_setup_cmd( cmd, SCF_CTYPE_ADTC | SCF_RSP_R1, SD_WRITE_SEC_CMD, len / SD_SEC_CMD_SIZE );
+	sge.sg_count	= SD_SEC_CMD_SIZE;
+	sge.sg_address	= SDIO_DATA_PTR_P( data );
+	sdio_setup_cmd_io( cmd, SCF_DIR_OUT, 1, SD_SEC_CMD_SIZE, &sge, 1, NULL );
+	status = sdio_send_cmd( dev, cmd, NULL, timeout, 0 );
+	if( status == EOK ) {
+		if( ( ext->eflags & SDMMC_EFLAG_ASSD_SEND_STOP ) ) {
+			if( sdio_stop_transmission( dev, 0 ) != EOK ) {
+				ext->eflags &= ~SDMMC_EFLAG_ASSD_SEND_STOP;
+			}
+		}
+	}
+
+	sdio_free_cmd( cmd );
+
+	return( status );
+}
+
+static int assd_read_sec_cmd( SIM_HBA *hba, int len, uint8_t *data, int timeout )
+{
+	SIM_SDMMC_EXT		*ext;
+	struct sdio_device	*dev;
+	struct sdio_cmd		*cmd;
+	int					status;
+	sdio_sge_t			sge;
+
+	ext		= (SIM_SDMMC_EXT *)hba->ext;
+	dev		= ext->device;
+
+#ifdef SDMMC_ASSD_DEBUG
+	cam_slogf( _SLOGC_SIM_MMC, _SLOG_INFO, 1, 1, "%s:  ", __FUNCTION__ );
+#endif
+
+	status =  sdio_set_block_length( dev, SD_SEC_CMD_SIZE );
+	if( status != EOK ) {
+		return( status );
+	}
+
+	cmd = sdio_alloc_cmd( );
+	if( cmd == NULL ) {
+		return( ENOMEM );
+	}
+
+	sdio_setup_cmd( cmd, SCF_CTYPE_ADTC | SCF_RSP_R1, SD_READ_SEC_CMD, len / SD_SEC_CMD_SIZE );
+	sge.sg_count	= SD_SEC_CMD_SIZE;
+	sge.sg_address	= SDIO_DATA_PTR_P( data );
+	sdio_setup_cmd_io( cmd, SCF_DIR_IN, 1, SD_SEC_CMD_SIZE, &sge, 1, NULL );
+	status = sdio_send_cmd( dev, cmd, NULL, timeout, 0 );
+	if( status == EOK ) {
+		if( ( ext->eflags & SDMMC_EFLAG_ASSD_SEND_STOP ) ) {
+			if( sdio_stop_transmission( dev, 0 ) != EOK ) {
+				ext->eflags &= ~SDMMC_EFLAG_ASSD_SEND_STOP;
+			}
+		}
+	}
+
+	sdio_free_cmd( cmd );
+
+	return( status );
+}
+
+static int assd_send_psi( SIM_HBA *hba, int rid, uint8_t *psi )
+{
+	SIM_SDMMC_EXT		*ext;
+	struct sdio_device	*dev;
+	struct sdio_cmd		*cmd;
+	int					status;
+	sdio_sge_t			sge;
+
+	ext		= (SIM_SDMMC_EXT *)hba->ext;
+	dev		= ext->device;
+
+#ifdef SDMMC_ASSD_DEBUG
+	cam_slogf( _SLOGC_SIM_MMC, _SLOG_INFO, 1, 1, "%s:  rid %d ", __FUNCTION__, rid );
+#endif
+
+	status =  sdio_set_block_length( dev, SD_PSI_SIZE );
+	if( status != EOK ) {
+		// apparently some cards fail this, but still work...
+	}
+
+	cmd = sdio_alloc_cmd( );
+	if( cmd == NULL ) {
+		return( ENOMEM );
+	}
+
+	sdio_setup_cmd( cmd, SCF_CTYPE_ADTC | SCF_RSP_R1, SD_SEND_PSI, rid );
+	sge.sg_count	= SD_PSI_SIZE;
+	sge.sg_address	= SDIO_DATA_PTR_P( psi );
+	sdio_setup_cmd_io( cmd, SCF_DIR_IN, 1, SD_PSI_SIZE, &sge, 1, NULL );
+	status = sdio_send_cmd( dev, cmd, NULL, ASSD_TIME_DEFAULT, 0 );
+	sdio_free_cmd( cmd );
+
+	if( ( status =  sdio_set_block_length( dev, 512 ) ) ) {
+		// apparently some cards fail this, but still work...
+	}
+
+	return( status );
+}
+
+static int assd_status( SIM_HBA *hba, SDMMC_ASSD_STATUS *as )
+{
+	uint8_t				*psi;
+	int					status;
+
+#ifdef SDMMC_ASSD_DEBUG
+	cam_slogf( _SLOGC_SIM_MMC, _SLOG_INFO, 1, 1, "%s:  ", __FUNCTION__ );
+#endif
+
+	psi = sdio_alloc( ASSD_STATUS_SIZE );
+	if( psi == NULL ) {
+		return( ENOMEM );
+	}
+
+		// read status register
+	status = assd_send_psi( hba, SD_PSI_ASSD_SR, psi );
+	if( status == EOK ) {
+		as->assd_state			= psi[0];
+		as->assd_err_state		= psi[1];
+		as->assd_sec_sys_err	= psi[2] >> 7;
+		as->pmem_state			= psi[3];
+		as->auth_alg			= psi[4];
+		as->enc_alg				= psi[5];
+		as->active_sec_system	= psi[6];
+		as->sec_token_prot		= psi[7];
+		as->read_block_count	= ( psi[8] << 8 ) | psi[9];
+		as->suspended_sec_sys	= ( psi[10] << 8 ) | psi[11];
+	}
+	
+	sdio_free( psi, ASSD_STATUS_SIZE );
+	return( status );
+}
+
+static int assd_properties( SIM_HBA *hba, SDMMC_ASSD_PROPERTIES *prop )
+{
+	uint8_t				*psi;
+	int					status;
+
+	status	= EINVAL;
+
+#ifdef SDMMC_ASSD_DEBUG
+	cam_slogf( _SLOGC_SIM_MMC, _SLOG_INFO, 1, 1, "%s:  ", __FUNCTION__ );
+#endif
+
+	psi = sdio_alloc( ASSD_STATUS_SIZE );
+	if( psi == NULL ) {
+		return( ENOMEM );
+	}
+
+		// read properties register
+	status = assd_send_psi( hba, SD_PSI_ASSD_PR, psi );
+	if( status == EOK ) {
+		prop->sec_read_latency			= psi[0];
+		prop->sec_write_latency			= psi[1];
+		prop->assd_version				= psi[2];
+		prop->cl_support				= ( psi[3] << 7 ) | ( psi[4] >> 1 );
+		prop->pmem_support				= psi[4] & 0x1;
+		prop->pmem_rd_time				= psi[5];
+		prop->pmem_wr_time				= psi[6];
+		prop->wr_sec_bus_busy			= psi[7];
+		prop->sup_auth_alg				= ( psi[8] << 8 ) | psi[9];
+		prop->sup_enc_alg				= ( psi[10] << 8 ) | psi[11];
+		prop->assd_sec_sys				= ( psi[12] << 8 ) | psi[13];
+		prop->assd_sec_sys_vendor_id	= psi[14];
+		prop->ctrl_sys_bus_busy			= psi[15];
+		prop->suspendible_sec_sys		= ( psi[16] << 8 ) | psi[17];
+	}
+	
+	sdio_free( psi, ASSD_STATUS_SIZE );
+	return( status );
+}
+
+static int assd_wait_scc( SIM_HBA *hba, uint32_t msec )
+{
+	uint8_t				*psi;
+	int					status;
+
+	status	= EOK;
+
+#ifdef SDMMC_ASSD_DEBUG
+	cam_slogf( _SLOGC_SIM_MMC, _SLOG_INFO, 1, 1, "%s:  ", __FUNCTION__ );
+#endif
+
+	psi = sdio_alloc( ASSD_STATUS_SIZE );
+	if( psi == NULL ) {
+		return( ENOMEM );
+	}
+
+	for( msec = max( msec, 1 ); msec; msec-- ) {
+		status = assd_send_psi( hba, SD_PSI_ASSD_SR, psi );
+		if( status != EOK ) {
+			break;
+		}
+
+		if( psi[ASSD_STATE_IDX] == ASSD_STATE_SCC ) {
+			status = EOK;
+			break;
+		}
+
+		if( psi[ASSD_STATE_IDX] == ASSD_STATE_SCA ) {
+			status = EIO;
+			break;
+		}
+
+		if( ( psi[ASSD_SEC_SYS_ERROR_IDX] & ASSD_SEC_SYS_ERR ) ) {
+			status = EIO;
+			break;
+		}
+
+		delay( 1 );
+	}
+
+	if( !msec ) {
+		status = ETIMEDOUT;
+	}
+
+	if( status ) {
+		cam_slogf( _SLOGC_SIM_MMC, _SLOG_ERROR, 1, 1, "%s: %s (%d), msec %d, state %d, error %d, sec sys err %d", __FUNCTION__, strerror( status ), status, msec, psi[ASSD_STATE_IDX], psi[ASSD_ERROR_IDX], psi[ASSD_SEC_SYS_ERROR_IDX] );
+	}
+
+	sdio_free( psi, ASSD_STATUS_SIZE );
+
+	return( status );
+}
+
+#ifdef SDMMC_ASSD_SWITCH
+static int assd_cmd_sys( SIM_HBA *hba, int state )
+{
+	SIM_SDMMC_EXT		*ext;
+	struct sdio_device	*dev;
+	int					idx;
+	int					status;
+	uint8_t				ss[64] = { 0 };
+
+	ext		= (SIM_SDMMC_EXT *)hba->ext;
+	dev		= ext->device;
+	idx		= 0;
+
+	if( state ) {
+		status = sdio_sd_switch( dev, SD_SF_MODE_CHECK, SD_SF_GRP_CMD_EXT, SD_SF_CUR_FCN, ss );
+		if( status != EOK ) {
+			return( status );
+		}
+
+		if( ( ss[11] & SD_CMD_SYS_EC ) || ( ss[11] & SD_CMD_SYS_ASSD ) ) {
+//			dev->caps |= DEV_CAP_ASSD;
+		}
+
+			// get index to eC/ASSD
+		idx = ffs( ss[11] & ( SD_CMD_SYS_EC | SD_CMD_SYS_ASSD ) ) - 1;
+	}
+
+	status = sdio_sd_switch( dev, SD_SF_MODE_SET, SD_SF_GRP_CMD_EXT, idx, ss );
+	if( status == EOK ) {
+		if( ( ( ss[16] >> 4 ) & 0x0F ) != idx ) {
+			status = EIO;
+		}
+	}
+
+	return( status );
+}
+#endif
+
+static int assd_state( SIM_HBA *hba, int reinit )
+{
+	SIM_SDMMC_EXT		*ext;
+	SDMMC_ASSD_STATUS	as;
+	int					status;
+
+	ext		= (SIM_SDMMC_EXT *)hba->ext;
+	status		= EOK;
+
+
+	if( !( ext->dev_inf.caps & DEV_CAP_ASSD ) ) {
+		return( ENOTSUP );
+	}
+
+	if( !( ext->eflags & SDMMC_EFLAG_ASSD_INIT ) ) {
+		return( EOK );
+	}
+
+#ifdef SDMMC_ASSD_SWITCH
+	status = assd_cmd_sys( hba, CAM_TRUE );
+	if( status != EOK ) {
+		return( status );
+	}
+#endif
+
+	if( !reinit ) {
+		status = assd_properties( hba, &ext->assd_properties );
+	}
+
+	if( ext->assd_active_sec_sys != -1 ) {
+		status = assd_control_system( hba, 0, ext->assd_active_sec_sys, SDMMC_AC_OP_SELECT_RESET );
+		if( status == EOK ) {
+			status = assd_status( hba, &as );
+			if( status == EOK ) {
+				if( ext->assd_active_sec_sys != as.active_sec_system ) {
+					status = EIO;
+				}
+			}
+		}
+	}
+
+	if( status == EOK ) {
+		atomic_clr( &ext->eflags, SDMMC_EFLAG_ASSD_INIT );
+	}
+
+	return( status );
+}
+
+int sdmmc_assd_control_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb )
+{
+	SIM_SDMMC_EXT			*ext;
+	SDMMC_ASSD_STATUS		as;
+	SDMMC_ASSD_CONTROL		*ctrl;
+	SDMMC_ASSD_PROPERTIES	*prop;
+	int						status;
+
+	ext		= (SIM_SDMMC_EXT *)hba->ext;
+	ctrl	= ccb->cam_devctl_data;
+	prop	= &ext->assd_properties;
+	status	= EINVAL;
+
+	if( sdmmc_unit_ready( hba, (CCB_SCSIIO *)ccb ) != CAM_REQ_CMP ) {
+		ccb->cam_devctl_status = EIO;
+		return( CAM_REQ_CMP );
+	}
+
+	status = assd_state( hba, CAM_TRUE );
+	if( status != EOK ) {
+		ccb->cam_devctl_status = status;
+		return( CAM_REQ_CMP );
+	}
+
+	if( ctrl->sec_sys_idx > SDMMC_AC_SSI_MAX ) {
+		ccb->cam_devctl_status = EINVAL;
+		return( CAM_REQ_CMP );
+	}
+
+	switch( ctrl->operation ) {
+		case SDMMC_AC_OP_START_SUSPEND:
+#if 0
+// untested/supported
+			if( prop->assd_version < ASSD_SPEC_A1_V2 ||
+					!( prop->assd_sec_sys & ( 1 << ctrl->sec_sys_idx ) ) ||
+					!( prop->suspendible_sec_sys & ( 1 << ctrl->sec_sys_idx ) ) ) {
+				status = EINVAL; break;
+			}
+
+			if( ( status = assd_control_system( hba, ctrl->suspend_resume_id, ctrl->sec_sys_idx, ctrl->operation ) ) == EOK ) {
+				if( ( status = assd_status( hba, &as ) ) == EOK ) {
+					if( ( ( 1 << ctrl->sec_sys_idx ) & as.suspended_sec_sys ) ) {
+						status = EIO; break;
+					}
+				}
+			}
+			break;
+#else
+			status = EINVAL;
+			break;
+#endif
+
+		case SDMMC_AC_OP_CLEAR_SUSPEND:
+#if 0
+// untested/supported
+			if( prop->assd_version < ASSD_SPEC_A1_V2 ||
+					!( prop->assd_sec_sys & ( 1 << ctrl->sec_sys_idx ) ) ||
+					!( prop->suspendible_sec_sys & ( 1 << ctrl->sec_sys_idx ) ) ) {
+				status = EINVAL; break;
+			}
+
+			if( ( status = assd_control_system( hba, ctrl->suspend_resume_id, ctrl->sec_sys_idx, ctrl->operation ) ) == EOK ) {
+				if( ( status = assd_status( hba, &as ) ) == EOK ) {
+					if( ctrl->sec_sys_idx != as.active_sec_system ) {
+						status = EIO; break;
+					}
+					ext->assd_active_sec_sys = as.active_sec_system;
+				}
+			}
+			break;
+#else
+			status = EINVAL;
+			break;
+#endif
+
+		case SDMMC_AC_OP_SELECT_RESET:
+			if( prop->assd_version < ASSD_SPEC_A1_V2 ) {
+				if( ctrl->sec_sys_idx != ASSD_SS_MCEX ) {
+					status = EINVAL;
+					break;
+				}
+			}
+			else if( !( prop->assd_sec_sys & ( 1 << ctrl->sec_sys_idx ) ) ) {
+				status = EINVAL;
+				break;
+			}
+			else {
+				// nothing
+			}
+
+			status = assd_control_system( hba, 0, ctrl->sec_sys_idx, ctrl->operation );
+			if( status == EOK ) {
+				status = assd_status( hba, &as );
+				if( status == EOK ) {
+					if( ctrl->sec_sys_idx != as.active_sec_system ) {
+						status = EIO;
+						break;
+					}
+					else {
+						ext->assd_active_sec_sys = as.active_sec_system;
+					}
+				}
+			}
+
+			break;
+
+		default:
+			status = EINVAL;
+			break;
+	}
+
+	ccb->cam_devctl_status = status;
+
+	return( CAM_REQ_CMP );
+}
+
+int sdmmc_assd_status_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb )
+{
+	SDMMC_ASSD_STATUS		*as;
+	int						status;
+
+	as		= ccb->cam_devctl_data;
+
+	if( sdmmc_unit_ready( hba, (CCB_SCSIIO *)ccb ) == CAM_REQ_CMP ) {
+		status = assd_state( hba, CAM_TRUE );
+		if( status == EOK ) {
+			status = assd_status( hba, as );
+		}
+	}
+	else {
+		status = EIO;
+	}
+
+	ccb->cam_devctl_status = status;
+
+	return( CAM_REQ_CMP );
+}
+
+int sdmmc_assd_properties_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb )
+{
+	SDMMC_ASSD_PROPERTIES	*prop;
+	int						status;
+
+	prop	= ccb->cam_devctl_data;
+
+	if( sdmmc_unit_ready( hba, (CCB_SCSIIO *)ccb ) != CAM_REQ_CMP ) {
+		ccb->cam_devctl_status = EIO;
+		return( CAM_REQ_CMP );
+	}
+
+	status = assd_state( hba, CAM_TRUE );
+	if( status == EOK ) {
+		status = assd_properties( hba, prop );
+	}
+
+	ccb->cam_devctl_status = status;
+
+	return( CAM_REQ_CMP );
+}
+
+int sdmmc_assd_apdu_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb )
+{
+	SIM_SDMMC_EXT		*ext;
+	SDMMC_ASSD_APDU		*apdu;
+	struct sdio_device	*dev;
+	uint8_t				*data;
+	uint8_t				*apdu_data;
+	uint32_t			len;
+	int					status;
+
+	ext			= (SIM_SDMMC_EXT *)hba->ext;
+	apdu		= ccb->cam_devctl_data;
+	apdu_data	= (uint8_t *)(apdu + 1);
+	dev			= ext->device;
+	len			= apdu->length + ASSD_APDU_STL_SIZE;	// add 2 for STL
+
+#ifdef SDMMC_ASSD_DEBUG
+	cam_slogf( _SLOGC_SIM_MMC, _SLOG_INFO, 1, 1, "%s:  ", __FUNCTION__ );
+#endif
+
+	if( sdmmc_unit_ready( hba, (CCB_SCSIIO *)ccb ) != CAM_REQ_CMP ) {
+		ccb->cam_devctl_status = EIO;
+		return( CAM_REQ_CMP );
+	}
+
+	status = assd_state( hba, CAM_TRUE );
+	if( status != EOK ) {
+		ccb->cam_devctl_status = status;
+		return( CAM_REQ_CMP );
+	}
+
+	if( ( len + sizeof( SDMMC_ASSD_APDU ) < ccb->cam_devctl_size ) &&
+			( len < ASSD_APDU_MAX_DLEN ) && ( len > ASSD_APDU_MIN_DLEN ) ) {
+		data = sdio_alloc( ASSD_APDU_MAX_DLEN );
+		if( data != NULL ) {
+			data[0] = len >> 8;
+			data[1] = len;
+			memcpy( data + ASSD_APDU_STL_SIZE, apdu_data, len - ASSD_APDU_STL_SIZE );
+			if( len < ASSD_APDU_MAX_DLEN ) {
+				memset( data + len, 0, ASSD_APDU_MAX_DLEN - len );
+			}
+
+#ifdef SDMMC_ASSD_DEBUG
+			sdio_dump( data, len );
+#endif
+			status = assd_write_sec_cmd( hba, ASSD_APDU_MAX_DLEN, data, ASSD_TIME_DEFAULT );
+			if( status == EOK ) {
+				status = sdio_wait_card_status( dev, NULL, CDS_READY_FOR_DATA | CDS_CUR_STATE_MSK, CDS_READY_FOR_DATA | CDS_CUR_STATE_TRAN, ASSD_TIME_DEFAULT );
+				if( status == EOK ) {
+					status = assd_wait_scc( hba, ASSD_TIME_DEFAULT );
+					if( status == EOK ) {
+						status = assd_read_sec_cmd( hba, ASSD_APDU_MAX_DLEN, data, ASSD_TIME_DEFAULT );
+						if( status == EOK ) {
+							apdu->length			= 0;
+							len				= ( ( data[0] << 8 ) + data[1] );
+							if( len > ASSD_APDU_STL_SIZE ) {
+								len -= ASSD_APDU_STL_SIZE;
+								apdu->length	= min( len, ASSD_APDU_MAX_DLEN );
+								memcpy( apdu_data, data + ASSD_APDU_STL_SIZE, apdu->length );
+							}
+#ifdef SDMMC_ASSD_DEBUG
+							sdio_dump( data, len + ASSD_APDU_STL_SIZE );
+#endif
+						}
+					}
+				}
+			}
+			sdio_free( data, ASSD_APDU_MAX_DLEN );
+		}
+		else {
+			status = ENOMEM;
+		}
+	}
+	else {
+		status = EINVAL;
+	}
+
+	ccb->cam_devctl_status = status;
+
+	return( CAM_REQ_CMP );
+}
+
+int sdmmc_assd_init( SIM_HBA *hba )
+{
+	SIM_SDMMC_EXT		*ext;
+	int					status;
+
+	ext			= (SIM_SDMMC_EXT *)hba->ext;
+
+// Some non conforming cards require a stop command during APDU.
+// Don't enable this feature until we find/test one of them.
+//	ext->eflags |= SDMMC_EFLAG_ASSD_SEND_STOP;
+
+	atomic_set( &ext->eflags, SDMMC_EFLAG_ASSD_INIT );
+
+	status = assd_state( hba, CAM_FALSE );
+
+	return( status );
+}
+
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sim_assd.c $ $Rev: 982571 $")
+#endif

src/hardware/devb/sdmmc/sim_sdmmc.h

@@ -0,0 +1,264 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2007, 2008, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+// Module Description:  SIM SDMMC header file
+
+#ifndef _SIM_SDMMC_H_INCLUDED
+#define _SIM_SDMMC_H_INCLUDED
+
+#include <time.h>
+#include <ctype.h>
+#include <stdio.h>
+#include <errno.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stddef.h>
+#include <malloc.h>
+#include <string.h>
+#include <signal.h>
+#include <atomic.h>
+#include <stdarg.h>
+#include <stdbool.h>
+#include <pthread.h>
+#include <gulliver.h>
+#include <hw/inout.h>
+#include <sys/mman.h>
+#include <sys/disk.h>
+#include <sys/types.h>
+#include <sys/trace.h>
+#include <sys/resmgr.h>
+#include <sys/procmgr.h>
+#include <sys/syspage.h>
+
+// CAM specific includes
+#include <module.h>
+#include <ntocam.h>
+#include <sim.h>
+#include <sys/dcmd_cam.h>
+#include <sys/rpmb.h>
+#include <hw/dcmd_sim_sdmmc.h>
+
+#include <sim_bs.h>
+
+#include <sdiodi.h>
+#include <sd.h>
+#include <mmc.h>
+
+#ifdef SDMMC_POWMAN_SUP
+#include <sys/slog2.h>
+#include <powerman/pm_client.h>
+#endif
+
+//#define SDMMC_WRITE_VERIFY
+#define SDMMC_TRIM_SUP
+//#define SDMMC_SIM_RETRY
+
+//#define SDMMC_TRACE
+//#define SDMMC_SIM_DEBUG
+
+#define SDMMC_TRACE_EVENT				1
+
+#define SDMMC_SIM_VERSION				100
+#define SDMMC_SIM_LETTER				'A'
+
+#define SDMMC_RW_RETRIES				2
+#define SDMMC_STACK_SIZE				16384
+#define SDMMC_SCHED_PRIORITY			21
+#define SDMMC_TIME_DEFAULT				5
+#define SDMMC_TIME_INFINITY				0xffffffff
+
+#define SDMMC_PM_TIMER					0x40		// Timer event
+
+#define SDMMC_POWMAN_UPDATE				0x41
+#define SDMMC_POWMAN_RECONNECT			0x42
+
+#define SDMMC_MAX_BUS					10
+
+#define SDMMC_MAX_HBA					8
+#define SDMMC_MAX_TARGET				8
+#define SDMMC_MAX_SG					128
+
+#define SDMMC_START_CCB_MAX				25			// max loops in sdmmc_start_ccb fcn
+
+#define SDMMC_TRIM_MAX_LBA				0xffffffff
+#define SDMMC_TIMEOUT_MS_TO_NS( _to )	( (uint64_t)( _to ) * 1000LL * 1000LL )
+#define SDMMC_TIMEOUT_S_TO_NS( _to )	( (uint64_t)( _to ) * 1000LL * 1000LL * 1000LL )
+
+#define SDMMC_ADDR_ALIGNED( _addr, _align )		( ( ( _addr ) & ( ( typeof( _addr ) )( _align ) - 1 ) ) == 0 )
+
+typedef struct _sdmmc_ctrl {
+	TAILQ_HEAD(,_sim_hba)	hlist;			// linked list of hba's
+
+#define SDMMC_CFLAG_SCAN		0x01		// auto detect interfaces
+#define SDMMC_CFLAG_ENUMERATING	0x02
+#define SDMMC_CFLG_ARGS_ERR		0x04		// flag to indicate arg processing error
+	uint32_t				cflags;
+	int						verbosity;
+	uint32_t				nhba;			// number of hba's
+	path_id_t				pathid_max;		// max path id
+	int						priority;
+
+	int						argc;
+	char					**argv;
+	struct sdio_connection	*connection;
+} SDMMC_CTRL;
+
+#define SDMMC_TARGET_MAX				8
+#define SDMMC_PARTITION_MAX				8
+
+typedef struct _sdmmc_partition {
+	_Uint32t		pflags;
+	_Uint32t		config;
+	char			name[20];
+	_Uint32t		blk_shft;
+	_Uint64t		slba;			// starting lba
+	_Uint64t		elba;			// ending lba
+	_Uint64t		nlba;			// num lba
+	_Uint64t		rc;				// Read Count
+	_Uint64t		wc;				// Written Count
+	_Uint64t		tc;				// TRIM Count
+	_Uint64t		ec;				// Erase Count
+	_Uint64t		dc;				// Discard Count
+} SDMMC_PARTITION;
+
+typedef struct _sdmmc_target {
+	_Uint32t			nluns;
+	_Uint32t			blksz;
+	SDMMC_PARTITION		partitions[SDMMC_PARTITION_MAX];
+} SDMMC_TARGET;
+
+typedef struct _sim_sdmmc_ext {
+	SIM_HBA					*hba;
+
+#define SDMMC_EFLAG_PRESENT				(1 << 0)
+#define SDMMC_EFLAG_TIMER				(1 << 1)
+#define SDMMC_EFLAG_BKOPS				(1 << 2)
+#define SDMMC_EFLAG_DEVNAME				(1 << 3)
+#define SDMMC_EFLAG_PARTITIONS			(1 << 4)	// create hw partitions
+#define SDMMC_EFLAG_ASSD_INIT			(1 << 5)
+#define SDMMC_EFLAG_ASSD_SEND_STOP		(1 << 6)
+#define SDMMC_EFLAG_DEV_BUSY			(1 << 7)
+#define SDMMC_EFLAG_CACHE				(1 << 8)
+#define SDMMC_EFLAG_PWROFF_NOTIFY		(1 << 9)
+#define SDMMC_EFLAG_BKOPS_AUTO			(1 << 10)	// Device BKOPS
+#define SDMMC_EFLAG_VCACHE_DIRTY		(1 << 11)
+#define SDMMC_EFLAG_RELWR				(1 << 12)	// Enable Reliable Writes
+#define SDMMC_EFLAG_POWMAN				(1 << 13)	// Attach to powerman for suspend/resume
+#define SDMMC_EFLAG_BS					(1 << 24)
+	_Uint32t				eflags;
+	_Uint8t					pwroff_notify;
+	_Uint8t					rsvd[7];
+
+	CCB_SCSIIO				*nexus;
+	int						start_ccb_max;			// max loops in sdmmc_start_ccb fcn
+
+	struct sdio_device		*device;
+	sdio_device_instance_t	instance;
+	sdio_hc_info_t			hc_inf;
+	sdio_dev_info_t			dev_inf;
+
+	timer_t					pm_timerid;
+
+	_Uint64t				pm_timestamp;
+	_Uint64t				pm_idle_time_ns;
+	_Uint64t				pm_sleep_time_ns;
+
+#ifdef SDMMC_POWMAN_SUP
+	struct powman			*powman_hdl;
+#endif
+	char					*powman_name;
+
+#define SDMMC_PM_IDLE							0
+#define SDMMC_PM_SLEEP							1
+#define SDMMC_PM_ACTIVE							2
+#define SDMMC_PM_SUSPEND						3
+	_Uint32t				pm_state;
+
+	_Uint32t				drvr_state;			// paused/running
+
+#define BKOPS_NC_TICKS							10
+#define BKOPS_IMPACTED_TICKS					5
+	_Uint32t				bkops_ticks;
+#define BKOPS_STATUS_OPERATIONS_NONE			0
+#define BKOPS_STATUS_OPERATIONS_NON_CRITICAL	1
+#define BKOPS_STATUS_OPERATIONS_IMPACTED		2
+#define BKOPS_STATUS_OPERATIONS_CRITICAL		3
+#define BKOPS_STATUS_OPERATIONS_INPROG			0x80000000
+	_Uint32t				bkops_status;
+#define SDMMC_TIME_BKOPS			( SDIO_TIME_DEFAULT	* 5 )
+
+	SDMMC_ASSD_PROPERTIES	assd_properties;
+	int						assd_active_sec_sys;
+
+	_Uint32t				ntargs;
+	SDMMC_TARGET			targets[SDMMC_TARGET_MAX];
+
+#ifdef SDMMC_WRITE_VERIFY
+#define SDMMC_VER_BSIZE		( 512 * 256 )
+	char					*ver_vaddr;
+	paddr64_t				ver_paddr;
+#endif
+
+} SIM_SDMMC_EXT;
+
+// sim_sdmmc.c
+extern int sdmmc_sim_args( char *options );
+extern int sdmmc_sim_detach( void );
+extern int sdmmc_sim_attach( CAM_ENTRY *centry );
+extern int sdmmc_sim_init( SIM_HBA *hba, int path );
+extern int sdmmc_sim_action( SIM_HBA *hba, CCB *ccbp );
+extern void *sdmmc_driver_thread( void *hdl );
+extern void sdmmc_powman_disconnect( SIM_HBA *hba );
+extern int sdmmc_suspend( SIM_HBA *hba );
+extern int sdmmc_resume( SIM_HBA *hba );
+
+extern int sdmmc_bkops( SIM_HBA *hba, int tick );
+extern int sdmmc_bkops_cfg( SIM_HBA *hba, int op );
+extern int sdmmc_pwroff_notify( SIM_HBA *hba, uint8_t cfg );
+extern int sdmmc_sense( CCB_SCSIIO *ccb, int sense, int asc, int ascq );
+extern int sdmmc_unit_ready( SIM_HBA *hba, CCB_SCSIIO *ccb );
+extern int sdmmc_wp_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb );
+extern int sdmmc_erase_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb );
+extern int sdmmc_card_register_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb );
+extern int sdmmc_rw( SIM_HBA *hba, SDMMC_PARTITION *part, int flgs, uint64_t addr, int dlen, sdio_sge_t *sgl, int sgc, void *mhdl, uint32_t timeout );
+extern int sdmmc_read_write( SIM_HBA *hba, CCB_SCSIIO *ccb, int flgs );
+extern int sdmmc_reset( SIM_HBA *hba );
+extern int sim_bs_partition_config( SIM_HBA *hba );
+extern int sim_bs_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb );
+extern int sim_bs_pass_through( SIM_HBA *hba, CCB_SCSIIO *ccb );
+
+// sim_assd.c
+extern int sdmmc_assd_init( SIM_HBA *hba );
+extern int sdmmc_assd_apdu_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb );
+extern int sdmmc_assd_status_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb );
+extern int sdmmc_assd_control_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb );
+extern int sdmmc_assd_properties_devctl( SIM_HBA *hba, CCB_DEVCTL *ccb );
+
+extern char			*__progname;
+
+extern SDMMC_CTRL sdmmc_ctrl;
+
+#endif
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sim_sdmmc.h $ $Rev: 982571 $")
+#endif

src/hardware/devc/Makefile

@@ -0,0 +1,2 @@
+LIST=DEVC
+include recurse.mk

src/hardware/devc/common.mk

@@ -0,0 +1,74 @@
+#  
+# Copyright 2007, 2008, QNX Software Systems. 
+#  
+# Licensed under the Apache License, Version 2.0 (the "License"). You 
+# may not reproduce, modify or distribute this software except in 
+# compliance with the License. You may obtain a copy of the License 
+# at: http://www.apache.org/licenses/LICENSE-2.0 
+#  
+# Unless required by applicable law or agreed to in writing, software 
+# distributed under the License is distributed on an "AS IS" basis, 
+# WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+# 
+# This file may contain contributions from others, either as 
+# contributors under the License or as licensors under other terms.  
+# Please review this entire file for other proprietary rights or license 
+# notices, as well as the QNX Development Suite License Guide at 
+# http://licensing.qnx.com/license-guide/ for other information.
+# 
+#
+# General purpose makefile for building a Neutrino character device driver
+#
+ifndef QCONFIG
+QCONFIG=qconfig.mk
+endif
+include $(QCONFIG)
+
+NAME=devc-$(SECTION)
+EXTRA_SILENT_VARIANTS+=$(subst -, ,$(SECTION))
+
+LIBS+=io-char smmu drvr secpol
+
+INSTALLDIR=sbin
+
+define PINFO
+PINFO DESCRIPTION=
+endef
+
+CCFLAGS += $(CCFLAGS_$(SECTION)_$(CPU))
+
+include $(MKFILES_ROOT)/qmacros.mk
+include $(SECTION_ROOT)/pinfo.mk
+-include $(SECTION_ROOT)/extra.mk
+
+# Generate a dynamic use file
+# Common io-char use file
+IOCHAR_USEFILE=$(PROJECT_ROOT)/devc.use
+# Generate usefile name and path
+USEFILE_NAME=$(addsuffix $(VARIANT_TAG),$(NAME)).use
+USEFILE=$(PWD)/$(USEFILE_NAME)
+# SOC usefile
+SOC_USEFILE=$(PROJECT_ROOT)/$(SECTION)/$(SECTION).use
+# Print SOC usefile if exists
+ifneq ($(wildcard $(SOC_USEFILE)),)
+$(shell cat $(SOC_USEFILE) > $(USEFILE))
+endif
+# io-char use file
+$(shell cat $(IOCHAR_USEFILE) >> $(USEFILE))
+# Clean up
+EXTRA_CLEAN += $(USEFILE)
+
+
+#####AUTO-GENERATED by packaging script... do not checkin#####
+   INSTALL_ROOT_nto = $(PROJECT_ROOT)/../../../install
+   USE_INSTALL_ROOT=1
+##############################################################
+
+include $(MKFILES_ROOT)/qtargets.mk
+
+
+-include $(PROJECT_ROOT)/roots.mk
+
+ifndef LIBIOCHAR_ROOT
+LIBIOCHAR_ROOT=$(PRODUCT_ROOT)
+endif

src/hardware/devc/devc.use

@@ -0,0 +1,35 @@
+
+io-char common options(Apply for all devc-*)
+ -C number    Size of canonical input buffer (default 256)
+ -e           Set options to "edit" mode
+ -E           Set options to "raw" mode (default)
+ -f           Enable hardware flow control (default)
+ -F           Disable hardware flow control
+ -I number    Size of raw input buffer (default 2048)
+ -o opt[,opt] string options:
+              disable=rx (Disable the UART receiver on driver startup)
+              devperm    (Set permissions to the serial device)
+              highwater=value (RX watermark for input flow control (bytes))
+              kdebug     (Drop into Kernel Debugger)
+              log=flow[@directory_path] (Specify whether to log data for receive, transmit, or both. Default log directory is /dev/shmem)
+                   Specify one of these values for flow:
+                   tx — transmit data only
+                   rx — receive data only
+                   all — both transmit and receive
+              nodaemon (Don't call procmgr_daemon() to make the driver run in the background)
+              priority=prio (Set the working priority of the internal pulse as a numeric value)
+              smmu=0|1|off|on (Specify whether or not support for the system memory management unit (IOMMU/SMMU) manager is required)
+                   0 or off — disable SMMU support. This is the default.
+                   1 or on  — SMMU support is required
+              termflags=[-]flag[:[-]flag]* (Specify terminal flag settings)
+              ticksize_ms=value    (timer granularity in ms. default 50ms)
+ -O number    Size of output buffer (default 2048)
+ -s           Enable software flow control
+ -S           Disable software flow control (default)
+ -v           Increase verbosity level(default 2)
+
+io-char serial options(Apply for devc-ser* and devc-virtio only)
+ -b number    Define initial baud rate (default 115200)
+ -c clk/div   Set the input clock rate and divisor
+ -u unit      Set serial unit number (default 1)
+

src/hardware/devc/serminiuart/Makefile

@@ -0,0 +1,2 @@
+LIST=CPU
+include recurse.mk

src/hardware/devc/serminiuart/aarch64/Makefile

@@ -0,0 +1,2 @@
+LIST=VARIANT
+include recurse.mk

src/hardware/devc/serminiuart/aarch64/le/Makefile

@@ -0,0 +1 @@
+include ../../../common.mk

src/hardware/devc/serminiuart/externs.c

@@ -0,0 +1,30 @@
+/*
+ * $QNXLicenseC:
+ * Copyright 2020, QNX Software Systems.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"). You
+ * may not reproduce, modify or distribute this software except in
+ * compliance with the License. You may obtain a copy of the License
+ * at: http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
+ *
+ * This file may contain contributions from others, either as
+ * contributors under the License or as licensors under other terms.
+ * Please review this entire file for other proprietary rights or license
+ * notices, as well as the QNX Development Suite License Guide at
+ * http://licensing.qnx.com/license-guide/ for other information.
+ * $
+ */
+
+
+#define DEFN
+
+#include "externs.h"
+
+#if defined(__QNXNTO__) && defined(__USESRCVERSION)
+#include <sys/srcversion.h>
+__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devc/serminiuart/externs.c $ $Rev: 932256 $")
+#endif