[uboot] Upgrade the MMF SDK from V4.0.0 to V4.1.0
1. add cv181x functions 2. Delete some useless files and add .gitignore Change-Id: Iea2b2fa43b5a1152e5e99fb32b88f8d2c249251a
This commit is contained in:
wangliang.wang
committed by
sam.xiang
sam.xiang
parent
aa1b345a00
commit
607778300c
@ -5,166 +5,95 @@
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#include <common.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <panel.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/hardware.h>
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//#include <asm/hardware.h>
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#include <asm/io.h>
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#include <dm/uclass-internal.h>
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//#include <dm/uclass-internal.h>
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#include <linux/kernel.h>
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#include "reg.h"
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#include "vip_common.h"
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#include "scaler.h"
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#include "dsi_phy.h"
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#include <cvi_lvds.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MHz 1000000
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/*
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* Private information for cvi lvds
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*
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* @regs: lvds controller address
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* @panel: panel assined by device tree
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* @ref_clk: reference clock for lvds dsi pll
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* @sysclk: config clock for lvds dsi register
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* @pix_clk: pixel clock for vop->dsi data transmission
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* @phy_clk: lvds dphy output clock
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* @txbyte_clk: clock for dsi->dphy high speed data transmission
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* @txesc_clk: clock for tx esc mode
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*/
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struct cvi_lvds_priv {
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struct udevice *panel;
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u32 ref_clk;
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u32 sys_clk;
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u32 pix_clk;
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u32 phy_clk;
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u32 txbyte_clk;
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u32 txesc_clk;
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};
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static int cvi_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
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static void _fill_disp_timing(struct sclr_disp_timing *timing, struct sync_info_s *sync_info)
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{
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int ret;
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timing->vtotal = sync_info->vid_vsa_lines + sync_info->vid_vbp_lines
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+ sync_info->vid_active_lines + sync_info->vid_vfp_lines - 1;
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timing->htotal = sync_info->vid_hsa_pixels + sync_info->vid_hbp_pixels
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+ sync_info->vid_hline_pixels + sync_info->vid_hfp_pixels - 1;
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timing->vsync_start = 1;
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timing->vsync_end = timing->vsync_start + sync_info->vid_vsa_lines - 1;
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timing->vfde_start = timing->vsync_start + sync_info->vid_vsa_lines + sync_info->vid_vbp_lines;
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timing->vfde_end = timing->vfde_start + sync_info->vid_active_lines - 1;
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timing->hsync_start = 1;
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timing->hsync_end = timing->hsync_start + sync_info->vid_hsa_pixels - 1;
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timing->hfde_start = timing->hsync_start + sync_info->vid_hsa_pixels + sync_info->vid_hbp_pixels;
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timing->hfde_end = timing->hfde_start + sync_info->vid_hline_pixels - 1;
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timing->vsync_pol = sync_info->vid_vsa_pos_polarity;
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timing->hsync_pol = sync_info->vid_hsa_pos_polarity;
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ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), 0, timing);
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if (ret) {
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debug("%s: Failed to decode display timing (ret=%d)\n",
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__func__, ret);
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return -EINVAL;
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}
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return 0;
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timing->vmde_start = timing->vfde_start;
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timing->vmde_end = timing->vfde_end;
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timing->hmde_start = timing->hfde_start;
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timing->hmde_end = timing->hfde_end;
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}
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/*
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* This function is called by cvi_display_init() using cvi_lvds_enable() and
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* cvi_lvds_phy_enable() to initialize lvds controller and dphy. If success,
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* enable backlight.
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*/
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static int cvi_lvds_enable(struct udevice *dev, int panel_bpp, const struct display_timing *timing)
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int lvds_init(struct cvi_lvds_cfg_s *lvds_cfg)
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{
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int ret = 0;
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struct cvi_lvds_priv *priv = dev_get_priv(dev);
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union sclr_lvdstx lvds_reg;
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bool data_en[LANE_MAX_NUM] = {false, false, false, false, false};
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struct sclr_disp_timing timing;
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struct disp_ctrl_gpios ctrl_gpios;
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int i = 0, ret = 0;
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/* Fill the lvds controller parameter */
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priv->ref_clk = 24 * MHz;
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priv->sys_clk = priv->ref_clk;
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priv->pix_clk = timing->pixelclock.typ;
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priv->phy_clk = priv->pix_clk * 6;
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priv->txbyte_clk = priv->phy_clk / 8;
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priv->txesc_clk = 20 * MHz;
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#if 0
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/* Config and enable lvds dsi according to timing */
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ret = rk_lvds_enable(dev, timing);
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if (ret) {
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debug("%s: rk_lvds_enable() failed (err=%d)\n",
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__func__, ret);
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return ret;
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for (i = 0; i < LANE_MAX_NUM; i++) {
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if (lvds_cfg->lane_id[i] < 0 || lvds_cfg->lane_id[i] >= LANE_MAX_NUM) {
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dphy_dsi_set_lane(i, VO_LVDS_LANE_MAX, false, false);
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continue;
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}
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dphy_dsi_set_lane(i, lvds_cfg->lane_id[i], lvds_cfg->lane_pn_swap[i], false);
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if (lvds_cfg->lane_id[i] != VO_LVDS_LANE_CLK) {
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data_en[lvds_cfg->lane_id[i] - 1] = true;
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}
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}
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/* Config and enable lvds phy */
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ret = rk_lvds_phy_enable(dev);
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if (ret) {
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debug("%s: rk_lvds_phy_enable() failed (err=%d)\n",
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__func__, ret);
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return ret;
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}
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dphy_dsi_lane_en(true, data_en, false);
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sclr_disp_set_intf(SCLR_VO_INTF_LVDS);
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/* Enable backlight */
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ret = panel_enable_backlight(priv->panel);
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if (ret) {
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debug("%s: panel_enable_backlight() failed (err=%d)\n",
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__func__, ret);
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return ret;
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lvds_reg.b.out_bit = lvds_cfg->out_bits;
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lvds_reg.b.vesa_mode = lvds_cfg->mode;
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if (lvds_cfg->chn_num == 1)
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lvds_reg.b.dual_ch = 0;
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else if (lvds_cfg->chn_num == 2)
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lvds_reg.b.dual_ch = 1;
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else {
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lvds_reg.b.dual_ch = 0;
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printf("invalid lvds chn_num(%d). Use 1 instead.", lvds_cfg->chn_num);
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}
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#endif
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lvds_reg.b.vs_out_en = 1;
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lvds_reg.b.hs_out_en = 1;
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lvds_reg.b.hs_blk_en = 1;
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lvds_reg.b.ml_swap = 1;
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lvds_reg.b.ctrl_rev = 0;
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lvds_reg.b.oe_swap = 0;
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lvds_reg.b.en = 1;
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dphy_lvds_set_pll(lvds_cfg->pixelclock, lvds_cfg->chn_num);
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dphy_dsi_analog_setting(true);
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sclr_lvdstx_set(lvds_reg);
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_fill_disp_timing(&timing, &lvds_cfg->sync_info);
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sclr_disp_set_timing(&timing);
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sclr_disp_tgen_enable(true);
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get_disp_ctrl_gpios(&ctrl_gpios);
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ret = dm_gpio_set_value(&ctrl_gpios.disp_pwm_gpio,
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ctrl_gpios.disp_pwm_gpio.flags & GPIOD_ACTIVE_LOW ? 0 : 1);
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if (ret < 0)
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printf("dm_gpio_set_value(disp_pwm_gpio, deassert) failed: %d", ret);
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return ret;
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}
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static int cvi_lvds_ofdata_to_platdata(struct udevice *dev)
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{
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struct cvi_lvds_priv *priv = dev_get_priv(dev);
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priv = priv;
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#if 0
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (priv->grf <= 0) {
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debug("%s: Get syscon grf failed (ret=%llu)\n",
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__func__, (u64)priv->grf);
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return -ENXIO;
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}
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#endif
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return 0;
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}
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/*
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* Probe function: check panel existence and readingit's timing. Then config
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* lvds dsi controller and enable it according to the timing parameter.
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*/
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static int cvi_lvds_probe(struct udevice *dev)
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{
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int ret = 0;
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struct cvi_lvds_priv *priv = dev_get_priv(dev);
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priv = priv;
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#if 0
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ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "cvitek,panel",
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&priv->panel);
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if (ret) {
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debug("%s: Can not find panel (err=%d)\n", __func__, ret);
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return ret;
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}
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#endif
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return ret;
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}
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static const struct dm_display_ops cvi_lvds_ops = {
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.read_timing = cvi_lvds_read_timing,
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.enable = cvi_lvds_enable,
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};
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static const struct udevice_id cvi_lvds_ids[] = {
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{ .compatible = "cvitek,lvds" },
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{ }
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};
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U_BOOT_DRIVER(cvi_lvds) = {
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.name = "cvi_lvds",
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.id = UCLASS_DISPLAY,
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.of_match = cvi_lvds_ids,
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.ofdata_to_platdata = cvi_lvds_ofdata_to_platdata,
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.probe = cvi_lvds_probe,
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.ops = &cvi_lvds_ops,
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.priv_auto_alloc_size = sizeof(struct cvi_lvds_priv),
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};
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