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uboot: version release v4.1.5

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[feat] add cvi_update_rtos tool
[feat](uboot):Support uart download

Change-Id: I4027f9ceba4205d2d5c7c5135b888172ac49203a
This commit is contained in:
forum_service
2023-12-18 13:50:17 +08:00
committed by carbon
parent 303ec5da3b
commit b7e531da4e
12 changed files with 761 additions and 45 deletions
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6
u-boot-2021.10/Makefile
View File

@ -17,6 +17,7 @@ NAME =
MAKEFLAGS += -rR
# Determine target architecture for the sandbox
-include ${BUILD_PATH}/.config
include include/host_arch.h
ifeq ("", "$(CROSS_COMPILE)")
MK_ARCH="${shell uname -m}"
@ -431,6 +432,11 @@ KBUILD_CFLAGS += -Werror
KBUILD_AFLAGS := -D__ASSEMBLY__
KBUILD_LDFLAGS :=
ifdef CONFIG_ENABLE_ALIOS_UPDATE
KBUILD_CFLAGS += -DCONFIG_ENABLE_ALIOS_UPDATE
endif
ifeq ($(cc-name),clang)
ifneq ($(CROSS_COMPILE),)
CLANG_TARGET := --target=$(notdir $(CROSS_COMPILE:%-=%))

1
u-boot-2021.10/cmd/Makefile
View File

@ -72,6 +72,7 @@ obj-$(CONFIG_CMD_CVI_JPEG) += cvi_jpeg.o
obj-$(CONFIG_CMD_CVI_VO) += cvi_vo.o
obj-$(CONFIG_CMD_CVI_UPDATE) += cvi_update.o
obj-$(CONFIG_CMD_CVI_UPDATE) += cvi_utask.o
obj-$(CONFIG_ENABLE_ALIOS_UPDATE) += cvi_update_rtos.o
obj-$(CONFIG_NAND_SUPPORT) += cvi_sd_update.o cvi_sd_update_spinand_v3.o
obj-$(CONFIG_CMD_FPGA) += fpga.o
obj-$(CONFIG_CMD_FPGAD) += fpgad.o

120
u-boot-2021.10/cmd/cvi_update.c
View File

@ -3,23 +3,15 @@
#include <asm/io.h>
#include <imgs.h>
#include <ubifs_uboot.h>
#include <serial.h>
#include <asm/global_data.h>
#include <linux/delay.h>
#ifdef CONFIG_NAND_SUPPORT
#include <nand.h>
#endif
#include "cvi_update.h"
#define COMPARE_STRING_LEN 3
#define SD_UPDATE_MAGIC 0x4D474E32
#define ETH_UPDATE_MAGIC 0x4D474E35
#define USB_DRIVE_UPGRADE_MAGIC 0x55425355
#define FIP_UPDATE_MAGIC 0x55464950
#define UPDATE_DONE_MAGIC 0x50524F47
#define OTA_MAGIC 0x5245434F
//#define ALWAYS_USB_DRVIVE_UPGRATE
#define HEADER_SIZE 64
#define SECTOR_SIZE 0x200
#define HEADER_MAGIC "CIMG"
#define MAX_LOADSIZE (16 * 1024 * 1024)
#ifdef CONFIG_CMD_SAVEENV
#define SET_DL_COMPLETE() \
do { \
@ -35,8 +27,7 @@ static uint32_t lastend;
#endif
uint32_t update_magic;
enum chunk_type_e { dont_care = 0, check_crc };
enum storage_type_e { sd_dl = 0, usb_dl };
#if (!defined CONFIG_TARGET_CVITEK_CV181X_FPGA) && (!defined CONFIG_TARGET_CVITEK_ATHENA2_FPGA) && \
(!defined ATHENA2_FPGA_PALLDIUM_ENV)
@ -313,6 +304,104 @@ static int _usb_update(uint32_t usb_pid)
}
#endif
DECLARE_GLOBAL_DATA_PTR;
static void set_baudrate(unsigned int baudrate)
{
mdelay(50);
gd->baudrate = baudrate;
serial_setbrg();
mdelay(50);
}
int uart_download(void *buf, const char *filename)
{
int ret = 0;
char cmd[255] = { '\0' };
snprintf(cmd, 255, "loadb %p %d ", (void *)HEADER_ADDR, UART_DL_BAUDRATE);
ret = run_command(cmd, 0);
if (ret)
return ret;
char *magic = (void *)HEADER_ADDR;
if (!strncmp(magic, "O", 1)) {
printf("File %s not exist, skip it!\n", filename);
return ret;
}
uint32_t chunk_header_sz = *(uint32_t *)((uintptr_t)HEADER_ADDR + 8);
ret = strncmp(magic, HEADER_MAGIC, 4);
if (ret) {
printf("File %s's magic number is wrong, skip it!\n", filename);
return ret;
}
ret = _prgImage((void *)(HEADER_ADDR + HEADER_SIZE), chunk_header_sz, NULL);
if (ret == 0) {
printf("Program file %s failed!\n", filename);
return ret;
}
return 0;
}
static int _uart_update(void)
{
int ret = 0;
char cmd[255] = { '\0' };
printf("Start UART downloading... Change boadrate to %d\n", UART_DL_BAUDRATE);
set_baudrate(UART_DL_BAUDRATE);
snprintf(cmd, 255, "loadb %p %d ", (void *)HEADER_ADDR, UART_DL_BAUDRATE);
ret = run_command(cmd, 0);
if (ret) {
printf("Download fip.bin failed!\n");
return ret;
}
#ifdef CONFIG_NAND_SUPPORT
snprintf(cmd, 255, "cvi_sd_update %p spinand fip", (void *)UPDATE_ADDR);
pr_debug("%s\n", cmd);
ret = run_command(cmd, 0);
#elif defined(CONFIG_SPI_FLASH)
ret = run_command("sf probe", 0);
snprintf(cmd, 255, "sf update %p ${fip_PART_OFFSET} ${fip_PART_SIZE};", (void *)UPDATE_ADDR)
pr_debug("%s\n", cmd);
ret = run_command(cmd, 0);
#else
// Switch to boot partition
ret = run_command("mmc dev 0 1", 0);
snprintf(cmd, 255, "mmc write %p 0 0x800;", (void *)UPDATE_ADDR);
pr_debug("%s\n", cmd);
ret = run_command(cmd, 0);
snprintf(cmd, 255, "mmc write %p 0x800 0x800;", (void *)UPDATE_ADDR);
pr_debug("%s\n", cmd);
ret = run_command(cmd, 0);
// Switch to user partition
ret = run_command("mmc dev 0 0", 0);
#endif
if (ret) {
printf("Program fip.bin failed!\n");
return ret;
}
SET_DL_COMPLETE();
printf("Program fip.bin done\n");
for (int i = 1; i < ARRAY_SIZE(imgs); i++) {
ret = uart_download((void *)HEADER_ADDR, imgs[i]);
if (ret) {
printf("Load %s failed, skip it!\n", imgs[i]);
continue;
}
}
// set_baudrate(CONFIG_BAUDRATE);
return ret;
}
static int do_cvi_update(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@ -324,7 +413,10 @@ static int do_cvi_update(struct cmd_tbl *cmdtp, int flag, int argc,
if (argc == 1) {
update_magic = readl((unsigned int *)BOOT_SOURCE_FLAG_ADDR);
if (update_magic == SD_UPDATE_MAGIC) {
if (update_magic == UART_UPDATE_MAGIC) {
run_command("env default -a", 0);
ret = _uart_update();
} else if (update_magic == SD_UPDATE_MAGIC) {
run_command("env default -a", 0);
ret = _storage_update(sd_dl);
} else if (update_magic == USB_UPDATE_MAGIC) {

463
u-boot-2021.10/cmd/cvi_update_rtos.c Normal file
View File

@ -0,0 +1,463 @@
/***************************************
* function: mars alios update
* *****************************************/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <ubifs_uboot.h>
#ifdef CONFIG_NAND_SUPPORT
#include <nand.h>
#endif
#include "cvi_update.h"
// #define DEBUG_ALIOS_UPDATE // Used when developing modes
#define PUBLIC_KEY_NAME_SIZE 8
#define MTB_IMAGE_NAME_SIZE 8
#define MTB_OS_VERSION_LEN_V4 64 /* for version 4.0, os version length is 64*/
#define ONCE_UPDATE_FILE_MAX_SIZE \
(16 * 1024 * 1024) /* once update file max size */
enum status_type {
STATUS_OK = 0,
ERROR_FATSIZE,
ERROR_FATLOAD,
ERROR_MMCDEV,
ERROR_ERASE,
ERROR_WRITE,
ERROR_PART,
ERROR_UNKONW
};
enum storage_device_type {
MEM_DEVICE_TYPE_EFLASH = 0,
MEM_DEVICE_TYPE_SPI_NOR_FLASH,
MEM_DEVICE_TYPE_SPI_NAND_FLASH,
MEM_DEVICE_TYPE_SD,
MEM_DEVICE_TYPE_EMMC,
MEM_DEVICE_TYPE_USB,
MEM_DEVICE_TYPE_EFUSE,
MEM_DEVICE_TYPE_MAX
};
struct tb_flag {
uint16_t encrypted : 1;
uint16_t reserve : 7;
uint16_t update_flag : 1;
uint16_t reserve2 : 7;
};
struct storage_info {
uint32_t id : 8;
uint32_t type : 8; // enum storage_device_type
uint32_t area : 4; // such as emmc area.
uint32_t hot_plug : 1;
uint32_t rsv : 11;
};
struct imtb_head_v4 {
uint32_t magic;
uint16_t version;
struct tb_flag flag;
uint16_t digest_sch;
uint16_t signature_sch;
char pub_key_name[PUBLIC_KEY_NAME_SIZE];
uint16_t partition_count;
uint16_t size;
};
struct imtb_partition_info_v4 {
char name[MTB_IMAGE_NAME_SIZE];
struct storage_info storage_info;
uint32_t preload_size;
uint16_t block_count_h;
uint16_t block_count;
uint32_t block_offset;
uint32_t load_address;
uint32_t img_size;
};
static uint32_t bcd2hex4(uint32_t bcd)
{
return ((bcd) & 0x0f) + (((bcd) >> 4) & 0xf0) + (((bcd) >> 8) & 0xf00) +
(((bcd) >> 12) & 0xf000);
}
#ifdef DEBUG_ALIOS_UPDATE
void show_imtb(struct imtb_partition_info_v4 *part_at)
{
printf("part_at->name = %s\n", part_at->name);
printf("part_at->storage_info.type = 0x%x\n",
part_at->storage_info.type);
printf("part_at->storage_info.area = 0x%x\n",
part_at->storage_info.area);
printf("part_at->preload_size = 0x%x\n", part_at->preload_size);
printf("part_at->block_count_h = 0x%x\n", part_at->block_count_h);
printf("part_at->block_count = 0x%x\n", part_at->block_count);
printf("part_at->block_offset = 0x%x\n", part_at->block_offset);
printf("part_at->load_address = 0x%x\n", part_at->load_address);
printf("part_at->img_size = 0x%x\n", part_at->img_size);
}
#endif
static int _storage_update_rtos(enum storage_type_e type)
{
char cmd[255] = { '\0' };
char strStorage[10] = { '\0' };
void *load_addr = NULL;
struct imtb_head_v4 *head = NULL;
struct imtb_partition_info_v4 *part_at = NULL;
uint32_t erase_size = 0;
uint32_t erase_pos = 0, erase_pos_next = 0;
uint32_t pro_addr = 0, pro_size = 0;
uint8_t sd_index = 0;
uint32_t block_count32 = 0, update_file_size = 0;
if (type == sd_dl) {
printf("Start SD downloading...\n");
// Consider SD card with MBR as default
#if defined(CONFIG_NAND_SUPPORT) || defined(CONFIG_SPI_FLASH)
strlcpy(strStorage, "mmc 0:1", 9);
#elif defined(CONFIG_EMMC_SUPPORT)
strlcpy(strStorage, "mmc 1:1", 9);
#endif
snprintf(cmd, 255, "mmc dev %u:1 SD_HS", sd_index);
run_command(cmd, 0);
snprintf(cmd, 255, "fatload %s %p imtb;", strStorage,
(void *)HEADER_ADDR);
if (run_command(cmd, 0)) {
// Consider SD card without MBR
printf("** Trying use partition 0 (without MBR) **\n");
#if defined(CONFIG_NAND_SUPPORT) || defined(CONFIG_SPI_FLASH)
strlcpy(strStorage, "mmc 0:0", 9);
sd_index = 0;
#elif defined(CONFIG_EMMC_SUPPORT)
sd_index = 1;
strlcpy(strStorage, "mmc 1:0", 9);
#endif
snprintf(cmd, 255, "mmc dev %u:0 SD_HS", sd_index);
run_command(cmd, 0);
snprintf(cmd, 255, "fatload %s %p imtb;", strStorage,
(void *)HEADER_ADDR);
if (run_command(cmd, 0)) {
printf("load imtb error\n");
return -1;
}
}
} else {
return -1;
}
#if defined(CONFIG_SPI_FLASH)
run_command("sf probe", 0);
#endif
head = (struct imtb_head_v4 *)HEADER_ADDR;
part_at =
(struct imtb_partition_info_v4 *)((uint8_t *)head +
sizeof(struct imtb_head_v4) +
MTB_OS_VERSION_LEN_V4);
load_addr = part_at + head->partition_count;
if (part_at->storage_info.type == MEM_DEVICE_TYPE_SPI_NOR_FLASH) {
snprintf(cmd, 255, "sf erase_size 0x%p;", &erase_size);
run_command(cmd, 0);
printf("get flash erase size = 0x%x\n", erase_size);
}
for (int i = 0; i < head->partition_count; i++, part_at++) {
#ifdef DEBUG_ALIOS_UPDATE
show_imtb(part_at);
#else
enum status_type status = STATUS_OK;
block_count32 =
(part_at->block_count_h << 16) | part_at->block_count;
// The file storage addresses in the imtb go from small to large
if (part_at->storage_info.type ==
MEM_DEVICE_TYPE_SPI_NOR_FLASH) {
memset(load_addr, 0, block_count32 * 512);
snprintf(cmd, 255, "fatload %s %p %s;", strStorage,
(void *)load_addr, part_at->name);
if (run_command(cmd, 0)) {
status = ERROR_FATLOAD;
printf("program %s failed, skip it!, status=%d\n",
part_at->name, status);
continue;
}
pro_addr = part_at->block_offset * 512;
pro_size = block_count32 * 512;
if (erase_pos <= (pro_addr + pro_size)) {
if (pro_addr >= erase_size + erase_pos) {
erase_pos =
pro_addr & (~(erase_size - 1));
}
erase_pos_next =
(pro_addr + pro_size + erase_size) &
(~(erase_size - 1));
if (erase_pos_next > erase_pos) {
snprintf(cmd, 255,
"sf erase 0x%x 0x%x;",
erase_pos,
(erase_pos_next - erase_pos));
run_command(cmd, 0);
erase_pos = erase_pos_next;
}
}
snprintf(cmd, 255, "sf write %p 0x%x 0x%x",
(void *)load_addr,
(part_at->block_offset * 512),
(block_count32 * 512));
if (run_command(cmd, 0))
status = ERROR_WRITE;
} else if (part_at->storage_info.type == MEM_DEVICE_TYPE_EMMC) {
/* 1. get update file size */
snprintf(cmd, 255, "fatsize %s %s;", strStorage,
part_at->name);
if (run_command(cmd, 0)) {
status = ERROR_FATSIZE;
printf("get %s size failed, skip it!, status=%d\n",
part_at->name, status);
continue;
}
update_file_size = env_get_hex("filesize", 0);
if (update_file_size <= 0) {
status = ERROR_FATSIZE;
printf("get %s size failed, skip it!, status=%d\n",
part_at->name, status);
continue;
}
if (update_file_size > (block_count32 * 512)) {
status = ERROR_FATSIZE;
printf("%s size too large, skip it!, status=%d\n",
part_at->name, status);
continue;
}
/* 2. erase storage partition size */
snprintf(cmd, 255, "mmc dev 0 %u;",
part_at->storage_info.area);
if (run_command(cmd, 0)) {
status = ERROR_MMCDEV;
printf("%s mmc dev failed, skip it!, status=%d\n",
part_at->name, status);
continue;
}
snprintf(cmd, 255, "mmc erase 0x%x 0x%x;",
part_at->block_offset, block_count32);
if (run_command(cmd, 0)) {
status = ERROR_ERASE;
printf("%s mmc erase failed, skip it!, status=%d\n",
part_at->name, status);
continue;
}
/* whether the file needs to be upgraded multiple times */
if (update_file_size <= ONCE_UPDATE_FILE_MAX_SIZE) {
/* 3. load update file to dram from sd */
snprintf(cmd, 255, "fatload %s %p %s;",
strStorage, (void *)load_addr,
part_at->name);
if (run_command(cmd, 0)) {
status = ERROR_FATLOAD;
printf("program %s failed, skip it!, status=%d\n",
part_at->name, status);
continue;
}
/* 4. write update file to storage */
snprintf(cmd, 255, "mmc write %p 0x%x 0x%x;",
(void *)load_addr,
part_at->block_offset, block_count32);
if (run_command(cmd, 0)) {
status = ERROR_WRITE;
printf("program %s failed, skip it!, status=%d\n",
part_at->name, status);
continue;
}
} else {
uint32_t offset_blk = 0;
int file_par_max = update_file_size /
ONCE_UPDATE_FILE_MAX_SIZE;
for (int file_par_num = 0;
file_par_num < file_par_max;
file_par_num++) {
/* 3. load update file to dram from sd */
snprintf(cmd, 255,
"fatload %s %p %s 0x%x 0x%x;",
strStorage, (void *)load_addr,
part_at->name,
ONCE_UPDATE_FILE_MAX_SIZE,
offset_blk * 512);
if (run_command(cmd, 0)) {
status = ERROR_FATLOAD;
printf("program %s failed, skip it!, status=%d\n",
part_at->name, status);
break;
}
/* 4. write update file to storage */
snprintf(cmd, 255,
"mmc write %p 0x%x 0x%x;",
(void *)load_addr,
part_at->block_offset +
offset_blk,
ONCE_UPDATE_FILE_MAX_SIZE /
512);
if (run_command(cmd, 0)) {
status = ERROR_WRITE;
printf("program %s failed, skip it!, status=%d\n",
part_at->name, status);
break;
}
offset_blk +=
ONCE_UPDATE_FILE_MAX_SIZE / 512;
}
if (status != STATUS_OK)
continue;
/* write the last part of update file */
if (update_file_size %
ONCE_UPDATE_FILE_MAX_SIZE) {
uint32_t last_part_size =
update_file_size -
offset_blk * 512;
memset(load_addr, 0,
ONCE_UPDATE_FILE_MAX_SIZE);
/* 3. load update file to dram from sd */
snprintf(cmd, 255,
"fatload %s %p %s 0x%x 0x%x;",
strStorage, (void *)load_addr,
part_at->name, last_part_size,
offset_blk * 512);
if (run_command(cmd, 0)) {
status = ERROR_FATLOAD;
printf("program %s failed, skip it!, status=%d\n",
part_at->name, status);
continue;
}
/* 4. write update file to storage */
snprintf(cmd, 255,
"mmc write %p 0x%x 0x%x;",
(void *)load_addr,
part_at->block_offset +
offset_blk,
last_part_size % 512 ?
last_part_size / 512 +
1 :
last_part_size / 512);
if (run_command(cmd, 0)) {
status = ERROR_WRITE;
printf("program %s failed, skip it!, status=%d\n",
part_at->name, status);
continue;
}
}
}
} else {
printf("Unknown storage type:0x%x\n",
part_at->storage_info.type);
status = ERROR_UNKONW;
}
if (status != STATUS_OK) {
printf("program %s failed, skip it!, status=%d\n",
part_at->name, status);
} else {
printf("program %s success\n", part_at->name);
}
#endif
}
return 0;
}
static int _usb_update_rtos(uint32_t usb_pid)
{
int ret = 0;
char cmd[255] = { '\0' };
printf("Start USB downloading...\n");
#ifdef CONFIG_SPI_FLASH
ret = run_command("sf probe", 0);
#endif
// Clean download flags
writel(0x0,
(unsigned int *)BOOT_SOURCE_FLAG_ADDR); //mw.l 0xe00fc00 0x0;
// Always download Fip first
snprintf(cmd, 255, "cvi_utask vid 0x3346 pid 0x%x", usb_pid);
ret = run_command(cmd, 0);
#ifdef CONFIG_NAND_SUPPORT
snprintf(cmd, 255, "cvi_sd_update %p spinand fip", (void *)UPDATE_ADDR);
pr_debug("%s\n", cmd);
ret = run_command(cmd, 0);
#elif defined(CONFIG_SPI_FLASH)
ret = run_command("sf probe", 0);
#else
// Switch to boot partition
run_command("mmc dev 0 1", 0);
snprintf(cmd, 255, "mmc write %p 0 0x800;", (void *)UPDATE_ADDR);
pr_debug("%s\n", cmd);
run_command(cmd, 0);
snprintf(cmd, 255, "mmc write %p 0x800 0x800;", (void *)UPDATE_ADDR);
pr_debug("%s\n", cmd);
run_command(cmd, 0);
printf("Program fip.bin done\n");
// Switch to user partition
run_command("mmc dev 0 0", 0);
#endif
snprintf(cmd, 255, "cvi_utask vid 0x3346 pid 0x%x", usb_pid);
while (1) {
ret = run_command(cmd, 0);
if (ret) {
pr_debug("cvi_utask failed(%d)\n", ret);
return ret;
}
//_prgImage((void *)UPDATE_ADDR, readl(HEADER_ADDR + 8));
};
return 0;
}
int do_cvi_update_rtos(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int ret = 1;
uint32_t usb_pid = 0;
uint32_t update_magic;
if (argc == 1) {
update_magic = readl((unsigned int *)BOOT_SOURCE_FLAG_ADDR);
if (update_magic == SD_UPDATE_MAGIC) {
run_command("env default -a", 0);
ret = _storage_update_rtos(sd_dl);
} else if (update_magic == USB_UPDATE_MAGIC) {
run_command("env default -a", 0);
usb_pid = in_be32(UBOOT_PID_SRAM_ADDR);
usb_pid = bcd2hex4(usb_pid);
ret = _usb_update_rtos(usb_pid);
}
} else {
printf("Usage:\n%s\n", cmdtp->usage);
}
return ret;
}
U_BOOT_CMD(cvi_update_rtos, 2, 0, do_cvi_update_rtos,
"cvi_update_rtos [eth, sd, usb]- check boot status and update if necessary\n",
"run cvi_update without parameter will check the boot status and try to update"
);

25
u-boot-2021.10/cmd/load.c
View File

@ -453,19 +453,6 @@ static int do_load_serial_bin(struct cmd_tbl *cmdtp, int flag, int argc,
load_baudrate = current_baudrate;
}
if (load_baudrate != current_baudrate) {
printf("## Switch baudrate to %d bps and press ENTER ...\n",
load_baudrate);
udelay(50000);
gd->baudrate = load_baudrate;
serial_setbrg();
udelay(50000);
for (;;) {
if (getchar() == '\r')
break;
}
}
if (strcmp(argv[0],"loady")==0) {
printf("## Ready for binary (ymodem) download "
"to 0x%08lX at %d bps...\n",
@ -499,18 +486,6 @@ static int do_load_serial_bin(struct cmd_tbl *cmdtp, int flag, int argc,
image_load_addr = addr;
}
}
if (load_baudrate != current_baudrate) {
printf("## Switch baudrate to %d bps and press ESC ...\n",
current_baudrate);
udelay(50000);
gd->baudrate = current_baudrate;
serial_setbrg();
udelay(50000);
for (;;) {
if (getchar() == 0x1B) /* ESC */
break;
}
}
return rcode;
}

145
u-boot-2021.10/drivers/mtd/nand/raw/cvitek/cvsnfc_spi_ids.c
View File

@ -171,6 +171,55 @@ static struct spi_nand_driver spi_nand_driver_mxic = {
#define SPI_NAND_ID_TAB_VER "1.3"
struct cvsnfc_chip_info cvsnfc_spi_nand_flash_table[] = {
{
.name = "GSS01GSAK1",
.id = {0x52, 0xba, 0x13},
.id_len = 3,
.chipsize = _128M,
.erasesize = _128K,
.pagesize = _2K,
.oobsize = 64,
.badblock_pos = BBP_FIRST_PAGE,
.driver = &spi_nand_driver_toshiba,
.flags = FLAGS_ENABLE_X2_BIT | FLAGS_ENABLE_X4_BIT,
.ecc_en_feature_offset = 0xb0, /* Configuration register */
.ecc_en_mask = 1 << 4, /* bit 4 */
.ecc_status_offset = 0xc0, /* Status register */
.ecc_status_mask = 0x30, /* bit 4 & 5 */
.ecc_status_shift = 4,
.ecc_status_uncorr_val = 0x2,
.sck_l = 1,
.sck_h = 0,
.max_freq = SPI_NAND_FREQ_62MHz,
.sample_param = 0x40001000,
.xtal_switch = 1,
},
{
.name = "GSS02GSAK1",
.id = {0x52, 0xba, 0x23},
.id_len = 3,
.chipsize = _256M,
.erasesize = _128K,
.pagesize = _2K,
.oobsize = 128,
.badblock_pos = BBP_FIRST_PAGE,
.driver = &spi_nand_driver_toshiba,
.flags = FLAGS_ENABLE_X2_BIT | FLAGS_ENABLE_X4_BIT,
.ecc_en_feature_offset = 0xb0, /* Configuration register */
.ecc_en_mask = 1 << 4, /* bit 4 */
.ecc_status_offset = 0xc0, /* Status register */
.ecc_status_mask = 0x30, /* bit 4 & 5 */
.ecc_status_shift = 4,
.ecc_status_uncorr_val = 0x2,
.sck_l = 1,
.sck_h = 0,
.max_freq = SPI_NAND_FREQ_62MHz,
.sample_param = 0x40001000,
.xtal_switch = 1,
},
/* ESMT F50L1G41LB 1Gbit */
{
@ -1331,6 +1380,102 @@ struct cvsnfc_chip_info cvsnfc_spi_nand_flash_table[] = {
.xtal_switch = 1,
},
{
.name = "FM25S01A",
.id = {0xA1, 0xE4},
.id_len = 2,
.chipsize = _128M,
.erasesize = _128K,
.pagesize = _2K,
.oobsize = 64,
.badblock_pos = BBP_FIRST_PAGE,
.driver = &spi_nand_driver_gd,
.flags = FLAGS_SET_QE_BIT | FLAGS_ENABLE_X2_BIT | FLAGS_ENABLE_X4_BIT,
.ecc_en_feature_offset = 0xb0, /* Configuration register */
.ecc_en_mask = 1 << 4, /* bit 4 */
.ecc_status_offset = 0xc0, /* Status register */
.ecc_status_mask = 0x30, /* bit 4 & 5 */
.ecc_status_shift = 4,
.ecc_status_uncorr_val = 0x2,
.sck_l = 1,
.sck_h = 1,
.max_freq = SPI_NAND_FREQ_62MHz,
.sample_param = 0x40001000,
.xtal_switch = 1,
},
{
.name = "FM25S02A",
.id = {0xA1, 0xE5},
.id_len = 2,
.chipsize = _256M,
.erasesize = _128K,
.pagesize = _2K,
.oobsize = 64,
.badblock_pos = BBP_FIRST_PAGE,
.driver = &spi_nand_driver_gd,
.flags = FLAGS_SET_QE_BIT | FLAGS_ENABLE_X2_BIT | FLAGS_ENABLE_X4_BIT,
.ecc_en_feature_offset = 0xb0, /* Configuration register */
.ecc_en_mask = 1 << 4, /* bit 4 */
.ecc_status_offset = 0xc0, /* Status register */
.ecc_status_mask = 0x30, /* bit 4 & 5 */
.ecc_status_shift = 4,
.ecc_status_uncorr_val = 0x2,
.sck_l = 1,
.sck_h = 1,
.max_freq = SPI_NAND_FREQ_62MHz,
.sample_param = 0x40001000,
.xtal_switch = 1,
},
{
.name = "FM25S01B",
.id = {0xA1, 0xD4},
.id_len = 2,
.chipsize = _128M,
.erasesize = _128K,
.pagesize = _2K,
.oobsize = 128,
.badblock_pos = BBP_FIRST_PAGE,
.driver = &spi_nand_driver_gd,
.flags = FLAGS_SET_QE_BIT | FLAGS_ENABLE_X2_BIT | FLAGS_ENABLE_X4_BIT,
.ecc_en_feature_offset = 0xb0, /* Configuration register */
.ecc_en_mask = 1 << 4, /* bit 4 */
.ecc_status_offset = 0xc0, /* Status register */
.ecc_status_mask = 0x70, /* bit 4 & 5 */
.ecc_status_shift = 4,
.ecc_status_uncorr_val = 0x2,
.sck_l = 1,
.sck_h = 1,
.max_freq = SPI_NAND_FREQ_62MHz,
.sample_param = 0x40001000,
.xtal_switch = 1,
},
{
.name = "F35SQA512M",
.id = {0xcd, 0x70, 0x70},
.id_len = 3,
.chipsize = _64M,
.erasesize = _128K,
.pagesize = _2K,
.oobsize = 64,
.badblock_pos = BBP_FIRST_PAGE,
.driver = &spi_nand_driver_gd,
.flags = FLAGS_SET_QE_BIT | FLAGS_ENABLE_X2_BIT | FLAGS_ENABLE_X4_BIT,
.ecc_en_feature_offset = 0xb0, /* Configuration register */
.ecc_en_mask = 1 << 4, /* bit 4 */
.ecc_status_offset = 0xc0, /* Status register */
.ecc_status_mask = 0x30, /* bit 4 & 5 */
.ecc_status_shift = 4,
.ecc_status_uncorr_val = 0x2,
.sck_l = 1,
.sck_h = 1,
.max_freq = SPI_NAND_FREQ_62MHz,
.sample_param = 0x40001000,
.xtal_switch = 1,
},
{ .id_len = 0, },
};

4
u-boot-2021.10/drivers/mtd/spi/spi-nor-core.c
View File

@ -2754,6 +2754,10 @@ static int spi_nor_init_params(struct spi_nor *nor,
case SNOR_MFR_JUYANG:
case SNOR_MFR_ZBIT:
case SNOR_MFR_XMC:
if (info->id[1] == 0x60) {
params->quad_enable = quad_enable_SR_bit6;
break;
}
case SNOR_MFR_XTX:
case SNOR_MFR_FM:
case SNOR_MFR_SPANSION:

6
u-boot-2021.10/drivers/mtd/spi/spi-nor-ids.c
View File

@ -101,6 +101,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_QUAD_READ | SECT_4K) },
{ INFO("XM25QH256C", 0x204019, 0x0, 64 * 1024, 512,
SPI_NOR_QUAD_READ | SECT_4K | SPI_NOR_4B_OPCODES) },
{ INFO("XM25QH256B", 0x206019, 0x0, 64 * 1024, 512,
SPI_NOR_QUAD_READ | SECT_4K | SPI_NOR_4B_OPCODES) },
// N25Q256 N25L256
{ INFO("N25Q256", 0x20ba19, 0x0, 64 * 1024, 512,
SPI_NOR_QUAD_READ | SECT_4K) },
@ -132,12 +134,16 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_QUAD_READ | SECT_4K) },
{ INFO("FM25W128", 0xA12818, 0x0, 64 * 1024, 256,
SPI_NOR_QUAD_READ | SECT_4K) },
{ INFO("BY25Q64ES", 0x684017, 0x0, 64 * 1024, 128,
SPI_NOR_QUAD_READ | SECT_4K) },
{ INFO("BY25Q128AS", 0x684018, 0x0, 64 * 1024, 256,
SPI_NOR_QUAD_READ | SECT_4K) },
{ INFO("BY25Q256FS", 0x684919, 0x0, 64 * 1024, 512,
SPI_NOR_QUAD_READ | SECT_4K | SPI_NOR_4B_OPCODES) },
{ INFO("PY25Q128HA", 0x852018, 0x0, 64 * 1024, 256,
SPI_NOR_QUAD_READ | SECT_4K) },
{ INFO("PY25Q64HA", 0x852017, 0x0, 64 * 1024, 128,
SPI_NOR_QUAD_READ | SECT_4K) },
{ INFO("P25Q64SH", 0x856017, 0x0, 64 * 1024, 128,
SPI_NOR_QUAD_READ | SECT_4K) },
{ },

8
u-boot-2021.10/include/configs/cv180x-asic.h
View File

@ -295,10 +295,12 @@
UBOOT_VBOOT_BOOTM_COMMAND \
"fi;"
#ifndef CONFIG_SD_BOOT
#define CONFIG_BOOTCOMMAND SHOWLOGOCMD "cvi_update || run norboot || run nandboot ||run emmcboot"
#else
#ifdef CONFIG_ENABLE_ALIOS_UPDATE
#define CONFIG_BOOTCOMMAND "cvi_update_rtos"
#elif CONFIG_SD_BOOT
#define CONFIG_BOOTCOMMAND SHOWLOGOCMD "run sdboot"
#else
#define CONFIG_BOOTCOMMAND SHOWLOGOCMD "cvi_update || run norboot || run nandboot ||run emmcboot"
#endif
#if defined(CONFIG_NAND_SUPPORT)

6
u-boot-2021.10/include/configs/cv181x-asic.h
View File

@ -294,9 +294,11 @@
"if test $? -eq 0; then " \
UBOOT_VBOOT_BOOTM_COMMAND \
"fi;"
#ifdef CONFIG_ENABLE_ALIOS_UPDATE
#define CONFIG_BOOTCOMMAND "cvi_update_rtos"
#else
#define CONFIG_BOOTCOMMAND SHOWLOGOCMD "cvi_update || run norboot || run nandboot ||run emmcboot"
#endif
#if defined(CONFIG_NAND_SUPPORT)
/* For spi nand boot, need to reset DMA and its setting before exiting uboot */
/* 0x4330058 : DMA reset */

19
u-boot-2021.10/include/cvi_update.h
View File

@ -2,6 +2,25 @@
#define __CVI_UPDATE_H__
#define EXTRA_FLAG_SIZE 32
#define COMPARE_STRING_LEN
#define SD_UPDATE_MAGIC 0x4D474E32
#define ETH_UPDATE_MAGIC 0x4D474E35
#define USB_DRIVE_UPGRADE_MAGIC 0x55425355
#define FIP_UPDATE_MAGIC 0x55464950
#define UPDATE_DONE_MAGIC 0x50524F47
#define OTA_MAGIC 0x5245434F
//#define ALWAYS_USB_DRVIVE_UPGRATE
#define SECTOR_SIZE 0x200
#define HEADER_MAGIC "CIMG"
#define MAX_LOADSIZE (16 * 1024 * 1024)
enum chunk_type_e { dont_care = 0, check_crc };
enum storage_type_e { sd_dl = 0, usb_dl };
// UART update defines
#define UART_UPDATE_MAGIC 0x4D474E33
#define UART_DL_BAUDRATE 1500000
#undef pr_debug
#ifdef DEBUG

1
u-boot-2021.10/scripts/config_whitelist.txt
View File

@ -339,6 +339,7 @@ CONFIG_EMMCBOOTCOMMAND
CONFIG_EMMC_SUPPORT
CONFIG_EMU
CONFIG_ENABLE_36BIT_PHYS
CONFIG_ENABLE_ALIOS_UPDATE
CONFIG_ENABLE_MMU
CONFIG_ENABLE_MUST_CHECK
CONFIG_ENV_ADDR_FLEX