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[u-boot] rk33plat: Adjust api rkclk_pll_mode for all pll except dpll enter mode.

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Change-Id: I1ef23d406e3e8ea1b7c562120add4d50f0a04756
Signed-off-by: Firefly <service@t-firefly.com>
(cherry picked from commit a21abdda5e5f5fcada8ac9c9e1b1183c370abac9)
This commit is contained in:
Firefly
2016-03-10 09:20:38 +08:00
committed by cjp
parent 6ad73e40a4
commit a801a3bf70
4 changed files with 19 additions and 20 deletions
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22
u-boot/arch/arm/cpu/armv8/rk33xx/clock-rk3368.c
View File

@ -782,9 +782,21 @@ static uint32 rkclk_get_periph_pclk_div(void)
/*
* rkplat clock set pll mode
*/
void rkclk_pll_mode(int pll_id, int pll_mode)
void rkclk_pll_mode(int pll_mode)
{
rkclk_pll_set_mode(pll_id, pll_mode);
if (pll_mode == RKCLK_PLL_MODE_NORMAL) {
rkclk_pll_set_mode(APLLL_ID, pll_mode);
rkclk_pll_set_mode(APLLB_ID, pll_mode);
rkclk_pll_set_mode(CPLL_ID, pll_mode);
rkclk_pll_set_mode(GPLL_ID, pll_mode);
rkclk_pll_set_mode(NPLL_ID, pll_mode);
} else {
rkclk_pll_set_mode(CPLL_ID, pll_mode);
rkclk_pll_set_mode(GPLL_ID, pll_mode);
rkclk_pll_set_mode(NPLL_ID, pll_mode);
rkclk_pll_set_mode(APLLL_ID, pll_mode);
rkclk_pll_set_mode(APLLB_ID, pll_mode);
}
}
@ -1463,11 +1475,7 @@ void rkclk_set_crypto_clk(uint32 rate)
void rkcru_cpu_soft_reset(void)
{
/* pll enter slow mode */
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(APLLB_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(APLLL_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(GPLL_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(CPLL_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(NPLL_ID, 3));
rkclk_pll_mode(RKCLK_PLL_MODE_SLOW);
/* soft reset */
writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND);

2
u-boot/arch/arm/cpu/armv8/rk33xx/clock.c
View File

@ -101,7 +101,7 @@ static uint32 rkclk_calc_clkdiv(uint32 clk_parent, uint32 clk_child, uint32 even
#else
void rkclk_pll_mode(int pll_id, int pll_mode) {}
void rkclk_pll_mode(int pll_mode) {}
void rkclk_set_pll(void) {}
void rkclk_get_pll(void) {}
void rkclk_dump_pll(void) {}

13
u-boot/arch/arm/cpu/armv8/rk33xx/pm.c
View File

@ -77,22 +77,13 @@ void rk_pm_enter(v_pm_cb_f module_pm_conf)
module_pm_conf(0);
/* pll enter slow mode */
rkclk_pll_mode(CPLL_ID, RKCLK_PLL_MODE_SLOW);
rkclk_pll_mode(GPLL_ID, RKCLK_PLL_MODE_SLOW);
rkclk_pll_mode(NPLL_ID, RKCLK_PLL_MODE_SLOW);
rkclk_pll_mode(APLLL_ID, RKCLK_PLL_MODE_SLOW);
rkclk_pll_mode(APLLB_ID, RKCLK_PLL_MODE_SLOW);
rkclk_pll_mode(RKCLK_PLL_MODE_SLOW);
/* cpu enter wfi mode */
wfi();
/* pll enter nornal mode */
rkclk_pll_mode(APLLB_ID, RKCLK_PLL_MODE_NORMAL);
rkclk_pll_mode(APLLL_ID, RKCLK_PLL_MODE_NORMAL);
rkclk_pll_mode(NPLL_ID, RKCLK_PLL_MODE_NORMAL);
rkclk_pll_mode(GPLL_ID, RKCLK_PLL_MODE_NORMAL);
rkclk_pll_mode(CPLL_ID, RKCLK_PLL_MODE_NORMAL);
rkclk_pll_mode(RKCLK_PLL_MODE_NORMAL);
if (module_pm_conf != NULL)
module_pm_conf(1);

2
u-boot/arch/arm/include/asm/arch-rk33xx/clock.h
View File

@ -23,7 +23,7 @@
/*
* rkplat clock set pll mode
*/
void rkclk_pll_mode(int pll_id, int pll_mode);
void rkclk_pll_mode(int pll_mode);
/*
* rkplat clock set pll rate by id