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Revert "Kernel->clk:always use cpll for lcdc"

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This reverts commit 6cf0f56841c33142cb152df63d2cdaa6d2bc3678.
This commit is contained in:
zouxf
2016-02-29 18:15:42 +08:00
committed by cjp
parent 79c1295b16
commit f642a51e9d
1 changed files with 4 additions and 8 deletions
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12
kernel/drivers/clk/rockchip/clk-ops.c
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@ -610,8 +610,7 @@ static long clk_3288_dclk_lcdc0_determine_rate(struct clk_hw *hw, unsigned long
gpll_rate = __clk_get_rate(gpll);
//if ((rate <= (594 * MHZ)) && (gpll_rate % rate == 0)) {
if (0) {
if ((rate <= (594 * MHZ)) && (gpll_rate % rate == 0)) {
*best_parent_p = gpll;
best = rate;
*best_parent_rate = gpll_rate;
@ -652,8 +651,7 @@ static int clk_3288_dclk_lcdc0_set_rate(struct clk_hw *hw, unsigned long rate,
clk_divider_ops.set_rate(hw, rate, parent_rate);
/* set aclk_vio */
//if (parent_rate == __clk_get_rate(gpll)) {
if (0) {
if (parent_rate == __clk_get_rate(gpll)) {
parent = clk_get(NULL, "clk_gpll");
clk_set_parent(aclk_vio0, gpll);
clk_set_rate(aclk_vio0, 300*MHZ);
@ -694,8 +692,7 @@ static long clk_3288_dclk_lcdc1_determine_rate(struct clk_hw *hw, unsigned long
gpll_rate = __clk_get_rate(gpll);
//if ((rate <= (594 * MHZ)) && ((gpll_rate) % rate == 0)) {
if (0) {
if ((rate <= (594 * MHZ)) && ((gpll_rate) % rate == 0)) {
*best_parent_p = gpll;
best = rate;
*best_parent_rate = gpll_rate;
@ -733,8 +730,7 @@ static int clk_3288_dclk_lcdc1_set_rate(struct clk_hw *hw, unsigned long rate,
clk_divider_ops.set_rate(hw, rate, parent_rate);
/* set aclk_vio */
//if (parent_rate == __clk_get_rate(gpll))
if (0)
if (parent_rate == __clk_get_rate(gpll))
parent = clk_get(NULL, "clk_gpll");
else
parent = clk_get(NULL, "clk_cpll");