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[freertos] add freertos firmware

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Change-Id: I4158d66d9b5fc444e28287f55e79ac24e0a1666f
This commit is contained in:
sam.xiang
2023-02-23 11:39:27 +08:00
parent 1cf39ecdd5
commit cbb030f19f
398 changed files with 151104 additions and 0 deletions
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24
freertos/cvitek/build_cv180x.sh Executable file
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#!/bin/bash
set -e
TOP_DIR="$( cd "$(dirname "$0")" ; pwd -P )"
TOOLCHAIN_FILE_PATH=$TOP_DIR/scripts/toolchain-riscv64-elf.cmake
BUILD_FREERTOS_PATH=$TOP_DIR/build
BUILD_ENV_PATH=$BUILD_PATH
INSTALL_PATH=$TOP_DIR/install
RUN_TYPE=CVIRTOS
RUN_CHIP=cv180x
RUN_ARCH=riscv64
if [ ! -e $BUILD_FREERTOS_PATH/task ]; then
mkdir -p $BUILD_FREERTOS_PATH/task
fi
if [ -f $TOP_DIR/task/isp/libisp.a ]; then
mkdir -p $BUILD_FREERTOS_PATH/task/isp
cp $TOP_DIR/task/isp/libisp.a $BUILD_FREERTOS_PATH/task/isp
cp $TOP_DIR/task/isp/libisp.a $INSTALL_PATH/lib/
fi
pushd $BUILD_FREERTOS_PATH/task
cmake -G Ninja -DCHIP=$RUN_CHIP -DRUN_ARCH=$RUN_ARCH -DRUN_TYPE=$RUN_TYPE -DTOP_DIR=$TOP_DIR -DBUILD_ENV_PATH=$BUILD_ENV_PATH -DBOARD_FPGA=n -DCMAKE_TOOLCHAIN_FILE=$TOOLCHAIN_FILE_PATH $TOP_DIR/task
cmake --build . --target install -- -v
cmake --build . --target cvirtos.bin -- -v
popd
cp $TOP_DIR/install/bin/cvirtos.bin ../cvirtos.bin

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freertos/cvitek/build_cv181x.sh Executable file
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#!/bin/bash
set -e
TOP_DIR="$( cd "$(dirname "$0")" ; pwd -P )"
TOOLCHAIN_FILE_PATH=$TOP_DIR/scripts/toolchain-riscv64-elf.cmake
BUILD_FREERTOS_PATH=$TOP_DIR/build
BUILD_ENV_PATH=$BUILD_PATH
INSTALL_PATH=$TOP_DIR/install
RUN_TYPE=CVIRTOS
RUN_CHIP=cv181x
RUN_ARCH=riscv64
if [ ! -e $BUILD_FREERTOS_PATH/task ]; then
mkdir -p $BUILD_FREERTOS_PATH/task
fi
if [ -f $TOP_DIR/task/isp/libisp.a ]; then
mkdir -p $BUILD_FREERTOS_PATH/task/isp
cp $TOP_DIR/task/isp/libisp.a $BUILD_FREERTOS_PATH/task/isp
cp $TOP_DIR/task/isp/libisp.a $INSTALL_PATH/lib/
fi
pushd $BUILD_FREERTOS_PATH/task
cmake -G Ninja -DCHIP=$RUN_CHIP -DRUN_ARCH=$RUN_ARCH -DRUN_TYPE=$RUN_TYPE -DTOP_DIR=$TOP_DIR -DBUILD_ENV_PATH=$BUILD_ENV_PATH -DBOARD_FPGA=n -DCMAKE_TOOLCHAIN_FILE=$TOOLCHAIN_FILE_PATH $TOP_DIR/task
cmake --build . --target install -- -v
cmake --build . --target cvirtos.bin -- -v
popd
cp $TOP_DIR/install/bin/cvirtos.bin ../cvirtos.bin

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#ifndef __ARCH_CPU__
#define __ARCH_CPU__
#ifdef PXP_PLAT
#define configSYS_CLOCK_HZ ( 1000000000 )
#elif defined RISCV_QEMU
#define configSYS_CLOCK_HZ ( 100000000 )
#elif defined FPGA_PLAT
#define configSYS_CLOCK_HZ ( 25000000 )
#else
#define configSYS_CLOCK_HZ ( 25000000 )
#endif
#endif // end of __ARCH_CPU__

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freertos/cvitek/install/include/arch/arch_helpers.h Normal file
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#ifndef __ARCH_HELPERS_H__
#define __ARCH_HELPERS_H__
#include <stdint.h>
#include <sys/types.h>
void flush_dcache_range(uintptr_t addr, size_t size);
void clean_dcache_range(uintptr_t addr, size_t size);
void inv_dcache_range(uintptr_t addr, size_t size);
void enable_dcache(void);
void disable_dcache(void);
#endif /* __ARCH_HELPERS_H__ */

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#ifndef _ARCH_SLEEP_H
#define _ARCH_SLEEP_H
void arch_usleep(unsigned long useconds);
void arch_nsleep(unsigned long nseconds);
#endif // end of _ARCH_SLEEP_H

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freertos/cvitek/install/include/arch/arch_time.h Normal file
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#ifndef __TIME_L_H__
#define __TIME_L_H__
inline static unsigned long GetSysTime(void)
{
unsigned long sys_tick = 0;
asm volatile("rdtime %0": "=r"(sys_tick));
return sys_tick;
}
#endif

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/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file csi_core.h
* @brief CSI Core Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef _CORE_H_
#define _CORE_H_
#include <stdint.h>
#if defined(__CK801__) || defined(__E801__)
#include <core_801.h>
#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__)
#include <core_802.h>
#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__) || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__)
#include <core_804.h>
#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__)
#include <core_803.h>
#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__)
#include <core_805.h>
#elif defined(__CK610__)
#include <core_ck610.h>
#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__)
#include <core_810.h>
#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__)
#include <core_807.h>
#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM)
#include <core_rv32_old.h>
#elif defined(__riscv)
#include <core_rv64.h>
#endif
#ifdef __riscv
#include <csi_rv64_gcc.h>
#else
#include <csi_gcc.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CORE_H_ */

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// See LICENSE for license details.
#ifndef RISCV_CSR_ENCODING_H
#define RISCV_CSR_ENCODING_H
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
#define MSTATUS_HIE 0x00000004
#define MSTATUS_MIE 0x00000008
#define MSTATUS_UPIE 0x00000010
#define MSTATUS_SPIE 0x00000020
#define MSTATUS_HPIE 0x00000040
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
#define MSTATUS_HPP 0x00000600
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
#define MSTATUS_XS 0x00018000
#define MSTATUS_MPRV 0x00020000
#define MSTATUS_SUM 0x00040000
#define MSTATUS_MXR 0x00080000
#define MSTATUS_TVM 0x00100000
#define MSTATUS_TW 0x00200000
#define MSTATUS_TSR 0x00400000
#define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000
#define MIP_SSIE (1 << IRQ_S_SOFT)
#define MIP_HSIE (1 << IRQ_H_SOFT)
#define MIP_MSIE (1 << IRQ_M_SOFT)
#define MIP_STIE (1 << IRQ_S_TIMER)
#define MIP_HTIE (1 << IRQ_H_TIMER)
#define MIP_MTIE (1 << IRQ_M_TIMER)
#define MIP_SEIE (1 << IRQ_S_EXT)
#define MIP_HEIE (1 << IRQ_H_EXT)
#define MIP_MEIE (1 << IRQ_M_EXT)
#define IRQ_S_SOFT 1
#define IRQ_H_SOFT 2
#define IRQ_M_SOFT 3
#define IRQ_S_TIMER 5
#define IRQ_H_TIMER 6
#define IRQ_M_TIMER 7
#define IRQ_S_EXT 9
#define IRQ_H_EXT 10
#define IRQ_M_EXT 11
#define IRQ_COP 12
#define IRQ_HOST 13
# define MAX_HARTS 1
#ifndef __ASSEMBLER__
#ifdef __GNUC__
#define read_csr(reg) ({ unsigned long __tmp; \
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; })
#define write_csr(reg, val) ({ \
asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
#define swap_csr(reg, val) ({ unsigned long __tmp; \
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
__tmp; })
#define set_csr(reg, bit) ({ unsigned long __tmp; \
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
__tmp; })
#define clear_csr(reg, bit) ({ unsigned long __tmp; \
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
__tmp; })
#define rdtime() read_csr(time)
#define rdcycle() read_csr(cycle)
#define rdinstret() read_csr(instret)
#endif
#endif
#endif

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/*
* Based on arch/arm/include/asm/io.h
*
* Copyright (C) 1996-2000 Russell King
* Copyright (C) 2012 ARM Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ASM_IO_H
#define __ASM_IO_H
/*
* I/O memory access primitives. Reads are ordered relative to any
* following Normal memory access. Writes are ordered relative to any prior
* Normal memory access.
*/
#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
#define writeb(v, c) ({ __iowmb(); writeb_relaxed((v), (c)); })
#define writew(v, c) ({ __iowmb(); writew_relaxed((v), (c)); })
#define writel(v, c) ({ __iowmb(); writel_relaxed((v), (c)); })
#define writeq(v, c) ({ __iowmb(); writeq_relaxed((v), (c)); })
#define ioread8 readb
#define ioread16 readw
#define ioread32 readl
#define ioread64 readq
#define iowrite8 writeb
#define iowrite16 writew
#define iowrite32 writel
#define iowrite64 writeq
#endif /* __ASM_IO_H */

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#ifndef __IRQ__
#define __IRQ__
#if 0
// IRQ API
typedef int (*irq_handler_t)(int irqn, void *priv);
extern int request_irq(unsigned int irqn, irq_handler_t handler, unsigned long flags,
const char *name, void *priv);
void disable_irq(unsigned int irqn);
void enable_irq(unsigned int irqn);
void cpu_enable_irqs(void);
void cpu_disable_irqs(void);
#endif
/* RISC-V */
#define CLINT_BASE 0x74000000
#define PLIC_BASE 0x70000000
/* CLINT */
#define CLINT_TIMECMPL0 (CLINT_BASE + 0x4000)
#define CLINT_TIMECMPH0 (CLINT_BASE + 0x4004)
#define CLINT_MTIME(cnt) asm volatile("csrr %0, time\n" : "=r"(cnt) :: "memory");
/* PLIC */
#define PLIC_PRIORITY0 (PLIC_BASE + 0x0)
#define PLIC_PRIORITY1 (PLIC_BASE + 0x4)
#define PLIC_PRIORITY2 (PLIC_BASE + 0x8)
#define PLIC_PRIORITY3 (PLIC_BASE + 0xc)
#define PLIC_PRIORITY4 (PLIC_BASE + 0x10)
#define PLIC_PENDING1 (PLIC_BASE + 0x1000)
#define PLIC_PENDING2 (PLIC_BASE + 0x1004)
#define PLIC_PENDING3 (PLIC_BASE + 0x1008)
#define PLIC_PENDING4 (PLIC_BASE + 0x100C)
#define PLIC_ENABLE1 (PLIC_BASE + 0x2000)
#define PLIC_ENABLE2 (PLIC_BASE + 0x2004)
#define PLIC_ENABLE3 (PLIC_BASE + 0x2008)
#define PLIC_ENABLE4 (PLIC_BASE + 0x200C)
#define PLIC_THRESHOLD (PLIC_BASE + 0x200000)
#define PLIC_CLAIM (PLIC_BASE + 0x200004)
#endif

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/*
* Copyright (c) 2017 Microsemi Corporation.
* Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_RISCV_PTRACE_H
#define __ASM_RISCV_PTRACE_H
struct pt_regs {
unsigned long sepc;
unsigned long ra;
unsigned long sp;
unsigned long gp;
unsigned long tp;
unsigned long t0;
unsigned long t1;
unsigned long t2;
unsigned long s0;
unsigned long s1;
unsigned long a0;
unsigned long a1;
unsigned long a2;
unsigned long a3;
unsigned long a4;
unsigned long a5;
unsigned long a6;
unsigned long a7;
unsigned long s2;
unsigned long s3;
unsigned long s4;
unsigned long s5;
unsigned long s6;
unsigned long s7;
unsigned long s8;
unsigned long s9;
unsigned long s10;
unsigned long s11;
unsigned long t3;
unsigned long t4;
unsigned long t5;
unsigned long t6;
/* Supervisor CSRs */
unsigned long sstatus;
unsigned long sbadaddr;
unsigned long scause;
};
#ifdef CONFIG_64BIT
#define REG_FMT "%016lx"
#else
#define REG_FMT "%08lx"
#endif
#define user_mode(regs) (((regs)->sstatus & SR_PS) == 0)
/* Helpers for working with the instruction pointer */
#define GET_IP(regs) ((regs)->sepc)
#define SET_IP(regs, val) (GET_IP(regs) = (val))
static inline unsigned long instruction_pointer(struct pt_regs *regs)
{
return GET_IP(regs);
}
static inline void instruction_pointer_set(struct pt_regs *regs,
unsigned long val)
{
SET_IP(regs, val);
}
#define profile_pc(regs) instruction_pointer(regs)
/* Helpers for working with the user stack pointer */
#define GET_USP(regs) ((regs)->sp)
#define SET_USP(regs, val) (GET_USP(regs) = (val))
static inline unsigned long user_stack_pointer(struct pt_regs *regs)
{
return GET_USP(regs);
}
static inline void user_stack_pointer_set(struct pt_regs *regs,
unsigned long val)
{
SET_USP(regs, val);
}
/* Helpers for working with the frame pointer */
#define GET_FP(regs) ((regs)->s0)
#define SET_FP(regs, val) (GET_FP(regs) = (val))
static inline unsigned long frame_pointer(struct pt_regs *regs)
{
return GET_FP(regs);
}
static inline void frame_pointer_set(struct pt_regs *regs,
unsigned long val)
{
SET_FP(regs, val);
}
#endif /* __ASM_RISCV_PTRACE_H */

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/*
* FreeRTOS V202107.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://www.github.com/FreeRTOS
*
* 1 tab == 4 spaces!
*/
#ifndef RISCV_REG_H_
#define RISCV_REG_H_
#if __riscv_xlen == 32
#define REGSIZE 4
#define REGSHIFT 2
#define LOAD lw
#define STOR sw
#elif __riscv_xlen == 64
#define REGSIZE 8
#define REGSHIFT 3
#define LOAD ld
#define STOR sd
#endif /* __riscv_xlen */
#endif /* RISCV_REG_H_ */

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/*
* FreeRTOS V202107.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://www.github.com/FreeRTOS
*
* 1 tab == 4 spaces!
*/
#ifndef RISCV_VIRT_H_
#define RISCV_VIRT_H_
#include "riscv-reg.h"
#ifdef __ASSEMBLER__
#define CONS(NUM, TYPE)NUM
#else
#define CONS(NUM, TYPE)NUM##TYPE
#endif /* __ASSEMBLER__ */
#define PRIM_HART 0
#ifdef RISCV_QEMU
#define CLINT_ADDR CONS(0x02000000, UL)
#define CLINT_MSIP CONS(0x0000, UL)
#define CLINT_MTIMECMP CONS(0x4000, UL)
#define CLINT_MTIME CONS(0xbff8, UL)
#else
#define CLINT_ADDR CONS(0x74000000, UL)
#define CLINT_MSIP CONS(0x0000, UL)
#define CLINT_MTIMECMP CONS(0x4000, UL)
#undef CLINT_MTIME
//#define CLINT_MTIME CONS(0x4004, UL)
#endif
//#define NS16550_ADDR CONS(0x10000000, UL)
#ifndef __ASSEMBLER__
int xGetCoreID( void );
#endif /* __ASSEMBLER__ */
#endif /* RISCV_VIRT_H_ */

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#ifndef _U_CIF_UAPI_H_
#define _U_CIF_UAPI_H_
#define MIPI_LANE_NUM 4
#define HDR_VC_NUM 2
#define SYNC_CODE_NUM 4
#define BT_DEMUX_NUM 4
#define MIPI_DEMUX_NUM 4
struct img_size_s {
unsigned int x; // start x
unsigned int y; // start y
unsigned int width;
unsigned int height;
};
enum rx_mac_clk_e {
RX_MAC_CLK_200M = 0,
RX_MAC_CLK_300M,
RX_MAC_CLK_400M,
RX_MAC_CLK_500M,
RX_MAC_CLK_600M,
RX_MAC_CLK_BUTT,
};
enum cam_pll_freq_e {
CAMPLL_FREQ_NONE = 0,
CAMPLL_FREQ_37P125M,
CAMPLL_FREQ_25M,
CAMPLL_FREQ_27M,
CAMPLL_FREQ_24M,
CAMPLL_FREQ_26M,
CAMPLL_FREQ_NUM
};
struct mclk_pll_s {
unsigned int cam;
enum cam_pll_freq_e freq;
};
struct dphy_s {
unsigned char enable;
unsigned char hs_settle;
};
enum lane_divide_mode_e {
LANE_DIVIDE_MODE_0 = 0,
LANE_DIVIDE_MODE_1,
LANE_DIVIDE_MODE_2,
LANE_DIVIDE_MODE_3,
LANE_DIVIDE_MODE_4,
LANE_DIVIDE_MODE_5,
LANE_DIVIDE_MODE_6,
LANE_DIVIDE_MODE_7,
LANE_DIVIDE_MODE_BUTT
};
enum input_mode_e {
INPUT_MODE_MIPI = 0,
INPUT_MODE_SUBLVDS,
INPUT_MODE_HISPI,
INPUT_MODE_CMOS,
INPUT_MODE_BT1120,
INPUT_MODE_BT601_19B_VHS,
INPUT_MODE_BT656_9B,
INPUT_MODE_CUSTOM_0,
INPUT_MODE_BT_DEMUX,
INPUT_MODE_BUTT
};
enum raw_data_type_e {
RAW_DATA_8BIT = 0,
RAW_DATA_10BIT,
RAW_DATA_12BIT,
YUV422_8BIT, /* MIPI-CSI only */
YUV422_10BIT, /* MIPI-CSI only*/
RAW_DATA_BUTT
};
enum mipi_hdr_mode_e {
CVI_MIPI_HDR_MODE_NONE = 0,
CVI_MIPI_HDR_MODE_VC,
CVI_MIPI_HDR_MODE_DT,
CVI_MIPI_HDR_MODE_DOL,
CVI_MIPI_HDR_MODE_MANUAL, /* SOI case */
CVI_MIPI_HDR_MODE_BUTT
};
enum hdr_mode_e {
CVI_HDR_MODE_NONE = 0,
CVI_HDR_MODE_2F,
CVI_HDR_MODE_3F,
CVI_HDR_MODE_DOL_2F,
CVI_HDR_MODE_DOL_3F,
CVI_HDR_MODE_DOL_BUTT
};
enum lvds_sync_mode_e {
LVDS_SYNC_MODE_SOF = 0,
LVDS_SYNC_MODE_SAV,
LVDS_SYNC_MODE_BUTT
};
enum lvds_bit_endian {
LVDS_ENDIAN_LITTLE = 0,
LVDS_ENDIAN_BIG,
LVDS_ENDIAN_BUTT
};
enum lvds_vsync_type_e {
LVDS_VSYNC_NORMAL = 0,
LVDS_VSYNC_SHARE,
LVDS_VSYNC_HCONNECT,
LVDS_VSYNC_BUTT
};
enum lvds_fid_type_e {
LVDS_FID_NONE = 0,
LVDS_FID_IN_SAV,
LVDS_FID_BUTT
};
struct lvds_fid_type_s {
enum lvds_fid_type_e fid;
};
struct lvds_vsync_type_s {
enum lvds_vsync_type_e sync_type;
unsigned short hblank1;
unsigned short hblank2;
};
struct lvds_dev_attr_s {
enum hdr_mode_e hdr_mode;
enum lvds_sync_mode_e sync_mode;
enum raw_data_type_e raw_data_type;
enum lvds_bit_endian data_endian;
enum lvds_bit_endian sync_code_endian;
short lane_id[MIPI_LANE_NUM+1];
short sync_code[MIPI_LANE_NUM][HDR_VC_NUM+1][SYNC_CODE_NUM];
/*
* sublvds:
* sync_code[x][0][0] sync_code[x][0][1] sync_code[x][0][2] sync_code[x][0][3]
* n0_lef_sav n0_lef_eav n1_lef_sav n1_lef_eav
* sync_code[x][1][0] sync_code[x][1][1] sync_code[x][1][2] sync_code[x][1][3]
* n0_sef_sav n0_sef_eav n1_sef_sav n1_sef_eav
* sync_code[x][2][0] sync_code[x][2][1] sync_code[x][2][2] sync_code[x][2][3]
* n0_lsef_sav n0_lsef_eav n1_lsef_sav n1_lsef_eav
*
* hispi:
* sync_code[x][0][0] sync_code[x][0][1] sync_code[x][0][2] sync_code[x][0][3]
* t1_sol tl_eol t1_sof t1_eof
* sync_code[x][1][0] sync_code[x][1][1] sync_code[x][1][2] sync_code[x][1][3]
* t2_sol t2_eol t2_sof t2_eof
*/
struct lvds_vsync_type_s vsync_type;
struct lvds_fid_type_s fid_type;
char pn_swap[MIPI_LANE_NUM+1];
};
struct mipi_demux_info_s {
unsigned int demux_en;
unsigned char vc_mapping[MIPI_DEMUX_NUM];
};
struct mipi_dev_attr_s {
enum raw_data_type_e raw_data_type;
short lane_id[MIPI_LANE_NUM+1];
enum mipi_hdr_mode_e hdr_mode;
short data_type[HDR_VC_NUM];
char pn_swap[MIPI_LANE_NUM+1];
struct dphy_s dphy;
struct mipi_demux_info_s demux;
};
struct manual_hdr_attr_s {
unsigned int manual_en;
unsigned short l2s_distance;
unsigned short lsef_length;
unsigned int discard_padding_lines;
unsigned int update;
};
enum ttl_pin_func_e {
TTL_PIN_FUNC_VS,
TTL_PIN_FUNC_HS,
TTL_PIN_FUNC_VDE,
TTL_PIN_FUNC_HDE,
TTL_PIN_FUNC_D0,
TTL_PIN_FUNC_D1,
TTL_PIN_FUNC_D2,
TTL_PIN_FUNC_D3,
TTL_PIN_FUNC_D4,
TTL_PIN_FUNC_D5,
TTL_PIN_FUNC_D6,
TTL_PIN_FUNC_D7,
TTL_PIN_FUNC_D8,
TTL_PIN_FUNC_D9,
TTL_PIN_FUNC_D10,
TTL_PIN_FUNC_D11,
TTL_PIN_FUNC_D12,
TTL_PIN_FUNC_D13,
TTL_PIN_FUNC_D14,
TTL_PIN_FUNC_D15,
TTL_PIN_FUNC_NUM,
};
enum ttl_src_e {
TTL_VI_SRC_VI0 = 0,
TTL_VI_SRC_VI1,
TTL_VI_SRC_VI2, /* BT demux */
TTL_VI_SRC_NUM
};
enum bt_demux_mode_e {
BT_DEMUX_DISABLE = 0,
BT_DEMUX_2,
BT_DEMUX_3,
BT_DEMUX_4,
};
struct bt_demux_sync_s {
unsigned char sav_vld;
unsigned char sav_blk;
unsigned char eav_vld;
unsigned char eav_blk;
};
struct bt_demux_attr_s {
signed char func[TTL_PIN_FUNC_NUM];
unsigned short v_fp;
unsigned short h_fp;
unsigned short v_bp;
unsigned short h_bp;
enum bt_demux_mode_e mode;
unsigned char sync_code_part_A[3]; /* sync code 0~2 */
struct bt_demux_sync_s sync_code_part_B[BT_DEMUX_NUM]; /* sync code 3 */
char yc_exchg;
};
struct ttl_dev_attr_s {
enum ttl_src_e vi;
signed char func[TTL_PIN_FUNC_NUM];
unsigned short v_bp;
unsigned short h_bp;
};
struct combo_dev_attr_s {
enum input_mode_e input_mode;
enum rx_mac_clk_e mac_clk;
struct mclk_pll_s mclk;
union {
struct mipi_dev_attr_s mipi_attr;
struct lvds_dev_attr_s lvds_attr;
struct ttl_dev_attr_s ttl_attr;
struct bt_demux_attr_s bt_demux_attr;
};
unsigned int devno;
struct img_size_s img_size;
struct manual_hdr_attr_s hdr_manu;
};
enum clk_edge_e {
CLK_UP_EDGE = 0,
CLK_DOWN_EDGE,
CLK_EDGE_BUTT
};
struct clk_edge_s {
unsigned int devno;
enum clk_edge_e edge;
};
enum output_msb_e {
OUTPUT_NORM_MSB = 0,
OUTPUT_REVERSE_MSB,
OUTPUT_MSB_BUTT
};
struct msb_s {
unsigned int devno;
enum output_msb_e msb;
};
struct crop_top_s {
unsigned int devno;
unsigned int crop_top;
unsigned int update;
};
struct manual_hdr_s {
unsigned int devno;
struct manual_hdr_attr_s attr;
};
struct vsync_gen_s {
unsigned int devno;
unsigned int distance_fp;
};
enum bt_fmt_out_e {
BT_FMT_OUT_CBYCRY,
BT_FMT_OUT_CRYCBY,
BT_FMT_OUT_YCBYCR,
BT_FMT_OUT_YCRYCB,
};
struct bt_fmt_out_s {
unsigned int devno;
enum bt_fmt_out_e fmt_out;
};
struct cif_crop_win_s {
unsigned int devno;
unsigned int enable;
unsigned int x;
unsigned int y;
unsigned int w;
unsigned int h;
};
struct cif_attr_s {
unsigned int devno;
unsigned int stagger_vsync;
};
#define IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */
#define IOC_VOID 0x20000000 /* no parameters */
#define IOC_OUT 0x40000000 /* copy out parameters */
#define IOC_IN 0x80000000 /* copy in parameters */
#define IOC_INOUT (IOC_IN|IOC_OUT)
#define _IO(x, y) (IOC_VOID|((x)<<8)|(y))
#define _IOR(x, y, t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
#define _IOW(x, y, t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
/* mipi_rx ioctl commands related definition */
#define CVI_MIPI_IOC_MAGIC 'm'
/* Support commands */
#define CVI_MIPI_SET_DEV_ATTR _IOW(CVI_MIPI_IOC_MAGIC, \
0x01, struct combo_dev_attr_s)
#define CVI_MIPI_SET_OUTPUT_CLK_EDGE _IOW(CVI_MIPI_IOC_MAGIC, \
0x02, struct clk_edge_s)
#define CVI_MIPI_RESET_SENSOR _IOW(CVI_MIPI_IOC_MAGIC, \
0x05, unsigned int)
#define CVI_MIPI_UNRESET_SENSOR _IOW(CVI_MIPI_IOC_MAGIC, \
0x06, unsigned int)
#define CVI_MIPI_RESET_MIPI _IOW(CVI_MIPI_IOC_MAGIC, \
0x07, unsigned int)
#define CVI_MIPI_ENABLE_SENSOR_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
0x10, unsigned int)
#define CVI_MIPI_DISABLE_SENSOR_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
0x11, unsigned int)
#define CVI_MIPI_SET_CROP_TOP _IOW(CVI_MIPI_IOC_MAGIC, \
0x20, struct crop_top_s)
#define CVI_MIPI_SET_HDR_MANUAL _IOW(CVI_MIPI_IOC_MAGIC, \
0x21, struct manual_hdr_s)
#define CVI_MIPI_SET_LVDS_FP_VS _IOW(CVI_MIPI_IOC_MAGIC, \
0x22, struct vsync_gen_s)
#define CVI_MIPI_SET_HS_MODE _IOW(CVI_MIPI_IOC_MAGIC, \
0x0B, unsigned int)
#define CVI_MIPI_RESET_LVDS _IOW(CVI_MIPI_IOC_MAGIC, \
0x23, unsigned int)
#define CVI_MIPI_SET_BT_FMT_OUT _IOW(CVI_MIPI_IOC_MAGIC, \
0x24, struct bt_fmt_out_s)
#define CVI_MIPI_GET_CIF_ATTR _IOR(CVI_MIPI_IOC_MAGIC, \
0x25, struct cif_attr_s)
#define CVI_MIPI_SET_SENSOR_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
0x26, struct mclk_pll_s)
#define CVI_MIPI_SET_MAX_MAC_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
0x27, unsigned int)
#define CVI_MIPI_SET_CROP_WINDOW _IOW(CVI_MIPI_IOC_MAGIC, \
0x28, struct cif_crop_win_s)
/* Unsupport commands */
#define CVI_MIPI_SET_PHY_CMVMODE _IOW(CVI_MIPI_IOC_MAGIC, \
0x04, unsigned int)
#define CVI_MIPI_UNRESET_MIPI _IOW(CVI_MIPI_IOC_MAGIC, \
0x08, unsigned int)
#define CVI_MIPI_RESET_SLVS _IOW(CVI_MIPI_IOC_MAGIC, \
0x09, unsigned int)
#define CVI_MIPI_UNRESET_SLVS _IOW(CVI_MIPI_IOC_MAGIC, \
0x0A, unsigned int)
#define CVI_MIPI_ENABLE_MIPI_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
0x0C, unsigned int)
#define CVI_MIPI_DISABLE_MIPI_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
0x0D, unsigned int)
#define CVI_MIPI_ENABLE_SLVS_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
0x0E, unsigned int)
#define CVI_MIPI_DISABLE_SLVS_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
0x0F, unsigned int)
/* Functions */
extern int cif_open(void *param);
extern int cif_release(void);
extern long cif_ioctl(uint32_t devno, unsigned int cmd, unsigned long arg);
#endif // _U_CVI_VIP_CIF_H_

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
*
* File Name: include/cvi_ae.h
* Description:
*/
#ifndef __CVI_AE_H__
#define __CVI_AE_H__
#include "cvi_comm_isp.h"
#include "cvi_comm_3a.h"
#include "cvi_ae_comm.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
typedef enum _AE_EXPOSURE_PROGRAM {
MANUAL_PROGRAM = 1,
NORMAL_PROGRAM,
APERATURE_PRIORITY_PROGRAM,
SHUTTER_PRIORITY_PROGRAM,
SLOW_SHUTTER_PROGRAM,
FAST_SHUTTER_PROGRAM,
PORTRAIT_PROGRAM,
LANDSCAPE_PROGRAM,
} AE_EXPOSURE_PROGRAM;
typedef enum _AE_EXPOSURE_MODE {
AUTO_MODE,
MANUAL_MODE,
} AE_EXPOSURE_MODE;
/* The interface of ae lib register to isp. */
CVI_S32 CVI_AE_Register(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib);
CVI_S32 CVI_AE_UnRegister(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib);
/* The callback function of sensor register to ae lib. */
CVI_S32 CVI_AE_SensorRegCallBack(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ISP_SNS_ATTR_INFO_S *pstSnsAttrInfo,
AE_SENSOR_REGISTER_S *pstRegister);
CVI_S32 CVI_AE_SensorUnRegCallBack(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, SENSOR_ID SensorId);
CVI_S32 CVI_ISP_SetExposureAttr(VI_PIPE ViPipe, const ISP_EXPOSURE_ATTR_S *pstExpAttr);
CVI_S32 CVI_ISP_GetExposureAttr(VI_PIPE ViPipe, ISP_EXPOSURE_ATTR_S *pstExpAttr);
CVI_S32 CVI_ISP_QueryExposureInfo(VI_PIPE ViPipe, ISP_EXP_INFO_S *pstExpInfo);
CVI_S32 CVI_ISP_SetWDRExposureAttr(VI_PIPE ViPipe, const ISP_WDR_EXPOSURE_ATTR_S *pstWDRExpAttr);
CVI_S32 CVI_ISP_GetWDRExposureAttr(VI_PIPE ViPipe, ISP_WDR_EXPOSURE_ATTR_S *pstWDRExpAttr);
CVI_S32 CVI_ISP_SetAERouteAttr(VI_PIPE ViPipe, const ISP_AE_ROUTE_S *pstAERouteAttr);
CVI_S32 CVI_ISP_GetAERouteAttr(VI_PIPE ViPipe, ISP_AE_ROUTE_S *pstAERouteAttr);
CVI_S32 CVI_ISP_SetAERouteAttrEx(VI_PIPE ViPipe, const ISP_AE_ROUTE_EX_S *pstAERouteAttrEx);
CVI_S32 CVI_ISP_GetAERouteAttrEx(VI_PIPE ViPipe, ISP_AE_ROUTE_EX_S *pstAERouteAttrEx);
CVI_S32 CVI_ISP_SetSmartExposureAttr(VI_PIPE ViPipe, const ISP_SMART_EXPOSURE_ATTR_S *pstSmartExpAttr);
CVI_S32 CVI_ISP_GetSmartExposureAttr(VI_PIPE ViPipe, ISP_SMART_EXPOSURE_ATTR_S *pstSmartExpAttr);
CVI_S32 CVI_ISP_SetAEStatisticsConfig(VI_PIPE ViPipe, const ISP_AE_STATISTICS_CFG_S *pstAeStatCfg);
CVI_S32 CVI_ISP_GetAEStatisticsConfig(VI_PIPE ViPipe, ISP_AE_STATISTICS_CFG_S *pstAeStatCfg);
CVI_S32 CVI_ISP_SetAERouteSFAttr(VI_PIPE ViPipe, const ISP_AE_ROUTE_S *pstAERouteSFAttr);
CVI_S32 CVI_ISP_GetAERouteSFAttr(VI_PIPE ViPipe, ISP_AE_ROUTE_S *pstAERouteSFAttr);
CVI_S32 CVI_ISP_SetAERouteSFAttrEx(VI_PIPE ViPipe, const ISP_AE_ROUTE_EX_S *pstAERouteSFAttrEx);
CVI_S32 CVI_ISP_GetAERouteSFAttrEx(VI_PIPE ViPipe, ISP_AE_ROUTE_EX_S *pstAERouteSFAttrEx);
CVI_S32 CVI_ISP_SetAntiFlicker(VI_PIPE ViPipe, CVI_BOOL enable, CVI_U8 frequency);
CVI_S32 CVI_ISP_GetAntiFlicker(VI_PIPE ViPipe, CVI_BOOL *pEnable, CVI_U8 *pFrequency);
CVI_S32 CVI_ISP_SetWDRLEOnly(VI_PIPE ViPipe, CVI_BOOL wdrLEOnly);
CVI_S32 CVI_ISP_GetFrameID(VI_PIPE ViPipe, CVI_U32 *frameID);
CVI_S32 CVI_ISP_QueryFps(VI_PIPE ViPipe, CVI_FLOAT *pFps);
CVI_S32 CVI_ISP_GetCurrentLvX100(VI_PIPE ViPipe, CVI_S16 *ps16Lv);
CVI_S32 CVI_ISP_SetFastBootExposure(VI_PIPE ViPipe, CVI_U32 expLine, CVI_U32 again, CVI_U32 dgain, CVI_U32 ispdgain);
CVI_S32 CVI_ISP_SetIrisAttr(VI_PIPE ViPipe, const ISP_IRIS_ATTR_S *pstIrisAttr);
CVI_S32 CVI_ISP_GetIrisAttr(VI_PIPE ViPipe, ISP_IRIS_ATTR_S *pstIrisAttr);
CVI_S32 CVI_ISP_SetDcirisAttr(VI_PIPE ViPipe, const ISP_DCIRIS_ATTR_S *pstDcirisAttr);
CVI_S32 CVI_ISP_GetDcirisAttr(VI_PIPE ViPipe, ISP_DCIRIS_ATTR_S *pstDcirisAttr);
CVI_S32 CVI_ISP_SetAELogPath(const char *szPath);
CVI_S32 CVI_ISP_GetAELogPath(char *szPath, CVI_U32 pathSize);
CVI_S32 CVI_ISP_SetAELogName(const char *szName);
CVI_S32 CVI_ISP_GetAELogName(char *szName, CVI_U32 nameSize);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __CVI_AE_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
*
* File Name: include/cvi_ae_comm.h
* Description:
*/
#ifndef __CVI_AE_COMM_H__
#define __CVI_AE_COMM_H__
#include "cvi_comm_inc.h"
#include "cvi_comm_3a.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
#define CVI_AE_LIB_NAME "cvi_ae_lib"
typedef enum _AE_ACCURACY_E {
AE_ACCURACY_DB = 0,
AE_ACCURACY_LINEAR,
AE_ACCURACY_TABLE,
AE_ACCURACY_BUTT,
} AE_ACCURACY_E;
typedef enum _AE_BLC_TYPE_E {
AE_BLC_TYPE_LINEAR = 0,
AE_BLC_TYPE_LADDER,
AE_BLC_TYPE_BUTT,
} AE_BLC_TYPE_E;
typedef enum _ISP_SNS_GAIN_MODE_E {
SNS_GAIN_MODE_SHARE = 0, /* gain setting for all wdr frames*/
SNS_GAIN_MODE_WDR_2F, /* separate gain for 2-frame wdr mode*/
SNS_GAIN_MODE_WDR_3F, /* separate gain for 3-frame wdr mode*/
SNS_GAIN_MODE_ONLY_LEF /* gain setting only apply to lef and sef is fixed to 1x */
} ISP_SNS_GAIN_MODE_E;
typedef struct _AE_ACCURACY_S {
AE_ACCURACY_E enAccuType;
float f32Accuracy;
float f32Offset;
} AE_ACCURACY_S;
typedef struct _AE_SENSOR_DEFAULT_S {
CVI_U8 au8HistThresh[HIST_THRESH_NUM];
CVI_U8 u8AeCompensation;
CVI_U32 u32LinesPer500ms;
CVI_U32 u32FlickerFreq;
CVI_U32 u32HmaxTimes; /* unit is ns */
CVI_U32 u32InitExposure;
CVI_U32 u32InitAESpeed;
CVI_U32 u32InitAETolerance;
CVI_U32 u32FullLinesStd;
CVI_U32 u32FullLinesMax;
CVI_U32 u32FullLines;
CVI_U32 u32MaxIntTime; /* RW;unit is line */
CVI_U32 u32MinIntTime;
CVI_U32 u32MaxIntTimeTarget;
CVI_U32 u32MinIntTimeTarget;
AE_ACCURACY_S stIntTimeAccu;
CVI_U32 u32MaxAgain;
CVI_U32 u32MinAgain;
CVI_U32 u32MaxAgainTarget;
CVI_U32 u32MinAgainTarget;
AE_ACCURACY_S stAgainAccu;
CVI_U32 u32MaxDgain;
CVI_U32 u32MinDgain;
CVI_U32 u32MaxDgainTarget;
CVI_U32 u32MinDgainTarget;
AE_ACCURACY_S stDgainAccu;
CVI_U32 u32MaxISPDgainTarget;
CVI_U32 u32MinISPDgainTarget;
CVI_U32 u32ISPDgainShift;
CVI_U32 u32MaxIntTimeStep;
CVI_U32 u32LFMaxShortTime;
CVI_U32 u32LFMinExposure;
#if 0
ISP_AE_ROUTE_S stAERouteAttr;
CVI_BOOL bAERouteExValid;
ISP_AE_ROUTE_EX_S stAERouteAttrEx;
CVI_U16 u16ManRatioEnable;
CVI_U32 au32Ratio[EXP_RATIO_NUM];
ISP_IRIS_TYPE_E enIrisType;
ISP_PIRIS_ATTR_S stPirisAttr;
ISP_IRIS_F_NO_E enMaxIrisFNO;
ISP_IRIS_F_NO_E enMinIrisFNO;
#endif
ISP_AE_STRATEGY_E enAeExpMode;
CVI_U16 u16ISOCalCoef;
CVI_U8 u8AERunInterval;
CVI_FLOAT f32Fps;
CVI_FLOAT f32MinFps;
CVI_U32 denom;
CVI_U32 u32AEResponseFrame;
CVI_U32 u32SnsStableFrame; /* delay for stable statistic after sensor init. (unit: frame) */
AE_BLC_TYPE_E enBlcType;
ISP_SNS_GAIN_MODE_E enWDRGainMode;
} AE_SENSOR_DEFAULT_S;
typedef struct _AE_FSWDR_ATTR_S {
ISP_FSWDR_MODE_E enFSWDRMode;
} AE_FSWDR_ATTR_S;
typedef struct _AE_SENSOR_EXP_FUNC_S {
CVI_S32 (*pfn_cmos_get_ae_default)(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft);
/* the function of sensor set fps */
CVI_S32 (*pfn_cmos_fps_set)(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft);
CVI_S32 (*pfn_cmos_slow_framerate_set)(VI_PIPE ViPipe, CVI_U32 u32FullLines, AE_SENSOR_DEFAULT_S *pstAeSnsDft);
/* while isp notify ae to update sensor regs, ae call these funcs. */
CVI_S32 (*pfn_cmos_inttime_update)(VI_PIPE ViPipe, CVI_U32 *u32IntTime);
CVI_S32 (*pfn_cmos_gains_update)(VI_PIPE ViPipe, CVI_U32 *u32Again, CVI_U32 *u32Dgain);
CVI_S32 (*pfn_cmos_again_calc_table)(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb);
CVI_S32 (*pfn_cmos_dgain_calc_table)(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb);
CVI_S32 (*pfn_cmos_get_inttime_max)
(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio, CVI_U32 *au32IntTimeMax,
CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime);
/* long frame mode set */
CVI_S32 (*pfn_cmos_ae_fswdr_attr_set)(VI_PIPE ViPipe, AE_FSWDR_ATTR_S *pstAeFSWDRAttr);
} AE_SENSOR_EXP_FUNC_S;
typedef struct _AE_SENSOR_REGISTER_S {
AE_SENSOR_EXP_FUNC_S stAeExp;
} AE_SENSOR_REGISTER_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __CVI_AE_COMM_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
*
* File Name: include/cvi_af.h
* Description:
*/
#ifndef __CVI_AF_H__
#define __CVI_AF_H__
#include "cvi_comm_isp.h"
#include "cvi_comm_3a.h"
#include "cvi_af_comm.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
CVI_S32 CVI_AF_Register(VI_PIPE ViPipe, ALG_LIB_S *pstAfLib);
CVI_S32 CVI_AF_UnRegister(VI_PIPE ViPipe, ALG_LIB_S *pstAfLib);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __CVI_AF_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
*
* File Name: include/cvi_af_comm.h
* Description:
*/
#ifndef __CVI_AF_COMM_H__
#define __CVI_AF_COMM_H__
#include "cvi_comm_inc.h"
#include "cvi_comm_3a.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
#define CVI_AF_LIB_NAME "cvi_af_lib"
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __CVI_AF_COMM_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
*
* File Name: include/cvi_awb.h
* Description:
*/
#ifndef __CVI_AWB_H__
#define __CVI_AWB_H__
#include "cvi_comm_isp.h"
#include "cvi_comm_3a.h"
#include "cvi_awb_comm.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
#define AWB_LOG_BUFF_SIZE (48*1024)
#define AWB_SNAP_LOG_BUFF_SIZE (AWB_LOG_BUFF_SIZE)
/* The interface of awb lib register to isp. */
CVI_S32 CVI_AWB_Register(VI_PIPE ViPipe, ALG_LIB_S *pstAwbLib);
CVI_S32 CVI_AWB_UnRegister(VI_PIPE ViPipe, ALG_LIB_S *pstAwbLib);
/* The callback function of sensor register to awb lib. */
CVI_S32 CVI_AWB_SensorRegCallBack(VI_PIPE ViPipe, ALG_LIB_S *pstAwbLib, ISP_SNS_ATTR_INFO_S *pstSnsAttrInfo,
AWB_SENSOR_REGISTER_S *pstRegister);
CVI_S32 CVI_AWB_SensorUnRegCallBack(VI_PIPE ViPipe, ALG_LIB_S *pstAwbLib, SENSOR_ID SensorId);
CVI_S32 CVI_AWB_QueryInfo(VI_PIPE ViPipe, ISP_WB_Q_INFO_S *pstWB_Q_Info);
CVI_S32 CVI_ISP_SetWBAttr(VI_PIPE ViPipe, const ISP_WB_ATTR_S *pstWBAttr);
CVI_S32 CVI_ISP_GetWBAttr(VI_PIPE ViPipe, ISP_WB_ATTR_S *pstWBAttr);
CVI_S32 CVI_ISP_SetAWBAttrEx(VI_PIPE ViPipe, const ISP_AWB_ATTR_EX_S *pstAWBAttrEx);
CVI_S32 CVI_ISP_GetAWBAttrEx(VI_PIPE ViPipe, ISP_AWB_ATTR_EX_S *pstAWBAttrEx);
CVI_S32 CVI_ISP_QueryWBInfo(VI_PIPE ViPipe, ISP_WB_INFO_S *pstWBInfo);
CVI_S32 CVI_ISP_GetGrayWorldAwbInfo(VI_PIPE ViPipe, CVI_U16 *pRgain, CVI_U16 *pBgain);
CVI_S32 CVI_ISP_SetAWBLogPath(const char *szPath);
CVI_S32 CVI_ISP_SetAWBLogName(const char *szName);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __CVI_AWB_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
*
* File Name: include/cvi_awb_comm.h
* Description:
*/
#ifndef __CVI_AWB_COMM_H__
#define __CVI_AWB_COMM_H__
#include "cvi_comm_inc.h"
#include "cvi_comm_3a.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
#define CVI_AWB_LIB_NAME "cvi_awb_lib"
typedef struct cviAWB_SENSOR_DEFAULT_S {
CVI_U16 u16WbRefTemp;
CVI_U16 au16GainOffset[ISP_BAYER_CHN_NUM];
// CVI_S32 as32WbPara[AWB_CURVE_PARA_NUM];
CVI_U16 u16GoldenRgain;
CVI_U16 u16GoldenBgain;
CVI_U16 u16SampleRgain;
CVI_U16 u16SampleBgain;
// AWB_AGC_TABLE_S stAgcTbl;
// AWB_CCM_S stCcm;
CVI_U16 u16InitRgain;
CVI_U16 u16InitGgain;
CVI_U16 u16InitBgain;
CVI_U8 u8AWBRunInterval;
} AWB_SENSOR_DEFAULT_S;
typedef struct cviAWB_SENSOR_EXP_FUNC_S {
CVI_S32 (*pfn_cmos_get_awb_default)(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft);
// CVI_S32(*pfn_cmos_get_awb_spec_default)(VI_PIPE ViPipe, AWB_SPEC_SENSOR_DEFAULT_S *pstAwbSpecSnsDft);
} AWB_SENSOR_EXP_FUNC_S;
typedef struct cviAWB_SENSOR_REGISTER_S {
AWB_SENSOR_EXP_FUNC_S stAwbExp;
} AWB_SENSOR_REGISTER_S;
typedef struct _ISP_WB_CURVE_S {
CVI_U16 u16CurveSize;
CVI_U16 *u16RGain;
CVI_U16 *u16BGain;
CVI_U16 *u16BGainTop;
CVI_U16 *u16BGainBottom;
} ISP_WB_CURVE_S;
typedef struct _ISP_WB_Q_INFO_S {
CVI_U16 u16Rgain;
CVI_U16 u16Grgain;
CVI_U16 u16Gbgain;
CVI_U16 u16Bgain;
CVI_U16 u16Saturation;
CVI_U16 u16ColorTemp;
CVI_U16 u16LS0CT;
CVI_U16 u16LS1CT;
CVI_U16 u16LS0Area;
CVI_U16 u16LS1Area;
CVI_U8 u8MultiDegree;
CVI_U16 u16ActiveShift;
CVI_U32 u32FirstStableTime;
ISP_AWB_INDOOR_OUTDOOR_STATUS_E enInOutStatus;
CVI_S16 s16Bv;
} ISP_WB_Q_INFO_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __CVI_AWB_COMM_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
*
* File Name: include/cvi_common_3a.h
* Description:
*/
#ifndef __CVI_COMM_3A_H__
#define __CVI_COMM_3A_H__
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
#include <stdbool.h>
#include "cvi_comm_isp.h"
#include "cvi_comm_sns.h"
#define ALG_LIB_NAME_SIZE_MAX (20)
#define MAX_REGISTER_ALG_LIB_NUM 4
#define HIST_THRESH_NUM (4)
#define MAX_AE_W (32)
#define MAX_AE_H (24)
#define MAX_AE_SIZE (MAX_AE_W * MAX_AE_H)
#define MAX_AE_WIN (2)
#define ENABLE_AF_LIB (0)
typedef enum _ISP_FSWDR_MODE_E {
ISP_FSWDR_NORMAL_MODE = 0x0,
ISP_FSWDR_LONG_FRAME_MODE = 0x1,
ISP_FSWDR_AUTO_LONG_FRAME_MODE = 0x2,
ISP_FSWDR_MODE_BUTT
} ISP_FSWDR_MODE_E;
typedef struct _ISP_AE_RANGE_S {
CVI_U32 u32Max; /*RW; Range:[0x0, 0x7FFFFFFF]*/
CVI_U32 u32Min; /*RW; Range:[0x0, 0x7FFFFFFF]*/
} ISP_AE_RANGE_S;
typedef enum _ISP_AE_STRATEGY_E {
AE_EXP_HIGHLIGHT_PRIOR = 0,
AE_EXP_LOWLIGHT_PRIOR = 1,
AE_STRATEGY_MODE_BUTT
} ISP_AE_STRATEGY_E;
typedef enum _ISP_AE_MODE_E {
AE_MODE_SLOW_SHUTTER = 0,
AE_MODE_FIX_FRAME_RATE = 1,
AE_MODE_BUTT
} ISP_AE_MODE_E;
typedef enum _ISP_ANTIFLICKER_MODE_E {
ISP_ANTIFLICKER_NORMAL_MODE = 0,
ISP_ANTIFLICKER_AUTO_MODE = 1,
ISP_ANTIFLICKER_MODE_BUTT
} ISP_ANTIFLICKER_MODE_E;
typedef struct _ISP_ANTIFLICKER_S {
CVI_BOOL bEnable;
ISP_AE_ANTIFLICKER_FREQUENCE_E enFrequency;
ISP_ANTIFLICKER_MODE_E enMode;
} ISP_ANTIFLICKER_S;
typedef struct _ISP_SUBFLICKER_S {
CVI_BOOL bEnable;
CVI_U8 u8LumaDiff; /*RW; Range:[0x0, 0x64]*/
} ISP_SUBFLICKER_S;
typedef struct _ISP_AE_DELAY_S {
CVI_U16 u16BlackDelayFrame;
CVI_U16 u16WhiteDelayFrame;
} ISP_AE_DELAY_S;
typedef struct _ISP_ME_ATTR_S {
ISP_OP_TYPE_E enExpTimeOpType;
ISP_OP_TYPE_E enAGainOpType;
ISP_OP_TYPE_E enDGainOpType;
ISP_OP_TYPE_E enISPDGainOpType;
CVI_U32 u32ExpTime; /*RW; Range:[0x0, 0x7FFFFFFF]*/
CVI_U32 u32AGain; /*RW; Range:[0x400, 0x7FFFFFFF]*/
CVI_U32 u32DGain; /*RW; Range:[0x400, 0x7FFFFFFF]*/
CVI_U32 u32ISPDGain; /*RW; Range:[0x400, 0x40000]*/
ISP_OP_TYPE_E enISONumOpType;
ISP_AE_GAIN_TYPE_E enGainType;
CVI_U32 u32ISONum; /*RW; Range:[0x64, 0x7FFFFFFF]*/
} ISP_ME_ATTR_S;
#define RESERVE_SIZE 10
typedef struct _ISP_AE_ATTR_S {
ISP_AE_RANGE_S stExpTimeRange;
ISP_AE_RANGE_S stAGainRange; /*RW; Range:[0x400, 0x7FFFFFFF]*/
ISP_AE_RANGE_S stDGainRange; /*RW; Range:[0x400, 0x7FFFFFFF]*/
ISP_AE_RANGE_S stISPDGainRange; /*RW; Range:[0x400, 0x40000]*/
ISP_AE_RANGE_S stSysGainRange; /*RW; Range:[0x400, 0x7FFFFFFF]*/
CVI_U32 u32GainThreshold; /*RW; Range:[0x400, 0x7FFFFFFF]*/
CVI_U8 u8Speed; // 1 means 0.1 ev
CVI_U16 u16BlackSpeedBias;
CVI_U8 u8Tolerance;
CVI_U8 u8Compensation;
CVI_U16 u16EVBias;
ISP_AE_STRATEGY_E enAEStrategyMode;
CVI_U16 u16HistRatioSlope;
CVI_U8 u8MaxHistOffset;
ISP_AE_MODE_E enAEMode;
ISP_ANTIFLICKER_S stAntiflicker;
ISP_SUBFLICKER_S stSubflicker;
ISP_AE_DELAY_S stAEDelayAttr;
CVI_BOOL bManualExpValue;
CVI_U32 u32ExpValue; /*RW; Range:[0x0, 0x7FFFFFFF]*/
ISP_FSWDR_MODE_E enFSWDRMode;
CVI_BOOL bWDRQuick;
CVI_U16 u16ISOCalCoef;
ISP_AE_GAIN_TYPE_E enGainType;
ISP_AE_RANGE_S stISONumRange; /*RW; Range:[0x64, 0x7FFFFFFF]*/
CVI_S16 s16IRCutOnLv;
CVI_S16 s16IRCutOffLv;
ISP_AE_IR_CUT_FORCE_STATUS enIRCutStatus;
CVI_U8 au8AdjustTargetMin[LV_TOTAL_NUM];
CVI_U8 au8AdjustTargetMax[LV_TOTAL_NUM];
CVI_U16 u16LowBinThr; /*RW; Range:[0x0, 0x100]*/
CVI_U16 u16HighBinThr; /*RW; Range:[0x0, 0x100]*/
CVI_BOOL bEnableFaceAE;
CVI_U8 u8FaceTargetLuma; /*RW; Range:[0x1, 0xFF]*/
CVI_U8 u8FaceWeight; /*RW; Range:[0x0, 0x64]*/
CVI_U8 u8GridBvWeight; /*RW; Range:[0x0, 0x64]*/
CVI_U32 au32Reserve[RESERVE_SIZE]; /*RW; Range:[0x0, 0x7FFFFFFF]*/
CVI_U8 u8HighLightLumaThr;
CVI_U8 u8HighLightBufLumaThr;
CVI_U8 u8LowLightLumaThr;
CVI_U8 u8LowLightBufLumaThr;
CVI_BOOL bHistogramAssist;
} ISP_AE_ATTR_S;
typedef struct _ISP_EXPOSURE_ATTR_S {
CVI_BOOL bByPass;
ISP_OP_TYPE_E enOpType;
CVI_U8 u8AERunInterval; /*RW; Range:[0x1, 0xFF]*/
CVI_BOOL bHistStatAdjust;
CVI_BOOL bAERouteExValid;
ISP_ME_ATTR_S stManual;
ISP_AE_ATTR_S stAuto;
CVI_U8 u8DebugMode;
ISP_AE_METER_MODE_E enMeterMode;
CVI_BOOL bAEGainSepCfg;
} ISP_EXPOSURE_ATTR_S;
typedef struct ISP_STITCH_ATTR_T {
CVI_BOOL enable;
} ISP_STITCH_ATTR_S;
typedef struct _ALG_LIB_S {
CVI_S32 s32Id;
CVI_CHAR acLibName[ALG_LIB_NAME_SIZE_MAX];
} ALG_LIB_S;
/* the init param of awb alg */
typedef struct _ISP_AE_PARAM_S {
SENSOR_ID SensorId;
CVI_U8 u8WDRMode;
CVI_U8 u8HDRMode;
CVI_U16 u16BlackLevel;
CVI_FLOAT f32Fps;
ISP_BAYER_FORMAT_E enBayer;
ISP_STITCH_ATTR_S stStitchAttr;
CVI_S32 s32Rsv;
ISP_3AWIN_CONFIG_S aeLEWinConfig[AE_MAX_NUM];
ISP_3AWIN_CONFIG_S aeSEWinConfig;
} ISP_AE_PARAM_S;
typedef struct _ISP_FE_AE_STAT_1_S {
CVI_U32 u32PixelCount[ISP_CHANNEL_MAX_NUM];
CVI_U32 u32PixelWeight[ISP_CHANNEL_MAX_NUM];
CVI_U32 au32HistogramMemArray[ISP_CHANNEL_MAX_NUM][MAX_HIST_BINS];
} ISP_FE_AE_STAT_1_S;
typedef struct _ISP_FE_AE_STAT_2_S {
CVI_U16 u16GlobalAvgR[ISP_CHANNEL_MAX_NUM];
CVI_U16 u16GlobalAvgGr[ISP_CHANNEL_MAX_NUM];
CVI_U16 u16GlobalAvgGb[ISP_CHANNEL_MAX_NUM];
CVI_U16 u16GlobalAvgB[ISP_CHANNEL_MAX_NUM];
} ISP_FE_AE_STAT_2_S;
typedef struct _ISP_FE_AE_STAT_3_S {
CVI_U16 au16ZoneAvg[ISP_CHANNEL_MAX_NUM][AE_ZONE_ROW][AE_ZONE_COLUMN][4];
} ISP_FE_AE_STAT_3_S;
typedef struct _ISP_FE_AE_STITCH_STAT_3_S {
CVI_U16 au16ZoneAvg[ISP_CHANNEL_MAX_NUM][ISP_CHANNEL_MAX_NUM][AE_ZONE_ROW][AE_ZONE_COLUMN][4];
} ISP_FE_AE_STITCH_STAT_3_S;
typedef struct _ISP_AE_STAT_ATTR_S {
CVI_BOOL bChange;
CVI_BOOL bHistAdjust;
CVI_U8 u8AEBESel;
CVI_U8 u8FourPlaneMode;
CVI_U8 u8HistOffsetX;
CVI_U8 u8HistOffsetY;
CVI_U8 u8HistSkipX;
CVI_U8 u8HistSkipY;
CVI_BOOL bModeUpdate;
CVI_U8 u8HistMode;
CVI_U8 u8AverMode;
CVI_U8 u8MaxGainMode;
CVI_BOOL bWightTableUpdate;
CVI_U8 au8WeightTable[VI_MAX_PIPE_NUM][AE_WEIGHT_ZONE_ROW][AE_WEIGHT_ZONE_COLUMN];
} ISP_AE_STAT_ATTR_S;
typedef struct _ISP_AE_STAT_RESULT_S {
CVI_U32 u32IntTime[VI_MAX_PIPE_NUM];
CVI_U32 u32IspDgain;
CVI_U32 u32Again;
CVI_U32 u32Dgain;
CVI_U32 u32Iso;
CVI_U8 u8AERunInterval;
CVI_BOOL bPirisValid;
CVI_S32 s32PirisPos;
CVI_U32 u32PirisGain;
ISP_FSWDR_MODE_E enFSWDRMode;
CVI_U32 au32WDRGain[4];
CVI_U32 u32HmaxTimes; /* unit is ns */
ISP_AE_STAT_ATTR_S stStatAttr;
ISP_DCF_UPDATE_INFO_S stUpdateInfo;
CVI_U32 u32ExpRatio;
CVI_S16 s16CurrentLV;
CVI_U32 u32AvgLuma;
CVI_U8 u8MeterFramePeriod;
CVI_BOOL bStable;
CVI_FLOAT fBvStep;
CVI_U32 u32BlcIso;
CVI_U32 u32IspDgainSF;
CVI_U32 u32AgainSF;
CVI_U32 u32DgainSF;
CVI_U32 u32IsoSF;
CVI_U32 u32BlcIsoSF;
CVI_FLOAT fEvRatio[2];
} ISP_AE_RESULT_S;
typedef struct _ISP_BE_AE_STAT_1_S {
CVI_BOOL bStable;
} ISP_BE_AE_STAT_1_S;
typedef struct _ISP_BE_AE_STAT_2_S {
CVI_BOOL bStable;
} ISP_BE_AE_STAT_2_S;
typedef struct _ISP_BE_AE_STAT_3_S {
CVI_BOOL bStable;
} ISP_BE_AE_STAT_3_S;
typedef struct _ISP_BE_AE_STITCH_STAT_3_S {
CVI_BOOL bStable;
} ISP_BE_AE_STITCH_STAT_3_S;
typedef struct _ISP_AE_INFO_S {
CVI_U32 u32FrameCnt; /* the counting of frame */
ISP_SMART_ROI_S stSmartInfo;
ISP_FE_AE_STAT_1_S * pstFEAeStat1[AE_MAX_NUM];
ISP_FE_AE_STAT_2_S * pstFEAeStat2[AE_MAX_NUM];
ISP_FE_AE_STAT_3_S * pstFEAeStat3[AE_MAX_NUM];
ISP_FE_AE_STITCH_STAT_3_S *pstFEAeStiStat;
ISP_BE_AE_STAT_1_S *pstBEAeStat1;
ISP_BE_AE_STAT_2_S *pstBEAeStat2;
ISP_BE_AE_STAT_3_S *pstBEAeStat3;
ISP_BE_AE_STITCH_STAT_3_S *pstBEAeStiStat;
ISP_3AWIN_CONFIG_S aeLEWinConfig[AE_MAX_NUM];
ISP_3AWIN_CONFIG_S aeSEWinConfig;
} ISP_AE_INFO_S;
typedef struct bmISP_DCI_INFO_S {
CVI_U32 u32FrameCnt; /* the counting of frame */
CVI_U16 pStat[DCI_BINS_NUM];
} ISP_DCI_INFO_S;
/* the init param of awb alg */
typedef struct _ISP_AWB_PARAM_S {
SENSOR_ID SensorId;
CVI_U8 u8WDRMode;
CVI_U8 u8AWBZoneRow;
CVI_U8 u8AWBZoneCol;
CVI_U8 u8AWBZoneBin;
ISP_STITCH_ATTR_S stStitchAttr;
CVI_U16 u16AWBWidth;
CVI_U16 u16AWBHeight;
CVI_S8 s8Rsv;
} ISP_AWB_PARAM_S;
typedef struct _ISP_AWB_RAW_STAT_ATTR_S {
bool bStatCfgUpdate;
CVI_U16 u16MeteringWhiteLevelAwb;
CVI_U16 u16MeteringBlackLevelAwb;
CVI_U16 u16MeteringCrRefMaxAwb;
CVI_U16 u16MeteringCbRefMaxAwb;
CVI_U16 u16MeteringCrRefMinAwb;
CVI_U16 u16MeteringCbRefMinAwb;
} ISP_AWB_RAW_STAT_ATTR_S;
typedef struct _ISP_AWB_RESULT_S {
CVI_U32 au32WhiteBalanceGain[ISP_BAYER_CHN_NUM];
CVI_U16 au16ColorMatrix[CCM_MATRIX_SIZE];
CVI_U32 u32ColorTemp;
CVI_U8 u8Saturation[4];
ISP_AWB_RAW_STAT_ATTR_S stRawStatAttr;
CVI_BOOL bStable;
} ISP_AWB_RESULT_S;
typedef struct _ISP_AWB_STAT_1_S {
CVI_U16 u16MeteringAwbAvgR;
CVI_U16 u16MeteringAwbAvgG;
CVI_U16 u16MeteringAwbAvgB;
CVI_U16 u16MeteringAwbCountAll;
} ISP_AWB_STAT_1_S;
typedef struct _ISP_AWB_STAT_RESULT_S {
CVI_U16 *pau16ZoneAvgR;
CVI_U16 *pau16ZoneAvgG;
CVI_U16 *pau16ZoneAvgB;
CVI_U16 *pau16ZoneCount;
} ISP_AWB_STAT_RESULT_S;
typedef struct _ISP_AWB_INFO_S {
CVI_U32 u32FrameCnt;
ISP_SMART_ROI_S stSmartInfo;
ISP_AWB_STAT_1_S * pstAwbStat1[ISP_CHANNEL_MAX_NUM];
ISP_AWB_STAT_RESULT_S stAwbStat2[ISP_CHANNEL_MAX_NUM];
CVI_U8 u8AwbGainSwitch;
CVI_U32 au32WDRWBGain[ISP_BAYER_CHN_NUM];
CVI_U32 u32IsoNum;
CVI_S16 s16LVx100;
CVI_FLOAT fBVstep;
} ISP_AWB_INFO_S;
// AF related structure
typedef struct _ISP_AF_PARAM_S {
SENSOR_ID SensorId;
CVI_U8 u8WDRMode;
CVI_S32 s32Rsv;
} ISP_AF_PARAM_S;
typedef struct _ISP_AF_INFO_S {
CVI_U32 u32FrameCnt;
ISP_AF_STATISTICS_S *pstAfStat;
} ISP_AF_INFO_S;
typedef struct _ISP_AF_RESULT_S {
CVI_S32 s32Rsv;
} ISP_AF_RESULT_S;
typedef struct _ISP_AE_STITCH_STATISTICS_S {
CVI_U32 enable;
} ISP_AE_STITCH_STATISTICS_S;
typedef struct _ISP_BIND_ATTR_S {
SENSOR_ID sensorId;
ALG_LIB_S stAeLib;
ALG_LIB_S stAfLib;
ALG_LIB_S stAwbLib;
} ISP_BIND_ATTR_S;
typedef struct _ISP_AE_EXP_FUNC_S {
CVI_S32 (*pfn_ae_init)(VI_PIPE ViPipe, const ISP_AE_PARAM_S *pstAeParam);
CVI_S32 (*pfn_ae_run)(VI_PIPE ViPipe, const ISP_AE_INFO_S *pstAeInfo,
ISP_AE_RESULT_S *pstAeResult, CVI_S32 s32Rsv);
CVI_S32 (*pfn_ae_ctrl)(VI_PIPE ViPipe, CVI_U32 u32Cmd, void *pValue);
CVI_S32 (*pfn_ae_exit)(VI_PIPE ViPipe);
} ISP_AE_EXP_FUNC_S;
typedef struct _ISP_AWB_EXP_FUNC_S {
CVI_S32 (*pfn_awb_init)(VI_PIPE ViPipe, const ISP_AWB_PARAM_S *pstAwbParam);
CVI_S32 (*pfn_awb_run)(VI_PIPE ViPipe, const ISP_AWB_INFO_S *pstAwbInfo, ISP_AWB_RESULT_S *pstAwbResult,
CVI_S32 s32Rsv);
CVI_S32 (*pfn_awb_ctrl)(VI_PIPE ViPipe, CVI_U32 u32Cmd, CVI_VOID *pValue);
CVI_S32 (*pfn_awb_exit)(VI_PIPE ViPipe);
} ISP_AWB_EXP_FUNC_S;
typedef struct _ISP_AF_EXP_FUNC_S {
CVI_S32 (*pfn_af_init)(VI_PIPE ViPipe, const ISP_AF_PARAM_S *pstAfParam);
CVI_S32 (*pfn_af_run)(VI_PIPE ViPipe, const ISP_AF_INFO_S *pstAfInfo, ISP_AF_RESULT_S *pstAfResult,
CVI_S32 s32Rsv);
CVI_S32 (*pfn_af_ctrl)(VI_PIPE ViPipe, CVI_U32 u32Cmd, CVI_VOID *pValue);
CVI_S32 (*pfn_af_exit)(VI_PIPE ViPipe);
} ISP_AF_EXP_FUNC_S;
typedef struct _ISP_AE_REGISTER_S {
ISP_AE_EXP_FUNC_S stAeExpFunc;
} ISP_AE_REGISTER_S;
typedef struct _ISP_AWB_REGISTER_S {
ISP_AWB_EXP_FUNC_S stAwbExpFunc;
} ISP_AWB_REGISTER_S;
typedef struct _ISP_AF_REGISTER_S {
ISP_AF_EXP_FUNC_S stAfExpFunc;
} ISP_AF_REGISTER_S;
typedef enum _ISP_CTRL_CMD_E {
ISP_WDR_MODE_SET = 0,
ISP_CTRL_CMD_BUTT_MAX,
} ISP_CTRL_CMD_E;
#define AWB_DBG_VER (11)
#define AWB_SENSOR_NUM (2)
#define AWB_DBG_W (64)
#define AWB_DBG_H (32)
#define AWB_SHIFT_REGION_NUM (4)
typedef struct _AWB_DBG_S {
//Don't modify ==>
CVI_U32 u32Date;
CVI_U16 u16AlgoVer;
CVI_U16 u16DbgVer;
CVI_U16 u16MaxFrameNum;
CVI_U16 u16SensorId;
CVI_U32 u32BinSize;
CVI_U16 u16WinWnum;
CVI_U16 u16WinHnum;
CVI_U16 u16WinOffX;
CVI_U16 u16WinOffY;
CVI_U16 u16WinWsize;
CVI_U16 u16WinHsize;
CVI_U16 u16P_R[2][AWB_DBG_W*AWB_DBG_H];//keep Max Size
CVI_U16 u16P_G[2][AWB_DBG_W*AWB_DBG_H];//keep Max Size
CVI_U16 u16P_B[2][AWB_DBG_W*AWB_DBG_H];//keep Max Size
CVI_U16 u16P_type[2][AWB_DBG_W*AWB_DBG_H];//keep Max Size
CVI_U16 u16GrayCnt;
CVI_U16 u16BalanceR;
CVI_U16 u16BalanceB;
CVI_U16 u16FinalR;
CVI_U16 u16FinalB;
CVI_U16 u16CurrentR;
CVI_U16 u16CurrentB;
CVI_U16 u16IdealR;
CVI_U16 u16IdealB;
CVI_U16 CalibRgain[AWB_CALIB_PTS_NUM];
CVI_U16 CalibBgain[AWB_CALIB_PTS_NUM];
CVI_U16 CalibTemp[AWB_CALIB_PTS_NUM];
CVI_U16 u16CurveR[256];//4096/16
CVI_U16 u16CurveB[256];
CVI_U16 u16CurveB_Top[256];
CVI_U16 u16CurveB_Bot[256];
CVI_S16 s16LvX100;
CVI_U32 u32ISONum;
ISP_WB_ATTR_S dbgMPIAttr[AWB_SENSOR_NUM];
ISP_WB_ATTR_S dbgInfoAttr[AWB_SENSOR_NUM];
ISP_AWB_ATTR_EX_S dbgMPIAttrEx[AWB_SENSOR_NUM];
ISP_AWB_ATTR_EX_S dbgInfoAttrEx[AWB_SENSOR_NUM];
//Don't modify <==
CVI_U8 calib_sts;
ISP_AWB_Calibration_Gain_S_EX calib_ex;
ISP_SMART_ROI_S stFace;
// fix size to 128 byte from here
CVI_U16 u16Region_R[AWB_SHIFT_REGION_NUM];
CVI_U8 u8Reserve[120];
} s_AWB_DBG_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __CVI_COMM_3A_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
*
* File Name: include/cvi_common_inc.h
* Description:
*/
#ifndef __CVI_COMM_INC_H__
#define __CVI_COMM_INC_H__
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
#include "stddef.h"
#include "stdint.h"
#include <sys/time.h>
#if defined(ARCH_CV183X) || defined(ARCH_CV182X)
#include <cvi_common.h>
#include <cvi_comm_vi.h>
#include <cvi_comm_video.h>
#include <cvi_defines.h>
#elif defined(ARCH_RTOS_CV181X)
#include <cvi_common.h>
#include <cvi_comm_vi.h>
#include <cvi_comm_video.h>
#include <cvi_defines.h>
#elif defined(ARCH_CV181X) || defined(ARCH_CV180X) || defined(__CV181X__) || defined(__CV180X__)
#include <linux/cvi_common.h>
#include <linux/cvi_comm_vi.h>
#include <linux/cvi_comm_video.h>
#include <linux/cvi_defines.h>
#endif
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __CVI_COMM_INC_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_common_sns.h
* Description:
*/
#ifndef _CVI_COMM_SNS_H_
#define _CVI_COMM_SNS_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#include <cvi_type.h>
#include <cvi_defines.h>
#include "cvi_debug.h"
#include "cvi_comm_isp.h"
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
#define NOISE_PROFILE_CHANNEL_NUM 4
#define NOISE_PROFILE_LEVEL_NUM 2
#define NOISE_PROFILE_ISO_NUM 16
#define USE_USER_SEN_DRIVER 1
typedef struct _ISP_CMOS_SENSOR_IMAGE_MODE_S {
CVI_U16 u16Width;
CVI_U16 u16Height;
CVI_FLOAT f32Fps;
CVI_U8 u8SnsMode;
} ISP_CMOS_SENSOR_IMAGE_MODE_S;
typedef struct _ISP_CMOS_BLACK_LEVEL_S {
CVI_BOOL bUpdate;
ISP_BLACK_LEVEL_ATTR_S blcAttr;
} ISP_CMOS_BLACK_LEVEL_S;
typedef struct _ISP_SNS_ATTR_INFO_S {
CVI_U32 eSensorId;
} ISP_SNS_ATTR_INFO_S;
typedef struct cviISP_CMOS_NOISE_CALIBRATION_S {
CVI_FLOAT CalibrationCoef[NOISE_PROFILE_ISO_NUM][NOISE_PROFILE_CHANNEL_NUM][NOISE_PROFILE_LEVEL_NUM];
} ISP_CMOS_NOISE_CALIBRATION_S;
typedef struct _ISP_CMOS_DEFAULT_S {
ISP_CMOS_NOISE_CALIBRATION_S stNoiseCalibration;
} ISP_CMOS_DEFAULT_S;
typedef struct _ISP_SENSOR_EXP_FUNC_S {
CVI_VOID (*pfn_cmos_sensor_init)(VI_PIPE ViPipe);
CVI_VOID (*pfn_cmos_sensor_exit)(VI_PIPE ViPipe);
CVI_VOID (*pfn_cmos_sensor_global_init)(VI_PIPE ViPipe);
CVI_S32 (*pfn_cmos_set_image_mode)(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode);
CVI_S32 (*pfn_cmos_set_wdr_mode)(VI_PIPE ViPipe, CVI_U8 u8Mode);
/* the algs get data which is associated with sensor, except 3a */
CVI_S32 (*pfn_cmos_get_isp_default)(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef);
CVI_S32 (*pfn_cmos_get_isp_black_level)(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlackLevel);
CVI_S32 (*pfn_cmos_get_sns_reg_info)(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsRegsInfo);
CVI_S32 (*pfn_cmos_set_sns_reg_info)(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsRegsInfo);
/* the function of sensor set pixel detect */
//CVI_VOID (*pfn_cmos_set_pixel_detect)(VI_PIPE ViPipe, bool bEnable);
} ISP_SENSOR_EXP_FUNC_S;
typedef struct bmISP_SENSOR_REGISTER_S {
ISP_SENSOR_EXP_FUNC_S stSnsExp;
} ISP_SENSOR_REGISTER_S;
typedef enum _MCLK_FREQ_E {
MCLK_FREQ_NONE = 0,
MCLK_FREQ_37P125M,
MCLK_FREQ_25M,
MCLK_FREQ_27M,
MCLK_FREQ_NUM
} MCLK_FREQ_E;
typedef struct _SNS_MCLK_S {
CVI_U32 u8Cam;
MCLK_FREQ_E enFreq;
} SNS_MCLK_S;
// -------- If you want to change these interfaces, please contact the isp team. --------
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif
#endif /* _CVI_COMM_SNS_H_ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_comm_sys.h
* Description:
* The common sys type defination.
*/
#ifndef __CVI_COMM_SYS_H__
#define __CVI_COMM_SYS_H__
// #include <linux/cvi_comm_video.h>
// #include "cvi_errno.h"
// #include "cvi_debug.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
// #define BIND_DEST_MAXNUM 32
// #define BIND_NODE_MAXNUM 64
// typedef struct _MMF_BIND_DEST_S {
// CVI_U32 u32Num;
// MMF_CHN_S astMmfChn[BIND_DEST_MAXNUM];
// } MMF_BIND_DEST_S;
// typedef struct _BIND_NODE_S {
// CVI_BOOL bUsed;
// MMF_CHN_S src;
// MMF_BIND_DEST_S dsts;
// } BIND_NODE_S;
typedef enum _VI_VPSS_MODE_E {
VI_OFFLINE_VPSS_OFFLINE = 0,
VI_OFFLINE_VPSS_ONLINE,
VI_ONLINE_VPSS_OFFLINE,
VI_ONLINE_VPSS_ONLINE,
VI_BE_OFL_POST_OL_VPSS_OFL,
VI_BE_OFL_POST_OFL_VPSS_OFL,
VI_BE_OL_POST_OFL_VPSS_OFL,
VI_BE_OL_POST_OL_VPSS_OFL,
VI_VPSS_MODE_BUTT
} VI_VPSS_MODE_E;
// typedef struct _VI_VPSS_MODE_S {
// VI_VPSS_MODE_E aenMode[VI_MAX_PIPE_NUM];
// } VI_VPSS_MODE_S;
// typedef enum _VPSS_MODE_E {
// VPSS_MODE_SINGLE = 0,
// VPSS_MODE_DUAL,
// VPSS_MODE_RGNEX,
// VPSS_MODE_BUTT
// } VPSS_MODE_E;
// typedef enum _VPSS_INPUT_E {
// VPSS_INPUT_MEM = 0,
// VPSS_INPUT_ISP,
// VPSS_INPUT_BUTT
// } VPSS_INPUT_E;
// * enMode: decide vpss work as 1/2 device.
// * aenInput: decide the input of each vpss device.
// * ViPipe: only meaningful if enInput is ISP.
// typedef struct _VPSS_MODE_S {
// VPSS_MODE_E enMode;
// VPSS_INPUT_E aenInput[VPSS_IP_NUM];
// VI_PIPE ViPipe[VPSS_IP_NUM];
// } VPSS_MODE_S;
// typedef struct _CVI_TDMA_2D_S {
// uint64_t paddr_src;
// uint64_t paddr_dst;
// uint32_t w_bytes;
// uint32_t h;
// uint32_t stride_bytes_src;
// uint32_t stride_bytes_dst;
// } CVI_TDMA_2D_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __CVI_COMM_SYS_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_comm_vi.h
* Description:
* Common video input definitions.
*/
#ifndef __CVI_COMM_VI_H__
#define __CVI_COMM_VI_H__
#include <cvi_common.h>
#include <cvi_comm_video.h>
//#include "cvi_comm_gdc.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
#define VI_MAX_ADCHN_NUM (4UL)
#define VI_COMPMASK_NUM (2UL)
#define VI_PRO_MAX_FRAME_NUM (8UL)
#define VI_SHARPEN_GAIN_NUM 32
#define VI_AUTO_ISO_STRENGTH_NUM 16
#define VI_INVALID_FRMRATE (-1)
#define VI_CHN0 0
#define VI_CHN1 1
#define VI_CHN2 2
#define VI_CHN3 3
#define VI_INVALID_CHN -1
#define VI_MAX_VC_NUM 4
typedef struct _VI_LOW_DELAY_INFO_S {
CVI_BOOL bEnable; /* RW; Low delay enable. */
CVI_U32 u32LineCnt; /* RW; Range: [32, 16384]; Low delay shoreline. */
} VI_LOW_DELAY_INFO_S;
/* Information of raw data cmpresss param */
typedef struct _VI_CMP_PARAM_S {
CVI_U8 au8CmpParam[VI_CMP_PARAM_SIZE];
} VI_CMP_PARAM_S;
typedef enum _VI_USERPIC_MODE_E {
VI_USERPIC_MODE_PIC = 0, /* YUV picture */
VI_USERPIC_MODE_BGC, /* Background picture only with a color */
VI_USERPIC_MODE_BUTT,
} VI_USERPIC_MODE_E;
typedef struct _VI_USERPIC_BGC_S {
CVI_U32 u32BgColor;
} VI_USERPIC_BGC_S;
typedef struct _VI_USERPIC_ATTR_S {
VI_USERPIC_MODE_E enUsrPicMode; /* User picture mode */
union {
VIDEO_FRAME_INFO_S stUsrPicFrm; /* Information about a YUV picture */
VI_USERPIC_BGC_S stUsrPicBg; /* Information about a background picture only with a color */
} unUsrPic;
} VI_USERPIC_ATTR_S;
/* interface mode of video input */
typedef enum _VI_INTF_MODE_E {
VI_MODE_BT656 = 0, /* ITU-R BT.656 YUV4:2:2 */
VI_MODE_BT601, /* ITU-R BT.601 YUV4:2:2 */
VI_MODE_DIGITAL_CAMERA, /* digatal camera mode */
VI_MODE_BT1120_STANDARD, /* BT.1120 progressive mode */
VI_MODE_BT1120_INTERLEAVED, /* BT.1120 interstage mode */
VI_MODE_MIPI, /* MIPI RAW mode */
VI_MODE_MIPI_YUV420_NORMAL, /* MIPI YUV420 normal mode */
VI_MODE_MIPI_YUV420_LEGACY, /* MIPI YUV420 legacy mode */
VI_MODE_MIPI_YUV422, /* MIPI YUV422 mode */
VI_MODE_LVDS, /* LVDS mode */
VI_MODE_HISPI, /* HiSPi mode */
VI_MODE_SLVS, /* SLVS mode */
VI_MODE_BUTT
} VI_INTF_MODE_E;
/* Input mode */
typedef enum _VI_INPUT_MODE_E {
VI_INPUT_MODE_BT656 = 0, /* ITU-R BT.656 YUV4:2:2 */
VI_INPUT_MODE_BT601, /* ITU-R BT.601 YUV4:2:2 */
VI_INPUT_MODE_DIGITAL_CAMERA, /* digatal camera mode */
VI_INPUT_MODE_INTERLEAVED, /* interstage mode */
VI_INPUT_MODE_MIPI, /* MIPI mode */
VI_INPUT_MODE_LVDS, /* LVDS mode */
VI_INPUT_MODE_HISPI, /* HiSPi mode */
VI_INPUT_MODE_SLVS, /* SLVS mode */
VI_INPUT_MODE_BUTT
} VI_INPUT_MODE_E;
/* Work mode */
typedef enum _VI_WORK_MODE_E {
VI_WORK_MODE_1Multiplex = 0, /* 1 Multiplex mode */
VI_WORK_MODE_2Multiplex, /* 2 Multiplex mode */
VI_WORK_MODE_3Multiplex, /* 3 Multiplex mode */
VI_WORK_MODE_4Multiplex, /* 4 Multiplex mode */
VI_WORK_MODE_BUTT
} VI_WORK_MODE_E;
/* whether an input picture is interlaced or progressive */
typedef enum _VI_SCAN_MODE_E {
VI_SCAN_INTERLACED = 0, /* interlaced mode */
VI_SCAN_PROGRESSIVE, /* progressive mode */
VI_SCAN_BUTT
} VI_SCAN_MODE_E;
/* Sequence of YUV data
*
* VI_DATA_SEQ_VUVU: The input sequence of the second component(only contains u and v) in BT.1120 mode is VUVU
* VI_DATA_SEQ_UVUV: The input sequence of the second component(only contains u and v) in BT.1120 mode is UVUV
*/
typedef enum _VI_YUV_DATA_SEQ_E {
VI_DATA_SEQ_VUVU = 0,
VI_DATA_SEQ_UVUV,
VI_DATA_SEQ_UYVY, /* The input sequence of YUV is UYVY */
VI_DATA_SEQ_VYUY, /* The input sequence of YUV is VYUY */
VI_DATA_SEQ_YUYV, /* The input sequence of YUV is YUYV */
VI_DATA_SEQ_YVYU, /* The input sequence of YUV is YVYU */
VI_DATA_SEQ_BUTT
} VI_YUV_DATA_SEQ_E;
/* Clock edge mode */
typedef enum _VI_CLK_EDGE_E {
VI_CLK_EDGE_SINGLE_UP = 0, /* single-edge mode and in rising edge */
VI_CLK_EDGE_SINGLE_DOWN, /* single-edge mode and in falling edge */
VI_CLK_EDGE_BUTT
} VI_CLK_EDGE_E;
/* Component mode */
typedef enum _VI_COMPONENT_MODE_E {
VI_COMPONENT_MODE_SINGLE = 0, /* single component mode */
VI_COMPONENT_MODE_DOUBLE, /* double component mode */
VI_COMPONENT_MODE_BUTT
} VI_COMPONENT_MODE_E;
/* Y/C composite or separation mode */
typedef enum _VI_COMBINE_MODE_E {
VI_COMBINE_COMPOSITE = 0, /* Composite mode */
VI_COMBINE_SEPARATE, /* Separate mode */
VI_COMBINE_BUTT
} VI_COMBINE_MODE_E;
/* Attribute of the vertical synchronization signal */
typedef enum _VI_VSYNC_E {
VI_VSYNC_FIELD = 0, /* Field/toggle mode:a signal reversal means a new frame or a field */
VI_VSYNC_PULSE, /* Pusle/effective mode:a pusle or an effective signal means a new frame or a field */
VI_VSYNC_BUTT
} VI_VSYNC_E;
/* Polarity of the vertical synchronization signal
*
* VI_VSYNC_NEG_HIGH: if VIU_VSYNC_E = VIU_VSYNC_FIELD,then the v-sync signal of even field is high-level,
* if VIU_VSYNC_E = VIU_VSYNC_PULSE,then the v-sync pulse is positive pulse.
* VI_VSYNC_NEG_LOW: if VIU_VSYNC_E = VIU_VSYNC_FIELD,then the v-sync signal of even field is low-level,
* if VIU_VSYNC_E = VIU_VSYNC_PULSE,then the v-sync pulse is negative pulse.
*/
typedef enum _VI_VSYNC_NEG_E {
VI_VSYNC_NEG_HIGH = 0,
VI_VSYNC_NEG_LOW,
VI_VSYNC_NEG_BUTT
} VI_VSYNC_NEG_E;
/* Attribute of the horizontal synchronization signal */
typedef enum _VI_HSYNC_E {
VI_HSYNC_VALID_SINGNAL = 0, /* the h-sync is valid signal mode */
VI_HSYNC_PULSE, /* the h-sync is pulse mode, a new pulse means the beginning of a new line */
VI_HSYNC_BUTT
} VI_HSYNC_E;
/* Polarity of the horizontal synchronization signal
*
* VI_HSYNC_NEG_HIGH: if VI_HSYNC_E = VI_HSYNC_VALID_SINGNAL,then the valid h-sync signal is high-level;
* if VI_HSYNC_E = VI_HSYNC_PULSE,then the h-sync pulse is positive pulse.
* VI_HSYNC_NEG_LOW: if VI_HSYNC_E = VI_HSYNC_VALID_SINGNAL,then the valid h-sync signal is low-level;
* if VI_HSYNC_E = VI_HSYNC_PULSE,then the h-sync pulse is negative pulse
*/
typedef enum _VI_HSYNC_NEG_E {
VI_HSYNC_NEG_HIGH = 0,
VI_HSYNC_NEG_LOW,
VI_HSYNC_NEG_BUTT
} VI_HSYNC_NEG_E;
/* Attribute of the valid vertical synchronization signal
*
* VI_VSYNC_NORM_PULSE: the v-sync is pusle mode, a pusle means a new frame or field
* VI_VSYNC_VALID_SIGNAL: the v-sync is effective mode, a effective signal means a new frame or field
*/
typedef enum _VI_VSYNC_VALID_E {
VI_VSYNC_NORM_PULSE = 0,
VI_VSYNC_VALID_SIGNAL,
VI_VSYNC_VALID_BUTT
} VI_VSYNC_VALID_E;
/* Polarity of the valid vertical synchronization signal
*
* VI_VSYNC_VALID_NEG_HIGH: if VI_VSYNC_VALID_E = VI_VSYNC_NORM_PULSE,a positive pulse means v-sync pulse;
* if VI_VSYNC_VALID_E = VI_VSYNC_VALID_SIGNAL,the valid v-sync signal is high-level
* VI_VSYNC_VALID_NEG_LOW: if VI_VSYNC_VALID_E = VI_VSYNC_NORM_PULSE,a negative pulse means v-sync pulse
* if VI_VSYNC_VALID_E = VI_VSYNC_VALID_SIGNAL,the valid v-sync signal is low-level
*/
typedef enum _VI_VSYNC_VALID_NEG_E {
VI_VSYNC_VALID_NEG_HIGH = 0,
VI_VSYNC_VALID_NEG_LOW,
VI_VSYNC_VALID_NEG_BUTT
} VI_VSYNC_VALID_NEG_E;
typedef enum _VI_STATE {
VI_RUNNING,
VI_SUSPEND,
VI_MAX,
} VI_STATE_E;
/* Blank information of the input timing
*
* u32VsyncVfb: RW;Vertical front blanking height of one frame or odd-field frame picture
* u32VsyncVact: RW;Vertical effetive width of one frame or odd-field frame picture
* u32VsyncVbb: RW;Vertical back blanking height of one frame or odd-field frame picture
* u32VsyncVbfb: RW;Even-field vertical front blanking height when input mode is interlace
* (invalid when progressive input mode)
* u32VsyncVbact: RW;Even-field vertical effetive width when input mode is interlace
* (invalid when progressive input mode)
* u32VsyncVbbb: RW;Even-field vertical back blanking height when input mode is interlace
* (invalid when progressive input mode)
*/
typedef struct _VI_TIMING_BLANK_S {
CVI_U32 u32HsyncHfb; /* RW;Horizontal front blanking width */
CVI_U32 u32HsyncAct; /* RW;Horizontal effetive width */
CVI_U32 u32HsyncHbb; /* RW;Horizontal back blanking width */
CVI_U32 u32VsyncVfb;
CVI_U32 u32VsyncVact;
CVI_U32 u32VsyncVbb;
CVI_U32 u32VsyncVbfb;
CVI_U32 u32VsyncVbact;
CVI_U32 u32VsyncVbbb;
} VI_TIMING_BLANK_S;
/* synchronization information about the BT.601 or DC timing */
typedef struct _VI_SYNC_CFG_S {
VI_VSYNC_E enVsync;
VI_VSYNC_NEG_E enVsyncNeg;
VI_HSYNC_E enHsync;
VI_HSYNC_NEG_E enHsyncNeg;
VI_VSYNC_VALID_E enVsyncValid;
VI_VSYNC_VALID_NEG_E enVsyncValidNeg;
VI_TIMING_BLANK_S stTimingBlank;
} VI_SYNC_CFG_S;
/* the highest bit of the BT.656 timing reference code */
typedef enum _VI_BT656_FIXCODE_E {
VI_BT656_FIXCODE_1 = 0, /* The highest bit of the EAV/SAV data over the BT.656 protocol is always 1. */
VI_BT656_FIXCODE_0, /* The highest bit of the EAV/SAV data over the BT.656 protocol is always 0. */
VI_BT656_FIXCODE_BUTT
} VI_BT656_FIXCODE_E;
/* Polarity of the field indicator bit (F) of the BT.656 timing reference code */
typedef enum _VI_BT656_FIELD_POLAR_E {
VI_BT656_FIELD_POLAR_STD = 0, /* the standard BT.656 mode,the first filed F=0,the second filed F=1 */
VI_BT656_FIELD_POLAR_NSTD, /* the non-standard BT.656 mode,the first filed F=1,the second filed F=0 */
VI_BT656_FIELD_POLAR_BUTT
} VI_BT656_FIELD_POLAR_E;
/* synchronization information about the BT.656 */
typedef struct _VI_BT656_SYNC_CFG_S {
VI_BT656_FIXCODE_E enFixCode;
VI_BT656_FIELD_POLAR_E enFieldPolar;
} VI_BT656_SYNC_CFG_S;
/* Input data type */
typedef enum _VI_DATA_TYPE_E {
VI_DATA_TYPE_YUV = 0,
VI_DATA_TYPE_RGB,
VI_DATA_TYPE_YUV_EARLY,
VI_DATA_TYPE_BUTT
} VI_DATA_TYPE_E;
/* Attribute of wdr */
typedef struct _VI_WDR_ATTR_S {
WDR_MODE_E enWDRMode; /* RW; WDR mode.*/
CVI_U32 u32CacheLine; /* RW; WDR cache line.*/
} VI_WDR_ATTR_S;
/* the extended attributes of VI device
*
* enInputDataType: RW;RGB: CSC-709 or CSC-601, PT YUV444 disable; YUV: default yuv CSC coef PT YUV444 enable.
*/
typedef struct _VI_DEV_ATTR_EX_S {
VI_INPUT_MODE_E enInputMode; /* RW;Input mode */
VI_WORK_MODE_E enWorkMode; /* RW; Work mode */
VI_COMBINE_MODE_E enCombineMode; /* RW;Y/C composite or separation mode */
VI_COMPONENT_MODE_E enComponentMode; /* RW;Component mode (single-component or dual-component) */
VI_CLK_EDGE_E enClkEdge; /* RW;Clock edge mode (sampling on the rising or falling edge) */
CVI_U32 au32ComponentMask[VI_COMPMASK_NUM]; /* RW;Component mask */
VI_SCAN_MODE_E enScanMode; /* RW;Input scanning mode (progressive or interlaced) */
CVI_S32 as32AdChnId[VI_MAX_ADCHN_NUM]; /* RW;AD channel ID. Typically, the default value -1 is recommended */
VI_YUV_DATA_SEQ_E enDataSeq; /* RW;Input data sequence (only the YUV format is supported) */
VI_SYNC_CFG_S stSynCfg; /* RW;Sync timing. This member must be configured in BT.601 mode or DC mode */
VI_BT656_SYNC_CFG_S stBT656SynCfg; /* RW;Sync timing. This member must be configured in BT.656 mode */
VI_DATA_TYPE_E enInputDataType;
CVI_BOOL bDataReverse; /* RW;Data reverse */
SIZE_S stSize; /* RW;Input size */
VI_WDR_ATTR_S stWDRAttr; /* RW;Attribute of WDR */
} VI_DEV_ATTR_EX_S;
/* The attributes of a VI device
*
* enInputDataType: RW;RGB: CSC-709 or CSC-601, PT YUV444 disable; YUV: default yuv CSC coef PT YUV444 enable.
*/
typedef struct _VI_DEV_ATTR_S {
VI_INTF_MODE_E enIntfMode; /* RW;Interface mode */
VI_WORK_MODE_E enWorkMode; /* RW;Work mode */
VI_SCAN_MODE_E enScanMode; /* RW;Input scanning mode (progressive or interlaced) */
CVI_S32 as32AdChnId[VI_MAX_ADCHN_NUM]; /* RW;AD channel ID. Typically, the default value -1 is recommended */
/* The below members must be configured in BT.601 mode or DC mode and are invalid in other modes */
VI_YUV_DATA_SEQ_E enDataSeq; /* RW;Input data sequence (only the YUV format is supported) */
VI_SYNC_CFG_S stSynCfg; /* RW;Sync timing. This member must be configured in BT.601 mode or DC mode */
VI_DATA_TYPE_E enInputDataType;
SNR_SIZE_S stSnrSize; /* RW;Input Snr Size */
VI_WDR_ATTR_S stWDRAttr; /* RW;Attribute of WDR */
BAYER_FORMAT_E enBayerFormat; /* RW;Bayer format of Device */
CVI_U32 chn_num; /* R; total chnannels sended from dev */
CVI_U32 snrFps; /* R; snr init fps from isp pub attr */
} VI_DEV_ATTR_S;
/* Information of pipe binded to device */
typedef struct _VI_DEV_BIND_PIPE_S {
CVI_U32 u32Num; /* RW;Range [1,VI_MAX_PIPE_NUM] */
VI_PIPE PipeId[VI_MAX_PIPE_NUM]; /* RW;Array of pipe ID */
} VI_DEV_BIND_PIPE_S;
/* Source of 3DNR reference frame */
typedef enum _VI_NR_REF_SOURCE_E {
VI_NR_REF_FROM_RFR = 0, /* Reference frame from reconstruction frame */
VI_NR_REF_FROM_CHN0, /* Reference frame from CHN0's frame */
VI_NR_REF_FROM_BUTT
} VI_NR_REF_SOURCE_E;
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef enum _VI_PIPE_BYPASS_MODE_E {
VI_PIPE_BYPASS_NONE,
VI_PIPE_BYPASS_FE,
VI_PIPE_BYPASS_BE,
VI_PIPE_BYPASS_BUTT
} VI_PIPE_BYPASS_MODE_E;
// -------- If you want to change these interfaces, please contact the isp team. --------
/* The attributes of 3DNR */
typedef struct _VI_NR_ATTR_S {
PIXEL_FORMAT_E enPixFmt; /* RW;Pixel format of reference frame */
DATA_BITWIDTH_E enBitWidth; /* RW;Bit Width of reference frame */
VI_NR_REF_SOURCE_E enNrRefSource; /* RW;Source of 3DNR reference frame */
COMPRESS_MODE_E enCompressMode; /* RW;Reference frame compress mode */
} VI_NR_ATTR_S;
/* The attributes of pipe
*
* bDiscardProPic: RW;when professional mode snap, whether to discard long exposure picture in the video pipe.
*/
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef struct _VI_PIPE_ATTR_S {
VI_PIPE_BYPASS_MODE_E enPipeBypassMode;
CVI_BOOL bYuvSkip; /* RW;YUV skip enable */
CVI_BOOL bIspBypass; /* RW;ISP bypass enable */
CVI_U32 u32MaxW; /* RW;Range[VI_PIPE_MIN_WIDTH,VI_PIPE_MAX_WIDTH];Maximum width */
CVI_U32 u32MaxH; /* RW;Range[VI_PIPE_MIN_HEIGHT,VI_PIPE_MAX_HEIGHT];Maximum height */
PIXEL_FORMAT_E enPixFmt; /* RW;Pixel format */
COMPRESS_MODE_E enCompressMode; /* RW;Compress mode.*/
DATA_BITWIDTH_E enBitWidth; /* RW;Bit width*/
CVI_BOOL bNrEn; /* RW;3DNR enable */
CVI_BOOL bSharpenEn; /* RW;Sharpen enable*/
FRAME_RATE_CTRL_S stFrameRate; /* RW;Frame rate */
CVI_BOOL bDiscardProPic;
CVI_BOOL bYuvBypassPath; /* RW;ISP YUV bypass enable */
} VI_PIPE_ATTR_S;
// -------- If you want to change these interfaces, please contact the isp team. --------
// /*
// * au16TextureStr: RW; range: [0, 4095]; Format:7.5;Undirectional sharpen strength for texture and detail enhancement.
// * au16EdgeStr: RW; range: [0, 4095]; Format:7.5;Directional sharpen strength for edge enhancement.
// * u16TextureFreq: RW; range: [0, 4095]; Format:6.6; Texture frequency adjustment.
// * Texture and detail will be finer when it increase.
// * u16EdgeFreq: RW; range: [0, 4095]; Format:6.6; Edge frequency adjustment.
// * Edge will be narrower and thiner when it increase.
// * u8ShootSupStr: RW; range: [0, 255]; Format:8.0;overshoot and undershoot suppression strength,
// * the amplitude and width of shoot will be decrease when shootSupSt increase.
// */
// typedef struct _VI_PIPE_SHARPEN_MANUAL_ATTR_S {
// CVI_U16 au16TextureStr[VI_SHARPEN_GAIN_NUM];
// CVI_U16 au16EdgeStr[VI_SHARPEN_GAIN_NUM];
// CVI_U16 u16TextureFreq;
// CVI_U16 u16EdgeFreq;
// CVI_U8 u8OverShoot; /* RW; range: [0, 127]; Format:7.0;u8OvershootAmt*/
// CVI_U8 u8UnderShoot; /* RW; range: [0, 127]; Format:7.0;u8UndershootAmt*/
// CVI_U8 u8ShootSupStr;
// } VI_PIPE_SHARPEN_MANUAL_ATTR_S;
// /*
// * au16TextureStr: RW; range: [0, 4095]; Format:7.5;Undirectional sharpen strength for texture and detail enhancement.
// * au16EdgeStr: RW; range: [0, 4095]; Format:7.5;Directional sharpen strength for edge enhancement
// * au16TextureFreq: RW; range: [0, 4095]; Format:6.6;Texture frequency adjustment.
// * Texture and detail will be finer when it increase
// * au16EdgeFreq: RW; range: [0, 4095]; Format:6.6;Edge frequency adjustment.
// * Edge will be narrower and thiner when it increase
// * au8ShootSupStr: RW; range: [0, 255]; Format:8.0;overshoot and undershoot suppression strength,
// * the amplitude and width of shoot will be decrease when shootSupSt increase
// */
// typedef struct _VI_PIPE_SHARPEN_AUTO_ATTR_S {
// CVI_U16 au16TextureStr[VI_SHARPEN_GAIN_NUM][VI_AUTO_ISO_STRENGTH_NUM];
// CVI_U16 au16EdgeStr[VI_SHARPEN_GAIN_NUM][VI_AUTO_ISO_STRENGTH_NUM];
// CVI_U16 au16TextureFreq[VI_AUTO_ISO_STRENGTH_NUM];
// CVI_U16 au16EdgeFreq[VI_AUTO_ISO_STRENGTH_NUM];
// CVI_U8 au8OverShoot[VI_AUTO_ISO_STRENGTH_NUM]; /* RW; range: [0, 127]; Format:7.0;u8OvershootAmt*/
// CVI_U8 au8UnderShoot[VI_AUTO_ISO_STRENGTH_NUM]; /* RW; range: [0, 127]; Format:7.0;u8UndershootAmt*/
// CVI_U8 au8ShootSupStr[VI_AUTO_ISO_STRENGTH_NUM];
// } VI_PIPE_SHARPEN_AUTO_ATTR_S;
// typedef struct _VI_PIPE_SHARPEN_ATTR_S {
// OPERATION_MODE_E enOpType;
// CVI_U8 au8LumaWgt[VI_SHARPEN_GAIN_NUM]; /* RW; range: [0, 127]; Format:7.0;*/
// VI_PIPE_SHARPEN_MANUAL_ATTR_S stSharpenManualAttr;
// VI_PIPE_SHARPEN_AUTO_ATTR_S stSharpenAutoAttr;
// } VI_PIPE_SHARPEN_ATTR_S;
// typedef enum _VI_PIPE_REPEAT_MODE_E {
// VI_PIPE_REPEAT_NONE = 0,
// VI_PIPE_REPEAT_ONCE = 1,
// VI_PIPE_REPEAT_BUTT
// } VI_PIPE_REPEAT_MODE_E;
// /*
// * IES: RW; Range:[0,255];Format 8.0;the absolute strength of image enhancement for edge
// * IESS:RW; Range:[0,255];Format 8.0;the absolute strength of image enhancement for texture and shadow
// * IEDZ: RW; Range:[0,8192];Format 14.0;the threshold of image enhancement for controlling noise
// */
// typedef struct {
// CVI_U8 IES;
// CVI_U8 IESS;
// CVI_U16 IEDZ;
// } tV59aIEy;
// /*
// * SBF: RW; Range:[0,3];Format 2.0;the band type of spatial filter,
// * notice: SBF0,SBF1 range is [2,3];SBF2,SBF3 range is [0,3]
// * STR: RW; Range:[0,13];Format 4.0;the relative strength of spatial filter refer to the previous frame
// * STHp: RW; Range:[0,2];Format 2.0;Not recommended for debugging
// * SFT: RW; Range:[0,31];Format 5.0;Not recommended for debugging
// * kPro: RW; Range:[0,7];Format 3.0;notice: the kPro of SFy2 range is [0,7],the kPro of SFy3 range is [0,4]
// * STH: RW; Range:[0,999];Format 10.0;the edge-preserve threshold for spatial filter
// * SBS: RW; Range:[0,9999];Format 14.0;the noise reduction strength of spatial filter for the relative bright pixel
// * SDS: RW; Range:[0,9999];Format 14.0;the noise reduction strength of spatial filter for the relative dark pixel
// */
// typedef struct {
// CVI_U8 SBF : 2;
// CVI_U8 STR : 4;
// CVI_U8 STHp : 2;
// CVI_U8 SFT : 5;
// CVI_U8 kPro : 3;
// CVI_U16 STH[3];
// CVI_U16 SBS[3];
// CVI_U16 SDS[3];
// } tV59aSFy;
// typedef struct {
// CVI_U16 MATH : 10; /* RW; Range:[0,1023];Format 10.0;the motion detection threshold for temporal filter */
// CVI_U16 MATE : 4; /* RW; Range:[0,11];Format 4.0;the motion detection index of flat area for temporal filter */
// CVI_U16 MATW : 2; /* RW; Range:[0,3];Format 2.0;the index of suppressing trailing for temporal filter */
// CVI_U8 MASW : 4; /* RW; Range:[0,12];Format 4.0;the index of suppressing raindrop noise for temporal filter */
// CVI_U8 MABW : 3; /* RW; Range:[0,4];Format 3.0;the window of motion detection for temporal filter */
// CVI_U8 MAXN : 1; /* RW; Range:[0,1];Format 1.0;Not recommended for debugging */
// } tV59aMDy;
// typedef struct {
// CVI_U8 TFR[4]; /* RW; Range:[0,255];Format 8.0;the relative strength of temporal filter for the static area */
// CVI_U16 TDZ : 14; /* RW; Range:[0,999];Format 10.0;the threshold of dead-area of temporal filter */
// CVI_U16 TDX : 2; /* RW; Range:[0,2];Format 2.0;Not recommended for debugging */
// CVI_U16 TFS : 6; /* RW; Range:[0,63];Format 6.0;the absolute strength of temporal filter */
// } tV59aTFy;
// typedef struct {
// CVI_U16 SFC : 10; /* RW; Range:[0,1023];Format 10.0;the strength of spatial filter for NRC0 */
// CVI_U16 TFC : 6; /* RW; Range:[0,63];Format 6.0;the strength of temporal filter for NRC0 */
// CVI_U16 CSFS : 14; /* RW; Range:[0,999];Format 10.0;the strength of spatial filter for NRC1 */
// CVI_U16 CSFk : 2; /* RW; Range:[0,3];Format 2.0;Not recommended for debugging */
// CVI_U16 CTFS : 4; /* RW; Range:[0,15];Format 4.0;the strength of temporal filter for NRC1 */
// CVI_U16 CIIR : 1; /* RW; Range:[0,1];Format 1.0;the mode of spatial filter for NRC1 */
// CVI_U16 CTFR : 11; /* RW; Range:[0,999];Format 10.0;the relative strength of temporal filter for NRC1 */
// } tV59aNRc;
// 3DNR Spatial Filter: SFy0,SFy1,SFy2,SFy3; Temporal Filter:TFy0,TFy1;Chroma Noise Reduction: NRC0,NRC1
// *
// * HdgType: RW; Range:[0,1];Format 1.0;the type of complexed mixed spatial filter whether is SFi or SFk
// * BriType: RW; Range:[0,1];Format 1.0;the mode decide SFy3 whether is SFk type or SFi type
// * HdgMode: RW; Range:[0,3];Format 2.0;the mode decide complexed mixed spatial filter band for flat area
// * kTab2: RW; Range:[0,1];Format 1.0;the parameter decide SFy2 whether or not based on the image absolute luminance
// * HdgWnd: RW; Range:[0,1];Format 1.0;the sampling window of complexed mixed spatial filter for noise detection
// * kTab3: RW; Range:[0,1];Format 1.0;the parameter decide SFy3 whether or not based on the image absolute luminance
// * HdgSFR: RW; Range:[0,13];Format 4.0;the trend of the noise reduction of complexed mixed spatial filter for flat area
// * nOut: RW; Range:[0,27];Format 5.0;the parameter for output intermediate result of SFy3
// * HdgIES: RW; Range:[0,255];Format 8.0;the strength of image enhancement for complexed mixed spatial filter
// * nRef: RW; Range:[0,1];Format 1.0;Not recommended for debugging
// *
// * SFRi: RW; Range:[0,255];Format 8.0;the relative strength of SFy3 when the filter type is SFi
// * SFRk: RW; Range:[0,255];Format 8.0;the relative strength of SFy3 when the filter type is SFk
// * SBSk2: RW; Range:[0,9999];Format 14.0;the noise reduction strength of SFy2 for the relative bright pixel
// * based on the image absolute luminance
// * SBSk3: RW; Range:[0,9999];Format 14.0;the noise reduction strength of SFy3 for the relative bright pixel
// * based on the image absolute luminance
// * SDSk2: RW; Range:[0,9999];Format 14.0;the noise reduction strength of SFy2 for the relative dark pixel
// * based on the image absolute luminance
// * SDSk3: RW; Range:[0,9999];Format 14.0;the noise reduction strength of SFy3 for the relative dark pixel
// * based on the image absolute luminance
// * BriThr: RW; Range:[0,1024];Format 11.0;the threshold decide SFy3 choose the SFi type filter or SFk type filter
// * in dark and bright area
// *
// typedef struct {
// tV59aIEy IEy;
// tV59aSFy SFy[5];
// tV59aMDy MDy[2];
// tV59aTFy TFy[2];
// CVI_U16 HdgType : 1;
// CVI_U16 BriType : 1;
// CVI_U16 HdgMode : 2;
// CVI_U16 kTab2 : 1;
// CVI_U16 HdgWnd : 1;
// CVI_U16 kTab3 : 1;
// CVI_U16 HdgSFR : 4;
// CVI_U16 nOut : 5;
// CVI_U8 HdgIES;
// CVI_U8 nRef : 1;
// CVI_U8 IEyMode : 1;
// CVI_U8 IEyEx[4];
// CVI_U8 SFRi[4];
// CVI_U8 SFRk[4];
// CVI_U16 SBSk2[32];
// CVI_U16 SBSk3[32];
// CVI_U16 SDSk2[32];
// CVI_U16 SDSk3[32];
// CVI_U16 BriThr[16];
// tV59aNRc NRc;
// } VI_PIPE_NRX_PARAM_V1_S;
// typedef enum _VI_NR_VERSION_E { VI_NR_V1 = 1, VI_NR_V2 = 2, VI_NR_V3 = 3, VI_NR_V4 = 4, VI_NR_BUTT } VI_NR_VERSION_E;
// typedef struct _NRX_PARAM_MANUAL_V1_S {
// VI_PIPE_NRX_PARAM_V1_S stNRXParamV1;
// } NRX_PARAM_MANUAL_V1_S;
// typedef struct _NRX_PARAM_AUTO_V1_S {
// CVI_U32 u32ParamNum;
// CVI_U32 *ATTRIBUTE pau32ISO;
// VI_PIPE_NRX_PARAM_V1_S *ATTRIBUTE pastNRXParamV1;
// } NRX_PARAM_AUTO_V1_S;
// typedef struct _NRX_PARAM_V1_S {
// OPERATION_MODE_E enOptMode; /* RW;Adaptive NR */
// NRX_PARAM_MANUAL_V1_S stNRXManualV1; /* RW;NRX V1 param for manual */
// NRX_PARAM_AUTO_V1_S stNRXAutoV1; /* RW;NRX V1 param for auto */
// } NRX_PARAM_V1_S;
// typedef struct {
// CVI_U8 IES0, IES1, IES2, IES3;
// CVI_U16 IEDZ : 10, _rb_ : 6;
// } tV500_VI_IEy;
// typedef struct {
// CVI_U8 SPN6 : 3, SFR : 5;
// CVI_U8 SBN6 : 3, PBR6 : 5;
// CVI_U16 SRT0 : 5, SRT1 : 5, JMODE : 3, DeIdx : 3;
// CVI_U8 DeRate, SFR6[3];
// CVI_U8 SFS1, SFT1, SBR1;
// CVI_U8 SFS2, SFT2, SBR2;
// CVI_U8 SFS4, SFT4, SBR4;
// CVI_U16 STH1 : 9, SFN1 : 3, NRyEn : 1, SFN0 : 3;
// CVI_U16 STH2 : 9, SFN2 : 3, BWSF4 : 1, kMode : 3;
// CVI_U16 STH3 : 9, SFN3 : 3, TriTh : 1, _rb0_ : 3;
// } tV500_VI_SFy;
// typedef struct {
// tV500_VI_IEy IEy;
// tV500_VI_SFy SFy;
// } VI_PIPE_NRX_PARAM_V2_S;
// typedef struct _NRX_PARAM_MANUAL_V2_S {
// VI_PIPE_NRX_PARAM_V2_S stNRXParamV2;
// } NRX_PARAM_MANUAL_V2_S;
// typedef struct _NRX_PARAM_AUTO_V2_S {
// CVI_U32 u32ParamNum;
// CVI_U32 *ATTRIBUTE pau32ISO;
// VI_PIPE_NRX_PARAM_V2_S *ATTRIBUTE pastNRXParamV2;
// } NRX_PARAM_AUTO_V2_S;
// typedef struct _NRX_PARAM_V2_S {
// OPERATION_MODE_E enOptMode; /* RW;Adaptive NR */
// NRX_PARAM_MANUAL_V2_S stNRXManualV2; /* RW;NRX V2 param for manual */
// NRX_PARAM_AUTO_V2_S stNRXAutoV2; /* RW;NRX V2 param for auto */
// } NRX_PARAM_V2_S;
// typedef struct _VI_PIPE_NRX_PARAM_S {
// VI_NR_VERSION_E enNRVersion; /* RW;3DNR Version*/
// union {
// NRX_PARAM_V1_S stNRXParamV1; /* RW;3DNR X param version 1 */
// NRX_PARAM_V2_S stNRXParamV2; /* RW;3DNR X param version 2 */
// };
// } VI_PIPE_NRX_PARAM_S;
// /* The attributes of channel */
// typedef struct _VI_CHN_ATTR_S {
// SIZE_S stSize; /* RW;Channel out put size */
// PIXEL_FORMAT_E enPixelFormat; /* RW;Pixel format */
// DYNAMIC_RANGE_E enDynamicRange; /* RW;Dynamic Range */
// VIDEO_FORMAT_E enVideoFormat; /* RW;Video format */
// COMPRESS_MODE_E enCompressMode; /* RW;256B Segment compress or no compress. */
// CVI_BOOL bMirror; /* RW;Mirror enable */
// CVI_BOOL bFlip; /* RW;Flip enable */
// CVI_U32 u32Depth; /* RW;Range [0,8];Depth */
// FRAME_RATE_CTRL_S stFrameRate; /* RW;Frame rate */
// } VI_CHN_ATTR_S;
// /* The status of pipe */
// typedef struct _VI_PIPE_STATUS_S {
// CVI_BOOL bEnable; /* RO;Whether this pipe is enabled */
// CVI_U32 u32IntCnt; /* RO;The video frame interrupt count */
// CVI_U32 u32FrameRate; /* RO;Current frame rate */
// CVI_U32 u32LostFrame; /* RO;Lost frame count */
// CVI_U32 u32VbFail; /* RO;Video buffer malloc failure */
// SIZE_S stSize; /* RO;Current pipe output size */
// } VI_PIPE_STATUS_S;
// /* VS signal output mode */
// typedef enum _VI_VS_SIGNAL_MODE_E {
// VI_VS_SIGNAL_ONCE = 0, /* output one time */
// VI_VS_SIGNAL_FREQ, /* output frequently */
// VI_VS_SIGNAL_MODE_BUTT
// } VI_VS_SIGNAL_MODE_E;
// /* The attributes of VS signal */
// typedef struct _VI_VS_SIGNAL_ATTR_S {
// VI_VS_SIGNAL_MODE_E enMode; /* RW;output one time, output frequently*/
// CVI_U32 u32StartTime; /* RW;output start time,unit: sensor pix clk.*/
// CVI_U32 u32Duration; /* RW;output high duration, unit: sensor pix clk.*/
// CVI_U32 u32CapFrmIndex; /* RW;VS signal will be output after trigger by which vframe, default is 0. */
// CVI_U32 u32Interval; /* RW;output frequently interval, unit: frame*/
// } VI_VS_SIGNAL_ATTR_S;
// typedef enum _VI_EXT_CHN_SOURCE_E {
// VI_EXT_CHN_SOURCE_TAIL,
// VI_EXT_CHN_SOURCE_HEAD,
// VI_EXT_CHN_SOURCE_BUTT
// } VI_EXT_CHN_SOURCE_E;
// typedef struct _VI_EXT_CHN_ATTR_S {
// VI_EXT_CHN_SOURCE_E enSource;
// VI_CHN s32BindChn; /* RW;Range [VI_CHN0, VI_MAX_PHY_CHN_NUM);The channel num which extend channel will bind to*/
// SIZE_S stSize; /* RW;Channel out put size */
// PIXEL_FORMAT_E enPixelFormat; /* RW;Pixel format */
// CVI_U32 u32Depth; /* RW;Range [0,8];Depth */
// FRAME_RATE_CTRL_S stFrameRate; /* RW;Frame rate */
// } VI_EXT_CHN_ATTR_S;
// typedef enum _VI_CROP_COORDINATE_E {
// VI_CROP_RATIO_COOR = 0, /* Ratio coordinate */
// VI_CROP_ABS_COOR, /* Absolute coordinate */
// VI_CROP_BUTT
// } VI_CROP_COORDINATE_E;
// /* Information of chn crop */
// typedef struct _VI_CROP_INFO_S {
// CVI_BOOL bEnable; /* RW;CROP enable*/
// VI_CROP_COORDINATE_E enCropCoordinate; /* RW;Coordinate mode of the crop start point*/
// RECT_S stCropRect; /* RW;CROP rectangular*/
// } VI_CROP_INFO_S;
// /* The attributes of LDC */
// typedef struct _VI_LDC_ATTR_S {
// CVI_BOOL bEnable; /* RW;Whether LDC is enbale */
// LDC_ATTR_S stAttr;
// } VI_LDC_ATTR_S;
/* The status of chn */
typedef struct _VI_CHN_STATUS_S {
CVI_BOOL bEnable; /* RO;Whether this channel is enabled */
CVI_U32 u32FrameRate; /* RO;current frame rate */
CVI_U64 u64PrevTime; // latest time (us)
CVI_U32 u32FrameNum; //The number of Frame in one second
CVI_U32 u32LostFrame; /* RO;Lost frame count */
CVI_U32 u32VbFail; /* RO;Video buffer malloc failure */
CVI_U32 u32IntCnt; /* RO;Receive frame int count */
CVI_U32 u32RecvPic; /* RO;Receive frame count */
CVI_U32 u32TotalMemByte; /* RO;VI buffer malloc failure */
SIZE_S stSize; /* RO;chn output size */
} VI_CHN_STATUS_S;
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef enum _VI_DUMP_TYPE_E {
VI_DUMP_TYPE_RAW = 0,
VI_DUMP_TYPE_YUV = 1,
VI_DUMP_TYPE_IR = 2,
VI_DUMP_TYPE_BUTT
} VI_DUMP_TYPE_E;
// -------- If you want to change these interfaces, please contact the isp team. --------
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef struct _VI_DUMP_ATTR_S {
CVI_BOOL bEnable; /* RW;Whether dump is enable */
CVI_U32 u32Depth; /* RW;Range [0,8];Depth */
VI_DUMP_TYPE_E enDumpType;
} VI_DUMP_ATTR_S;
// -------- If you want to change these interfaces, please contact the isp team. --------
typedef enum _VI_PIPE_FRAME_SOURCE_E {
VI_PIPE_FRAME_SOURCE_DEV = 0, /* RW;Source from dev */
VI_PIPE_FRAME_SOURCE_USER_FE, /* RW;User send to FE */
VI_PIPE_FRAME_SOURCE_USER_BE, /* RW;User send to BE */
VI_PIPE_FRAME_SOURCE_BUTT
} VI_PIPE_FRAME_SOURCE_E;
typedef struct _VI_RAW_INFO_S {
VIDEO_FRAME_INFO_S stVideoFrame;
ISP_CONFIG_INFO_S stIspInfo;
} VI_RAW_INFO_S;
/* module params */
typedef struct _VI_MOD_PARAM_S {
CVI_S32 s32DetectErrFrame;
CVI_U32 u32DropErrFrame;
} VI_MOD_PARAM_S;
typedef struct _VI_DEV_TIMING_ATTR_S {
CVI_BOOL bEnable; /* RW;Whether enable VI generate timing */
CVI_S32 s32FrmRate; /* RW;Generate timing Frame rate*/
} VI_DEV_TIMING_ATTR_S;
typedef struct _VI_EARLY_INTERRUPT_S {
CVI_BOOL bEnable;
CVI_U32 u32LineCnt;
} VI_EARLY_INTERRUPT_S;
/* VI dump register table */
typedef struct _MLSC_GAIN_LUT_S {
CVI_U16 *RGain;
CVI_U16 *GGain;
CVI_U16 *BGain;
} MLSC_GAIN_LUT_S;
typedef struct _VI_DUMP_REGISTER_TABLE_S {
MLSC_GAIN_LUT_S MlscGainLut;
} VI_DUMP_REGISTER_TABLE_S;
typedef int (*pfnViDevPmOps)(void *pvData);
typedef struct _VI_PM_OPS_S {
pfnViDevPmOps pfnSnsSuspend;
pfnViDevPmOps pfnSnsResume;
pfnViDevPmOps pfnMipiSuspend;
pfnViDevPmOps pfnMipiResume;
} VI_PM_OPS_S;
typedef struct _VI_SMOOTH_RAW_DUMP_INFO_S {
VI_PIPE ViPipe;
CVI_U8 u8BlkCnt; // ring buffer number
CVI_U64 *phy_addr_list; // ring buffer addr
} VI_SMOOTH_RAW_DUMP_INFO_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* End of #ifndef__CVI_COMM_VIDEO_IN_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_comm_video.h
* Description:
* Common video definitions.
*/
#ifndef __CVI_COMM_VIDEO_H__
#define __CVI_COMM_VIDEO_H__
#include <cvi_type.h>
#include <cvi_common.h>
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
#define SRC_LENS_COEF_SEG 2
#define DST_LENS_COEF_SEG 3
#define SRC_LENS_COEF_NUM 4
#define DST_LENS_COEF_NUM 4
#define ISP_BAYER_CHN (4)
#define IS_FMT_YUV(fmt) \
((fmt == PIXEL_FORMAT_YUV_PLANAR_420) || (fmt == PIXEL_FORMAT_YUV_PLANAR_422) || \
(fmt == PIXEL_FORMAT_YUV_PLANAR_444) || (fmt == PIXEL_FORMAT_YUV_400) || \
(fmt == PIXEL_FORMAT_NV12) || (fmt == PIXEL_FORMAT_NV21) || \
(fmt == PIXEL_FORMAT_NV16) || (fmt == PIXEL_FORMAT_NV61) || \
(fmt == PIXEL_FORMAT_YUYV) || (fmt == PIXEL_FORMAT_UYVY) || \
(fmt == PIXEL_FORMAT_YVYU) || (fmt == PIXEL_FORMAT_VYUY))
#define IS_FMT_YUV420(fmt) \
((fmt == PIXEL_FORMAT_YUV_PLANAR_420) || \
(fmt == PIXEL_FORMAT_NV12) || (fmt == PIXEL_FORMAT_NV21) || \
(fmt == PIXEL_FORMAT_YUYV) || (fmt == PIXEL_FORMAT_UYVY) || \
(fmt == PIXEL_FORMAT_YVYU) || (fmt == PIXEL_FORMAT_VYUY))
#define IS_FMT_YUV422(fmt) \
((fmt == PIXEL_FORMAT_YUV_PLANAR_422) || \
(fmt == PIXEL_FORMAT_NV16) || (fmt == PIXEL_FORMAT_NV61))
#define IS_FRAME_OFFSET_INVALID(f) \
((f).s16OffsetLeft < 0 || (f).s16OffsetRight < 0 || \
(f).s16OffsetTop < 0 || (f).s16OffsetBottom < 0 || \
((CVI_U32)((f).s16OffsetLeft + (f).s16OffsetRight) > (f).u32Width) || \
((CVI_U32)((f).s16OffsetTop + (f).s16OffsetBottom) > (f).u32Height))
typedef enum _OPERATION_MODE_E {
OPERATION_MODE_AUTO = 0,
OPERATION_MODE_MANUAL = 1,
OPERATION_MODE_BUTT
} OPERATION_MODE_E;
/*Angle of rotation*/
typedef enum _ROTATION_E {
ROTATION_0 = 0,
ROTATION_90,
ROTATION_180,
ROTATION_270,
ROTATION_MAX
} ROTATION_E;
typedef enum _VB_SOURCE_E {
VB_SOURCE_COMMON = 0,
VB_SOURCE_MODULE = 1,
VB_SOURCE_PRIVATE = 2,
VB_SOURCE_USER = 3,
VB_SOURCE_BUTT
} VB_SOURCE_E;
typedef struct _BORDER_S {
CVI_U32 u32TopWidth;
CVI_U32 u32BottomWidth;
CVI_U32 u32LeftWidth;
CVI_U32 u32RightWidth;
CVI_U32 u32Color;
} BORDER_S;
typedef struct _POINT_S {
CVI_S32 s32X;
CVI_S32 s32Y;
} POINT_S;
typedef struct _SIZE_S {
CVI_U32 u32Width;
CVI_U32 u32Height;
} SIZE_S;
/*
* u32Width : total pixels from snr
* u32Height : total lines from snr
* u32StartX : crop x
* u32StartY : crop y
* u32ActiveW : actual video pixels
* u32ActiveH : actual video lines
*/
typedef struct _SNR_SIZE_S {
CVI_U32 u32Width;
CVI_U32 u32Height;
CVI_U32 u32StartX;
CVI_U32 u32StartY;
CVI_U32 u32ActiveW;
CVI_U32 u32ActiveH;
} SNR_SIZE_S;
typedef struct _RECT_S {
CVI_S32 s32X;
CVI_S32 s32Y;
CVI_U32 u32Width;
CVI_U32 u32Height;
} RECT_S;
typedef struct _VIDEO_REGION_INFO_S {
CVI_U32 u32RegionNum; /* W; count of the region */
RECT_S *pstRegion; /* W; region attribute */
} VIDEO_REGION_INFO_S;
typedef struct _CROP_INFO_S {
CVI_BOOL bEnable;
RECT_S stRect;
} CROP_INFO_S;
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef struct _FRAME_RATE_CTRL_S {
CVI_S32 s32SrcFrameRate; /* RW; source frame rate */
CVI_S32 s32DstFrameRate; /* RW; dest frame rate */
} FRAME_RATE_CTRL_S;
// -------- If you want to change these interfaces, please contact the isp team. --------
/*
* ASPECT_RATIO_NONE: full screen
* ASPECT_RATIO_AUTO: Keep ratio, automatically get the region of video.
* ASPECT_RATIO_MANUAL: Manully set the region of video.
*/
typedef enum _ASPECT_RATIO_E {
ASPECT_RATIO_NONE = 0,
ASPECT_RATIO_AUTO,
ASPECT_RATIO_MANUAL,
ASPECT_RATIO_MAX
} ASPECT_RATIO_E;
/*
* enMode: aspect ratio mode: none/auto/manual
* bEnableBgColor: fill bgcolor
* u32BgColor: background color, RGB 888
* stVideoRect: valid in ASPECT_RATIO_MANUAL mode
*/
typedef struct _ASPECT_RATIO_S {
ASPECT_RATIO_E enMode;
CVI_BOOL bEnableBgColor;
CVI_U32 u32BgColor;
RECT_S stVideoRect;
} ASPECT_RATIO_S;
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef enum _PIXEL_FORMAT_E {
PIXEL_FORMAT_RGB_888 = 0,
PIXEL_FORMAT_BGR_888,
PIXEL_FORMAT_RGB_888_PLANAR,
PIXEL_FORMAT_BGR_888_PLANAR,
PIXEL_FORMAT_ARGB_1555, // 4,
PIXEL_FORMAT_ARGB_4444,
PIXEL_FORMAT_ARGB_8888,
PIXEL_FORMAT_RGB_BAYER_8BPP, // 7,
PIXEL_FORMAT_RGB_BAYER_10BPP,
PIXEL_FORMAT_RGB_BAYER_12BPP,
PIXEL_FORMAT_RGB_BAYER_14BPP,
PIXEL_FORMAT_RGB_BAYER_16BPP,
PIXEL_FORMAT_YUV_PLANAR_422, // 12,
PIXEL_FORMAT_YUV_PLANAR_420,
PIXEL_FORMAT_YUV_PLANAR_444,
PIXEL_FORMAT_YUV_400,
PIXEL_FORMAT_HSV_888, // 16,
PIXEL_FORMAT_HSV_888_PLANAR,
PIXEL_FORMAT_NV12, // 18,
PIXEL_FORMAT_NV21,
PIXEL_FORMAT_NV16,
PIXEL_FORMAT_NV61,
PIXEL_FORMAT_YUYV,
PIXEL_FORMAT_UYVY,
PIXEL_FORMAT_YVYU,
PIXEL_FORMAT_VYUY,
PIXEL_FORMAT_FP32_C1 = 32, // 32
PIXEL_FORMAT_FP32_C3_PLANAR,
PIXEL_FORMAT_INT32_C1,
PIXEL_FORMAT_INT32_C3_PLANAR,
PIXEL_FORMAT_UINT32_C1,
PIXEL_FORMAT_UINT32_C3_PLANAR,
PIXEL_FORMAT_BF16_C1,
PIXEL_FORMAT_BF16_C3_PLANAR,
PIXEL_FORMAT_INT16_C1,
PIXEL_FORMAT_INT16_C3_PLANAR,
PIXEL_FORMAT_UINT16_C1,
PIXEL_FORMAT_UINT16_C3_PLANAR,
PIXEL_FORMAT_INT8_C1,
PIXEL_FORMAT_INT8_C3_PLANAR,
PIXEL_FORMAT_UINT8_C1,
PIXEL_FORMAT_UINT8_C3_PLANAR,
PIXEL_FORMAT_8BIT_MODE = 48, //48
PIXEL_FORMAT_MAX
} PIXEL_FORMAT_E;
// -------- If you want to change these interfaces, please contact the isp team. --------
/*
* VIDEO_FORMAT_LINEAR: nature video line.
*/
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef enum _VIDEO_FORMAT_E {
VIDEO_FORMAT_LINEAR = 0,
VIDEO_FORMAT_MAX
} VIDEO_FORMAT_E;
// -------- If you want to change these interfaces, please contact the isp team. --------
/*
* COMPRESS_MODE_NONE: no compress.
* COMPRESS_MODE_TILE: compress unit is a tile.
* COMPRESS_MODE_LINE: compress unit is the whole line.
* COMPRESS_MODE_FRAME: ompress unit is the whole frame.
*/
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef enum _COMPRESS_MODE_E {
COMPRESS_MODE_NONE = 0,
COMPRESS_MODE_TILE,
COMPRESS_MODE_LINE,
COMPRESS_MODE_FRAME,
COMPRESS_MODE_BUTT
} COMPRESS_MODE_E;
// -------- If you want to change these interfaces, please contact the isp team. --------
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef enum _BAYER_FORMAT_E {
BAYER_FORMAT_BG = 0,
BAYER_FORMAT_GB,
BAYER_FORMAT_GR,
BAYER_FORMAT_RG,
BAYER_FORMAT_MAX
} BAYER_FORMAT_E;
// -------- If you want to change these interfaces, please contact the isp team. --------
typedef enum _VIDEO_DISPLAY_MODE_E {
VIDEO_DISPLAY_MODE_PREVIEW = 0x0,
VIDEO_DISPLAY_MODE_PLAYBACK = 0x1,
VIDEO_DISPLAY_MODE_MAX
} VIDEO_DISPLAY_MODE_E;
/*
* u32ISO: ISP internal ISO : Again*Dgain*ISPgain
* u32ExposureTime: Exposure time (reciprocal of shutter speed),unit is us
* u32FNumber: The actual F-number (F-stop) of lens when the image was taken
* u32SensorID: which sensor is used
* u32HmaxTimes: Sensor HmaxTimes,unit is ns
* u32VcNum: when dump wdr frame, which is long or short exposure frame.
*/
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef struct _ISP_FRAME_INFO_S {
CVI_U32 u32ISO;
CVI_U32 u32ExposureTime;
CVI_U32 u32IspDgain;
CVI_U32 u32Again;
CVI_U32 u32Dgain;
CVI_U32 au32Ratio[3];
CVI_U32 u32IspNrStrength;
CVI_U32 u32FNumber;
CVI_U32 u32SensorID;
CVI_U32 u32SensorMode;
CVI_U32 u32HmaxTimes;
CVI_U32 u32VcNum;
} ISP_FRAME_INFO_S;
// -------- If you want to change these interfaces, please contact the isp team. --------
typedef struct _ISP_HDR_INFO_S {
CVI_U32 u32ColorTemp;
CVI_U16 au16CCM[9];
CVI_U8 u8Saturation;
} ISP_HDR_INFO_S;
typedef struct _ISP_ATTACH_INFO_S {
ISP_HDR_INFO_S stIspHdr;
CVI_U32 u32ISO;
CVI_U8 *u8SnsWDRMode;
} ISP_ATTACH_INFO_S;
typedef enum _FRAME_FLAG_E {
FRAME_FLAG_SNAP_FLASH = 0x1 << 0,
FRAME_FLAG_SNAP_CUR = 0x1 << 1,
FRAME_FLAG_SNAP_REF = 0x1 << 2,
FRAME_FLAG_SNAP_END = 0x1 << 31,
FRAME_FLAG_MAX
} FRAME_FLAG_E;
/* RGGB=4 */
#define ISP_WB_GAIN_NUM 4
/* 3*3=9 matrix */
#define ISP_CAP_CCM_NUM 9
typedef struct _ISP_CONFIG_INFO_S {
CVI_U32 u32ISO;
CVI_U32 u32IspDgain;
CVI_U32 u32ExposureTime;
CVI_U32 au32WhiteBalanceGain[ISP_WB_GAIN_NUM];
CVI_U32 u32ColorTemperature;
CVI_U16 au16CapCCM[ISP_CAP_CCM_NUM];
} ISP_CONFIG_INFO_S;
/*
* pJpegDCFVirAddr: JPEG_DCF_S, used in JPEG DCF
* pIspInfoVirAddr: ISP_FRAME_INFO_S, used in ISP debug, when get raw and send raw
* pLowDelayVirAddr: used in low delay
*/
typedef struct _VIDEO_SUPPLEMENT_S {
CVI_U64 u64JpegDCFPhyAddr;
CVI_U64 u64IspInfoPhyAddr;
CVI_U64 u64LowDelayPhyAddr;
CVI_U64 u64FrameDNGPhyAddr;
CVI_VOID * ATTRIBUTE pJpegDCFVirAddr;
CVI_VOID * ATTRIBUTE pIspInfoVirAddr;
CVI_VOID * ATTRIBUTE pLowDelayVirAddr;
CVI_VOID * ATTRIBUTE pFrameDNGVirAddr;
} VIDEO_SUPPLEMENT_S;
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef enum _COLOR_GAMUT_E {
COLOR_GAMUT_BT601 = 0,
COLOR_GAMUT_BT709,
COLOR_GAMUT_BT2020,
COLOR_GAMUT_USER,
COLOR_GAMUT_MAX
} COLOR_GAMUT_E;
// -------- If you want to change these interfaces, please contact the isp team. --------
typedef struct _ISP_COLORGAMMUT_INFO_S {
COLOR_GAMUT_E enColorGamut;
} ISP_COLORGAMMUT_INFO_S;
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef enum _DYNAMIC_RANGE_E {
DYNAMIC_RANGE_SDR8 = 0,
DYNAMIC_RANGE_SDR10,
DYNAMIC_RANGE_HDR10,
DYNAMIC_RANGE_HLG,
DYNAMIC_RANGE_SLF,
DYNAMIC_RANGE_XDR,
DYNAMIC_RANGE_MAX
} DYNAMIC_RANGE_E;
// -------- If you want to change these interfaces, please contact the isp team. --------
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef enum _DATA_BITWIDTH_E {
DATA_BITWIDTH_8 = 0,
DATA_BITWIDTH_10,
DATA_BITWIDTH_12,
DATA_BITWIDTH_14,
DATA_BITWIDTH_16,
DATA_BITWIDTH_MAX
} DATA_BITWIDTH_E;
// -------- If you want to change these interfaces, please contact the isp team. --------
/**
* @brief Define video frame
*
* s16OffsetTop: top offset of show area
* s16OffsetBottom: bottom offset of show area
* s16OffsetLeft: left offset of show area
* s16OffsetRight: right offset of show area
* u32FrameFlag: FRAME_FLAG_E, can be OR operation.
*/
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef struct _VIDEO_FRAME_S {
CVI_U32 u32Width;
CVI_U32 u32Height;
PIXEL_FORMAT_E enPixelFormat;
BAYER_FORMAT_E enBayerFormat;
VIDEO_FORMAT_E enVideoFormat;
COMPRESS_MODE_E enCompressMode;
DYNAMIC_RANGE_E enDynamicRange;
COLOR_GAMUT_E enColorGamut;
CVI_U32 u32Stride[3];
CVI_U64 u64PhyAddr[3];
CVI_U8 *pu8VirAddr[3];
#ifdef __arm__
__u32 u32VirAddrPadding[3];
#endif
CVI_U32 u32Length[3];
CVI_S16 s16OffsetTop;
CVI_S16 s16OffsetBottom;
CVI_S16 s16OffsetLeft;
CVI_S16 s16OffsetRight;
CVI_U32 u32TimeRef;
CVI_U64 u64PTS;
void *pPrivateData;
#ifdef __arm__
__u32 u32PrivateDataPadding;
#endif
CVI_U32 u32FrameFlag;
CVI_U32 u32DevNum;
} VIDEO_FRAME_S;
// -------- If you want to change these interfaces, please contact the isp team. --------
/**
* @brief Define the information of video frame.
*
* stVFrame: Video frame info.
* u32PoolId: VB pool ID.
*/
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef struct _VIDEO_FRAME_INFO_S {
VIDEO_FRAME_S stVFrame;
CVI_U32 u32PoolId;
} VIDEO_FRAME_INFO_S;
// -------- If you want to change these interfaces, please contact the isp team. --------
/*
* u32VBSize: size of VB needed.
* u32MainStride: stride of planar0.
* u32CStride: stride of planar1/2 if there is.
* u32MainSize: size of all planars.
* u32MainYSize: size of planar0.
* u32MainCSize: size of planar1/2 if there is.
* u16AddrAlign: address alignment needed between planar.
*/
typedef struct _VB_CAL_CONFIG_S {
CVI_U32 u32VBSize;
CVI_U32 u32MainStride;
CVI_U32 u32CStride;
CVI_U32 u32MainSize;
CVI_U32 u32MainYSize;
CVI_U32 u32MainCSize;
CVI_U16 u16AddrAlign;
CVI_U8 plane_num;
} VB_CAL_CONFIG_S;
/*
* enPixelFormat: Bitmap's pixel format
* u32Width: Bitmap's width
* u32Height: Bitmap's height
* pData: Address of Bitmap's data
*/
typedef struct _BITMAP_S {
PIXEL_FORMAT_E enPixelFormat;
CVI_U32 u32Width;
CVI_U32 u32Height;
CVI_VOID * ATTRIBUTE pData;
} BITMAP_S;
/*
*
* s32CenterXOffset: RW; Range: [-511, 511], horizontal offset of the image distortion center relative to image center
* s32CenterYOffset: RW; Range: [-511, 511], vertical offset of the image distortion center relative to image center
* s32DistortionRatio: RW; Range: [-300, 500], LDC Distortion ratio.
* When spread on,s32DistortionRatio range should be [0, 500]
*/
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef struct _LDC_ATTR_S {
CVI_BOOL bAspect; /* RW;Whether aspect ration is keep */
CVI_S32 s32XRatio; /* RW; Range: [0, 100], field angle ration of horizontal,valid when bAspect=0.*/
CVI_S32 s32YRatio; /* RW; Range: [0, 100], field angle ration of vertical,valid when bAspect=0.*/
CVI_S32 s32XYRatio; /* RW; Range: [0, 100], field angle ration of all,valid when bAspect=1.*/
CVI_S32 s32CenterXOffset;
CVI_S32 s32CenterYOffset;
CVI_S32 s32DistortionRatio;
} LDC_ATTR_S;
// -------- If you want to change these interfaces, please contact the isp team. --------
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef enum _WDR_MODE_E {
WDR_MODE_NONE = 0,
WDR_MODE_BUILT_IN,
WDR_MODE_QUDRA,
WDR_MODE_2To1_LINE,
WDR_MODE_2To1_FRAME,
WDR_MODE_2To1_FRAME_FULL_RATE,
WDR_MODE_3To1_LINE,
WDR_MODE_3To1_FRAME,
WDR_MODE_3To1_FRAME_FULL_RATE,
WDR_MODE_4To1_LINE,
WDR_MODE_4To1_FRAME,
WDR_MODE_4To1_FRAME_FULL_RATE,
WDR_MODE_MAX,
} WDR_MODE_E;
// -------- If you want to change these interfaces, please contact the isp team. --------
// ++++++++ If you want to change these interfaces, please contact the isp team. ++++++++
typedef enum _PROC_AMP_E {
PROC_AMP_BRIGHTNESS = 0,
PROC_AMP_CONTRAST,
PROC_AMP_SATURATION,
PROC_AMP_HUE,
PROC_AMP_MAX,
} PROC_AMP_E;
// -------- If you want to change these interfaces, please contact the isp team. --------
typedef struct _PROC_AMP_CTRL_S {
CVI_S32 minimum;
CVI_S32 maximum;
CVI_S32 step;
CVI_S32 default_value;
} PROC_AMP_CTRL_S;
typedef struct _VCODEC_PERF_FPS_S {
CVI_U32 u32InFPS;
CVI_U32 u32OutFPS;
CVI_U64 u64HwTime;
} VCODEC_PERF_FPS_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* _CVI_COMM_VIDEO_H_ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_common.h
* Description: Common video definitions.
*/
#ifndef __CVI_COMMON_H__
#define __CVI_COMMON_H__
#include <cvi_type.h>
#include <cvi_defines.h>
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
#ifndef __FILENAME__
#define __FILENAME__ (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__)
#endif
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
#undef ALIGN
#define ALIGN(x, a) (((x) + ((a)-1)) & ~((a)-1))
#define ATTRIBUTE __attribute__((aligned(ALIGN_NUM)))
#define CVI_INVALID_CHN (-1)
#define CVI_INVALID_LAYER (-1)
#define CVI_INVALID_DEV (-1)
#define CVI_INVALID_HANDLE (-1)
#define CVI_INVALID_VALUE (-1)
#define CVI_INVALID_TYPE (-1)
typedef CVI_S32 VI_DEV;
typedef CVI_S32 VI_PIPE;
typedef CVI_S32 VI_CHN;
typedef CVI_S32 ISP_DEV;
typedef CVI_S32 SENSOR_ID;
#define FOREACH_MOD(MOD) {\
MOD(BASE) \
MOD(VB) \
MOD(SYS) \
MOD(RGN) \
MOD(CHNL) \
MOD(VDEC) \
MOD(VPSS) \
MOD(VENC) \
MOD(H264E) \
MOD(JPEGE) \
MOD(MPEG4E) \
MOD(H265E) \
MOD(JPEGD) \
MOD(VO) \
MOD(VI) \
MOD(DIS) \
MOD(RC) \
MOD(AIO) \
MOD(AI) \
MOD(AO) \
MOD(AENC) \
MOD(ADEC) \
MOD(AUD) \
MOD(VPU) \
MOD(ISP) \
MOD(IVE) \
MOD(USER) \
MOD(PROC) \
MOD(LOG) \
MOD(H264D) \
MOD(GDC) \
MOD(PHOTO) \
MOD(FB) \
MOD(BUTT) \
}
#define GENERATE_ENUM(ENUM) CVI_ID_ ## ENUM,
typedef enum _MOD_ID_E FOREACH_MOD(GENERATE_ENUM) MOD_ID_E;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __CVI_COMMON_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_debug.h
* Description:
*/
#ifndef __CVI_DEBUG_H__
#define __CVI_DEBUG_H__
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <cvi_common.h>
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
#define syslog(...)
#define LOG_LOCAL5 5
/*
* Debug Config
*/
#define CONFIG_CVI_GDB_NO 1
#define CONFIG_CVI_GDB "n"
#define CONFIG_CVI_LOG_TRACE_SUPPORT 1
#define CONFIG_CVI_LOG_TRACE_ALL 1
#define CONFIG_CVI_LOG_TRACE_LEVEL 4
#define CVI_DBG_EMERG 0 /* system is unusable */
#define CVI_DBG_ALERT 1 /* action must be taken immediately */
#define CVI_DBG_CRIT 2 /* critical conditions */
#define CVI_DBG_ERR 3 /* error conditions */
#define CVI_DBG_WARN 4 /* warning conditions */
#define CVI_DBG_NOTICE 5 /* normal but significant condition */
#define CVI_DBG_INFO 6 /* informational */
#define CVI_DBG_DEBUG 7 /* debug-level messages */
typedef struct _LOG_LEVEL_CONF_S {
MOD_ID_E enModId;
CVI_S32 s32Level;
char cModName[16];
} LOG_LEVEL_CONF_S;
#define CVI_PRINT printf
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-variable"
static CVI_S32 *log_levels;
static CVI_CHAR const *log_name[8] = {
(CVI_CHAR *)"EMG", (CVI_CHAR *)"ALT", (CVI_CHAR *)"CRI", (CVI_CHAR *)"ERR",
(CVI_CHAR *)"WRN", (CVI_CHAR *)"NOT", (CVI_CHAR *)"INF", (CVI_CHAR *)"DBG"
};
#pragma GCC diagnostic pop
#define _GENERATE_STRING(STRING) (#STRING),
static const char *const MOD_STRING[] = FOREACH_MOD(_GENERATE_STRING);
#define CVI_GET_MOD_NAME(id) (id < CVI_ID_BUTT)? MOD_STRING[id] : "UNDEF"
/* #ifdef CVI_DEBUG */
#ifdef CONFIG_CVI_LOG_TRACE_SUPPORT
#define CVI_ASSERT(expr) \
do { \
if (!(expr)) { \
printf("\nASSERT at:\n" \
" >Function : %s\n" \
" >Line No. : %d\n" \
" >Condition: %s\n", \
__func__, __LINE__, #expr); \
_exit(-1); \
} \
} while (0)
#ifndef FPGA_PORTING
#define CVI_TRACE(level, enModId, fmt, ...) \
do { \
CVI_S32 LogLevel = (log_levels == NULL) ? CONFIG_CVI_LOG_TRACE_LEVEL : log_levels[enModId]; \
if (level <= LogLevel) { \
syslog(LOG_LOCAL5|level, "[%s-%s] " fmt, CVI_GET_MOD_NAME(enModId), log_name[level], \
##__VA_ARGS__); \
} \
} while (0)
#else
#define CVI_TRACE(level, enModId, fmt, ...) \
printf(fmt, ##__VA_ARGS__)
#endif
#else
#define CVI_ASSERT(expr)
#define CVI_TRACE(level, enModId, fmt...)
#endif
#define CVI_TRACE_ID(level, id, fmt, ...) \
CVI_TRACE(level, id, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#define CVI_TRACE_LOG(level, fmt, ...) \
CVI_TRACE(level, CVI_ID_LOG, "%s:%d:%s(): " fmt, __FILENAM__, __LINE__, __func__, ##__VA_ARGS__)
#define CVI_TRACE_SYS(level, fmt, ...) \
CVI_TRACE(level, CVI_ID_SYS, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#define CVI_TRACE_VB(level, fmt, ...) \
CVI_TRACE(level, CVI_ID_VB, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#define CVI_TRACE_SNS(level, fmt, ...) \
CVI_TRACE(level, CVI_ID_VI, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#define CVI_TRACE_VI(level, fmt, ...) \
CVI_TRACE(level, CVI_ID_VI, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#define CVI_TRACE_VPSS(level, fmt, ...) \
CVI_TRACE(level, CVI_ID_VPSS, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#define CVI_TRACE_VO(level, fmt, ...) \
CVI_TRACE(level, CVI_ID_VO, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#define CVI_TRACE_GDC(level, fmt, ...) \
CVI_TRACE(level, CVI_ID_GDC, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#define CVI_TRACE_RGN(level, fmt, ...) \
CVI_TRACE(level, CVI_ID_RGN, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#define CVI_TRACE_MISC(level, fmt, ...) \
CVI_TRACE(level, CVI_ID_SYS, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __CVI_COMM_SYS_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_defines.h
* Description:
* The common definitions per chip capability.
*/
/****************************************************************************** */
#ifndef __U_CVI_DEFINES_H__
#define __U_CVI_DEFINES_H__
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
#define CVI_CHIP_TEST 0x0
#ifndef CVI_CHIP_NAME
#ifdef __CV181X__
#define CVI_CHIP_NAME "CV181X"
#else
#define CVI_CHIP_NAME "CV180X"
#endif
#endif
#define CVI1835 0x1
#define CVI1832 0x2
#define CVI1838 0x3
#define CVI1822 0x4
#define CVI1829 0x5
#define CVI1826 0x6
#define CVI1821 0x7
#define CVI1820 0x8
#define CVI1823 0x9
#define CVI1825 0xA
#define CVIU01 0x1
#define CVIU02 0x2
#define CVI_COLDBOOT 0x1
#define CVI_WDTBOOT 0x2
#define CVI_SUSPENDBOOT 0x3
#define CVI_WARMBOOT 0x4
#define IS_CHIP_CV183X(x) (((x) == CVI1829) || ((x) == CVI1832) || ((x) == CVI1835) || ((x) == CVI1838))
#define IS_CHIP_CV182X(x) (((x) == CVI1820) || ((x) == CVI1821) || ((x) == CVI1822) \
|| ((x) == CVI1823) || ((x) == CVI1825) || ((x) == CVI1826))
#define MMF_VER_PRIX "_MMF_V"
#define ALIGN_NUM 4
#define LUMA_PHY_ALIGN 16
#define DEFAULT_ALIGN 64
#define MAX_ALIGN 1024
#define SEG_CMP_LENGTH 256
/* For VENC */
#define VENC_MAX_NAME_LEN 16
#define VENC_MAX_CHN_NUM 64
#define VEDU_IP_NUM 1
#define H264E_MAX_WIDTH 4096
#define H264E_MAX_HEIGHT 4096
#define H264E_MIN_WIDTH 114
#define H264E_MIN_HEIGHT 114
#define H265E_MAX_WIDTH 4096
#define H265E_MAX_HEIGHT 4096
#define H265E_MIN_WIDTH 114
#define H265E_MIN_HEIGHT 114
#define JPEGE_MAX_WIDTH 8192
#define JPEGE_MAX_HEIGHT 8192
#define JPEGE_MIN_WIDTH 32
#define JPEGE_MIN_HEIGHT 32
#define JPGE_MAX_NUM 1
#define VENC_MAX_ROI_NUM 8
#define H264E_MIN_HW_INDEX 0
#define H264E_MAX_HW_INDEX 11
#define H264E_MIN_VW_INDEX 0
#define H264E_MAX_VW_INDEX 3
#define VENC_QP_HISGRM_NUM 52
#define MAX_TILE_NUM 1
#define H265E_ADAPTIVE_FRAME_TYPE 4
#define H265E_ADAPTIVE_QP_TYPE 5
#define VENC_MIN_INPUT_FRAME_RATE 1
#define VENC_MAX_INPUT_FRAME_RATE 240
#define VENC_MAX_RECEIVE_SOURCE 4
#define VENC_PIC_RECEIVE_SOURCE0 0
#define VENC_PIC_RECEIVE_SOURCE1 1
#define VENC_PIC_RECEIVE_SOURCE2 2
#define VENC_PIC_RECEIVE_SOURCE3 3
#define VENC_ALIGN_W 32
#define VENC_ALIGN_H 16
/* For RC */
#define RC_TEXTURE_THR_SIZE 16
#define MIN_BITRATE 2
#define MAX_BITRATE (100*1024)
/* For VDEC */
#define VDEC_MAX_CHN_NUM 64
#define VDH_MAX_CHN_NUM 0
#define VEDU_CHN_START VDH_MAX_CHN_NUM
#define VEDU_H264D_ERRRATE 10
#define VEDU_H264D_FULLERR 100
#define H264D_ALIGN_W 64
#define H264D_ALIGN_H 64
#define H265D_ALIGN_W 64
#define H265D_ALIGN_H 64
#define JPEGD_ALIGN_W 64
#define JPEGD_ALIGN_H 16
#define JPEGD_RGB_ALIGN 16
#define H264D_ALIGN_FRM 0x1000
#define H265D_ALIGN_FRM 0x1000
#define JPEGD_ALIGN_FRM 0x1000
#define H264D_MAX_SPS 32
#define H264D_MIN_SPS 1
#define H264D_MAX_PPS 256
#define H264D_MIN_PPS 1
#define H264D_MAX_SLICE 300
#define H264D_MIN_SLICE 1
#define H265D_MAX_VPS 16
#define H265D_MIN_VPS 1
#define H265D_MAX_SPS 16
#define H265D_MIN_SPS 1
#define H265D_MAX_PPS 64
#define H265D_MIN_PPS 1
#define H265D_MAX_SLICE 200
#define H265D_MIN_SLICE 1
#define VEDU_H264D_MAX_WIDTH 2880
#define VEDU_H264D_MAX_HEIGHT 1920
#define VEDU_H264D_MIN_WIDTH 114
#define VEDU_H264D_MIN_HEIGHT 114
#define VEDU_H265D_MAX_WIDTH 2880
#define VEDU_H265D_MAX_HEIGHT 1920
#define VEDU_H265D_MIN_WIDTH 114
#define VEDU_H265D_MIN_HEIGHT 114
#define JPEGD_IP_NUM 1
#define JPEGD_MAX_WIDTH 2880
#define JPEGD_MAX_HEIGHT 1920
#define JPEGD_MIN_WIDTH 8
#define JPEGD_MIN_HEIGHT 8
/* For Region */
#define RGN_MIN_WIDTH 2
#define RGN_MIN_HEIGHT 2
#define RGN_COVER_MIN_X -8192
#define RGN_COVER_MIN_Y -8192
#define RGN_COVER_MAX_X 8190
#define RGN_COVER_MAX_Y 8190
#define RGN_COVER_MAX_WIDTH 8192
#define RGN_COVER_MAX_HEIGHT 8192
#define RGN_COVEREX_MIN_X -8192
#define RGN_COVEREX_MIN_Y -8192
#define RGN_COVEREX_MAX_X 8190
#define RGN_COVEREX_MAX_Y 8190
#define RGN_COVEREX_MAX_WIDTH 8192
#define RGN_COVEREX_MAX_HEIGHT 8192
#define RGN_OVERLAY_MIN_X 0
#define RGN_OVERLAY_MIN_Y 0
#define RGN_OVERLAY_MAX_X 8190
#define RGN_OVERLAY_MAX_Y 8190
#define RGN_OVERLAY_MAX_WIDTH 8192
#define RGN_OVERLAY_MAX_HEIGHT 8192
#define RGN_OVERLAYEX_MIN_X 0
#define RGN_OVERLAYEX_MIN_Y 0
#define RGN_OVERLAYEX_MAX_X 8190
#define RGN_OVERLAYEX_MAX_Y 8190
#define RGN_OVERLAYEX_MAX_WIDTH 8192
#define RGN_OVERLAYEX_MAX_HEIGHT 8192
#define RGN_MOSAIC_X_ALIGN 4
#define RGN_MOSAIC_Y_ALIGN 2
#define RGN_MOSAIC_WIDTH_ALIGN 4
#define RGN_MOSAIC_HEIGHT_ALIGN 4
#define RGN_MOSAIC_MIN_X 0
#define RGN_MOSAIC_MIN_Y 0
#define RGN_MOSAIC_MAX_X 8190
#define RGN_MOSAIC_MAX_Y 8190
#define RGN_MOSAIC_MIN_WIDTH 32
#define RGN_MOSAIC_MIN_HEIGHT 32
#define RGN_MOSAIC_MAX_WIDTH 8192
#define RGN_MOSAIC_MAX_HEIGHT 8192
#define SCL_MAX_GOP_INST 2
#define RGN_MAX_BUF_NUM 2
#define RGN_MAX_NUM_VPSS 8
#define RGN_MAX_NUM_VO 8
#define RGN_EX_MAX_NUM_VPSS 32
#define RGN_EX_MAX_WIDTH 2304
#define RGN_MAX_NUM 108
/*************************************/
#define VENC_MAX_SSE_NUM 8
#define CVI_MAX_SENSOR_NUM 2
/* For VI */
/* number of channel and device on video input unit of chip
* Note! VI_MAX_CHN_NUM is NOT equal to VI_MAX_DEV_NUM
* multiplied by VI_MAX_CHN_NUM, because all VI devices
* can't work at mode of 4 channels at the same time.
*/
#define VI_MAX_DEV_NUM 3
#define VI_MAX_PHY_PIPE_NUM 4
#define VI_MAX_VIR_PIPE_NUM 0
#define VI_MAX_PIPE_NUM (VI_MAX_PHY_PIPE_NUM + VI_MAX_VIR_PIPE_NUM)
#define VI_MAX_WDR_NUM 1
#define VI_MAX_VIR_CHN_NUM 2
#define VI_MAX_PHY_CHN_NUM 2
#define VI_MAX_EXT_CHN_NUM 2
#define VI_MAX_CHN_NUM (VI_MAX_PHY_CHN_NUM + VI_MAX_VIR_CHN_NUM)
#define VI_EXT_CHN_START VI_MAX_CHN_NUM
#define VI_MAX_EXTCHN_BIND_PER_CHN 1
#define VI_MAX_WDR_FRAME_NUM 2
#define VI_MAX_NODE_NUM 3
#define VIPROC_IP_NUM 1
#define VICAP_IP_NUM 1
#define VI_MAX_SPLIT_NODE_NUM 3
#define VI_DEV_MIN_WIDTH 120
#define VI_DEV_MIN_HEIGHT 120
#define VI_DEV_MAX_WIDTH 4608
#define VI_DEV_MAX_HEIGHT 4608
#define VI_FPN_MAX_WIDTH 4096
#define VI_FPN_MAX_HEIGHT VI_DEV_MAX_HEIGHT
#define VI_PIPE_OFFLINE_MIN_WIDTH 120
#define VI_PIPE_OFFLINE_MIN_HEIGHT 120
#define VI_PIPE_OFFLINE_MAX_WIDTH 4096
#define VI_PIPE_OFFLINE_MAX_HEIGHT 2160
#define VI_PIPE_ONLINE_MIN_WIDTH 120
#define VI_PIPE_ONLINE_MIN_HEIGHT 120
#define VI_PIPE_ONLINE_MAX_WIDTH 2688
#define VI_PIPE_ONLINE_MAX_HEIGHT 1944
#define VI_PIPE0_MAX_WIDTH 4096
#define VI_PIPE0_MAX_HEIGHT 2160
#define VI_PIPE1_MAX_WIDTH 4096
#define VI_PIPE1_MAX_HEIGHT 2160
#define VI_PIPE2_MAX_WIDTH 2688
#define VI_PIPE2_MAX_HEIGHT 1944
#define VI_PIPE3_MAX_WIDTH 2688
#define VI_PIPE3_MAX_HEIGHT 1944
#define VI_PIPE_WDR_FIRST_MAX_WIDTH VI_PIPE1_MAX_WIDTH
#define VI_PIPE_FUSION_MAX_WIDTH 2688
#define VI_PIPE_FUSION_MAX_HEIGHT 1944
#define VI_PHYCHN_OFFLINE_MIN_WIDTH 120
#define VI_PHYCHN_OFFLINE_MIN_HEIGHT 120
#define VI_PHYCHN_OFFLINE_MAX_WIDTH 4608
#define VI_PHYCHN_OFFLINE_MAX_HEIGHT 4608
#define VI_PHYCHN_ONLINE_MIN_WIDTH 120
#define VI_PHYCHN_ONLINE_MIN_HEIGHT 120
#define VI_PHYCHN_ONLINE_MAX_WIDTH 2048
#define VI_PHYCHN_ONLINE_MAX_HEIGHT 4608
#define VI_CMP_PARAM_SIZE 152
#define VI_PIXEL_FORMAT PIXEL_FORMAT_NV21
#define CVI_VI_VPSS_EXTRA_BUF 0
#define CVI_VI_CHN_0_BUF (2 + CVI_VI_VPSS_EXTRA_BUF)
#define CVI_VI_CHN_1_BUF (2 + CVI_VI_VPSS_EXTRA_BUF)
#define CVI_VI_CHN_2_BUF (2 + CVI_VI_VPSS_EXTRA_BUF)
#define CVI_VI_CHN_3_BUF (2 + CVI_VI_VPSS_EXTRA_BUF)
#define CVI_VI_BUF (CVI_VI_CHN_0_BUF + CVI_VI_CHN_1_BUF + CVI_VI_CHN_2_BUF + CVI_VI_CHN_3_BUF)
/* For VO */
#define VO_MIN_CHN_WIDTH 32 /* channel minimal width */
#define VO_MIN_CHN_HEIGHT 32 /* channel minimal height */
#define VO_MAX_DEV_NUM 1 /* max dev num */
#define VO_MAX_LAYER_NUM 1 /* max layer num */
#define VO_MAX_PRIORITY 1 /* max layer priority */
#define VO_MAX_CHN_NUM 1 /* max chn num */
#define VO_MAX_LAYER_IN_DEV 1 /* max layer num of each dev */
#define VO_MAX_GRAPHICS_LAYER_NUM 1
#define VO_MIN_TOLERATE 1 /* min play toleration 1ms */
#define VO_MAX_TOLERATE 100000 /* max play toleration 100s */
/* For AUDIO */
#define AI_DEV_MAX_NUM 1
#define AO_DEV_MIN_NUM 0
#define AO_DEV_MAX_NUM 2
#define AIO_MAX_NUM 2
#define AENC_MAX_CHN_NUM 2
#define ADEC_MAX_CHN_NUM 2
#define AI_MAX_CHN_NUM 2
#define AO_MAX_CHN_NUM 1
#define AO_SYSCHN_CHNID (AO_MAX_CHN_NUM - 1)
#define AIO_MAX_CHN_NUM ((AO_MAX_CHN_NUM > AI_MAX_CHN_NUM) ? AO_MAX_CHN_NUM:AI_MAX_CHN_NUM)
/* For VPSS */
#define VPSS_IP_NUM 2
#define VPSS_DEV_0 0
#define VPSS_DEV_1 1
#define VPSS_MAX_GRP_NUM 16
#define VPSS_ONLINE_GRP_0 0
#define VPSS_ONLINE_GRP_1 1
#define VPSS_MAX_PHY_CHN_NUM 4 /* sc_d, sc_v1, sc_v2, sc_v3 */
#define VPSS_MAX_CHN_NUM (VPSS_MAX_PHY_CHN_NUM)
#define VPSS_MIN_IMAGE_WIDTH 32
#define VPSS_MAX_IMAGE_WIDTH 2880
#define VPSS_MAX_IMAGE_HEIGHT 2880
#define VPSS_MAX_ZOOMIN 32
#define VPSS_MAX_ZOOMOUT 32
/*For Gdc*/
#define LDC_ALIGN 64
#define LDC_MIN_IMAGE_WIDTH 640
#define LDC_MIN_IMAGE_HEIGHT 480
#define SPREAD_MIN_IMAGE_WIDTH 640
#define SPREAD_MIN_IMAGE_HEIGHT 480
/* For GDC */
#define GDC_IP_NUM 1
#define GDC_PROC_JOB_INFO_NUM (500)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __U_CVI_DEFINES_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_errno.h
* Description:
* error code definition.
*/
#ifndef __CVI_ERRNO_H__
#define __CVI_ERRNO_H__
#include "cvi_debug.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
#ifndef CVI_ERR_APPID
#define CVI_ERR_APPID (0x00000000UL)
#endif
typedef enum _ERR_LEVEL_E {
EN_ERR_LEVEL_DEBUG = 0, /* debug-level */
EN_ERR_LEVEL_INFO, /* informational */
EN_ERR_LEVEL_NOTICE, /* normal but significant condition */
EN_ERR_LEVEL_WARNING, /* warning conditions */
EN_ERR_LEVEL_ERROR, /* error conditions */
EN_ERR_LEVEL_CRIT, /* critical conditions */
EN_ERR_LEVEL_ALERT, /* action must be taken immediately */
EN_ERR_LEVEL_FATAL, /* just for compatibility with previous version */
EN_ERR_LEVEL_BUTT
} ERR_LEVEL_E;
/****************************************************************************** */
/*|----------------------------------------------------------------|*/
/*| 11| APP_ID | MOD_ID | ERR_LEVEL | ERR_ID |*/
/*|----------------------------------------------------------------|*/
/*|<--><--6bits----><----8bits---><--3bits---><------13bits------->|*/
/*******************************************************************************/
#define CVI_DEF_ERR(module, level, errid) \
((CVI_S32)(0xC0000000UL | (CVI_ERR_APPID) | ((module) << 16) | ((level) << 13) | (errid)))
/* NOTE! the following defined all common error code, */
/*** all module must reserved 0~63 for their common error code*/
typedef enum _EN_ERR_CODE_E {
EN_ERR_INVALID_DEVID = 1, /* invalid device ID */
EN_ERR_INVALID_CHNID = 2, /* invalid channel ID*/
EN_ERR_ILLEGAL_PARAM = 3,
/* at least one parameter is illegal*/
/* eg, an illegal enumeration value */
EN_ERR_EXIST = 4, /* resource exists*/
EN_ERR_UNEXIST = 5, /* resource unexists */
EN_ERR_NULL_PTR = 6, /* using a NULL point*/
EN_ERR_NOT_CONFIG = 7,
/* try to enable or initialize system, device*/
/* or channel, before configing attribute*/
EN_ERR_NOT_SUPPORT = 8,
/* operation or type is not supported by NOW*/
EN_ERR_NOT_PERM = 9,
/* operation is not permitted*/
/* eg, try to change static attribute*/
EN_ERR_INVALID_PIPEID = 10,
/* invalid pipe ID*/
EN_ERR_INVALID_GRPID = 11,
/* invalid group ID*/
EN_ERR_NOMEM = 12,
/* failure caused by malloc memory*/
EN_ERR_NOBUF = 13,
/* failure caused by malloc buffer*/
EN_ERR_BUF_EMPTY = 14,
/* no data in buffer */
EN_ERR_BUF_FULL = 15,
/* no buffer for new data*/
EN_ERR_SYS_NOTREADY = 16,
/* System is not ready, maybe not initialized or*/
/* loaded. Returning the error code when opening*/
/* a device file failed.*/
EN_ERR_BADADDR = 17,
/* bad address,*/
/* eg. used for copy_from_user & copy_to_user*/
EN_ERR_BUSY = 18,
/* resource is busy,*/
/* eg. destroy a venc chn without unregister it */
EN_ERR_SIZE_NOT_ENOUGH = 19,
/* buffer size is smaller than the actual size required */
EN_ERR_INVALID_VB = 20,
/* invalid VB handle */
EN_ERR_BUTT = 63,
/* maximum code, private error code of all modules*/
/* must be greater than it */
} EN_ERR_CODE_E;
typedef enum _EN_VI_ERR_CODE_E {
ERR_VI_FAILED_NOT_ENABLED = 64, /* device or channel not enable*/
ERR_VI_FAILED_NOT_DISABLED, /* device not disable*/
ERR_VI_FAILED_CHN_NOT_DISABLED, /* channel not disable*/
ERR_VI_CFG_TIMEOUT, /* config timeout*/
ERR_VI_NORM_UNMATCH, /* video norm of ADC and VIU is unmatch*/
ERR_VI_INVALID_PHYCHNID, /* invalid phychn id*/
ERR_VI_FAILED_NOTBIND, /* device or channel not bind */
ERR_VI_FAILED_BINDED, /* device or channel not unbind */
ERR_VI_DIS_PROCESS_FAIL /* dis process failed */
} EN_VI_ERR_CODE_E;
typedef enum _EN_VOU_ERR_CODE_E {
EN_ERR_VO_DEV_NOT_CONFIG = 0x40,
EN_ERR_VO_DEV_NOT_ENABLED = 0x41,
EN_ERR_VO_DEV_HAS_ENABLED = 0x42,
EN_ERR_VO_LAYER_NOT_ENABLED = 0x45,
EN_ERR_VO_LAYER_NOT_DISABLED = 0x46,
EN_ERR_VO_LAYER_NOT_CONFIG = 0x47,
EN_ERR_VO_CHN_NOT_DISABLED = 0x48,
EN_ERR_VO_CHN_NOT_ENABLED = 0x49,
EN_ERR_VO_CHN_NOT_CONFIG = 0x4a,
EN_ERR_VO_WAIT_TIMEOUT = 0x4e,
EN_ERR_VO_INVALID_VFRAME = 0x4f,
EN_ERR_VO_INVALID_RECT_PARA = 0x50,
EN_ERR_VO_CHN_AREA_OVERLAP = 0x65,
EN_ERR_VO_INVALID_LAYERID = 0x66,
/* new added */
ERR_VO_BUTT
} EN_VOU_ERR_CODE_E;
#define CVI_ERR_SYS_NULL_PTR CVI_DEF_ERR(CVI_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define CVI_ERR_SYS_NOTREADY CVI_DEF_ERR(CVI_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define CVI_ERR_SYS_NOT_PERM CVI_DEF_ERR(CVI_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
#define CVI_ERR_SYS_NOMEM CVI_DEF_ERR(CVI_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define CVI_ERR_SYS_ILLEGAL_PARAM CVI_DEF_ERR(CVI_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define CVI_ERR_SYS_BUSY CVI_DEF_ERR(CVI_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define CVI_ERR_SYS_NOT_SUPPORT CVI_DEF_ERR(CVI_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
#define CVI_ERR_SYS_REMAPPING CVI_DEF_ERR(CVI_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
#define CVI_ERR_VB_NULL_PTR CVI_DEF_ERR(CVI_ID_VB, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define CVI_ERR_VB_INVALID CVI_DEF_ERR(CVI_ID_VB, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_VB)
#define CVI_ERR_VB_NOMEM CVI_DEF_ERR(CVI_ID_VB, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define CVI_ERR_VB_NOBUF CVI_DEF_ERR(CVI_ID_VB, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
#define CVI_ERR_VB_UNEXIST CVI_DEF_ERR(CVI_ID_VB, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
#define CVI_ERR_VB_ILLEGAL_PARAM CVI_DEF_ERR(CVI_ID_VB, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define CVI_ERR_VB_NOTREADY CVI_DEF_ERR(CVI_ID_VB, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define CVI_ERR_VB_BUSY CVI_DEF_ERR(CVI_ID_VB, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define CVI_ERR_VB_NOT_PERM CVI_DEF_ERR(CVI_ID_VB, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
#define CVI_ERR_VB_SIZE_NOT_ENOUGH CVI_DEF_ERR(CVI_ID_VB, EN_ERR_LEVEL_ERROR, EN_ERR_SIZE_NOT_ENOUGH)
#define CVI_ERR_VB_2MPOOLS CVI_DEF_ERR(CVI_ID_VB, EN_ERR_LEVEL_ERROR, EN_ERR_BUTT + 1)
#define CVI_ERR_VI_INVALID_PARA CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define CVI_ERR_VI_INVALID_DEVID CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
#define CVI_ERR_VI_INVALID_PIPEID CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_PIPEID)
#define CVI_ERR_VI_INVALID_CHNID CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
#define CVI_ERR_VI_INVALID_NULL_PTR CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define CVI_ERR_VI_FAILED_NOTCONFIG CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
#define CVI_ERR_VI_SYS_NOTREADY CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define CVI_ERR_VI_BUF_EMPTY CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
#define CVI_ERR_VI_BUF_FULL CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
#define CVI_ERR_VI_NOMEM CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define CVI_ERR_VI_NOT_SUPPORT CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
#define CVI_ERR_VI_BUSY CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define CVI_ERR_VI_NOT_PERM CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
#define CVI_ERR_VI_FAILED_NOT_ENABLED CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_NOT_ENABLED)
#define CVI_ERR_VI_FAILED_NOT_DISABLED CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_NOT_DISABLED)
#define CVI_ERR_VI_FAILED_CHN_NOT_DISABLED CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_CHN_NOT_DISABLED)
#define CVI_ERR_VI_CFG_TIMEOUT CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, ERR_VI_CFG_TIMEOUT)
#define CVI_ERR_VI_NORM_UNMATCH CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, ERR_VI_NORM_UNMATCH)
#define CVI_ERR_VI_INVALID_PHYCHNID CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, ERR_VI_INVALID_PHYCHNID)
#define CVI_ERR_VI_FAILED_NOTBIND CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_NOTBIND)
#define CVI_ERR_VI_FAILED_BINDED CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_BINDED)
#define CVI_ERR_VI_PIPE_EXIST CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_EXIST)
#define CVI_ERR_VI_PIPE_UNEXIST CVI_DEF_ERR(CVI_ID_VI, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
#define CVI_ERR_VPSS_NULL_PTR CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define CVI_ERR_VPSS_NOTREADY CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define CVI_ERR_VPSS_INVALID_DEVID CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
#define CVI_ERR_VPSS_INVALID_CHNID CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
#define CVI_ERR_VPSS_EXIST CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_EXIST)
#define CVI_ERR_VPSS_UNEXIST CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
#define CVI_ERR_VPSS_NOT_SUPPORT CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
#define CVI_ERR_VPSS_NOT_PERM CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
#define CVI_ERR_VPSS_NOMEM CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define CVI_ERR_VPSS_NOBUF CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
#define CVI_ERR_VPSS_ILLEGAL_PARAM CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define CVI_ERR_VPSS_BUSY CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define CVI_ERR_VPSS_BUF_EMPTY CVI_DEF_ERR(CVI_ID_VPSS, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* System define error code */
#define CVI_ERR_VO_BUSY CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define CVI_ERR_VO_NO_MEM CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define CVI_ERR_VO_NULL_PTR CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define CVI_ERR_VO_SYS_NOTREADY CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define CVI_ERR_VO_INVALID_DEVID CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
#define CVI_ERR_VO_INVALID_CHNID CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
#define CVI_ERR_VO_ILLEGAL_PARAM CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define CVI_ERR_VO_NOT_SUPPORT CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
#define CVI_ERR_VO_NOT_PERMIT CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
#define CVI_ERR_VO_INVALID_LAYERID CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_INVALID_LAYERID)
/* Device relative error code */
#define CVI_ERR_VO_DEV_NOT_CONFIG CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_CONFIG)
#define CVI_ERR_VO_DEV_NOT_ENABLED CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_ENABLED)
#define CVI_ERR_VO_DEV_HAS_ENABLED CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_HAS_ENABLED)
/* Video layer relative error code */
#define CVI_ERR_VO_VIDEO_NOT_ENABLED CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_LAYER_NOT_ENABLED)
#define CVI_ERR_VO_VIDEO_NOT_DISABLED CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_LAYER_NOT_DISABLED)
#define CVI_ERR_VO_VIDEO_NOT_CONFIG CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_LAYER_NOT_CONFIG)
/* Channel Relative error code */
#define CVI_ERR_VO_CHN_NOT_DISABLED CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_CHN_NOT_DISABLED)
#define CVI_ERR_VO_CHN_NOT_ENABLED CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_CHN_NOT_ENABLED)
#define CVI_ERR_VO_CHN_NOT_CONFIG CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_CHN_NOT_CONFIG)
#define CVI_ERR_VO_CHN_AREA_OVERLAP CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_CHN_AREA_OVERLAP)
/* MISCellaneous error code*/
#define CVI_ERR_VO_WAIT_TIMEOUT CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_WAIT_TIMEOUT)
#define CVI_ERR_VO_INVALID_VFRAME CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_INVALID_VFRAME)
#define CVI_ERR_VO_INVALID_RECT_PARA CVI_DEF_ERR(CVI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_INVALID_RECT_PARA)
/* failure caused by malloc buffer */
#define CVI_ERR_GDC_NOBUF CVI_DEF_ERR(CVI_ID_GDC, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
#define CVI_ERR_GDC_NOMEM CVI_DEF_ERR(CVI_ID_GDC, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define CVI_ERR_GDC_BUF_EMPTY CVI_DEF_ERR(CVI_ID_GDC, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
#define CVI_ERR_GDC_NULL_PTR CVI_DEF_ERR(CVI_ID_GDC, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define CVI_ERR_GDC_ILLEGAL_PARAM CVI_DEF_ERR(CVI_ID_GDC, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define CVI_ERR_GDC_BUF_FULL CVI_DEF_ERR(CVI_ID_GDC, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
#define CVI_ERR_GDC_SYS_NOTREADY CVI_DEF_ERR(CVI_ID_GDC, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define CVI_ERR_GDC_NOT_SUPPORT CVI_DEF_ERR(CVI_ID_GDC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
#define CVI_ERR_GDC_NOT_PERMITTED CVI_DEF_ERR(CVI_ID_GDC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
#define CVI_ERR_GDC_BUSY CVI_DEF_ERR(CVI_ID_GDC, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define CVI_ERR_RGN_SYS_NOTREADY CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
/* PingPong buffer change when set attr, it needs to remap memory */
#define CVI_NOTICE_RGN_BUFFER_CHANGE CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_NOTICE, CVI_SUCCESS)
/* invalid device ID */
#define CVI_ERR_RGN_INVALID_DEVID CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
/* invalid channel ID */
#define CVI_ERR_RGN_INVALID_CHNID CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
/* at least one parameter is illegal ,eg, an illegal enumeration value */
#define CVI_ERR_RGN_ILLEGAL_PARAM CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
/* channel exists */
#define CVI_ERR_RGN_EXIST CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_EXIST)
/* region unexist */
#define CVI_ERR_RGN_UNEXIST CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
/* using a NULL point */
#define CVI_ERR_RGN_NULL_PTR CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
/* try to enable or initialize system, device or channel, before config attribute */
#define CVI_ERR_RGN_NOT_CONFIG CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
/* operation is not supported by NOW */
#define CVI_ERR_RGN_NOT_SUPPORT CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
/* operation is not permitted ,eg, try to change static attribute */
#define CVI_ERR_RGN_NOT_PERM CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
/* failure caused by malloc memory */
#define CVI_ERR_RGN_NOMEM CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
/* failure caused by malloc buffer */
#define CVI_ERR_RGN_NOBUF CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
/* no data in buffer */
#define CVI_ERR_RGN_BUF_EMPTY CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* no buffer for new data */
#define CVI_ERR_RGN_BUF_FULL CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
/* bad address, eg. used for copy_from_user & copy_to_user */
#define CVI_ERR_RGN_BADADDR CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_BADADDR)
/* resource is busy, eg. destroy a venc chn without unregistering it */
#define CVI_ERR_RGN_BUSY CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
/* System is not ready,maybe not initialized or loaded.
* Returning the error code when opening a device file failed.
*/
#define CVI_ERR_RGN_NOTREADY CVI_DEF_ERR(CVI_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __CVI_ERRNO_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2022. All rights reserved.
*
* File Name: include/cvi_isp.h
* Description:
*/
#ifndef __CVI_ISP_H__
#define __CVI_ISP_H__
#include "stdio.h"
#include "cvi_comm_isp.h"
#include "cvi_comm_3a.h"
#include "cvi_comm_sns.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
/* Firmware Main Operation */
CVI_S32 CVI_ISP_Init(VI_PIPE ViPipe);
CVI_S32 CVI_ISP_MemInit(VI_PIPE ViPipe);
CVI_S32 CVI_ISP_Run(VI_PIPE ViPipe);
CVI_S32 CVI_ISP_RunOnce(VI_PIPE ViPipe);
CVI_S32 CVI_ISP_Exit(VI_PIPE ViPipe);
/* Each Param set / get Operation */
CVI_S32 CVI_ISP_SetPubAttr(VI_PIPE ViPipe, const ISP_PUB_ATTR_S *pstPubAttr);
CVI_S32 CVI_ISP_GetPubAttr(VI_PIPE ViPipe, ISP_PUB_ATTR_S *pstPubAttr);
CVI_S32 CVI_ISP_SetModParam(const ISP_MOD_PARAM_S *pstModParam);
CVI_S32 CVI_ISP_GetModParam(ISP_MOD_PARAM_S *pstModParam);
CVI_S32 CVI_ISP_SetCtrlParam(VI_PIPE ViPipe,
const ISP_CTRL_PARAM_S *pstIspCtrlParam);
CVI_S32 CVI_ISP_GetCtrlParam(VI_PIPE ViPipe, ISP_CTRL_PARAM_S *pstIspCtrlParam);
CVI_S32 CVI_ISP_SetFMWState(VI_PIPE ViPipe, const ISP_FMW_STATE_E enState);
CVI_S32 CVI_ISP_GetFMWState(VI_PIPE ViPipe, ISP_FMW_STATE_E *penState);
/* sensor related register */
CVI_S32 CVI_ISP_SensorRegCallBack(VI_PIPE ViPipe,
ISP_SNS_ATTR_INFO_S *pstSnsAttrInfo, ISP_SENSOR_REGISTER_S *pstRegister);
CVI_S32 CVI_ISP_SensorUnRegCallBack(VI_PIPE ViPipe, SENSOR_ID SensorId);
/* 3a algo &static related function. */
CVI_S32 CVI_AWB_Register(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib);
CVI_S32 CVI_AWB_UnRegister(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib);
CVI_S32 CVI_ISP_AELibRegCallBack(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib,
ISP_AE_REGISTER_S *pstRegister);
CVI_S32 CVI_ISP_AELibUnRegCallBack(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib);
CVI_S32 CVI_ISP_AWBLibRegCallBack(VI_PIPE ViPipe, ALG_LIB_S *pstAwbLib,
ISP_AWB_REGISTER_S *pstRegister);
CVI_S32 CVI_ISP_AWBLibUnRegCallBack(VI_PIPE ViPipe, ALG_LIB_S *pstAwbLib);
CVI_S32 CVI_ISP_AFLibRegCallBack(VI_PIPE ViPipe, ALG_LIB_S *pstAfLib,
ISP_AF_REGISTER_S *pstRegister);
CVI_S32 CVI_ISP_AFLibUnRegCallBack(VI_PIPE ViPipe, ALG_LIB_S *pstAwbLib);
CVI_S32 CVI_ISP_SetBindAttr(VI_PIPE ViPipe, const ISP_BIND_ATTR_S *pstBindAttr);
CVI_S32 CVI_ISP_GetBindAttr(VI_PIPE ViPipe, ISP_BIND_ATTR_S *pstBindAttr);
CVI_S32 CVI_ISP_SetModuleControl(VI_PIPE ViPipe, const ISP_MODULE_CTRL_U *punModCtrl);
CVI_S32 CVI_ISP_GetModuleControl(VI_PIPE ViPipe, ISP_MODULE_CTRL_U *punModCtrl);
CVI_S32 CVI_ISP_SetRegister(VI_PIPE ViPipe, CVI_U32 u32Addr, CVI_U32 u32Value);
CVI_S32 CVI_ISP_GetRegister(VI_PIPE ViPipe, CVI_U32 u32Addr, CVI_U32 *pu32Value);
//-----------------------------------------------------------------------------
// Black Level Correction(BLC)
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetBlackLevelAttr(VI_PIPE ViPipe, const ISP_BLACK_LEVEL_ATTR_S *pstBlackLevelAttr);
CVI_S32 CVI_ISP_GetBlackLevelAttr(VI_PIPE ViPipe, ISP_BLACK_LEVEL_ATTR_S *pstBlackLevelAttr);
//-----------------------------------------------------------------------------
// Dead pixel correction(DPC)
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetDPDynamicAttr(VI_PIPE ViPipe, const ISP_DP_DYNAMIC_ATTR_S *pstDPCDynamicAttr);
CVI_S32 CVI_ISP_GetDPDynamicAttr(VI_PIPE ViPipe, ISP_DP_DYNAMIC_ATTR_S *pstDPCDynamicAttr);
CVI_S32 CVI_ISP_SetDPStaticAttr(VI_PIPE ViPipe, const ISP_DP_STATIC_ATTR_S *pstDPStaticAttr);
CVI_S32 CVI_ISP_GetDPStaticAttr(VI_PIPE ViPipe, ISP_DP_STATIC_ATTR_S *pstDPStaticAttr);
CVI_S32 CVI_ISP_SetDPCalibrate(VI_PIPE ViPipe, const ISP_DP_CALIB_ATTR_S *pstDPCalibAttr);
CVI_S32 CVI_ISP_GetDPCalibrate(VI_PIPE ViPipe, ISP_DP_CALIB_ATTR_S *pstDPCalibAttr);
//-----------------------------------------------------------------------------
// Crosstalk
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetCrosstalkAttr(VI_PIPE ViPipe, const ISP_CROSSTALK_ATTR_S *pstCrosstalkAttr);
CVI_S32 CVI_ISP_GetCrosstalkAttr(VI_PIPE ViPipe, ISP_CROSSTALK_ATTR_S *pstCrosstalkAttr);
//-----------------------------------------------------------------------------
// Bayer domain noise reduction (BNR)
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetNRAttr(VI_PIPE ViPipe, const ISP_NR_ATTR_S *pstNRAttr);
CVI_S32 CVI_ISP_GetNRAttr(VI_PIPE ViPipe, ISP_NR_ATTR_S *pstNRAttr);
CVI_S32 CVI_ISP_SetNRFilterAttr(VI_PIPE ViPipe, const ISP_NR_FILTER_ATTR_S *pstNRFilterAttr);
CVI_S32 CVI_ISP_GetNRFilterAttr(VI_PIPE ViPipe, ISP_NR_FILTER_ATTR_S *pstNRFilterAttr);
//-----------------------------------------------------------------------------
// Demosaic
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetDemosaicAttr(VI_PIPE ViPipe, const ISP_DEMOSAIC_ATTR_S *pstDemosaicAttr);
CVI_S32 CVI_ISP_GetDemosaicAttr(VI_PIPE ViPipe, ISP_DEMOSAIC_ATTR_S *pstDemosaicAttr);
CVI_S32 CVI_ISP_SetDemosaicDemoireAttr(VI_PIPE ViPipe, const ISP_DEMOSAIC_DEMOIRE_ATTR_S *pstDemosaicDemoireAttr);
CVI_S32 CVI_ISP_GetDemosaicDemoireAttr(VI_PIPE ViPipe, ISP_DEMOSAIC_DEMOIRE_ATTR_S *pstDemosaicDemoireAttr);
//-----------------------------------------------------------------------------
// RGBCAC
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetRGBCACAttr(VI_PIPE ViPipe, const ISP_RGBCAC_ATTR_S *pstRGBCACAttr);
CVI_S32 CVI_ISP_GetRGBCACAttr(VI_PIPE ViPipe, ISP_RGBCAC_ATTR_S *pstRGBCACAttr);
//-----------------------------------------------------------------------------
// LCAC
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetLCACAttr(VI_PIPE ViPipe, const ISP_LCAC_ATTR_S *pstLCACAttr);
CVI_S32 CVI_ISP_GetLCACAttr(VI_PIPE ViPipe, ISP_LCAC_ATTR_S *pstLCACAttr);
//-----------------------------------------------------------------------------
// Mesh lens shading correction (MLSC)
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetMeshShadingAttr(VI_PIPE ViPipe, const ISP_MESH_SHADING_ATTR_S *pstMeshShadingAttr);
CVI_S32 CVI_ISP_GetMeshShadingAttr(VI_PIPE ViPipe, ISP_MESH_SHADING_ATTR_S *pstMeshShadingAttr);
CVI_S32 CVI_ISP_SetMeshShadingGainLutAttr(VI_PIPE ViPipe,
const ISP_MESH_SHADING_GAIN_LUT_ATTR_S *pstMeshShadingGainLutAttr);
CVI_S32 CVI_ISP_GetMeshShadingGainLutAttr(VI_PIPE ViPipe,
ISP_MESH_SHADING_GAIN_LUT_ATTR_S *pstMeshShadingGainLutAttr);
//-----------------------------------------------------------------------------
// CCM
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetSaturationAttr(VI_PIPE ViPipe, const ISP_SATURATION_ATTR_S *pstSaturationAttr);
CVI_S32 CVI_ISP_GetSaturationAttr(VI_PIPE ViPipe, ISP_SATURATION_ATTR_S *pstSaturationAttr);
CVI_S32 CVI_ISP_SetCCMSaturationAttr(VI_PIPE ViPipe, const ISP_CCM_SATURATION_ATTR_S *pstCCMSaturationAttr);
CVI_S32 CVI_ISP_GetCCMSaturationAttr(VI_PIPE ViPipe, ISP_CCM_SATURATION_ATTR_S *pstCCMSaturationAttr);
CVI_S32 CVI_ISP_SetCCMAttr(VI_PIPE ViPipe, const ISP_CCM_ATTR_S *pstCCMAttr);
CVI_S32 CVI_ISP_GetCCMAttr(VI_PIPE ViPipe, ISP_CCM_ATTR_S *pstCCMAttr);
//-----------------------------------------------------------------------------
// CSC
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetCSCAttr(VI_PIPE ViPipe, const ISP_CSC_ATTR_S *pstCSCAttr);
CVI_S32 CVI_ISP_GetCSCAttr(VI_PIPE ViPipe, ISP_CSC_ATTR_S *pstCSCAttr);
//-----------------------------------------------------------------------------
// Color tone
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetColorToneAttr(VI_PIPE ViPipe,
const ISP_COLOR_TONE_ATTR_S *pstColorToneAttr);
CVI_S32 CVI_ISP_GetColorToneAttr(VI_PIPE ViPipe, ISP_COLOR_TONE_ATTR_S *pstColorToneAttr);
//-----------------------------------------------------------------------------
// FSWDR
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetFSWDRAttr(VI_PIPE ViPipe, const ISP_FSWDR_ATTR_S *pstFSWDRAttr);
CVI_S32 CVI_ISP_GetFSWDRAttr(VI_PIPE ViPipe, ISP_FSWDR_ATTR_S *pstFSWDRAttr);
//-----------------------------------------------------------------------------
// DRC
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetDRCAttr(VI_PIPE ViPipe, const ISP_DRC_ATTR_S *pstDRCAttr);
CVI_S32 CVI_ISP_GetDRCAttr(VI_PIPE ViPipe, ISP_DRC_ATTR_S *pstDRCAttr);
//-----------------------------------------------------------------------------
// Gamma
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetGammaAttr(VI_PIPE ViPipe, const ISP_GAMMA_ATTR_S *pstGammaAttr);
CVI_S32 CVI_ISP_GetGammaAttr(VI_PIPE ViPipe, ISP_GAMMA_ATTR_S *pstGammaAttr);
CVI_S32 CVI_ISP_GetGammaCurveByType(VI_PIPE ViPipe, ISP_GAMMA_ATTR_S *pstGammaAttr,
const ISP_GAMMA_CURVE_TYPE_E curveType);
CVI_S32 CVI_ISP_SetAutoGammaAttr(VI_PIPE ViPipe, const ISP_AUTO_GAMMA_ATTR_S *pstGammaAttr);
CVI_S32 CVI_ISP_GetAutoGammaAttr(VI_PIPE ViPipe, ISP_AUTO_GAMMA_ATTR_S *pstGammaAttr);
//-----------------------------------------------------------------------------
// Dehaze
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetDehazeAttr(VI_PIPE ViPipe,
const ISP_DEHAZE_ATTR_S *pstDehazeAttr);
CVI_S32 CVI_ISP_GetDehazeAttr(VI_PIPE ViPipe, ISP_DEHAZE_ATTR_S *pstDehazeAttr);
//-----------------------------------------------------------------------------
// CLUT
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetClutAttr(VI_PIPE ViPipe, const ISP_CLUT_ATTR_S *pstClutAttr);
CVI_S32 CVI_ISP_GetClutAttr(VI_PIPE ViPipe, ISP_CLUT_ATTR_S *pstClutAttr);
CVI_S32 CVI_ISP_SetClutSaturationAttr(VI_PIPE ViPipe, const ISP_CLUT_SATURATION_ATTR_S *pstClutSaturationAttr);
CVI_S32 CVI_ISP_GetClutSaturationAttr(VI_PIPE ViPipe, ISP_CLUT_SATURATION_ATTR_S *pstClutSaturationAttr);
//-----------------------------------------------------------------------------
// DCI
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetDCIAttr(VI_PIPE ViPipe, const ISP_DCI_ATTR_S *pstDCIAttr);
CVI_S32 CVI_ISP_GetDCIAttr(VI_PIPE ViPipe, ISP_DCI_ATTR_S *pstDCIAttr);
//-----------------------------------------------------------------------------
// LDCI
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetLDCIAttr(VI_PIPE ViPipe, const ISP_LDCI_ATTR_S *pstLDCIAttr);
CVI_S32 CVI_ISP_GetLDCIAttr(VI_PIPE ViPipe, ISP_LDCI_ATTR_S *pstLDCIAttr);
//-----------------------------------------------------------------------------
// CA (CA/CP)
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetCAAttr(VI_PIPE ViPipe, const ISP_CA_ATTR_S *pstCAAttr);
CVI_S32 CVI_ISP_GetCAAttr(VI_PIPE ViPipe, ISP_CA_ATTR_S *pstCAAttr);
//-----------------------------------------------------------------------------
// CA2
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetCA2Attr(VI_PIPE ViPipe, const ISP_CA2_ATTR_S *pstCA2Attr);
CVI_S32 CVI_ISP_GetCA2Attr(VI_PIPE ViPipe, ISP_CA2_ATTR_S *pstCA2Attr);
//-----------------------------------------------------------------------------
// PreSharpen
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetPreSharpenAttr(VI_PIPE ViPipe, const ISP_PRESHARPEN_ATTR_S *pstPreSharpenAttr);
CVI_S32 CVI_ISP_GetPreSharpenAttr(VI_PIPE ViPipe, ISP_PRESHARPEN_ATTR_S *pstPreSharpenAttr);
//-----------------------------------------------------------------------------
// Time-domain noise reduction (TNR)
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetTNRAttr(VI_PIPE ViPipe, const ISP_TNR_ATTR_S *pstTNRAttr);
CVI_S32 CVI_ISP_GetTNRAttr(VI_PIPE ViPipe, ISP_TNR_ATTR_S *pstTNRAttr);
CVI_S32 CVI_ISP_SetTNRNoiseModelAttr(VI_PIPE ViPipe, const ISP_TNR_NOISE_MODEL_ATTR_S *pstTNRNoiseModelAttr);
CVI_S32 CVI_ISP_GetTNRNoiseModelAttr(VI_PIPE ViPipe, ISP_TNR_NOISE_MODEL_ATTR_S *pstTNRNoiseModelAttr);
CVI_S32 CVI_ISP_SetTNRLumaMotionAttr(VI_PIPE ViPipe, const ISP_TNR_LUMA_MOTION_ATTR_S *pstTNRLumaMotionAttr);
CVI_S32 CVI_ISP_GetTNRLumaMotionAttr(VI_PIPE ViPipe, ISP_TNR_LUMA_MOTION_ATTR_S *pstTNRLumaMotionAttr);
CVI_S32 CVI_ISP_SetTNRGhostAttr(VI_PIPE ViPipe, const ISP_TNR_GHOST_ATTR_S *pstTNRGhostAttr);
CVI_S32 CVI_ISP_GetTNRGhostAttr(VI_PIPE ViPipe, ISP_TNR_GHOST_ATTR_S *pstTNRGhostAttr);
CVI_S32 CVI_ISP_SetTNRMtPrtAttr(VI_PIPE ViPipe, const ISP_TNR_MT_PRT_ATTR_S *pstTNRMtPrtAttr);
CVI_S32 CVI_ISP_GetTNRMtPrtAttr(VI_PIPE ViPipe, ISP_TNR_MT_PRT_ATTR_S *pstTNRMtPrtAttr);
CVI_S32 CVI_ISP_SetTNRMotionAdaptAttr(VI_PIPE ViPipe, const ISP_TNR_MOTION_ADAPT_ATTR_S *pstTNRMotionAdaptAttr);
CVI_S32 CVI_ISP_GetTNRMotionAdaptAttr(VI_PIPE ViPipe, ISP_TNR_MOTION_ADAPT_ATTR_S *pstTNRMotionAdaptAttr);
//-----------------------------------------------------------------------------
// Y domain noise reduction (YNR)
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetYNRAttr(VI_PIPE ViPipe, const ISP_YNR_ATTR_S *pstYNRAttr);
CVI_S32 CVI_ISP_GetYNRAttr(VI_PIPE ViPipe, ISP_YNR_ATTR_S *pstYNRAttr);
CVI_S32 CVI_ISP_SetYNRMotionNRAttr(VI_PIPE ViPipe, const ISP_YNR_MOTION_NR_ATTR_S *pstYNRMotionNRAttr);
CVI_S32 CVI_ISP_GetYNRMotionNRAttr(VI_PIPE ViPipe, ISP_YNR_MOTION_NR_ATTR_S *pstYNRMotionNRAttr);
CVI_S32 CVI_ISP_SetYNRFilterAttr(VI_PIPE ViPipe, const ISP_YNR_FILTER_ATTR_S *pstYNRFilterAttr);
CVI_S32 CVI_ISP_GetYNRFilterAttr(VI_PIPE ViPipe, ISP_YNR_FILTER_ATTR_S *pstYNRFilterAttr);
//-----------------------------------------------------------------------------
// UV domain noise reduction (CNR)
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetCNRAttr(VI_PIPE ViPipe, const ISP_CNR_ATTR_S *pstCNRAttr);
CVI_S32 CVI_ISP_GetCNRAttr(VI_PIPE ViPipe, ISP_CNR_ATTR_S *pstCNRAttr);
CVI_S32 CVI_ISP_SetCNRMotionNRAttr(VI_PIPE ViPipe, const ISP_CNR_MOTION_NR_ATTR_S *pstCNRMotionNRAttr);
CVI_S32 CVI_ISP_GetCNRMotionNRAttr(VI_PIPE ViPipe, ISP_CNR_MOTION_NR_ATTR_S *pstCNRMotionNRAttr);
//-----------------------------------------------------------------------------
// CAC
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetCACAttr(VI_PIPE ViPipe, const ISP_CAC_ATTR_S *pstCACAttr);
CVI_S32 CVI_ISP_GetCACAttr(VI_PIPE ViPipe, ISP_CAC_ATTR_S *pstCACAttr);
//-----------------------------------------------------------------------------
// Sharpen
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetSharpenAttr(VI_PIPE ViPipe, const ISP_SHARPEN_ATTR_S *pstSharpenAttr);
CVI_S32 CVI_ISP_GetSharpenAttr(VI_PIPE ViPipe, ISP_SHARPEN_ATTR_S *pstSharpenAttr);
//-----------------------------------------------------------------------------
// Y Contrast
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetYContrastAttr(VI_PIPE ViPipe, const ISP_YCONTRAST_ATTR_S *pstYContrastAttr);
CVI_S32 CVI_ISP_GetYContrastAttr(VI_PIPE ViPipe, ISP_YCONTRAST_ATTR_S *pstYContrastAttr);
//-----------------------------------------------------------------------------
// Mono
//-----------------------------------------------------------------------------
CVI_S32 CVI_ISP_SetMonoAttr(VI_PIPE ViPipe, const ISP_MONO_ATTR_S *pstMonoAttr);
CVI_S32 CVI_ISP_GetMonoAttr(VI_PIPE ViPipe, ISP_MONO_ATTR_S *pstMonoAttr);
CVI_S32 CVI_ISP_SetStatisticsConfig(VI_PIPE ViPipe, const ISP_STATISTICS_CFG_S *pstStatCfg);
CVI_S32 CVI_ISP_GetStatisticsConfig(VI_PIPE ViPipe, ISP_STATISTICS_CFG_S *pstStatCfg);
CVI_S32 CVI_ISP_GetAEStatistics(VI_PIPE ViPipe, ISP_AE_STATISTICS_S *pstAeStat);
CVI_S32 CVI_ISP_GetWBStatistics(VI_PIPE ViPipe, ISP_WB_STATISTICS_S *pstWBStat);
CVI_S32 CVI_ISP_GetFocusStatistics(VI_PIPE ViPipe, ISP_AF_STATISTICS_S *pstAfStat);
CVI_S32 CVI_ISP_GetLightboxGain(VI_PIPE ViPipe, ISP_AWB_LightBox_Gain_S *pstAWBLightBoxGain);
CVI_S32 CVI_ISP_SetNoiseProfileAttr(VI_PIPE ViPipe, const ISP_CMOS_NOISE_CALIBRATION_S *pstNoiseProfileAttr);
CVI_S32 CVI_ISP_GetNoiseProfileAttr(VI_PIPE ViPipe, ISP_CMOS_NOISE_CALIBRATION_S *pstNoiseProfileAttr);
/* MIPI related function. */
CVI_S32 CVI_MIPI_SetMipiReset(CVI_S32 devno, CVI_U32 reset);
CVI_S32 CVI_MIPI_SetSensorClock(CVI_S32 devno, CVI_U32 enable);
CVI_S32 CVI_MIPI_SetSensorReset(CVI_S32 devno, CVI_U32 reset);
CVI_S32 CVI_MIPI_SetMipiAttr(CVI_S32 ViPipe, const CVI_VOID *devAttr);
CVI_S32 CVI_MIPI_SetClkEdge(CVI_S32 devno, CVI_U32 is_up);
CVI_S32 CVI_MIPI_SetSnsMclk(SNS_MCLK_S *mclk);
CVI_S32 CVI_ISP_QueryInnerStateInfo(VI_PIPE ViPipe, ISP_INNER_STATE_INFO_S *pstInnerStateInfo);
CVI_S32 CVI_ISP_GetVDTimeOut(VI_PIPE ViPipe, ISP_VD_TYPE_E enIspVDType, CVI_U32 u32MilliSec);
//CVI_S32 CVI_ISP_GetAEStitchStatistics(VI_PIPE ViPipe, ISP_AE_STITCH_STATISTICS_S *pstStitchStat);
//CVI_S32 CVI_ISP_GetMGStatistics(VI_PIPE ViPipe, ISP_MG_STATISTICS_S *pstMgStat);
//CVI_S32 CVI_ISP_GetWBStitchStatistics(VI_PIPE ViPipe, ISP_WB_STITCH_STATISTICS_S *pstStitchWBStat);
CVI_S32 CVI_ISP_SetDisAttr(VI_PIPE ViPipe, const ISP_DIS_ATTR_S *pstDisAttr);
CVI_S32 CVI_ISP_GetDisAttr(VI_PIPE ViPipe, ISP_DIS_ATTR_S *pstDisAttr);
CVI_S32 CVI_ISP_SetDisConfig(VI_PIPE ViPipe, const ISP_DIS_CONFIG_S *pstDisConfig);
CVI_S32 CVI_ISP_GetDisConfig(VI_PIPE ViPipe, ISP_DIS_CONFIG_S *pstDisConfig);
CVI_S32 CVI_ISP_SetVCAttr(VI_PIPE ViPipe, const ISP_VC_ATTR_S *pstVCAttr);
CVI_S32 CVI_ISP_GetVCAttr(VI_PIPE ViPipe, ISP_VC_ATTR_S *pstVCAttr);
CVI_S32 CVI_ISP_DumpHwRegisterToFile(VI_PIPE ViPipe, FILE *fp);
CVI_S32 CVI_ISP_DumpFrameRawInfoToFile(VI_PIPE ViPipe, FILE *fp);
CVI_S32 CVI_ISP_IrAutoRunOnce(ISP_DEV IspDev, ISP_IR_AUTO_ATTR_S *pstIrAttr);
CVI_S32 CVI_ISP_SetSmartInfo(VI_PIPE ViPipe, const ISP_SMART_INFO_S *pstSmartInfo, CVI_U8 TimeOut);
CVI_S32 CVI_ISP_GetSmartInfo(VI_PIPE ViPipe, ISP_SMART_INFO_S *pstSmartInfo);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /*__CVI_ISP_H__ */

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#ifndef CVI_LIST_H
#define CVI_LIST_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Get offset of a member variable.
*
* @param[in] type the type of the struct this is embedded in.
* @param[in] member the name of the variable within the struct.
*/
#define cvi_offsetof(type, member) ((size_t)&(((type *)0)->member))
/*
* Get the struct for this entry.
*
* @param[in] ptr the list head to take the element from.
* @param[in] type the type of the struct this is embedded in.
* @param[in] member the name of the variable within the struct.
*/
#define cvi_container_of(ptr, type, member) \
((type *) ((char *) (ptr) - cvi_offsetof(type, member)))
/* for double link list */
typedef struct dlist_s {
struct dlist_s *prev;
struct dlist_s *next;
} dlist_t;
static inline void __dlist_add(dlist_t *node, dlist_t *prev, dlist_t *next)
{
node->next = next;
node->prev = prev;
prev->next = node;
next->prev = node;
}
/*
* Get the struct for this entry.
*
* @param[in] addr the list head to take the element from.
* @param[in] type the type of the struct this is embedded in.
* @param[in] member the name of the dlist_t within the struct.
*/
#define dlist_entry(addr, type, member) \
((type *)((long)addr - cvi_offsetof(type, member)))
static inline void dlist_add(dlist_t *node, dlist_t *queue)
{
__dlist_add(node, queue, queue->next);
}
static inline void dlist_add_tail(dlist_t *node, dlist_t *queue)
{
__dlist_add(node, queue->prev, queue);
}
static inline void dlist_del(dlist_t *node)
{
dlist_t *prev = node->prev;
dlist_t *next = node->next;
prev->next = next;
next->prev = prev;
}
static inline void dlist_init(dlist_t *node)
{
node->next = node->prev = node;
}
static inline void INIT_CVI_DLIST_HEAD(dlist_t *list)
{
list->next = list;
list->prev = list;
}
static inline int dlist_empty(const dlist_t *head)
{
return head->next == head;
}
/*
* Initialise the list.
*
* @param[in] list the list to be inited.
*/
#define CVI_DLIST_INIT(list) {&(list), &(list)}
/*
* Get the first element from a list
*
* @param[in] ptr the list head to take the element from.
* @param[in] type the type of the struct this is embedded in.
* @param[in] member the name of the dlist_t within the struct.
*/
#define dlist_first_entry(ptr, type, member) \
dlist_entry((ptr)->next, type, member)
/*
* Iterate over a list.
*
* @param[in] pos the &struct dlist_t to use as a loop cursor.
* @param[in] head he head for your list.
*/
#define dlist_for_each(pos, head) \
for (pos = (head)->next; pos != (head); pos = pos->next)
/*
* Iterate over a list safe against removal of list entry.
*
* @param[in] pos the &struct dlist_t to use as a loop cursor.
* @param[in] n another &struct dlist_t to use as temporary storage.
* @param[in] head the head for your list.
*/
#define dlist_for_each_safe(pos, n, head) \
for (pos = (head)->next, n = pos->next; pos != (head); \
pos = n, n = pos->next)
/*
* Iterate over list of given type.
*
* @param[in] queue he head for your list.
* @param[in] node the &struct dlist_t to use as a loop cursor.
* @param[in] type the type of the struct this is embedded in.
* @param[in] member the name of the dlist_t within the struct.
*/
#define dlist_for_each_entry(queue, node, type, member) \
for (node = cvi_container_of((queue)->next, type, member); \
&node->member != (queue); \
node = cvi_container_of(node->member.next, type, member))
/*
* Iterate over list of given type safe against removal of list entry.
*
* @param[in] queue the head for your list.
* @param[in] n the type * to use as a temp.
* @param[in] node the type * to use as a loop cursor.
* @param[in] type the type of the struct this is embedded in.
* @param[in] member the name of the dlist_t within the struct.
*/
#define dlist_for_each_entry_safe(queue, n, node, type, member) \
for (node = cvi_container_of((queue)->next, type, member), \
n = (queue)->next ? (queue)->next->next : NULL; \
&node->member != (queue); \
node = cvi_container_of(n, type, member), n = n ? n->next : NULL)
/*
* Get the struct for this entry.
* @param[in] ptr the list head to take the element from.
* @param[in] type the type of the struct this is embedded in.
* @param[in] member the name of the variable within the struct.
*/
#define list_entry(ptr, type, member) \
cvi_container_of(ptr, type, member)
/*
* Iterate backwards over list of given type.
*
* @param[in] pos the type * to use as a loop cursor.
* @param[in] head he head for your list.
* @param[in] member the name of the dlist_t within the struct.
* @param[in] type the type of the struct this is embedded in.
*/
#define dlist_for_each_entry_reverse(pos, head, member, type) \
for (pos = list_entry((head)->prev, type, member); \
&pos->member != (head); \
pos = list_entry(pos->member.prev, type, member))
/*
* Get the list length.
*
* @param[in] queue the head for your list.
*/
int dlist_entry_number(dlist_t *queue);
/*
* Initialise the list.
*
* @param[in] name the list to be initialized.
*/
#define CVI_DLIST_HEAD_INIT(name) { &(name), &(name) }
/*
* Initialise the list.
*
* @param[in] name the list to be initialized.
*/
#define CVI_DLIST_HEAD(name) \
dlist_t name = CVI_DLIST_HEAD_INIT(name)
/* for single link list */
typedef struct slist_s {
struct slist_s *next;
} slist_t;
static inline void slist_add(slist_t *node, slist_t *head)
{
node->next = head->next;
head->next = node;
}
void slist_add_tail(slist_t *node, slist_t *head);
void slist_del(slist_t *node, slist_t *head);
static inline int slist_empty(const slist_t *head)
{
return !head->next;
}
static inline void slist_init(slist_t *head)
{
head->next = 0;
}
static inline slist_t *slist_remove(slist_t *l, slist_t *n)
{
/* remove slist head */
struct slist_s *node = l;
while (node->next && node->next != n)
node = node->next;
/* remove node */
if (node->next != (slist_t *)0)
node->next = node->next->next;
return l;
}
static inline slist_t *slist_first(slist_t *l)
{
return l->next;
}
static inline slist_t *slist_tail(slist_t *l)
{
while (l->next)
l = l->next;
return l;
}
static inline slist_t *slist_next(slist_t *n)
{
return n->next;
}
/*
* Iterate over list of given type.
*
* @param[in] queue he head for your list.
* @param[in] node the type * to use as a loop cursor.
* @param[in] type the type of the struct this is embedded in.
* @param[in] member the name of the slist_t within the struct.
*/
#define slist_for_each_entry(queue, node, type, member) \
for (node = (queue)->next ? cvi_container_of((queue)->next, type, member) : NULL; \
node; \
node = node->member.next ? cvi_container_of(node->member.next, type, member) : NULL)
/*
* Iterate over list of given type safe against removal of list entry.
*
* @param[in] queue the head for your list.
* @param[in] tmp the type * to use as a temp.
* @param[in] node the type * to use as a loop cursor.
* @param[in] type the type of the struct this is embedded in.
* @param[in] member the name of the slist_t within the struct.
*/
#define slist_for_each_entry_safe(queue, tmp, node, type, member) \
for (node = (queue)->next ? cvi_container_of((queue)->next, type, member) : NULL, \
tmp = (queue)->next ? (queue)->next->next : NULL; \
node; \
node = tmp ? cvi_container_of(tmp, type, member) : NULL, tmp = tmp ? tmp->next : NULL)
/*
* Initialise the list.
*
* @param[in] name the list to be initialized.
*/
#define CVI_SLIST_HEAD_INIT(name) {0}
/*
* Initialise the list.
*
* @param[in] name the list to be initialized.
*/
#define CVI_SLIST_HEAD(name) \
slist_t name = CVI_SLIST_HEAD_INIT(name)
/*
* Get the struct for this entry.
* @param[in] addr the list head to take the element from.
* @param[in] type the type of the struct this is embedded in.
* @param[in] member the name of the slist_t within the struct.
*/
#define slist_entry(addr, type, member) ( \
addr ? (type *)((long)addr - cvi_offsetof(type, member)) : (type *)addr \
)
/*
* Get the first element from a list.
*
* @param[in] ptr the list head to take the element from.
* @param[in] type the type of the struct this is embedded in.
* @param[in] member the name of the slist_t within the struct.
*/
#define slist_first_entry(ptr, type, member) \
slist_entry((ptr)->next, type, member)
/**
* slist_tail_entry - get the tail element from a slist
* @ptr: the slist head to take the element from.
* @type: the type of the struct this is embedded in.
* @member: the name of the slist_struct within the struct.
*
* Note, that slist is expected to be not empty.
*/
#define slist_tail_entry(ptr, type, member) \
slist_entry(slist_tail(ptr), type, member)
/*
* Get the list length.
*
* @param[in] queue the head for your list.
*/
int slist_entry_number(slist_t *queue);
#ifdef __cplusplus
}
#endif
#endif /* CVI_LIST_H */

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#ifndef __CVI_MAILBOX_H__
#define __CVI_MAILBOX_H__
union cpu_mailbox_info_offset{
char mbox_info;
int reserved;
};
union cpu_mailbox_int_clr_offset{
char mbox_int_clr;
int reserved;
};
union cpu_mailbox_int_mask_offset{
char mbox_int_mask;
int reserved;
};
union cpu_mailbox_int_offset{
char mbox_int;
int reserved;
};
union cpu_mailbox_int_raw_offset{
char mbox_int_raw;
int reserved;
};
union mailbox_set{
char mbox_set;
int reserved;
};
union mailbox_status{
char mbox_status;
int reserved;
};
union cpu_mailbox_status{
char mbox_status;
int reserved;
};
/* register mapping refers to mailbox user guide*/
struct cpu_mbox_int{
union cpu_mailbox_int_clr_offset cpu_mbox_int_clr;
union cpu_mailbox_int_mask_offset cpu_mbox_int_mask;
union cpu_mailbox_int_offset cpu_mbox_int_int;
union cpu_mailbox_int_raw_offset cpu_mbox_int_raw;
};
struct mailbox_set_register{
union cpu_mailbox_info_offset cpu_mbox_en[4]; //0x00, 0x04, 0x08, 0x0c
struct cpu_mbox_int cpu_mbox_set[4]; //0x10~0x1C, 0x20~0x2C, 0x30~0x3C, 0x40~0x4C
int reserved[4]; //0x50~0x5C
union mailbox_set mbox_set; //0x60
union mailbox_status mbox_status; //0x64
int reserved2[2]; //0x68~0x6C
union cpu_mailbox_status cpu_mbox_status[4]; //0x70
};
struct mailbox_done_register{
union cpu_mailbox_info_offset cpu_mbox_done_en[4];
struct cpu_mbox_int cpu_mbox_done[4];
};
#define MAILBOX_MAX_NUM 0x0008
#define MAILBOX_DONE_OFFSET 0x0002
#define MAILBOX_CONTEXT_OFFSET 0x0400
#ifdef FREERTOS_BSP
#define RECEIVE_CPU 2 // c906L
#define SEND_TO_CPU1 1 // c906B
#define SEND_TO_CPU0 0 // ca53
#else
// __linux__
#ifdef __riscv
// C906B
#define RECEIVE_CPU 1
#else
// Ca53
#define RECEIVE_CPU 0
#endif
// C906L
#define SEND_TO_CPU 2
#endif
#endif // end of__CVI_MAILBOX_H__

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_math.h
* Description:
* mathematical functions.
*/
#ifndef __CVI_MATH_H__
#define __CVI_MATH_H__
#include <cvi_type.h>
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
#define PI 3.1415926
/******************************************************************************
* ABS(x) absolute value of x
* SIGN(x) sign of x
* CMP(x,y) 0 if x==y; 1 if x>y; -1 if x<y
*****************************************************************************/
#undef ABS
#define ABS(x) ((x) >= 0 ? (x) : (-(x)))
#undef _SIGN
#define _SIGN(x) ((x) >= 0 ? 1 : -1)
#undef CMP
#define CMP(x, y) (((x) == (y)) ? 0 : (((x) > (y)) ? 1 : -1))
/******************************************************************************
* MAX2(x,y) maximum of x and y
* MIN2(x,y) minimum of x and y
* MAX3(x,y,z) maximum of x, y and z
* MIN3(x,y,z) minimun of x, y and z
* MEDIAN(x,y,z) median of x,y,z
* MEAN2(x,y) mean of x,y
*****************************************************************************/
#undef MAX2
#define MAX2(x, y) ((x) > (y) ? (x) : (y))
#undef MIN2
#define MIN2(x, y) ((x) < (y) ? (x) : (y))
#undef MAX3
#define MAX3(x, y, z) ((x) > (y) ? MAX2(x, z) : MAX2(y, z))
#undef MIN3
#define MIN3(x, y, z) ((x) < (y) ? MIN2(x, z) : MIN2(y, z))
#undef MEDIAN
#define MEDIAN(x, y, z) (((x) + (y) + (z)-MAX3(x, y, z)) - MIN3(x, y, z))
#undef MEAN2
#define MEAN2(x, y) (((x) + (y)) >> 1)
/******************************************************************************
* CLIP3(x,min,max) clip x within [min,max]
* WRAP_MAX(x,max,min) wrap to min if x equal max
* WRAP_MIN(x,min,max) wrap to max if x equal min
* VALUE_BETWEEN(x,min.max) True if x is between [min,max] inclusively.
*****************************************************************************/
#undef CLIP_MIN
#define CLIP_MIN(x, min) (((x) >= min) ? (x) : min)
#undef CLIP3
#define CLIP3(x, min, max) ((x) < (min) ? (min) : ((x) > (max) ? (max) : (x)))
#undef CLIP_MAX
#define CLIP_MAX(x, max) ((x) > (max) ? (max) : (x))
#undef WRAP_MAX
#define WRAP_MAX(x, max, min) ((x) >= (max) ? (min) : (x))
#undef WRAP_MIN
#define WRAP_MIN(x, min, max) ((x) <= (min) ? (max) : (x))
#undef VALUE_BETWEEN
#define VALUE_BETWEEN(x, min, max) (((x) >= (min)) && ((x) <= (max)))
/******************************************************************************
* a is a power of 2 value
*
* Example:
* ALIGN(48,32) = 64
* ALIGN_DOWN(48,32) = 32
*****************************************************************************/
#undef IS_ALIGNED
#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
#undef ALIGN
#define ALIGN(x, a) (((x) + ((a)-1)) & ~((a)-1))
#undef ALIGN_DOWN
#define ALIGN_DOWN(x, a) ((x) & ~((a)-1))
#undef DIV_UP
#define DIV_UP(x, a) (((x) + ((a)-1)) / a)
/******************************************************************************
* Get the span between two unsigned number, such as
* SPAN(CVI_U32, 100, 200) is 200 - 100 = 100
* SPAN(CVI_U32, 200, 100) is 0xFFFFFFFF - 200 + 100
* SPAN(CVI_U64, 200, 100) is 0xFFFFFFFFFFFFFFFF - 200 + 100
*****************************************************************************/
#undef SPAN
#define SPAN(type, begin, end) \
({ \
type b = (begin); \
type e = (end); \
(type)((b >= e) ? (b - e) : (b + ((~((type)0)) - e))); \
})
/******************************************************************************
* FRACTION32(de,nu) fraction: nu(minator) / de(nominator).
* NUMERATOR32(x) of x(x is fraction)
* DENOMINATOR32(x) Denominator of x(x is fraction)
* represent fraction in 32 bit. LSB 16 is numerator, MSB 16 is denominator
* It is integer if denominator is 0.
*****************************************************************************/
#undef FRACTION32
#define FRACTION32(de, nu) (((de) << 16) | (nu))
#undef NUMERATOR32
#define NUMERATOR32(x) ((x)&0xffff)
#undef DENOMINATOR32
#define DENOMINATOR32(x) ((x) >> 16)
/******************************************************************************
* RGB(r,g,b) assemble the r,g,b to 30bit color
* RGB_R(c) get RED from 30bit color
* RGB_G(c) get GREEN from 30bit color
* RGB_B(c) get BLUE from 30bit color
*****************************************************************************/
#undef RGB
#define RGB(r, g, b) ((((r)&0x3ff) << 20) | (((g)&0x3ff) << 10) | ((b)&0x3ff))
#undef RGB_R
#define RGB_R(c) (((c)&0x3ff00000) >> 20)
#undef RGB_G
#define RGB_G(c) (((c)&0x000ffc00) >> 10)
#undef RGB_B
#define RGB_B(c) ((c)&0x000003ff)
/******************************************************************************
* RGB(r,g,b) assemble the r,g,b to 24bit color
* RGB_R(c) get RED from 24bit color
* RGB_G(c) get GREEN from 24bit color
* RGB_B(c) get BLUE from 24bit color
*****************************************************************************/
#undef RGB_8BIT
#define RGB_8BIT(r, g, b) ((((r)&0xff) << 16) | (((g)&0xff) << 8) | ((b)&0xff))
#undef RGB_8BIT_R
#define RGB_8BIT_R(c) (((c)&0xff0000) >> 16)
#undef RGB_8BIT_G
#define RGB_8BIT_G(c) (((c)&0xff00) >> 8)
#undef RGB_8BIT_B
#define RGB_8BIT_B(c) ((c)&0xff)
/******************************************************************************
* YUV(y,u,v) assemble the y,u,v to 30bit color
* YUV_Y(c) get Y from 30bit color
* YUV_U(c) get U from 30bit color
* YUV_V(c) get V from 30bit color
*****************************************************************************/
#undef YUV
#define YUV(y, u, v) ((((y)&0x03ff) << 20) | (((u)&0x03ff) << 10) | ((v)&0x03ff))
#undef YUV_Y
#define YUV_Y(c) (((c)&0x3ff00000) >> 20)
#undef YUV_U
#define YUV_U(c) (((c)&0x000ffc00) >> 10)
#undef YUV_V
#define YUV_V(c) ((c)&0x000003ff)
/******************************************************************************
* YUV_8BIT(y,u,v) assemble the y,u,v to 24bit color
* YUV_8BIT_Y(c) get Y from 24bit color
* YUV_8BIT_U(c) get U from 24bit color
* YUV_8BIT_V(c) get V from 24bit color
*****************************************************************************/
#undef YUV_8BIT
#define YUV_8BIT(y, u, v) ((((y)&0xff) << 16) | (((u)&0xff) << 8) | ((v)&0xff))
#undef YUV_8BIT_Y
#define YUV_8BIT_Y(c) (((c)&0xff0000) >> 16)
#undef YUV_8BIT_U
#define YUV_8BIT_U(c) (((c)&0xff00) >> 8)
#undef YUV_8BIT_V
#define YUV_8BIT_V(c) ((c)&0xff)
/******************************************************************************
* Rgb2Yc(r, g, b, *y, *u, *u) convert r,g,b to y,u,v
* Rgb2Yuv(rgb) convert rgb to yuv
*****************************************************************************/
static inline CVI_VOID Rgb2Yc(CVI_U16 r, CVI_U16 g, CVI_U16 b, CVI_U16 *py, CVI_U16 *pcb, CVI_U16 *pcr)
{
/* Y */
*py = (CVI_U16)((((r * 66 + g * 129 + b * 25) >> 8) + 16) << 2);
/* Cb */
*pcb = (CVI_U16)(((((b * 112 - r * 38) - g * 74) >> 8) + 128) << 2);
/* Cr */
*pcr = (CVI_U16)(((((r * 112 - g * 94) - b * 18) >> 8) + 128) << 2);
}
static inline CVI_U32 Rgb2Yuv(CVI_U32 u32Rgb)
{
CVI_U16 y, u, v;
Rgb2Yc(RGB_R(u32Rgb), RGB_G(u32Rgb), RGB_B(u32Rgb), &y, &u, &v);
return YUV(y, u, v);
}
static inline CVI_VOID Rgb2Yc_full(CVI_U16 r, CVI_U16 g, CVI_U16 b, CVI_U16 *py, CVI_U16 *pcb, CVI_U16 *pcr)
{
CVI_U16 py_temp, pcb_temp, pcr_temp;
py_temp = (CVI_U16)(((r * 76 + g * 150 + b * 29) >> 8) * 4);
pcb_temp = (CVI_U16)(CLIP_MIN(((((b * 130 - r * 44) - g * 86) >> 8) + 128), 0) * 4);
pcr_temp = (CVI_U16)(CLIP_MIN(((((r * 130 - g * 109) - b * 21) >> 8) + 128), 0) * 4);
*py = MAX2(MIN2(py_temp, 1023), 0);
*pcb = MAX2(MIN2(pcb_temp, 1023), 0);
*pcr = MAX2(MIN2(pcr_temp, 1023), 0);
}
static inline CVI_U32 Rgb2Yuv_full(CVI_U32 u32Rgb)
{
CVI_U16 y, u, v;
Rgb2Yc_full(RGB_R(u32Rgb), RGB_G(u32Rgb), RGB_B(u32Rgb), &y, &u, &v);
return YUV(y, u, v);
}
/******************************************************************************
* Rgb2Yc_8BIT(r, g, b, *y, *u, *u) convert r,g,b to y,u,v
* Rgb2Yuv_8BIT(rgb) convert rgb to yuv
*****************************************************************************/
static inline CVI_VOID Rgb2Yc_8BIT(CVI_U8 r, CVI_U8 g, CVI_U8 b, CVI_U8 *py, CVI_U8 *pcb, CVI_U8 *pcr)
{
/* Y */
*py = (CVI_U8)(((r * 66 + g * 129 + b * 25) >> 8) + 16);
/* Cb */
*pcb = (CVI_U8)((((b * 112 - r * 38) - g * 74) >> 8) + 128);
/* Cr */
*pcr = (CVI_U8)((((r * 112 - g * 94) - b * 18) >> 8) + 128);
}
static inline CVI_U32 Rgb2Yuv_8BIT(CVI_U32 u32Rgb)
{
CVI_U8 y, u, v;
Rgb2Yc_8BIT(RGB_8BIT_R(u32Rgb), RGB_8BIT_G(u32Rgb), RGB_8BIT_B(u32Rgb), &y, &u, &v);
return YUV_8BIT(y, u, v);
}
static inline CVI_VOID Rgb2Yc_full_8BIT(CVI_U8 r, CVI_U8 g, CVI_U8 b, CVI_U8 *py, CVI_U8 *pcb, CVI_U8 *pcr)
{
CVI_S16 py_temp, pcb_temp, pcr_temp;
py_temp = (r * 76 + g * 150 + b * 29) >> 8;
pcb_temp = (((b * 130 - r * 44) - g * 86) >> 8) + 128;
pcr_temp = (((r * 130 - g * 109) - b * 21) >> 8) + 128;
*py = MAX2(MIN2(py_temp, 255), 0);
*pcb = MAX2(MIN2(pcb_temp, 255), 0);
*pcr = MAX2(MIN2(pcr_temp, 255), 0);
}
static inline CVI_U32 Rgb2Yuv_full_8BIT(CVI_U32 u32Rgb)
{
CVI_U8 y, u, v;
Rgb2Yc_full_8BIT(RGB_8BIT_R(u32Rgb), RGB_8BIT_G(u32Rgb), RGB_8BIT_B(u32Rgb), &y, &u, &v);
return YUV_8BIT(y, u, v);
}
/*******************************************************************************
* FpsControl Useing Sample:
* FPS_CTRL_S g_stFpsCtrl;
*
* Take 12 frame uniform in 25.
* InitFps(&g_stFpsCtrl, 25, 12);
*
* {
* if(FpsControl(&g_stFpsCtrl)) printf("Yes, this frmae should be token");
* }
*
******************************************************************************/
typedef struct _FPS_CTRL_S {
CVI_U32 u32Ffps; /* Full frame rate */
CVI_U32 u32Tfps; /* Target frame rate */
CVI_U32 u32FrmKey; /* update key frame */
} FPS_CTRL_S;
static inline CVI_VOID InitFps(FPS_CTRL_S *pFrmCtrl, CVI_U32 u32FullFps, CVI_U32 u32TagFps)
{
pFrmCtrl->u32Ffps = u32FullFps;
pFrmCtrl->u32Tfps = u32TagFps;
pFrmCtrl->u32FrmKey = 0;
}
static inline CVI_BOOL FpsControl(FPS_CTRL_S *pFrmCtrl)
{
CVI_BOOL bReturn = CVI_FALSE;
pFrmCtrl->u32FrmKey += pFrmCtrl->u32Tfps;
if (pFrmCtrl->u32FrmKey >= pFrmCtrl->u32Ffps) {
pFrmCtrl->u32FrmKey -= pFrmCtrl->u32Ffps;
bReturn = CVI_TRUE;
}
return bReturn;
}
static inline CVI_U32 GetLowAddr(CVI_U64 u64Phyaddr)
{
return (CVI_U32)u64Phyaddr;
}
static inline CVI_U32 GetHighAddr(CVI_U64 u64Phyaddr)
{
return (CVI_U32)(u64Phyaddr >> 32);
}
#define CVI_usleep(usec) usleep(usec)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __CVI_MATH_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_mipi.h
* Description:
* Common mipi definitions.
*/
#ifndef __CVI_MIPI_H__
#define __CVI_MIPI_H__
// #include <linux/cvi_common.h>
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
typedef unsigned int combo_dev_t;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __CVI_MIPI_H__ */

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#ifndef __CVI_SNS_CTRL_H__
#define __CVI_SNS_CTRL_H__
#include <cif_uapi.h>
#include "cvi_errno.h"
#include <cvi_type.h>
#include "cvi_debug.h"
#include "cvi_comm_3a.h"
#include "cvi_comm_isp.h"
#include "cvi_ae_comm.h"
#include "cvi_comm_vi.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
typedef struct combo_dev_attr_s SNS_COMBO_DEV_ATTR_S;
typedef struct mclk_pll_s SNS_MCLK_ATTR_S;
typedef struct _SNS_ATTR_S {
CVI_U16 u16Min;
CVI_U16 u16Max;
CVI_U16 u16Def;
CVI_U16 u16Step;
} SNS_ATTR_S;
typedef struct _SNS_ATTR_LARGE_S {
CVI_U32 u32Min;
CVI_U32 u32Max;
CVI_U32 u32Def;
CVI_U32 u32Step;
} SNS_ATTR_LARGE_S;
typedef struct _ISP_SNS_STATE_S {
CVI_BOOL bInit; /* CVI_TRUE: Sensor init */
CVI_BOOL bSyncInit; /* CVI_TRUE: Sync Reg init */
CVI_U8 u8ImgMode;
CVI_U8 u8Hdr; /* CVI_TRUE: HDR enbale */
WDR_MODE_E enWDRMode;
ISP_SNS_SYNC_INFO_S astSyncInfo[2]; /* [0]: Sensor reg info of cur-frame; [1]: Sensor reg info of pre-frame ; */
CVI_U32 au32FL[2]; /* [0]: FullLines of cur-frame; [1]: Pre FullLines of pre-frame */
CVI_U32 u32FLStd; /* FullLines std */
CVI_U32 au32WDRIntTime[4];
} ISP_SNS_STATE_S;
typedef enum _ISP_SNS_MIRRORFLIP_TYPE_E {
ISP_SNS_NORMAL = 0,
ISP_SNS_MIRROR = 1,
ISP_SNS_FLIP = 2,
ISP_SNS_MIRROR_FLIP = 3,
ISP_SNS_BUTT
} ISP_SNS_MIRRORFLIP_TYPE_E;
typedef enum _ISP_SNS_L2S_MODE_E {
SNS_L2S_MODE_AUTO = 0, /* sensor l2s distance varies by the inttime of sef. */
SNS_L2S_MODE_FIX, /* sensor l2s distance is fixed. */
} ISP_SNS_INTTIME_MODE_E;
typedef struct _MCLK_ATTR_S {
CVI_U8 u8Mclk;
CVI_BOOL bMclkEn;
} MCLK_ATTR_S;
typedef struct _RX_INIT_ATTR_S {
CVI_U32 MipiDev;
CVI_S16 as16LaneId[5];
CVI_S8 as8PNSwap[5];
MCLK_ATTR_S stMclkAttr;
} RX_INIT_ATTR_S;
typedef enum _SNS_BDG_MUX_MODE_E {
SNS_BDG_MUX_NONE = 0, /* sensor bridge mux is disabled */
SNS_BDG_MUX_2, /* sensor bridge mux 2 input */
SNS_BDG_MUX_3, /* sensor bridge mux 3 input */
SNS_BDG_MUX_4, /* sensor bridge mux 4 input */
} SNS_BDG_MUX_MODE_E;
typedef struct _ISP_INIT_ATTR_S {
CVI_U32 u32ExpTime;
CVI_U32 u32AGain;
CVI_U32 u32DGain;
CVI_U32 u32ISPDGain;
CVI_U32 u32Exposure;
CVI_U32 u32LinesPer500ms;
CVI_U32 u32PirisFNO;
CVI_U16 u16WBRgain;
CVI_U16 u16WBGgain;
CVI_U16 u16WBBgain;
CVI_U16 u16SampleRgain;
CVI_U16 u16SampleBgain;
CVI_U16 u16UseHwSync;
ISP_SNS_GAIN_MODE_E enGainMode;
ISP_SNS_INTTIME_MODE_E enL2SMode;
SNS_BDG_MUX_MODE_E enSnsBdgMuxMode;
} ISP_INIT_ATTR_S;
typedef struct _ISP_SNS_OBJ_S {
#ifdef RUN_IN_SRAM
#else
CVI_S32 (*pfnRegisterCallback)(VI_PIPE ViPipe, ALG_LIB_S *, ALG_LIB_S *);
CVI_S32 (*pfnUnRegisterCallback)(VI_PIPE ViPipe, ALG_LIB_S *, ALG_LIB_S *);
CVI_S32 (*pfnSetBusInfo)(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo);
CVI_VOID (*pfnStandby)(VI_PIPE ViPipe);
CVI_VOID (*pfnRestart)(VI_PIPE ViPipe);
CVI_VOID (*pfnMirrorFlip)(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
CVI_S32 (*pfnWriteReg)(VI_PIPE ViPipe, CVI_S32 s32Addr, CVI_S32 s32Data);
CVI_S32 (*pfnReadReg)(VI_PIPE ViPipe, CVI_S32 s32Addr);
CVI_S32 (*pfnSetInit)(VI_PIPE ViPipe, ISP_INIT_ATTR_S *);
CVI_S32 (*pfnPatchRxAttr)(RX_INIT_ATTR_S *);
CVI_VOID (*pfnPatchI2cAddr)(CVI_S32 s32I2cAddr);
CVI_S32 (*pfnGetRxAttr)(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *);
CVI_S32 (*pfnExpSensorCb)(ISP_SENSOR_EXP_FUNC_S *);
CVI_S32 (*pfnExpAeCb)(AE_SENSOR_EXP_FUNC_S *);
CVI_S32 (*pfnSnsProbe)(VI_PIPE ViPipe);
#endif
} ISP_SNS_OBJ_S;
extern ISP_SNS_OBJ_S stSnsImx327_fpga_Obj;
extern ISP_SNS_OBJ_S stSnsImx327_Obj;
extern ISP_SNS_OBJ_S stSnsOs08a20_Obj;
extern ISP_SNS_OBJ_S stSnsOs08a20_Slave_Obj;
extern ISP_SNS_OBJ_S stSnsOs04c10_Obj;
extern ISP_SNS_OBJ_S stSnsOs04c10_Slave_Obj;
extern ISP_SNS_OBJ_S stSnsF23_Obj;
extern ISP_SNS_OBJ_S stSnsF35_Obj;
extern ISP_SNS_OBJ_S stSnsF35_Slave_Obj;
extern ISP_SNS_OBJ_S stSnsH65_Obj;
extern ISP_SNS_OBJ_S stSnsImx327_2l_Obj;
extern ISP_SNS_OBJ_S stSnsImx290_2l_Obj;
extern ISP_SNS_OBJ_S stSnsImx327_Slave_Obj;
extern ISP_SNS_OBJ_S stSnsImx327_Sublvds_Obj;
extern ISP_SNS_OBJ_S stSnsImx307_Obj;
extern ISP_SNS_OBJ_S stSnsImx307_2l_Obj;
extern ISP_SNS_OBJ_S stSnsImx307_Slave_Obj;
extern ISP_SNS_OBJ_S stSnsPICO640_Obj;
extern ISP_SNS_OBJ_S stSnsPICO384_Obj;
extern ISP_SNS_OBJ_S stSnsImx307_Sublvds_Obj;
extern ISP_SNS_OBJ_S stSnsMCS369Q_Obj;
extern ISP_SNS_OBJ_S stSnsMM308M2_Obj;
extern ISP_SNS_OBJ_S stSnsN5_Obj;
extern ISP_SNS_OBJ_S stSnsSC3335_Obj;
extern ISP_SNS_OBJ_S stSnsSC3335_Slave_Obj;
extern ISP_SNS_OBJ_S stSnsImx335_Obj;
extern ISP_SNS_OBJ_S stSnsPR2020_Obj;
extern ISP_SNS_OBJ_S stSnsPR2100_Obj;
extern ISP_SNS_OBJ_S stSnsImx334_Obj;
extern ISP_SNS_OBJ_S stSnsSC8238_Obj;
extern ISP_SNS_OBJ_S stSnsMCS369_Obj;
extern ISP_SNS_OBJ_S stSnsSC4210_Obj;
extern ISP_SNS_OBJ_S stSnsSC200AI_Obj;
extern ISP_SNS_OBJ_S stSnsSC850SL_Obj;
extern ISP_SNS_OBJ_S stSnsN6_Obj;
extern ISP_SNS_OBJ_S stSnsGc2053_Obj;
extern ISP_SNS_OBJ_S stSnsGc2053_Slave_Obj;
extern ISP_SNS_OBJ_S stSnsGc2093_Obj;
extern ISP_SNS_OBJ_S stSnsGc2093_Slave_Obj;
extern ISP_SNS_OBJ_S stSnsGc4653_Obj;
extern ISP_SNS_OBJ_S stSnsGc4653_Slave_Obj;
extern ISP_SNS_OBJ_S stSnsGc1054_Obj;
extern ISP_SNS_OBJ_S stSnsImx347_Obj;
extern ISP_SNS_OBJ_S stSnsImx385_Obj;
extern ISP_SNS_OBJ_S stSnsGc2053_1l_Obj;
extern ISP_SNS_OBJ_S stSnsSC035HGS_Obj;
extern ISP_SNS_OBJ_S stSnsSC500AI_Obj;
extern ISP_SNS_OBJ_S stSnsSC501AI_2L_Obj;
extern ISP_SNS_OBJ_S stSnsSC035GS_Obj;
extern ISP_SNS_OBJ_S stSnsSC401AI_Obj;
extern ISP_SNS_OBJ_S stSnsTP2850_Obj;
#define CMOS_CHECK_POINTER(ptr)\
do {\
if (ptr == CVI_NULL) {\
syslog(LOG_ERR, "Null Pointer!\n");\
return CVI_ERR_VI_INVALID_NULL_PTR;\
} \
} while (0)
#define CMOS_CHECK_POINTER_VOID(ptr)\
do {\
if (ptr == CVI_NULL) {\
syslog(LOG_ERR, "Null Pointer!\n");\
return;\
} \
} while (0)
#define SENSOR_FREE(ptr)\
do {\
if (ptr != CVI_NULL) {\
free(ptr);\
ptr = CVI_NULL;\
} \
} while (0)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __CVI_SNS_CTRL_H__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_type.h
* Description:
*/
#ifndef __CVI_TYPE_H__
#define __CVI_TYPE_H__
// #include "linux/types.h"
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
/*----------------------------------------------
* The common data type
*----------------------------------------------
*/
typedef unsigned char CVI_UCHAR;
typedef unsigned char CVI_U8;
typedef unsigned short CVI_U16;
typedef unsigned int CVI_U32;
typedef unsigned int CVI_HANDLE;
typedef signed char CVI_S8;
typedef char CVI_CHAR;
typedef short CVI_S16;
typedef int CVI_S32;
typedef unsigned long CVI_UL;
typedef signed long CVI_SL;
typedef float CVI_FLOAT;
typedef double CVI_DOUBLE;
typedef void CVI_VOID;
typedef unsigned char CVI_BOOL;
typedef uint64_t CVI_U64;
typedef int64_t CVI_S64;
typedef size_t CVI_SIZE_T;
/*----------------------------------------------
* const defination
*----------------------------------------------
*/
#define UNUSED(x) if(x) {}
#ifndef MIN
#define MIN(x, y) ((x) < (y) ? (x) : (y))
#endif
#ifndef MAX
#define MAX(x, y) ((x) > (y) ? (x) : (y))
#endif
#ifndef CLAMP
#define CLAMP(x, low, high) (((x) > (high)) ? (high) : (((x) < (low)) ? (low) : (x)))
#endif
#ifndef EINVAL
#define EINVAL 22 /* Invalid argument */
#endif /*EINVAL*/
#define CVI_NULL 0L
#define CVI_SUCCESS 0
#define CVI_FAILURE (-1)
#define CVI_FAILURE_ILLEGAL_PARAM (-2)
#define CVI_TRUE 1
#define CVI_FALSE 0
#ifndef BIT
#define BIT(x) (1 << (x))
#endif
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __CVI_TYPE_H__ */

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#ifndef _DELAY_H
#define _DELAY_H
#include "FreeRTOS.h"
#include <sleep.h>
#ifndef udelay
#define udelay(us) usleep(us)
#endif
/* use vTaskDelay to replace usleep api
* usleep is a busy waiting api
*/
#ifndef mdelay
#define mdelay(ms) usleep(ms * 1000)
/*#define mdelay(ms) \
do { \
if (ms < (configTICK_RATE_HZ / 1000)) \
usleep(ms * 1000); \
else \
vTaskDelay(pdMS_TO_TICKS(ms)); \
} while(0)
*/
#endif
#endif // end of _DELAY_H

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#ifndef __FIFO_H__
#define __FIFO_H__
#ifdef __cplusplus
extern "C" {
#endif
#define FIFO_HEAD(name, type) \
struct name { \
struct type *fifo; \
int front, tail, capacity; \
}
#define FIFO_INIT(head, _capacity) do { \
(head)->fifo = pvPortMalloc(sizeof(*(head)->fifo) * _capacity); \
(head)->front = (head)->tail = -1; \
(head)->capacity = _capacity; \
} while (0)
#define FIFO_EMPTY(head) ((head)->front == -1)
#define FIFO_FULL(head) (((head)->front == ((head)->tail + 1)) \
|| (((head)->front == 0) && ((head)->tail == ((head)->capacity - 1))))
#define FIFO_CAPACITY(head) ((head)->capacity)
#define FIFO_SIZE(head) (FIFO_EMPTY(head) ?\
0 : ((((head)->tail + (head)->capacity - (head)->front) % (head)->capacity) + 1))
#define FIFO_PUSH(head, elm) do { \
if (FIFO_EMPTY(head)) \
(head)->front = (head)->tail = 0; \
else \
(head)->tail = ((head)->tail == (head)->capacity - 1) \
? 0 : (head)->tail + 1; \
(head)->fifo[(head)->tail] = *elm; \
} while (0)
#define FIFO_POP(head, pelm) do { \
*(pelm) = (head)->fifo[(head)->front]; \
if ((head)->front == (head)->tail) \
(head)->front = (head)->tail = -1; \
else \
(head)->front = ((head)->front == (head)->capacity - 1) \
? 0 : (head)->front + 1; \
} while (0)
#define FIFO_FOREACH(var, head, idx) \
for (idx = (head)->front, var = (head)->fifo[idx]; \
idx < (head)->front + FIFO_SIZE(head); \
idx = idx + 1, var = (head)->fifo[idx % (head)->capacity])
#define FIFO_GET_FRONT(head, pelm) (*(pelm) = (head)->fifo[(head)->front])
#define FIFO_GET_FRONT_PTR(head, pelm) ((pelm) = &(head)->fifo[(head)->front])
#define FIFO_GET_TAIL(head, pelm) (*(pelm) = (head)->fifo[(head)->tail])
#ifdef __cplusplus
}
#endif
#endif /* __FIFO_H__ */

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#ifndef __MALLOC_H___
#define __MALLOC_H__
/* here use freertos malloc & free function*/
extern void *pvPortMalloc(size_t xWantedSize);
extern void vPortFree(void *pv);
void *memset(void *dest, int value, unsigned long size);
void *memcpy(void *dest, const void *source, unsigned long size);
/*
* Replace the normal allocation functions with the versions from
* <linux/decompress/mm.h>. vfree() needs to support vfree(NULL)
*/
#undef malloc
#undef free
#undef kmalloc
#undef kfree
#undef vmalloc
#undef vfree
#define malloc(size) pvPortMalloc(size)
#define free(ptr) vPortFree(ptr)
#define kmalloc(size, flags) pvPortMalloc(size)
#define kcalloc(nelem, size, flags) calloc(nelem, size)
#define kzalloc(size, flags) calloc(1, size)
#define devm_kzalloc(nelem, size, flags) calloc(1, size)
#define kfree(ptr) vPortFree(ptr)
#define vmalloc(size) pvPortMalloc(size)
#define vfree(ptr) \
do { \
if (ptr != NULL) \
vPortFree(ptr); \
} while (0)
void *calloc(size_t nelem, size_t size);
/* align addr on a size boundary - adjust address up/down if needed */
#define _ALIGN_UP(addr, size) (((addr)+((size)-1))&(~((typeof(addr))(size)-1)))
#define _ALIGN_DOWN(addr, size) ((addr)&(~((typeof(addr))(size)-1)))
/* align addr on a size boundary - adjust address up if needed */
#define _ALIGN(addr,size) _ALIGN_UP(addr,size)
/* to align the pointer to the (next) page boundary */
#define PAGE_ALIGN(addr) _ALIGN(addr, PAGE_SIZE)
#endif // end of __MALLOC_H__

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/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __MMIO_H__
#define __MMIO_H__
#include <stdint.h>
#include "types.h"
#define __raw_readb(a) (*(volatile unsigned char *)(a))
#define __raw_readw(a) (*(volatile unsigned short *)(a))
#define __raw_readl(a) (*(volatile unsigned int *)(a))
#define __raw_readq(a) (*(volatile unsigned long long *)(a))
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
#define __raw_writeq(v,a) (*(volatile unsigned long long *)(a) = (v))
/*
* I/O memory access primitives. Reads are ordered relative to any
* following Normal memory access. Writes are ordered relative to any prior
* Normal memory access. The memory barriers here are necessary as RISC-V
* doesn't define any ordering between the memory space and the I/O space.
*/
#define __io_br() do {} while (0)
#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory")
#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory")
//#define __io_aw() mmiowb_set_pending()
#define __io_aw() do {} while (0)
#define readb(c) ({ u8 __v; __io_br(); __v = __raw_readb(c); __io_ar(__v); __v; })
#define readw(c) ({ u16 __v; __io_br(); __v = __raw_readw(c); __io_ar(__v); __v; })
#define readl(c) ({ u32 __v; __io_br(); __v = __raw_readl(c); __io_ar(__v); __v; })
#define writeb(v, c) ({ __io_bw(); __raw_writeb((v), (c)); __io_aw(); })
#define writew(v, c) ({ __io_bw(); __raw_writew((v), (c)); __io_aw(); })
#define writel(v, c) ({ __io_bw(); __raw_writel((v), (c)); __io_aw(); })
#ifdef CONFIG_64BIT
#define readq(c) ({ u64 __v; __io_br(); __v = __raw_readq(c); __io_ar(__v); __v; })
#define writeq(v, c) ({ __io_bw(); __raw_writeq((v), (c)); __io_aw(); })
#endif // CONFIG_64BIT
/*
#define __raw_readb(a) (*(volatile unsigned char *)(a))
#define __raw_readw(a) (*(volatile unsigned short *)(a))
#define __raw_readl(a) (*(volatile unsigned int *)(a))
#define __raw_readq(a) (*(volatile unsigned long long *)(a))
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
#define __raw_writeq(v,a) (*(volatile unsigned long long *)(a) = (v))
#define readb(a) __raw_readb(a)
#define readw(a) __raw_readw(a)
#define readl(a) __raw_readl(a)
#define readq(a) __raw_readq(a)
#define writeb(v, a) __raw_writeb(v,a)
#define writew(v, a) __raw_writew(v,a)
#define writel(v, a) __raw_writel(v,a)
#define writeq(v, a) __raw_writeq(v,a)
#define cpu_write8(a, v) writeb(a, v)
#define cpu_write16(a, v) writew(a, v)
#define cpu_write32(a, v) writel(a, v)
*/
#define mmio_wr32 mmio_write_32
#define mmio_rd32 mmio_read_32
static inline void mmio_write_8(uintptr_t addr, uint8_t value)
{
writeb(value, (void *) addr);
}
static inline uint8_t mmio_read_8(uintptr_t addr)
{
return readb((void *) addr);
}
static inline void mmio_write_16(uintptr_t addr, uint16_t value)
{
writew(value, (void *) addr);
}
static inline uint16_t mmio_read_16(uintptr_t addr)
{
return readw((void *) addr);
}
static inline void mmio_write_32(uintptr_t addr, uint32_t value)
{
writel(value, (void *) addr);
}
static inline uint32_t mmio_read_32(uintptr_t addr)
{
return readl((void *) addr);
}
static inline void mmio_write_64(uintptr_t addr, uint64_t value)
{
writeq(value, (void *) addr);
}
static inline uint64_t mmio_read_64(uintptr_t addr)
{
return readq((void *) addr);
}
static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear)
{
writel(readl((void *) addr) & ~clear , (void *) addr);
}
static inline void mmio_setbits_32(uintptr_t addr, uint32_t set)
{
writel(readl((void *) addr) | set , (void *) addr);
}
static inline void mmio_clrsetbits_32(uintptr_t addr, uint32_t clear,
uint32_t set)
{
writel((readl((void *) addr) & ~clear) | set , (void *) addr);
}
/* from Linux usage */
#define ioremap(a, l) (a)
#define _reg_read(addr) mmio_read_32((addr))
#define _reg_write(addr, data) mmio_write_32((addr), (data))
#define _reg_write_mask(addr, mask, data) mmio_clrsetbits_32(addr, mask, data)
#define ioread8 readb
#define ioread16 readw
#define ioread32 readl
#define ioread64 readq
#define iowrite8 writeb
#define iowrite16 writew
#define iowrite32 writel
#define iowrite64 writeq
#endif /* __MMIO_H__ */

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#ifndef _PRINTF_H
#define _PRINTF_H
#ifdef __cplusplus
extern "C" {
#endif
int printf(const char *fmt, ...);
#ifdef __cplusplus
}
#endif
#endif /* end of printf*/

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: sample_common.h
* Description:
*/
#ifndef __SAMPLE_COMM_H__
#define __SAMPLE_COMM_H__
// #include <pthread.h>
// #include "cvi_sys.h"
// #include <linux/cvi_common.h>
// #include "cvi_buffer.h"
#include "cvi_comm_sys.h"
// #include "cvi_comm_vb.h"
// #include "cvi_comm_isp.h"
// #include "cvi_comm_3a.h"
// #include "cvi_comm_sns.h"
// #include <linux/cvi_comm_vi.h>
// #include <linux/cvi_comm_vpss.h>
// #include <linux/cvi_comm_vo.h>
// #include "cvi_comm_venc.h"
// #include "cvi_comm_vdec.h"
// #include <linux/cvi_comm_region.h>
// #include "cvi_comm_adec.h"
// #include "cvi_comm_aenc.h"
// #include "cvi_comm_ao.h"
// #include "cvi_comm_aio.h"
// #include "cvi_audio.h"
// #include <linux/cvi_defines.h>
#include "cvi_mipi.h"
// #include "cvi_vb.h"
// #include "cvi_vi.h"
// #include "cvi_vpss.h"
// #include "cvi_vo.h"
#include "cvi_isp.h"
// #include "cvi_venc.h"
// #include "cvi_vdec.h"
// #include "cvi_gdc.h"
// #include "cvi_region.h"
// #include "md5sum.h"
#include "cvi_common.h"
#include "cvi_comm_video.h"
#include "stdint.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* End of #ifdef __cplusplus */
// #define FILE_NAME_LEN 128
// #define MAX_NUM_INSTANCE 4
// #define NUM_OF_USER_DATA_BUF 4
/*#define CHECK_CHN_RET(express, Chn, name) \
do { \
CVI_S32 Ret; \
Ret = express; \
if (Ret != CVI_SUCCESS) { \
printf("\033[0;31m%s chn %d failed at %s: LINE: %d with %#x!\033[0;39m\n", name, Chn, \
__func__, __LINE__, Ret); \
fflush(stdout); \
return Ret; \
} \
} while (0)
#define CHECK_RET(express, name) \
do { \
CVI_S32 Ret; \
Ret = express; \
if (Ret != CVI_SUCCESS) { \
printf("\033[0;31m%s failed at %s: LINE: %d with %#x!\033[0;39m\n", name, __func__, \
__LINE__, Ret); \
return Ret; \
} \
} while (0)
*/
// #define SAMPLE_PIXEL_FORMAT VI_PIXEL_FORMAT
// #define COLOR_RGB_RED RGB_8BIT(0xFF, 0, 0)
// #define COLOR_RGB_GREEN RGB_8BIT(0, 0xFF, 0)
// #define COLOR_RGB_BLUE RGB_8BIT(0, 0, 0xFF)
// #define COLOR_RGB_BLACK RGB_8BIT(0, 0, 0)
// #define COLOR_RGB_YELLOW RGB_8BIT(0xFF, 0xFF, 0)
// #define COLOR_RGB_CYN RGB_8BIT(0, 0xFF, 0xFF)
// #define COLOR_RGB_WHITE RGB_8BIT(0xFF, 0xFF, 0xFF)
// #define COLOR_10_RGB_RED RGB(0x3FF, 0, 0)
// #define COLOR_10_RGB_GREEN RGB(0, 0x3FF, 0)
// #define COLOR_10_RGB_BLUE RGB(0, 0, 0x3FF)
// #define COLOR_10_RGB_BLACK RGB(0, 0, 0)
// #define COLOR_10_RGB_YELLOW RGB(0x3FF, 0x3FF, 0)
// #define COLOR_10_RGB_CYN RGB(0, 0x3FF, 0x3FF)
// #define COLOR_10_RGB_WHITE RGB(0x3FF, 0x3FF, 0x3FF)
// #define SAMPLE_VO_DEV_DHD0 0 /* VO's device HD0 */
// #define SAMPLE_VO_DEV_DHD1 1 /* VO's device HD1 */
// #define SAMPLE_VO_DEV_UHD SAMPLE_VO_DEV_DHD0 /* VO's ultra HD device:HD0 */
// #define SAMPLE_VO_DEV_HD SAMPLE_VO_DEV_DHD1 /* VO's HD device:HD1 */
// #define SAMPLE_VO_LAYER_VHD0 0
// #define SAMPLE_VO_LAYER_VHD1 1
// #define SAMPLE_VO_LAYER_VHD2 2
// #define SAMPLE_VO_LAYER_PIP SAMPLE_VO_LAYER_VHD2
// #define SAMPLE_AUDIO_EXTERN_AI_DEV 0
// #define SAMPLE_AUDIO_EXTERN_AO_DEV 0
// #define SAMPLE_AUDIO_INNER_AI_DEV 0
// #define SAMPLE_AUDIO_INNER_AO_DEV 0
// #define SAMPLE_AUDIO_INNER_HDMI_AO_DEV 1
// #define SAMPLE_AUDIO_PTNUMPERFRM 480
#define WDR_MAX_PIPE_NUM 4 //need checking by jammy
#define ISP_MAX_DEV_NUM 3
// #define __FILENAM__ (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__)
// #define MAX_STRING_LEN 255
/*#define PAUSE() \
do { \
printf("---------------press Enter key to exit!---------------\n"); \
getchar(); \
} while (0)
*/
#define SAMPLE_PRT(fmt...) \
do { \
printf("[%s]-%d: ", __func__, __LINE__); \
printf(fmt); \
} while (0)
/*#define CHECK_NULL_PTR(ptr) \
do { \
if (ptr == NULL) { \
printf("func:%s,line:%d, NULL pointer\n", __func__, __LINE__); \
return CVI_FAILURE; \
} \
} while (0)
*/
// #define ALIGN_BASE(val, base) (((val) + ((base)-1)) & ~((base)-1))
// /*******************************************************
// * enum define
// *******************************************************/
typedef enum _PIC_SIZE_E {
PIC_CIF,
PIC_D1_PAL, /* 720 * 576 */
PIC_D1_NTSC, /* 720 * 480 */
PIC_720P, /* 1280 * 720 */
PIC_1080P, /* 1920 * 1080 */
PIC_1088, /* 1920 * 1088 */
PIC_1440P, /* 2560 * 1440 */
PIC_2304x1296,
PIC_2560x1600,
PIC_2592x1520,
PIC_2592x1536,
PIC_2592x1944,
PIC_2688x1520,
PIC_2716x1524,
PIC_2880x1620,
PIC_3844x1124,
PIC_3840x2160,
PIC_4096x2160,
PIC_3000x3000,
PIC_4000x3000,
PIC_3840x8640,
PIC_7688x1124,
PIC_640x480,
PIC_479P, /* 632 * 479 */
PIC_288P, /* 384 * 288 */
PIC_CUSTOMIZE,
PIC_BUTT
} PIC_SIZE_E;
typedef enum _SAMPLE_SNS_TYPE_E {
/* ------ LINEAR BEGIN ------*/
SONY_IMX290_MIPI_1M_30FPS_12BIT,
SONY_IMX290_MIPI_2M_60FPS_12BIT,
SONY_IMX327_MIPI_1M_30FPS_10BIT,
SONY_IMX327_MIPI_2M_30FPS_12BIT,
SONY_IMX307_MIPI_2M_30FPS_12BIT,
SONY_IMX327_2L_MIPI_2M_30FPS_12BIT,
SONY_IMX327_SLAVE_MIPI_2M_30FPS_12BIT,
SONY_IMX307_2L_MIPI_2M_30FPS_12BIT,
SONY_IMX307_SLAVE_MIPI_2M_30FPS_12BIT,
OV_OS08A20_MIPI_8M_30FPS_10BIT,
OV_OS08A20_MIPI_5M_30FPS_10BIT,
OV_OS08A20_MIPI_4M_30FPS_10BIT,
OV_OS08A20_SLAVE_MIPI_8M_30FPS_10BIT,
OV_OS08A20_SLAVE_MIPI_5M_30FPS_10BIT,
OV_OS08A20_SLAVE_MIPI_4M_30FPS_10BIT,
OV_OS04C10_MIPI_4M_30FPS_12BIT,
OV_OS04C10_SLAVE_MIPI_4M_30FPS_12BIT,
SOI_F23_MIPI_2M_30FPS_10BIT,
SOI_F35_MIPI_2M_30FPS_10BIT,
SOI_F35_SLAVE_MIPI_2M_30FPS_10BIT,
SOI_H65_MIPI_1M_30FPS_10BIT,
PICO640_THERMAL_479P,
PICO384_THERMAL_384X288,
SONY_IMX327_SUBLVDS_2M_30FPS_12BIT,
SONY_IMX307_SUBLVDS_2M_30FPS_12BIT,
VIVO_MCS369Q_4M_30FPS_12BIT,
VIVO_MM308M2_2M_25FPS_8BIT,
NEXTCHIP_N5_2M_25FPS_8BIT,
SMS_SC3335_MIPI_3M_30FPS_10BIT,
SMS_SC3335_SLAVE_MIPI_3M_30FPS_10BIT,
SONY_IMX335_MIPI_5M_30FPS_12BIT,
SONY_IMX335_MIPI_4M_30FPS_12BIT,
SONY_IMX335_MIPI_4M_1600P_30FPS_12BIT,
SONY_IMX335_2L_MIPI_4M_30FPS_10BIT,
PIXELPLUS_PR2020_1M_25FPS_8BIT,
SONY_IMX385_MIPI_2M_30FPS_12BIT,
PIXELPLUS_PR2020_1M_30FPS_8BIT,
PIXELPLUS_PR2020_2M_25FPS_8BIT,
PIXELPLUS_PR2020_2M_30FPS_8BIT,
PIXELPLUS_PR2100_2M_25FPS_8BIT,
PIXELPLUS_PR2100_2M_2CH_25FPS_8BIT,
PIXELPLUS_PR2100_2M_4CH_25FPS_8BIT,
SONY_IMX334_MIPI_8M_30FPS_12BIT,
SMS_SC8238_MIPI_8M_30FPS_10BIT,
VIVO_MCS369_2M_30FPS_12BIT,
SMS_SC4210_MIPI_4M_30FPS_12BIT,
SMS_SC200AI_MIPI_2M_30FPS_10BIT,
SMS_SC850SL_MIPI_8M_30FPS_12BIT,
NEXTCHIP_N6_2M_4CH_25FPS_8BIT,
NEXTCHIP_N5_1M_2CH_25FPS_8BIT,
GCORE_GC2053_MIPI_2M_30FPS_10BIT,
GCORE_GC2053_SLAVE_MIPI_2M_30FPS_10BIT,
GCORE_GC2093_MIPI_2M_30FPS_10BIT,
GCORE_GC2093_SLAVE_MIPI_2M_30FPS_10BIT,
GCORE_GC4653_MIPI_4M_30FPS_10BIT,
GCORE_GC4653_SLAVE_MIPI_4M_30FPS_10BIT,
SONY_IMX335_MIPI_5M_60FPS_10BIT,
SONY_IMX335_MIPI_4M_60FPS_10BIT,
GCORE_GC1054_MIPI_1M_30FPS_10BIT,
SONY_IMX327_MIPI_2M_60FPS_12BIT,
SONY_IMX347_MIPI_4M_60FPS_12BIT,
SONY_IMX307_SUBLVDS_2M_60FPS_12BIT,
SONY_IMX307_MIPI_2M_60FPS_12BIT,
GCORE_GC2053_1L_MIPI_2M_30FPS_10BIT,
SONY_IMX335_MIPI_2M_60FPS_10BIT,
SMS_SC035HGS_MIPI_480P_120FPS_12BIT,
SMS_SC500AI_MIPI_5M_30FPS_10BIT,
SMS_SC500AI_MIPI_4M_30FPS_10BIT,
SMS_SC501AI_2L_MIPI_5M_30FPS_10BIT,
SMS_SC401AI_MIPI_4M_30FPS_10BIT,
SMS_SC401AI_MIPI_3M_30FPS_10BIT,
SMS_SC035GS_MIPI_480P_120FPS_12BIT,
TECHPOINT_TP2850_MIPI_2M_30FPS_8BIT,
TECHPOINT_TP2850_MIPI_4M_30FPS_8BIT,
/* ------ LINEAR END ------*/
SAMPLE_SNS_TYPE_LINEAR_BUTT,
/* ------ WDR 2TO1 BEGIN ------*/
SONY_IMX327_MIPI_2M_30FPS_12BIT_WDR2TO1 = SAMPLE_SNS_TYPE_LINEAR_BUTT,
SONY_IMX327_MIPI_1M_30FPS_10BIT_WDR2TO1,
SONY_IMX307_MIPI_2M_30FPS_12BIT_WDR2TO1,
SONY_IMX327_2L_MIPI_2M_30FPS_12BIT_WDR2TO1,
SONY_IMX327_SLAVE_MIPI_2M_30FPS_12BIT_WDR2TO1,
SONY_IMX307_2L_MIPI_2M_30FPS_12BIT_WDR2TO1,
SONY_IMX307_SLAVE_MIPI_2M_30FPS_12BIT_WDR2TO1,
OV_OS08A20_MIPI_8M_30FPS_10BIT_WDR2TO1,
OV_OS08A20_MIPI_5M_30FPS_10BIT_WDR2TO1,
OV_OS08A20_MIPI_4M_30FPS_10BIT_WDR2TO1,
OV_OS08A20_SLAVE_MIPI_8M_30FPS_10BIT_WDR2TO1,
OV_OS08A20_SLAVE_MIPI_5M_30FPS_10BIT_WDR2TO1,
OV_OS08A20_SLAVE_MIPI_4M_30FPS_10BIT_WDR2TO1,
OV_OS04C10_MIPI_4M_30FPS_10BIT_WDR2TO1,
OV_OS04C10_SLAVE_MIPI_4M_30FPS_10BIT_WDR2TO1,
SOI_F35_MIPI_2M_30FPS_10BIT_WDR2TO1,
SOI_F35_SLAVE_MIPI_2M_30FPS_10BIT_WDR2TO1,
SONY_IMX327_SUBLVDS_2M_30FPS_12BIT_WDR2TO1,
SONY_IMX307_SUBLVDS_2M_30FPS_12BIT_WDR2TO1,
SONY_IMX335_MIPI_5M_30FPS_10BIT_WDR2TO1,
SONY_IMX335_MIPI_4M_30FPS_10BIT_WDR2TO1,
SONY_IMX335_MIPI_4M_1600P_30FPS_10BIT_WDR2TO1,
SONY_IMX335_MIPI_2M_30FPS_10BIT_WDR2TO1,
SONY_IMX334_MIPI_8M_30FPS_12BIT_WDR2TO1,
SONY_IMX385_MIPI_2M_30FPS_12BIT_WDR2TO1,
SMS_SC8238_MIPI_8M_15FPS_10BIT_WDR2TO1,
SMS_SC4210_MIPI_4M_30FPS_10BIT_WDR2TO1,
SMS_SC200AI_MIPI_2M_30FPS_10BIT_WDR2TO1,
SMS_SC850SL_MIPI_8M_30FPS_10BIT_WDR2TO1,
GCORE_GC2093_MIPI_2M_30FPS_10BIT_WDR2TO1,
GCORE_GC2093_SLAVE_MIPI_2M_30FPS_10BIT_WDR2TO1,
SONY_IMX347_MIPI_4M_30FPS_12BIT_WDR2TO1,
SMS_SC500AI_MIPI_5M_30FPS_10BIT_WDR2TO1,
SMS_SC500AI_MIPI_4M_30FPS_10BIT_WDR2TO1,
/* ------ WDR 2TO1 END ------*/
SAMPLE_SNS_TYPE_BUTT,
} SAMPLE_SNS_TYPE_E;
typedef struct _SAMPLE_SENSOR_MCLK_ATTR_S {
CVI_U8 u8Mclk;
CVI_BOOL bMclkEn;
} SAMPLE_SENSOR_MCLK_ATTR_S;
typedef struct _SAMPLE_SENSOR_INFO_S {
SAMPLE_SNS_TYPE_E enSnsType;
CVI_S32 s32SnsId;
CVI_S32 s32BusId;
CVI_S32 s32SnsI2cAddr;
combo_dev_t MipiDev;
CVI_S16 as16LaneId[5];
CVI_S8 as8PNSwap[5];
CVI_U8 u8HwSync;
SAMPLE_SENSOR_MCLK_ATTR_S stMclkAttr;
CVI_U8 u8Orien; // 0: normal, 1: mirror, 2: flip, 3: mirror and flip.
} SAMPLE_SENSOR_INFO_S;
// typedef enum _SAMPLE_VO_MODE_E {
// VO_MODE_1MUX,
// VO_MODE_2MUX,
// VO_MODE_4MUX,
// VO_MODE_8MUX,
// VO_MODE_9MUX,
// VO_MODE_16MUX,
// VO_MODE_25MUX,
// VO_MODE_36MUX,
// VO_MODE_49MUX,
// VO_MODE_64MUX,
// VO_MODE_2X4,
// VO_MODE_BUTT
// } SAMPLE_VO_MODE_E;
// typedef enum _SAMPLE_RC_E {
// SAMPLE_RC_CBR = 0,
// SAMPLE_RC_VBR,
// SAMPLE_RC_AVBR,
// SAMPLE_RC_QVBR,
// SAMPLE_RC_FIXQP,
// SAMPLE_RC_QPMAP,
// SAMPLE_RC_UBR,
// SAMPLE_RC_MAX
// } SAMPLE_RC_E;
// /*******************************************************
// * structure define
// *******************************************************/
// typedef struct _SAMPLE_SNAP_INFO_S {
// bool bSnap;
// bool bDoublePipe;
// VI_PIPE VideoPipe;
// VI_PIPE SnapPipe;
// VI_VPSS_MODE_E enVideoPipeMode;
// VI_VPSS_MODE_E enSnapPipeMode;
// } SAMPLE_SNAP_INFO_S;
typedef struct _SAMPLE_DEV_INFO_S {
VI_DEV ViDev;
WDR_MODE_E enWDRMode;
} SAMPLE_DEV_INFO_S;
typedef struct _SAMPLE_PIPE_INFO_S {
VI_PIPE aPipe[WDR_MAX_PIPE_NUM];
VI_VPSS_MODE_E enMastPipeMode;
CVI_BOOL bMultiPipe;
CVI_BOOL bVcNumCfged;
CVI_BOOL bIspBypass;
PIXEL_FORMAT_E enPixFmt;
CVI_U32 u32VCNum[WDR_MAX_PIPE_NUM];
} SAMPLE_PIPE_INFO_S;
// typedef struct _SAMPLE_CHN_INFO_S {
// VI_CHN ViChn;
// PIXEL_FORMAT_E enPixFormat;
// DYNAMIC_RANGE_E enDynamicRange;
// VIDEO_FORMAT_E enVideoFormat;
// COMPRESS_MODE_E enCompressMode;
// } SAMPLE_CHN_INFO_S;
typedef struct _SAMPLE_VI_INFO_S {
SAMPLE_SENSOR_INFO_S stSnsInfo;
SAMPLE_DEV_INFO_S stDevInfo;
SAMPLE_PIPE_INFO_S stPipeInfo;
// SAMPLE_CHN_INFO_S stChnInfo;
// SAMPLE_SNAP_INFO_S stSnapInfo;
} SAMPLE_VI_INFO_S;
typedef struct _SAMPLE_VI_CONFIG_S {
SAMPLE_VI_INFO_S astViInfo[VI_MAX_DEV_NUM];
CVI_S32 as32WorkingViId[VI_MAX_DEV_NUM];
CVI_S32 s32WorkingViNum;
CVI_BOOL bViRotation;
} SAMPLE_VI_CONFIG_S;
// typedef struct _SAMPLE_VI_FRAME_CONFIG_S {
// CVI_U32 u32Width;
// CVI_U32 u32Height;
// CVI_U32 u32ByteAlign;
// PIXEL_FORMAT_E enPixelFormat;
// VIDEO_FORMAT_E enVideoFormat;
// COMPRESS_MODE_E enCompressMode;
// DYNAMIC_RANGE_E enDynamicRange;
// } SAMPLE_VI_FRAME_CONFIG_S;
// typedef struct _SAMPLE_VI_FRAME_INFO_S {
// VB_BLK VbBlk;
// CVI_U32 u32Size;
// VIDEO_FRAME_INFO_S stVideoFrameInfo;
// } SAMPLE_VI_FRAME_INFO_S;
// typedef struct _SAMPLE_VI_FPN_CALIBRATE_INFO_S {
// CVI_U32 u32Threshold;
// CVI_U32 u32FrameNum;
// //ISP_FPN_TYPE_E enFpnType;
// PIXEL_FORMAT_E enPixelFormat;
// COMPRESS_MODE_E enCompressMode;
// } SAMPLE_VI_FPN_CALIBRATE_INFO_S;
// typedef struct _SAMPLE_VI_FPN_CORRECTION_INFO_S {
// ISP_OP_TYPE_E enOpType;
// //ISP_FPN_TYPE_E enFpnType;
// CVI_U32 u32Strength;
// PIXEL_FORMAT_E enPixelFormat;
// COMPRESS_MODE_E enCompressMode;
// SAMPLE_VI_FRAME_INFO_S stViFrameInfo;
// } SAMPLE_VI_FPN_CORRECTION_INFO_S;
// typedef struct _SAMPLE_COMM_VO_LAYER_CONFIG_S {
// /* for layer */
// VO_LAYER VoLayer;
// VO_INTF_SYNC_E enIntfSync;
// RECT_S stDispRect;
// SIZE_S stImageSize;
// PIXEL_FORMAT_E enPixFormat;
// CVI_U32 u32DisBufLen;
// /* for chn */
// SAMPLE_VO_MODE_E enVoMode;
// } SAMPLE_COMM_VO_LAYER_CONFIG_S;
// typedef struct _SAMPLE_VO_CONFIG_S {
// /* for device */
// VO_DEV VoDev;
// VO_PUB_ATTR_S stVoPubAttr;
// PIC_SIZE_E enPicSize;
// /* for layer */
// PIXEL_FORMAT_E enPixFormat;
// RECT_S stDispRect;
// SIZE_S stImageSize;
// CVI_U32 u32DisBufLen;
// /* for channel */
// SAMPLE_VO_MODE_E enVoMode;
// } SAMPLE_VO_CONFIG_S;
// typedef enum _THREAD_CONTRL_E {
// THREAD_CTRL_START,
// THREAD_CTRL_PAUSE,
// THREAD_CTRL_STOP,
// } THREAD_CONTRL_E;
// typedef struct _VDEC_THREAD_PARAM_S {
// CVI_S32 s32ChnId;
// PAYLOAD_TYPE_E enType;
// CVI_CHAR cFilePath[128];
// CVI_CHAR cFileName[128];
// CVI_S32 s32StreamMode;
// CVI_S32 s32MilliSec;
// CVI_S32 s32MinBufSize;
// CVI_S32 s32IntervalTime;
// THREAD_CONTRL_E eThreadCtrl;
// CVI_U64 u64PtsInit;
// CVI_U64 u64PtsIncrease;
// CVI_BOOL bCircleSend;
// CVI_BOOL bFileEnd;
// CVI_BOOL bDumpYUV;
// MD5_CTX tMD5Ctx;
// } VDEC_THREAD_PARAM_S;
// typedef struct _SAMPLE_VDEC_BUF {
// CVI_U32 u32PicBufSize;
// CVI_U32 u32TmvBufSize;
// CVI_BOOL bPicBufAlloc;
// CVI_BOOL bTmvBufAlloc;
// } SAMPLE_VDEC_BUF;
// typedef struct _SAMPLE_VDEC_VIDEO_ATTR {
// VIDEO_DEC_MODE_E enDecMode;
// CVI_U32 u32RefFrameNum;
// DATA_BITWIDTH_E enBitWidth;
// } SAMPLE_VDEC_VIDEO_ATTR;
// typedef struct _SAMPLE_VDEC_PICTURE_ATTR {
// CVI_U32 u32Alpha;
// } SAMPLE_VDEC_PICTURE_ATTR;
// typedef struct _SAMPLE_VDEC_ATTR {
// PAYLOAD_TYPE_E enType;
// PIXEL_FORMAT_E enPixelFormat;
// VIDEO_MODE_E enMode;
// CVI_U32 u32Width;
// CVI_U32 u32Height;
// CVI_U32 u32FrameBufCnt;
// CVI_U32 u32DisplayFrameNum;
// union {
// SAMPLE_VDEC_VIDEO_ATTR stSampleVdecVideo; /* structure with video ( h265/h264) */
// SAMPLE_VDEC_PICTURE_ATTR stSampleVdecPicture; /* structure with picture (jpeg/mjpeg )*/
// };
// } SAMPLE_VDEC_ATTR;
// typedef struct _vdecChnCtx_ {
// VDEC_THREAD_PARAM_S stVdecThreadParamSend;
// VDEC_THREAD_PARAM_S stVdecThreadParamGet;
// SAMPLE_VDEC_ATTR stSampleVdecAttr;
// pthread_t vdecThreadSend;
// pthread_t vdecThreadGet;
// VDEC_CHN VdecChn;
// CVI_S32 bCreateChn;
// } vdecChnCtx;
extern SAMPLE_SNS_TYPE_E g_enSnsType[VI_MAX_DEV_NUM];
// typedef struct SAMPLE_VENC_GETSTREAM_PARA_S {
// CVI_BOOL bThreadStart;
// VENC_CHN VeChn[VENC_MAX_CHN_NUM];
// CVI_S32 s32Cnt;
// } SAMPLE_VENC_GETSTREAM_PARA_S;
// typedef struct _commonInputCfg_ {
// CVI_U32 testMode;
// CVI_S32 numChn;
// CVI_S32 ifInitVb;
// CVI_U32 bindmode;
// CVI_U32 u32ViWidth; // frame width of VI input or VPSS input
// CVI_U32 u32ViHeight; // frame height of VI input or VPSS input
// CVI_U32 u32VpssWidth; // frame width of VPSS output
// CVI_U32 u32VpssHeight; // frame height of VPSS output
// CVI_CHAR yuvFolder[MAX_STRING_LEN];
// CVI_S32 vbMode;
// CVI_S32 bSingleEsBuf_jpege;
// CVI_S32 bSingleEsBuf_h264e;
// CVI_S32 bSingleEsBuf_h265e;
// CVI_S32 singleEsBufSize_jpege;
// CVI_S32 singleEsBufSize_h264e;
// CVI_S32 singleEsBufSize_h265e;
// CVI_S32 h265RefreshType;
// CVI_S32 jpegMarkerOrder;
// CVI_BOOL bThreadDisable;
// } commonInputCfg;
// typedef struct _chnInputCfg_ {
// char codec[64];
// unsigned int width;
// unsigned int height;
// char input_path[MAX_STRING_LEN];
// char vpssSrcPath[MAX_STRING_LEN];
// char output_path[MAX_STRING_LEN];
// char outputFileName[MAX_STRING_LEN];
// char roiCfgFile[MAX_STRING_LEN];
// char qpMapCfgFile[MAX_STRING_LEN];
// char user_data[NUM_OF_USER_DATA_BUF][MAX_STRING_LEN];
// CVI_S32 num_frames;
// CVI_S32 bsMode;
// CVI_U32 u32Profile;
// CVI_S32 rcMode;
// CVI_S32 iqp;
// CVI_S32 pqp;
// CVI_S32 gop;
// CVI_U32 gopMode;
// CVI_S32 bitrate;
// CVI_S32 minIprop;
// CVI_S32 maxIprop;
// CVI_U32 u32RowQpDelta;
// CVI_S32 firstFrmstartQp;
// CVI_S32 minIqp;
// CVI_S32 maxIqp;
// CVI_S32 minQp;
// CVI_S32 maxQp;
// CVI_S32 framerate;
// CVI_S32 quality;
// CVI_S32 maxbitrate;
// CVI_S32 s32ChangePos;
// CVI_S32 s32MinStillPercent;
// CVI_U32 u32MaxStillQP;
// CVI_U32 u32MotionSensitivity;
// CVI_S32 s32AvbrFrmLostOpen;
// CVI_S32 s32AvbrFrmGap;
// CVI_S32 s32AvbrPureStillThr;
// CVI_S32 statTime;
// CVI_S32 bind_mode;
// CVI_S32 pixel_format;
// CVI_S32 posX;
// CVI_S32 posY;
// CVI_S32 inWidth;
// CVI_S32 inHeight;
// CVI_S32 srcFramerate;
// CVI_U32 bitstreamBufSize;
// CVI_S32 single_LumaBuf;
// CVI_S32 single_core;
// CVI_S32 vpssGrp;
// CVI_S32 vpssChn;
// CVI_S32 forceIdr;
// CVI_S32 chgNum;
// CVI_S32 chgBitrate;
// CVI_S32 chgFramerate;
// CVI_S32 tempLayer;
// CVI_S32 testRoi;
// CVI_S32 bgInterval;
// CVI_S32 frameLost;
// CVI_U32 frameLostGap;
// CVI_U32 frameLostBspThr;
// CVI_S32 MCUPerECS;
// CVI_S32 bCreateChn;
// CVI_S32 getstream_timeout;
// CVI_S32 sendframe_timeout;
// CVI_S32 s32IPQpDelta;
// CVI_S32 s32BgQpDelta;
// CVI_S32 s32ViQpDelta;
// CVI_S32 bVariFpsEn;
// CVI_S32 initialDelay;
// CVI_U32 u32IntraCost;
// CVI_U32 u32ThrdLv;
// CVI_BOOL bBgEnhanceEn;
// CVI_S32 s32BgDeltaQp;
// CVI_U32 h264EntropyMode;
// CVI_S32 h264ChromaQpOffset;
// CVI_S32 h265CbQpOffset;
// CVI_S32 h265CrQpOffset;
// CVI_U32 enSuperFrmMode;
// CVI_U32 u32SuperIFrmBitsThr;
// CVI_U32 u32SuperPFrmBitsThr;
// CVI_S32 s32MaxReEncodeTimes;
// CVI_U8 aspectRatioInfoPresentFlag;
// CVI_U8 aspectRatioIdc;
// CVI_U8 overscanInfoPresentFlag;
// CVI_U8 overscanAppropriateFlag;
// CVI_U16 sarWidth;
// CVI_U16 sarHeight;
// CVI_U8 timingInfoPresentFlag;
// CVI_U8 fixedFrameRateFlag;
// CVI_U32 numUnitsInTick;
// CVI_U32 timeScale;
// CVI_U8 videoSignalTypePresentFlag;
// CVI_U8 videoFormat;
// CVI_U8 videoFullRangeFlag;
// CVI_U8 colourDescriptionPresentFlag;
// CVI_U8 colourPrimaries;
// CVI_U8 transferCharacteristics;
// CVI_U8 matrixCoefficients;
// CVI_U32 u32FrameQp;
// CVI_BOOL bTestUbrEn;
// CVI_BOOL bEsBufQueueEn;
// } chnInputCfg;
// typedef enum _CHN_STATE_ {
// CHN_STAT_NONE = 0,
// CHN_STAT_START,
// CHN_STAT_STOP,
// } CHN_STATE;
// typedef enum _BS_MODE_ {
// BS_MODE_QUERY_STAT = 0,
// BS_MODE_SELECT,
// } BS_MODE;
// typedef struct _SAMPLE_COMM_VENC_ROI_ATTR_ {
// VENC_ROI_ATTR_S stVencRoiAttr;
// CVI_U32 u32FrameStart;
// CVI_U32 u32FrameEnd;
// } SAMPLE_COMM_VENC_ROI;
// #define MAX_NUM_ROI 8
// typedef struct _vencChnCtx_ {
// VENC_CHN VencChn;
// PIC_SIZE_E enSize;
// SIZE_S stSize;
// VIDEO_FRAME_INFO_S *pstFrameInfo;
// VIDEO_FRAME_S *pstVFrame;
// CVI_U32 u32LumaSize;
// CVI_U32 u32ChrmSize;
// CVI_U32 u32FrameSize;
// CVI_U32 num_frames;
// CVI_S32 s32ChnNum;
// CVI_U32 s32FbCnt;
// CVI_U32 u32Profile;
// PAYLOAD_TYPE_E enPayLoad;
// VENC_GOP_MODE_E enGopMode;
// VENC_GOP_ATTR_S stGopAttr;
// SAMPLE_RC_E enRcMode;
// FILE *fpSrc;
// long file_size;
// FILE *pFile;
// chnInputCfg chnIc;
// PIXEL_FORMAT_E enPixelFormat;
// CHN_STATE chnStat;
// CHN_STATE nextChnStat;
// SAMPLE_COMM_VENC_ROI vencRoi[MAX_NUM_ROI];
// CVI_U8 *pu8QpMap;
// CVI_BOOL bQpMapValid;
// CVI_S32 s32VencFd;
// } vencChnCtx;
// typedef struct _SAMPLE_INI_CFG_S {
// VI_PIPE_FRAME_SOURCE_E enSource;
// CVI_U8 devNum;
// CVI_U8 u8UseMultiSns;
// SAMPLE_SNS_TYPE_E enSnsType[VI_MAX_DEV_NUM];
// WDR_MODE_E enWDRMode[VI_MAX_DEV_NUM];
// CVI_S32 s32BusId[VI_MAX_DEV_NUM];
// CVI_S32 s32SnsI2cAddr[VI_MAX_DEV_NUM];
// combo_dev_t MipiDev[VI_MAX_DEV_NUM];
// CVI_S16 as16LaneId[VI_MAX_DEV_NUM][5];
// CVI_S8 as8PNSwap[VI_MAX_DEV_NUM][5];
// CVI_U8 u8HwSync[VI_MAX_DEV_NUM];
// SAMPLE_SENSOR_MCLK_ATTR_S stMclkAttr[VI_MAX_DEV_NUM];
// CVI_U8 u8Orien[VI_MAX_DEV_NUM];
// } SAMPLE_INI_CFG_S;
// /********************************************************
// * function announce
// ********************************************************/
// CVI_VOID *SAMPLE_SYS_IOMmap(CVI_U64 u64PhyAddr, CVI_U32 u32Size);
// CVI_S32 SAMPLE_SYS_Munmap(CVI_VOID *pVirAddr, CVI_U32 u32Size);
// CVI_S32 SAMPLE_SYS_SetReg(CVI_U64 u64Addr, CVI_U32 u32Value);
// CVI_S32 SAMPLE_SYS_GetReg(CVI_U64 u64Addr, CVI_U32 *pu32Value);
CVI_S32 SAMPLE_COMM_SYS_GetPicSize(PIC_SIZE_E enPicSize, SIZE_S *pstSize);
// CVI_S32 SAMPLE_COMM_SYS_MemConfig(void);
// CVI_VOID SAMPLE_COMM_SYS_Exit(void);
// CVI_S32 SAMPLE_COMM_SYS_Init(VB_CONFIG_S *pstVbConfig);
// CVI_S32 SAMPLE_COMM_SYS_InitWithVbSupplement(VB_CONFIG_S *pstVbConf, CVI_U32 u32SupplementConfig);
CVI_S32 SAMPLE_COMM_VI_CreateIsp(SAMPLE_VI_CONFIG_S *pstViConfig);
CVI_S32 SAMPLE_COMM_VI_DestroyIsp(SAMPLE_VI_CONFIG_S *pstViConfig);
// CVI_S32 SAMPLE_COMM_VI_Bind_VO(VI_PIPE ViPipe, VI_CHN ViChn, VO_LAYER VoLayer, VO_CHN VoChn);
// CVI_S32 SAMPLE_COMM_VI_UnBind_VO(VI_PIPE ViPipe, VI_CHN ViChn, VO_LAYER VoLayer, VO_CHN VoChn);
// CVI_S32 SAMPLE_COMM_VI_Bind_VPSS(VI_PIPE ViPipe, VI_CHN ViChn, VPSS_GRP VpssGrp);
// CVI_S32 SAMPLE_COMM_VI_UnBind_VPSS(VI_PIPE ViPipe, VI_CHN ViChn, VPSS_GRP VpssGrp);
// CVI_S32 SAMPLE_COMM_VI_Bind_VENC(VI_PIPE ViPipe, VI_CHN ViChn, VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VI_UnBind_VENC(VI_PIPE ViPipe, VI_CHN ViChn, VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VPSS_Bind_VO(VPSS_GRP VpssGrp, VPSS_CHN VpssChn, VO_LAYER VoLayer, VO_CHN VoChn);
// CVI_S32 SAMPLE_COMM_VPSS_UnBind_VO(VPSS_GRP VpssGrp, VPSS_CHN VpssChn, VO_LAYER VoLayer, VO_CHN VoChn);
// CVI_S32 SAMPLE_COMM_VPSS_Bind_VENC(VPSS_GRP VpssGrp, VPSS_CHN VpssChn, VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VPSS_UnBind_VENC(VPSS_GRP VpssGrp, VPSS_CHN VpssChn, VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VDEC_Bind_VPSS(VDEC_CHN VdecChn, VPSS_GRP VpssGrp);
// CVI_S32 SAMPLE_COMM_VDEC_UnBind_VPSS(VDEC_CHN VdecChn, VPSS_GRP VpssGrp);
// CVI_S32 SAMPLE_COMM_VPSS_Bind_VPSS(VPSS_GRP VpssGrpSrc, VPSS_CHN VpssChnSrc, VPSS_GRP VpssGrpDst);
// CVI_S32 SAMPLE_COMM_VPSS_UnBind_VPSS(VPSS_GRP VpssGrpSrc, VPSS_CHN VpssChnSrc, VPSS_GRP VpssGrpDst);
CVI_S32 SAMPLE_COMM_ISP_Run(CVI_U8 IspDev);
CVI_VOID SAMPLE_COMM_ISP_Stop(CVI_U8 IspDev);
// CVI_VOID SAMPLE_COMM_All_ISP_Stop(void);
CVI_S32 SAMPLE_COMM_ISP_Aelib_Callback(ISP_DEV IspDev);
CVI_S32 SAMPLE_COMM_ISP_Aelib_UnCallback(ISP_DEV IspDev);
CVI_S32 SAMPLE_COMM_ISP_Awblib_Callback(ISP_DEV IspDev);
CVI_S32 SAMPLE_COMM_ISP_Sensor_Regiter_callback(ISP_DEV IspDev, CVI_U32 u32SnsId, CVI_S32 s32BusId,
CVI_S32 s32I2cAddr);
CVI_S32 SAMPLE_COMM_ISP_Awblib_UnCallback(ISP_DEV IspDev);
CVI_S32 SAMPLE_COMM_ISP_Aflib_Callback(ISP_DEV IspDev);
CVI_S32 SAMPLE_COMM_ISP_Aflib_UnCallback(ISP_DEV IspDev);
CVI_S32 SAMPLE_COMM_ISP_Sensor_UnRegiter_callback(ISP_DEV IspDev);
CVI_S32 SAMPLE_COMM_ISP_GetIspAttrBySns(SAMPLE_SNS_TYPE_E enSnsType, ISP_PUB_ATTR_S *pstPubAttr);
CVI_S32 SAMPLE_COMM_ISP_SetSensorMode(SAMPLE_VI_CONFIG_S *pstViConfig);
CVI_S32 SAMPLE_COMM_ISP_SetSnsObj(CVI_U32 u32SnsId, SAMPLE_SNS_TYPE_E enSnsType);
CVI_S32 SAMPLE_COMM_ISP_SetSnsInit(CVI_U32 u32SnsId, CVI_U8 u8HwSync);
CVI_S32 SAMPLE_COMM_ISP_PatchSnsObj(CVI_U32 u32SnsId, SAMPLE_SENSOR_INFO_S *pstSnsInfo);
CVI_VOID *SAMPLE_COMM_ISP_GetSnsObj(CVI_U32 u32SnsId);
CVI_VOID *SAMPLE_COMM_GetSnsObj(SAMPLE_SNS_TYPE_E enSnsType);
// CVI_S32 SAMPLE_AUDIO_DEBUG(void);
// CVI_S32 SAMPLE_AUDIO_DEBUG_LEVEL(ST_AudioUnitTestCfg *testCfg);
CVI_S32 SAMPLE_COMM_VI_GetDevAttrBySns(CVI_U32 u32SnsId, SAMPLE_SNS_TYPE_E enSnsType, VI_DEV_ATTR_S *pstViDevAttr);
void SAMPLE_COMM_VI_GetSensorInfo(SAMPLE_VI_CONFIG_S *pstViConfig);
CVI_S32 SAMPLE_COMM_VI_GetSizeBySensor(SAMPLE_SNS_TYPE_E enMode, PIC_SIZE_E *penSize);
// CVI_S32 SAMPLE_COMM_VI_GetChnAttrBySns(SAMPLE_SNS_TYPE_E enSnsType, VI_CHN_ATTR_S *pstChnAttr);
CVI_S32 SAMPLE_COMM_VI_StartIsp(SAMPLE_VI_INFO_S *pstViInfo);
CVI_S32 SAMPLE_COMM_VI_StopIsp(SAMPLE_VI_INFO_S *pstViInfo);
// CVI_S32 SAMPLE_COMM_VI_StartDev(SAMPLE_VI_INFO_S *pstViInfo);
// CVI_S32 SAMPLE_COMM_VI_StopDev(SAMPLE_VI_INFO_S *pstViInfo);
// CVI_S32 SAMPLE_COMM_VI_StartViChn(SAMPLE_VI_CONFIG_S *pstViConfig);
// CVI_S32 SAMPLE_COMM_VI_StopViChn(SAMPLE_VI_INFO_S *pstViInfo);
// CVI_S32 SAMPLE_COMM_VI_StopViPipe(SAMPLE_VI_INFO_S *pstViInfo);
// CVI_S32 SAMPLE_COMM_VI_DestroyVi(SAMPLE_VI_CONFIG_S *pstViConfig);
// CVI_S32 SAMPLE_COMM_VI_OPEN(void);
// CVI_S32 SAMPLE_COMM_VI_CLOSE(void);
CVI_S32 SAMPLE_COMM_VI_StartSensor(SAMPLE_VI_CONFIG_S *pstViConfig);
// CVI_S32 SAMPLE_COMM_VI_StartMIPI(SAMPLE_VI_CONFIG_S *pstViConfig);
// CVI_S32 SAMPLE_COMM_VI_SensorProbe(SAMPLE_VI_CONFIG_S *pstViConfig);
// CVI_S32 SAMPLE_COMM_VI_SetIniPath(const CVI_CHAR *iniPath);
// CVI_S32 SAMPLE_COMM_VI_ParseIni(SAMPLE_INI_CFG_S *pstIniCfg);
// CVI_S32 SAMPLE_COMM_VI_DefaultConfig(void);
// CVI_S32 SAMPLE_COMM_VI_IniToViCfg(SAMPLE_INI_CFG_S *pstIniCfg, SAMPLE_VI_CONFIG_S *pstViConfig);
// CVI_CHAR *SAMPLE_COMM_VI_GetSnsrTypeName(void);
// CVI_S32 SAMPLE_COMM_VPSS_Start(VPSS_GRP VpssGrp, CVI_BOOL *pabChnEnable, VPSS_GRP_ATTR_S *pstVpssGrpAttr,
// VPSS_CHN_ATTR_S *pastVpssChnAttr);
// CVI_S32 SAMPLE_COMM_VPSS_Init(VPSS_GRP VpssGrp, CVI_BOOL *pabChnEnable, VPSS_GRP_ATTR_S *pstVpssGrpAttr,
// VPSS_CHN_ATTR_S *pastVpssChnAttr);
// CVI_S32 SAMPLE_COMM_VPSS_Stop(VPSS_GRP VpssGrp, CVI_BOOL *pabChnEnable);
// CVI_S32 SAMPLE_COMM_VPSS_SendFrame(VPSS_GRP VpssGrp, SIZE_S *stSize, PIXEL_FORMAT_E enPixelFormat, CVI_CHAR *filename);
// CVI_VOID SAMPLE_COMM_VENC_InitCommonInputCfg(commonInputCfg *pCic);
// CVI_VOID SAMPLE_COMM_VENC_InitChnInputCfg(chnInputCfg *pIc);
// CVI_S32 SAMPLE_COMM_VENC_SaveStream(PAYLOAD_TYPE_E enType,
// FILE *pFd, VENC_STREAM_S *pstStream);
// CVI_S32 SAMPLE_COMM_VENC_SaveChannelStream(vencChnCtx *pvecc);
// CVI_S32 SAMPLE_COMM_VENC_Stop(VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VENC_GetGopAttr(VENC_GOP_MODE_E enGopMode, VENC_GOP_ATTR_S *pstGopAttr);
// CVI_S32 SAMPLE_COMM_VENC_GetFilePostfix(PAYLOAD_TYPE_E enPayload, char *szFilePostfix);
// CVI_S32 SAMPLE_COMM_VENC_InitVBPool(vencChnCtx *pvecc, VENC_CHN VencChnIdx);
// CVI_S32 SAMPLE_COMM_VENC_CloseReEncode(VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VENC_SetJpegParam(chnInputCfg *pIc, VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VENC_SetModParam(const commonInputCfg *pCic);
// CVI_S32 SAMPLE_COMM_VENC_SetRoiAttr(VENC_CHN VencChn, PAYLOAD_TYPE_E enType);
// CVI_S32 SAMPLE_COMM_VENC_SetQpMapByCfgFile(VENC_CHN VencChn,
// SAMPLE_COMM_VENC_ROI *vencRoi, CVI_U32 frame_idx,
// CVI_U8 *pu8QpMap, CVI_BOOL *pbQpMapValid,
// CVI_U32 u32Width, CVI_U32 u32Height);
// CVI_S32 SAMPLE_COMM_VENC_SetRoiAttrByCfgFile(VENC_CHN VencChn, SAMPLE_COMM_VENC_ROI *vencRoi, CVI_U32 frame_idx);
// CVI_S32 SAMPLE_COMM_VENC_LoadRoiCfgFile(SAMPLE_COMM_VENC_ROI *vencRoi, CVI_CHAR *cfgFileName);
// CVI_S32 SAMPLE_COMM_VENC_SetH264Trans(chnInputCfg *pIc, VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VENC_SetH265Trans(chnInputCfg *pIc, VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VENC_SetH264Vui(chnInputCfg *pIc, VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VENC_SetH265Vui(chnInputCfg *pIc, VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VENC_SetChnParam(chnInputCfg *pIc, VENC_CHN VencChn);
// CVI_S32 SAMPLE_COMM_VENC_Start(
// chnInputCfg * pIc,
// VENC_CHN VencChn,
// PAYLOAD_TYPE_E enType,
// PIC_SIZE_E enSize,
// SAMPLE_RC_E enRcMode,
// CVI_U32 u32Profile,
// CVI_BOOL bRcnRefShareBuf,
// VENC_GOP_ATTR_S *pstGopAttr);
// CVI_S32 SAMPLE_COMM_VDEC_InitVBPool(VDEC_CHN VdecChn, SAMPLE_VDEC_ATTR *pastSampleVdec);
// CVI_VOID SAMPLE_COMM_VDEC_StartSendStream(VDEC_THREAD_PARAM_S *pstVdecSend,
// pthread_t *pVdecThread);
// CVI_S32 SAMPLE_COMM_VDEC_SetVBPool(CVI_S32 Chn, CVI_U32 VBPoolID);
// CVI_S32 SAMPLE_COMM_VDEC_GetVBPool(CVI_S32 Chn);
// CVI_S32 SAMPLE_COMM_VDEC_SetVbMode(CVI_S32 VdecVbSrc);
// CVI_S32 SAMPLE_COMM_VDEC_GetVbMode(void);
// CVI_S32 SAMPLE_COMM_VDEC_Start(vdecChnCtx *pvdchnCtx);
// CVI_VOID SAMPLE_COMM_VDEC_CmdCtrl(VDEC_THREAD_PARAM_S *pstVdecSend, pthread_t *pVdecThread);
// CVI_VOID SAMPLE_COMM_VDEC_StopSendStream(VDEC_THREAD_PARAM_S *pstVdecSend, pthread_t *pVdecThread);
// CVI_S32 SAMPLE_COMM_VDEC_Stop(CVI_S32 s32ChnNum);
// CVI_VOID SAMPLE_COMM_VDEC_ExitVBPool(void);
// CVI_VOID SAMPLE_COMM_VDEC_StartGetPic(VDEC_THREAD_PARAM_S *pstVdecGet,
// pthread_t *pVdecThread);
// CVI_VOID SAMPLE_COMM_VDEC_StopGetPic(VDEC_THREAD_PARAM_S *pstVdecGet, pthread_t *pVdecThread);
// CVI_S32 SAMPLE_COMM_VO_GetWH(VO_INTF_SYNC_E enIntfSync, CVI_U32 *pu32W, CVI_U32 *pu32H, CVI_U32 *pu32Frm);
// CVI_S32 SAMPLE_COMM_VO_StartDev(VO_DEV VoDev, VO_PUB_ATTR_S *pstPubAttr);
// CVI_S32 SAMPLE_COMM_VO_StopDev(VO_DEV VoDev);
// CVI_S32 SAMPLE_COMM_VO_StartLayer(VO_LAYER VoLayer, const VO_VIDEO_LAYER_ATTR_S *pstLayerAttr);
// CVI_S32 SAMPLE_COMM_VO_StopLayer(VO_LAYER VoLayer);
// CVI_S32 SAMPLE_COMM_VO_StartChn(VO_LAYER VoLayer, SAMPLE_VO_MODE_E enMode);
// CVI_S32 SAMPLE_COMM_VO_StopChn(VO_LAYER VoLayer, SAMPLE_VO_MODE_E enMode);
// CVI_S32 SAMPLE_COMM_VO_BindVpss(VO_LAYER VoLayer, VO_CHN VoChn, VPSS_GRP VpssGrp, VPSS_CHN VpssChn);
// CVI_S32 SAMPLE_COMM_VO_UnBindVpss(VO_LAYER VoLayer, VO_CHN VoChn, VPSS_GRP VpssGrp, VPSS_CHN VpssChn);
// CVI_S32 SAMPLE_COMM_VO_BindVi(VO_LAYER VoLayer, VO_CHN VoChn, VI_CHN ViChn);
// CVI_S32 SAMPLE_COMM_VO_UnBindVi(VO_LAYER VoLayer, VO_CHN VoChn);
// CVI_S32 SAMPLE_COMM_VO_GetDefConfig(SAMPLE_VO_CONFIG_S *pstVoConfig);
// CVI_S32 SAMPLE_COMM_VO_StopVO(SAMPLE_VO_CONFIG_S *pstVoConfig);
// CVI_S32 SAMPLE_COMM_VO_StartVO(SAMPLE_VO_CONFIG_S *pstVoConfig);
// CVI_S32 SAMPLE_COMM_VO_StopPIP(SAMPLE_VO_CONFIG_S *pstVoConfig);
// CVI_S32 SAMPLE_COMM_VO_StartPIP(SAMPLE_VO_CONFIG_S *pstVoConfig);
// CVI_S32 SAMPLE_COMM_VO_GetDefLayerConfig(SAMPLE_COMM_VO_LAYER_CONFIG_S *pstVoLayerConfig);
// CVI_S32 SAMPLE_COMM_VO_StartLayerChn(SAMPLE_COMM_VO_LAYER_CONFIG_S *pstVoLayerConfig);
// CVI_S32 SAMPLE_COMM_VO_StopLayerChn(SAMPLE_COMM_VO_LAYER_CONFIG_S *pstVoLayerConfig);
// CVI_VOID SAMPLE_COMM_VO_Exit(void);
// CVI_S32 SAMPLE_COMM_REGION_Create(CVI_S32 HandleNum, RGN_TYPE_E enType);
// CVI_S32 SAMPLE_COMM_REGION_Destroy(CVI_S32 HandleNum, RGN_TYPE_E enType);
// CVI_S32 SAMPLE_COMM_REGION_AttachToChn(CVI_S32 HandleNum, RGN_TYPE_E enType, MMF_CHN_S *pstChn);
// CVI_S32 SAMPLE_COMM_REGION_DetachFrmChn(CVI_S32 HandleNum, RGN_TYPE_E enType, MMF_CHN_S *pstChn);
// CVI_S32 SAMPLE_COMM_REGION_SetBitMap(RGN_HANDLE Handle, const char *filename);
// CVI_S32 SAMPLE_COMM_REGION_GetUpCanvas(RGN_HANDLE Handle, const char *filename);
// CVI_S32 SAMPLE_COMM_REGION_GetMinHandle(RGN_TYPE_E enType);
// CVI_S32 SAMPLE_COMM_AUDIO_CreatTrdAiAo(AUDIO_DEV AiDev, AI_CHN AiChn, AUDIO_DEV AoDev, AO_CHN AoChn);
// CVI_S32 SAMPLE_COMM_AUDIO_CreatTrdAiAenc(AUDIO_DEV AiDev, AI_CHN AiChn, AENC_CHN AeChn);
// CVI_S32 SAMPLE_COMM_AUDIO_CreatTrdAencAdec(AENC_CHN AeChn, ADEC_CHN AdChn, FILE *pAecFd);
// CVI_S32 SAMPLE_COMM_AUDIO_GetAenc(AENC_CHN AeChn, FILE *pAencFd);
// CVI_S32 SAMPLE_COMM_AUDIO_DestoryGetAenc(AENC_CHN AeChn);
// CVI_S32 SAMPLE_COMM_AUDIO_CreatTrdFileAdec(ADEC_CHN AdChn, FILE *pAdcFd);
// CVI_S32 SAMPLE_COMM_AUDIO_CreatTrdAdecAo(ADEC_CHN AdChn, AUDIO_DEV AoDev, FILE *pFd);
// CVI_S32 SAMPLE_COMM_AUDIO_DestoryTrdAdecAo(ADEC_CHN AdChn);
// CVI_S32 SAMPLE_COMM_AUDIO_CreatTrdAoVolCtrl(AUDIO_DEV AoDev);
// CVI_S32 SAMPLE_COMM_AUDIO_DestoryTrdAi(AUDIO_DEV AiDev, AI_CHN AiChn);
// CVI_S32 SAMPLE_COMM_AUDIO_DestoryTrdAencAdec(AENC_CHN AeChn);
// CVI_S32 SAMPLE_COMM_AUDIO_DestoryTrdFileAdec(ADEC_CHN AdChn);
// CVI_S32 SAMPLE_COMM_AUDIO_DestoryTrdAoVolCtrl(AUDIO_DEV AoDev);
// CVI_S32 SAMPLE_COMM_AUDIO_DestoryAllTrd(void);
// CVI_S32 SAMPLE_COMM_AUDIO_AoBindAdec(AUDIO_DEV AoDev, AO_CHN AoChn, ADEC_CHN AdChn);
// CVI_S32 SAMPLE_COMM_AUDIO_AoUnbindAdec(AUDIO_DEV AoDev, AO_CHN AoChn, ADEC_CHN AdChn);
// CVI_S32 SAMPLE_COMM_AUDIO_AoBindAi(AUDIO_DEV AiDev, AI_CHN AiChn, AUDIO_DEV AoDev, AO_CHN AoChn);
// CVI_S32 SAMPLE_COMM_AUDIO_AoUnbindAi(AUDIO_DEV AiDev, AI_CHN AiChn, AUDIO_DEV AoDev, AO_CHN AoChn);
// CVI_S32 SAMPLE_COMM_AUDIO_AencBindAi(AUDIO_DEV AiDev, AI_CHN AiChn, AENC_CHN AeChn);
// CVI_S32 SAMPLE_COMM_AUDIO_AencUnbindAi(AUDIO_DEV AiDev, AI_CHN AiChn, AENC_CHN AeChn);
// CVI_S32 SAMPLE_COMM_AUDIO_CfgAcodec(AIO_ATTR_S *pstAioAttr);
// CVI_S32 SAMPLE_COMM_AUDIO_StartAi(AUDIO_DEV AiDevId, CVI_S32 s32AiChn, AIO_ATTR_S *pstAioAttr,
// AUDIO_SAMPLE_RATE_E enOutSampleRate, CVI_BOOL bResampleEn, CVI_VOID *pstAiVqeAttr,
// CVI_U32 u32AiVqeType);
// CVI_S32 SAMPLE_COMM_AUDIO_StopAi(AUDIO_DEV AiDevId, CVI_S32 s32AiChn, CVI_BOOL bResampleEn, CVI_BOOL bVqeEn);
// CVI_S32 SAMPLE_COMM_AUDIO_StartAo(AUDIO_DEV AoDevId, CVI_S32 s32AoChn, AIO_ATTR_S *pstAioAttr,
// AUDIO_SAMPLE_RATE_E enInSampleRate, CVI_BOOL bResampleEn);
// CVI_S32 SAMPLE_COMM_AUDIO_StopAo(AUDIO_DEV AoDevId, CVI_S32 s32AoChn, CVI_BOOL bResampleEn);
// CVI_S32 SAMPLE_COMM_AUDIO_StartAenc(CVI_S32 s32AencChn, AIO_ATTR_S *pstAioAttr, PAYLOAD_TYPE_E enType);
// CVI_S32 SAMPLE_COMM_AUDIO_StopAenc(CVI_S32 s32AencChn);
// CVI_S32 SAMPLE_COMM_AUDIO_StartAdec(ADEC_CHN AdChn, PAYLOAD_TYPE_E enType, ADEC_CHN_ATTR_S *pAdecAttr);
// CVI_S32 SAMPLE_COMM_AUDIO_StopAdec(ADEC_CHN AdChn);
// CVI_S32 SAMPLE_PLAT_SYS_INIT(SIZE_S stSize);
// CVI_S32 SAMPLE_PLAT_VI_INIT(SAMPLE_VI_CONFIG_S *pstViConfig);
// CVI_S32 SAMPLE_PLAT_VPSS_INIT(VPSS_GRP VpssGrp, SIZE_S stSizeIn, SIZE_S stSizeOut);
// CVI_S32 SAMPLE_PLAT_VO_INIT(void);
// CVI_S32 SAMPLE_PLAT_VO_INIT_BT656(void);
// CVI_S32 SAMPLE_COMM_I2C_Write(CVI_S32 file, CVI_U16 addr, CVI_U16 reg, CVI_U16 val, CVI_U16 reg_w, CVI_U16 val_w);
// CVI_S32 SAMPLE_COMM_I2C_Read(CVI_S32 file, CVI_U16 addr, CVI_U16 reg, CVI_U16 reg_w, CVI_U8 *r_val);
// CVI_S32 SAMPLE_COMM_I2C_Open(CVI_CHAR *i2c_bus);
// CVI_S32 SAMPLE_COMM_I2C_Close(CVI_S32 i2c_file);
// CVI_S32 SAMPLE_COMM_VO_Init_BT656_MS7024(char *i2c_bus_str, uint8_t slave_addr, uint8_t selection);
// CVI_S32 SAMPLE_COMM_VO_Init_MIPI_HX8394(void *pvData);
// /* SAMPLE_COMM_FRAME_SaveToFile:
// * Save videoframe to the file
// *
// * [in]filename: char string of the file to save data.
// * [IN]pstVideoFrame: the videoframe whose data will be saved to file.
// * return: CVI_SUCCESS if no problem.
// */
// CVI_S32 SAMPLE_COMM_FRAME_SaveToFile(const CVI_CHAR *filename, VIDEO_FRAME_INFO_S *pstVideoFrame);
// /* SAMPLE_COMM_PrepareFrame:
// * Prepare videoframe per size & format.
// *
// * [in]stSize: the size of videoframe
// * [in]enPixelFormat: pixel format of videoframe
// * [Out]pstVideoFrame: the videoframe generated.
// * return: CVI_SUCCESS if no problem.
// */
// CVI_S32 SAMPLE_COMM_PrepareFrame(SIZE_S stSize, PIXEL_FORMAT_E enPixelFormat, VIDEO_FRAME_INFO_S *pstVideoFrame);
// /* SAMPLE_COMM_FRAME_CompareWithFile:
// * Compare data with frame.
// *
// * [in]filename: file to read.
// * [in]pstVideoFrame: the video-frame to store data from file.
// * return: True if match; False if mismatch.
// */
// CVI_BOOL SAMPLE_COMM_FRAME_CompareWithFile(const CVI_CHAR *filename, VIDEO_FRAME_INFO_S *pstVideoFrame);
// /* SAMPLE_COMM_FRAME_LoadFromFile:
// * Load data to frame, whose data loaded from given filename.
// *
// * [in]filename: file to read.
// * [in]pstVideoFrame: the video-frame to store data from file.
// * [in]stSize: size of image.
// * [in]enPixelFormat: format of image
// * return: CVI_SUCCESS if no problem.
// */
// CVI_S32 SAMPLE_COMM_FRAME_LoadFromFile(const CVI_CHAR *filename, VIDEO_FRAME_INFO_S *pstVideoFrame,
// SIZE_S *stSize, PIXEL_FORMAT_E enPixelFormat);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif

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#ifndef _SLEEP_H
#define _SLEEP_H
void usleep(unsigned long useconds);
void nanosleep(unsigned long nseconds);
#endif // end of _SLEEP_H

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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _LINUX_TYPES_H
#define _LINUX_TYPES_H
#ifndef __ASSEMBLY__
#ifdef CONFIG_64BIT
typedef unsigned long uintptr_t;
typedef unsigned long size_t;
/* bsd */
typedef unsigned char u_char;
typedef unsigned short u_short;
typedef unsigned int u_int;
typedef unsigned long u_long;
/* sysv */
typedef unsigned char unchar;
typedef unsigned short ushort;
typedef unsigned int uint;
typedef unsigned long ulong;
typedef signed char s8;
typedef signed short s16;
typedef signed int s32;
typedef signed long s64;
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
typedef unsigned long u64;
typedef signed char __s8;
typedef signed short __s16;
typedef signed int __s32;
typedef signed long __s64;
typedef unsigned char __u8;
typedef unsigned short __u16;
typedef unsigned int __u32;
typedef unsigned long __u64;
#endif /* CONFIG_64BIT */
#endif /* __ASSEMBLY__ */
#endif /* _LINUX_TYPES_H */

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#ifndef __U_VI_ISP_H__
#define __U_VI_ISP_H__
//#include <vi_snsr.h>
#include <stdbool.h>
#include <types.h>
#include <vi_uapi.h>
#include <vi_snsr.h>
enum ISP_SCENE_INFO {
PRE_OFF_POST_OFF_SC, //183x
PRE_OFF_POST_ON_SC, //183x
FE_ON_BE_ON_POST_OFF_SC, //182x
FE_ON_BE_ON_POST_ON_SC, //182x
FE_ON_BE_OFF_POST_OFF_SC, //182x
FE_ON_BE_OFF_POST_ON_SC, //182x
FE_OFF_BE_ON_POST_OFF_SC, //182x
FE_OFF_BE_ON_POST_ON_SC, //182x
};
enum cvi_isp_source {
CVI_ISP_SOURCE_DEV = 0,
CVI_ISP_SOURCE_FE,
CVI_ISP_SOURCE_BE,
CVI_ISP_SOURCE_MAX,
};
enum IP_INFO_GRP {
IP_INFO_ID_MIN = 0,
//Pre_raw_be
IP_INFO_ID_PRE_RAW_BE = IP_INFO_ID_MIN,
IP_INFO_ID_CROP4,
IP_INFO_ID_CROP5,
IP_INFO_ID_BLC4,
IP_INFO_ID_BLC5,
IP_INFO_ID_FPN,
IP_INFO_ID_IR_PRE_PROC_LE,
IP_INFO_ID_IR_PRE_PROC_SE,
IP_INFO_ID_IR_PROC,
IP_INFO_ID_AEHIST0,
IP_INFO_ID_AEHIST1,
IP_INFO_ID_AWB0,
IP_INFO_ID_GMS,
IP_INFO_ID_AF,
IP_INFO_ID_WBG0,
IP_INFO_ID_WBG1,
IP_INFO_ID_DPC0,
IP_INFO_ID_DPC1,
IP_INFO_ID_INV_WBG0,
IP_INFO_ID_INV_WBG1,
IP_INFO_ID_LSCR4,
IP_INFO_ID_LSCR5,
//Pre_raw_0_fe
IP_INFO_ID_PRE_RAW_FE0,
IP_INFO_ID_CSIBDG0,
IP_INFO_ID_CROP0,
IP_INFO_ID_CROP1,
IP_INFO_ID_BLC0,
IP_INFO_ID_BLC1,
IP_INFO_ID_LMP0,
IP_INFO_ID_WBG11,
IP_INFO_ID_LMP1,
IP_INFO_ID_WBG12,
IP_INFO_ID_RGBMAP0,
IP_INFO_ID_WBG7,
IP_INFO_ID_RGBMAP1,
IP_INFO_ID_WBG8,
IP_INFO_ID_LSCR0,
IP_INFO_ID_LSCR1,
//Pre_raw_1_fe
IP_INFO_ID_PRE_RAW_FE1,
IP_INFO_ID_CSIBDG1_R1,
IP_INFO_ID_CROP2,
IP_INFO_ID_CROP3,
IP_INFO_ID_BLC2,
IP_INFO_ID_BLC3,
IP_INFO_ID_LMP2,
IP_INFO_ID_WBG13,
IP_INFO_ID_LMP3,
IP_INFO_ID_WBG14,
IP_INFO_ID_RGBMAP2,
IP_INFO_ID_WBG9,
IP_INFO_ID_RGBMAP3,
IP_INFO_ID_WBG10,
IP_INFO_ID_LSCR2,
IP_INFO_ID_LSCR3,
//Rawtop
IP_INFO_ID_RAWTOP,
IP_INFO_ID_CFA,
IP_INFO_ID_BNR,
IP_INFO_ID_CROP6,
IP_INFO_ID_CROP7,
//Rgbtop
IP_INFO_ID_RGBTOP,
IP_INFO_ID_LSCM0,
IP_INFO_ID_CCM0,
IP_INFO_ID_CCM1,
IP_INFO_ID_CCM2,
IP_INFO_ID_CCM3,
IP_INFO_ID_CCM4,
IP_INFO_ID_MANR,
IP_INFO_ID_GAMMA,
IP_INFO_ID_CLUT,
IP_INFO_ID_DHZ,
IP_INFO_ID_R2Y4,
IP_INFO_ID_RGBDITHER,
IP_INFO_ID_PREYEE,
IP_INFO_ID_DCI,
IP_INFO_ID_HIST_EDGE_V,
IP_INFO_ID_HDRFUSION,
IP_INFO_ID_HDRLTM,
IP_INFO_ID_AWB2,
//Yuvtop
IP_INFO_ID_YUVTOP,
IP_INFO_ID_444422,
IP_INFO_ID_FBCE,
IP_INFO_ID_FBCD,
IP_INFO_ID_YUVDITHER,
IP_INFO_ID_YNR,
IP_INFO_ID_CNR,
IP_INFO_ID_EE,
IP_INFO_ID_YCURVE,
IP_INFO_ID_CROP8,
IP_INFO_ID_CROP9,
IP_INFO_ID_ISPTOP,
IP_INFO_ID_CSIBDG_LITE,
IP_INFO_ID_MAX,
};
struct ip_info {
__u32 str_addr; //IP start address
__u32 size; //IP total registers size
};
#if 0
struct cvi_vip_isp_raw_blk {
struct cvi_vip_memblock raw_dump;
__u32 time_out;//msec
__u16 src_w;
__u16 src_h;
__u16 crop_x;
__u16 crop_y;
__u8 is_b_not_rls;
__u8 is_timeout;
__u8 is_sig_int;
};
struct cvi_isp_sts_mem {
__u8 raw_num;
struct cvi_vip_memblock af;
struct cvi_vip_memblock gms;
struct cvi_vip_memblock ae_le;
struct cvi_vip_memblock ae_se;
struct cvi_vip_memblock awb;
struct cvi_vip_memblock awb_post;
struct cvi_vip_memblock dci;
struct cvi_vip_memblock hist_edge_v;
struct cvi_vip_memblock mmap;
};
#endif
struct cvi_isp_mbus_framefmt {
__u32 width;
__u32 height;
__u32 code;
};
struct cvi_isp_rect {
__s32 left;
__s32 top;
__u32 width;
__u32 height;
};
struct cvi_isp_usr_pic_cfg {
struct cvi_isp_mbus_framefmt fmt;
struct cvi_isp_rect crop;
};
#if 0
struct cvi_isp_snr_info {
__u8 raw_num;
__u16 color_mode;
__u32 pixel_rate;
struct wdr_size_s snr_fmt;
};
struct cvi_isp_snr_update {
__u8 raw_num;
struct snsr_cfg_node_s snr_cfg_node;
};
#endif
struct cvi_vip_isp_yuv_param {
__u8 raw_num;
__u32 yuv_bypass_path;
};
struct cvi_isp_mmap_grid_size {
__u8 raw_num;
__u8 grid_size;
};
struct isp_proc_cfg {
void *buffer;
#ifdef __arm__
__u32 padding;
#endif
size_t buffer_size;
};
struct cvi_vip_isp_awb_sts {
__u8 raw_num;
__u8 is_se;
__u8 buf_idx;
};
struct cvi_vi_dma_buf_info {
__u64 paddr;
__u32 size;
};
struct cvi_isp_sc_online {
__u8 raw_num;
__u8 is_sc_online;
};
#endif // __U_VI_ISP_H__

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#ifndef __U_VI_SNSR_H__
#define __U_VI_SNSR_H__
#include <cif_uapi.h>
#define MAX_HDR_FRAME_NUM 2
#define ISP_MAX_SNS_REGS 32
/**
* struct active_size_s - linear/wdr image information
*
* @width: image total width
* @height: image total height
* @start_x: horizontal shift of the 1st pixel
* @start_y: horizontal shift of the 1st pixel
* @active_w: effective image width
* @active_h: effective image height
* @max_width: max width for buffer allocation
* @max_height: max height for buffer allocation
*/
struct active_size_s {
unsigned short width;
unsigned short height;
unsigned short start_x;
unsigned short start_y;
unsigned short active_w;
unsigned short active_h;
unsigned short max_width;
unsigned short max_height;
};
/**
* struct wdr_size_s - structure for CVI_SNSR_G_WDR_SIZE
*
* @frm_num: [output] Effective image instance. 1 for linear mode, >1 for wdr mode.
* @img_size: [output] Image information.
*/
struct wdr_size_s {
unsigned int frm_num;
struct active_size_s img_size[MAX_HDR_FRAME_NUM];
};
enum isp_sns_type_e {
ISP_SNS_I2C_TYPE = 0,
ISP_SNS_TYPE_BUTT,
};
enum sns_wdr_e {
SNS_WDR_MODE_NONE = 0,
SNS_WDR_MODE_2TO1_LINE,
SNS_WDR_MODE_BUTT
};
/**
* struct isp_i2c_data - sensor setting with i2c interface.
*
* @update: update this register or not
* @drop_frame: drop next frame or not
* @i2c_dev: i2c device number.
* @dev_addr: sensor slave address
* @dly_frm_num: this setting would be set with delay frame number
* @drop_frame_cnt: this setting would be set with drop frame
* @reg_addr: sensor register address
* @addr_bytes: sensor register address bytes number
* @data: sensor register value
* @data_bytes: sensor register value bytes number
*/
struct isp_i2c_data {
unsigned char update;
unsigned char drop_frame;
unsigned char i2c_dev;
unsigned char dev_addr;
unsigned char dly_frm_num;
unsigned short drop_frame_cnt;
unsigned short reg_addr;
unsigned short addr_bytes;
unsigned short data;
unsigned short data_bytes;
};
/**
* struct snsr_regs_s - structure of sensor update wrapper
*
* @sns_type: i2c or other interface
* @regs_num: the maximum sensor registers to be updated
* @i2c_data: sensor registers to be updated
* @use_snsr_sram: does this sensor support group update
* @need_update: global flag for sensor update. Ignore this wrapper
* when it is zero.
*/
struct snsr_regs_s {
enum isp_sns_type_e sns_type;
unsigned int magic_num;
unsigned int regs_num;
struct isp_i2c_data i2c_data[ISP_MAX_SNS_REGS];
unsigned char cfg_valid_max_dly_frm;
unsigned char use_snsr_sram;
unsigned char need_update;
};
/**
* struct snsr_isp_s - structure of isp update wrapper
*
* @wdr: the image information for isp driver.
* @need_update: global flag for isp update. Ignore this wrapper
* when it is zero.
*/
struct snsr_isp_s {
struct wdr_size_s wdr;
unsigned char dly_frm_num;
unsigned char need_update;
};
/**
* struct snsr_cif_s - structure of cif(mipi_rx) update wrapper
*
* @wdr: the image information for isp driver.
* @need_update: global flag for cif update. Ignore this wrapper
* when it is zero.
*/
struct snsr_cif_s {
struct manual_hdr_s wdr_manu;
unsigned char dly_frm_num;
unsigned char need_update;
};
/**
* struct snsr_cfg_node_s - structure of cfg node for runtime update
*
* @snsr: [output] snsr wrapper for runtime update
* @isp: [output] isp wrapper for runtime update
* @cif: [output] cif wrapper for runtime update
* @configed: [intput] after CVI_SNSR_G_CFG_NODE is called, this flag
* is set as false by sensor driver. The caller shall set it as
* true after this cfg_node is passed to isp driver.
*/
struct snsr_cfg_node_s {
struct snsr_regs_s snsr;
struct snsr_isp_s isp;
struct snsr_cif_s cif;
unsigned char configed;
};
#endif // __U_VI_SNSR_H__

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#ifndef __U_VI_UAPI_H__
#define __U_VI_UAPI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <types.h>
enum ISP_CMDQ_E {
ISP_CMDQ_RECV_EV = 0x30,
ISP_CMDQ_GET_STS_MEM,
ISP_CMDQ_GET_TUNING_NODE_MEM,
ISP_CMDQ_GET_LSC_PHY_BUF,
ISP_CMDQ_MAX,
};
enum CODEC_CMDQ_E {
CODEC_CMDQ_RECV_BUF = ISP_CMDQ_MAX,
CODEC_CMDQ_MAX,
};
enum VI_CMDQ_E {
VI_CMDQ_INFO_RECV_BUF_ACK = CODEC_CMDQ_MAX,
VI_CMDQ_INFO_MAX,
};
/*
* Events
*/
enum VI_EVENT {
VI_EVENT_BASE,
VI_EVENT_PRE0_SOF,
VI_EVENT_PRE1_SOF,
VI_EVENT_PRE0_EOF,
VI_EVENT_PRE1_EOF,
VI_EVENT_POST_EOF,
VI_EVENT_POST1_EOF,
VI_EVENT_ISP_PROC_READ,
VI_EVENT_AWB0_DONE,
VI_EVENT_AWB1_DONE,
VI_EVENT_MAX,
};
enum ISP_BLC_ID {
ISP_BLC_ID_FE0_LE = 0,
ISP_BLC_ID_FE0_SE,
ISP_BLC_ID_FE1_LE,
ISP_BLC_ID_FE1_SE,
ISP_BLC_ID_FE2_LE,
ISP_BLC_ID_BE_LE,
ISP_BLC_ID_BE_SE,
ISP_BLC_ID_MAX,
};
enum ISP_WBG_ID {
ISP_WBG_ID_FE0_RGBMAP_LE = 0,
ISP_WBG_ID_FE0_RGBMAP_SE,
ISP_WBG_ID_FE1_RGBMAP_LE,
ISP_WBG_ID_FE1_RGBMAP_SE,
ISP_WBG_ID_FE2_RGBMAP_LE,
ISP_WBG_ID_RAW_TOP_LE,
ISP_WBG_ID_RAW_TOP_SE,
ISP_WBG_ID_MAX,
};
struct vi_event {
__u32 dev_id;
__u32 type;
__u32 frame_sequence;
__u32 stt_idx;
};
/* struct cvi_vip_memblock
* @base: the address of the memory allocated.
* @size: Size in bytes of the memblock.
*/
struct cvi_vip_memblock {
__u8 raw_num;
__u64 phy_addr;
void *vir_addr;
__u32 size;
};
struct cvi_isp_sts_mem {
__u8 raw_num;
struct cvi_vip_memblock af;
struct cvi_vip_memblock gms;
struct cvi_vip_memblock ae_le;
struct cvi_vip_memblock ae_se;
struct cvi_vip_memblock awb;
struct cvi_vip_memblock awb_post;
struct cvi_vip_memblock dci;
struct cvi_vip_memblock hist_edge_v;
struct cvi_vip_memblock mmap;
};
#ifdef __cplusplus
}
#endif
#endif /* __U_VI_UAPI_H__ */

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#ifndef __VIP_SYS_H__
#define __VIP_SYS_H__
#include <stddef.h>
#include <stdint.h>
#include "mmio.h"
#include "reg_vip_sys.h"
/* VIP_SYS */
#include "mmio.h"
#define CV181X_SYS_CLOCK_BASE 0x03002000
#define REG_DIV_CLK_SRC_VIP_SYS_2 0x110
#define VIP_SYS_2_SRC_DISPPLL (2 << 8) // 1188MHz
#define VIP_SYS_2_SRC_FPLL (3 << 8) // 1500MHz
#define VIP_SYS_2_SRC_MASK (3 << 8) // [8:9]
#define SET_VIP_SYS_2_CLK_DIV(s, v) \
_reg_write(CV181X_SYS_CLOCK_BASE + REG_DIV_CLK_SRC_VIP_SYS_2, \
(s == VIP_SYS_2_SRC_DISPPLL) ? ((v << 16) | 0x209) : ((v << 16) | 0x309))
#define VIP_SYS_BASE 0x0A0C8000
#define vip_sys_reg_write_mask(addr, mask, data) \
mmio_clrsetbits_32((VIP_SYS_BASE + addr), mask, data)
#define VIP_NORM_CLK_RATIO_MASK(CLK_NAME) VIP_SYS_REG_NORM_DIV_##CLK_NAME##_MASK
#define VIP_NORM_CLK_RATIO_OFFSET(CLK_NAME) VIP_SYS_REG_NORM_DIV_##CLK_NAME##_OFFSET
#define VIP_NORM_CLK_RATIO_CONFIG(CLK_NAME, RATIO) \
vip_sys_reg_write_mask(VIP_SYS_REG_NORM_DIV_##CLK_NAME, \
VIP_NORM_CLK_RATIO_MASK(CLK_NAME), \
RATIO << VIP_NORM_CLK_RATIO_OFFSET(CLK_NAME))
#define VIP_UPDATE_CLK_RATIO_MASK(CLK_NAME) VIP_SYS_REG_UPDATE_##CLK_NAME##_MASK
#define VIP_UPDATE_CLK_RATIO_OFFSET(CLK_NAME) VIP_SYS_REG_UPDATE_##CLK_NAME##_OFFSET
#define VIP_UPDATE_CLK_RATIO(CLK_NAME) \
vip_sys_reg_write_mask(VIP_SYS_REG_UPDATE_##CLK_NAME, \
VIP_UPDATE_CLK_RATIO_MASK(CLK_NAME), \
1 << VIP_UPDATE_CLK_RATIO_OFFSET(CLK_NAME))
static void vip_toggle_reset(uint32_t mask)
{
uint32_t reset;
uint32_t reset_base = VIP_SYS_BASE + VIP_SYS_VIP_RESETS;
reset = _reg_read(reset_base);
reset |= mask;
_reg_write(reset_base, reset);
udelay(20);
reset &= ~mask;
_reg_write(reset_base, reset);
}
#endif

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/*
* Copyright CviTek Inc.
*
* Created Time: May, 2021
*/
#ifndef __CVI_CIF_H__
#define __CVI_CIF_H__
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#ifdef RUN_IN_SRAM
#include "drv/cif_drv.h"
#elif (RUN_TYPE == CVIRTOS)
#include "cif_drv.h"
#endif
#include "gpio.h"
#include "cif_uapi.h"
#include "sensor.h"
#define CIF_MAX_CSI_NUM 2
#define CIF_MAX_MAC_NUM 3
#define CSIMAC0_INTR_NUM (22)
#define CSIMAC1_INTR_NUM (23)
/* Register Base Address */
#define DPHY_TOP_BASE (0x0A0D0000)
#define DPHY_4L_BASE (0x0A0D0300)
#define DPHY_2L_BASE (0x0A0D0600)
#define SENSOR_MAC0_BASE (0x0A0C2000)
#define SENSOR_MAC1_BASE (0x0A0C4000)
#define SENSOR_MAC_VI_BASE (0x0A0C6000)
#define SENSOR_CSI0_BASE (0x0A0C2400)
#define SENSOR_CSI1_BASE (0x0A0C4400)
// CAM_PLL
#define CLK_CAM0_SRC_DIV (0x030028C0)
#define CLK_CAM1_SRC_DIV (0x030028C4)
/* Register fileds */
#define DPHY_TOP_REG_04 (DPHY_TOP_BASE + 0x04)
#define DPHY_TOP_REG_30 (DPHY_TOP_BASE + 0x30)
#define DPHY_4L_REG_04 (DPHY_4L_BASE + 0x04)
#define DPHY_4L_REG_08 (DPHY_4L_BASE + 0x08)
#define DPHY_4L_REG_0C (DPHY_4L_BASE + 0x0C)
#define DPHY_4L_REG_10 (DPHY_4L_BASE + 0x10)
#define DPHY_2L_REG_04 (DPHY_2L_BASE + 0x04)
#define DPHY_2L_REG_08 (DPHY_2L_BASE + 0x08)
#define DPHY_2L_REG_0C (DPHY_2L_BASE + 0x0C)
#define DPHY_2L_REG_10 (DPHY_2L_BASE + 0x10)
// CAM_PLL
#define REG_CAM_DIV_DIS (4)
#define REG_CAM_SRC (8)
#define REG_CAM_SRC_MASK (3 << REG_CAM_SRC)
#define REG_CAM_DIV (16)
#define REG_CAM_DIV_MASK (0x3F << REG_CAM_DIV)
/* Macro */
#define CSI_HDR_ID_VALUE (0xfff00)
#define CSI_HDR_VC_VALUE (0xdff00)
#define CSI_LINEAR_VALUE (0xcff00)
#define CIF_PHY_LANE_NUM 6
#define MAX_PAD_NUM 19
#define ENOIOCTLCMD 515 /* No ioctl command */
/* Struct */
struct cvi_csi_status {
unsigned int errcnt_ecc;
unsigned int errcnt_crc;
unsigned int errcnt_hdr;
unsigned int errcnt_wc;
unsigned int fifo_full;
};
struct cvi_lvds_status {
unsigned int fifo_full;
};
struct cvi_link {
struct cif_ctx cif_ctx;
unsigned int irq_num;
// struct reset_control *phy_reset;
// struct reset_control *phy_apb_reset;
unsigned int is_on;
struct cif_param param;
struct combo_dev_attr_s attr;
enum clk_edge_e clk_edge;
enum output_msb_e msb;
unsigned int crop_top;
unsigned int distance_fp;
int snsr_rst_pin;
enum of_gpio_flags snsr_rst_pol;
union {
struct cvi_csi_status sts_csi;
struct cvi_lvds_status sts_lvds;
};
// struct device *dev;
enum rx_mac_clk_e mac_clk;
enum ttl_bt_fmt_out bt_fmt_out;
};
struct cvi_cam_clk {
int is_on;
// struct clk *clk_o;
};
struct cvi_cif_dev {
uint32_t devno;
// struct miscdevice miscdev;
// spinlock_t lock;
// struct mutex mutex;
struct cvi_link link[MAX_LINK_NUM];
// struct cvi_cam_clk clk_cam0;
// struct cvi_cam_clk clk_cam1;
// struct cvi_cam_clk vip_sys2;
// struct cvi_cam_clk clk_div_0_src_vip_sys_2; /* mipipll */
// struct cvi_cam_clk clk_div_1_src_vip_sys_2; /* fpll */
unsigned int max_mac_clk;
void *pad_ctrl;
};
#endif //__CVI_CIF_H__

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#ifndef _LINUX_IRQRETURN_H
#define _LINUX_IRQRETURN_H
/**
* enum irqreturn
* @IRQ_NONE interrupt was not from this device or was not handled
* @IRQ_HANDLED interrupt was handled by this device
* @IRQ_WAKE_THREAD handler requests to wake the handler thread
*/
enum irqreturn {
IRQ_NONE = (0 << 0),
IRQ_HANDLED = (1 << 0),
IRQ_WAKE_THREAD = (1 << 1),
};
typedef enum irqreturn irqreturn_t;
#define IRQ_RETVAL(x) ((x) ? IRQ_HANDLED : IRQ_NONE)
#endif

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Cvitek Co., Ltd. 2019-2022. All rights reserved.
*
* File Name: fast_image.h
* Description:
*/
#ifndef __FAST_IMAGE_HEADER__
#define __FAST_IMAGE_HEADER__
#include "rtos_cmdqu.h"
#ifndef __linux__
#include "types.h"
#else
#include <linux/kernel.h>
enum FAST_IMAGE_CMD_TYPE {
FAST_SEND_STOP_REC = CMDQU_SYSTEM_LIMIT,
FAST_SEND_QUERY_ISP_PADDR,
FAST_SEND_QUERY_ISP_VADDR,
FAST_SEND_QUERY_ISP_SIZE,
FAST_SEND_QUERY_ISP_CTXT,
FAST_SEND_QUERY_IMG_PADDR,
FAST_SEND_QUERY_IMG_VADDR,
FAST_SEND_QUERY_IMG_SIZE,
FAST_SEND_QUERY_IMG_CTXT,
FAST_SEND_QUERY_ENC_PADDR,
FAST_SEND_QUERY_ENC_VADDR,
FAST_SEND_QUERY_ENC_SIZE,
FAST_SEND_QUERY_ENC_CTXT,
FAST_SEND_QUERY_FREE_ISP_ION,
FAST_SEND_QUERY_FREE_IMG_ION,
FAST_SEND_QUERY_FREE_ENC_ION,
FAST_SEND_QUERY_DUMP_MSG,
FAST_SEND_QUERY_DUMP_MSG_INFO,
FAST_SEND_QUERY_DUMP_EN,
FAST_SEND_QUERY_DUMP_DIS,
FAST_SEND_QUERY_DUMP_JPG,
FAST_SEND_QUERY_DUMP_JPG_INFO,
FAST_SEND_QUERY_TRACE_SNAPSHOT_START,
FAST_SEND_QUERY_TRACE_SNAPSHOT_STOP,
FAST_SEND_QUERY_TRACE_SNAPSHOT_DUMP,
FAST_SEND_QUERY_TRACE_STREAM_START,
FAST_SEND_QUERY_TRACE_STREAM_STOP,
FAST_SEND_QUERY_TRACE_STREAM_DUMP,
FAST_SEND_LIMIT,
};
#define FAST_IMAGE_DEV_NAME "cvi-fast-image"
#define FAST_IMAGE_SEND_STOP_REC _IOW('r', FAST_SEND_STOP_REC, unsigned long)
#define FAST_IMAGE_QUERY_ISP_PADDR _IOW('r', FAST_SEND_QUERY_ISP_PADDR, unsigned long)
#define FAST_IMAGE_QUERY_ISP_VADDR _IOW('r', FAST_SEND_QUERY_ISP_VADDR, unsigned long)
#define FAST_IMAGE_QUERY_ISP_SIZE _IOW('r', FAST_SEND_QUERY_ISP_SIZE, unsigned long)
#define FAST_IMAGE_QUERY_ISP_CTXT _IOW('r', FAST_SEND_QUERY_ISP_CTXT, unsigned long)
#define FAST_IMAGE_QUERY_IMG_PADDR _IOW('r', FAST_SEND_QUERY_IMG_PADDR, unsigned long)
#define FAST_IMAGE_QUERY_IMG_VADDR _IOW('r', FAST_SEND_QUERY_IMG_VADDR, unsigned long)
#define FAST_IMAGE_QUERY_IMG_SIZE _IOW('r', FAST_SEND_QUERY_IMG_SIZE, unsigned long)
#define FAST_IMAGE_QUERY_IMG_CTXT _IOW('r', FAST_SEND_QUERY_IMG_CTXT, unsigned long)
#define FAST_IMAGE_QUERY_ENC_PADDR _IOW('r', FAST_SEND_QUERY_ENC_PADDR, unsigned long)
#define FAST_IMAGE_QUERY_ENC_VADDR _IOW('r', FAST_SEND_QUERY_ENC_VADDR, unsigned long)
#define FAST_IMAGE_QUERY_ENC_SIZE _IOW('r', FAST_SEND_QUERY_ENC_SIZE, unsigned long)
#define FAST_IMAGE_QUERY_ENC_CTXT _IOW('r', FAST_SEND_QUERY_ENC_CTXT, unsigned long)
#define FAST_IMAGE_QUERY_FREE_ISP_ION _IOW('r', FAST_SEND_QUERY_FREE_ISP_ION, unsigned long)
#define FAST_IMAGE_QUERY_FREE_IMG_ION _IOW('r', FAST_SEND_QUERY_FREE_IMG_ION, unsigned long)
#define FAST_IMAGE_QUERY_FREE_ENC_ION _IOW('r', FAST_SEND_QUERY_FREE_ENC_ION, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_MSG _IOW('r', FAST_SEND_QUERY_DUMP_MSG, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_MSG_INFO _IOW('r', FAST_SEND_QUERY_DUMP_MSG_INFO, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_EN _IOW('r', FAST_SEND_QUERY_DUMP_EN, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_DIS _IOW('r', FAST_SEND_QUERY_DUMP_DIS, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_JPG _IOW('r', FAST_SEND_QUERY_DUMP_JPG, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_JPG_INFO _IOW('r', FAST_SEND_QUERY_DUMP_JPG_INFO, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_SNAPSHOT_START _IOW('r', FAST_SEND_QUERY_TRACE_SNAPSHOT_START, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_SNAPSHOT_STOP _IOW('r', FAST_SEND_QUERY_TRACE_SNAPSHOT_STOP, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_SNAPSHOT_DUMP _IOW('r', FAST_SEND_QUERY_TRACE_SNAPSHOT_DUMP, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_STREAM_START _IOW('r', FAST_SEND_QUERY_TRACE_STREAM_START, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_STREAM_STOP _IOW('r', FAST_SEND_QUERY_TRACE_STREAM_STOP, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_STREAM_DUMP _IOW('r', FAST_SEND_QUERY_TRACE_STREAM_DUMP, unsigned long)
#endif // end of __linux__
#define C906_MAGIC_HEADER 0xA55AC906 // master cpu is c906
#define CA53_MAGIC_HEADER 0xA55ACA53 // master cpu is ca53
#ifdef __riscv
#define RTOS_MAGIC_HEADER C906_MAGIC_HEADER
#else
#define RTOS_MAGIC_HEADER CA53_MAGIC_HEADER
#endif
enum E_IMAGE_TYPE {
E_FAST_NONE = 0,
E_FAST_JEPG = 1,
E_FAST_H264,
E_FAST_H265,
};
enum _MUC_STATUS_E {
MCU_STATUS_NONOS_INIT = 1,
MCU_STATUS_NONOS_RUNNING,
MCU_STATUS_NONOS_DONE,
MCU_STATUS_RTOS_T1_INIT, // before linux running
MCU_STATUS_RTOS_T1_RUNNING,
MCU_STATUS_RTOS_T2_INIT, // after linux running
MCU_STATUS_RTOS_T2_RUNNING,
MCU_STATUS_LINUX_INIT,
MCU_STATUS_LINUX_RUNNING,
};
enum DUMP_PRINT_SIZE_E {
DUMP_PRINT_SZ_IDX_0K = 0,
DUMP_PRINT_SZ_IDX_4K = 12, // 4096 = 1<<12
DUMP_PRINT_SZ_IDX_8K,
DUMP_PRINT_SZ_IDX_16K,
DUMP_PRINT_SZ_IDX_32K,
DUMP_PRINT_SZ_IDX_64K,
DUMP_PRINT_SZ_IDX_128K,
DUMP_PRINT_SZ_IDX_LIMIT,
};
#define ATTR __attribute__
#ifndef __packed
#define __packed ATTR((packed))
#endif
#ifndef __aligned
#define __aligned(x) ATTR((aligned(x)))
#endif
/* this structure should be modified both fsbl & MCU & osdrv side */
struct transfer_config_t {
uint32_t conf_magic;
uint32_t conf_size; //conf_size exclude mcu_status & linux_status
uint32_t isp_buffer_addr;
uint32_t isp_buffer_size;
uint32_t encode_img_addr;
uint32_t encode_img_size;
uint32_t encode_buf_addr;
uint32_t encode_buf_size;
uint8_t dump_print_enable;
uint8_t dump_print_size_idx;
uint16_t image_type;
uint16_t checksum; // checksum exclude mcu_status & linux_status
uint8_t mcu_status;
uint8_t linux_status;
} __packed __aligned(0x40);
struct trace_snapshot_t {
uint32_t ptr;
uint16_t size;
uint16_t type;
} __packed;
#endif // end of __FAST_IMAGE_HEADER__

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#ifndef __GPIO_H__
#define __GPIO_H__
#include <stddef.h>
#include <stdint.h>
#define CVI_GPIOA_BASE 0x03020000
#define CVI_GPIOB_BASE 0x03021000
#define CVI_GPIOC_BASE 0x03022000
#define CVI_GPIOD_BASE 0x03023000
enum of_gpio_flags {
OF_GPIO_ACTIVE_LOW = 0x1
};
int gpio_is_valid(int pin);
void gpio_direction_output(int pin, int val);
#endif

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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DRV_JENC_H__
#define __DRV_JENC_H__
#ifdef FREERTOS_BSP
#include "cvi_type.h"
int jpu_enc(CVI_U32 width, CVI_U32 height, CVI_U32 phySrcAddr, CVI_U32 phyDstAddr, CVI_U64 pts);
#else
#include <linux/cvi_type.h>
#endif
#define MAX_JPEG_NUM 16
typedef struct _JPEG_PIC {
CVI_U32 width;
CVI_U32 height;
CVI_U32 addr;
CVI_U32 size;
CVI_U64 pts;
} JPEG_PIC;
#endif // end of __DRV_JENC_H__

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#ifndef __PINMUX_CONFIG_H__
#define __PINMUX_CONFIG_H__
void pinmux_init(void);
#endif //end of __PINMUX_CONFIG_H__

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#ifndef __CMPR_CANVAS__
#define __CMPR_CANVAS__
#include <float.h>
#include <string.h>
#include <math.h>
#include "osd_cmpr.h"
#include "cvi_list.h"
#define BUF_GUARD_SIZE (1 << 12)
#define OSDEC_RL_BD (6)
#define OSDEC_PAL_BD (3)
#define OSDEC_MAX_RL (1 << OSDEC_RL_BD)
#define MIN_THICKNESS (1)
#define MAX_THICKNESS (32)
#define BG_COLOR_CODE (2)
#define CMPR_CANVAS_DBG (0)
typedef enum {
RECT = 0,
STROKE_RECT,
BIT_MAP,
LINE,
CMPR_BIT_MAP,
NUM_OF_DRAW_OBJ
} DRAW_OBJ_TYPE;
typedef struct {
int width;
int height;
OSD_FORMAT format;
uint32_t bg_color_code;
} Canvas_Attr;
typedef union _COLOR {
uint32_t code;
uint8_t *buf;
} COLOR;
typedef struct {
int x0; // start position
int x1; // end position
uint16_t obj_id;
} OBJ_SLICE;
typedef struct {
OBJ_SLICE slice;
int num;
dlist_t item;
} SLICE_LIST;
typedef struct {
bool is_const;
bool is_cmpr;
uint16_t width;
union {
uint32_t stride;
uint16_t *bs_len;
};
COLOR color;
uint16_t id;
} SEGMENT;
typedef struct {
SEGMENT segment;
int num;
dlist_t item;
} SEGMENT_LIST;
typedef struct {
int x;
int y;
int width;
int height;
int thickness;
} RECT_ATTR;
typedef struct {
RECT_ATTR rect;
union {
uint32_t stride;
uint32_t bs_offset;
};
} BITMAP_ATTR;
typedef struct {
float _mx; // slope of two end-point vector
float _bx[2];
float _by[2];
float _ex[2];
float _ey[2];
float ts_h; // thickness proj. on horizontal slice
} LINE_ATTR;
typedef struct {
DRAW_OBJ_TYPE type;
union {
RECT_ATTR rect;
LINE_ATTR line;
BITMAP_ATTR bitmap;
};
COLOR color;
int _max_y;
int _min_y;
} DRAW_OBJ;
typedef struct {
OSDCmpr_Ctrl osdCmpr_ctrl;
StreamBuffer bitstream;
RGBA last_color;
int rl_cnt;
MODE_TYPE md;
CODE code;
} Cmpr_Canvas_Ctrl;
uint32_t est_cmpr_canvas_size(Canvas_Attr *canvas, DRAW_OBJ *objs, uint32_t obj_num);
int draw_cmpr_canvas(Canvas_Attr *canvas, DRAW_OBJ *objs, uint32_t obj_num,
uint8_t *obuf, int buf_size, uint32_t *p_osize);
void set_rect_obj_attr(DRAW_OBJ *obj, Canvas_Attr *canvas, uint32_t color_code,
int pt_x, int pt_y, int width, int height,
bool is_filled, int thickness);
void set_bitmap_obj_attr(DRAW_OBJ *obj_attr, Canvas_Attr *canvas, uint8_t *buf,
int pt_x, int pt_y, int width, int height,
bool is_cmpr);
void set_line_obj_attr(DRAW_OBJ *obj, Canvas_Attr *canvas, uint32_t color_code,
int pt_x0, int pt_y0, int pt_x1, int pt_y1,
int thickness);
int cmpr_bitmap(Canvas_Attr *canvas, uint8_t *ibuf, uint8_t *obuf, int width,
int height, int buf_size, uint32_t *p_osize);
#if (CMPR_CANVAS_DBG)
int draw_canvas_raw_buffer(Canvas_Attr *canvas, DRAW_OBJ *obj_vec,
uint8_t *obuf);
int draw_canvas_raw_buffer2(Canvas_Attr *canvas, DRAW_OBJ *obj_vec,
uint8_t *obuf);
#endif
//==============================================================================================
//CVI interface
#ifdef __cplusplus
extern "C"
{
#endif
uint32_t CVI_OSDC_est_cmpr_canvas_size(Canvas_Attr *canvas, DRAW_OBJ *objs, uint32_t obj_num);
int CVI_OSDC_draw_cmpr_canvas(Canvas_Attr *canvas, DRAW_OBJ *objs, uint32_t obj_num,
uint8_t *obuf, uint32_t buf_size, uint32_t *p_osize);
void CVI_OSDC_set_rect_obj_attr(Canvas_Attr *canvas, DRAW_OBJ *obj, uint32_t color_code,
int pt_x, int pt_y, int width, int height, bool is_filled, int thickness);
void CVI_OSDC_set_bitmap_obj_attr(Canvas_Attr *canvas, DRAW_OBJ *obj_attr, uint8_t *buf,
int pt_x, int pt_y, int width, int height, bool is_cmpr);
void CVI_OSDC_set_line_obj_attr(Canvas_Attr *canvas, DRAW_OBJ *obj, uint32_t color_code,
int pt_x0, int pt_y0, int pt_x1, int pt_y1, int thickness);
int CVI_OSDC_cmpr_bitmap(Canvas_Attr *canvas, uint8_t *ibuf, uint8_t *obuf, int width, int height,
int buf_size, uint32_t *p_osize);
#if (CMPR_CANVAS_DBG)
int CVI_OSDC_draw_canvas_raw_buffer(Canvas_Attr *canvas, DRAW_OBJ *obj_vec, uint8_t *obuf);
int CVI_OSDC_draw_canvas_raw_buffer2(Canvas_Attr *canvas, DRAW_OBJ *obj_vec, uint8_t *obuf);
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CMPR_CANVAS__ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_comm_osdc.h
* Description:
* The common data type defination for osdc module.
*/
#ifndef __CVI_COMM_OSDC_H__
#define __CVI_COMM_OSDC_H__
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
typedef enum _OSDC_OSD_FORMAT_E {
OSD_ARGB8888 = 0,
OSD_ARGB4444 = 4,
OSD_ARGB1555 = 5,
OSD_LUT8 = 8,
OSD_LUT4 = 10,
NUM_OF_FORMAT
} OSDC_OSD_FORMAT_E;
typedef enum _OSDC_DRAW_OBJ_TYPE_E {
RECT = 0,
STROKE_RECT,
BIT_MAP,
LINE,
CMPR_BIT_MAP,
NUM_OF_DRAW_OBJ
} OSDC_DRAW_OBJ_TYPE_E;
typedef struct _OSDC_Canvas_Attr_S {
int width;
int height;
OSDC_OSD_FORMAT_E format;
uint32_t bg_color_code;
} OSDC_Canvas_Attr_S;
typedef struct _OSDC_RECT_ATTR_S {
int x;
int y;
int width;
int height;
int thickness;
} OSDC_RECT_ATTR_S;
typedef struct _OSDC_LINE_ATTR_S {
float _mx; // slope of two end-point vector
float _bx[2];
float _by[2];
float _ex[2];
float _ey[2];
float ts_h; // thickness proj. on horizontal slice
} OSDC_LINE_ATTR_S;
typedef struct _OSDC_BITMAP_ATTR_S {
OSDC_RECT_ATTR_S rect;
union {
uint32_t stride;
uint32_t bs_offset;
};
} OSDC_BITMAP_ATTR_S;
typedef union _OSDC_COLOR_S {
uint32_t code;
uint8_t *buf;
} OSDC_COLOR_S;
typedef struct _OSDC_DRAW_OBJ_S {
OSDC_DRAW_OBJ_TYPE_E type;
union {
OSDC_RECT_ATTR_S rect;
OSDC_LINE_ATTR_S line;
OSDC_BITMAP_ATTR_S bitmap;
};
OSDC_COLOR_S color;
int _max_y;
int _min_y;
} OSDC_DRAW_OBJ_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __CVI_COMM_OSDC_H__ */

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#ifndef __CVI_OSDC_H__
#define __CVI_OSDC_H__
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
#include <cvi_comm_osdc.h>
uint32_t CVI_OSDC_EstCmprCanvasSize(OSDC_Canvas_Attr_S * canvas, OSDC_DRAW_OBJ_S * objs, uint32_t obj_num);
int CVI_OSDC_DrawCmprCanvas(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *objs, uint32_t obj_num,
uint8_t *obuf, uint32_t buf_size, uint32_t *p_osize);
void CVI_OSDC_SetRectObjAttr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj, uint32_t color_code,
int pt_x, int pt_y, int width, int height, bool is_filled, int thickness);
void CVI_OSDC_SetBitmapObjAttr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj_attr, uint8_t *buf,
int pt_x, int pt_y, int width, int height, bool is_cmpr);
void CVI_OSDC_SetLineObjAttr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj, uint32_t color_code,
int pt_x0, int pt_y0, int pt_x1, int pt_y1, int thickness);
int CVI_OSDC_CmprBitmap(OSDC_Canvas_Attr_S *canvas, uint8_t *ibuf, uint8_t *obuf, int width, int height,
int buf_size, uint32_t *p_osize);
extern uint32_t CVI_OSDC_est_cmpr_canvas_size(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *objs, uint32_t obj_num);
extern int CVI_OSDC_draw_cmpr_canvas(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *objs, uint32_t obj_num,
uint8_t *obuf, uint32_t buf_size, uint32_t *p_osize);
extern void CVI_OSDC_set_rect_obj_attr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj, uint32_t color_code,
int pt_x, int pt_y, int width, int height, bool is_filled, int thickness);
extern void CVI_OSDC_set_bitmap_obj_attr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj_attr, uint8_t *buf,
int pt_x, int pt_y, int width, int height, bool is_cmpr);
extern void CVI_OSDC_set_line_obj_attr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj, uint32_t color_code,
int pt_x0, int pt_y0, int pt_x1, int pt_y1, int thickness);
extern int CVI_OSDC_cmpr_bitmap(OSDC_Canvas_Attr_S *canvas, uint8_t *ibuf, uint8_t *obuf, int width, int height,
int buf_size, uint32_t *p_osize);
#if (CMPR_CANVAS_DBG)
int CVI_OSDC_draw_canvas_raw_buffer(OSDC_Canvas_Attr_S *canvas, DRAW_OBJ *obj_vec, uint8_t *obuf);
int CVI_OSDC_draw_canvas_raw_buffer2(OSDC_Canvas_Attr_S *canvas, DRAW_OBJ *obj_vec, uint8_t *obuf);
#endif
#ifdef __cplusplus
}
#endif
#endif /*__CVI_OSDC_H__ */

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#ifndef __OSD_CMPR_H__
#define __OSD_CMPR_H__
#include <stdbool.h>
#include <stdint.h>
#include <sys/param.h>
// DataType-free color field copy
#define CPY_C(in, out) \
{ \
out.r = in.r; \
out.g = in.g; \
out.b = in.b; \
out.a = in.a; \
}
#define HDR_SZ (8)
typedef enum {
OSD_ARGB8888 = 0,
OSD_ARGB4444 = 4,
OSD_ARGB1555 = 5,
OSD_LUT8 = 8,
OSD_LUT4 = 10,
NUM_OF_FORMAT
} OSD_FORMAT;
typedef struct {
int img_width;
int img_height;
bool palette_mode_en;
bool zeroize_by_alpha;
int rgb_trunc_bit;
int alpha_trunc_bit;
int run_len_bd;
int palette_idx_bd;
OSD_FORMAT osd_format;
bool hdr_en;
} OSDCmpr_Cfg;
typedef struct {
uint8_t *stream; // stream buffer pointer
int bit_pos; // current pointer (in bit)
int buf_size; // in byte
int status;
} StreamBuffer;
int clip(int data, int min, int max);
void init_stream(StreamBuffer *bs, const uint8_t *buf, int buf_size,
bool read_only);
void write_stream(StreamBuffer *bs, uint8_t *src, int bit_len);
void parse_stream(StreamBuffer *bs, uint8_t *dest, int bit_len, bool read_only);
void move_stream_ptr(StreamBuffer *bs, int bit_len);
uint8_t get_bit_val(uint8_t *buf, int byte_idx, int bit_idx);
typedef union {
struct {
uint8_t g;
uint8_t b;
uint8_t r;
uint8_t a;
};
uint32_t code;
} RGBA;
typedef union {
struct {
uint16_t g : 4;
uint16_t b : 4;
uint16_t r : 4;
uint16_t a : 4;
};
uint16_t code;
} ARGB4444;
typedef union {
struct {
uint16_t g : 5;
uint16_t b : 5;
uint16_t r : 5;
uint16_t a : 1;
};
uint16_t code;
} ARGB1555;
typedef union {
RGBA color;
int palette_idx;
} CODE;
typedef enum {
Literal = 0,
Palette,
Literal_RL,
Palette_RL,
NUM_OF_MODE
} MODE_TYPE;
typedef struct {
RGBA *color;
int num;
} PaletteRGBA;
typedef struct {
int reg_image_width;
int reg_image_height;
bool reg_zeroize_by_alpha;
int reg_rgb_trunc_bit;
int reg_alpha_trunc_bit;
bool reg_palette_mode_en;
int reg_run_len_bd;
int reg_palette_idx_bd;
OSD_FORMAT reg_osd_format;
int pel_sz;
PaletteRGBA palette_cache;
int bs_buf_size;
uint8_t *bsbuf; // intermediate bitstream buffer
} OSDCmpr_Ctrl;
// RGBA get_color(uint8_t *ptr, OSD_FORMAT format = OSD_ARGB8888);
// void set_color(uint8_t *ptr, RGBA color, OSD_FORMAT format = OSD_ARGB8888);
RGBA get_color(uint8_t *ptr, OSD_FORMAT format);
void set_color(uint8_t *ptr, RGBA color, OSD_FORMAT format);
void osd_cmpr_frame_init(OSDCmpr_Ctrl *p_ctrl);
int osd_cmpr_enc_one_frame(uint8_t *ibuf, uint8_t *obs, OSDCmpr_Ctrl *p_ctrl);
void osd_cmpr_dec_one_frame(uint8_t *bsbuf, size_t bs_size, uint8_t *obuf,
OSDCmpr_Ctrl *p_ctrl);
void osd_cmpr_enc_header(uint8_t *hdrbuf, OSDCmpr_Ctrl *p_ctrl);
void osd_cmpr_dec_header(uint8_t *hdrbuf, OSDCmpr_Ctrl *p_ctrl);
void osd_cmpr_setup(OSDCmpr_Ctrl *p_ctrl, OSDCmpr_Cfg *p_cfg);
void osd_cmpr_enc_const_pixel(RGBA cur_c, RGBA *last_c, int *rl_cnt,
MODE_TYPE *md, CODE *code, uint16_t *length,
bool is_force_new_run, uint16_t max_run_len,
OSDCmpr_Ctrl *p_ctrl, StreamBuffer *bitstream);
void osd_cmpr_enc_followed_run(RGBA cur_c, int *rl_cnt, MODE_TYPE *md,
CODE *code, uint16_t *length, uint16_t max_run_len,
OSDCmpr_Ctrl *p_ctrl, StreamBuffer *bitstream);
size_t osd_cmpr_get_pixel_sz(OSD_FORMAT format);
size_t osd_cmpr_get_bs_buf_max_sz(int pel_num, int pel_sz);
size_t osd_cmpr_get_header_sz(void);
void osd_cmpr_debug_frame_compare(OSDCmpr_Ctrl *p_ctrl, uint8_t *buf0,
uint8_t *buf1);
void palette_cache_init(PaletteRGBA *cache, int cache_sz);
int palette_cache_lookup_color(PaletteRGBA *cache, RGBA color);
void palette_cache_lru_update(PaletteRGBA *cache, int index);
void palette_cache_push_color(PaletteRGBA *cache, RGBA color);
#endif /* __OSD_CMPR_H__ */

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#ifndef __RTOS_COMMAND_QUEUE__
#define __RTOS_COMMAND_QUEUE__
#ifdef __linux__
#include <linux/kernel.h>
#endif
#define NR_SYSTEM_CMD 20
#define NR_RTOS_CMD 127
#define NR_RTOS_IP IP_LIMIT
enum IP_TYPE {
IP_ISP = 0,
IP_VCODEC,
IP_VIP,
IP_VI,
IP_RGN,
IP_AUDIO,
IP_SYSTEM,
IP_CAMERA,
IP_LIMIT,
};
enum SYS_CMD_ID {
SYS_CMD_INFO_TRANS = 0x50,
SYS_CMD_INFO_LINUX_INIT_DONE,
SYS_CMD_INFO_RTOS_INIT_DONE,
SYS_CMD_INFO_STOP_ISR,
SYS_CMD_INFO_STOP_ISR_DONE,
SYS_CMD_INFO_LINUX,
SYS_CMD_INFO_RTOS,
SYS_CMD_SYNC_TIME,
SYS_CMD_INFO_DUMP_MSG,
SYS_CMD_INFO_DUMP_EN,
SYS_CMD_INFO_DUMP_DIS,
SYS_CMD_INFO_DUMP_JPG,
SYS_CMD_INFO_TRACE_SNAPSHOT_START,
SYS_CMD_INFO_TRACE_SNAPSHOT_STOP,
SYS_CMD_INFO_TRACE_STREAM_START,
SYS_CMD_INFO_TRACE_STREAM_STOP,
SYS_CMD_INFO_LIMIT,
};
struct valid_t {
unsigned char linux_valid;
unsigned char rtos_valid;
} __attribute__((packed));
typedef union resv_t {
struct valid_t valid;
unsigned short mstime; // 0 : noblock, -1 : block infinite
} resv_t;
typedef struct cmdqu_t cmdqu_t;
/* cmdqu size should be 8 bytes because of mailbox buffer size */
struct cmdqu_t {
unsigned char ip_id;
unsigned char cmd_id : 7;
unsigned char block : 1;
union resv_t resv;
unsigned int param_ptr;
} __attribute__((packed)) __attribute__((aligned(0x8)));
#ifdef __linux__
/* keep those commands for ioctl system used */
enum SYSTEM_CMD_TYPE {
CMDQU_SEND = 1,
CMDQU_REQUEST,
CMDQU_REQUEST_FREE,
CMDQU_SEND_WAIT,
CMDQU_SEND_WAKEUP,
CMDQU_SYSTEM_LIMIT = NR_SYSTEM_CMD,
};
#define RTOS_CMDQU_DEV_NAME "cvi-rtos-cmdqu"
#define RTOS_CMDQU_SEND _IOW('r', CMDQU_SEND, unsigned long)
#define RTOS_CMDQU_REQUEST _IOW('r', CMDQU_REQUEST, unsigned long)
#define RTOS_CMDQU_REQUEST_FREE _IOW('r', CMDQU_REQUEST_FREE, unsigned long)
#define RTOS_CMDQU_SEND_WAIT _IOW('r', CMDQU_SEND_WAIT, unsigned long)
#define RTOS_CMDQU_SEND_WAKEUP _IOW('r', CMDQU_SEND_WAKEUP, unsigned long)
int rtos_cmdqu_send(cmdqu_t *cmdq);
int rtos_cmdqu_send_wait(cmdqu_t *cmdq, int wait_cmd_id);
int request_rtos_irq(unsigned char ip_id, void *handler, const char *devname, void *dev_id);
int free_rtos_irq(unsigned char ip_id);
#endif // end of __linux__
#endif // end of __RTOS_COMMAND_QUEUE__

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#ifndef __SENSOR_GAIN_TABLE_H__
#define __SENSOR_GAIN_TABLE_H__
extern const uint32_t imx327_gain_table[];
#endif // __SENSOR_GAIN_TABLE_H__

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#ifndef __CV_IMAGE_SENSOR_H__
#define __CV_IMAGE_SENSOR_H__
#include <delay.h>
#include "cvi_comm_video.h"
#include "cvi_common.h"
#include "cvi_comm_vi.h"
#include "cvi_comm_isp.h"
#include "cvi_sns_ctrl.h"
#include "cif_uapi.h"
#include "gpio.h"
#include "sample_comm.h"
#define TPU_SRAM_BASE_ADDR (0x0C020000)
#define TPU_SRAM_BASE_SIZE (0x00010000)
#define RTC_SRAM_BASE_ADDR (0x05200000)
#define RTC_SRAM_BASE_SIZE (24 << 10) // 24KB
//#define SENSOR_USE_I2C_DMA 0
#define CHECK_SENSOR_ID 1
#define SEN_CFG_ADDR (RTC_SRAM_BASE_SIZE - 1024)
#define SEN_CFG_INI_ADDR (RTC_SRAM_BASE_SIZE - 1024)
#define SYSDMA_LLP_ADDR (RTC_SRAM_BASE_SIZE - 1024)
#define SEN_ITB_START_ADDR (RTC_SRAM_BASE_SIZE - 1024)
#define SEN_MAX_LANE_NUM (MIPI_LANE_NUM + 1) // 1C4D
#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))
#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a))
/* Sensor resolutions */
#define SENSOR_RES_IS_2160P(w, h) ((w) <= 3840 && (h) <= 2160)
#define SENSOR_RES_IS_1440P(w, h) ((w) <= 2560 && (h) <= 1440)
#define SENSOR_RES_IS_1080P(w, h) ((w) <= 1920 && (h) <= 1080)
#define SENSOR_RES_IS_720P(w, h) ((w) <= 1280 && (h) <= 720)
#define delay_ms(a) mdelay(a)
enum HDR_EXPOSURE_FRAME_ID {
SHORT_EXP_ID,
LONG_EXP_ID,
};
enum IMAGE_FORMAT_E {
BAYER_RAW12 = 0,
BAYER_RAW10,
BAYER_RAW8,
BAYER_FORMAT_NUM,
YUV422_8B = BAYER_FORMAT_NUM,
YUV422_10B,
};
/*
* To indicate the 1st two pixel in the bayer_raw.
*/
enum DPHY_LANE_NUM {
DPHY_1_DLANE = 0,
DPHY_2_DLANE = 1,
DPHY_4_DLANE = 3,
DPHY_8_DLANE = 7
};
enum HDR_MODE_E {
HDR_MODE_VC, // CSI
HDR_MODE_ID, // CSI
HDR_MODE_DT, // CSI
HDR_MODE_DOL, // CSI
HDR_MODE_PAT1, // SLVDS
HDR_MODE_PAT2, // SLVDS
HDR_MODE_LINEAR = 0xF
};
enum ISP_BAYER_TYPE {
ISP_BAYER_TYPE_BG = 0,
ISP_BAYER_TYPE_GB,
ISP_BAYER_TYPE_GR,
ISP_BAYER_TYPE_RG,
// ISP_BAYER_TYPE_MAX,
};
typedef struct _ISP_HDR_SIZE_S {
RECT_S stWndRect;
SIZE_S stSnsSize;
// SIZE_S stMaxSize;
} ISP_HDR_SIZE_S;
typedef struct _SIMPLE_AE_CTRL_S {
uint32_t seLuma;
uint32_t seExp;
uint32_t seGain;
uint32_t leLuma;
uint32_t leExp;
uint32_t leGain;
uint16_t rWb_Gain;
uint16_t bWb_Gain;
} SIMPLE_AE_CTRL_S;
/* define of Linux
typedef struct _SAMPLE_SENSOR_INFO_S {
SAMPLE_SNS_TYPE_E enSnsType;
CVI_S32 s32SnsId;
CVI_S32 s32BusId;
CVI_S32 s32SnsI2cAddr;
combo_dev_t MipiDev;
CVI_S16 as16LaneId[5];
CVI_S8 as8PNSwap[5];
CVI_U8 u8HwSync;
SAMPLE_SENSOR_MCLK_ATTR_S stMclkAttr;
CVI_U8 u8Orien; // 0: normal, 1: mirror, 2: flip, 3: mirror and flip.
} SAMPLE_SENSOR_INFO_S;
*/
typedef struct _SENSOR_CFG_INI_HEADER {
uint32_t magic_num; // date for check
uint16_t dev_num; // totla sensor number
uint16_t cfg_ofs; // sizeof SENSOR_USR_CFG
} __attribute__((packed)) __attribute__((aligned(0x8))) SENSOR_CFG_INI_HEADER;
typedef struct _SENSOR_USR_CFG_INI {
char name[64]; // sensor name
uint8_t devno; // support 0:sensor0, 1:sensor1, 2: sensor2
uint8_t mclk_en; // enable of mclk (0: driver default, 1: mclk0 enable, 2:maclk1 enable)
uint8_t mclk; // mclk clock
// i2c info
int8_t slave_id; // slave id (slave addr[7:1]) 0: use default
int8_t bus_id; // i2c bus id
// lane info
uint8_t mipi_dev; // MIPI phy number,
uint8_t hs_settle; // 0: use default
int8_t lane_id[SEN_MAX_LANE_NUM]; // {clk, d0 ,d1, d2, d3}
int8_t pn_swap[SEN_MAX_LANE_NUM]; // {clk, d0 ,d1, d2, d3}
uint8_t u8HwSync;
uint8_t u8Orien; // 0: normal, 1: mirror, 2: flip, 3: mirror and flip.
// reset-pin info
uint32_t snsr_reset; // sensor reset pin
uint8_t reset_act; // sensor reset low/high act fill by sensor driver
uint32_t reset_delay; // delay us after reset
} __attribute__((packed)) __attribute__((aligned(0x8))) SENSOR_USR_CFG;
typedef struct _SENSOR_INFO {
SENSOR_CFG_INI_HEADER *header;
SENSOR_USR_CFG *cfg; // load from flash
ISP_SNS_OBJ_S *pstSnsObj;
enum input_mode_e vi_mode; // fill by sensor name
enum IMAGE_FORMAT_E format; // fill by sensor driver
enum ISP_BAYER_TYPE bayer_type; // fill by sensor driver
enum HDR_MODE_E hdr_mode; // fill by sensor name
VI_WORK_MODE_E chn; // fill by sensor name
enum DPHY_LANE_NUM lane_num; // fill by sensor name
uint32_t width; // output width fill by sensor name
uint32_t height; // output height fill by sensor name
uint8_t init_ok; // sensor init success
} SENSOR_INFO;
/*
* Support Sensor Objects
*/
// extern ISP_SNS_OBJ_S stSnsImx327_Obj;
extern const char *snsr_type_name[SAMPLE_SNS_TYPE_BUTT];
/*
* Sensor I2C API
*/
int sensor_i2c_init(VI_PIPE ViPipe, uint8_t u8I2cDev, uint16_t speed,
uint8_t slave_addr, uint8_t alen, uint8_t dlen);
int sensor_i2c_exit(VI_PIPE ViPipe);
int sensor_read_register(VI_PIPE ViPipe, int addr);
int sensor_write_register(VI_PIPE ViPipe, int addr, int data);
/*
* Sensor API
*/
extern int32_t cmos_set_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo);
#endif //__CV_IMAGE_SENSOR_H__

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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DRV_SPINLOCK_H__
#define __DRV_SPINLOCK_H__
enum SPINLOCK_FIELD {
SPIN_UART,
SPIN_LINUX_RTOS = 4, // this spinlock field is used for linux & rtos
SPIN_MBOX = SPIN_LINUX_RTOS,
SPIN_MAX = 7,
};
typedef struct hw_raw_spinlock {
unsigned short locks;
unsigned short hw_field;
} hw_raw_spinlock_t;
#define MAILBOX_LOCK_SUCCESS 1
#define MAILBOX_LOCK_FAILED (-1)
#define __CVI_ARCH_SPIN_LOCK_UNLOCKED { 0 }
#define __CVI_RAW_SPIN_LOCK_INITIALIZER(spinlock_hw_field) \
{ \
.locks = __CVI_ARCH_SPIN_LOCK_UNLOCKED, \
.hw_field = spinlock_hw_field, \
}
#define DEFINE_CVI_SPINLOCK(x, y) hw_raw_spinlock_t x = __CVI_RAW_SPIN_LOCK_INITIALIZER(y)
int _hw_raw_spin_lock_irqsave(hw_raw_spinlock_t *lock);
void _hw_raw_spin_unlock_irqrestore(hw_raw_spinlock_t *lock, int flag);
#define drv_spin_lock_irqsave(lock, flags) \
{ flags = _hw_raw_spin_lock_irqsave(lock); }
#define drv_spin_unlock_irqrestore(lock, flags) \
_hw_raw_spin_unlock_irqrestore(lock, flags)
void spinlock_base(unsigned long mb_base);
void cvi_spinlock_init(void);
#endif // end of __DRV_SPINLOCK_H__

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#ifndef __DUMP_UART_H__
#define __DUMP_UART_H__
#define DUMP_PRINT_DEFAULT_SIZE 0x1000
/* this structure should be modified both freertos & osdrv side */
struct dump_uart_s {
uint64_t dump_uart_ptr;
unsigned int dump_uart_max_size;
unsigned int dump_uart_pos;
unsigned char dump_uart_enable;
unsigned char dump_uart_overflow;
} __attribute__((packed));
#ifndef __linux__
/* used for freertos */
struct dump_uart_s *dump_uart_init(void);
struct dump_uart_s *dump_uart_msg(void);
void dump_uart_enable(void);
void dump_uart_disable(void);
#endif
#endif // end of __DUMP_UART_H__

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#ifndef _UART_H_
#define _UART_H_
#ifdef __riscv
#include <stdint.h>
#else
#include "linux/types.h"
#endif
void uart_init(void);
int uart_getc(void);
int uart_tstc(void);
uint8_t uart_putc(uint8_t ch);
void uart_puts(char *str);
int uart_put_buff(char *buf);
#endif

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#ifndef __CVI_VI_H__
#define __CVI_VI_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
#include <cvi_comm_vi.h>
CVI_S32 CVI_VI_SetDevAttr(VI_DEV ViDev, const VI_DEV_ATTR_S *pstDevAttr);
CVI_S32 CVI_VI_Start(CVI_U32 addr, CVI_U32 size);
CVI_S32 CVI_VI_Stop(CVI_VOID);
CVI_VOID CVI_VI_UT_MAIN(CVI_U32 addr, CVI_U32 size);
QueueHandle_t CVI_VI_GetQueHandle(CVI_VOID);
CVI_VOID CVI_VI_QBUF(CVI_VOID);
#ifdef __cplusplus
}
#endif
#endif /* __CVI_VI_H__ */

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#ifndef __CVI_VI_CTX_H__
#define __CVI_VI_CTX_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <cvi_defines.h>
#include <cvi_comm_vi.h>
struct cvi_vi_ctx {
CVI_U8 total_chn_num;
CVI_U8 total_dev_num;
CVI_BOOL is_enable[VI_MAX_CHN_NUM];
CVI_BOOL isDevEnable[VI_MAX_DEV_NUM];
CVI_BOOL isTile;
// dev
VI_DEV_ATTR_S devAttr[VI_MAX_DEV_NUM];
// chn
VI_CHN_STATUS_S chnStatus[VI_MAX_CHN_NUM];
CVI_U32 blk_size[VI_MAX_CHN_NUM];
CVI_U32 timeout_cnt;
CVI_U8 bypass_frm[VI_MAX_CHN_NUM];
CVI_U32 vi_mem_base;
CVI_U32 vi_mem_size;
};
#ifdef __cplusplus
}
#endif
#endif /* __CVI_VI_CTX_H__ */

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#ifndef _ISP_REG_H_
#define _ISP_REG_H_
#include "vi_reg_fields.h"
#include "vi_reg_blocks.h"
#define FPGA_TEST
/* ISP BLOCK ADDR OFFSET DEFINE */
#define ISP_BLK_BA_PRE_RAW_FE0 (0x00000000)
#define ISP_BLK_BA_CSIBDG0 (0x00000800)
#define ISP_BLK_BA_DMA_CTL6 (0x00000B00)
#define ISP_BLK_BA_DMA_CTL7 (0x00000C00)
#define ISP_BLK_BA_DMA_CTL8 (0x00000D00)
#define ISP_BLK_BA_DMA_CTL9 (0x00000E00)
#define ISP_BLK_BA_BLC0 (0x00001000)
#define ISP_BLK_BA_BLC1 (0x00001800)
#define ISP_BLK_BA_RGBMAP0 (0x00002000)
#define ISP_BLK_BA_WBG2 (0x00002100)
#define ISP_BLK_BA_DMA_CTL10 (0x00002200)
#define ISP_BLK_BA_RGBMAP1 (0x00002300)
#define ISP_BLK_BA_WBG3 (0x00002400)
#define ISP_BLK_BA_DMA_CTL11 (0x00002500)
#define ISP_BLK_BA_PRE_RAW_FE1 (0x00008000)
#define ISP_BLK_BA_CSIBDG1 (0x00008800)
#define ISP_BLK_BA_DMA_CTL12 (0x00008B00)
#define ISP_BLK_BA_DMA_CTL13 (0x00008C00)
#define ISP_BLK_BA_DMA_CTL14 (0x00008D00)
#define ISP_BLK_BA_DMA_CTL15 (0x00008E00)
#define ISP_BLK_BA_BLC2 (0x00009000)
#define ISP_BLK_BA_BLC3 (0x00009800)
#define ISP_BLK_BA_RGBMAP2 (0x0000A000)
#define ISP_BLK_BA_WBG4 (0x0000A100)
#define ISP_BLK_BA_DMA_CTL16 (0x0000A200)
#define ISP_BLK_BA_RGBMAP3 (0x0000A300)
#define ISP_BLK_BA_WBG5 (0x0000A400)
#define ISP_BLK_BA_DMA_CTL17 (0x0000A500)
#define ISP_BLK_BA_PRE_RAW_FE2 (0x00010000)
#define ISP_BLK_BA_CSIBDG2 (0x00010800)
#define ISP_BLK_BA_DMA_CTL18 (0x00010B00)
#define ISP_BLK_BA_DMA_CTL19 (0x00010C00)
#define ISP_BLK_BA_BLC4 (0x00011000)
#define ISP_BLK_BA_RGBMAP4 (0x00012000)
#define ISP_BLK_BA_WBG6 (0x00012100)
#define ISP_BLK_BA_DMA_CTL20 (0x00012200)
#define ISP_BLK_BA_PRE_RAW_BE (0x00018000)
#define ISP_BLK_BA_CROP0 (0x00018800)
#define ISP_BLK_BA_CROP1 (0x00019000)
#define ISP_BLK_BA_BLC5 (0x00019800)
#define ISP_BLK_BA_BLC6 (0x0001A000)
#define ISP_BLK_BA_AF (0x0001A800)
#define ISP_BLK_BA_DMA_CTL21 (0x0001AA00)
#define ISP_BLK_BA_DPC0 (0x0001B000)
#define ISP_BLK_BA_DPC1 (0x0001B100)
#define ISP_BLK_BA_DMA_CTL22 (0x0001B800)
#define ISP_BLK_BA_DMA_CTL23 (0x0001B880)
#define ISP_BLK_BA_PRE_WDMA (0x0001B900)
#define ISP_BLK_BA_PCHK0 (0x0001C000)
#define ISP_BLK_BA_PCHK1 (0x0001C800)
#define ISP_BLK_BA_RAWTOP (0x00030000)
#define ISP_BLK_BA_CFA (0x00031000)
#define ISP_BLK_BA_LSC (0x00032000)
#define ISP_BLK_BA_DMA_CTL24 (0x00032100)
#define ISP_BLK_BA_GMS (0x00033000)
#define ISP_BLK_BA_DMA_CTL25 (0x00033100)
#define ISP_BLK_BA_AEHIST0 (0x00034000)
#define ISP_BLK_BA_DMA_CTL26 (0x00034400)
#define ISP_BLK_BA_AEHIST1 (0x00035000)
#define ISP_BLK_BA_DMA_CTL27 (0x00035400)
#define ISP_BLK_BA_DMA_CTL28 (0x00036000)
#define ISP_BLK_BA_DMA_CTL29 (0x00036080)
#define ISP_BLK_BA_RAW_RDMA (0x00036100)
#define ISP_BLK_BA_BNR (0x0003C000)
#define ISP_BLK_BA_CROP2 (0x0003D000)
#define ISP_BLK_BA_CROP3 (0x0003E000)
#define ISP_BLK_BA_LMAP0 (0x0003F000)
#define ISP_BLK_BA_DMA_CTL30 (0x0003F100)
#define ISP_BLK_BA_LMAP1 (0x0003F200)
#define ISP_BLK_BA_DMA_CTL31 (0x0003F300)
#define ISP_BLK_BA_WBG0 (0x00040000)
#define ISP_BLK_BA_WBG1 (0x00041000)
#define ISP_BLK_BA_PCHK2 (0x00042000)
#define ISP_BLK_BA_PCHK3 (0x00043000)
#define ISP_BLK_BA_LCAC (0x00044000)
#define ISP_BLK_BA_RGBCAC (0x00045000)
#define ISP_BLK_BA_RGBTOP (0x00050000)
#define ISP_BLK_BA_CCM0 (0x00052000)
#define ISP_BLK_BA_CCM1 (0x00052100)
#define ISP_BLK_BA_RGBGAMMA (0x00052200)
#define ISP_BLK_BA_YGAMMA (0x00052300)
#define ISP_BLK_BA_MMAP (0x00053000)
#define ISP_BLK_BA_DMA_CTL32 (0x00053200)
#define ISP_BLK_BA_DMA_CTL33 (0x00053300)
#define ISP_BLK_BA_DMA_CTL34 (0x00053400)
#define ISP_BLK_BA_DMA_CTL35 (0x00053500)
#define ISP_BLK_BA_DMA_CTL36 (0x00053600)
#define ISP_BLK_BA_DMA_CTL37 (0x00053700)
#define ISP_BLK_BA_CLUT (0x00054000)
#define ISP_BLK_BA_DHZ (0x00055000)
#define ISP_BLK_BA_CSC (0x00056000)
#define ISP_BLK_BA_RGBDITHER (0x00057000)
#define ISP_BLK_BA_PCHK4 (0x00059000)
#define ISP_BLK_BA_PCHK5 (0x0005A000)
#define ISP_BLK_BA_HIST_V (0x0005C000)
#define ISP_BLK_BA_DMA_CTL38 (0x0005C100)
#define ISP_BLK_BA_HDRFUSION (0x0005D000)
#define ISP_BLK_BA_HDRLTM (0x0005E000)
#define ISP_BLK_BA_DMA_CTL39 (0x0005E100)
#define ISP_BLK_BA_DMA_CTL40 (0x0005E200)
#define ISP_BLK_BA_YUVTOP (0x00060000)
#define ISP_BLK_BA_TNR (0x00061000)
#define ISP_BLK_BA_DMA_CTL41 (0x00061800)
#define ISP_BLK_BA_DMA_CTL42 (0x00061900)
#define ISP_BLK_BA_FBCE (0x00061A00)
#define ISP_BLK_BA_DMA_CTL43 (0x00061B00)
#define ISP_BLK_BA_DMA_CTL44 (0x00061C00)
#define ISP_BLK_BA_FBCD (0x00061D00)
#define ISP_BLK_BA_YUVDITHER (0x00061E00)
#define ISP_BLK_BA_CA (0x00062000)
#define ISP_BLK_BA_CA_LITE (0x00063000)
#define ISP_BLK_BA_YNR (0x00064000)
#define ISP_BLK_BA_CNR (0x00065000)
#define ISP_BLK_BA_EE (0x00066000)
#define ISP_BLK_BA_YCURVE (0x00067000)
#define ISP_BLK_BA_DCI (0x00068000)
#define ISP_BLK_BA_DMA_CTL45 (0x00068100)
#define ISP_BLK_BA_DCI_GAMMA (0x00068200)
#define ISP_BLK_BA_CROP4 (0x00069000)
#define ISP_BLK_BA_DMA_CTL46 (0x00069100)
#define ISP_BLK_BA_CROP5 (0x0006A000)
#define ISP_BLK_BA_DMA_CTL47 (0x0006A100)
#define ISP_BLK_BA_LDCI (0x0006B000)
#define ISP_BLK_BA_DMA_CTL48 (0x0006B300)
#define ISP_BLK_BA_DMA_CTL49 (0x0006B400)
#define ISP_BLK_BA_PRE_EE (0x0006C000)
#define ISP_BLK_BA_PCHK6 (0x0006D000)
#define ISP_BLK_BA_PCHK7 (0x0006E000)
#define ISP_BLK_BA_ISPTOP (0x00070000)
#define ISP_BLK_BA_WDMA_CORE0 (0x00072000)
#define ISP_BLK_BA_RDMA_CORE (0x00074000)
#define ISP_BLK_BA_CSIBDG_LITE (0x00076000)
#define ISP_BLK_BA_DMA_CTL0 (0x00076200)
#define ISP_BLK_BA_DMA_CTL1 (0x00076300)
#define ISP_BLK_BA_DMA_CTL2 (0x00076400)
#define ISP_BLK_BA_DMA_CTL3 (0x00076500)
#define ISP_BLK_BA_WDMA_CORE1 (0x00078000)
#define ISP_BLK_BA_PRE_RAW_VI_SEL (0x0007F400)
#define ISP_BLK_BA_DMA_CTL4 (0x0007F500)
#define ISP_BLK_BA_DMA_CTL5 (0x0007F600)
#define ISP_BLK_BA_CMDQ (0x0007FC00)
enum ISP_BLK_ID_T {
ISP_BLK_ID_PRE_RAW_FE0,
ISP_BLK_ID_CSIBDG0,
ISP_BLK_ID_DMA_CTL6,
ISP_BLK_ID_DMA_CTL7,
ISP_BLK_ID_DMA_CTL8,
ISP_BLK_ID_DMA_CTL9,
ISP_BLK_ID_BLC0,
ISP_BLK_ID_BLC1,
ISP_BLK_ID_RGBMAP0,
ISP_BLK_ID_WBG2,
ISP_BLK_ID_DMA_CTL10, //10
ISP_BLK_ID_RGBMAP1,
ISP_BLK_ID_WBG3,
ISP_BLK_ID_DMA_CTL11, //13
ISP_BLK_ID_PRE_RAW_FE1,
ISP_BLK_ID_CSIBDG1,
ISP_BLK_ID_DMA_CTL12,
ISP_BLK_ID_DMA_CTL13,
ISP_BLK_ID_DMA_CTL14,
ISP_BLK_ID_DMA_CTL15,
ISP_BLK_ID_BLC2,
ISP_BLK_ID_BLC3,
ISP_BLK_ID_RGBMAP2,
ISP_BLK_ID_WBG4,
ISP_BLK_ID_DMA_CTL16,
ISP_BLK_ID_RGBMAP3,
ISP_BLK_ID_WBG5,
ISP_BLK_ID_DMA_CTL17,
ISP_BLK_ID_PRE_RAW_FE2,
ISP_BLK_ID_CSIBDG2,
ISP_BLK_ID_DMA_CTL18,
ISP_BLK_ID_DMA_CTL19,
ISP_BLK_ID_BLC4,
ISP_BLK_ID_RGBMAP4,
ISP_BLK_ID_WBG6,
ISP_BLK_ID_DMA_CTL20,
ISP_BLK_ID_PRE_RAW_BE,
ISP_BLK_ID_CROP0,
ISP_BLK_ID_CROP1,
ISP_BLK_ID_BLC5,
ISP_BLK_ID_BLC6,
ISP_BLK_ID_AF,
ISP_BLK_ID_DMA_CTL21,
ISP_BLK_ID_DPC0,
ISP_BLK_ID_DPC1,
ISP_BLK_ID_DMA_CTL22, //45
ISP_BLK_ID_DMA_CTL23, //46
ISP_BLK_ID_PRE_WDMA,
ISP_BLK_ID_PCHK0,
ISP_BLK_ID_PCHK1,
ISP_BLK_ID_RAWTOP,
ISP_BLK_ID_CFA,
ISP_BLK_ID_LSC,
ISP_BLK_ID_DMA_CTL24, //53
ISP_BLK_ID_GMS,
ISP_BLK_ID_DMA_CTL25, //55
ISP_BLK_ID_AEHIST0,
ISP_BLK_ID_DMA_CTL26, //57
ISP_BLK_ID_AEHIST1,
ISP_BLK_ID_DMA_CTL27, //59
ISP_BLK_ID_DMA_CTL28,
ISP_BLK_ID_DMA_CTL29,
ISP_BLK_ID_RAW_RDMA,
ISP_BLK_ID_BNR,
ISP_BLK_ID_CROP2,
ISP_BLK_ID_CROP3,
ISP_BLK_ID_LMAP0,
ISP_BLK_ID_DMA_CTL30, //67
ISP_BLK_ID_LMAP1,
ISP_BLK_ID_DMA_CTL31,
ISP_BLK_ID_WBG0,
ISP_BLK_ID_WBG1,
ISP_BLK_ID_PCHK2,
ISP_BLK_ID_PCHK3,
ISP_BLK_ID_LCAC,
ISP_BLK_ID_RGBCAC,
ISP_BLK_ID_RGBTOP,
ISP_BLK_ID_CCM0,
ISP_BLK_ID_CCM1,
ISP_BLK_ID_RGBGAMMA,
ISP_BLK_ID_YGAMMA,
ISP_BLK_ID_MMAP,
ISP_BLK_ID_DMA_CTL32,
ISP_BLK_ID_DMA_CTL33,
ISP_BLK_ID_DMA_CTL34,
ISP_BLK_ID_DMA_CTL35,
ISP_BLK_ID_DMA_CTL36, //86
ISP_BLK_ID_DMA_CTL37,
ISP_BLK_ID_CLUT,
ISP_BLK_ID_DHZ,
ISP_BLK_ID_CSC,
ISP_BLK_ID_RGBDITHER,
ISP_BLK_ID_PCHK4,
ISP_BLK_ID_PCHK5,
ISP_BLK_ID_HIST_V,
ISP_BLK_ID_DMA_CTL38, //95
ISP_BLK_ID_HDRFUSION,
ISP_BLK_ID_HDRLTM,
ISP_BLK_ID_DMA_CTL39,
ISP_BLK_ID_DMA_CTL40,
ISP_BLK_ID_YUVTOP,
ISP_BLK_ID_TNR,
ISP_BLK_ID_DMA_CTL41, //102
ISP_BLK_ID_DMA_CTL42,
ISP_BLK_ID_FBCE,
ISP_BLK_ID_DMA_CTL43, //105
ISP_BLK_ID_DMA_CTL44,
ISP_BLK_ID_FBCD,
ISP_BLK_ID_YUVDITHER,
ISP_BLK_ID_CA,
ISP_BLK_ID_CA_LITE,
ISP_BLK_ID_YNR,
ISP_BLK_ID_CNR,
ISP_BLK_ID_EE,
ISP_BLK_ID_YCURVE,
ISP_BLK_ID_DCI,
ISP_BLK_ID_DMA_CTL45, //116
ISP_BLK_ID_DCI_GAMMA,
ISP_BLK_ID_CROP4,
ISP_BLK_ID_DMA_CTL46,
ISP_BLK_ID_CROP5,
ISP_BLK_ID_DMA_CTL47,
ISP_BLK_ID_LDCI,
ISP_BLK_ID_DMA_CTL48,
ISP_BLK_ID_DMA_CTL49,
ISP_BLK_ID_PRE_EE,
ISP_BLK_ID_PCHK6,
ISP_BLK_ID_PCHK7,
ISP_BLK_ID_ISPTOP,
ISP_BLK_ID_WDMA_CORE0,
ISP_BLK_ID_RDMA_CORE,
ISP_BLK_ID_CSIBDG_LITE,
ISP_BLK_ID_DMA_CTL0,
ISP_BLK_ID_DMA_CTL1,
ISP_BLK_ID_DMA_CTL2,
ISP_BLK_ID_DMA_CTL3,
ISP_BLK_ID_WDMA_CORE1,
ISP_BLK_ID_PRE_RAW_VI_SEL,
ISP_BLK_ID_DMA_CTL4,
ISP_BLK_ID_DMA_CTL5,
ISP_BLK_ID_CMDQ,
ISP_BLK_ID_MAX
};
#endif //_ISP_REG_H_

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#ifndef __VI_H__
#define __VI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <vi_tun_cfg.h>
#include <vi_isp.h>
#include <vi_uapi.h>
#include <vi_common.h>
#include <vi_defines.h>
#define OFFLINE_RAW_BUF_NUM 2
#define OFFLINE_PRE_BE_BUF_NUM 2
#define OFFLINE_YUV_BUF_NUM 2
#define MAX_RGBMAP_BUF_NUM 3
enum cvi_isp_postraw_state {
ISP_POSTRAW_IDLE,
ISP_POSTRAW_RUNNING,
};
enum cvi_isp_pre_be_state {
ISP_PRE_BE_IDLE,
ISP_PRE_BE_RUNNING,
};
enum cvi_isp_preraw_state {
ISP_PRERAW_IDLE,
ISP_PRERAW_RUNNING,
};
struct vi_plane {
__u64 addr;
};
/*
* @index:
* @length: length of planes
* @planes: to describe buf
* @reserved
*/
struct vi_buffer {
__u32 index;
__u32 length;
struct vi_plane planes[3];
__u32 reserved;
};
/* struct mempool
* @base: the address of the mempool
* @size: the size of the mempool
* @byteused: the number of bytes used
*/
struct _mempool {
uint64_t base;
uint32_t size;
uint32_t byteused;
} isp_mempool;
struct _membuf {
uint64_t bayer_le[OFFLINE_RAW_BUF_NUM];
uint64_t bayer_se[OFFLINE_RAW_BUF_NUM];
uint64_t prebe_le[OFFLINE_PRE_BE_BUF_NUM];
uint64_t prebe_se[OFFLINE_PRE_BE_BUF_NUM];
uint64_t yuv_yuyv[ISP_CHN_MAX][2];//yuv sensor is yuyv format
uint64_t manr;
uint64_t rgbmap_le[MAX_RGBMAP_BUF_NUM];
uint64_t rgbmap_se[MAX_RGBMAP_BUF_NUM];
uint64_t lmap_le;
uint64_t lmap_se;
uint64_t lsc;
uint64_t tdnr[4];//0 for UV, 1 for Y, 2 for uv fbc double buffer, 3 for y fbc double buffer
uint64_t ldci;
//struct cvi_vip_isp_fswdr_report *fswdr_rpt;
struct cvi_isp_sts_mem sts_mem[2];
uint8_t pre_fe_sts_busy_idx;
uint8_t pre_be_sts_busy_idx;
uint8_t post_sts_busy_idx;
//spinlock_t pre_fe_sts_lock;
//uint8_t pre_fe_sts_in_use;
//spinlock_t pre_be_sts_lock;
//uint8_t pre_be_sts_in_use;
//spinlock_t post_sts_lock;
//uint8_t post_sts_in_use;
} isp_bufpool[ISP_PRERAW_MAX] = {0};
static u8 RGBMAP_BUF_IDX = 2;
/* viproc control for sensor numbers */
static int viproc_en[2] = {1, 0};
/* control internal patgen
*
* 1: enable
* 0: disable
*/
static int csi_patgen_en[ISP_PRERAW_MAX] = {0, 0};
/* runtime tuning control
* ctrl:
* 0: all ch stop update.
* 1: stop after apply ch1 setting
* 2: stop after apply ch2 setting
*/
int tuning_dis[4] = {0, 0, 0, 0}; //ctrl, fe, be, post
/* Runtime to enable/disable isp_top_clk
* Ctrl:
* 0: Disable isp_top_clk dynamic contorl
* 1: Enable isp_top_clk dynamic control
*/
int clk_dynamic_en;
//void _pre_hw_enque(
// struct cvi_vi_dev *vdev,
// const enum cvi_isp_raw raw_num,
// const u8 chn_num);
//static void _vi_sw_init(struct cvi_vi_dev *vdev);
//static int _vi_clk_ctrl(struct cvi_vi_dev *vdev, u8 enable);
//void _postraw_outbuf_enq(struct cvi_vi_dev *vdev, const enum cvi_isp_raw raw_num);
static void _vi_deferred_thread(void *arg);
void _vi_send_isp_cmdq(enum cvi_isp_raw raw_num, enum ISP_CMDQ_E cmdq_id, void *ptr);
#ifdef __cplusplus
}
#endif
#endif /* __VI_H__ */

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#ifndef __VI_COMMON_H__
#define __VI_COMMON_H__
#ifdef __cplusplus
extern "C" {
#endif
//#include <linux/clk.h>
//#include <linux/debugfs.h>
//#include <linux/io.h>
#include <stdint.h>
#include <stdbool.h>
#include <types.h>
#include <time.h>
#include "FreeRTOS.h"
#include <fifo.h>
#ifndef NULL
#define NULL 0
#endif
#define NONE 0 /* No errors */
#define ENOENT 2 /* No such file or directory */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define EBADF 9 /* Bad file number */
#define EAGAIN 11 /* No more processes */
#define EWOULDBLOCK 11 /* Operation would block */
#define ENOMEM 12 /* Not enough memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define EBUSY 16 /* Mount device busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read only file system */
#define EUNATCH 42 /* Protocol driver not attached */
#define EBADE 50 /* Invalid exchange */
#define EFTYPE 79 /* Inappropriate file type or format */
#define ENMFILE 89 /* No more files */
#define ENOTEMPTY 90 /* Directory not empty */
#define ENAMETOOLONG 91 /* File or path name too long */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define ENOBUFS 105 /* No buffer space available */
#define ENOPROTOOPT 109 /* Protocol not available */
#define EADDRINUSE 112 /* Address already in use */
#define ETIMEDOUT 116 /* Connection timed out */
#define EINPROGRESS 119 /* Connection already in progress */
#define EALREADY 120 /* Socket already connected */
#define EADDRNOTAVAIL 125 /* Address not available */
#define EISCONN 127 /* Socket is already connected */
#define ENOTCONN 128 /* Socket is not connected */
#define ENOMEDIUM 135 /* No medium inserted */
#define EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */
#define ECANCELED 140 /* Operation canceled. */
// #define MIN(a, b) (((a) < (b))?(a):(b))
// #define MAX(a, b) (((a) > (b))?(a):(b))
#define VI_64_ALIGN(x) (((x) + 0x3F) & ~0x3F) // for 64byte alignment
#define VI_256_ALIGN(x) (((x) + 0xFF) & ~0xFF) // for 256byte alignment
#define VI_ALIGN(x) (((x) + 0xF) & ~0xF) // for 16byte alignment
#define VI_256_ALIGN(x) (((x) + 0xFF) & ~0xFF) // for 256byte alignment
#define ISP_ALIGN(x, y) (((x) + (y - 1)) & ~(y - 1)) // for any bytes alignment
#define UPPER(x, y) (((x) + ((1 << (y)) - 1)) >> (y)) // for alignment
#define CEIL(x, y) (((x) + ((1 << (y)))) >> (y)) // for alignment
extern u32 vi_log_lv;
#define vi_pr(level, fmt, arg...) \
do { \
if (vi_log_lv & level) { \
if (level == VI_ERR) \
printf("%s:%d(): " fmt, __func__, __LINE__, ## arg); \
else if (level == VI_WARN) \
printf("%s:%d(): " fmt, __func__, __LINE__, ## arg); \
else if (level == VI_NOTICE) \
printf("%s:%d(): " fmt, __func__, __LINE__, ## arg); \
else if (level == VI_INFO) \
printf("%s:%d(): " fmt, __func__, __LINE__, ## arg); \
else if (level == VI_DBG) \
printf("%s:%d(): " fmt, __func__, __LINE__, ## arg); \
} \
} while (0)
enum vi_msg_pri {
VI_ERR = 0x1,
VI_WARN = 0x2,
VI_NOTICE = 0x4,
VI_INFO = 0x8,
VI_DBG = 0x10,
};
struct vi_rect {
u16 x;
u16 y;
u16 w;
u16 h;
};
void _reg_write_mask(uintptr_t addr, u32 mask, u32 data);
int vip_sys_cif_cb(unsigned int cmd, void *arg);
int vip_sys_cmm_cb_i2c(unsigned int cmd, void *arg);
void vip_sys_reg_write_mask(uintptr_t addr, u32 mask, u32 data);
//extern bool __clk_is_enabled(struct clk *clk);
#ifdef __cplusplus
}
#endif
#endif /* __VI_COMMON_H__ */

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#ifndef __VI_CORE_H__
#define __VI_CORE_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <vi_common.h>
#include <vi_defines.h>
/*******************************************************
* Common interface for core
******************************************************/
void vi_irq_handler(struct cvi_vi_dev *vdev);
int vi_create_instance(struct cvi_vi_dev *vdev);
int vi_destroy_instance(void);
int vi_start_streaming(struct cvi_vi_dev *vdev);
int vi_stop_streaming(struct cvi_vi_dev *vdev);
int vi_enq_buf(void);
#ifdef __cplusplus
}
#endif
#endif /* __VI_CORE_H__ */

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#ifndef __VI_DEFINES_H__
#define __VI_DEFINES_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <vi_tun_cfg.h>
#include <vi_isp.h>
#include <vi_drv.h>
#define FPGA_TEST
#define VI_REG_ADDR_BASE 0x0A000000
#define VI_IRQ_NUM 20
/**
* struct cvi_vi - VI IP abstraction
*/
struct cvi_vi_dev {
void *reg_base;
int irq_num;
struct isp_ctx ctx;
struct cvi_isp_mbus_framefmt usr_fmt;
struct cvi_isp_rect usr_crop;
//struct cvi_isp_snr_info snr_info[ISP_PRERAW_MAX];
u32 pre_fe_sof_cnt[ISP_PRERAW_MAX][ISP_FE_CHN_MAX];
u32 pre_fe_frm_num[ISP_PRERAW_MAX][ISP_FE_CHN_MAX];
u32 pre_be_frm_num[ISP_PRERAW_MAX][ISP_BE_CHN_MAX];
bool preraw_first_frm[ISP_PRERAW_MAX];
u32 postraw_frame_number[ISP_PRERAW_MAX];
u32 drop_frame_number[ISP_PRERAW_MAX];
u8 pre_fe_state[ISP_PRERAW_MAX][ISP_FE_CHN_MAX];
u8 pre_be_state[ISP_BE_CHN_MAX];
volatile u8 postraw_state;
u8 isp_streamoff;
u8 isp_streamon;
};
#ifdef __cplusplus
}
#endif
#endif /* __VI_DEFINES_H__ */

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#ifndef __VI_DRV_H__
#define __VI_DRV_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <mmio.h>
#include <isp_reg.h>
#include <vi_reg_blocks.h>
#include <vi_reg_fields.h>
#include <vi_tun_cfg.h>
#include <cvi_vi_ctx.h>
#include <vi_common.h>
#ifndef _OFST
#define _OFST(_BLK_T, _REG) ((uintptr_t)&(((struct _BLK_T *)0)->_REG))
#endif
// #define _reg_read(addr) mmio_read_32((uintptr_t)addr)
// #define _reg_write(addr, data) mmio_write_32((uintptr_t)addr, (uint32_t)data)
#define ISP_RD_REG_BA(_BA) \
(_reg_read(_BA))
#define ISP_RD_REG(_BA, _BLK_T, _REG) \
(_reg_read(_BA+_OFST(_BLK_T, _REG)))
#define ISP_RD_BITS(_BA, _BLK_T, _REG, _FLD) \
({\
typeof(((struct _BLK_T *)0)->_REG) _r;\
_r.raw = _reg_read(_BA+_OFST(_BLK_T, _REG));\
_r.bits._FLD;\
})
#define ISP_WR_REG(_BA, _BLK_T, _REG, _V) \
(_reg_write((_BA+_OFST(_BLK_T, _REG)), _V))
#define ISP_WR_REG_OFT(_BA, _BLK_T, _REG, _OFT, _V) \
(_reg_write((_BA+_OFST(_BLK_T, _REG) + _OFT), _V))
#define ISP_WR_BITS(_BA, _BLK_T, _REG, _FLD, _V) \
do {\
typeof(((struct _BLK_T *)0)->_REG) _r;\
_r.raw = _reg_read(_BA+_OFST(_BLK_T, _REG));\
_r.bits._FLD = _V;\
_reg_write((_BA+_OFST(_BLK_T, _REG)), _r.raw);\
} while (0)
#define ISP_WO_BITS(_BA, _BLK_T, _REG, _FLD, _V) \
do {\
typeof(((struct _BLK_T *)0)->_REG) _r;\
_r.raw = 0;\
_r.bits._FLD = _V;\
_reg_write((_BA+_OFST(_BLK_T, _REG)), _r.raw);\
} while (0)
#define ISP_WR_REGS_BURST(_BA, _BLK_T, _REG, _SIZE, _STR)\
do {\
u32 k = 0;\
uintptr_t ofst = _OFST(_BLK_T, _REG);\
for (; k < sizeof(_SIZE) / 0x4; k++) {\
u32 val = (&_STR + k)->raw;\
_reg_write((_BA + ofst + (k * 0x4)), val);\
} \
} while (0)
#define ISP_WR_REG_LOOP_SHFT(_BA, _BLK_T, _REG, _TOTAL_SIZE, _SFT_SIZE, _LUT, _SFT_BIT) \
do {\
uint16_t i = 0, j = 0;\
uint32_t val = 0;\
for (; i < _TOTAL_SIZE / _SFT_SIZE; i++) {\
val = 0;\
for (j = 0; j < _SFT_SIZE; j++) {\
val += (_LUT[(i * _SFT_SIZE) + j] << (_SFT_BIT * j));\
} \
_reg_write((_BA + _OFST(_BLK_T, _REG) + (i * 0x4)), val);\
} \
} while (0)
#define REG_ARRAY_UPDATE2_SIZE(addr, array, size) \
do { \
uint16_t i; \
for (i = 0; i < size; i += 2) { \
val = array[i]; \
if ((i + 1) < size) \
val |= (array[i+1] << 16); \
_reg_write(addr + (i << 1), val); \
} \
} while (0)
#define REG_ARRAY_UPDATE2(addr, array) \
REG_ARRAY_UPDATE2_SIZE(addr, array, ARRAY_SIZE(array))
#define REG_ARRAY_UPDATE4(addr, array) \
do { \
uint16_t i; \
for (i = 0; i < ARRAY_SIZE(array); i += 4) { \
val = array[i]; \
if ((i + 1) < ARRAY_SIZE(array)) \
val |= (array[i+1] << 8); \
if ((i + 2) < ARRAY_SIZE(array)) \
val |= (array[i+2] << 16); \
if ((i + 3) < ARRAY_SIZE(array)) \
val |= (array[i+3] << 24); \
_reg_write(addr + i, val); \
} \
} while (0)
#define LTM_REG_ARRAY_UPDATE11(addr, array) \
do { \
uint32_t val; \
val = array[0] | (array[1] << 5) | (array[2] << 10) | \
(array[3] << 15) | (array[4] << 20) | (array[5] << 25); \
_reg_write(addr, val); \
val = array[6] | (array[7] << 5) | (array[8] << 10) | \
(array[9] << 15) | (array[10] << 20); \
_reg_write(addr + 4, val); \
} while (0)
#define LTM_REG_ARRAY_UPDATE30(addr, array) \
do { \
uint8_t i, j; \
uint32_t val; \
for (i = 0, j = 0; i < ARRAY_SIZE(array); i += 6, j++) { \
val = array[i] | (array[i + 1] << 5) | \
(array[i + 2] << 10) | (array[i + 3] << 15) | \
(array[i + 4] << 20) | (array[i + 5] << 25); \
_reg_write(addr + j * 4, val); \
} \
} while (0)
enum ISP_RGB_PROB_OUT {
ISP_RGB_PROB_OUT_CFA = 0,
ISP_RGB_PROB_OUT_RGBEE,
ISP_RGB_PROB_OUT_CCM,
ISP_RGB_PROB_OUT_GMA,
ISP_RGB_PROB_OUT_DHZ,
ISP_RGB_PROB_OUT_HSV,
ISP_RGB_PROB_OUT_RGBDITHER,
ISP_RGB_PROB_OUT_CSC,
ISP_RGB_PROB_OUT_MAX,
};
enum ISP_RAW_PATH {
ISP_RAW_PATH_LE = 0,
ISP_RAW_PATH_SE,
ISP_RAW_PATH_MAX,
};
/*
* To indicate the 1st two pixel in the bayer_raw.
*/
enum ISP_BAYER_TYPE {
ISP_BAYER_TYPE_BG = 0,
ISP_BAYER_TYPE_GB,
ISP_BAYER_TYPE_GR,
ISP_BAYER_TYPE_RG,
ISP_BAYER_TYPE_MAX,
};
enum ISP_BNR_OUT {
ISP_BNR_OUT_BYPASS = 0,
ISP_BNR_OUT_B_DELAY,
ISP_BNR_OUT_FACTOR,
ISP_BNR_OUT_B_NL,
ISP_BNR_OUT_RESV_0,
ISP_BNR_OUT_RESV_1,
ISP_BNR_OUT_RESV_2,
ISP_BNR_OUT_RESV_3,
ISP_BNR_OUT_B_OUT,
ISP_BNR_OUT_INTENSITY,
ISP_BNR_OUT_DELTA,
ISP_BNR_OUT_NOT_SM,
ISP_BNR_OUT_FLAG_V,
ISP_BNR_OUT_FLAG_H,
ISP_BNR_OUT_FLAG_D45,
ISP_BNR_OUT_FLAG_D135,
ISP_BNR_OUT_MAX,
};
enum ISP_YNR_OUT {
ISP_YNR_OUT_BYPASS = 0,
ISP_YNR_OUT_Y_DELAY,
ISP_YNR_OUT_FACTOR,
ISP_YNR_OUT_ALPHA,
ISP_YNR_OUT_Y_BF,
ISP_YNR_OUT_Y_NL,
ISP_YNR_OUT_RESV_0,
ISP_YNR_OUT_RESV_1,
ISP_YNR_OUT_Y_OUT,
ISP_YNR_OUT_INTENSITY,
ISP_YNR_OUT_DELTA,
ISP_YNR_OUT_NOT_SM,
ISP_YNR_OUT_FLAG_V,
ISP_YNR_OUT_FLAG_H,
ISP_YNR_OUT_FLAG_D45,
ISP_YNR_OUT_FLAG_D135,
ISP_YNR_OUT_MAX,
};
enum ISP_FS_OUT {
ISP_FS_OUT_FS = 0,
ISP_FS_OUT_LONG,
ISP_FS_OUT_SHORT,
ISP_FS_OUT_SHORT_EX,
ISP_FS_OUT_MOTION_PXL,
ISP_FS_OUT_LE_BLD_WHT,
ISP_FS_OUT_SE_BLD_WHT,
ISP_FS_OUT_MOTION_LUT,
ISP_FS_OUT_AC_FS,
ISP_FS_OUT_DELTA_LE,
ISP_FS_OUT_DELTA_SE,
ISP_FS_OUT_MAX,
};
enum isp_dump_grp {
ISP_DUMP_PRERAW = 0x1,
ISP_DUMP_POSTRAW = 0x2,
ISP_DUMP_ALL = 0x4,
ISP_DUMP_DMA = 0x8,
ISP_DUMP_ALL_DMA = 0x10,
};
enum ISP_CCM_ID {
ISP_CCM_ID_0 = 0,
ISP_CCM_ID_1,
ISP_CCM_ID_2,
ISP_CCM_ID_3,
ISP_CCM_ID_4,
ISP_CCM_ID_MAX,
};
enum ISP_LSCR_ID {
ISP_LSCR_ID_PRE0_FE_LE = 0,
ISP_LSCR_ID_PRE0_FE_SE,
ISP_LSCR_ID_PRE1_FE_LE,
ISP_LSCR_ID_PRE1_FE_SE,
ISP_LSCR_ID_PRE_BE_LE,
ISP_LSCR_ID_PRE_BE_SE,
ISP_LSCR_ID_MAX
};
enum ISP_PRE_PROC_ID {
ISP_IR_PRE_PROC_ID_LE,
ISP_IR_PRE_PROC_ID_SE,
ISP_IR_PRE_PROC_ID_MAX
};
struct lmap_cfg {
u8 pre_chg[2]; //le/se
u8 pre_w_bit;
u8 pre_h_bit;
u8 post_w_bit;
u8 post_h_bit;
};
struct isp_dump_info {
uint64_t phy_base;
uint64_t reg_base;
uint32_t blk_size;
};
struct isp_vblock_info {
uint32_t block_id;
uint32_t block_size;
uint64_t reg_base;
};
struct tile {
u16 start;
u16 end;
};
struct isp_ccm_cfg {
u16 coef[3][3];
};
struct _fe_dbg_i {
uint32_t fe_idle_sts;
uint32_t fe_done_sts;
};
struct _be_dbg_i {
uint32_t be_done_sts;
uint32_t be_dma_idle_sts;
};
struct _post_dbg_i {
uint32_t top_sts;
};
struct _dma_dbg_i {
uint32_t wdma_0_err_sts;
uint32_t wdma_0_idle;
uint32_t wdma_1_err_sts;
uint32_t wdma_1_idle;
uint32_t rdma_err_sts;
uint32_t rdma_idle;
};
struct _isp_dg_info {
struct _fe_dbg_i fe_sts;
struct _be_dbg_i be_sts;
struct _post_dbg_i post_sts;
struct _dma_dbg_i dma_sts;
uint32_t isp_top_sts;
uint32_t bdg_chn_debug[ISP_FE_CHN_MAX];
uint32_t bdg_int_sts_0;
uint32_t bdg_int_sts_1;
uint32_t bdg_fifo_of_cnt;
uint8_t bdg_w_gt_cnt[ISP_FE_CHN_MAX];
uint8_t bdg_w_ls_cnt[ISP_FE_CHN_MAX];
uint8_t bdg_h_gt_cnt[ISP_FE_CHN_MAX];
uint8_t bdg_h_ls_cnt[ISP_FE_CHN_MAX];
};
struct isp_grid_s_info {
u8 w_bit;
u8 h_bit;
};
struct _isp_cfg {
uint32_t csibdg_width;
uint32_t csibdg_height;
uint32_t max_width;
uint32_t max_height;
uint32_t post_img_w;
uint32_t post_img_h;
uint32_t drop_ref_frm_num;
uint32_t drop_frm_cnt;
struct vi_rect crop;
struct vi_rect crop_se;
struct vi_rect postout_crop;
struct _isp_dg_info dg_info;
struct isp_grid_s_info rgbmap_i;
struct isp_grid_s_info lmap_i;
enum ISP_BAYER_TYPE rgb_color_mode;
enum _VI_INTF_MODE_E infMode;
enum _VI_WORK_MODE_E muxMode;
enum _VI_YUV_DATA_SEQ_E enDataSeq;
uint32_t is_patgen_en : 1;
uint32_t is_offline_preraw : 1;
uint32_t is_yuv_bypass_path : 1;
uint32_t is_hdr_on : 1;
uint32_t is_hdr_detail_en : 1;
uint32_t is_tile : 1;
uint32_t is_fbc_on : 1;
uint32_t is_rgbir_sensor : 1;
uint32_t is_offline_scaler : 1;
uint32_t is_stagger_vsync : 1;
uint32_t is_slice_buf_on : 1;
};
/*
* @src_width: width of original image
* @src_height: height of original image
* @img_width: width of image after crop
* @img_height: height of image after crop
* @pyhs_regs: index by enum ISP_BLK_ID_T, always phys reg
* @vreg_bases: index by enum ISP_BLK_ID_T
* @vreg_bases_pa: index by enum ISP_BLK_ID_T
*
* @rgb_color_mode: bayer_raw type after crop could change
*
* @cam_id: preraw(0,1)
* @is_offline_preraw: preraw src offline(from dram)
* @is_offline_postraw: postraw src offline(from dram)
*/
struct isp_ctx {
uint32_t src_width;
uint32_t src_height;
uint32_t img_width;
uint32_t img_height;
uint32_t crop_x;
uint32_t crop_y;
uint32_t crop_se_x;
uint32_t crop_se_y;
uintptr_t *phys_regs;
struct _isp_cfg isp_pipe_cfg[ISP_PRERAW_MAX];
enum ISP_BAYER_TYPE rgb_color_mode[ISP_PRERAW_MAX];
uint8_t rgbmap_prebuf_idx;
uint8_t rawb_chnstr_num;
uint8_t total_chn_num;
uint8_t cam_id;
uint32_t is_dual_sensor : 1;
uint32_t is_yuv_sensor : 1;
uint32_t is_hdr_on : 1;
uint32_t is_3dnr_on : 1;
uint32_t is_dpcm_on : 1;
uint32_t is_offline_be : 1;
uint32_t is_offline_postraw : 1;
uint32_t is_sublvds_path : 1;
uint32_t is_fbc_on : 1;
uint32_t is_ctrl_inited : 1;
uint32_t is_slice_buf_on : 1;
};
struct vi_fbc_cfg {
u8 cu_size;
u8 target_cr; //compression ratio
u8 is_lossless; // lossless or lossy
u32 y_bs_size; //Y WDMA seglen
u32 c_bs_size; //C WDMA seglen
u32 y_buf_size; //total Y buf size
u32 c_buf_size; //total C buf size
};
struct slc_cfg_s {
u32 le_buf_size;
u32 se_buf_size;
u32 le_w_thshd;
u32 se_w_thshd;
u32 le_r_thshd;
u32 se_r_thshd;
};
struct slice_buf_s {
u16 line_delay; //sensor exposure ratio
u16 buffer; //cover for read/write latency, axi latency..etc
u8 max_grid_size; //rgbmap grid size
u8 min_r_thshd; // minimum read threshold
struct slc_cfg_s main_path;
struct slc_cfg_s sub_path;
};
/**********************************************************
* SW scenario path check APIs
**********************************************************/
u32 _is_fe_be_online(struct isp_ctx *ctx);
u32 _is_be_post_online(struct isp_ctx *ctx);
u32 _is_all_online(struct isp_ctx *ctx);
u32 _is_post_sclr_online(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
/****************************************************************************
* Interfaces
****************************************************************************/
uint64_t _mempool_get_addr(void);
int64_t _mempool_pop(uint32_t size);
void vi_set_base_addr(void *base);
uintptr_t *isp_get_phys_reg_bases(void);
void isp_debug_dump(struct isp_ctx *ctx);
/**
* isp_init - setup isp
*
* @param :
*/
void isp_init(struct isp_ctx *ctx);
/**
* isp_reset - do reset. This can be activated only if dma stop to avoid
* hang fabric.
*
*/
void isp_reset(struct isp_ctx *ctx);
/**
* isp_stream_on - start/stop isp stream.
*
* @param on: 1 for stream start, 0 for stream stop
*/
void isp_streaming(struct isp_ctx *ctx, uint32_t on, enum cvi_isp_raw raw_num);
struct isp_grid_s_info ispblk_rgbmap_info(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
struct isp_grid_s_info ispblk_lmap_info(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void ispblk_preraw_fe_config(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void ispblk_preraw_vi_sel_config(struct isp_ctx *ctx);
void ispblk_pre_wdma_ctrl_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_preraw_be_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_raw_rdma_ctrl_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_rawtop_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_rgbtop_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_yuvtop_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_isptop_config(struct isp_ctx *ctx);
void ispblk_crop_enable(struct isp_ctx *ctx, int crop_id, bool en);
int ispblk_crop_config(struct isp_ctx *ctx, int crop_id, struct vi_rect crop);
int ccm_find_hwid(int id);
int blc_find_hwid(int id);
void ispblk_blc_set_offset(struct isp_ctx *ctx, int blc_id,
uint16_t roffset, uint16_t groffset,
uint16_t gboffset, uint16_t boffset);
void ispblk_blc_set_2ndoffset(struct isp_ctx *ctx, int blc_id,
uint16_t roffset, uint16_t groffset,
uint16_t gboffset, uint16_t boffset);
void ispblk_blc_set_gain(struct isp_ctx *ctx, int blc_id,
uint16_t rgain, uint16_t grgain,
uint16_t gbgain, uint16_t bgain);
void ispblk_blc_enable(struct isp_ctx *ctx, int blc_id, bool en, bool bypass);
int wbg_find_hwid(int id);
int ispblk_wbg_config(struct isp_ctx *ctx, int wbg_id, uint16_t rgain, uint16_t ggain, uint16_t bgain);
int ispblk_wbg_enable(struct isp_ctx *ctx, int wbg_id, bool enable, bool bypass);
void ispblk_lscr_set_lut(struct isp_ctx *ctx, int lscr_id, uint16_t *gain_lut, uint8_t lut_count);
void ispblk_lscr_config(struct isp_ctx *ctx, int lscr_id, bool en);
uint64_t ispblk_dma_getaddr(struct isp_ctx *ctx, uint32_t dmaid);
int ispblk_dma_config(struct isp_ctx *ctx, int dmaid, uint64_t buf_addr);
void ispblk_dma_setaddr(struct isp_ctx *ctx, uint32_t dmaid, uint64_t buf_addr);
void ispblk_dma_enable(struct isp_ctx *ctx, uint32_t dmaid, uint32_t on, uint8_t dma_disable);
int ispblk_dma_buf_get_size2(struct isp_ctx *ctx, int dmaid, u8 raw_num);
void ispblk_dma_set_sw_mode(struct isp_ctx *ctx, uint32_t dmaid, bool is_sw_mode);
/****************************************************************************
* PRERAW FE SUBSYS
****************************************************************************/
void ispblk_csidbg_dma_wr_en(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num, const u8 chn_num, const u8 en);
void ispblk_csibdg_wdma_crop_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num, struct vi_rect crop);
void ispblk_csibdg_crop_update(struct isp_ctx *ctx, enum cvi_isp_raw raw_num, bool en);
int ispblk_csibdg_config(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void ispblk_rgbmap_config(struct isp_ctx *ctx, int map_id, bool en, enum cvi_isp_raw raw_num);
void ispblk_lmap_chg_size(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num, const enum cvi_isp_pre_chn_num chn_num);
void ispblk_lmap_config(struct isp_ctx *ctx, int map_id, bool en);
/****************************************************************************
* PRE BE SUBSYS
****************************************************************************/
void ispblk_dpc_config(struct isp_ctx *ctx, enum ISP_RAW_PATH path, bool enable, uint8_t test_case);
void ispblk_dpc_set_static(struct isp_ctx *ctx, enum ISP_RAW_PATH path,
uint16_t offset, uint32_t *bps, uint8_t count);
void ispblk_af_config(struct isp_ctx *ctx, bool enable);
void ispblk_rgbir_preproc_config(struct isp_ctx *ctx,
uint8_t *wdata, int16_t *data_r, int16_t *data_g, int16_t *data_b);
void ispblk_ir_proc_config(struct isp_ctx *ctx, uint8_t *gamma);
/****************************************************************************
* RAW TOP SUBSYS
****************************************************************************/
void ispblk_bnr_config(struct isp_ctx *ctx, enum ISP_BNR_OUT out_sel, bool lsc_en, uint8_t ns_gain, uint8_t str);
void ispblk_cfa_config(struct isp_ctx *ctx);
void ispblk_aehist_reset(struct isp_ctx *ctx, int blk_id, enum cvi_isp_raw raw_num);
void ispblk_aehist_config(struct isp_ctx *ctx, int blk_id, bool enable);
void ispblk_gms_config(struct isp_ctx *ctx, bool enable);
void ispblk_rgbcac_config(struct isp_ctx *ctx, bool en);
void ispblk_lcac_config(struct isp_ctx *ctx, bool en, uint8_t test_case);
/****************************************************************************
* RGB TOP SUBSYS
****************************************************************************/
void ispblk_lsc_config(struct isp_ctx *ctx, bool en);
void ispblk_fusion_hdr_cfg(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void ispblk_fusion_config(struct isp_ctx *ctx, bool enable, bool mc_enable, enum ISP_FS_OUT out_sel);
void ispblk_ltm_d_lut(struct isp_ctx *ctx, uint8_t sel, uint16_t *data);
void ispblk_ltm_b_lut(struct isp_ctx *ctx, uint8_t sel, uint16_t *data);
void ispblk_ltm_g_lut(struct isp_ctx *ctx, uint8_t sel, uint16_t *data);
void ispblk_ltm_config(struct isp_ctx *ctx, u8 ltm_en, u8 dehn_en, u8 behn_en, u8 ee_en);
void ispblk_ccm_config(struct isp_ctx *ctx, enum ISP_BLK_ID_T blk_id, bool en, struct isp_ccm_cfg *cfg);
void ispblk_hist_v_config(struct isp_ctx *ctx, bool en, uint8_t test_case);
void ispblk_dhz_config(struct isp_ctx *ctx, bool en);
void ispblk_ygamma_config(struct isp_ctx *ctx, bool en,
uint8_t sel, uint16_t *data, uint8_t inv, uint8_t test_case);
void ispblk_ygamma_enable(struct isp_ctx *ctx, bool enable);
void ispblk_gamma_config(struct isp_ctx *ctx, bool en, uint8_t sel, uint16_t *data, uint8_t inv);
void ispblk_gamma_enable(struct isp_ctx *ctx, bool enable);
void ispblk_clut_config(struct isp_ctx *ctx, bool en,
int16_t *r_lut, int16_t *g_lut, int16_t *b_lut);
void ispblk_rgbdither_config(struct isp_ctx *ctx, bool en, bool mod_en, bool histidx_en, bool fmnum_en);
void ispblk_csc_config(struct isp_ctx *ctx);
void ispblk_manr_config(struct isp_ctx *ctx, bool en);
void ispblk_ir_merge_config(struct isp_ctx *ctx);
/****************************************************************************
* YUV TOP SUBSYS
****************************************************************************/
int ispblk_pre_ee_config(struct isp_ctx *ctx, bool en);
int ispblk_yuvdither_config(struct isp_ctx *ctx, uint8_t sel, bool en,
bool mod_en, bool histidx_en, bool fmnum_en);
void ispblk_tnr_config(struct isp_ctx *ctx, bool en, u8 test_case);
void ispblk_fbc_clear_fbcd_ring_base(struct isp_ctx *ctx, u8 raw_num);
void ispblk_fbc_chg_to_sw_mode(struct isp_ctx *ctx, u8 raw_num);
void vi_fbc_calculate_size(struct isp_ctx *ctx, u8 raw_num);
void ispblk_fbc_ring_buf_config(struct isp_ctx *ctx, u8 en);
void ispblk_fbcd_config(struct isp_ctx *ctx, bool en);
void ispblk_fbce_config(struct isp_ctx *ctx, bool en);
void ispblk_cnr_config(struct isp_ctx *ctx, bool en, bool pfc_en, uint8_t str_mode, uint8_t test_case);
void ispblk_ynr_config(struct isp_ctx *ctx, enum ISP_YNR_OUT out_sel, uint8_t ns_gain);
int ispblk_ee_config(struct isp_ctx *ctx, bool en);
void ispblk_dci_config(struct isp_ctx *ctx, bool en, uint16_t *lut, uint8_t test_case);
void ispblk_ldci_config(struct isp_ctx *ctx, bool en, uint8_t test_case);
void ispblk_ca_config(struct isp_ctx *ctx, bool en);
void ispblk_ca_lite_config(struct isp_ctx *ctx, bool en);
void ispblk_ycur_config(struct isp_ctx *ctx, bool en, uint8_t sel, uint16_t *data);
void ispblk_ycur_enable(struct isp_ctx *ctx, bool enable, uint8_t sel);
void isp_pre_trig(struct isp_ctx *ctx, enum cvi_isp_raw raw_num, const u8 chn_num);
void isp_post_trig(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void isp_intr_set_mask(struct isp_ctx *ctx);
void isp_intr_status(
struct isp_ctx *ctx,
union REG_ISP_TOP_INT_EVENT0 *s0,
union REG_ISP_TOP_INT_EVENT1 *s1,
union REG_ISP_TOP_INT_EVENT2 *s2);
void isp_csi_intr_status(
struct isp_ctx *ctx,
enum cvi_isp_raw raw_num,
union REG_ISP_CSI_BDG_INTERRUPT_STATUS_0 *s0,
union REG_ISP_CSI_BDG_INTERRUPT_STATUS_1 *s1);
void ispblk_tnr_rgbmap_chg(struct isp_ctx *ctx, enum cvi_isp_raw raw_num, const u8 chn_num);
void ispblk_tnr_post_chg(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
/****************************************************************************
* Runtime Control Flow Config
****************************************************************************/
void isp_first_frm_reset(struct isp_ctx *ctx, uint8_t reset);
void ispblk_post_yuv_cfg_update(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_post_cfg_update(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_pre_be_cfg_update(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
int ispblk_dma_get_size(struct isp_ctx *ctx, int dmaid, uint32_t _w, uint32_t _h);
uint32_t ispblk_csibdg_chn_dbg(struct isp_ctx *ctx, enum cvi_isp_raw raw_num, enum cvi_isp_pre_chn_num chn);
struct _fe_dbg_i ispblk_fe_dbg_info(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
struct _be_dbg_i ispblk_be_dbg_info(struct isp_ctx *ctx);
struct _post_dbg_i ispblk_post_dbg_info(struct isp_ctx *ctx);
struct _dma_dbg_i ispblk_dma_dbg_info(struct isp_ctx *ctx);
int isp_frm_err_handler(struct isp_ctx *ctx, const enum cvi_isp_raw err_raw_num, const u8 step);
/****************************************************************************
* YUV Bypass Control Flow Config
****************************************************************************/
void ispblk_csibdg_yuv_bypass_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
u32 ispblk_dma_yuv_bypass_config(struct isp_ctx *ctx, uint32_t dmaid, uint64_t buf_addr,
const enum cvi_isp_raw raw_num);
/****************************************************************************
* Slice buffer Control
****************************************************************************/
void vi_calculate_slice_buf_setting(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void isp_slice_buf_trig(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void manr_clear_prv_ring_base(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void ispblk_slice_buf_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num, u8 en);
/*******************************************************************************
* Tuning interfaces
******************************************************************************/
void vi_tuning_gamma_ips_update(
struct isp_ctx *ctx,
enum cvi_isp_raw raw_num);
void vi_tuning_dci_update(
struct isp_ctx *ctx,
enum cvi_isp_raw raw_num);
int vi_tuning_buf_setup(void);
void vi_tuning_buf_release(void);
void *vi_get_tuning_buf_addr(u32 *size);
void vi_tuning_buf_clear(void);
#ifdef __cplusplus
}
#endif
#endif /* __VI_DRV_H__ */

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#ifndef __VI_INTER_CMDQ_H__
#define __VI_INTER_CMDQ_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <types.h>
enum VI_EVENT_E {
VI_EV_SOF = 1,
VI_EV_FE_DONE,
VI_EV_BE_DONE,
VI_EV_POST_SHAW_DONE,
VI_EV_POST_DONE,
VI_EV_MAX,
};
enum VI_INTER_CMDQ_E {
VI_CMDQ_EV_TYPE,
VI_CMDQ_MAX,
};
#ifdef __cplusplus
}
#endif
#endif /* __VI_INTER_CMDQ_H__ */

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#ifndef __VI_INTERFACES_H__
#define __VI_INTERFACES_H__
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************
* Common interface for cvi_vi
******************************************************/
int vi_drv_open(struct cvi_vi_ctx *viCtx);
int vi_drv_cfg(void);
int vi_drv_streamon(void);
int vi_drv_streamoff(void);
int vi_drv_release(void);
#ifdef __cplusplus
}
#endif
#endif /* __VI_INTERFACES_H__ */

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#ifndef __U_VI_SNSR_H__
#define __U_VI_SNSR_H__
//#include <linux/cif_uapi.h>
#define MAX_WDR_FRAME_NUM 2
#define ISP_MAX_SNS_REGS 32
struct manual_wdr_attr_s {
unsigned int manual_en;
unsigned short l2s_distance;
unsigned short lsef_length;
unsigned int discard_padding_lines;
unsigned int update;
};
struct manual_wdr_s {
unsigned int devno;
struct manual_wdr_attr_s attr;
};
/**
* struct active_size_s - linear/wdr image information
*
* @width: image total width
* @height: image total height
* @start_x: horizontal shift of the 1st pixel
* @start_y: horizontal shift of the 1st pixel
* @active_w: effective image width
* @active_h: effective image height
* @max_width: max width for buffer allocation
* @max_height: max height for buffer allocation
*/
struct active_size_s {
unsigned short width;
unsigned short height;
unsigned short start_x;
unsigned short start_y;
unsigned short active_w;
unsigned short active_h;
unsigned short max_width;
unsigned short max_height;
};
/**
* struct wdr_size_s - structure for CVI_SNSR_G_WDR_SIZE
*
* @frm_num: [output] Effective image instance. 1 for linear mode, >1 for wdr mode.
* @img_size: [output] Image information.
*/
struct wdr_size_s {
unsigned int frm_num;
struct active_size_s img_size[MAX_WDR_FRAME_NUM];
};
enum isp_sns_type_e {
ISP_SNS_I2C_TYPE = 0,
ISP_SNS_TYPE_BUTT,
};
enum sns_wdr_e {
SNS_WDR_MODE_NONE = 0,
SNS_WDR_MODE_2TO1_LINE,
SNS_WDR_MODE_BUTT
};
/**
* struct isp_i2c_data - sensor setting with i2c interface.
*
* @update: update this register or not
* @drop_frame: drop next frame or not
* @i2c_dev: i2c device number.
* @dev_addr: sensor slave address
* @dly_frm_num: this setting would be set with delay frame number
* @drop_frame_cnt: this setting would be set with drop frame
* @reg_addr: sensor register address
* @addr_bytes: sensor register address bytes number
* @data: sensor register value
* @data_bytes: sensor register value bytes number
*/
struct isp_i2c_data {
unsigned char update;
unsigned char drop_frame;
unsigned char i2c_dev;
unsigned char dev_addr;
unsigned char dly_frm_num;
unsigned short drop_frame_cnt;
unsigned short reg_addr;
unsigned short addr_bytes;
unsigned short data;
unsigned short data_bytes;
};
/**
* struct snsr_regs_s - structure of sensor update wrapper
*
* @sns_type: i2c or other interface
* @regs_num: the maximum sensor registers to be updated
* @i2c_data: sensor registers to be updated
* @use_snsr_sram: does this sensor support group update
* @need_update: global flag for sensor update. Ignore this wrapper
* when it is zero.
*/
struct snsr_regs_s {
enum isp_sns_type_e sns_type;
unsigned int magic_num;
unsigned int regs_num;
struct isp_i2c_data i2c_data[ISP_MAX_SNS_REGS];
unsigned char cfg_valid_max_dly_frm;
unsigned char use_snsr_sram;
unsigned char need_update;
};
/**
* struct snsr_isp_s - structure of isp update wrapper
*
* @wdr: the image information for isp driver.
* @need_update: global flag for isp update. Ignore this wrapper
* when it is zero.
*/
struct snsr_isp_s {
struct wdr_size_s wdr;
unsigned char dly_frm_num;
unsigned char need_update;
};
/**
* struct snsr_cif_s - structure of cif(mipi_rx) update wrapper
*
* @wdr: the image information for isp driver.
* @need_update: global flag for cif update. Ignore this wrapper
* when it is zero.
*/
struct snsr_cif_s {
struct manual_wdr_s wdr_manu;
unsigned char dly_frm_num;
unsigned char need_update;
};
/**
* struct snsr_cfg_node_s - structure of cfg node for runtime update
*
* @snsr: [output] snsr wrapper for runtime update
* @isp: [output] isp wrapper for runtime update
* @cif: [output] cif wrapper for runtime update
* @configed: [intput] after CVI_SNSR_G_CFG_NODE is called, this flag
* is set as false by sensor driver. The caller shall set it as
* true after this cfg_node is passed to isp driver.
*/
struct snsr_cfg_node_s {
struct snsr_regs_s snsr;
struct snsr_isp_s isp;
struct snsr_cif_s cif;
unsigned char configed;
};
#endif // __U_VI_SNSR_H__

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#ifndef _CIF_DRV_H_
#define _CIF_DRV_H_
#define MAX_LINK_NUM 3
#define MAX_HDR_FRAME_NUM 2
#define MAX_VC_NUM 4
#define EXPORT_SYMBOL_GPL(x)
#ifndef _OFST
#define _OFST(_BLK_T, _REG) ((uintptr_t)&(((struct _BLK_T *)0)->_REG))
#endif
#define CIF_RD_REG(_BA, _BLK_T, _REG) \
(_reg_read(_BA+_OFST(_BLK_T, _REG)))
#define CIF_RD_BITS(_BA, _BLK_T, _REG, _FLD) \
({\
typeof(((struct _BLK_T *)0)->_REG) _r;\
_r.raw = _reg_read(_BA+_OFST(_BLK_T, _REG));\
_r.bits._FLD;\
})
#define CIF_WR_REG(_BA, _BLK_T, _REG, _V) \
(_reg_write((_BA+_OFST(_BLK_T, _REG)), _V))
#define CIF_WR_BITS(_BA, _BLK_T, _REG, _FLD, _V) \
do {\
typeof(((struct _BLK_T *)0)->_REG) _r;\
_r.raw = _reg_read(_BA+_OFST(_BLK_T, _REG));\
_r.bits._FLD = _V;\
_reg_write((_BA+_OFST(_BLK_T, _REG)), _r.raw);\
} while (0)
#define CIF_WR_BITS_GRP2(_BA, _BLK_T, _REG, _FLD1, _V1, _FLD2, _V2) \
do {\
typeof(((struct _BLK_T *)0)->_REG) _r;\
_r.raw = _reg_read(_BA+_OFST(_BLK_T, _REG));\
_r.bits._FLD1 = _V1;\
_r.bits._FLD2 = _V2;\
_reg_write((_BA+_OFST(_BLK_T, _REG)), _r.raw);\
} while (0)
#define CIF_WR_BITS_GRP3(_BA, _BLK_T, _REG, _FLD1, _V1, _FLD2, _V2, \
_FLD3, _V3) \
do {\
typeof(((struct _BLK_T *)0)->_REG) _r;\
_r.raw = _reg_read(_BA+_OFST(_BLK_T, _REG));\
_r.bits._FLD1 = _V1;\
_r.bits._FLD2 = _V2;\
_r.bits._FLD3 = _V3;\
_reg_write((_BA+_OFST(_BLK_T, _REG)), _r.raw);\
} while (0)
#define CIF_WO_BITS(_BA, _BLK_T, _REG, _FLD, _V) \
do {\
typeof(((struct _BLK_T *)0)->_REG) _r;\
_r.raw = 0;\
_r.bits._FLD = _V;\
_reg_write((_BA+_OFST(_BLK_T, _REG)), _r.raw);\
} while (0)
#define CIF_INT_STS_ECC_ERR_OFFSET 0U
#define CIF_INT_STS_CRC_ERR_OFFSET 1U
#define CIF_INT_STS_HDR_ERR_OFFSET 2U
#define CIF_INT_STS_WC_ERR_OFFSET 3U
#define CIF_INT_STS_FIFO_FULL_OFFSET 4U
#define CIF_INT_STS_ECC_ERR_MASK (1U<<CIF_INT_STS_ECC_ERR_OFFSET)
#define CIF_INT_STS_CRC_ERR_MASK (1U<<CIF_INT_STS_CRC_ERR_OFFSET)
#define CIF_INT_STS_HDR_ERR_MASK (1U<<CIF_INT_STS_HDR_ERR_OFFSET)
#define CIF_INT_STS_WC_ERR_MASK (1U<<CIF_INT_STS_WC_ERR_OFFSET)
#define CIF_INT_STS_FIFO_FULL_MASK (1U<<CIF_INT_STS_FIFO_FULL_OFFSET)
enum cif_type {
CIF_TYPE_CSI,
CIF_TYPE_SUBLVDS,
CIF_TYPE_HISPI,
CIF_TYPE_TTL,
CIF_TYPE_BT_DMUX,
CIF_TYPE_NUM
};
enum sublvds_fmt {
CIF_SLVDS_8_BIT,
CIF_SLVDS_10_BIT,
CIF_SLVDS_12_BIT
};
enum sublvds_hdr {
CIF_SLVDS_HDR_PAT1,
CIF_SLVDS_HDR_PAT2
};
enum hispi_mode {
CIF_HISPI_MODE_PKT_SP,
CIF_HISPI_MODE_STREAM_SP
};
enum ttl_sensor_fmt {
TTL_SENSOR_8_BIT,
TTL_SENSOR_10_BIT,
TTL_SENSOR_12_BIT,
TTL_SENSOR_16_BIT
};
enum ttl_bt_fmt_out {
TTL_BT_FMT_OUT_CBYCRY,
TTL_BT_FMT_OUT_CRYCBY,
TTL_BT_FMT_OUT_YCBYCR,
TTL_BT_FMT_OUT_YCRYCB,
};
enum ttl_fmt {
TTL_SYNC_PAT_9B_BT656,
TTL_SYNC_PAT_17B_BT1120,
TTL_VHS_11B_BT601,
TTL_VHS_19B_BT601,
TTL_VDE_11B_BT601,
TTL_VDE_19B_BT601,
TTL_VSDE_11B_BT601,
TTL_VSDE_19B_BT601,
TTL_SYNC_PAT_SENSOR = 8,
TTL_VHS_SENSOR = 10,
TTL_VDE_SENSOR = 12,
TTL_VSDE_SENSOR = 14,
TTL_CUSTOM_0,
};
enum csi_fmt {
CSI_YUV422_8B,
CSI_YUV422_10B,
CSI_RAW_8,
CSI_RAW_10,
CSI_RAW_12
};
enum csi_vs_gen_mode {
CSI_VGEN_MODE_FS,
CSI_VGEN_MODE_FE,
CSI_VGEN_MODE_FS_FE
};
enum csi_hdr_mode {
CSI_HDR_MODE_VC,
CSI_HDR_MODE_ID,
CSI_HDR_MODE_DT,
CSI_HDR_MODE_DOL
};
enum cif_endian {
CIF_SLVDS_ENDIAN_MSB,
CIF_SLVDS_ENDIAN_LSB
};
struct sublvds_sync_code {
uint16_t n0_lef_sav;
uint16_t n0_lef_eav;
uint16_t n0_sef_sav;
uint16_t n0_sef_eav;
uint16_t n1_lef_sav;
uint16_t n1_lef_eav;
uint16_t n1_sef_sav;
uint16_t n1_sef_eav;
uint16_t n0_lsef_sav;
uint16_t n0_lsef_eav;
uint16_t n1_lsef_sav;
uint16_t n1_lsef_eav;
};
struct hispi_sync_code {
uint16_t t1_sol;
uint16_t t1_eol;
uint16_t t2_sol;
uint16_t t2_eol;
uint16_t t1_sof;
uint16_t t1_eof;
uint16_t t2_sof;
uint16_t t2_eof;
uint16_t vsync_gen;
};
struct sync_code_s {
uint16_t norm_bk_sav;
uint16_t norm_bk_eav;
uint16_t norm_sav;
uint16_t norm_eav;
uint16_t n0_bk_sav;
uint16_t n0_bk_eav;
uint16_t n1_bk_sav;
uint16_t n1_bk_eav;
union {
struct sublvds_sync_code slvds;
struct hispi_sync_code hispi;
};
};
/*
* @v_front_porch: the line inteval between the last data line and created VSYNC
* @lane_nm: lane number
* @hdr_hblank: the pixel interval between the lef and sef line.
* @h_size: the pixel number of one data line.
* @hdr_mode: SUBLVDS pattern
* @endian: the endian of the raw data.
* @info_line_num: information line num, for hdr pattern 2 only.
* @hdr_v_fp: v_front_porch in hdr mode.
*/
struct param_sublvds {
uint16_t v_front_porch;
uint16_t lane_num;
uint16_t hdr_hblank[2];
uint16_t h_size;
enum sublvds_hdr hdr_mode;
enum cif_endian endian;
enum cif_endian wrap_endian;
enum sublvds_fmt fmt;
uint16_t hdr_v_fp;
struct sync_code_s sync_code;
};
/*
* @lane_nm: lane number
* @h_size: the pixel number of one data line.
* @v_size: the line number of one frame
* @hdr_se_line_shift: the line interval between the le and se readout.
* @mode: HiSPi packetized-SP or streaming-SP
* @endian: the endian of the raw data.
*/
struct param_hispi {
uint16_t lane_num;
uint16_t h_size;
enum hispi_mode mode;
enum cif_endian endian;
enum cif_endian wrap_endian;
enum sublvds_fmt fmt;
struct sync_code_s sync_code;
};
enum mipi_dlane_state_e {
HS_IDLE = 0,
HS_SYNC,
HS_SKEW_CAL,
HS_ALT_CAL,
HS_PREAMPLE,
HS_HST,
HS_ERR,
HS_STATE_NUM
};
enum mipi_deskew_state_e {
DESKEW_IDLE = 0,
DESKEW_START,
DESKEW_DONE,
DESKEW_NUM
};
union mipi_phy_state {
uint32_t raw;
struct {
uint32_t clk_hs_state : 1;
uint32_t clk_ulps_state : 1;
uint32_t clk_stop_state : 1;
uint32_t clk_err_state : 1;
uint32_t p1_clk_hs_state : 1;
uint32_t p1_clk_ulps_state : 1;
uint32_t p1_clk_stop_state : 1;
uint32_t p1_clk_err_state : 1;
uint32_t d0_datahs_state : 3;
uint32_t reserve1 : 1;
uint32_t d1_datahs_state : 3;
uint32_t reserve2 : 1;
uint32_t d2_datahs_state : 3;
uint32_t reserve3 : 1;
uint32_t d3_datahs_state : 3;
uint32_t reserve4 : 1;
uint32_t deskew_state : 2;
uint32_t p1_deskew_state : 2;
uint32_t reserve5 : 4;
} bits;
};
/*
* @fmt: ttl format
*/
enum ttl_vi_mode_e {
VI_RAW = 1,
VI_BT601,
VI_BT656,
VI_BT1120,
};
enum ttl_vi_from_e {
FROM_VI0 = 0,
FROM_VI1,
FROM_VI2,
};
enum ttl_vi_func_e {
VI_FUNC_VS,
VI_FUNC_HS,
VI_FUNC_VDE,
VI_FUNC_HDE,
VI_FUNC_D0,
VI_FUNC_D1,
VI_FUNC_D2,
VI_FUNC_D3,
VI_FUNC_D4,
VI_FUNC_D5,
VI_FUNC_D6,
VI_FUNC_D7,
VI_FUNC_D8,
VI_FUNC_D9,
VI_FUNC_D10,
VI_FUNC_D11,
VI_FUNC_D12,
VI_FUNC_D13,
VI_FUNC_D14,
VI_FUNC_D15,
VI_FUNC_NUM,
};
struct param_ttl {
enum ttl_fmt fmt;
enum ttl_sensor_fmt sensor_fmt;
enum ttl_bt_fmt_out fmt_out;
uint16_t width;
uint16_t height;
uint16_t v_bp;
uint16_t h_bp;
uint32_t clk_inv;
uint32_t vi_sel;
enum ttl_vi_from_e vi_from;
};
/*
* @lane_nm: lane number
* @fmt: ttl format
*/
struct param_csi {
uint16_t lane_num;
enum csi_fmt fmt;
enum csi_vs_gen_mode vs_gen_mode;
enum csi_hdr_mode hdr_mode;
uint16_t data_type[MAX_HDR_FRAME_NUM];
uint16_t decode_type;
uint8_t vc_mapping[MAX_VC_NUM];
};
/*
* @fmt: bt_demux format
*/
#define MAX_BT_DEMUX_NUM 4
enum cif_btdmux_mode_e {
CIF_BTDMUX_DISABLE = 0,
CIF_BTDMUX_2,
CIF_BTDMUX_3,
CIF_BTDMUX_4,
};
struct cif_btdmux_sync_s {
uint8_t sav_vld;
uint8_t sav_blk;
uint8_t eav_vld;
uint8_t eav_blk;
};
struct param_btdemux {
enum ttl_fmt fmt;
enum cif_btdmux_mode_e demux;
uint16_t width;
uint16_t height;
uint16_t v_fp;
uint16_t h_fp;
uint16_t v_bp;
uint16_t h_bp;
uint32_t clk_inv;
uint8_t sync_code_part_A[3];
struct cif_btdmux_sync_s
sync_code_part_B[MAX_BT_DEMUX_NUM];
uint8_t yc_exchg;
};
/*
* @sublvds: config of sublvds
* @hispi: config of hispi
* @ttl: config of ttl
* @csi: config of csi
*/
union cif_cfg {
struct param_sublvds sublvds;
struct param_hispi hispi;
struct param_ttl ttl;
struct param_csi csi;
struct param_btdemux btdemux;
};
/*
* @type: camera interface type
* @cfg: union of interface config
* @hdr_manual: hdr manual mode enable
* @hdr_shfit: line shift between le and se
* @hdr_vsize: vertical size
* @hdr_en: multi frame enable
*/
struct cif_param {
enum cif_type type;
union cif_cfg cfg;
uint32_t hdr_manual;
uint16_t hdr_shift;
uint16_t hdr_vsize;
uint16_t hdr_rm_padding;
uint16_t info_line_num;
uint16_t hdr_en;
};
/*
* @pyhs_regs: index by enum ISP_BLK_ID_T, always phys reg
* @vreg_bases: index by enum ISP_BLK_ID_T
* @vreg_bases_pa: index by enum ISP_BLK_ID_T
*/
struct cif_ctx {
uintptr_t *mac_phys_regs;
uintptr_t *wrap_phys_regs;
struct cif_param *cur_config;
uint16_t mac_num;
};
enum phy_lane_id_e {
CIF_PHY_LANE_0 = 0,
CIF_PHY_LANE_1,
CIF_PHY_LANE_2,
CIF_PHY_LANE_3,
CIF_PHY_LANE_4,
CIF_PHY_LANE_5,
CIF_PHY_LANE_NUM,
};
enum lane_id_e {
CIF_LANE_CLK = 0,
CIF_LANE_0,
CIF_LANE_1,
CIF_LANE_2,
CIF_LANE_3,
CIF_LANE_NUM,
};
enum csi_decode_fmt_e {
DEC_FMT_YUV422_8 = 0,
DEC_FMT_YUV422_10,
DEC_FMT_RAW8,
DEC_FMT_RAW10,
DEC_FMT_RAW12,
DEC_FMT_NUM,
};
enum cif_clk_edge_e {
CIF_CLK_RISING = 0,
CIF_CLK_FALLING,
};
enum cif_clk_dir_e {
CIF_CLK_P02P1 = 0,
CIF_CLK_P12P0,
CIF_CLK_FREERUN,
};
void cif_set_base_addr(uint32_t link, void *mac_base, void *wrap_base);
/**
* cif_init - setup cif
*
* @param :
*/
void cif_init(struct cif_ctx *ctx);
/**
* cif_uninit - clear cif setting
*
* @param :
*/
void cif_uninit(struct cif_ctx *ctx);
/**
* cif_reset - do reset. This can be activated only if dma stop to avoid
* hang fabric.
*
*/
void cif_reset(struct cif_ctx *ctx);
/**
* cif_config - configuration cif.
*
*/
void cif_config(struct cif_ctx *ctx, struct cif_param *param);
uintptr_t *cif_get_mac_phys_reg_bases(uint32_t link);
uintptr_t *cif_get_wrap_phys_reg_bases(uint32_t link);
void cif_set_lane_id(struct cif_ctx *ctx, enum lane_id_e lane,
uint32_t select, uint32_t pn_swap);
void cif_hdr_enable(struct cif_ctx *ctx, struct cif_param *param, uint32_t on);
void cif_streaming(struct cif_ctx *ctx, uint32_t on, uint32_t hdr);
void cif_hdr_manual_config(struct cif_ctx *ctx,
struct cif_param *param,
uint32_t sw_up);
void cif_crop_info_line(struct cif_ctx *ctx, uint32_t line_num, uint32_t sw_up);
void cif_set_clk_edge(struct cif_ctx *ctx,
enum phy_lane_id_e lane, enum cif_clk_edge_e edge);
void cif_set_lvds_endian(struct cif_ctx *ctx,
enum cif_endian mac, enum cif_endian wrap);
void cif_set_lane_deskew(struct cif_ctx *ctx,
enum phy_lane_id_e lane, uint8_t phase);
uint8_t cif_get_lane_data(struct cif_ctx *ctx, enum phy_lane_id_e lane);
void cif_set_lvds_vsync_gen(struct cif_ctx *ctx, uint32_t fp);
int cif_check_csi_int_sts(struct cif_ctx *ctx, uint32_t mask);
void cif_mask_csi_int_sts(struct cif_ctx *ctx, uint32_t mask);
void cif_unmask_csi_int_sts(struct cif_ctx *ctx, uint32_t mask);
void cif_clear_csi_int_sts(struct cif_ctx *ctx);
int cif_check_csi_fifo_full(struct cif_ctx *ctx);
int cif_check_lvds_fifo_full(struct cif_ctx *ctx);
int cif_get_csi_decode_fmt(struct cif_ctx *ctx);
int cif_get_csi_phy_state(struct cif_ctx *ctx, union mipi_phy_state *state);
void cif_set_hs_settle(struct cif_ctx *ctx, uint8_t hs_settle);
void cif_set_bt_fmt_out(struct cif_ctx *ctx, enum ttl_bt_fmt_out fmt_out);
void cif_set_clk_dir(struct cif_ctx *ctx, enum cif_clk_dir_e dir);
void cif_set_ttl_pinmux(struct cif_ctx *ctx,
enum ttl_vi_from_e vi, enum ttl_vi_func_e func, uint32_t pad);
#endif // _CIF_DRV_H_

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#ifndef _CIF_REG_H_
#define _CIF_REG_H_
#include "mmio.h"
#include "reg_fields_csi_mac.h"
#include "reg_fields_csi_wrap.h"
#include "reg_blocks_csi_mac.h"
#include "reg_blocks_csi_wrap.h"
// #define CIF_MAC0_TOP_PHY_REG_BASE (0x0A0C2000)
// #define CIF_MAC1_TOP_PHY_REG_BASE (0x0A0C4000)
// #define CIF_MAC2_TOP_PHY_REG_BASE (0x0A0C6000)
// #define CIF_WRAP_TOP_PHY_REG_BASE (0x0A0D0000)
// #define CIF_WRAP_TOP_PHY4L_REG_BASE (0x0A0D3000)
// #define CIF_WRAP_TOP_PHY2L_REG_BASE (0x0A0D0000)
#define DRAM_PHY_BASE (0x100000000)
#define CIF_BLK_REGS_BITW (9)
#define CIF_BLK_ID_BITW (4)
#define MAP_CIF_BLOCK_ID(_ba) (((_ba) >> CIF_BLK_REGS_BITW) \
& ((1 << CIF_BLK_ID_BITW) - 1))
/* CIF REG FIELD DEFINE */
/* CIF CSI MAC BLOCK ADDR OFFSET DEFINE */
#define CIF_MAC_BLK_BA_TOP (0x00000000) //sensor mac
#define CIF_MAC_BLK_BA_SLVDS (0x00000200) //subLVDS
#define CIF_MAC_BLK_BA_CSI (0x00000400) //csi_ctrl_top
enum CIF_MAC_BLK_ID_T {
CIF_MAC_BLK_ID_TOP = MAP_CIF_BLOCK_ID(CIF_MAC_BLK_BA_TOP),
CIF_MAC_BLK_ID_SLVDS = MAP_CIF_BLOCK_ID(CIF_MAC_BLK_BA_SLVDS),
CIF_MAC_BLK_ID_CSI = MAP_CIF_BLOCK_ID(CIF_MAC_BLK_BA_CSI),
CIF_MAC_BLK_ID_MAX
};
/* CIF CSI WRAP BLOCK ADDR OFFSET DEFINE */
#define CIF_WRAP_BLK_BA_TOP (0x00000000)
#define CIF_WRAP_BLK_BA_4L (0x00000300)
#define CIF_WRAP_BLK_BA_2L (0x00000600)
enum CIF_WRAP_BLK_ID_T {
CIF_WRAP_BLK_ID_TOP = MAP_CIF_BLOCK_ID(CIF_WRAP_BLK_BA_TOP),
CIF_WRAP_BLK_ID_4L = MAP_CIF_BLOCK_ID(CIF_WRAP_BLK_BA_4L),
CIF_WRAP_BLK_ID_2L = MAP_CIF_BLOCK_ID(CIF_WRAP_BLK_BA_2L),
CIF_WRAP_BLK_ID_MAX
};
#endif //_CIF_REG_H_

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#ifndef _REG_BLOCKS_CSI_MAC_H_
#define _REG_BLOCKS_CSI_MAC_H_
/******************************************/
/* Module Definition */
/******************************************/
struct REG_SENSOR_MAC_T {
union REG_SENSOR_MAC_00 REG_00;
uint32_t _resv_0x4[3];
union REG_SENSOR_MAC_10 REG_10;
union REG_SENSOR_MAC_14 REG_14;
union REG_SENSOR_MAC_18 REG_18;
union REG_SENSOR_MAC_1C REG_1C;
union REG_SENSOR_MAC_20 REG_20;
union REG_SENSOR_MAC_24 REG_24;
union REG_SENSOR_MAC_28 REG_28;
uint32_t _resv_0x2c[1];
union REG_SENSOR_MAC_30 REG_30;
union REG_SENSOR_MAC_34 REG_34;
uint32_t _resv_0x38[2];
union REG_SENSOR_MAC_40 REG_40;
union REG_SENSOR_MAC_44 REG_44;
union REG_SENSOR_MAC_48 REG_48;
union REG_SENSOR_MAC_4C REG_4C;
union REG_SENSOR_MAC_50 REG_50;
union REG_SENSOR_MAC_54 REG_54;
union REG_SENSOR_MAC_58 REG_58;
uint32_t _resv_0x5c[1];
union REG_SENSOR_MAC_60 REG_60;
union REG_SENSOR_MAC_64 REG_64;
union REG_SENSOR_MAC_68 REG_68;
union REG_SENSOR_MAC_6C REG_6C;
union REG_SENSOR_MAC_70 REG_70;
union REG_SENSOR_MAC_74 REG_74;
uint32_t _resv_0x78[2];
union REG_SENSOR_MAC_80 REG_80;
union REG_SENSOR_MAC_84 REG_84;
union REG_SENSOR_MAC_88 REG_88;
union REG_SENSOR_MAC_8C REG_8C;
union REG_SENSOR_MAC_90 REG_90;
union REG_SENSOR_MAC_94 REG_94;
union REG_SENSOR_MAC_98 REG_98;
union REG_SENSOR_MAC_9C REG_9C;
union REG_SENSOR_MAC_A0 REG_A0;
union REG_SENSOR_MAC_A4 REG_A4;
union REG_SENSOR_MAC_A8 REG_A8;
uint32_t _resv_0xac[1];
union REG_SENSOR_MAC_B0 REG_B0;
union REG_SENSOR_MAC_B4 REG_B4;
union REG_SENSOR_MAC_B8 REG_B8;
union REG_SENSOR_MAC_BC REG_BC;
union REG_SENSOR_MAC_C0 REG_C0;
union REG_SENSOR_MAC_C4 REG_C4;
union REG_SENSOR_MAC_C8 REG_C8;
};
/******************************************/
/* Module Definition */
/******************************************/
struct REG_SUBLVDS_CTRL_TOP_T {
union REG_SUBLVDS_CTRL_TOP_00 REG_00;
union REG_SUBLVDS_CTRL_TOP_04 REG_04;
union REG_SUBLVDS_CTRL_TOP_08 REG_08;
union REG_SUBLVDS_CTRL_TOP_0C REG_0C;
union REG_SUBLVDS_CTRL_TOP_10 REG_10;
union REG_SUBLVDS_CTRL_TOP_14 REG_14;
union REG_SUBLVDS_CTRL_TOP_18 REG_18;
union REG_SUBLVDS_CTRL_TOP_1C REG_1C;
union REG_SUBLVDS_CTRL_TOP_20 REG_20;
union REG_SUBLVDS_CTRL_TOP_24 REG_24;
union REG_SUBLVDS_CTRL_TOP_28 REG_28;
union REG_SUBLVDS_CTRL_TOP_2C REG_2C;
union REG_SUBLVDS_CTRL_TOP_30 REG_30;
uint32_t _resv_0x34[3];
union REG_SUBLVDS_CTRL_TOP_40 REG_40;
uint32_t _resv_0x44[3];
union REG_SUBLVDS_CTRL_TOP_50 REG_50;
union REG_SUBLVDS_CTRL_TOP_54 REG_54;
union REG_SUBLVDS_CTRL_TOP_58 REG_58;
uint32_t _resv_0x5c[1];
union REG_SUBLVDS_CTRL_TOP_60 REG_60;
union REG_SUBLVDS_CTRL_TOP_64 REG_64;
union REG_SUBLVDS_CTRL_TOP_68 REG_68;
union REG_SUBLVDS_CTRL_TOP_6C REG_6C;
union REG_SUBLVDS_CTRL_TOP_70 REG_70;
union REG_SUBLVDS_CTRL_TOP_74 REG_74;
uint32_t _resv_0x78[2];
union REG_SUBLVDS_CTRL_TOP_80 REG_80;
};
/******************************************/
/* Module Definition */
/******************************************/
struct REG_CSI_CTRL_TOP_T {
union REG_CSI_CTRL_TOP_00 REG_00;
union REG_CSI_CTRL_TOP_04 REG_04;
union REG_CSI_CTRL_TOP_08 REG_08;
union REG_CSI_CTRL_TOP_0C REG_0C;
union REG_CSI_CTRL_TOP_10 REG_10;
union REG_CSI_CTRL_TOP_14 REG_14;
union REG_CSI_CTRL_TOP_18 REG_18;
union REG_CSI_CTRL_TOP_1C REG_1C;
union REG_CSI_CTRL_TOP_20 REG_20;
union REG_CSI_CTRL_TOP_24 REG_24;
uint32_t _resv_0x28[2];
union REG_CSI_CTRL_TOP_30 REG_30;
union REG_CSI_CTRL_TOP_34 REG_34;
uint32_t _resv_0x38[2];
union REG_CSI_CTRL_TOP_40 REG_40;
uint32_t _resv_0x44[1];
union REG_CSI_CTRL_TOP_48 REG_48;
union REG_CSI_CTRL_TOP_4C REG_4C;
union REG_CSI_CTRL_TOP_50 REG_50;
union REG_CSI_CTRL_TOP_54 REG_54;
union REG_CSI_CTRL_TOP_58 REG_58;
union REG_CSI_CTRL_TOP_5C REG_5C;
union REG_CSI_CTRL_TOP_60 REG_60;
union REG_CSI_CTRL_TOP_64 REG_64;
uint32_t _resv_0x68[2];
union REG_CSI_CTRL_TOP_70 REG_70;
union REG_CSI_CTRL_TOP_74 REG_74;
};
/******************************************/
/* Module Definition */
/******************************************/
struct REG_SENSOR_MAC_VI_T {
union REG_SENSOR_MAC_VI_00 REG_00;
uint32_t _resv_0x4[3];
union REG_SENSOR_MAC_VI_10 REG_10;
union REG_SENSOR_MAC_VI_14 REG_14;
union REG_SENSOR_MAC_VI_18 REG_18;
union REG_SENSOR_MAC_VI_1C REG_1C;
union REG_SENSOR_MAC_VI_20 REG_20;
union REG_SENSOR_MAC_VI_24 REG_24;
union REG_SENSOR_MAC_VI_28 REG_28;
uint32_t _resv_0x2c[1];
union REG_SENSOR_MAC_VI_30 REG_30;
union REG_SENSOR_MAC_VI_34 REG_34;
uint32_t _resv_0x38[2];
union REG_SENSOR_MAC_VI_40 REG_40;
union REG_SENSOR_MAC_VI_44 REG_44;
union REG_SENSOR_MAC_VI_48 REG_48;
union REG_SENSOR_MAC_VI_4C REG_4C;
uint32_t _resv_0x50[4];
union REG_SENSOR_MAC_VI_60 REG_60;
union REG_SENSOR_MAC_VI_64 REG_64;
union REG_SENSOR_MAC_VI_68 REG_68;
union REG_SENSOR_MAC_VI_6C REG_6C;
union REG_SENSOR_MAC_VI_70 REG_70;
union REG_SENSOR_MAC_VI_74 REG_74;
uint32_t _resv_0x78[2];
union REG_SENSOR_MAC_VI_80 REG_80;
union REG_SENSOR_MAC_VI_84 REG_84;
union REG_SENSOR_MAC_VI_88 REG_88;
union REG_SENSOR_MAC_VI_8C REG_8C;
union REG_SENSOR_MAC_VI_90 REG_90;
union REG_SENSOR_MAC_VI_94 REG_94;
union REG_SENSOR_MAC_VI_98 REG_98;
union REG_SENSOR_MAC_VI_9C REG_9C;
union REG_SENSOR_MAC_VI_A0 REG_A0;
union REG_SENSOR_MAC_VI_A4 REG_A4;
union REG_SENSOR_MAC_VI_A8 REG_A8;
uint32_t _resv_0xac[1];
union REG_SENSOR_MAC_VI_B0 REG_B0;
union REG_SENSOR_MAC_VI_B4 REG_B4;
union REG_SENSOR_MAC_VI_B8 REG_B8;
union REG_SENSOR_MAC_VI_BC REG_BC;
union REG_SENSOR_MAC_VI_C0 REG_C0;
union REG_SENSOR_MAC_VI_C4 REG_C4;
union REG_SENSOR_MAC_VI_C8 REG_C8;
};
#endif // _REG_BLOCKS_CSI_MAC_H_

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#ifndef _REG_BLOCKS_CSI_WRAP_H_
#define _REG_BLOCKS_CSI_WRAP_H_
/******************************************/
/* Module Definition */
/******************************************/
struct REG_SENSOR_PHY_2L_T {
union REG_SENSOR_PHY_2L_00 REG_00;
union REG_SENSOR_PHY_2L_04 REG_04;
union REG_SENSOR_PHY_2L_08 REG_08;
union REG_SENSOR_PHY_2L_0C REG_0C;
union REG_SENSOR_PHY_2L_10 REG_10;
uint32_t _resv_0x14[3];
union REG_SENSOR_PHY_2L_20 REG_20;
union REG_SENSOR_PHY_2L_24 REG_24;
union REG_SENSOR_PHY_2L_28 REG_28;
uint32_t _resv_0x2c[1];
union REG_SENSOR_PHY_2L_30 REG_30;
union REG_SENSOR_PHY_2L_34 REG_34;
union REG_SENSOR_PHY_2L_38 REG_38;
union REG_SENSOR_PHY_2L_3C REG_3C;
union REG_SENSOR_PHY_2L_40 REG_40;
union REG_SENSOR_PHY_2L_44 REG_44;
union REG_SENSOR_PHY_2L_48 REG_48;
union REG_SENSOR_PHY_2L_4C REG_4C;
union REG_SENSOR_PHY_2L_50 REG_50;
union REG_SENSOR_PHY_2L_54 REG_54;
uint32_t _resv_0x58[14];
union REG_SENSOR_PHY_2L_DBG_90 DBG_90;
union REG_SENSOR_PHY_2L_DBG_94 DBG_94;
union REG_SENSOR_PHY_2L_STATUS_98 STATUS_98;
union REG_SENSOR_PHY_2L_STATUS_9C STATUS_9C;
uint32_t _resv_0xa0[24];
union REG_SENSOR_PHY_2L_D0_0 D0_0;
union REG_SENSOR_PHY_2L_D0_1 D0_1;
union REG_SENSOR_PHY_2L_D0_2 D0_2;
union REG_SENSOR_PHY_2L_D0_3 D0_3;
union REG_SENSOR_PHY_2L_D0_4 D0_4;
union REG_SENSOR_PHY_2L_D0_5 D0_5;
union REG_SENSOR_PHY_2L_D0_6 D0_6;
union REG_SENSOR_PHY_2L_D0_7 D0_7;
union REG_SENSOR_PHY_2L_D0_8 D0_8;
union REG_SENSOR_PHY_2L_D0_9 D0_9;
union REG_SENSOR_PHY_2L_D0_A D0_A;
union REG_SENSOR_PHY_2L_D0_B D0_B;
uint32_t _resv_0x130[4];
union REG_SENSOR_PHY_2L_D1_0 D1_0;
union REG_SENSOR_PHY_2L_D1_1 D1_1;
union REG_SENSOR_PHY_2L_D1_2 D1_2;
union REG_SENSOR_PHY_2L_D1_3 D1_3;
union REG_SENSOR_PHY_2L_D1_4 D1_4;
union REG_SENSOR_PHY_2L_D1_5 D1_5;
union REG_SENSOR_PHY_2L_D1_6 D1_6;
union REG_SENSOR_PHY_2L_D1_7 D1_7;
union REG_SENSOR_PHY_2L_D1_8 D1_8;
union REG_SENSOR_PHY_2L_D1_9 D1_9;
union REG_SENSOR_PHY_2L_D1_A D1_A;
union REG_SENSOR_PHY_2L_D1_B D1_B;
};
/******************************************/
/* Module Definition */
/******************************************/
struct REG_SENSOR_PHY_4L_T {
union REG_SENSOR_PHY_4L_00 REG_00;
union REG_SENSOR_PHY_4L_04 REG_04;
union REG_SENSOR_PHY_4L_08 REG_08;
union REG_SENSOR_PHY_4L_0C REG_0C;
union REG_SENSOR_PHY_4L_10 REG_10;
uint32_t _resv_0x14[3];
union REG_SENSOR_PHY_4L_20 REG_20;
union REG_SENSOR_PHY_4L_24 REG_24;
union REG_SENSOR_PHY_4L_28 REG_28;
uint32_t _resv_0x2c[1];
union REG_SENSOR_PHY_4L_30 REG_30;
union REG_SENSOR_PHY_4L_34 REG_34;
union REG_SENSOR_PHY_4L_38 REG_38;
union REG_SENSOR_PHY_4L_3C REG_3C;
union REG_SENSOR_PHY_4L_40 REG_40;
union REG_SENSOR_PHY_4L_44 REG_44;
union REG_SENSOR_PHY_4L_48 REG_48;
union REG_SENSOR_PHY_4L_4C REG_4C;
union REG_SENSOR_PHY_4L_50 REG_50;
union REG_SENSOR_PHY_4L_54 REG_54;
union REG_SENSOR_PHY_4L_58 REG_58;
union REG_SENSOR_PHY_4L_5C REG_5C;
union REG_SENSOR_PHY_4L_60 REG_60;
union REG_SENSOR_PHY_4L_64 REG_64;
uint32_t _resv_0x68[10];
union REG_SENSOR_PHY_4L_DBG_90 DBG_90;
union REG_SENSOR_PHY_4L_DBG_94 DBG_94;
union REG_SENSOR_PHY_4L_STATUS_98 STATUS_98;
union REG_SENSOR_PHY_4L_STATUS_9C STATUS_9C;
uint32_t _resv_0xa0[1];
union REG_SENSOR_PHY_4L_STATUS_A4 STATUS_A4;
union REG_SENSOR_PHY_4L_STATUS_A8 STATUS_A8;
uint32_t _resv_0xac[21];
union REG_SENSOR_PHY_4L_D0_0 D0_0;
union REG_SENSOR_PHY_4L_D0_1 D0_1;
union REG_SENSOR_PHY_4L_D0_2 D0_2;
union REG_SENSOR_PHY_4L_D0_3 D0_3;
union REG_SENSOR_PHY_4L_D0_4 D0_4;
union REG_SENSOR_PHY_4L_D0_5 D0_5;
union REG_SENSOR_PHY_4L_D0_6 D0_6;
union REG_SENSOR_PHY_4L_D0_7 D0_7;
union REG_SENSOR_PHY_4L_D0_8 D0_8;
union REG_SENSOR_PHY_4L_D0_9 D0_9;
union REG_SENSOR_PHY_4L_D0_A D0_A;
union REG_SENSOR_PHY_4L_D0_B D0_B;
uint32_t _resv_0x130[4];
union REG_SENSOR_PHY_4L_D1_0 D1_0;
union REG_SENSOR_PHY_4L_D1_1 D1_1;
union REG_SENSOR_PHY_4L_D1_2 D1_2;
union REG_SENSOR_PHY_4L_D1_3 D1_3;
union REG_SENSOR_PHY_4L_D1_4 D1_4;
union REG_SENSOR_PHY_4L_D1_5 D1_5;
union REG_SENSOR_PHY_4L_D1_6 D1_6;
union REG_SENSOR_PHY_4L_D1_7 D1_7;
union REG_SENSOR_PHY_4L_D1_8 D1_8;
union REG_SENSOR_PHY_4L_D1_9 D1_9;
union REG_SENSOR_PHY_4L_D1_A D1_A;
union REG_SENSOR_PHY_4L_D1_B D1_B;
uint32_t _resv_0x170[4];
union REG_SENSOR_PHY_4L_D2_0 D2_0;
union REG_SENSOR_PHY_4L_D2_1 D2_1;
union REG_SENSOR_PHY_4L_D2_2 D2_2;
union REG_SENSOR_PHY_4L_D2_3 D2_3;
union REG_SENSOR_PHY_4L_D2_4 D2_4;
union REG_SENSOR_PHY_4L_D2_5 D2_5;
union REG_SENSOR_PHY_4L_D2_6 D2_6;
union REG_SENSOR_PHY_4L_D2_7 D2_7;
union REG_SENSOR_PHY_4L_D2_8 D2_8;
union REG_SENSOR_PHY_4L_D2_9 D2_9;
union REG_SENSOR_PHY_4L_D2_A D2_A;
union REG_SENSOR_PHY_4L_D2_B D2_B;
uint32_t _resv_0x1b0[4];
union REG_SENSOR_PHY_4L_D3_0 D3_0;
union REG_SENSOR_PHY_4L_D3_1 D3_1;
union REG_SENSOR_PHY_4L_D3_2 D3_2;
union REG_SENSOR_PHY_4L_D3_3 D3_3;
union REG_SENSOR_PHY_4L_D3_4 D3_4;
union REG_SENSOR_PHY_4L_D3_5 D3_5;
union REG_SENSOR_PHY_4L_D3_6 D3_6;
union REG_SENSOR_PHY_4L_D3_7 D3_7;
union REG_SENSOR_PHY_4L_D3_8 D3_8;
union REG_SENSOR_PHY_4L_D3_9 D3_9;
union REG_SENSOR_PHY_4L_D3_A D3_A;
union REG_SENSOR_PHY_4L_D3_B D3_B;
};
/******************************************/
/* Module Definition */
/******************************************/
struct REG_SENSOR_PHY_TOP_T {
union REG_SENSOR_PHY_TOP_00 REG_00;
union REG_SENSOR_PHY_TOP_04 REG_04;
union REG_SENSOR_PHY_TOP_08 REG_08;
union REG_SENSOR_PHY_TOP_0C REG_0C;
union REG_SENSOR_PHY_TOP_10 REG_10;
uint32_t _resv_0x14[3];
union REG_SENSOR_PHY_TOP_20 REG_20;
union REG_SENSOR_PHY_TOP_24 REG_24;
uint32_t _resv_0x28[1];
union REG_SENSOR_PHY_TOP_2C REG_2C;
union REG_SENSOR_PHY_TOP_30 REG_30;
union REG_SENSOR_PHY_TOP_34 REG_34;
union REG_SENSOR_PHY_TOP_38 REG_38;
union REG_SENSOR_PHY_TOP_3C REG_3C;
union REG_SENSOR_PHY_TOP_40 REG_40;
union REG_SENSOR_PHY_TOP_44 REG_44;
union REG_SENSOR_PHY_TOP_48 REG_48;
uint32_t _resv_0x4c[9];
union REG_SENSOR_PHY_TOP_70 REG_70;
union REG_SENSOR_PHY_TOP_74 REG_74;
uint32_t _resv_0x78[1];
union REG_SENSOR_PHY_TOP_7C REG_7C;
union REG_SENSOR_PHY_TOP_80 REG_80;
union REG_SENSOR_PHY_TOP_84 REG_84;
union REG_SENSOR_PHY_TOP_88 REG_88;
uint32_t _resv_0x8c[1];
union REG_SENSOR_PHY_TOP_90 REG_90;
union REG_SENSOR_PHY_TOP_94 REG_94;
uint32_t _resv_0x98[2];
union REG_SENSOR_PHY_TOP_A0 REG_A0;
union REG_SENSOR_PHY_TOP_A4 REG_A4;
union REG_SENSOR_PHY_TOP_A8 REG_A8;
union REG_SENSOR_PHY_TOP_AC REG_AC;
uint32_t _resv_0xb0[20];
union REG_SENSOR_PHY_TOP_DFT_100 DFT_100;
union REG_SENSOR_PHY_TOP_DFT_104 DFT_104;
union REG_SENSOR_PHY_TOP_DFT_108 DFT_108;
union REG_SENSOR_PHY_TOP_DFT_10C DFT_10C;
union REG_SENSOR_PHY_TOP_DFT_110 DFT_110;
union REG_SENSOR_PHY_TOP_DFT_114 DFT_114;
uint32_t _resv_0x118[1];
union REG_SENSOR_PHY_TOP_DFT_11C DFT_11C;
union REG_SENSOR_PHY_TOP_DBG_12 DBG_12;
uint32_t _resv_0x124[55];
union REG_SENSOR_PHY_TOP_TEST_0 TEST_0;
union REG_SENSOR_PHY_TOP_TEST_1 TEST_1;
union REG_SENSOR_PHY_TOP_TEST_2 TEST_2;
union REG_SENSOR_PHY_TOP_TEST_3 TEST_3;
union REG_SENSOR_PHY_TOP_TEST_4 TEST_4;
union REG_SENSOR_PHY_TOP_TEST_5 TEST_5;
union REG_SENSOR_PHY_TOP_TEST_6 TEST_6;
union REG_SENSOR_PHY_TOP_TEST_7 TEST_7;
union REG_SENSOR_PHY_TOP_TEST_8 TEST_8;
union REG_SENSOR_PHY_TOP_TEST_9 TEST_9;
union REG_SENSOR_PHY_TOP_TEST_A TEST_A;
union REG_SENSOR_PHY_TOP_TEST_B TEST_B;
uint32_t _resv_0x230[12];
union REG_SENSOR_PHY_TOP_DUMMY_D0 DUMMY_D0;
union REG_SENSOR_PHY_TOP_DUMMY_D1 DUMMY_D1;
union REG_SENSOR_PHY_TOP_DUMMY_D2 DUMMY_D2;
union REG_SENSOR_PHY_TOP_DUMMY_D3 DUMMY_D3;
union REG_SENSOR_PHY_TOP_DUMMY_D4 DUMMY_D4;
union REG_SENSOR_PHY_TOP_DUMMY_D5 DUMMY_D5;
union REG_SENSOR_PHY_TOP_DUMMY_D6 DUMMY_D6;
union REG_SENSOR_PHY_TOP_DUMMY_D7 DUMMY_D7;
};
#endif // _REG_BLOCKS_CSI_WRAP_H_

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freertos/cvitek/install/include/hal/cif/reg_fields_csi_mac.h Normal file
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1686
freertos/cvitek/install/include/hal/cif/reg_fields_csi_wrap.h Normal file
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freertos/cvitek/install/include/hal/config/cv180x_pinlist_swconfig.h Normal file
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//##==============================================================================
//##=== This script is generate by genswconfig.pl from .\00_Phobos_Pinlist_20220315.xls
//##=== Generate Time stamp is : 2022-03-17 14:04:49
//##==============================================================================
#ifndef __CV180X_PINLIST_SWCONFIG_H__
#define __CV180X_PINLIST_SWCONFIG_H__
#define SD0_CLK__SDIO0_CLK 0
#define SD0_CLK__IIC1_SDA 1
#define SD0_CLK__SPI0_SCK 2
#define SD0_CLK__XGPIOA_7 3
#define SD0_CLK__PWM_15 5
#define SD0_CLK__EPHY_LNK_LED 6
#define SD0_CLK__DBG_0 7
#define SD0_CMD__SDIO0_CMD 0
#define SD0_CMD__IIC1_SCL 1
#define SD0_CMD__SPI0_SDO 2
#define SD0_CMD__XGPIOA_8 3
#define SD0_CMD__PWM_14 5
#define SD0_CMD__EPHY_SPD_LED 6
#define SD0_CMD__DBG_1 7
#define SD0_D0__SDIO0_D_0 0
#define SD0_D0__CAM_MCLK1 1
#define SD0_D0__SPI0_SDI 2
#define SD0_D0__XGPIOA_9 3
#define SD0_D0__UART3_TX 4
#define SD0_D0__PWM_13 5
#define SD0_D0__WG0_D0 6
#define SD0_D0__DBG_2 7
#define SD0_D1__SDIO0_D_1 0
#define SD0_D1__IIC1_SDA 1
#define SD0_D1__AUX0 2
#define SD0_D1__XGPIOA_10 3
#define SD0_D1__UART1_TX 4
#define SD0_D1__PWM_12 5
#define SD0_D1__WG0_D1 6
#define SD0_D1__DBG_3 7
#define SD0_D2__SDIO0_D_2 0
#define SD0_D2__IIC1_SCL 1
#define SD0_D2__AUX1 2
#define SD0_D2__XGPIOA_11 3
#define SD0_D2__UART1_RX 4
#define SD0_D2__PWM_11 5
#define SD0_D2__WG1_D0 6
#define SD0_D2__DBG_4 7
#define SD0_D3__SDIO0_D_3 0
#define SD0_D3__CAM_MCLK0 1
#define SD0_D3__SPI0_CS_X 2
#define SD0_D3__XGPIOA_12 3
#define SD0_D3__UART3_RX 4
#define SD0_D3__PWM_10 5
#define SD0_D3__WG1_D1 6
#define SD0_D3__DBG_5 7
#define SD0_CD__SDIO0_CD 0
#define SD0_CD__XGPIOA_13 3
#define SD0_PWR_EN__SDIO0_PWR_EN 0
#define SD0_PWR_EN__XGPIOA_14 3
#define SPK_EN__XGPIOA_15 3
#define UART0_TX__UART0_TX 0
#define UART0_TX__CAM_MCLK1 1
#define UART0_TX__PWM_4 2
#define UART0_TX__XGPIOA_16 3
#define UART0_TX__UART1_TX 4
#define UART0_TX__AUX1 5
#define UART0_TX__JTAG_TMS 6
#define UART0_TX__DBG_6 7
#define UART0_RX__UART0_RX 0
#define UART0_RX__CAM_MCLK0 1
#define UART0_RX__PWM_5 2
#define UART0_RX__XGPIOA_17 3
#define UART0_RX__UART1_RX 4
#define UART0_RX__AUX0 5
#define UART0_RX__JTAG_TCK 6
#define UART0_RX__DBG_7 7
#define SPINOR_HOLD_X__SPINOR_HOLD_X 1
#define SPINOR_HOLD_X__SPINAND_HOLD 2
#define SPINOR_HOLD_X__XGPIOA_26 3
#define SPINOR_SCK__SPINOR_SCK 1
#define SPINOR_SCK__SPINAND_CLK 2
#define SPINOR_SCK__XGPIOA_22 3
#define SPINOR_MOSI__SPINOR_MOSI 1
#define SPINOR_MOSI__SPINAND_MOSI 2
#define SPINOR_MOSI__XGPIOA_25 3
#define SPINOR_WP_X__SPINOR_WP_X 1
#define SPINOR_WP_X__SPINAND_WP 2
#define SPINOR_WP_X__XGPIOA_27 3
#define SPINOR_MISO__SPINOR_MISO 1
#define SPINOR_MISO__SPINAND_MISO 2
#define SPINOR_MISO__XGPIOA_23 3
#define SPINOR_CS_X__SPINOR_CS_X 1
#define SPINOR_CS_X__SPINAND_CS 2
#define SPINOR_CS_X__XGPIOA_24 3
#define JTAG_CPU_TMS__JTAG_TMS 0
#define JTAG_CPU_TMS__CAM_MCLK0 1
#define JTAG_CPU_TMS__PWM_7 2
#define JTAG_CPU_TMS__XGPIOA_19 3
#define JTAG_CPU_TMS__UART1_RTS 4
#define JTAG_CPU_TMS__AUX0 5
#define JTAG_CPU_TMS__UART1_TX 6
#define JTAG_CPU_TCK__JTAG_TCK 0
#define JTAG_CPU_TCK__CAM_MCLK1 1
#define JTAG_CPU_TCK__PWM_6 2
#define JTAG_CPU_TCK__XGPIOA_18 3
#define JTAG_CPU_TCK__UART1_CTS 4
#define JTAG_CPU_TCK__AUX1 5
#define JTAG_CPU_TCK__UART1_RX 6
#define IIC0_SCL__CV_SCL0__CR_4WTDI 0
#define IIC0_SDA__CV_SDA0__CR_4WTDO 0
#define IIC0_SCL__JTAG_TDI 0
#define IIC0_SCL__UART1_TX 1
#define IIC0_SCL__UART2_TX 2
#define IIC0_SCL__XGPIOA_28 3
#define IIC0_SCL__IIC0_SCL 4
#define IIC0_SCL__WG0_D0 5
#define IIC0_SCL__DBG_10 7
#define IIC0_SDA__JTAG_TDO 0
#define IIC0_SDA__UART1_RX 1
#define IIC0_SDA__UART2_RX 2
#define IIC0_SDA__XGPIOA_29 3
#define IIC0_SDA__IIC0_SDA 4
#define IIC0_SDA__WG0_D1 5
#define IIC0_SDA__WG1_D0 6
#define IIC0_SDA__DBG_11 7
#define AUX0__AUX0 0
#define AUX0__XGPIOA_30 3
#define AUX0__IIS1_MCLK 4
#define AUX0__WG1_D1 6
#define AUX0__DBG_12 7
#define GPIO_ZQ__PWR_GPIO_24 3
#define GPIO_ZQ__PWM_2 4
#define PWR_VBAT_DET__PWR_VBAT_DET 0
#define PWR_RSTN__PWR_RSTN 0
#define PWR_SEQ1__PWR_SEQ1 0
#define PWR_SEQ1__PWR_GPIO_3 3
#define PWR_SEQ2__PWR_SEQ2 0
#define PWR_SEQ2__PWR_GPIO_4 3
#define PTEST__PWR_PTEST 0
#define PWR_WAKEUP0__PWR_WAKEUP0 0
#define PWR_WAKEUP0__PWR_IR0 1
#define PWR_WAKEUP0__PWR_UART0_TX 2
#define PWR_WAKEUP0__PWR_GPIO_6 3
#define PWR_WAKEUP0__UART1_TX 4
#define PWR_WAKEUP0__IIC4_SCL 5
#define PWR_WAKEUP0__EPHY_LNK_LED 6
#define PWR_WAKEUP0__WG2_D0 7
#define PWR_BUTTON1__PWR_BUTTON1 0
#define PWR_BUTTON1__PWR_GPIO_8 3
#define PWR_BUTTON1__UART1_RX 4
#define PWR_BUTTON1__IIC4_SDA 5
#define PWR_BUTTON1__EPHY_SPD_LED 6
#define PWR_BUTTON1__WG2_D1 7
#define XTAL_XIN__PWR_XTAL_CLKIN 0
#define PWR_GPIO0__PWR_GPIO_0 0
#define PWR_GPIO0__UART2_TX 1
#define PWR_GPIO0__PWR_UART0_RX 2
#define PWR_GPIO0__PWM_8 4
#define PWR_GPIO1__PWR_GPIO_1 0
#define PWR_GPIO1__UART2_RX 1
#define PWR_GPIO1__EPHY_LNK_LED 3
#define PWR_GPIO1__PWM_9 4
#define PWR_GPIO1__PWR_IIC_SCL 5
#define PWR_GPIO1__IIC2_SCL 6
#define PWR_GPIO1__IIC0_SDA 7
#define PWR_GPIO2__PWR_GPIO_2 0
#define PWR_GPIO2__PWR_SECTICK 2
#define PWR_GPIO2__EPHY_SPD_LED 3
#define PWR_GPIO2__PWM_10 4
#define PWR_GPIO2__PWR_IIC_SDA 5
#define PWR_GPIO2__IIC2_SDA 6
#define PWR_GPIO2__IIC0_SCL 7
#define SD1_GPIO1__UART4_TX 1
#define SD1_GPIO1__PWR_GPIO_26 3
#define SD1_GPIO1__PWM_10 7
#define SD1_GPIO0__UART4_RX 1
#define SD1_GPIO0__PWR_GPIO_25 3
#define SD1_GPIO0__PWM_11 7
#define SD1_D3__PWR_SD1_D3 0
#define SD1_D3__SPI2_CS_X 1
#define SD1_D3__IIC1_SCL 2
#define SD1_D3__PWR_GPIO_18 3
#define SD1_D3__CAM_MCLK0 4
#define SD1_D3__UART3_CTS 5
#define SD1_D3__PWR_SPINOR1_CS_X 6
#define SD1_D3__PWM_4 7
#define SD1_D2__PWR_SD1_D2 0
#define SD1_D2__IIC1_SCL 1
#define SD1_D2__UART2_TX 2
#define SD1_D2__PWR_GPIO_19 3
#define SD1_D2__CAM_MCLK0 4
#define SD1_D2__UART3_TX 5
#define SD1_D2__PWR_SPINOR1_HOLD_X 6
#define SD1_D2__PWM_5 7
#define SD1_D1__PWR_SD1_D1 0
#define SD1_D1__IIC1_SDA 1
#define SD1_D1__UART2_RX 2
#define SD1_D1__PWR_GPIO_20 3
#define SD1_D1__CAM_MCLK1 4
#define SD1_D1__UART3_RX 5
#define SD1_D1__PWR_SPINOR1_WP_X 6
#define SD1_D1__PWM_6 7
#define SD1_D0__PWR_SD1_D0 0
#define SD1_D0__SPI2_SDI 1
#define SD1_D0__IIC1_SDA 2
#define SD1_D0__PWR_GPIO_21 3
#define SD1_D0__CAM_MCLK1 4
#define SD1_D0__UART3_RTS 5
#define SD1_D0__PWR_SPINOR1_MISO 6
#define SD1_D0__PWM_7 7
#define SD1_CMD__PWR_SD1_CMD 0
#define SD1_CMD__SPI2_SDO 1
#define SD1_CMD__IIC3_SCL 2
#define SD1_CMD__PWR_GPIO_22 3
#define SD1_CMD__CAM_VS0 4
#define SD1_CMD__EPHY_LNK_LED 5
#define SD1_CMD__PWR_SPINOR1_MOSI 6
#define SD1_CMD__PWM_8 7
#define SD1_CLK__PWR_SD1_CLK 0
#define SD1_CLK__SPI2_SCK 1
#define SD1_CLK__IIC3_SDA 2
#define SD1_CLK__PWR_GPIO_23 3
#define SD1_CLK__CAM_HS0 4
#define SD1_CLK__EPHY_SPD_LED 5
#define SD1_CLK__PWR_SPINOR1_SCK 6
#define SD1_CLK__PWM_9 7
#define PWM0_BUCK__PWM_0 0
#define PWM0_BUCK__XGPIOB_0 3
#define ADC1__XGPIOB_3 3
#define ADC1__KEY_COL2 4
#define ADC1__PWM_3 6
#define USB_VBUS_DET__USB_VBUS_DET 0
#define USB_VBUS_DET__XGPIOB_6 3
#define USB_VBUS_DET__CAM_MCLK0 4
#define USB_VBUS_DET__CAM_MCLK1 5
#define USB_VBUS_DET__PWM_4 6
#define MUX_SPI1_MISO__UART3_RTS 1
#define MUX_SPI1_MISO__IIC1_SDA 2
#define MUX_SPI1_MISO__XGPIOB_8 3
#define MUX_SPI1_MISO__PWM_9 4
#define MUX_SPI1_MISO__KEY_COL1 5
#define MUX_SPI1_MISO__SPI1_SDI 6
#define MUX_SPI1_MISO__DBG_14 7
#define MUX_SPI1_MOSI__UART3_RX 1
#define MUX_SPI1_MOSI__IIC1_SCL 2
#define MUX_SPI1_MOSI__XGPIOB_7 3
#define MUX_SPI1_MOSI__PWM_8 4
#define MUX_SPI1_MOSI__KEY_COL0 5
#define MUX_SPI1_MOSI__SPI1_SDO 6
#define MUX_SPI1_MOSI__DBG_13 7
#define MUX_SPI1_CS__UART3_CTS 1
#define MUX_SPI1_CS__CAM_MCLK0 2
#define MUX_SPI1_CS__XGPIOB_10 3
#define MUX_SPI1_CS__PWM_11 4
#define MUX_SPI1_CS__KEY_ROW3 5
#define MUX_SPI1_CS__SPI1_CS_X 6
#define MUX_SPI1_CS__DBG_16 7
#define MUX_SPI1_SCK__UART3_TX 1
#define MUX_SPI1_SCK__CAM_MCLK1 2
#define MUX_SPI1_SCK__XGPIOB_9 3
#define MUX_SPI1_SCK__PWM_10 4
#define MUX_SPI1_SCK__KEY_ROW2 5
#define MUX_SPI1_SCK__SPI1_SCK 6
#define MUX_SPI1_SCK__DBG_15 7
#define PAD_ETH_TXP__UART3_RX 1
#define PAD_ETH_TXP__IIC1_SCL 2
#define PAD_ETH_TXP__XGPIOB_25 3
#define PAD_ETH_TXP__PWM_13 4
#define PAD_ETH_TXP__CAM_MCLK0 5
#define PAD_ETH_TXP__SPI1_SDO 6
#define PAD_ETH_TXP__IIS2_LRCK 7
#define PAD_ETH_TXM__UART3_RTS 1
#define PAD_ETH_TXM__IIC1_SDA 2
#define PAD_ETH_TXM__XGPIOB_24 3
#define PAD_ETH_TXM__PWM_12 4
#define PAD_ETH_TXM__CAM_MCLK1 5
#define PAD_ETH_TXM__SPI1_SDI 6
#define PAD_ETH_TXM__IIS2_BCLK 7
#define PAD_ETH_RXP__UART3_TX 1
#define PAD_ETH_RXP__CAM_MCLK1 2
#define PAD_ETH_RXP__XGPIOB_27 3
#define PAD_ETH_RXP__PWM_15 4
#define PAD_ETH_RXP__CAM_HS0 5
#define PAD_ETH_RXP__SPI1_SCK 6
#define PAD_ETH_RXP__IIS2_DO 7
#define PAD_ETH_RXM__UART3_CTS 1
#define PAD_ETH_RXM__CAM_MCLK0 2
#define PAD_ETH_RXM__XGPIOB_26 3
#define PAD_ETH_RXM__PWM_14 4
#define PAD_ETH_RXM__CAM_VS0 5
#define PAD_ETH_RXM__SPI1_CS_X 6
#define PAD_ETH_RXM__IIS2_DI 7
#define GPIO_RTX__VI0_D_15 1
#define GPIO_RTX__XGPIOB_23 3
#define GPIO_RTX__PWM_1 4
#define GPIO_RTX__CAM_MCLK0 5
#define GPIO_RTX__IIS2_MCLK 7
#define PAD_MIPIRX4N__VI0_CLK 1
#define PAD_MIPIRX4N__IIC0_SCL 2
#define PAD_MIPIRX4N__XGPIOC_2 3
#define PAD_MIPIRX4N__IIC1_SDA 4
#define PAD_MIPIRX4N__CAM_MCLK0 5
#define PAD_MIPIRX4N__KEY_ROW0 6
#define PAD_MIPIRX4N__MUX_SPI1_SCK 7
#define PAD_MIPIRX4P__VI0_D_0 1
#define PAD_MIPIRX4P__IIC0_SDA 2
#define PAD_MIPIRX4P__XGPIOC_3 3
#define PAD_MIPIRX4P__IIC1_SCL 4
#define PAD_MIPIRX4P__CAM_MCLK1 5
#define PAD_MIPIRX4P__KEY_ROW1 6
#define PAD_MIPIRX4P__MUX_SPI1_CS 7
#define PAD_MIPIRX3N__VI0_D_1 1
#define PAD_MIPIRX3N__XGPIOC_4 3
#define PAD_MIPIRX3N__CAM_MCLK0 4
#define PAD_MIPIRX3N__MUX_SPI1_MISO 7
#define PAD_MIPIRX3P__VI0_D_2 1
#define PAD_MIPIRX3P__XGPIOC_5 3
#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7
#define PAD_MIPIRX2N__VI0_D_3 1
#define PAD_MIPIRX2N__XGPIOC_6 3
#define PAD_MIPIRX2N__IIC4_SCL 5
#define PAD_MIPIRX2N__DBG_6 7
#define PAD_MIPIRX2P__VI0_D_4 1
#define PAD_MIPIRX2P__XGPIOC_7 3
#define PAD_MIPIRX2P__IIC4_SDA 5
#define PAD_MIPIRX2P__DBG_7 7
#define PAD_MIPIRX1N__VI0_D_5 1
#define PAD_MIPIRX1N__XGPIOC_8 3
#define PAD_MIPIRX1N__KEY_ROW3 6
#define PAD_MIPIRX1N__DBG_8 7
#define PAD_MIPIRX1P__VI0_D_6 1
#define PAD_MIPIRX1P__XGPIOC_9 3
#define PAD_MIPIRX1P__IIC1_SDA 4
#define PAD_MIPIRX1P__KEY_ROW2 6
#define PAD_MIPIRX1P__DBG_9 7
#define PAD_MIPIRX0N__VI0_D_7 1
#define PAD_MIPIRX0N__XGPIOC_10 3
#define PAD_MIPIRX0N__IIC1_SCL 4
#define PAD_MIPIRX0N__CAM_MCLK1 5
#define PAD_MIPIRX0N__DBG_10 7
#define PAD_MIPIRX0P__VI0_D_8 1
#define PAD_MIPIRX0P__XGPIOC_11 3
#define PAD_MIPIRX0P__CAM_MCLK0 4
#define PAD_MIPIRX0P__DBG_11 7
#define PAD_MIPI_TXM2__VI0_D_13 1
#define PAD_MIPI_TXM2__IIC0_SDA 2
#define PAD_MIPI_TXM2__XGPIOC_16 3
#define PAD_MIPI_TXM2__IIC1_SDA 4
#define PAD_MIPI_TXM2__PWM_8 5
#define PAD_MIPI_TXM2__SPI0_SCK 6
#define PAD_MIPI_TXP2__VI0_D_14 1
#define PAD_MIPI_TXP2__IIC0_SCL 2
#define PAD_MIPI_TXP2__XGPIOC_17 3
#define PAD_MIPI_TXP2__IIC1_SCL 4
#define PAD_MIPI_TXP2__PWM_9 5
#define PAD_MIPI_TXP2__SPI0_CS_X 6
#define PAD_MIPI_TXP2__IIS1_MCLK 7
#define PAD_MIPI_TXM1__SPI3_SDO 0
#define PAD_MIPI_TXM1__VI0_D_11 1
#define PAD_MIPI_TXM1__IIS1_LRCK 2
#define PAD_MIPI_TXM1__XGPIOC_14 3
#define PAD_MIPI_TXM1__IIC2_SDA 4
#define PAD_MIPI_TXM1__PWM_10 5
#define PAD_MIPI_TXM1__SPI0_SDO 6
#define PAD_MIPI_TXM1__DBG_14 7
#define PAD_MIPI_TXP1__SPI3_SDI 0
#define PAD_MIPI_TXP1__VI0_D_12 1
#define PAD_MIPI_TXP1__IIS1_DO 2
#define PAD_MIPI_TXP1__XGPIOC_15 3
#define PAD_MIPI_TXP1__IIC2_SCL 4
#define PAD_MIPI_TXP1__PWM_11 5
#define PAD_MIPI_TXP1__SPI0_SDI 6
#define PAD_MIPI_TXP1__DBG_15 7
#define PAD_MIPI_TXM0__SPI3_SCK 0
#define PAD_MIPI_TXM0__VI0_D_9 1
#define PAD_MIPI_TXM0__IIS1_DI 2
#define PAD_MIPI_TXM0__XGPIOC_12 3
#define PAD_MIPI_TXM0__CAM_MCLK1 4
#define PAD_MIPI_TXM0__PWM_14 5
#define PAD_MIPI_TXM0__CAM_VS0 6
#define PAD_MIPI_TXM0__DBG_12 7
#define PAD_MIPI_TXP0__SPI3_CS_X 0
#define PAD_MIPI_TXP0__VI0_D_10 1
#define PAD_MIPI_TXP0__IIS1_BCLK 2
#define PAD_MIPI_TXP0__XGPIOC_13 3
#define PAD_MIPI_TXP0__CAM_MCLK0 4
#define PAD_MIPI_TXP0__PWM_15 5
#define PAD_MIPI_TXP0__CAM_HS0 6
#define PAD_MIPI_TXP0__DBG_13 7
#define PKG_TYPE0__PKG_TYPE0 0
#define PKG_TYPE1__PKG_TYPE1 0
#define PKG_TYPE2__PKG_TYPE2 0
#define PAD_AUD_AINL_MIC__XGPIOC_23 3
#define PAD_AUD_AINL_MIC__IIS1_BCLK 4
#define PAD_AUD_AINL_MIC__IIS2_BCLK 5
#define PAD_AUD_AINR_MIC__XGPIOC_22 3
#define PAD_AUD_AINR_MIC__IIS1_DO 4
#define PAD_AUD_AINR_MIC__IIS2_DI 5
#define PAD_AUD_AINR_MIC__IIS1_DI 6
#define PAD_AUD_AOUTL__XGPIOC_25 3
#define PAD_AUD_AOUTL__IIS1_LRCK 4
#define PAD_AUD_AOUTL__IIS2_LRCK 5
#define PAD_AUD_AOUTR__XGPIOC_24 3
#define PAD_AUD_AOUTR__IIS1_DI 4
#define PAD_AUD_AOUTR__IIS2_DO 5
#define PAD_AUD_AOUTR__IIS1_DO 6
#endif /* __CV180X_PINLIST_SWCONFIG_H__ */

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freertos/cvitek/install/include/hal/config/cv180x_pinmux.h Normal file
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#ifndef _CV180X_PINMUX_H_
#define _CV180X_PINMUX_H_
/*
* Pinmux definitions
*/
#define PINMUX_UART0 0
#define PINMUX_UART1 1
#define PINMUX_UART2 2
#define PINMUX_UART3 3
#define PINMUX_UART3_2 4
#define PINMUX_I2C0 5
#define PINMUX_I2C1 6
#define PINMUX_I2C2 7
#define PINMUX_I2C3 8
#define PINMUX_I2C4 9
#define PINMUX_I2C4_2 10
#define PINMUX_SPI0 11
#define PINMUX_SPI1 12
#define PINMUX_SPI2 13
#define PINMUX_SPI2_2 14
#define PINMUX_SPI3 15
#define PINMUX_SPI3_2 16
#define PINMUX_I2S0 17
#define PINMUX_I2S1 18
#define PINMUX_I2S2 19
#define PINMUX_I2S3 20
#define PINMUX_USBID 21
#define PINMUX_SDIO0 22
#define PINMUX_SDIO1 23
#define PINMUX_ND 24
#define PINMUX_EMMC 25
#define PINMUX_SPI_NOR 26
#define PINMUX_SPI_NAND 27
#define PINMUX_CAM0 28
#define PINMUX_CAM1 29
#define PINMUX_PCM0 30
#define PINMUX_PCM1 31
#define PINMUX_CSI0 32
#define PINMUX_CSI1 33
#define PINMUX_CSI2 34
#define PINMUX_DSI 35
#define PINMUX_VI0 36
#define PINMUX_VO 37
#define PINMUX_RMII1 38
#define PINMUX_EPHY_LED 39
#define PINMUX_I80 40
#define PINMUX_LVDS 41
#define PINMUX_USB 42
#endif // end of _CV180X_PINMUX_H_

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freertos/cvitek/install/include/hal/config/cv180x_reg_fmux_gpio.h Normal file
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// $Module: fmux_gpio $
// $RegisterBank Version: V 1.0.00 $
// $Author: ghost $
// $Date: Thu, 17 Mar 2022 04:53:31 PM $
//
//GEN REG ADDR/OFFSET/MASK
#ifndef __CV180X_REG_FMUX_GPIO_H__
#define __CV180X_REG_FMUX_GPIO_H__
#define FMUX_GPIO_REG_IOCTRL_SD0_CLK 0x0
#define FMUX_GPIO_REG_IOCTRL_SD0_CMD 0x4
#define FMUX_GPIO_REG_IOCTRL_SD0_D0 0x8
#define FMUX_GPIO_REG_IOCTRL_SD0_D1 0xc
#define FMUX_GPIO_REG_IOCTRL_SD0_D2 0x10
#define FMUX_GPIO_REG_IOCTRL_SD0_D3 0x14
#define FMUX_GPIO_REG_IOCTRL_SD0_CD 0x18
#define FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN 0x1c
#define FMUX_GPIO_REG_IOCTRL_SPK_EN 0x20
#define FMUX_GPIO_REG_IOCTRL_UART0_TX 0x24
#define FMUX_GPIO_REG_IOCTRL_UART0_RX 0x28
#define FMUX_GPIO_REG_IOCTRL_SPINOR_HOLD_X 0x2c
#define FMUX_GPIO_REG_IOCTRL_SPINOR_SCK 0x30
#define FMUX_GPIO_REG_IOCTRL_SPINOR_MOSI 0x34
#define FMUX_GPIO_REG_IOCTRL_SPINOR_WP_X 0x38
#define FMUX_GPIO_REG_IOCTRL_SPINOR_MISO 0x3c
#define FMUX_GPIO_REG_IOCTRL_SPINOR_CS_X 0x40
#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS 0x44
#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK 0x48
#define FMUX_GPIO_REG_IOCTRL_IIC0_SCL 0x4c
#define FMUX_GPIO_REG_IOCTRL_IIC0_SDA 0x50
#define FMUX_GPIO_REG_IOCTRL_AUX0 0x54
#define FMUX_GPIO_REG_IOCTRL_GPIO_ZQ 0x58
#define FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET 0x5c
#define FMUX_GPIO_REG_IOCTRL_PWR_RSTN 0x60
#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ1 0x64
#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ2 0x68
#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0 0x6c
#define FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1 0x70
#define FMUX_GPIO_REG_IOCTRL_XTAL_XIN 0x74
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO0 0x78
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO1 0x7c
#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO2 0x80
#define FMUX_GPIO_REG_IOCTRL_SD1_GPIO1 0x84
#define FMUX_GPIO_REG_IOCTRL_SD1_GPIO0 0x88
#define FMUX_GPIO_REG_IOCTRL_SD1_D3 0x8c
#define FMUX_GPIO_REG_IOCTRL_SD1_D2 0x90
#define FMUX_GPIO_REG_IOCTRL_SD1_D1 0x94
#define FMUX_GPIO_REG_IOCTRL_SD1_D0 0x98
#define FMUX_GPIO_REG_IOCTRL_SD1_CMD 0x9c
#define FMUX_GPIO_REG_IOCTRL_SD1_CLK 0xa0
#define FMUX_GPIO_REG_IOCTRL_PWM0_BUCK 0xa4
#define FMUX_GPIO_REG_IOCTRL_ADC1 0xa8
#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET 0xac
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO 0xb0
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI 0xb4
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS 0xb8
#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK 0xbc
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP 0xc0
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM 0xc4
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP 0xc8
#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM 0xcc
#define FMUX_GPIO_REG_IOCTRL_GPIO_RTX 0xd0
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N 0xd4
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P 0xd8
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N 0xdc
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P 0xe0
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N 0xe4
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P 0xe8
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N 0xec
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P 0xf0
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N 0xf4
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P 0xf8
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2 0xfc
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2 0x100
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1 0x104
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1 0x108
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0 0x10c
#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0 0x110
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE0 0x114
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE1 0x118
#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE2 0x11c
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC 0x120
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC 0x124
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL 0x128
#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR 0x12c
#define FMUX_GPIO_REG_DEVMATRIX_UART0_IP_SEL 0x1d4
#define FMUX_GPIO_REG_DEVMATRIX_UART1_IP_SEL 0x1d8
#define FMUX_GPIO_REG_DEVMATRIX_UART2_IP_SEL 0x1dc
#define FMUX_GPIO_REG_DEVMATRIX_UART3_IP_SEL 0x1e0
#define FMUX_GPIO_REG_DEVMATRIX_UART4_IP_SEL 0x1e4
#define FMUX_GPIO_FUNCSEL_SD0_CLK 0x0
#define FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_CMD 0x4
#define FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CMD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D0 0x8
#define FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D1 0xc
#define FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D2 0x10
#define FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_D3 0x14
#define FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_D3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_CD 0x18
#define FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_CD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN 0x1c
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPK_EN 0x20
#define FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPK_EN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART0_TX 0x24
#define FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART0_TX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_UART0_RX 0x28
#define FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_UART0_RX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X 0x2c
#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_SCK 0x30
#define FMUX_GPIO_FUNCSEL_SPINOR_SCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_SCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI 0x34
#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X 0x38
#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_MISO 0x3c
#define FMUX_GPIO_FUNCSEL_SPINOR_MISO_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_MISO_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X 0x40
#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X_MASK 0x7
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS 0x44
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK 0x48
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC0_SCL 0x4c
#define FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_IIC0_SDA 0x50
#define FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0
#define FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK 0x7
#define FMUX_GPIO_FUNCSEL_AUX0 0x54
#define FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_AUX0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ 0x58
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0
#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET 0x5c
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_RSTN 0x60
#define FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1 0x64
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2 0x68
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0 0x6c
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1 0x70
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_XTAL_XIN 0x74
#define FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0
#define FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0 0x78
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1 0x7c
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2 0x80
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_GPIO1 0x84
#define FMUX_GPIO_FUNCSEL_SD1_GPIO1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_GPIO1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_GPIO0 0x88
#define FMUX_GPIO_FUNCSEL_SD1_GPIO0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_GPIO0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D3 0x8c
#define FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D3_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D2 0x90
#define FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D1 0x94
#define FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_D0 0x98
#define FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_D0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_CMD 0x9c
#define FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_CMD_MASK 0x7
#define FMUX_GPIO_FUNCSEL_SD1_CLK 0xa0
#define FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_SD1_CLK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK 0xa4
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_ADC1 0xa8
#define FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_ADC1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET 0xac
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0
#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO 0xb0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI 0xb4
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS 0xb8
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK 0x7
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK 0xbc
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0
#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP 0xc0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM 0xc4
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP 0xc8
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM 0xcc
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK 0x7
#define FMUX_GPIO_FUNCSEL_GPIO_RTX 0xd0
#define FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0
#define FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N 0xd4
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P 0xd8
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N 0xdc
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P 0xe0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N 0xe4
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P 0xe8
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N 0xec
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P 0xf0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N 0xf4
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P 0xf8
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2 0xfc
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2 0x100
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1 0x104
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1 0x108
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0 0x10c
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0 0x110
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0 0x114
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1 0x118
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2 0x11c
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC 0x120
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC 0x124
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL 0x128
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK 0x7
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR 0x12c
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0
#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK 0x7
#define FMUX_GPIO_MUX_UART0_IP_SEL 0x1d4
#define FMUX_GPIO_MUX_UART0_IP_SEL_OFFSET 0
#define FMUX_GPIO_MUX_UART0_IP_SEL_MASK 0x7
#define FMUX_GPIO_MUX_UART1_IP_SEL 0x1d8
#define FMUX_GPIO_MUX_UART1_IP_SEL_OFFSET 0
#define FMUX_GPIO_MUX_UART1_IP_SEL_MASK 0x7
#define FMUX_GPIO_MUX_UART2_IP_SEL 0x1dc
#define FMUX_GPIO_MUX_UART2_IP_SEL_OFFSET 0
#define FMUX_GPIO_MUX_UART2_IP_SEL_MASK 0x7
#define FMUX_GPIO_MUX_UART3_IP_SEL 0x1e0
#define FMUX_GPIO_MUX_UART3_IP_SEL_OFFSET 0
#define FMUX_GPIO_MUX_UART3_IP_SEL_MASK 0x7
#define FMUX_GPIO_MUX_UART4_IP_SEL 0x1e4
#define FMUX_GPIO_MUX_UART4_IP_SEL_OFFSET 0
#define FMUX_GPIO_MUX_UART4_IP_SEL_MASK 0x7
#endif /* __CV180X_REG_FMUX_GPIO_H__ */

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freertos/cvitek/install/include/hal/config/intr_conf.h Normal file
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#ifndef _CV180X_INTERRUPT_CONFIG_H_
#define _CV180X_INTERRUPT_CONFIG_H_
/* irq */
#define IRQ_LEVEL 0
#define IRQ_EDGE 3
#define NA 0xFFFF
#define TEMPSEN_IRQ_O NA
#define RTC_ALARM_O NA
#define RTC_PWR_BUTTON1_LONGPRESS_O NA
#define VBAT_DEB_IRQ_O NA
#define JPEG_INTERRUPT 16
#define H264_INTERRUPT 17
#define H265_INTERRUPT 18
#define VC_SBM_INT 19
#define ISP_INT 20
#define SC_INTR_0 21
#define VIP_INT_CSI_MAC0 22
#define VIP_INT_CSI_MAC1 23
#define LDC_INT 24
#define SDMA_INTR_CPU0 NA
#define SDMA_INTR_CPU1 NA
#define SDMA_INTR_CPU2 25
#define USB_IRQS NA
#define ETH0_SBD_INTR_O NA
#define ETH0_LPI_INTR_O NA
#define EMMC_WAKEUP_INTR NA
#define EMMC_INTR NA
#define SD0_WAKEUP_INTR NA
#define SD0_INTR NA
#define SD1_WAKEUP_INTR NA
#define SD1_INTR NA
#define SPI_NAND_INTR NA
#define I2S0_INT 26
#define I2S1_INT 27
#define I2S2_INT 28
#define I2S3_INT 29
#define UART0_INTR 30
#define UART1_INTR 31
#define UART2_INTR NA
#define UART3_INTR NA
#define UART4_INTR NA
#define I2C0_INTR 32
#define I2C1_INTR 33
#define I2C2_INTR 34
#define I2C3_INTR 35
#define I2C4_INTR 36
#define SPI_0_SSI_INTR 37
#define SPI_1_SSI_INTR 38
#define SPI_2_SSI_INTR NA
#define SPI_3_SSI_INTR NA
#define WDT0_INTR NA
#define WDT1_INTR NA
#define WDT2_INTR 39
#define KEYSCAN_IRQ 40
#define GPIO0_INTR_FLAG 41
#define GPIO1_INTR_FLAG 42
#define GPIO2_INTR_FLAG 43
#define GPIO3_INTR_FLAG 44
#define WGN0_IRQ 45
#define WGN1_IRQ NA
#define WGN2_IRQ NA
#define MBOX_INT1 46
#define IRRX_INT 47
#define GPIO_INT 48
#define UART_INT 49
#define SPI_INT NA
#define I2C_INT 50
#define WDT_INT 51
#define TPU_INTR NA
#define TDMA_INTERRUPT 52
#define SW_INT_0_CPU0 NA
#define SW_INT_1_CPU0 NA
#define SW_INT_0_CPU1 NA
#define SW_INT_1_CPU1 NA
#define SW_INT_0_CPU2 53
#define SW_INT_1_CPU2 54
#define TIMER_INTR_0 NA
#define TIMER_INTR_1 NA
#define TIMER_INTR_2 NA
#define TIMER_INTR_3 NA
#define TIMER_INTR_4 55
#define TIMER_INTR_5 56
#define TIMER_INTR_6 57
#define TIMER_INTR_7 58
#define PERI_FIREWALL_IRQ NA
#define HSPERI_FIREWALL_IRQ NA
#define DDR_FW_INTR NA
#define ROM_FIREWALL_IRQ NA
#define SPACC_IRQ 59
#define TRNG_IRQ NA
#define AXI_MON_INTR NA
#define DDRC_PI_PHY_INTR NA
#define SF_SPI_INT NA
#define EPHY_INT_N_O NA
#define IVE_INT 60
#define DBGSYS_APBUSMON_HANG_INT NA
#define INTR_SARADC NA
#define MBOX_INT_CA53 NA
#define MBOX_INT_C906 NA
#define MBOX_INT_C906_2ND 61
#define NPMUIRQ_0 NA
#define CTIIRQ_0 NA
#define NEXTERRIRQ NA
#define IRQF_TRIGGER_NONE 0x00000000
#define IRQF_TRIGGER_RISING 0x00000001
#define IRQF_TRIGGER_FALLING 0x00000002
#define IRQF_TRIGGER_HIGH 0x00000004
#define IRQF_TRIGGER_LOW 0x00000008
#define IRQF_TRIGGER_MASK \
(IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW | IRQF_TRIGGER_RISING | \
IRQF_TRIGGER_FALLING)
typedef int (*irq_handler_t)(int irqn, void *priv);
int request_irq(int irqn, irq_handler_t handler,
unsigned long flags, const char *name, void *priv);
/*
void disable_irq(unsigned int irqn);
void enable_irq(unsigned int irqn);
void cpu_enable_irqs(void);
void cpu_disable_irqs(void);
extern void irq_trigger(int irqn);
extern void irq_clear(int irqn);
extern int irq_get_nums(void);
void pinmux_config(int io_type);
*/
/*FIXME
* NUM_IRQ may be different accross
* different platform, we should review it when porting
*/
#define NUM_IRQ (62)
#endif //end of_CV180X_INTERRUPT_CONFIG_H_

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freertos/cvitek/install/include/hal/config/memmap.h Normal file
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#ifndef __MEMMAP_H__
#define __MEMMAP_H__
/* confirm with CONFIG_SYS_RESVIONSZ & CONFIG_SYS_RESVOSSZ by uboot defconfig */
/* H26X_BITSTREAM_ADDR = CONFIG_SYS_BOOTMAPSZ - CONFIG_SYS_RESVIONSZ - CONFIG_SYS_RESVOSSZ*/
#ifdef LINUX_BSP_64MB
#define H26X_BITSTREAM_ADDR (0x82700000)
#define H26X_BITSTREAM_SIZE (0x00200000)
#define H26X_ENC_BUFF_ADDR (H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE)
#define H26X_ENC_BUFF_SIZE (0x00000000)
#define ISP_MEM_BASE_ADDR (H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE)
#define ISP_MEM_BASE_SIZE (0x00A00000)
#elif defined (LINUX_BSP_128MB)
#define H26X_BITSTREAM_ADDR (0x83C80000)
#define H26X_BITSTREAM_SIZE (0x00200000)
#define H26X_ENC_BUFF_ADDR (H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE)
#define H26X_ENC_BUFF_SIZE (0x00000000)
#define ISP_MEM_BASE_ADDR (H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE)
#define ISP_MEM_BASE_SIZE (0x00A00000)
#else
#define H26X_BITSTREAM_ADDR (0x00000000)
#define H26X_BITSTREAM_SIZE (0x00000000)
#define H26X_ENC_BUFF_ADDR (H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE)
#define H26X_ENC_BUFF_SIZE (0x00000000)
#define ISP_MEM_BASE_ADDR (H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE)
#define ISP_MEM_BASE_SIZE (0x00000000)
#endif
#endif // end of __MEMMAP_H__

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freertos/cvitek/install/include/hal/config/pinctrl.h Normal file
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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: pinctrl.h
* Description:
*/
#ifndef __PINCTRL_CV180X_H__
#define __PINCTRL_CV180X_H__
#include "cv180x_pinlist_swconfig.h"
#include "cv180x_reg_fmux_gpio.h"
#define PAD_MIPI_TXM4__MIPI_TXM4 0
#define PAD_MIPI_TXP4__MIPI_TXP4 0
#define PAD_MIPI_TXM3__MIPI_TXM3 0
#define PAD_MIPI_TXP3__MIPI_TXP3 0
#define PAD_MIPI_TXM2__MIPI_TXM2 0
#define PAD_MIPI_TXP2__MIPI_TXP2 0
#define PAD_MIPI_TXM1__MIPI_TXM1 0
#define PAD_MIPI_TXP1__MIPI_TXP1 0
#define PAD_MIPI_TXM0__MIPI_TXM0 0
#define PAD_MIPI_TXP0__MIPI_TXP0 0
#define PINMUX_BASE 0x03001000
#define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK
#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET
#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME
#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \
FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK << FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET, \
PIN_NAME##__##FUNC_NAME)
#endif /* __PINCTRL_CV180X_H__ */

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freertos/cvitek/install/include/hal/config/reg.h Normal file
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#ifndef _CVI_REG_H_
#define _CVI_REG_H_
#include "mmio.h"
#define _reg_read(addr) mmio_read_32(addr)
#define _reg_write(addr, data) mmio_write_32(addr, data)
#define _reg_write_mask(addr, mask, data) mmio_clrsetbits_32(addr, mask, data)
#endif //_CVI_REG_H_

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