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[freertos] add freertos firmware

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Change-Id: I4158d66d9b5fc444e28287f55e79ac24e0a1666f
This commit is contained in:
sam.xiang
2023-02-23 11:39:27 +08:00
parent 1cf39ecdd5
commit cbb030f19f
398 changed files with 151104 additions and 0 deletions
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133
freertos/cvitek/install/include/driver/cif/cif.h Normal file
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/*
* Copyright CviTek Inc.
*
* Created Time: May, 2021
*/
#ifndef __CVI_CIF_H__
#define __CVI_CIF_H__
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#ifdef RUN_IN_SRAM
#include "drv/cif_drv.h"
#elif (RUN_TYPE == CVIRTOS)
#include "cif_drv.h"
#endif
#include "gpio.h"
#include "cif_uapi.h"
#include "sensor.h"
#define CIF_MAX_CSI_NUM 2
#define CIF_MAX_MAC_NUM 3
#define CSIMAC0_INTR_NUM (22)
#define CSIMAC1_INTR_NUM (23)
/* Register Base Address */
#define DPHY_TOP_BASE (0x0A0D0000)
#define DPHY_4L_BASE (0x0A0D0300)
#define DPHY_2L_BASE (0x0A0D0600)
#define SENSOR_MAC0_BASE (0x0A0C2000)
#define SENSOR_MAC1_BASE (0x0A0C4000)
#define SENSOR_MAC_VI_BASE (0x0A0C6000)
#define SENSOR_CSI0_BASE (0x0A0C2400)
#define SENSOR_CSI1_BASE (0x0A0C4400)
// CAM_PLL
#define CLK_CAM0_SRC_DIV (0x030028C0)
#define CLK_CAM1_SRC_DIV (0x030028C4)
/* Register fileds */
#define DPHY_TOP_REG_04 (DPHY_TOP_BASE + 0x04)
#define DPHY_TOP_REG_30 (DPHY_TOP_BASE + 0x30)
#define DPHY_4L_REG_04 (DPHY_4L_BASE + 0x04)
#define DPHY_4L_REG_08 (DPHY_4L_BASE + 0x08)
#define DPHY_4L_REG_0C (DPHY_4L_BASE + 0x0C)
#define DPHY_4L_REG_10 (DPHY_4L_BASE + 0x10)
#define DPHY_2L_REG_04 (DPHY_2L_BASE + 0x04)
#define DPHY_2L_REG_08 (DPHY_2L_BASE + 0x08)
#define DPHY_2L_REG_0C (DPHY_2L_BASE + 0x0C)
#define DPHY_2L_REG_10 (DPHY_2L_BASE + 0x10)
// CAM_PLL
#define REG_CAM_DIV_DIS (4)
#define REG_CAM_SRC (8)
#define REG_CAM_SRC_MASK (3 << REG_CAM_SRC)
#define REG_CAM_DIV (16)
#define REG_CAM_DIV_MASK (0x3F << REG_CAM_DIV)
/* Macro */
#define CSI_HDR_ID_VALUE (0xfff00)
#define CSI_HDR_VC_VALUE (0xdff00)
#define CSI_LINEAR_VALUE (0xcff00)
#define CIF_PHY_LANE_NUM 6
#define MAX_PAD_NUM 19
#define ENOIOCTLCMD 515 /* No ioctl command */
/* Struct */
struct cvi_csi_status {
unsigned int errcnt_ecc;
unsigned int errcnt_crc;
unsigned int errcnt_hdr;
unsigned int errcnt_wc;
unsigned int fifo_full;
};
struct cvi_lvds_status {
unsigned int fifo_full;
};
struct cvi_link {
struct cif_ctx cif_ctx;
unsigned int irq_num;
// struct reset_control *phy_reset;
// struct reset_control *phy_apb_reset;
unsigned int is_on;
struct cif_param param;
struct combo_dev_attr_s attr;
enum clk_edge_e clk_edge;
enum output_msb_e msb;
unsigned int crop_top;
unsigned int distance_fp;
int snsr_rst_pin;
enum of_gpio_flags snsr_rst_pol;
union {
struct cvi_csi_status sts_csi;
struct cvi_lvds_status sts_lvds;
};
// struct device *dev;
enum rx_mac_clk_e mac_clk;
enum ttl_bt_fmt_out bt_fmt_out;
};
struct cvi_cam_clk {
int is_on;
// struct clk *clk_o;
};
struct cvi_cif_dev {
uint32_t devno;
// struct miscdevice miscdev;
// spinlock_t lock;
// struct mutex mutex;
struct cvi_link link[MAX_LINK_NUM];
// struct cvi_cam_clk clk_cam0;
// struct cvi_cam_clk clk_cam1;
// struct cvi_cam_clk vip_sys2;
// struct cvi_cam_clk clk_div_0_src_vip_sys_2; /* mipipll */
// struct cvi_cam_clk clk_div_1_src_vip_sys_2; /* fpll */
unsigned int max_mac_clk;
void *pad_ctrl;
};
#endif //__CVI_CIF_H__

19
freertos/cvitek/install/include/driver/cif/irqreturn.h Normal file
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#ifndef _LINUX_IRQRETURN_H
#define _LINUX_IRQRETURN_H
/**
* enum irqreturn
* @IRQ_NONE interrupt was not from this device or was not handled
* @IRQ_HANDLED interrupt was handled by this device
* @IRQ_WAKE_THREAD handler requests to wake the handler thread
*/
enum irqreturn {
IRQ_NONE = (0 << 0),
IRQ_HANDLED = (1 << 0),
IRQ_WAKE_THREAD = (1 << 1),
};
typedef enum irqreturn irqreturn_t;
#define IRQ_RETVAL(x) ((x) ? IRQ_HANDLED : IRQ_NONE)
#endif

155
freertos/cvitek/install/include/driver/fast_image/fast_image.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Cvitek Co., Ltd. 2019-2022. All rights reserved.
*
* File Name: fast_image.h
* Description:
*/
#ifndef __FAST_IMAGE_HEADER__
#define __FAST_IMAGE_HEADER__
#include "rtos_cmdqu.h"
#ifndef __linux__
#include "types.h"
#else
#include <linux/kernel.h>
enum FAST_IMAGE_CMD_TYPE {
FAST_SEND_STOP_REC = CMDQU_SYSTEM_LIMIT,
FAST_SEND_QUERY_ISP_PADDR,
FAST_SEND_QUERY_ISP_VADDR,
FAST_SEND_QUERY_ISP_SIZE,
FAST_SEND_QUERY_ISP_CTXT,
FAST_SEND_QUERY_IMG_PADDR,
FAST_SEND_QUERY_IMG_VADDR,
FAST_SEND_QUERY_IMG_SIZE,
FAST_SEND_QUERY_IMG_CTXT,
FAST_SEND_QUERY_ENC_PADDR,
FAST_SEND_QUERY_ENC_VADDR,
FAST_SEND_QUERY_ENC_SIZE,
FAST_SEND_QUERY_ENC_CTXT,
FAST_SEND_QUERY_FREE_ISP_ION,
FAST_SEND_QUERY_FREE_IMG_ION,
FAST_SEND_QUERY_FREE_ENC_ION,
FAST_SEND_QUERY_DUMP_MSG,
FAST_SEND_QUERY_DUMP_MSG_INFO,
FAST_SEND_QUERY_DUMP_EN,
FAST_SEND_QUERY_DUMP_DIS,
FAST_SEND_QUERY_DUMP_JPG,
FAST_SEND_QUERY_DUMP_JPG_INFO,
FAST_SEND_QUERY_TRACE_SNAPSHOT_START,
FAST_SEND_QUERY_TRACE_SNAPSHOT_STOP,
FAST_SEND_QUERY_TRACE_SNAPSHOT_DUMP,
FAST_SEND_QUERY_TRACE_STREAM_START,
FAST_SEND_QUERY_TRACE_STREAM_STOP,
FAST_SEND_QUERY_TRACE_STREAM_DUMP,
FAST_SEND_LIMIT,
};
#define FAST_IMAGE_DEV_NAME "cvi-fast-image"
#define FAST_IMAGE_SEND_STOP_REC _IOW('r', FAST_SEND_STOP_REC, unsigned long)
#define FAST_IMAGE_QUERY_ISP_PADDR _IOW('r', FAST_SEND_QUERY_ISP_PADDR, unsigned long)
#define FAST_IMAGE_QUERY_ISP_VADDR _IOW('r', FAST_SEND_QUERY_ISP_VADDR, unsigned long)
#define FAST_IMAGE_QUERY_ISP_SIZE _IOW('r', FAST_SEND_QUERY_ISP_SIZE, unsigned long)
#define FAST_IMAGE_QUERY_ISP_CTXT _IOW('r', FAST_SEND_QUERY_ISP_CTXT, unsigned long)
#define FAST_IMAGE_QUERY_IMG_PADDR _IOW('r', FAST_SEND_QUERY_IMG_PADDR, unsigned long)
#define FAST_IMAGE_QUERY_IMG_VADDR _IOW('r', FAST_SEND_QUERY_IMG_VADDR, unsigned long)
#define FAST_IMAGE_QUERY_IMG_SIZE _IOW('r', FAST_SEND_QUERY_IMG_SIZE, unsigned long)
#define FAST_IMAGE_QUERY_IMG_CTXT _IOW('r', FAST_SEND_QUERY_IMG_CTXT, unsigned long)
#define FAST_IMAGE_QUERY_ENC_PADDR _IOW('r', FAST_SEND_QUERY_ENC_PADDR, unsigned long)
#define FAST_IMAGE_QUERY_ENC_VADDR _IOW('r', FAST_SEND_QUERY_ENC_VADDR, unsigned long)
#define FAST_IMAGE_QUERY_ENC_SIZE _IOW('r', FAST_SEND_QUERY_ENC_SIZE, unsigned long)
#define FAST_IMAGE_QUERY_ENC_CTXT _IOW('r', FAST_SEND_QUERY_ENC_CTXT, unsigned long)
#define FAST_IMAGE_QUERY_FREE_ISP_ION _IOW('r', FAST_SEND_QUERY_FREE_ISP_ION, unsigned long)
#define FAST_IMAGE_QUERY_FREE_IMG_ION _IOW('r', FAST_SEND_QUERY_FREE_IMG_ION, unsigned long)
#define FAST_IMAGE_QUERY_FREE_ENC_ION _IOW('r', FAST_SEND_QUERY_FREE_ENC_ION, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_MSG _IOW('r', FAST_SEND_QUERY_DUMP_MSG, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_MSG_INFO _IOW('r', FAST_SEND_QUERY_DUMP_MSG_INFO, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_EN _IOW('r', FAST_SEND_QUERY_DUMP_EN, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_DIS _IOW('r', FAST_SEND_QUERY_DUMP_DIS, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_JPG _IOW('r', FAST_SEND_QUERY_DUMP_JPG, unsigned long)
#define FAST_IMAGE_QUERY_DUMP_JPG_INFO _IOW('r', FAST_SEND_QUERY_DUMP_JPG_INFO, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_SNAPSHOT_START _IOW('r', FAST_SEND_QUERY_TRACE_SNAPSHOT_START, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_SNAPSHOT_STOP _IOW('r', FAST_SEND_QUERY_TRACE_SNAPSHOT_STOP, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_SNAPSHOT_DUMP _IOW('r', FAST_SEND_QUERY_TRACE_SNAPSHOT_DUMP, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_STREAM_START _IOW('r', FAST_SEND_QUERY_TRACE_STREAM_START, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_STREAM_STOP _IOW('r', FAST_SEND_QUERY_TRACE_STREAM_STOP, unsigned long)
#define FAST_IMAGE_QUERY_TRACE_STREAM_DUMP _IOW('r', FAST_SEND_QUERY_TRACE_STREAM_DUMP, unsigned long)
#endif // end of __linux__
#define C906_MAGIC_HEADER 0xA55AC906 // master cpu is c906
#define CA53_MAGIC_HEADER 0xA55ACA53 // master cpu is ca53
#ifdef __riscv
#define RTOS_MAGIC_HEADER C906_MAGIC_HEADER
#else
#define RTOS_MAGIC_HEADER CA53_MAGIC_HEADER
#endif
enum E_IMAGE_TYPE {
E_FAST_NONE = 0,
E_FAST_JEPG = 1,
E_FAST_H264,
E_FAST_H265,
};
enum _MUC_STATUS_E {
MCU_STATUS_NONOS_INIT = 1,
MCU_STATUS_NONOS_RUNNING,
MCU_STATUS_NONOS_DONE,
MCU_STATUS_RTOS_T1_INIT, // before linux running
MCU_STATUS_RTOS_T1_RUNNING,
MCU_STATUS_RTOS_T2_INIT, // after linux running
MCU_STATUS_RTOS_T2_RUNNING,
MCU_STATUS_LINUX_INIT,
MCU_STATUS_LINUX_RUNNING,
};
enum DUMP_PRINT_SIZE_E {
DUMP_PRINT_SZ_IDX_0K = 0,
DUMP_PRINT_SZ_IDX_4K = 12, // 4096 = 1<<12
DUMP_PRINT_SZ_IDX_8K,
DUMP_PRINT_SZ_IDX_16K,
DUMP_PRINT_SZ_IDX_32K,
DUMP_PRINT_SZ_IDX_64K,
DUMP_PRINT_SZ_IDX_128K,
DUMP_PRINT_SZ_IDX_LIMIT,
};
#define ATTR __attribute__
#ifndef __packed
#define __packed ATTR((packed))
#endif
#ifndef __aligned
#define __aligned(x) ATTR((aligned(x)))
#endif
/* this structure should be modified both fsbl & MCU & osdrv side */
struct transfer_config_t {
uint32_t conf_magic;
uint32_t conf_size; //conf_size exclude mcu_status & linux_status
uint32_t isp_buffer_addr;
uint32_t isp_buffer_size;
uint32_t encode_img_addr;
uint32_t encode_img_size;
uint32_t encode_buf_addr;
uint32_t encode_buf_size;
uint8_t dump_print_enable;
uint8_t dump_print_size_idx;
uint16_t image_type;
uint16_t checksum; // checksum exclude mcu_status & linux_status
uint8_t mcu_status;
uint8_t linux_status;
} __packed __aligned(0x40);
struct trace_snapshot_t {
uint32_t ptr;
uint16_t size;
uint16_t type;
} __packed;
#endif // end of __FAST_IMAGE_HEADER__

19
freertos/cvitek/install/include/driver/gpio/gpio.h Normal file
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#ifndef __GPIO_H__
#define __GPIO_H__
#include <stddef.h>
#include <stdint.h>
#define CVI_GPIOA_BASE 0x03020000
#define CVI_GPIOB_BASE 0x03021000
#define CVI_GPIOC_BASE 0x03022000
#define CVI_GPIOD_BASE 0x03023000
enum of_gpio_flags {
OF_GPIO_ACTIVE_LOW = 0x1
};
int gpio_is_valid(int pin);
void gpio_direction_output(int pin, int val);
#endif

23
freertos/cvitek/install/include/driver/jenc/jenc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DRV_JENC_H__
#define __DRV_JENC_H__
#ifdef FREERTOS_BSP
#include "cvi_type.h"
int jpu_enc(CVI_U32 width, CVI_U32 height, CVI_U32 phySrcAddr, CVI_U32 phyDstAddr, CVI_U64 pts);
#else
#include <linux/cvi_type.h>
#endif
#define MAX_JPEG_NUM 16
typedef struct _JPEG_PIC {
CVI_U32 width;
CVI_U32 height;
CVI_U32 addr;
CVI_U32 size;
CVI_U64 pts;
} JPEG_PIC;
#endif // end of __DRV_JENC_H__

6
freertos/cvitek/install/include/driver/pinmux/pinmux.h Normal file
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#ifndef __PINMUX_CONFIG_H__
#define __PINMUX_CONFIG_H__
void pinmux_init(void);
#endif //end of __PINMUX_CONFIG_H__

177
freertos/cvitek/install/include/driver/rgn/cmpr_canvas.h Normal file
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#ifndef __CMPR_CANVAS__
#define __CMPR_CANVAS__
#include <float.h>
#include <string.h>
#include <math.h>
#include "osd_cmpr.h"
#include "cvi_list.h"
#define BUF_GUARD_SIZE (1 << 12)
#define OSDEC_RL_BD (6)
#define OSDEC_PAL_BD (3)
#define OSDEC_MAX_RL (1 << OSDEC_RL_BD)
#define MIN_THICKNESS (1)
#define MAX_THICKNESS (32)
#define BG_COLOR_CODE (2)
#define CMPR_CANVAS_DBG (0)
typedef enum {
RECT = 0,
STROKE_RECT,
BIT_MAP,
LINE,
CMPR_BIT_MAP,
NUM_OF_DRAW_OBJ
} DRAW_OBJ_TYPE;
typedef struct {
int width;
int height;
OSD_FORMAT format;
uint32_t bg_color_code;
} Canvas_Attr;
typedef union _COLOR {
uint32_t code;
uint8_t *buf;
} COLOR;
typedef struct {
int x0; // start position
int x1; // end position
uint16_t obj_id;
} OBJ_SLICE;
typedef struct {
OBJ_SLICE slice;
int num;
dlist_t item;
} SLICE_LIST;
typedef struct {
bool is_const;
bool is_cmpr;
uint16_t width;
union {
uint32_t stride;
uint16_t *bs_len;
};
COLOR color;
uint16_t id;
} SEGMENT;
typedef struct {
SEGMENT segment;
int num;
dlist_t item;
} SEGMENT_LIST;
typedef struct {
int x;
int y;
int width;
int height;
int thickness;
} RECT_ATTR;
typedef struct {
RECT_ATTR rect;
union {
uint32_t stride;
uint32_t bs_offset;
};
} BITMAP_ATTR;
typedef struct {
float _mx; // slope of two end-point vector
float _bx[2];
float _by[2];
float _ex[2];
float _ey[2];
float ts_h; // thickness proj. on horizontal slice
} LINE_ATTR;
typedef struct {
DRAW_OBJ_TYPE type;
union {
RECT_ATTR rect;
LINE_ATTR line;
BITMAP_ATTR bitmap;
};
COLOR color;
int _max_y;
int _min_y;
} DRAW_OBJ;
typedef struct {
OSDCmpr_Ctrl osdCmpr_ctrl;
StreamBuffer bitstream;
RGBA last_color;
int rl_cnt;
MODE_TYPE md;
CODE code;
} Cmpr_Canvas_Ctrl;
uint32_t est_cmpr_canvas_size(Canvas_Attr *canvas, DRAW_OBJ *objs, uint32_t obj_num);
int draw_cmpr_canvas(Canvas_Attr *canvas, DRAW_OBJ *objs, uint32_t obj_num,
uint8_t *obuf, int buf_size, uint32_t *p_osize);
void set_rect_obj_attr(DRAW_OBJ *obj, Canvas_Attr *canvas, uint32_t color_code,
int pt_x, int pt_y, int width, int height,
bool is_filled, int thickness);
void set_bitmap_obj_attr(DRAW_OBJ *obj_attr, Canvas_Attr *canvas, uint8_t *buf,
int pt_x, int pt_y, int width, int height,
bool is_cmpr);
void set_line_obj_attr(DRAW_OBJ *obj, Canvas_Attr *canvas, uint32_t color_code,
int pt_x0, int pt_y0, int pt_x1, int pt_y1,
int thickness);
int cmpr_bitmap(Canvas_Attr *canvas, uint8_t *ibuf, uint8_t *obuf, int width,
int height, int buf_size, uint32_t *p_osize);
#if (CMPR_CANVAS_DBG)
int draw_canvas_raw_buffer(Canvas_Attr *canvas, DRAW_OBJ *obj_vec,
uint8_t *obuf);
int draw_canvas_raw_buffer2(Canvas_Attr *canvas, DRAW_OBJ *obj_vec,
uint8_t *obuf);
#endif
//==============================================================================================
//CVI interface
#ifdef __cplusplus
extern "C"
{
#endif
uint32_t CVI_OSDC_est_cmpr_canvas_size(Canvas_Attr *canvas, DRAW_OBJ *objs, uint32_t obj_num);
int CVI_OSDC_draw_cmpr_canvas(Canvas_Attr *canvas, DRAW_OBJ *objs, uint32_t obj_num,
uint8_t *obuf, uint32_t buf_size, uint32_t *p_osize);
void CVI_OSDC_set_rect_obj_attr(Canvas_Attr *canvas, DRAW_OBJ *obj, uint32_t color_code,
int pt_x, int pt_y, int width, int height, bool is_filled, int thickness);
void CVI_OSDC_set_bitmap_obj_attr(Canvas_Attr *canvas, DRAW_OBJ *obj_attr, uint8_t *buf,
int pt_x, int pt_y, int width, int height, bool is_cmpr);
void CVI_OSDC_set_line_obj_attr(Canvas_Attr *canvas, DRAW_OBJ *obj, uint32_t color_code,
int pt_x0, int pt_y0, int pt_x1, int pt_y1, int thickness);
int CVI_OSDC_cmpr_bitmap(Canvas_Attr *canvas, uint8_t *ibuf, uint8_t *obuf, int width, int height,
int buf_size, uint32_t *p_osize);
#if (CMPR_CANVAS_DBG)
int CVI_OSDC_draw_canvas_raw_buffer(Canvas_Attr *canvas, DRAW_OBJ *obj_vec, uint8_t *obuf);
int CVI_OSDC_draw_canvas_raw_buffer2(Canvas_Attr *canvas, DRAW_OBJ *obj_vec, uint8_t *obuf);
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CMPR_CANVAS__ */

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freertos/cvitek/install/include/driver/rgn/cvi_comm_osdc.h Normal file
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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: include/cvi_comm_osdc.h
* Description:
* The common data type defination for osdc module.
*/
#ifndef __CVI_COMM_OSDC_H__
#define __CVI_COMM_OSDC_H__
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
typedef enum _OSDC_OSD_FORMAT_E {
OSD_ARGB8888 = 0,
OSD_ARGB4444 = 4,
OSD_ARGB1555 = 5,
OSD_LUT8 = 8,
OSD_LUT4 = 10,
NUM_OF_FORMAT
} OSDC_OSD_FORMAT_E;
typedef enum _OSDC_DRAW_OBJ_TYPE_E {
RECT = 0,
STROKE_RECT,
BIT_MAP,
LINE,
CMPR_BIT_MAP,
NUM_OF_DRAW_OBJ
} OSDC_DRAW_OBJ_TYPE_E;
typedef struct _OSDC_Canvas_Attr_S {
int width;
int height;
OSDC_OSD_FORMAT_E format;
uint32_t bg_color_code;
} OSDC_Canvas_Attr_S;
typedef struct _OSDC_RECT_ATTR_S {
int x;
int y;
int width;
int height;
int thickness;
} OSDC_RECT_ATTR_S;
typedef struct _OSDC_LINE_ATTR_S {
float _mx; // slope of two end-point vector
float _bx[2];
float _by[2];
float _ex[2];
float _ey[2];
float ts_h; // thickness proj. on horizontal slice
} OSDC_LINE_ATTR_S;
typedef struct _OSDC_BITMAP_ATTR_S {
OSDC_RECT_ATTR_S rect;
union {
uint32_t stride;
uint32_t bs_offset;
};
} OSDC_BITMAP_ATTR_S;
typedef union _OSDC_COLOR_S {
uint32_t code;
uint8_t *buf;
} OSDC_COLOR_S;
typedef struct _OSDC_DRAW_OBJ_S {
OSDC_DRAW_OBJ_TYPE_E type;
union {
OSDC_RECT_ATTR_S rect;
OSDC_LINE_ATTR_S line;
OSDC_BITMAP_ATTR_S bitmap;
};
OSDC_COLOR_S color;
int _max_y;
int _min_y;
} OSDC_DRAW_OBJ_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __CVI_COMM_OSDC_H__ */

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freertos/cvitek/install/include/driver/rgn/cvi_osdc.h Normal file
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#ifndef __CVI_OSDC_H__
#define __CVI_OSDC_H__
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
#include <cvi_comm_osdc.h>
uint32_t CVI_OSDC_EstCmprCanvasSize(OSDC_Canvas_Attr_S * canvas, OSDC_DRAW_OBJ_S * objs, uint32_t obj_num);
int CVI_OSDC_DrawCmprCanvas(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *objs, uint32_t obj_num,
uint8_t *obuf, uint32_t buf_size, uint32_t *p_osize);
void CVI_OSDC_SetRectObjAttr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj, uint32_t color_code,
int pt_x, int pt_y, int width, int height, bool is_filled, int thickness);
void CVI_OSDC_SetBitmapObjAttr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj_attr, uint8_t *buf,
int pt_x, int pt_y, int width, int height, bool is_cmpr);
void CVI_OSDC_SetLineObjAttr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj, uint32_t color_code,
int pt_x0, int pt_y0, int pt_x1, int pt_y1, int thickness);
int CVI_OSDC_CmprBitmap(OSDC_Canvas_Attr_S *canvas, uint8_t *ibuf, uint8_t *obuf, int width, int height,
int buf_size, uint32_t *p_osize);
extern uint32_t CVI_OSDC_est_cmpr_canvas_size(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *objs, uint32_t obj_num);
extern int CVI_OSDC_draw_cmpr_canvas(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *objs, uint32_t obj_num,
uint8_t *obuf, uint32_t buf_size, uint32_t *p_osize);
extern void CVI_OSDC_set_rect_obj_attr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj, uint32_t color_code,
int pt_x, int pt_y, int width, int height, bool is_filled, int thickness);
extern void CVI_OSDC_set_bitmap_obj_attr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj_attr, uint8_t *buf,
int pt_x, int pt_y, int width, int height, bool is_cmpr);
extern void CVI_OSDC_set_line_obj_attr(OSDC_Canvas_Attr_S *canvas, OSDC_DRAW_OBJ_S *obj, uint32_t color_code,
int pt_x0, int pt_y0, int pt_x1, int pt_y1, int thickness);
extern int CVI_OSDC_cmpr_bitmap(OSDC_Canvas_Attr_S *canvas, uint8_t *ibuf, uint8_t *obuf, int width, int height,
int buf_size, uint32_t *p_osize);
#if (CMPR_CANVAS_DBG)
int CVI_OSDC_draw_canvas_raw_buffer(OSDC_Canvas_Attr_S *canvas, DRAW_OBJ *obj_vec, uint8_t *obuf);
int CVI_OSDC_draw_canvas_raw_buffer2(OSDC_Canvas_Attr_S *canvas, DRAW_OBJ *obj_vec, uint8_t *obuf);
#endif
#ifdef __cplusplus
}
#endif
#endif /*__CVI_OSDC_H__ */

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#ifndef __OSD_CMPR_H__
#define __OSD_CMPR_H__
#include <stdbool.h>
#include <stdint.h>
#include <sys/param.h>
// DataType-free color field copy
#define CPY_C(in, out) \
{ \
out.r = in.r; \
out.g = in.g; \
out.b = in.b; \
out.a = in.a; \
}
#define HDR_SZ (8)
typedef enum {
OSD_ARGB8888 = 0,
OSD_ARGB4444 = 4,
OSD_ARGB1555 = 5,
OSD_LUT8 = 8,
OSD_LUT4 = 10,
NUM_OF_FORMAT
} OSD_FORMAT;
typedef struct {
int img_width;
int img_height;
bool palette_mode_en;
bool zeroize_by_alpha;
int rgb_trunc_bit;
int alpha_trunc_bit;
int run_len_bd;
int palette_idx_bd;
OSD_FORMAT osd_format;
bool hdr_en;
} OSDCmpr_Cfg;
typedef struct {
uint8_t *stream; // stream buffer pointer
int bit_pos; // current pointer (in bit)
int buf_size; // in byte
int status;
} StreamBuffer;
int clip(int data, int min, int max);
void init_stream(StreamBuffer *bs, const uint8_t *buf, int buf_size,
bool read_only);
void write_stream(StreamBuffer *bs, uint8_t *src, int bit_len);
void parse_stream(StreamBuffer *bs, uint8_t *dest, int bit_len, bool read_only);
void move_stream_ptr(StreamBuffer *bs, int bit_len);
uint8_t get_bit_val(uint8_t *buf, int byte_idx, int bit_idx);
typedef union {
struct {
uint8_t g;
uint8_t b;
uint8_t r;
uint8_t a;
};
uint32_t code;
} RGBA;
typedef union {
struct {
uint16_t g : 4;
uint16_t b : 4;
uint16_t r : 4;
uint16_t a : 4;
};
uint16_t code;
} ARGB4444;
typedef union {
struct {
uint16_t g : 5;
uint16_t b : 5;
uint16_t r : 5;
uint16_t a : 1;
};
uint16_t code;
} ARGB1555;
typedef union {
RGBA color;
int palette_idx;
} CODE;
typedef enum {
Literal = 0,
Palette,
Literal_RL,
Palette_RL,
NUM_OF_MODE
} MODE_TYPE;
typedef struct {
RGBA *color;
int num;
} PaletteRGBA;
typedef struct {
int reg_image_width;
int reg_image_height;
bool reg_zeroize_by_alpha;
int reg_rgb_trunc_bit;
int reg_alpha_trunc_bit;
bool reg_palette_mode_en;
int reg_run_len_bd;
int reg_palette_idx_bd;
OSD_FORMAT reg_osd_format;
int pel_sz;
PaletteRGBA palette_cache;
int bs_buf_size;
uint8_t *bsbuf; // intermediate bitstream buffer
} OSDCmpr_Ctrl;
// RGBA get_color(uint8_t *ptr, OSD_FORMAT format = OSD_ARGB8888);
// void set_color(uint8_t *ptr, RGBA color, OSD_FORMAT format = OSD_ARGB8888);
RGBA get_color(uint8_t *ptr, OSD_FORMAT format);
void set_color(uint8_t *ptr, RGBA color, OSD_FORMAT format);
void osd_cmpr_frame_init(OSDCmpr_Ctrl *p_ctrl);
int osd_cmpr_enc_one_frame(uint8_t *ibuf, uint8_t *obs, OSDCmpr_Ctrl *p_ctrl);
void osd_cmpr_dec_one_frame(uint8_t *bsbuf, size_t bs_size, uint8_t *obuf,
OSDCmpr_Ctrl *p_ctrl);
void osd_cmpr_enc_header(uint8_t *hdrbuf, OSDCmpr_Ctrl *p_ctrl);
void osd_cmpr_dec_header(uint8_t *hdrbuf, OSDCmpr_Ctrl *p_ctrl);
void osd_cmpr_setup(OSDCmpr_Ctrl *p_ctrl, OSDCmpr_Cfg *p_cfg);
void osd_cmpr_enc_const_pixel(RGBA cur_c, RGBA *last_c, int *rl_cnt,
MODE_TYPE *md, CODE *code, uint16_t *length,
bool is_force_new_run, uint16_t max_run_len,
OSDCmpr_Ctrl *p_ctrl, StreamBuffer *bitstream);
void osd_cmpr_enc_followed_run(RGBA cur_c, int *rl_cnt, MODE_TYPE *md,
CODE *code, uint16_t *length, uint16_t max_run_len,
OSDCmpr_Ctrl *p_ctrl, StreamBuffer *bitstream);
size_t osd_cmpr_get_pixel_sz(OSD_FORMAT format);
size_t osd_cmpr_get_bs_buf_max_sz(int pel_num, int pel_sz);
size_t osd_cmpr_get_header_sz(void);
void osd_cmpr_debug_frame_compare(OSDCmpr_Ctrl *p_ctrl, uint8_t *buf0,
uint8_t *buf1);
void palette_cache_init(PaletteRGBA *cache, int cache_sz);
int palette_cache_lookup_color(PaletteRGBA *cache, RGBA color);
void palette_cache_lru_update(PaletteRGBA *cache, int index);
void palette_cache_push_color(PaletteRGBA *cache, RGBA color);
#endif /* __OSD_CMPR_H__ */

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#ifndef __RTOS_COMMAND_QUEUE__
#define __RTOS_COMMAND_QUEUE__
#ifdef __linux__
#include <linux/kernel.h>
#endif
#define NR_SYSTEM_CMD 20
#define NR_RTOS_CMD 127
#define NR_RTOS_IP IP_LIMIT
enum IP_TYPE {
IP_ISP = 0,
IP_VCODEC,
IP_VIP,
IP_VI,
IP_RGN,
IP_AUDIO,
IP_SYSTEM,
IP_CAMERA,
IP_LIMIT,
};
enum SYS_CMD_ID {
SYS_CMD_INFO_TRANS = 0x50,
SYS_CMD_INFO_LINUX_INIT_DONE,
SYS_CMD_INFO_RTOS_INIT_DONE,
SYS_CMD_INFO_STOP_ISR,
SYS_CMD_INFO_STOP_ISR_DONE,
SYS_CMD_INFO_LINUX,
SYS_CMD_INFO_RTOS,
SYS_CMD_SYNC_TIME,
SYS_CMD_INFO_DUMP_MSG,
SYS_CMD_INFO_DUMP_EN,
SYS_CMD_INFO_DUMP_DIS,
SYS_CMD_INFO_DUMP_JPG,
SYS_CMD_INFO_TRACE_SNAPSHOT_START,
SYS_CMD_INFO_TRACE_SNAPSHOT_STOP,
SYS_CMD_INFO_TRACE_STREAM_START,
SYS_CMD_INFO_TRACE_STREAM_STOP,
SYS_CMD_INFO_LIMIT,
};
struct valid_t {
unsigned char linux_valid;
unsigned char rtos_valid;
} __attribute__((packed));
typedef union resv_t {
struct valid_t valid;
unsigned short mstime; // 0 : noblock, -1 : block infinite
} resv_t;
typedef struct cmdqu_t cmdqu_t;
/* cmdqu size should be 8 bytes because of mailbox buffer size */
struct cmdqu_t {
unsigned char ip_id;
unsigned char cmd_id : 7;
unsigned char block : 1;
union resv_t resv;
unsigned int param_ptr;
} __attribute__((packed)) __attribute__((aligned(0x8)));
#ifdef __linux__
/* keep those commands for ioctl system used */
enum SYSTEM_CMD_TYPE {
CMDQU_SEND = 1,
CMDQU_REQUEST,
CMDQU_REQUEST_FREE,
CMDQU_SEND_WAIT,
CMDQU_SEND_WAKEUP,
CMDQU_SYSTEM_LIMIT = NR_SYSTEM_CMD,
};
#define RTOS_CMDQU_DEV_NAME "cvi-rtos-cmdqu"
#define RTOS_CMDQU_SEND _IOW('r', CMDQU_SEND, unsigned long)
#define RTOS_CMDQU_REQUEST _IOW('r', CMDQU_REQUEST, unsigned long)
#define RTOS_CMDQU_REQUEST_FREE _IOW('r', CMDQU_REQUEST_FREE, unsigned long)
#define RTOS_CMDQU_SEND_WAIT _IOW('r', CMDQU_SEND_WAIT, unsigned long)
#define RTOS_CMDQU_SEND_WAKEUP _IOW('r', CMDQU_SEND_WAKEUP, unsigned long)
int rtos_cmdqu_send(cmdqu_t *cmdq);
int rtos_cmdqu_send_wait(cmdqu_t *cmdq, int wait_cmd_id);
int request_rtos_irq(unsigned char ip_id, void *handler, const char *devname, void *dev_id);
int free_rtos_irq(unsigned char ip_id);
#endif // end of __linux__
#endif // end of __RTOS_COMMAND_QUEUE__

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#ifndef __SENSOR_GAIN_TABLE_H__
#define __SENSOR_GAIN_TABLE_H__
extern const uint32_t imx327_gain_table[];
#endif // __SENSOR_GAIN_TABLE_H__

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#ifndef __CV_IMAGE_SENSOR_H__
#define __CV_IMAGE_SENSOR_H__
#include <delay.h>
#include "cvi_comm_video.h"
#include "cvi_common.h"
#include "cvi_comm_vi.h"
#include "cvi_comm_isp.h"
#include "cvi_sns_ctrl.h"
#include "cif_uapi.h"
#include "gpio.h"
#include "sample_comm.h"
#define TPU_SRAM_BASE_ADDR (0x0C020000)
#define TPU_SRAM_BASE_SIZE (0x00010000)
#define RTC_SRAM_BASE_ADDR (0x05200000)
#define RTC_SRAM_BASE_SIZE (24 << 10) // 24KB
//#define SENSOR_USE_I2C_DMA 0
#define CHECK_SENSOR_ID 1
#define SEN_CFG_ADDR (RTC_SRAM_BASE_SIZE - 1024)
#define SEN_CFG_INI_ADDR (RTC_SRAM_BASE_SIZE - 1024)
#define SYSDMA_LLP_ADDR (RTC_SRAM_BASE_SIZE - 1024)
#define SEN_ITB_START_ADDR (RTC_SRAM_BASE_SIZE - 1024)
#define SEN_MAX_LANE_NUM (MIPI_LANE_NUM + 1) // 1C4D
#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))
#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a))
/* Sensor resolutions */
#define SENSOR_RES_IS_2160P(w, h) ((w) <= 3840 && (h) <= 2160)
#define SENSOR_RES_IS_1440P(w, h) ((w) <= 2560 && (h) <= 1440)
#define SENSOR_RES_IS_1080P(w, h) ((w) <= 1920 && (h) <= 1080)
#define SENSOR_RES_IS_720P(w, h) ((w) <= 1280 && (h) <= 720)
#define delay_ms(a) mdelay(a)
enum HDR_EXPOSURE_FRAME_ID {
SHORT_EXP_ID,
LONG_EXP_ID,
};
enum IMAGE_FORMAT_E {
BAYER_RAW12 = 0,
BAYER_RAW10,
BAYER_RAW8,
BAYER_FORMAT_NUM,
YUV422_8B = BAYER_FORMAT_NUM,
YUV422_10B,
};
/*
* To indicate the 1st two pixel in the bayer_raw.
*/
enum DPHY_LANE_NUM {
DPHY_1_DLANE = 0,
DPHY_2_DLANE = 1,
DPHY_4_DLANE = 3,
DPHY_8_DLANE = 7
};
enum HDR_MODE_E {
HDR_MODE_VC, // CSI
HDR_MODE_ID, // CSI
HDR_MODE_DT, // CSI
HDR_MODE_DOL, // CSI
HDR_MODE_PAT1, // SLVDS
HDR_MODE_PAT2, // SLVDS
HDR_MODE_LINEAR = 0xF
};
enum ISP_BAYER_TYPE {
ISP_BAYER_TYPE_BG = 0,
ISP_BAYER_TYPE_GB,
ISP_BAYER_TYPE_GR,
ISP_BAYER_TYPE_RG,
// ISP_BAYER_TYPE_MAX,
};
typedef struct _ISP_HDR_SIZE_S {
RECT_S stWndRect;
SIZE_S stSnsSize;
// SIZE_S stMaxSize;
} ISP_HDR_SIZE_S;
typedef struct _SIMPLE_AE_CTRL_S {
uint32_t seLuma;
uint32_t seExp;
uint32_t seGain;
uint32_t leLuma;
uint32_t leExp;
uint32_t leGain;
uint16_t rWb_Gain;
uint16_t bWb_Gain;
} SIMPLE_AE_CTRL_S;
/* define of Linux
typedef struct _SAMPLE_SENSOR_INFO_S {
SAMPLE_SNS_TYPE_E enSnsType;
CVI_S32 s32SnsId;
CVI_S32 s32BusId;
CVI_S32 s32SnsI2cAddr;
combo_dev_t MipiDev;
CVI_S16 as16LaneId[5];
CVI_S8 as8PNSwap[5];
CVI_U8 u8HwSync;
SAMPLE_SENSOR_MCLK_ATTR_S stMclkAttr;
CVI_U8 u8Orien; // 0: normal, 1: mirror, 2: flip, 3: mirror and flip.
} SAMPLE_SENSOR_INFO_S;
*/
typedef struct _SENSOR_CFG_INI_HEADER {
uint32_t magic_num; // date for check
uint16_t dev_num; // totla sensor number
uint16_t cfg_ofs; // sizeof SENSOR_USR_CFG
} __attribute__((packed)) __attribute__((aligned(0x8))) SENSOR_CFG_INI_HEADER;
typedef struct _SENSOR_USR_CFG_INI {
char name[64]; // sensor name
uint8_t devno; // support 0:sensor0, 1:sensor1, 2: sensor2
uint8_t mclk_en; // enable of mclk (0: driver default, 1: mclk0 enable, 2:maclk1 enable)
uint8_t mclk; // mclk clock
// i2c info
int8_t slave_id; // slave id (slave addr[7:1]) 0: use default
int8_t bus_id; // i2c bus id
// lane info
uint8_t mipi_dev; // MIPI phy number,
uint8_t hs_settle; // 0: use default
int8_t lane_id[SEN_MAX_LANE_NUM]; // {clk, d0 ,d1, d2, d3}
int8_t pn_swap[SEN_MAX_LANE_NUM]; // {clk, d0 ,d1, d2, d3}
uint8_t u8HwSync;
uint8_t u8Orien; // 0: normal, 1: mirror, 2: flip, 3: mirror and flip.
// reset-pin info
uint32_t snsr_reset; // sensor reset pin
uint8_t reset_act; // sensor reset low/high act fill by sensor driver
uint32_t reset_delay; // delay us after reset
} __attribute__((packed)) __attribute__((aligned(0x8))) SENSOR_USR_CFG;
typedef struct _SENSOR_INFO {
SENSOR_CFG_INI_HEADER *header;
SENSOR_USR_CFG *cfg; // load from flash
ISP_SNS_OBJ_S *pstSnsObj;
enum input_mode_e vi_mode; // fill by sensor name
enum IMAGE_FORMAT_E format; // fill by sensor driver
enum ISP_BAYER_TYPE bayer_type; // fill by sensor driver
enum HDR_MODE_E hdr_mode; // fill by sensor name
VI_WORK_MODE_E chn; // fill by sensor name
enum DPHY_LANE_NUM lane_num; // fill by sensor name
uint32_t width; // output width fill by sensor name
uint32_t height; // output height fill by sensor name
uint8_t init_ok; // sensor init success
} SENSOR_INFO;
/*
* Support Sensor Objects
*/
// extern ISP_SNS_OBJ_S stSnsImx327_Obj;
extern const char *snsr_type_name[SAMPLE_SNS_TYPE_BUTT];
/*
* Sensor I2C API
*/
int sensor_i2c_init(VI_PIPE ViPipe, uint8_t u8I2cDev, uint16_t speed,
uint8_t slave_addr, uint8_t alen, uint8_t dlen);
int sensor_i2c_exit(VI_PIPE ViPipe);
int sensor_read_register(VI_PIPE ViPipe, int addr);
int sensor_write_register(VI_PIPE ViPipe, int addr, int data);
/*
* Sensor API
*/
extern int32_t cmos_set_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo);
#endif //__CV_IMAGE_SENSOR_H__

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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DRV_SPINLOCK_H__
#define __DRV_SPINLOCK_H__
enum SPINLOCK_FIELD {
SPIN_UART,
SPIN_LINUX_RTOS = 4, // this spinlock field is used for linux & rtos
SPIN_MBOX = SPIN_LINUX_RTOS,
SPIN_MAX = 7,
};
typedef struct hw_raw_spinlock {
unsigned short locks;
unsigned short hw_field;
} hw_raw_spinlock_t;
#define MAILBOX_LOCK_SUCCESS 1
#define MAILBOX_LOCK_FAILED (-1)
#define __CVI_ARCH_SPIN_LOCK_UNLOCKED { 0 }
#define __CVI_RAW_SPIN_LOCK_INITIALIZER(spinlock_hw_field) \
{ \
.locks = __CVI_ARCH_SPIN_LOCK_UNLOCKED, \
.hw_field = spinlock_hw_field, \
}
#define DEFINE_CVI_SPINLOCK(x, y) hw_raw_spinlock_t x = __CVI_RAW_SPIN_LOCK_INITIALIZER(y)
int _hw_raw_spin_lock_irqsave(hw_raw_spinlock_t *lock);
void _hw_raw_spin_unlock_irqrestore(hw_raw_spinlock_t *lock, int flag);
#define drv_spin_lock_irqsave(lock, flags) \
{ flags = _hw_raw_spin_lock_irqsave(lock); }
#define drv_spin_unlock_irqrestore(lock, flags) \
_hw_raw_spin_unlock_irqrestore(lock, flags)
void spinlock_base(unsigned long mb_base);
void cvi_spinlock_init(void);
#endif // end of __DRV_SPINLOCK_H__

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#ifndef __DUMP_UART_H__
#define __DUMP_UART_H__
#define DUMP_PRINT_DEFAULT_SIZE 0x1000
/* this structure should be modified both freertos & osdrv side */
struct dump_uart_s {
uint64_t dump_uart_ptr;
unsigned int dump_uart_max_size;
unsigned int dump_uart_pos;
unsigned char dump_uart_enable;
unsigned char dump_uart_overflow;
} __attribute__((packed));
#ifndef __linux__
/* used for freertos */
struct dump_uart_s *dump_uart_init(void);
struct dump_uart_s *dump_uart_msg(void);
void dump_uart_enable(void);
void dump_uart_disable(void);
#endif
#endif // end of __DUMP_UART_H__

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#ifndef _UART_H_
#define _UART_H_
#ifdef __riscv
#include <stdint.h>
#else
#include "linux/types.h"
#endif
void uart_init(void);
int uart_getc(void);
int uart_tstc(void);
uint8_t uart_putc(uint8_t ch);
void uart_puts(char *str);
int uart_put_buff(char *buf);
#endif

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#ifndef __CVI_VI_H__
#define __CVI_VI_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
#include <cvi_comm_vi.h>
CVI_S32 CVI_VI_SetDevAttr(VI_DEV ViDev, const VI_DEV_ATTR_S *pstDevAttr);
CVI_S32 CVI_VI_Start(CVI_U32 addr, CVI_U32 size);
CVI_S32 CVI_VI_Stop(CVI_VOID);
CVI_VOID CVI_VI_UT_MAIN(CVI_U32 addr, CVI_U32 size);
QueueHandle_t CVI_VI_GetQueHandle(CVI_VOID);
CVI_VOID CVI_VI_QBUF(CVI_VOID);
#ifdef __cplusplus
}
#endif
#endif /* __CVI_VI_H__ */

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freertos/cvitek/install/include/driver/vi/cvi_vi_ctx.h Normal file
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#ifndef __CVI_VI_CTX_H__
#define __CVI_VI_CTX_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <cvi_defines.h>
#include <cvi_comm_vi.h>
struct cvi_vi_ctx {
CVI_U8 total_chn_num;
CVI_U8 total_dev_num;
CVI_BOOL is_enable[VI_MAX_CHN_NUM];
CVI_BOOL isDevEnable[VI_MAX_DEV_NUM];
CVI_BOOL isTile;
// dev
VI_DEV_ATTR_S devAttr[VI_MAX_DEV_NUM];
// chn
VI_CHN_STATUS_S chnStatus[VI_MAX_CHN_NUM];
CVI_U32 blk_size[VI_MAX_CHN_NUM];
CVI_U32 timeout_cnt;
CVI_U8 bypass_frm[VI_MAX_CHN_NUM];
CVI_U32 vi_mem_base;
CVI_U32 vi_mem_size;
};
#ifdef __cplusplus
}
#endif
#endif /* __CVI_VI_CTX_H__ */

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#ifndef _ISP_REG_H_
#define _ISP_REG_H_
#include "vi_reg_fields.h"
#include "vi_reg_blocks.h"
#define FPGA_TEST
/* ISP BLOCK ADDR OFFSET DEFINE */
#define ISP_BLK_BA_PRE_RAW_FE0 (0x00000000)
#define ISP_BLK_BA_CSIBDG0 (0x00000800)
#define ISP_BLK_BA_DMA_CTL6 (0x00000B00)
#define ISP_BLK_BA_DMA_CTL7 (0x00000C00)
#define ISP_BLK_BA_DMA_CTL8 (0x00000D00)
#define ISP_BLK_BA_DMA_CTL9 (0x00000E00)
#define ISP_BLK_BA_BLC0 (0x00001000)
#define ISP_BLK_BA_BLC1 (0x00001800)
#define ISP_BLK_BA_RGBMAP0 (0x00002000)
#define ISP_BLK_BA_WBG2 (0x00002100)
#define ISP_BLK_BA_DMA_CTL10 (0x00002200)
#define ISP_BLK_BA_RGBMAP1 (0x00002300)
#define ISP_BLK_BA_WBG3 (0x00002400)
#define ISP_BLK_BA_DMA_CTL11 (0x00002500)
#define ISP_BLK_BA_PRE_RAW_FE1 (0x00008000)
#define ISP_BLK_BA_CSIBDG1 (0x00008800)
#define ISP_BLK_BA_DMA_CTL12 (0x00008B00)
#define ISP_BLK_BA_DMA_CTL13 (0x00008C00)
#define ISP_BLK_BA_DMA_CTL14 (0x00008D00)
#define ISP_BLK_BA_DMA_CTL15 (0x00008E00)
#define ISP_BLK_BA_BLC2 (0x00009000)
#define ISP_BLK_BA_BLC3 (0x00009800)
#define ISP_BLK_BA_RGBMAP2 (0x0000A000)
#define ISP_BLK_BA_WBG4 (0x0000A100)
#define ISP_BLK_BA_DMA_CTL16 (0x0000A200)
#define ISP_BLK_BA_RGBMAP3 (0x0000A300)
#define ISP_BLK_BA_WBG5 (0x0000A400)
#define ISP_BLK_BA_DMA_CTL17 (0x0000A500)
#define ISP_BLK_BA_PRE_RAW_FE2 (0x00010000)
#define ISP_BLK_BA_CSIBDG2 (0x00010800)
#define ISP_BLK_BA_DMA_CTL18 (0x00010B00)
#define ISP_BLK_BA_DMA_CTL19 (0x00010C00)
#define ISP_BLK_BA_BLC4 (0x00011000)
#define ISP_BLK_BA_RGBMAP4 (0x00012000)
#define ISP_BLK_BA_WBG6 (0x00012100)
#define ISP_BLK_BA_DMA_CTL20 (0x00012200)
#define ISP_BLK_BA_PRE_RAW_BE (0x00018000)
#define ISP_BLK_BA_CROP0 (0x00018800)
#define ISP_BLK_BA_CROP1 (0x00019000)
#define ISP_BLK_BA_BLC5 (0x00019800)
#define ISP_BLK_BA_BLC6 (0x0001A000)
#define ISP_BLK_BA_AF (0x0001A800)
#define ISP_BLK_BA_DMA_CTL21 (0x0001AA00)
#define ISP_BLK_BA_DPC0 (0x0001B000)
#define ISP_BLK_BA_DPC1 (0x0001B100)
#define ISP_BLK_BA_DMA_CTL22 (0x0001B800)
#define ISP_BLK_BA_DMA_CTL23 (0x0001B880)
#define ISP_BLK_BA_PRE_WDMA (0x0001B900)
#define ISP_BLK_BA_PCHK0 (0x0001C000)
#define ISP_BLK_BA_PCHK1 (0x0001C800)
#define ISP_BLK_BA_RAWTOP (0x00030000)
#define ISP_BLK_BA_CFA (0x00031000)
#define ISP_BLK_BA_LSC (0x00032000)
#define ISP_BLK_BA_DMA_CTL24 (0x00032100)
#define ISP_BLK_BA_GMS (0x00033000)
#define ISP_BLK_BA_DMA_CTL25 (0x00033100)
#define ISP_BLK_BA_AEHIST0 (0x00034000)
#define ISP_BLK_BA_DMA_CTL26 (0x00034400)
#define ISP_BLK_BA_AEHIST1 (0x00035000)
#define ISP_BLK_BA_DMA_CTL27 (0x00035400)
#define ISP_BLK_BA_DMA_CTL28 (0x00036000)
#define ISP_BLK_BA_DMA_CTL29 (0x00036080)
#define ISP_BLK_BA_RAW_RDMA (0x00036100)
#define ISP_BLK_BA_BNR (0x0003C000)
#define ISP_BLK_BA_CROP2 (0x0003D000)
#define ISP_BLK_BA_CROP3 (0x0003E000)
#define ISP_BLK_BA_LMAP0 (0x0003F000)
#define ISP_BLK_BA_DMA_CTL30 (0x0003F100)
#define ISP_BLK_BA_LMAP1 (0x0003F200)
#define ISP_BLK_BA_DMA_CTL31 (0x0003F300)
#define ISP_BLK_BA_WBG0 (0x00040000)
#define ISP_BLK_BA_WBG1 (0x00041000)
#define ISP_BLK_BA_PCHK2 (0x00042000)
#define ISP_BLK_BA_PCHK3 (0x00043000)
#define ISP_BLK_BA_LCAC (0x00044000)
#define ISP_BLK_BA_RGBCAC (0x00045000)
#define ISP_BLK_BA_RGBTOP (0x00050000)
#define ISP_BLK_BA_CCM0 (0x00052000)
#define ISP_BLK_BA_CCM1 (0x00052100)
#define ISP_BLK_BA_RGBGAMMA (0x00052200)
#define ISP_BLK_BA_YGAMMA (0x00052300)
#define ISP_BLK_BA_MMAP (0x00053000)
#define ISP_BLK_BA_DMA_CTL32 (0x00053200)
#define ISP_BLK_BA_DMA_CTL33 (0x00053300)
#define ISP_BLK_BA_DMA_CTL34 (0x00053400)
#define ISP_BLK_BA_DMA_CTL35 (0x00053500)
#define ISP_BLK_BA_DMA_CTL36 (0x00053600)
#define ISP_BLK_BA_DMA_CTL37 (0x00053700)
#define ISP_BLK_BA_CLUT (0x00054000)
#define ISP_BLK_BA_DHZ (0x00055000)
#define ISP_BLK_BA_CSC (0x00056000)
#define ISP_BLK_BA_RGBDITHER (0x00057000)
#define ISP_BLK_BA_PCHK4 (0x00059000)
#define ISP_BLK_BA_PCHK5 (0x0005A000)
#define ISP_BLK_BA_HIST_V (0x0005C000)
#define ISP_BLK_BA_DMA_CTL38 (0x0005C100)
#define ISP_BLK_BA_HDRFUSION (0x0005D000)
#define ISP_BLK_BA_HDRLTM (0x0005E000)
#define ISP_BLK_BA_DMA_CTL39 (0x0005E100)
#define ISP_BLK_BA_DMA_CTL40 (0x0005E200)
#define ISP_BLK_BA_YUVTOP (0x00060000)
#define ISP_BLK_BA_TNR (0x00061000)
#define ISP_BLK_BA_DMA_CTL41 (0x00061800)
#define ISP_BLK_BA_DMA_CTL42 (0x00061900)
#define ISP_BLK_BA_FBCE (0x00061A00)
#define ISP_BLK_BA_DMA_CTL43 (0x00061B00)
#define ISP_BLK_BA_DMA_CTL44 (0x00061C00)
#define ISP_BLK_BA_FBCD (0x00061D00)
#define ISP_BLK_BA_YUVDITHER (0x00061E00)
#define ISP_BLK_BA_CA (0x00062000)
#define ISP_BLK_BA_CA_LITE (0x00063000)
#define ISP_BLK_BA_YNR (0x00064000)
#define ISP_BLK_BA_CNR (0x00065000)
#define ISP_BLK_BA_EE (0x00066000)
#define ISP_BLK_BA_YCURVE (0x00067000)
#define ISP_BLK_BA_DCI (0x00068000)
#define ISP_BLK_BA_DMA_CTL45 (0x00068100)
#define ISP_BLK_BA_DCI_GAMMA (0x00068200)
#define ISP_BLK_BA_CROP4 (0x00069000)
#define ISP_BLK_BA_DMA_CTL46 (0x00069100)
#define ISP_BLK_BA_CROP5 (0x0006A000)
#define ISP_BLK_BA_DMA_CTL47 (0x0006A100)
#define ISP_BLK_BA_LDCI (0x0006B000)
#define ISP_BLK_BA_DMA_CTL48 (0x0006B300)
#define ISP_BLK_BA_DMA_CTL49 (0x0006B400)
#define ISP_BLK_BA_PRE_EE (0x0006C000)
#define ISP_BLK_BA_PCHK6 (0x0006D000)
#define ISP_BLK_BA_PCHK7 (0x0006E000)
#define ISP_BLK_BA_ISPTOP (0x00070000)
#define ISP_BLK_BA_WDMA_CORE0 (0x00072000)
#define ISP_BLK_BA_RDMA_CORE (0x00074000)
#define ISP_BLK_BA_CSIBDG_LITE (0x00076000)
#define ISP_BLK_BA_DMA_CTL0 (0x00076200)
#define ISP_BLK_BA_DMA_CTL1 (0x00076300)
#define ISP_BLK_BA_DMA_CTL2 (0x00076400)
#define ISP_BLK_BA_DMA_CTL3 (0x00076500)
#define ISP_BLK_BA_WDMA_CORE1 (0x00078000)
#define ISP_BLK_BA_PRE_RAW_VI_SEL (0x0007F400)
#define ISP_BLK_BA_DMA_CTL4 (0x0007F500)
#define ISP_BLK_BA_DMA_CTL5 (0x0007F600)
#define ISP_BLK_BA_CMDQ (0x0007FC00)
enum ISP_BLK_ID_T {
ISP_BLK_ID_PRE_RAW_FE0,
ISP_BLK_ID_CSIBDG0,
ISP_BLK_ID_DMA_CTL6,
ISP_BLK_ID_DMA_CTL7,
ISP_BLK_ID_DMA_CTL8,
ISP_BLK_ID_DMA_CTL9,
ISP_BLK_ID_BLC0,
ISP_BLK_ID_BLC1,
ISP_BLK_ID_RGBMAP0,
ISP_BLK_ID_WBG2,
ISP_BLK_ID_DMA_CTL10, //10
ISP_BLK_ID_RGBMAP1,
ISP_BLK_ID_WBG3,
ISP_BLK_ID_DMA_CTL11, //13
ISP_BLK_ID_PRE_RAW_FE1,
ISP_BLK_ID_CSIBDG1,
ISP_BLK_ID_DMA_CTL12,
ISP_BLK_ID_DMA_CTL13,
ISP_BLK_ID_DMA_CTL14,
ISP_BLK_ID_DMA_CTL15,
ISP_BLK_ID_BLC2,
ISP_BLK_ID_BLC3,
ISP_BLK_ID_RGBMAP2,
ISP_BLK_ID_WBG4,
ISP_BLK_ID_DMA_CTL16,
ISP_BLK_ID_RGBMAP3,
ISP_BLK_ID_WBG5,
ISP_BLK_ID_DMA_CTL17,
ISP_BLK_ID_PRE_RAW_FE2,
ISP_BLK_ID_CSIBDG2,
ISP_BLK_ID_DMA_CTL18,
ISP_BLK_ID_DMA_CTL19,
ISP_BLK_ID_BLC4,
ISP_BLK_ID_RGBMAP4,
ISP_BLK_ID_WBG6,
ISP_BLK_ID_DMA_CTL20,
ISP_BLK_ID_PRE_RAW_BE,
ISP_BLK_ID_CROP0,
ISP_BLK_ID_CROP1,
ISP_BLK_ID_BLC5,
ISP_BLK_ID_BLC6,
ISP_BLK_ID_AF,
ISP_BLK_ID_DMA_CTL21,
ISP_BLK_ID_DPC0,
ISP_BLK_ID_DPC1,
ISP_BLK_ID_DMA_CTL22, //45
ISP_BLK_ID_DMA_CTL23, //46
ISP_BLK_ID_PRE_WDMA,
ISP_BLK_ID_PCHK0,
ISP_BLK_ID_PCHK1,
ISP_BLK_ID_RAWTOP,
ISP_BLK_ID_CFA,
ISP_BLK_ID_LSC,
ISP_BLK_ID_DMA_CTL24, //53
ISP_BLK_ID_GMS,
ISP_BLK_ID_DMA_CTL25, //55
ISP_BLK_ID_AEHIST0,
ISP_BLK_ID_DMA_CTL26, //57
ISP_BLK_ID_AEHIST1,
ISP_BLK_ID_DMA_CTL27, //59
ISP_BLK_ID_DMA_CTL28,
ISP_BLK_ID_DMA_CTL29,
ISP_BLK_ID_RAW_RDMA,
ISP_BLK_ID_BNR,
ISP_BLK_ID_CROP2,
ISP_BLK_ID_CROP3,
ISP_BLK_ID_LMAP0,
ISP_BLK_ID_DMA_CTL30, //67
ISP_BLK_ID_LMAP1,
ISP_BLK_ID_DMA_CTL31,
ISP_BLK_ID_WBG0,
ISP_BLK_ID_WBG1,
ISP_BLK_ID_PCHK2,
ISP_BLK_ID_PCHK3,
ISP_BLK_ID_LCAC,
ISP_BLK_ID_RGBCAC,
ISP_BLK_ID_RGBTOP,
ISP_BLK_ID_CCM0,
ISP_BLK_ID_CCM1,
ISP_BLK_ID_RGBGAMMA,
ISP_BLK_ID_YGAMMA,
ISP_BLK_ID_MMAP,
ISP_BLK_ID_DMA_CTL32,
ISP_BLK_ID_DMA_CTL33,
ISP_BLK_ID_DMA_CTL34,
ISP_BLK_ID_DMA_CTL35,
ISP_BLK_ID_DMA_CTL36, //86
ISP_BLK_ID_DMA_CTL37,
ISP_BLK_ID_CLUT,
ISP_BLK_ID_DHZ,
ISP_BLK_ID_CSC,
ISP_BLK_ID_RGBDITHER,
ISP_BLK_ID_PCHK4,
ISP_BLK_ID_PCHK5,
ISP_BLK_ID_HIST_V,
ISP_BLK_ID_DMA_CTL38, //95
ISP_BLK_ID_HDRFUSION,
ISP_BLK_ID_HDRLTM,
ISP_BLK_ID_DMA_CTL39,
ISP_BLK_ID_DMA_CTL40,
ISP_BLK_ID_YUVTOP,
ISP_BLK_ID_TNR,
ISP_BLK_ID_DMA_CTL41, //102
ISP_BLK_ID_DMA_CTL42,
ISP_BLK_ID_FBCE,
ISP_BLK_ID_DMA_CTL43, //105
ISP_BLK_ID_DMA_CTL44,
ISP_BLK_ID_FBCD,
ISP_BLK_ID_YUVDITHER,
ISP_BLK_ID_CA,
ISP_BLK_ID_CA_LITE,
ISP_BLK_ID_YNR,
ISP_BLK_ID_CNR,
ISP_BLK_ID_EE,
ISP_BLK_ID_YCURVE,
ISP_BLK_ID_DCI,
ISP_BLK_ID_DMA_CTL45, //116
ISP_BLK_ID_DCI_GAMMA,
ISP_BLK_ID_CROP4,
ISP_BLK_ID_DMA_CTL46,
ISP_BLK_ID_CROP5,
ISP_BLK_ID_DMA_CTL47,
ISP_BLK_ID_LDCI,
ISP_BLK_ID_DMA_CTL48,
ISP_BLK_ID_DMA_CTL49,
ISP_BLK_ID_PRE_EE,
ISP_BLK_ID_PCHK6,
ISP_BLK_ID_PCHK7,
ISP_BLK_ID_ISPTOP,
ISP_BLK_ID_WDMA_CORE0,
ISP_BLK_ID_RDMA_CORE,
ISP_BLK_ID_CSIBDG_LITE,
ISP_BLK_ID_DMA_CTL0,
ISP_BLK_ID_DMA_CTL1,
ISP_BLK_ID_DMA_CTL2,
ISP_BLK_ID_DMA_CTL3,
ISP_BLK_ID_WDMA_CORE1,
ISP_BLK_ID_PRE_RAW_VI_SEL,
ISP_BLK_ID_DMA_CTL4,
ISP_BLK_ID_DMA_CTL5,
ISP_BLK_ID_CMDQ,
ISP_BLK_ID_MAX
};
#endif //_ISP_REG_H_

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#ifndef __VI_H__
#define __VI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <vi_tun_cfg.h>
#include <vi_isp.h>
#include <vi_uapi.h>
#include <vi_common.h>
#include <vi_defines.h>
#define OFFLINE_RAW_BUF_NUM 2
#define OFFLINE_PRE_BE_BUF_NUM 2
#define OFFLINE_YUV_BUF_NUM 2
#define MAX_RGBMAP_BUF_NUM 3
enum cvi_isp_postraw_state {
ISP_POSTRAW_IDLE,
ISP_POSTRAW_RUNNING,
};
enum cvi_isp_pre_be_state {
ISP_PRE_BE_IDLE,
ISP_PRE_BE_RUNNING,
};
enum cvi_isp_preraw_state {
ISP_PRERAW_IDLE,
ISP_PRERAW_RUNNING,
};
struct vi_plane {
__u64 addr;
};
/*
* @index:
* @length: length of planes
* @planes: to describe buf
* @reserved
*/
struct vi_buffer {
__u32 index;
__u32 length;
struct vi_plane planes[3];
__u32 reserved;
};
/* struct mempool
* @base: the address of the mempool
* @size: the size of the mempool
* @byteused: the number of bytes used
*/
struct _mempool {
uint64_t base;
uint32_t size;
uint32_t byteused;
} isp_mempool;
struct _membuf {
uint64_t bayer_le[OFFLINE_RAW_BUF_NUM];
uint64_t bayer_se[OFFLINE_RAW_BUF_NUM];
uint64_t prebe_le[OFFLINE_PRE_BE_BUF_NUM];
uint64_t prebe_se[OFFLINE_PRE_BE_BUF_NUM];
uint64_t yuv_yuyv[ISP_CHN_MAX][2];//yuv sensor is yuyv format
uint64_t manr;
uint64_t rgbmap_le[MAX_RGBMAP_BUF_NUM];
uint64_t rgbmap_se[MAX_RGBMAP_BUF_NUM];
uint64_t lmap_le;
uint64_t lmap_se;
uint64_t lsc;
uint64_t tdnr[4];//0 for UV, 1 for Y, 2 for uv fbc double buffer, 3 for y fbc double buffer
uint64_t ldci;
//struct cvi_vip_isp_fswdr_report *fswdr_rpt;
struct cvi_isp_sts_mem sts_mem[2];
uint8_t pre_fe_sts_busy_idx;
uint8_t pre_be_sts_busy_idx;
uint8_t post_sts_busy_idx;
//spinlock_t pre_fe_sts_lock;
//uint8_t pre_fe_sts_in_use;
//spinlock_t pre_be_sts_lock;
//uint8_t pre_be_sts_in_use;
//spinlock_t post_sts_lock;
//uint8_t post_sts_in_use;
} isp_bufpool[ISP_PRERAW_MAX] = {0};
static u8 RGBMAP_BUF_IDX = 2;
/* viproc control for sensor numbers */
static int viproc_en[2] = {1, 0};
/* control internal patgen
*
* 1: enable
* 0: disable
*/
static int csi_patgen_en[ISP_PRERAW_MAX] = {0, 0};
/* runtime tuning control
* ctrl:
* 0: all ch stop update.
* 1: stop after apply ch1 setting
* 2: stop after apply ch2 setting
*/
int tuning_dis[4] = {0, 0, 0, 0}; //ctrl, fe, be, post
/* Runtime to enable/disable isp_top_clk
* Ctrl:
* 0: Disable isp_top_clk dynamic contorl
* 1: Enable isp_top_clk dynamic control
*/
int clk_dynamic_en;
//void _pre_hw_enque(
// struct cvi_vi_dev *vdev,
// const enum cvi_isp_raw raw_num,
// const u8 chn_num);
//static void _vi_sw_init(struct cvi_vi_dev *vdev);
//static int _vi_clk_ctrl(struct cvi_vi_dev *vdev, u8 enable);
//void _postraw_outbuf_enq(struct cvi_vi_dev *vdev, const enum cvi_isp_raw raw_num);
static void _vi_deferred_thread(void *arg);
void _vi_send_isp_cmdq(enum cvi_isp_raw raw_num, enum ISP_CMDQ_E cmdq_id, void *ptr);
#ifdef __cplusplus
}
#endif
#endif /* __VI_H__ */

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#ifndef __VI_COMMON_H__
#define __VI_COMMON_H__
#ifdef __cplusplus
extern "C" {
#endif
//#include <linux/clk.h>
//#include <linux/debugfs.h>
//#include <linux/io.h>
#include <stdint.h>
#include <stdbool.h>
#include <types.h>
#include <time.h>
#include "FreeRTOS.h"
#include <fifo.h>
#ifndef NULL
#define NULL 0
#endif
#define NONE 0 /* No errors */
#define ENOENT 2 /* No such file or directory */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define EBADF 9 /* Bad file number */
#define EAGAIN 11 /* No more processes */
#define EWOULDBLOCK 11 /* Operation would block */
#define ENOMEM 12 /* Not enough memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define EBUSY 16 /* Mount device busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read only file system */
#define EUNATCH 42 /* Protocol driver not attached */
#define EBADE 50 /* Invalid exchange */
#define EFTYPE 79 /* Inappropriate file type or format */
#define ENMFILE 89 /* No more files */
#define ENOTEMPTY 90 /* Directory not empty */
#define ENAMETOOLONG 91 /* File or path name too long */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define ENOBUFS 105 /* No buffer space available */
#define ENOPROTOOPT 109 /* Protocol not available */
#define EADDRINUSE 112 /* Address already in use */
#define ETIMEDOUT 116 /* Connection timed out */
#define EINPROGRESS 119 /* Connection already in progress */
#define EALREADY 120 /* Socket already connected */
#define EADDRNOTAVAIL 125 /* Address not available */
#define EISCONN 127 /* Socket is already connected */
#define ENOTCONN 128 /* Socket is not connected */
#define ENOMEDIUM 135 /* No medium inserted */
#define EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */
#define ECANCELED 140 /* Operation canceled. */
// #define MIN(a, b) (((a) < (b))?(a):(b))
// #define MAX(a, b) (((a) > (b))?(a):(b))
#define VI_64_ALIGN(x) (((x) + 0x3F) & ~0x3F) // for 64byte alignment
#define VI_256_ALIGN(x) (((x) + 0xFF) & ~0xFF) // for 256byte alignment
#define VI_ALIGN(x) (((x) + 0xF) & ~0xF) // for 16byte alignment
#define VI_256_ALIGN(x) (((x) + 0xFF) & ~0xFF) // for 256byte alignment
#define ISP_ALIGN(x, y) (((x) + (y - 1)) & ~(y - 1)) // for any bytes alignment
#define UPPER(x, y) (((x) + ((1 << (y)) - 1)) >> (y)) // for alignment
#define CEIL(x, y) (((x) + ((1 << (y)))) >> (y)) // for alignment
extern u32 vi_log_lv;
#define vi_pr(level, fmt, arg...) \
do { \
if (vi_log_lv & level) { \
if (level == VI_ERR) \
printf("%s:%d(): " fmt, __func__, __LINE__, ## arg); \
else if (level == VI_WARN) \
printf("%s:%d(): " fmt, __func__, __LINE__, ## arg); \
else if (level == VI_NOTICE) \
printf("%s:%d(): " fmt, __func__, __LINE__, ## arg); \
else if (level == VI_INFO) \
printf("%s:%d(): " fmt, __func__, __LINE__, ## arg); \
else if (level == VI_DBG) \
printf("%s:%d(): " fmt, __func__, __LINE__, ## arg); \
} \
} while (0)
enum vi_msg_pri {
VI_ERR = 0x1,
VI_WARN = 0x2,
VI_NOTICE = 0x4,
VI_INFO = 0x8,
VI_DBG = 0x10,
};
struct vi_rect {
u16 x;
u16 y;
u16 w;
u16 h;
};
void _reg_write_mask(uintptr_t addr, u32 mask, u32 data);
int vip_sys_cif_cb(unsigned int cmd, void *arg);
int vip_sys_cmm_cb_i2c(unsigned int cmd, void *arg);
void vip_sys_reg_write_mask(uintptr_t addr, u32 mask, u32 data);
//extern bool __clk_is_enabled(struct clk *clk);
#ifdef __cplusplus
}
#endif
#endif /* __VI_COMMON_H__ */

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#ifndef __VI_CORE_H__
#define __VI_CORE_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <vi_common.h>
#include <vi_defines.h>
/*******************************************************
* Common interface for core
******************************************************/
void vi_irq_handler(struct cvi_vi_dev *vdev);
int vi_create_instance(struct cvi_vi_dev *vdev);
int vi_destroy_instance(void);
int vi_start_streaming(struct cvi_vi_dev *vdev);
int vi_stop_streaming(struct cvi_vi_dev *vdev);
int vi_enq_buf(void);
#ifdef __cplusplus
}
#endif
#endif /* __VI_CORE_H__ */

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#ifndef __VI_DEFINES_H__
#define __VI_DEFINES_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <vi_tun_cfg.h>
#include <vi_isp.h>
#include <vi_drv.h>
#define FPGA_TEST
#define VI_REG_ADDR_BASE 0x0A000000
#define VI_IRQ_NUM 20
/**
* struct cvi_vi - VI IP abstraction
*/
struct cvi_vi_dev {
void *reg_base;
int irq_num;
struct isp_ctx ctx;
struct cvi_isp_mbus_framefmt usr_fmt;
struct cvi_isp_rect usr_crop;
//struct cvi_isp_snr_info snr_info[ISP_PRERAW_MAX];
u32 pre_fe_sof_cnt[ISP_PRERAW_MAX][ISP_FE_CHN_MAX];
u32 pre_fe_frm_num[ISP_PRERAW_MAX][ISP_FE_CHN_MAX];
u32 pre_be_frm_num[ISP_PRERAW_MAX][ISP_BE_CHN_MAX];
bool preraw_first_frm[ISP_PRERAW_MAX];
u32 postraw_frame_number[ISP_PRERAW_MAX];
u32 drop_frame_number[ISP_PRERAW_MAX];
u8 pre_fe_state[ISP_PRERAW_MAX][ISP_FE_CHN_MAX];
u8 pre_be_state[ISP_BE_CHN_MAX];
volatile u8 postraw_state;
u8 isp_streamoff;
u8 isp_streamon;
};
#ifdef __cplusplus
}
#endif
#endif /* __VI_DEFINES_H__ */

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freertos/cvitek/install/include/driver/vi/vi_drv.h Normal file
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#ifndef __VI_DRV_H__
#define __VI_DRV_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <mmio.h>
#include <isp_reg.h>
#include <vi_reg_blocks.h>
#include <vi_reg_fields.h>
#include <vi_tun_cfg.h>
#include <cvi_vi_ctx.h>
#include <vi_common.h>
#ifndef _OFST
#define _OFST(_BLK_T, _REG) ((uintptr_t)&(((struct _BLK_T *)0)->_REG))
#endif
// #define _reg_read(addr) mmio_read_32((uintptr_t)addr)
// #define _reg_write(addr, data) mmio_write_32((uintptr_t)addr, (uint32_t)data)
#define ISP_RD_REG_BA(_BA) \
(_reg_read(_BA))
#define ISP_RD_REG(_BA, _BLK_T, _REG) \
(_reg_read(_BA+_OFST(_BLK_T, _REG)))
#define ISP_RD_BITS(_BA, _BLK_T, _REG, _FLD) \
({\
typeof(((struct _BLK_T *)0)->_REG) _r;\
_r.raw = _reg_read(_BA+_OFST(_BLK_T, _REG));\
_r.bits._FLD;\
})
#define ISP_WR_REG(_BA, _BLK_T, _REG, _V) \
(_reg_write((_BA+_OFST(_BLK_T, _REG)), _V))
#define ISP_WR_REG_OFT(_BA, _BLK_T, _REG, _OFT, _V) \
(_reg_write((_BA+_OFST(_BLK_T, _REG) + _OFT), _V))
#define ISP_WR_BITS(_BA, _BLK_T, _REG, _FLD, _V) \
do {\
typeof(((struct _BLK_T *)0)->_REG) _r;\
_r.raw = _reg_read(_BA+_OFST(_BLK_T, _REG));\
_r.bits._FLD = _V;\
_reg_write((_BA+_OFST(_BLK_T, _REG)), _r.raw);\
} while (0)
#define ISP_WO_BITS(_BA, _BLK_T, _REG, _FLD, _V) \
do {\
typeof(((struct _BLK_T *)0)->_REG) _r;\
_r.raw = 0;\
_r.bits._FLD = _V;\
_reg_write((_BA+_OFST(_BLK_T, _REG)), _r.raw);\
} while (0)
#define ISP_WR_REGS_BURST(_BA, _BLK_T, _REG, _SIZE, _STR)\
do {\
u32 k = 0;\
uintptr_t ofst = _OFST(_BLK_T, _REG);\
for (; k < sizeof(_SIZE) / 0x4; k++) {\
u32 val = (&_STR + k)->raw;\
_reg_write((_BA + ofst + (k * 0x4)), val);\
} \
} while (0)
#define ISP_WR_REG_LOOP_SHFT(_BA, _BLK_T, _REG, _TOTAL_SIZE, _SFT_SIZE, _LUT, _SFT_BIT) \
do {\
uint16_t i = 0, j = 0;\
uint32_t val = 0;\
for (; i < _TOTAL_SIZE / _SFT_SIZE; i++) {\
val = 0;\
for (j = 0; j < _SFT_SIZE; j++) {\
val += (_LUT[(i * _SFT_SIZE) + j] << (_SFT_BIT * j));\
} \
_reg_write((_BA + _OFST(_BLK_T, _REG) + (i * 0x4)), val);\
} \
} while (0)
#define REG_ARRAY_UPDATE2_SIZE(addr, array, size) \
do { \
uint16_t i; \
for (i = 0; i < size; i += 2) { \
val = array[i]; \
if ((i + 1) < size) \
val |= (array[i+1] << 16); \
_reg_write(addr + (i << 1), val); \
} \
} while (0)
#define REG_ARRAY_UPDATE2(addr, array) \
REG_ARRAY_UPDATE2_SIZE(addr, array, ARRAY_SIZE(array))
#define REG_ARRAY_UPDATE4(addr, array) \
do { \
uint16_t i; \
for (i = 0; i < ARRAY_SIZE(array); i += 4) { \
val = array[i]; \
if ((i + 1) < ARRAY_SIZE(array)) \
val |= (array[i+1] << 8); \
if ((i + 2) < ARRAY_SIZE(array)) \
val |= (array[i+2] << 16); \
if ((i + 3) < ARRAY_SIZE(array)) \
val |= (array[i+3] << 24); \
_reg_write(addr + i, val); \
} \
} while (0)
#define LTM_REG_ARRAY_UPDATE11(addr, array) \
do { \
uint32_t val; \
val = array[0] | (array[1] << 5) | (array[2] << 10) | \
(array[3] << 15) | (array[4] << 20) | (array[5] << 25); \
_reg_write(addr, val); \
val = array[6] | (array[7] << 5) | (array[8] << 10) | \
(array[9] << 15) | (array[10] << 20); \
_reg_write(addr + 4, val); \
} while (0)
#define LTM_REG_ARRAY_UPDATE30(addr, array) \
do { \
uint8_t i, j; \
uint32_t val; \
for (i = 0, j = 0; i < ARRAY_SIZE(array); i += 6, j++) { \
val = array[i] | (array[i + 1] << 5) | \
(array[i + 2] << 10) | (array[i + 3] << 15) | \
(array[i + 4] << 20) | (array[i + 5] << 25); \
_reg_write(addr + j * 4, val); \
} \
} while (0)
enum ISP_RGB_PROB_OUT {
ISP_RGB_PROB_OUT_CFA = 0,
ISP_RGB_PROB_OUT_RGBEE,
ISP_RGB_PROB_OUT_CCM,
ISP_RGB_PROB_OUT_GMA,
ISP_RGB_PROB_OUT_DHZ,
ISP_RGB_PROB_OUT_HSV,
ISP_RGB_PROB_OUT_RGBDITHER,
ISP_RGB_PROB_OUT_CSC,
ISP_RGB_PROB_OUT_MAX,
};
enum ISP_RAW_PATH {
ISP_RAW_PATH_LE = 0,
ISP_RAW_PATH_SE,
ISP_RAW_PATH_MAX,
};
/*
* To indicate the 1st two pixel in the bayer_raw.
*/
enum ISP_BAYER_TYPE {
ISP_BAYER_TYPE_BG = 0,
ISP_BAYER_TYPE_GB,
ISP_BAYER_TYPE_GR,
ISP_BAYER_TYPE_RG,
ISP_BAYER_TYPE_MAX,
};
enum ISP_BNR_OUT {
ISP_BNR_OUT_BYPASS = 0,
ISP_BNR_OUT_B_DELAY,
ISP_BNR_OUT_FACTOR,
ISP_BNR_OUT_B_NL,
ISP_BNR_OUT_RESV_0,
ISP_BNR_OUT_RESV_1,
ISP_BNR_OUT_RESV_2,
ISP_BNR_OUT_RESV_3,
ISP_BNR_OUT_B_OUT,
ISP_BNR_OUT_INTENSITY,
ISP_BNR_OUT_DELTA,
ISP_BNR_OUT_NOT_SM,
ISP_BNR_OUT_FLAG_V,
ISP_BNR_OUT_FLAG_H,
ISP_BNR_OUT_FLAG_D45,
ISP_BNR_OUT_FLAG_D135,
ISP_BNR_OUT_MAX,
};
enum ISP_YNR_OUT {
ISP_YNR_OUT_BYPASS = 0,
ISP_YNR_OUT_Y_DELAY,
ISP_YNR_OUT_FACTOR,
ISP_YNR_OUT_ALPHA,
ISP_YNR_OUT_Y_BF,
ISP_YNR_OUT_Y_NL,
ISP_YNR_OUT_RESV_0,
ISP_YNR_OUT_RESV_1,
ISP_YNR_OUT_Y_OUT,
ISP_YNR_OUT_INTENSITY,
ISP_YNR_OUT_DELTA,
ISP_YNR_OUT_NOT_SM,
ISP_YNR_OUT_FLAG_V,
ISP_YNR_OUT_FLAG_H,
ISP_YNR_OUT_FLAG_D45,
ISP_YNR_OUT_FLAG_D135,
ISP_YNR_OUT_MAX,
};
enum ISP_FS_OUT {
ISP_FS_OUT_FS = 0,
ISP_FS_OUT_LONG,
ISP_FS_OUT_SHORT,
ISP_FS_OUT_SHORT_EX,
ISP_FS_OUT_MOTION_PXL,
ISP_FS_OUT_LE_BLD_WHT,
ISP_FS_OUT_SE_BLD_WHT,
ISP_FS_OUT_MOTION_LUT,
ISP_FS_OUT_AC_FS,
ISP_FS_OUT_DELTA_LE,
ISP_FS_OUT_DELTA_SE,
ISP_FS_OUT_MAX,
};
enum isp_dump_grp {
ISP_DUMP_PRERAW = 0x1,
ISP_DUMP_POSTRAW = 0x2,
ISP_DUMP_ALL = 0x4,
ISP_DUMP_DMA = 0x8,
ISP_DUMP_ALL_DMA = 0x10,
};
enum ISP_CCM_ID {
ISP_CCM_ID_0 = 0,
ISP_CCM_ID_1,
ISP_CCM_ID_2,
ISP_CCM_ID_3,
ISP_CCM_ID_4,
ISP_CCM_ID_MAX,
};
enum ISP_LSCR_ID {
ISP_LSCR_ID_PRE0_FE_LE = 0,
ISP_LSCR_ID_PRE0_FE_SE,
ISP_LSCR_ID_PRE1_FE_LE,
ISP_LSCR_ID_PRE1_FE_SE,
ISP_LSCR_ID_PRE_BE_LE,
ISP_LSCR_ID_PRE_BE_SE,
ISP_LSCR_ID_MAX
};
enum ISP_PRE_PROC_ID {
ISP_IR_PRE_PROC_ID_LE,
ISP_IR_PRE_PROC_ID_SE,
ISP_IR_PRE_PROC_ID_MAX
};
struct lmap_cfg {
u8 pre_chg[2]; //le/se
u8 pre_w_bit;
u8 pre_h_bit;
u8 post_w_bit;
u8 post_h_bit;
};
struct isp_dump_info {
uint64_t phy_base;
uint64_t reg_base;
uint32_t blk_size;
};
struct isp_vblock_info {
uint32_t block_id;
uint32_t block_size;
uint64_t reg_base;
};
struct tile {
u16 start;
u16 end;
};
struct isp_ccm_cfg {
u16 coef[3][3];
};
struct _fe_dbg_i {
uint32_t fe_idle_sts;
uint32_t fe_done_sts;
};
struct _be_dbg_i {
uint32_t be_done_sts;
uint32_t be_dma_idle_sts;
};
struct _post_dbg_i {
uint32_t top_sts;
};
struct _dma_dbg_i {
uint32_t wdma_0_err_sts;
uint32_t wdma_0_idle;
uint32_t wdma_1_err_sts;
uint32_t wdma_1_idle;
uint32_t rdma_err_sts;
uint32_t rdma_idle;
};
struct _isp_dg_info {
struct _fe_dbg_i fe_sts;
struct _be_dbg_i be_sts;
struct _post_dbg_i post_sts;
struct _dma_dbg_i dma_sts;
uint32_t isp_top_sts;
uint32_t bdg_chn_debug[ISP_FE_CHN_MAX];
uint32_t bdg_int_sts_0;
uint32_t bdg_int_sts_1;
uint32_t bdg_fifo_of_cnt;
uint8_t bdg_w_gt_cnt[ISP_FE_CHN_MAX];
uint8_t bdg_w_ls_cnt[ISP_FE_CHN_MAX];
uint8_t bdg_h_gt_cnt[ISP_FE_CHN_MAX];
uint8_t bdg_h_ls_cnt[ISP_FE_CHN_MAX];
};
struct isp_grid_s_info {
u8 w_bit;
u8 h_bit;
};
struct _isp_cfg {
uint32_t csibdg_width;
uint32_t csibdg_height;
uint32_t max_width;
uint32_t max_height;
uint32_t post_img_w;
uint32_t post_img_h;
uint32_t drop_ref_frm_num;
uint32_t drop_frm_cnt;
struct vi_rect crop;
struct vi_rect crop_se;
struct vi_rect postout_crop;
struct _isp_dg_info dg_info;
struct isp_grid_s_info rgbmap_i;
struct isp_grid_s_info lmap_i;
enum ISP_BAYER_TYPE rgb_color_mode;
enum _VI_INTF_MODE_E infMode;
enum _VI_WORK_MODE_E muxMode;
enum _VI_YUV_DATA_SEQ_E enDataSeq;
uint32_t is_patgen_en : 1;
uint32_t is_offline_preraw : 1;
uint32_t is_yuv_bypass_path : 1;
uint32_t is_hdr_on : 1;
uint32_t is_hdr_detail_en : 1;
uint32_t is_tile : 1;
uint32_t is_fbc_on : 1;
uint32_t is_rgbir_sensor : 1;
uint32_t is_offline_scaler : 1;
uint32_t is_stagger_vsync : 1;
uint32_t is_slice_buf_on : 1;
};
/*
* @src_width: width of original image
* @src_height: height of original image
* @img_width: width of image after crop
* @img_height: height of image after crop
* @pyhs_regs: index by enum ISP_BLK_ID_T, always phys reg
* @vreg_bases: index by enum ISP_BLK_ID_T
* @vreg_bases_pa: index by enum ISP_BLK_ID_T
*
* @rgb_color_mode: bayer_raw type after crop could change
*
* @cam_id: preraw(0,1)
* @is_offline_preraw: preraw src offline(from dram)
* @is_offline_postraw: postraw src offline(from dram)
*/
struct isp_ctx {
uint32_t src_width;
uint32_t src_height;
uint32_t img_width;
uint32_t img_height;
uint32_t crop_x;
uint32_t crop_y;
uint32_t crop_se_x;
uint32_t crop_se_y;
uintptr_t *phys_regs;
struct _isp_cfg isp_pipe_cfg[ISP_PRERAW_MAX];
enum ISP_BAYER_TYPE rgb_color_mode[ISP_PRERAW_MAX];
uint8_t rgbmap_prebuf_idx;
uint8_t rawb_chnstr_num;
uint8_t total_chn_num;
uint8_t cam_id;
uint32_t is_dual_sensor : 1;
uint32_t is_yuv_sensor : 1;
uint32_t is_hdr_on : 1;
uint32_t is_3dnr_on : 1;
uint32_t is_dpcm_on : 1;
uint32_t is_offline_be : 1;
uint32_t is_offline_postraw : 1;
uint32_t is_sublvds_path : 1;
uint32_t is_fbc_on : 1;
uint32_t is_ctrl_inited : 1;
uint32_t is_slice_buf_on : 1;
};
struct vi_fbc_cfg {
u8 cu_size;
u8 target_cr; //compression ratio
u8 is_lossless; // lossless or lossy
u32 y_bs_size; //Y WDMA seglen
u32 c_bs_size; //C WDMA seglen
u32 y_buf_size; //total Y buf size
u32 c_buf_size; //total C buf size
};
struct slc_cfg_s {
u32 le_buf_size;
u32 se_buf_size;
u32 le_w_thshd;
u32 se_w_thshd;
u32 le_r_thshd;
u32 se_r_thshd;
};
struct slice_buf_s {
u16 line_delay; //sensor exposure ratio
u16 buffer; //cover for read/write latency, axi latency..etc
u8 max_grid_size; //rgbmap grid size
u8 min_r_thshd; // minimum read threshold
struct slc_cfg_s main_path;
struct slc_cfg_s sub_path;
};
/**********************************************************
* SW scenario path check APIs
**********************************************************/
u32 _is_fe_be_online(struct isp_ctx *ctx);
u32 _is_be_post_online(struct isp_ctx *ctx);
u32 _is_all_online(struct isp_ctx *ctx);
u32 _is_post_sclr_online(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
/****************************************************************************
* Interfaces
****************************************************************************/
uint64_t _mempool_get_addr(void);
int64_t _mempool_pop(uint32_t size);
void vi_set_base_addr(void *base);
uintptr_t *isp_get_phys_reg_bases(void);
void isp_debug_dump(struct isp_ctx *ctx);
/**
* isp_init - setup isp
*
* @param :
*/
void isp_init(struct isp_ctx *ctx);
/**
* isp_reset - do reset. This can be activated only if dma stop to avoid
* hang fabric.
*
*/
void isp_reset(struct isp_ctx *ctx);
/**
* isp_stream_on - start/stop isp stream.
*
* @param on: 1 for stream start, 0 for stream stop
*/
void isp_streaming(struct isp_ctx *ctx, uint32_t on, enum cvi_isp_raw raw_num);
struct isp_grid_s_info ispblk_rgbmap_info(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
struct isp_grid_s_info ispblk_lmap_info(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void ispblk_preraw_fe_config(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void ispblk_preraw_vi_sel_config(struct isp_ctx *ctx);
void ispblk_pre_wdma_ctrl_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_preraw_be_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_raw_rdma_ctrl_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_rawtop_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_rgbtop_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_yuvtop_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_isptop_config(struct isp_ctx *ctx);
void ispblk_crop_enable(struct isp_ctx *ctx, int crop_id, bool en);
int ispblk_crop_config(struct isp_ctx *ctx, int crop_id, struct vi_rect crop);
int ccm_find_hwid(int id);
int blc_find_hwid(int id);
void ispblk_blc_set_offset(struct isp_ctx *ctx, int blc_id,
uint16_t roffset, uint16_t groffset,
uint16_t gboffset, uint16_t boffset);
void ispblk_blc_set_2ndoffset(struct isp_ctx *ctx, int blc_id,
uint16_t roffset, uint16_t groffset,
uint16_t gboffset, uint16_t boffset);
void ispblk_blc_set_gain(struct isp_ctx *ctx, int blc_id,
uint16_t rgain, uint16_t grgain,
uint16_t gbgain, uint16_t bgain);
void ispblk_blc_enable(struct isp_ctx *ctx, int blc_id, bool en, bool bypass);
int wbg_find_hwid(int id);
int ispblk_wbg_config(struct isp_ctx *ctx, int wbg_id, uint16_t rgain, uint16_t ggain, uint16_t bgain);
int ispblk_wbg_enable(struct isp_ctx *ctx, int wbg_id, bool enable, bool bypass);
void ispblk_lscr_set_lut(struct isp_ctx *ctx, int lscr_id, uint16_t *gain_lut, uint8_t lut_count);
void ispblk_lscr_config(struct isp_ctx *ctx, int lscr_id, bool en);
uint64_t ispblk_dma_getaddr(struct isp_ctx *ctx, uint32_t dmaid);
int ispblk_dma_config(struct isp_ctx *ctx, int dmaid, uint64_t buf_addr);
void ispblk_dma_setaddr(struct isp_ctx *ctx, uint32_t dmaid, uint64_t buf_addr);
void ispblk_dma_enable(struct isp_ctx *ctx, uint32_t dmaid, uint32_t on, uint8_t dma_disable);
int ispblk_dma_buf_get_size2(struct isp_ctx *ctx, int dmaid, u8 raw_num);
void ispblk_dma_set_sw_mode(struct isp_ctx *ctx, uint32_t dmaid, bool is_sw_mode);
/****************************************************************************
* PRERAW FE SUBSYS
****************************************************************************/
void ispblk_csidbg_dma_wr_en(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num, const u8 chn_num, const u8 en);
void ispblk_csibdg_wdma_crop_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num, struct vi_rect crop);
void ispblk_csibdg_crop_update(struct isp_ctx *ctx, enum cvi_isp_raw raw_num, bool en);
int ispblk_csibdg_config(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void ispblk_rgbmap_config(struct isp_ctx *ctx, int map_id, bool en, enum cvi_isp_raw raw_num);
void ispblk_lmap_chg_size(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num, const enum cvi_isp_pre_chn_num chn_num);
void ispblk_lmap_config(struct isp_ctx *ctx, int map_id, bool en);
/****************************************************************************
* PRE BE SUBSYS
****************************************************************************/
void ispblk_dpc_config(struct isp_ctx *ctx, enum ISP_RAW_PATH path, bool enable, uint8_t test_case);
void ispblk_dpc_set_static(struct isp_ctx *ctx, enum ISP_RAW_PATH path,
uint16_t offset, uint32_t *bps, uint8_t count);
void ispblk_af_config(struct isp_ctx *ctx, bool enable);
void ispblk_rgbir_preproc_config(struct isp_ctx *ctx,
uint8_t *wdata, int16_t *data_r, int16_t *data_g, int16_t *data_b);
void ispblk_ir_proc_config(struct isp_ctx *ctx, uint8_t *gamma);
/****************************************************************************
* RAW TOP SUBSYS
****************************************************************************/
void ispblk_bnr_config(struct isp_ctx *ctx, enum ISP_BNR_OUT out_sel, bool lsc_en, uint8_t ns_gain, uint8_t str);
void ispblk_cfa_config(struct isp_ctx *ctx);
void ispblk_aehist_reset(struct isp_ctx *ctx, int blk_id, enum cvi_isp_raw raw_num);
void ispblk_aehist_config(struct isp_ctx *ctx, int blk_id, bool enable);
void ispblk_gms_config(struct isp_ctx *ctx, bool enable);
void ispblk_rgbcac_config(struct isp_ctx *ctx, bool en);
void ispblk_lcac_config(struct isp_ctx *ctx, bool en, uint8_t test_case);
/****************************************************************************
* RGB TOP SUBSYS
****************************************************************************/
void ispblk_lsc_config(struct isp_ctx *ctx, bool en);
void ispblk_fusion_hdr_cfg(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void ispblk_fusion_config(struct isp_ctx *ctx, bool enable, bool mc_enable, enum ISP_FS_OUT out_sel);
void ispblk_ltm_d_lut(struct isp_ctx *ctx, uint8_t sel, uint16_t *data);
void ispblk_ltm_b_lut(struct isp_ctx *ctx, uint8_t sel, uint16_t *data);
void ispblk_ltm_g_lut(struct isp_ctx *ctx, uint8_t sel, uint16_t *data);
void ispblk_ltm_config(struct isp_ctx *ctx, u8 ltm_en, u8 dehn_en, u8 behn_en, u8 ee_en);
void ispblk_ccm_config(struct isp_ctx *ctx, enum ISP_BLK_ID_T blk_id, bool en, struct isp_ccm_cfg *cfg);
void ispblk_hist_v_config(struct isp_ctx *ctx, bool en, uint8_t test_case);
void ispblk_dhz_config(struct isp_ctx *ctx, bool en);
void ispblk_ygamma_config(struct isp_ctx *ctx, bool en,
uint8_t sel, uint16_t *data, uint8_t inv, uint8_t test_case);
void ispblk_ygamma_enable(struct isp_ctx *ctx, bool enable);
void ispblk_gamma_config(struct isp_ctx *ctx, bool en, uint8_t sel, uint16_t *data, uint8_t inv);
void ispblk_gamma_enable(struct isp_ctx *ctx, bool enable);
void ispblk_clut_config(struct isp_ctx *ctx, bool en,
int16_t *r_lut, int16_t *g_lut, int16_t *b_lut);
void ispblk_rgbdither_config(struct isp_ctx *ctx, bool en, bool mod_en, bool histidx_en, bool fmnum_en);
void ispblk_csc_config(struct isp_ctx *ctx);
void ispblk_manr_config(struct isp_ctx *ctx, bool en);
void ispblk_ir_merge_config(struct isp_ctx *ctx);
/****************************************************************************
* YUV TOP SUBSYS
****************************************************************************/
int ispblk_pre_ee_config(struct isp_ctx *ctx, bool en);
int ispblk_yuvdither_config(struct isp_ctx *ctx, uint8_t sel, bool en,
bool mod_en, bool histidx_en, bool fmnum_en);
void ispblk_tnr_config(struct isp_ctx *ctx, bool en, u8 test_case);
void ispblk_fbc_clear_fbcd_ring_base(struct isp_ctx *ctx, u8 raw_num);
void ispblk_fbc_chg_to_sw_mode(struct isp_ctx *ctx, u8 raw_num);
void vi_fbc_calculate_size(struct isp_ctx *ctx, u8 raw_num);
void ispblk_fbc_ring_buf_config(struct isp_ctx *ctx, u8 en);
void ispblk_fbcd_config(struct isp_ctx *ctx, bool en);
void ispblk_fbce_config(struct isp_ctx *ctx, bool en);
void ispblk_cnr_config(struct isp_ctx *ctx, bool en, bool pfc_en, uint8_t str_mode, uint8_t test_case);
void ispblk_ynr_config(struct isp_ctx *ctx, enum ISP_YNR_OUT out_sel, uint8_t ns_gain);
int ispblk_ee_config(struct isp_ctx *ctx, bool en);
void ispblk_dci_config(struct isp_ctx *ctx, bool en, uint16_t *lut, uint8_t test_case);
void ispblk_ldci_config(struct isp_ctx *ctx, bool en, uint8_t test_case);
void ispblk_ca_config(struct isp_ctx *ctx, bool en);
void ispblk_ca_lite_config(struct isp_ctx *ctx, bool en);
void ispblk_ycur_config(struct isp_ctx *ctx, bool en, uint8_t sel, uint16_t *data);
void ispblk_ycur_enable(struct isp_ctx *ctx, bool enable, uint8_t sel);
void isp_pre_trig(struct isp_ctx *ctx, enum cvi_isp_raw raw_num, const u8 chn_num);
void isp_post_trig(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void isp_intr_set_mask(struct isp_ctx *ctx);
void isp_intr_status(
struct isp_ctx *ctx,
union REG_ISP_TOP_INT_EVENT0 *s0,
union REG_ISP_TOP_INT_EVENT1 *s1,
union REG_ISP_TOP_INT_EVENT2 *s2);
void isp_csi_intr_status(
struct isp_ctx *ctx,
enum cvi_isp_raw raw_num,
union REG_ISP_CSI_BDG_INTERRUPT_STATUS_0 *s0,
union REG_ISP_CSI_BDG_INTERRUPT_STATUS_1 *s1);
void ispblk_tnr_rgbmap_chg(struct isp_ctx *ctx, enum cvi_isp_raw raw_num, const u8 chn_num);
void ispblk_tnr_post_chg(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
/****************************************************************************
* Runtime Control Flow Config
****************************************************************************/
void isp_first_frm_reset(struct isp_ctx *ctx, uint8_t reset);
void ispblk_post_yuv_cfg_update(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_post_cfg_update(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
void ispblk_pre_be_cfg_update(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
int ispblk_dma_get_size(struct isp_ctx *ctx, int dmaid, uint32_t _w, uint32_t _h);
uint32_t ispblk_csibdg_chn_dbg(struct isp_ctx *ctx, enum cvi_isp_raw raw_num, enum cvi_isp_pre_chn_num chn);
struct _fe_dbg_i ispblk_fe_dbg_info(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
struct _be_dbg_i ispblk_be_dbg_info(struct isp_ctx *ctx);
struct _post_dbg_i ispblk_post_dbg_info(struct isp_ctx *ctx);
struct _dma_dbg_i ispblk_dma_dbg_info(struct isp_ctx *ctx);
int isp_frm_err_handler(struct isp_ctx *ctx, const enum cvi_isp_raw err_raw_num, const u8 step);
/****************************************************************************
* YUV Bypass Control Flow Config
****************************************************************************/
void ispblk_csibdg_yuv_bypass_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num);
u32 ispblk_dma_yuv_bypass_config(struct isp_ctx *ctx, uint32_t dmaid, uint64_t buf_addr,
const enum cvi_isp_raw raw_num);
/****************************************************************************
* Slice buffer Control
****************************************************************************/
void vi_calculate_slice_buf_setting(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void isp_slice_buf_trig(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void manr_clear_prv_ring_base(struct isp_ctx *ctx, enum cvi_isp_raw raw_num);
void ispblk_slice_buf_config(struct isp_ctx *ctx, const enum cvi_isp_raw raw_num, u8 en);
/*******************************************************************************
* Tuning interfaces
******************************************************************************/
void vi_tuning_gamma_ips_update(
struct isp_ctx *ctx,
enum cvi_isp_raw raw_num);
void vi_tuning_dci_update(
struct isp_ctx *ctx,
enum cvi_isp_raw raw_num);
int vi_tuning_buf_setup(void);
void vi_tuning_buf_release(void);
void *vi_get_tuning_buf_addr(u32 *size);
void vi_tuning_buf_clear(void);
#ifdef __cplusplus
}
#endif
#endif /* __VI_DRV_H__ */

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#ifndef __VI_INTER_CMDQ_H__
#define __VI_INTER_CMDQ_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <types.h>
enum VI_EVENT_E {
VI_EV_SOF = 1,
VI_EV_FE_DONE,
VI_EV_BE_DONE,
VI_EV_POST_SHAW_DONE,
VI_EV_POST_DONE,
VI_EV_MAX,
};
enum VI_INTER_CMDQ_E {
VI_CMDQ_EV_TYPE,
VI_CMDQ_MAX,
};
#ifdef __cplusplus
}
#endif
#endif /* __VI_INTER_CMDQ_H__ */

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#ifndef __VI_INTERFACES_H__
#define __VI_INTERFACES_H__
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************
* Common interface for cvi_vi
******************************************************/
int vi_drv_open(struct cvi_vi_ctx *viCtx);
int vi_drv_cfg(void);
int vi_drv_streamon(void);
int vi_drv_streamoff(void);
int vi_drv_release(void);
#ifdef __cplusplus
}
#endif
#endif /* __VI_INTERFACES_H__ */

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#ifndef __U_VI_SNSR_H__
#define __U_VI_SNSR_H__
//#include <linux/cif_uapi.h>
#define MAX_WDR_FRAME_NUM 2
#define ISP_MAX_SNS_REGS 32
struct manual_wdr_attr_s {
unsigned int manual_en;
unsigned short l2s_distance;
unsigned short lsef_length;
unsigned int discard_padding_lines;
unsigned int update;
};
struct manual_wdr_s {
unsigned int devno;
struct manual_wdr_attr_s attr;
};
/**
* struct active_size_s - linear/wdr image information
*
* @width: image total width
* @height: image total height
* @start_x: horizontal shift of the 1st pixel
* @start_y: horizontal shift of the 1st pixel
* @active_w: effective image width
* @active_h: effective image height
* @max_width: max width for buffer allocation
* @max_height: max height for buffer allocation
*/
struct active_size_s {
unsigned short width;
unsigned short height;
unsigned short start_x;
unsigned short start_y;
unsigned short active_w;
unsigned short active_h;
unsigned short max_width;
unsigned short max_height;
};
/**
* struct wdr_size_s - structure for CVI_SNSR_G_WDR_SIZE
*
* @frm_num: [output] Effective image instance. 1 for linear mode, >1 for wdr mode.
* @img_size: [output] Image information.
*/
struct wdr_size_s {
unsigned int frm_num;
struct active_size_s img_size[MAX_WDR_FRAME_NUM];
};
enum isp_sns_type_e {
ISP_SNS_I2C_TYPE = 0,
ISP_SNS_TYPE_BUTT,
};
enum sns_wdr_e {
SNS_WDR_MODE_NONE = 0,
SNS_WDR_MODE_2TO1_LINE,
SNS_WDR_MODE_BUTT
};
/**
* struct isp_i2c_data - sensor setting with i2c interface.
*
* @update: update this register or not
* @drop_frame: drop next frame or not
* @i2c_dev: i2c device number.
* @dev_addr: sensor slave address
* @dly_frm_num: this setting would be set with delay frame number
* @drop_frame_cnt: this setting would be set with drop frame
* @reg_addr: sensor register address
* @addr_bytes: sensor register address bytes number
* @data: sensor register value
* @data_bytes: sensor register value bytes number
*/
struct isp_i2c_data {
unsigned char update;
unsigned char drop_frame;
unsigned char i2c_dev;
unsigned char dev_addr;
unsigned char dly_frm_num;
unsigned short drop_frame_cnt;
unsigned short reg_addr;
unsigned short addr_bytes;
unsigned short data;
unsigned short data_bytes;
};
/**
* struct snsr_regs_s - structure of sensor update wrapper
*
* @sns_type: i2c or other interface
* @regs_num: the maximum sensor registers to be updated
* @i2c_data: sensor registers to be updated
* @use_snsr_sram: does this sensor support group update
* @need_update: global flag for sensor update. Ignore this wrapper
* when it is zero.
*/
struct snsr_regs_s {
enum isp_sns_type_e sns_type;
unsigned int magic_num;
unsigned int regs_num;
struct isp_i2c_data i2c_data[ISP_MAX_SNS_REGS];
unsigned char cfg_valid_max_dly_frm;
unsigned char use_snsr_sram;
unsigned char need_update;
};
/**
* struct snsr_isp_s - structure of isp update wrapper
*
* @wdr: the image information for isp driver.
* @need_update: global flag for isp update. Ignore this wrapper
* when it is zero.
*/
struct snsr_isp_s {
struct wdr_size_s wdr;
unsigned char dly_frm_num;
unsigned char need_update;
};
/**
* struct snsr_cif_s - structure of cif(mipi_rx) update wrapper
*
* @wdr: the image information for isp driver.
* @need_update: global flag for cif update. Ignore this wrapper
* when it is zero.
*/
struct snsr_cif_s {
struct manual_wdr_s wdr_manu;
unsigned char dly_frm_num;
unsigned char need_update;
};
/**
* struct snsr_cfg_node_s - structure of cfg node for runtime update
*
* @snsr: [output] snsr wrapper for runtime update
* @isp: [output] isp wrapper for runtime update
* @cif: [output] cif wrapper for runtime update
* @configed: [intput] after CVI_SNSR_G_CFG_NODE is called, this flag
* is set as false by sensor driver. The caller shall set it as
* true after this cfg_node is passed to isp driver.
*/
struct snsr_cfg_node_s {
struct snsr_regs_s snsr;
struct snsr_isp_s isp;
struct snsr_cif_s cif;
unsigned char configed;
};
#endif // __U_VI_SNSR_H__

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