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yegaogang
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12
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1
.svn/format
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.svn/format
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12
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PROJECT(NxpRdLib_Log)
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FILE(GLOB NxpRdLib_Log_Sources
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./src/phLog.c
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./src/phLog_Int.h
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)
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ADD_LIBRARY(NxpRdLib_Log
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${NxpRdLib_Log_Sources}
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)
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/*
|
||||
* @brief LPC175x/6x basic chip inclusion file
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __CHIP_LPC175X_6X_H_
|
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#define __CHIP_LPC175X_6X_H_
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|
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#include "lpc_types.h"
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#include "sys_config.h"
|
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#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
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#endif
|
||||
|
||||
#if !defined(CORE_M3)
|
||||
#error CORE_M3 is not defined for the LPC175x/6x architecture
|
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#error CORE_M3 should be defined as part of your compiler define list
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#endif
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|
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#ifndef CHIP_LPC175X_6X
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#error CHIP_LPC175X_6X is not defined!
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#endif
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|
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/** @defgroup PERIPH_175X_6X_BASE CHIP: LPC175x/6x Peripheral addresses and register set declarations
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* @ingroup CHIP_17XX_40XX_Drivers
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||||
* @{
|
||||
*/
|
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|
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#define LPC_GPIO0_BASE 0x2009C000
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#define LPC_GPIO1_BASE 0x2009C020
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#define LPC_GPIO2_BASE 0x2009C040
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#define LPC_GPIO3_BASE 0x2009C060
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#define LPC_GPIO4_BASE 0x2009C080
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|
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/* APB0 peripheral */
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#define LPC_WWDT_BASE 0x40000000
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#define LPC_TIMER0_BASE 0x40004000
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#define LPC_TIMER1_BASE 0x40008000
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#define LPC_UART0_BASE 0x4000C000
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#define LPC_UART1_BASE 0x40010000
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#define LPC_PWM1_BASE 0x40018000
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#define LPC_I2C0_BASE 0x4001C000
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#define LPC_SPI_BASE 0x40020000
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#define LPC_RTC_BASE 0x40024000
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#define LPC_REGFILE_BASE 0x40024044
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#define LPC_GPIOINT_BASE 0x40028080
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#define LPC_IOCON_BASE 0x4002C000
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#define LPC_SSP1_BASE 0x40030000
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#define LPC_ADC_BASE 0x40034000
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#define LPC_CANAF_RAM_BASE 0x40038000
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#define LPC_CANAF_BASE 0x4003C000
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#define LPC_CANCR_BASE 0x40040000
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#define LPC_CAN1_BASE 0x40044000
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#define LPC_CAN2_BASE 0x40048000
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#define LPC_I2C1_BASE 0x4005C000
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/* APB1 peripheral */
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#define LPC_FMC_BASE 0x40084000
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#define LPC_SSP0_BASE 0x40088000
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#define LPC_DAC_BASE 0x4008C000
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#define LPC_TIMER2_BASE 0x40090000
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#define LPC_TIMER3_BASE 0x40094000
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#define LPC_UART2_BASE 0x40098000
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#define LPC_UART3_BASE 0x4009C000
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#define LPC_I2C2_BASE 0x400A0000
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#define LPC_I2S_BASE 0x400A8000
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#define LPC_RITIMER_BASE 0x400B0000
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#define LPC_MCPWM_BASE 0x400B8000
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#define LPC_QEI_BASE 0x400BC000
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#define LPC_SYSCTL_BASE 0x400FC000
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#define LPC_PMU_BASE 0x400FC0C0
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||||
|
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/* AHB peripheral */
|
||||
#define LPC_ENET_BASE 0x50000000
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#define LPC_GPDMA_BASE 0x50004000
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#define LPC_USB_BASE 0x5000C000
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|
||||
/* Assign LPC_* names to structures mapped to addresses */
|
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#define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE)
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#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
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#define LPC_USB ((LPC_USB_T *) LPC_USB_BASE)
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||||
#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ENET_BASE)
|
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#define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO0_BASE)
|
||||
#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
|
||||
#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
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||||
#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
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||||
#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
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||||
#define LPC_GPIOINT ((LPC_GPIOINT_T *) LPC_GPIOINT_BASE)
|
||||
#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
|
||||
#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
|
||||
#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
|
||||
#define LPC_UART0 ((LPC_USART_T *) LPC_UART0_BASE)
|
||||
#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
|
||||
#define LPC_UART2 ((LPC_USART_T *) LPC_UART2_BASE)
|
||||
#define LPC_UART3 ((LPC_USART_T *) LPC_UART3_BASE)
|
||||
#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
|
||||
#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
|
||||
#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
|
||||
#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
|
||||
#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
|
||||
#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
|
||||
#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
|
||||
#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
|
||||
#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
|
||||
#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
|
||||
#define LPC_I2C2 ((LPC_I2C_T *) LPC_I2C2_BASE)
|
||||
#define LPC_I2S ((LPC_I2S_T *) LPC_I2S_BASE)
|
||||
#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
|
||||
#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
|
||||
#define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE)
|
||||
#define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE)
|
||||
#define LPC_SYSCTL ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE)
|
||||
#define LPC_SYSCON ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE) /* Alias for LPC_SYSCTL */
|
||||
#define LPC_CANAF_RAM ((LPC_CANAF_RAM_T *) LPC_CANAF_RAM_BASE)
|
||||
#define LPC_CANAF ((LPC_CANAF_T *) LPC_CANAF_BASE)
|
||||
#define LPC_CANCR ((LPC_CANCR_T *) LPC_CANCR_BASE)
|
||||
#define LPC_CAN1 ((LPC_CAN_T *) LPC_CAN1_BASE)
|
||||
#define LPC_CAN2 ((LPC_CAN_T *) LPC_CAN2_BASE)
|
||||
#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
|
||||
#define LPC_FMC ((LPC_FMC_T *) LPC_FMC_BASE)
|
||||
|
||||
/* IRQ Handler Alias list */
|
||||
#define UART_IRQHandler UART0_IRQHandler
|
||||
#define I2C_IRQHandler I2C0_IRQHandler
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||||
#define SSP_IRQHandler SSP0_IRQHandler
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "sysctl_17xx_40xx.h"
|
||||
#include "clock_17xx_40xx.h"
|
||||
#include "iocon_17xx_40xx.h"
|
||||
#include "adc_17xx_40xx.h"
|
||||
#include "can_17xx_40xx.h"
|
||||
#include "dac_17xx_40xx.h"
|
||||
#include "enet_17xx_40xx.h"
|
||||
#include "gpdma_17xx_40xx.h"
|
||||
#include "gpio_17xx_40xx.h"
|
||||
#include "gpioint_17xx_40xx.h"
|
||||
#include "i2c_17xx_40xx.h"
|
||||
#include "i2s_17xx_40xx.h"
|
||||
#include "mcpwm_17xx_40xx.h"
|
||||
#include "pmu_17xx_40xx.h"
|
||||
#include "qei_17xx_40xx.h"
|
||||
#include "ritimer_17xx_40xx.h"
|
||||
#include "rtc_17xx_40xx.h"
|
||||
#include "spi_17xx_40xx.h"
|
||||
#include "ssp_17xx_40xx.h"
|
||||
#include "timer_17xx_40xx.h"
|
||||
#include "uart_17xx_40xx.h"
|
||||
#include "usb_17xx_40xx.h"
|
||||
#include "wwdt_17xx_40xx.h"
|
||||
#include "fmc_17xx_40xx.h"
|
||||
#include "romapi_17xx_40xx.h"
|
||||
/* FIXME : PWM drivers */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CHIP_LPC175X_6X_H_ */
|
||||
@ -0,0 +1,85 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
2142
.svn/pristine/01/0159c9a88016c3186a9198fe4b75b7d84e94fdf8.svn-base
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.svn/pristine/01/0159c9a88016c3186a9198fe4b75b7d84e94fdf8.svn-base
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|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2009-2023 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Generic ISO14443-3B Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHPALI14443P3B_H
|
||||
#define PHPALI14443P3B_H
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <phhalHw.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P3B_SW
|
||||
|
||||
/** \defgroup phpalI14443p3b_Sw Component : Software
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PHPAL_I14443P3B_SW_ID 0x01U /**< ID for Software ISO14443-3B layer */
|
||||
|
||||
/**
|
||||
* \brief Software PAL-ISO14443P3B parameter structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t wId; /**< Layer ID for this component, NEVER MODIFY! */
|
||||
void * pHalDataParams; /**< Pointer to the parameter structure of the underlying layer.*/
|
||||
uint8_t bExtAtqb; /**< Stores whether last request used extended ATQB. */
|
||||
uint8_t pPupi[4]; /**< Array holding the activated PUPI. */
|
||||
uint8_t bPupiValid; /**< Whether the stored Pupi is valid (\c 1) or not (\c 0). */
|
||||
uint8_t bCidSupported; /**< Cid Support indicator; Unequal '0' if supported. */
|
||||
uint8_t bNadSupported; /**< Nad Support indicator; Unequal '0' if supported. */
|
||||
uint8_t bCid; /**< Card Identifier; Ignored if bCidSupported is equal '0'. */
|
||||
uint8_t bFwi; /**< Frame Waiting Integer. */
|
||||
uint8_t bFsci; /**< PICC Frame Size Integer; 0-12; */
|
||||
uint8_t bFsdi; /**< (Current) PCD Frame Size Integer; 0-12; */
|
||||
uint8_t bDri; /**< (Current) Divisor Receive (PCD to PICC) Integer; 0-3; */
|
||||
uint8_t bDsi; /**< (Current) Divisor Send (PICC to PCD) Integer; 0-3; */
|
||||
uint8_t bAttribParam1; /**< Param1 parameter for attrib command. */
|
||||
uint8_t * pHigherLayerInf; /**< Pointer to higher layer information buffer. */
|
||||
uint16_t wTxWait; /**< Tx Wait Time */
|
||||
uint16_t wHigherLayerInfLen; /**< Length higher layer information. */
|
||||
uint8_t * pHigherLayerResp; /**< Pointer to higher layer response buffer. */
|
||||
uint16_t wHigherLayerRespSize; /**< Size of higher layer response buffer. */
|
||||
uint16_t wHigherLayerRespLen; /**< Length of higher layer response. */
|
||||
uint8_t bOpeMode; /**< Operation mode. One of NFC, EMVCo, ISO. */
|
||||
uint8_t bPollCmd; /**< Used to differentiate which command to send REQA or WakeUpA command for polling */
|
||||
uint8_t bRetryCount; /**< Retry count for ATTRIB command as per NFC Digital Protocol Version 2.3\n
|
||||
For mode #RD_LIB_MODE_EMVCO retry count should be 1. */
|
||||
} phpalI14443p3b_Sw_DataParams_t;
|
||||
|
||||
phStatus_t phpalI14443p3b_Sw_Init(
|
||||
phpalI14443p3b_Sw_DataParams_t * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint16_t wSizeOfDataParams, /**< [In] Specifies the size of the data parameter structure. */
|
||||
void * pHalDataParams /**< [In] Pointer to the parameter structure of the underlying layer.*/
|
||||
);
|
||||
|
||||
/** @} */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P3B_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P3B
|
||||
|
||||
/** \defgroup phpalI14443p3b ISO/IEC 14443-3B
|
||||
* \brief These Components implement the ISO/IEC 14443-3 Type-B contactless protocol.
|
||||
*
|
||||
* \b Note: The "Timing before the PCD SOF" <em>(see 7.1.7, ISO/IEC 14443-3:2009(E))</em> is mandatory and is
|
||||
* neither implemented here nor implemented in every \ref phhalHw layer.\n
|
||||
* Make sure that either the used HAL or the used application does comply to this rule.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \name 14443-3B constant definitions
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I14443P3B_CONFIG_ATTRIB_PARAM1 0x0000U /**< Set or get the AttribB param1 byte. */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Configuration
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* Configure Operation Mode for this Layer. \n
|
||||
* Possible values are\n
|
||||
* #RD_LIB_MODE_EMVCO, \n
|
||||
* #RD_LIB_MODE_NFC, \n
|
||||
* #RD_LIB_MODE_ISO,\n
|
||||
* Default value is #RD_LIB_MODE_NFC.
|
||||
* */
|
||||
#define PHPAL_I14443P3B_CONFIG_OPE_MODE 0x0001U
|
||||
|
||||
/**
|
||||
* Configure which command to be used for Type B Polling. \n
|
||||
* Possible values are\n
|
||||
* #PHPAL_I14443P3B_USE_WUPB, \n
|
||||
* #PHPAL_I14443P3B_USE_REQB, \n
|
||||
* Default value is #PHPAL_I14443P3B_USE_REQB.
|
||||
* */
|
||||
#define PHPAL_I14443P3B_CONFIG_POLL_CMD 0x0002U
|
||||
|
||||
/**
|
||||
* Configure retry count for ATTRIB command.\n
|
||||
* Possible values are\n
|
||||
* #PHPAL_I14443P3B_ATTRIB_RETRY_MIN, \n
|
||||
* #PHPAL_I14443P3B_ATTRIB_RETRY_MAX, \n
|
||||
*
|
||||
* Default value is #PHPAL_I14443P3B_ATTRIB_RETRY_MAX.\n
|
||||
*
|
||||
* For mode #RD_LIB_MODE_EMVCO retry count should be 1.
|
||||
* */
|
||||
#define PHPAL_I14443P3B_CONFIG_ATTRIB_RETRY_COUNT 0x0003U
|
||||
|
||||
/**
|
||||
* Get the Divisor Receive Integer (DRI).
|
||||
*
|
||||
* Default is 0.
|
||||
* */
|
||||
#define PHPAL_I14443P3B_CONFIG_DRI 0x0004U
|
||||
|
||||
/**
|
||||
* Get the Divisor Send Integer (DSI).
|
||||
*
|
||||
* Default is 0.
|
||||
* */
|
||||
#define PHPAL_I14443P3B_CONFIG_DSI 0x0005U
|
||||
|
||||
/*@}*/
|
||||
/**
|
||||
* \name Poll Command
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I14443P3B_USE_REQB 0x00U /**< Indicate REQB command to be used for Type B Polling*/
|
||||
#define PHPAL_I14443P3B_USE_WUPB 0x01U /**< Indicate WakeupB command to be used for Type B Polling*/
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name DRI/DSI Values
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I14443P3B_DATARATE_106 0x00U /**< DRI/DSI value for 106 kBit/s */
|
||||
#define PHPAL_I14443P3B_DATARATE_212 0x01U /**< DRI/DSI value for 212 kBit/s */
|
||||
#define PHPAL_I14443P3B_DATARATE_424 0x02U /**< DRI/DSI value for 424 kBit/s */
|
||||
#define PHPAL_I14443P3B_DATARATE_848 0x03U /**< DRI/DSI value for 848 kBit/s */
|
||||
#define PHPAL_I14443P3B_DATARATE_FORCE 0x80U /**< Flag that forces the use of the given baud rates */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Attrib Command Retry Values
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I14443P3B_ATTRIB_RETRY_MAX 1U /**< Maximum retry value of ATTRIB during transmission and timeout error.*/
|
||||
#define PHPAL_I14443P3B_ATTRIB_RETRY_MIN 0U /**< Minimum retry value of ATTRIB during transmission and timeout error.*/
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Maximum allowed FSDI/FSCI Value
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I14443P3B_FRAMESIZE_MAX 12U /**< Maximum allowed FSDI/FSCI Value.*/
|
||||
/*@}*/
|
||||
|
||||
#ifdef NXPRDLIB_REM_GEN_INTFS
|
||||
#include "../comps/phpalI14443p3b/src/Sw/phpalI14443p3b_Sw.h"
|
||||
|
||||
#define phpalI14443p3b_SetConfig( pDataParams, wConfig, wValue) \
|
||||
phpalI14443p3b_Sw_SetConfig((phpalI14443p3b_Sw_DataParams_t *)pDataParams, wConfig, wValue)
|
||||
|
||||
#define phpalI14443p3b_GetConfig( pDataParams, wConfig, pValue ) \
|
||||
phpalI14443p3b_Sw_GetConfig((phpalI14443p3b_Sw_DataParams_t *)pDataParams, wConfig, pValue)
|
||||
|
||||
#define phpalI14443p3b_RequestB( pDataParams, bNumSlots, bAfi, bExtAtqb, pAtqb, pAtqbLen) \
|
||||
phpalI14443p3b_Sw_RequestB((phpalI14443p3b_Sw_DataParams_t *)pDataParams, bNumSlots, bAfi, bExtAtqb, pAtqb, pAtqbLen)
|
||||
|
||||
#define phpalI14443p3b_WakeUpB( pDataParams, bNumSlots, bAfi, bExtAtqb, pAtqb, pAtqbLen) \
|
||||
phpalI14443p3b_Sw_WakeUpB((phpalI14443p3b_Sw_DataParams_t *)pDataParams, bNumSlots, bAfi, bExtAtqb, pAtqb, pAtqbLen)
|
||||
|
||||
#define phpalI14443p3b_SlotMarker( pDataParams, bSlotNumber, pAtqb, pAtqbLen) \
|
||||
phpalI14443p3b_Sw_SlotMarker((phpalI14443p3b_Sw_DataParams_t *)pDataParams, bSlotNumber, pAtqb, pAtqbLen)
|
||||
|
||||
#define phpalI14443p3b_HaltB( pDataParams) \
|
||||
phpalI14443p3b_Sw_HaltB((phpalI14443p3b_Sw_DataParams_t *)pDataParams)
|
||||
|
||||
#define phpalI14443p3b_Attrib( pDataParams, pAtqb, bAtqbLen, bFsdi, bCid, bDri, bDsi, pMbli) \
|
||||
phpalI14443p3b_Sw_Attrib((phpalI14443p3b_Sw_DataParams_t *)pDataParams, pAtqb, bAtqbLen, bFsdi, bCid, bDri, bDsi, pMbli)
|
||||
|
||||
#define phpalI14443p3b_ActivateCard( pDataParams, pPupi, bPupiLength, bNumSlots, bAfi, \
|
||||
bExtAtqb, bFsdi, bCid, bDri, bDsi, pAtqb, pAtqbLen, pMbli, pMoreCardsAvailable) \
|
||||
phpalI14443p3b_Sw_ActivateCard((phpalI14443p3b_Sw_DataParams_t *)pDataParams,pPupi, bPupiLength, bNumSlots, bAfi, bExtAtqb, \
|
||||
bFsdi, bCid, bDri, bDsi, pAtqb, pAtqbLen,pMbli, pMoreCardsAvailable)
|
||||
|
||||
#define phpalI14443p3b_Exchange( pDataParams, wOption, pTxBuffer, wTxLength, ppRxBuffer, pRxLength) \
|
||||
phpalI14443p3b_Sw_Exchange((phpalI14443p3b_Sw_DataParams_t *)pDataParams, wOption, pTxBuffer, wTxLength, ppRxBuffer, pRxLength)
|
||||
|
||||
#define phpalI14443p3b_GetSerialNo( pDataParams, pPupi) \
|
||||
phpalI14443p3b_Sw_GetSerialNo((phpalI14443p3b_Sw_DataParams_t *)pDataParams, pPupi)
|
||||
|
||||
#define phpalI14443p3b_SetSerialNo( pDataParams, pPupi) \
|
||||
phpalI14443p3b_Sw_SetSerialNo((phpalI14443p3b_Sw_DataParams_t *)pDataParams, pPupi)
|
||||
|
||||
#define phpalI14443p3b_SetHigherLayerInf( pDataParams, pTxBuffer, wTxLength, pRxBuffer, wRxBufSize) \
|
||||
phpalI14443p3b_Sw_SetHigherLayerInf((phpalI14443p3b_Sw_DataParams_t *)pDataParams, pTxBuffer, wTxLength, pRxBuffer, wRxBufSize)
|
||||
|
||||
#define phpalI14443p3b_GetHigherLayerResp( pDataParams, ppRxBuffer, pRxLength) \
|
||||
phpalI14443p3b_Sw_GetHigherLayerResp((phpalI14443p3b_Sw_DataParams_t *)pDataParams, ppRxBuffer, pRxLength)
|
||||
|
||||
#define phpalI14443p3b_GetProtocolParams( pDataParams, pCidEnabled, pCid, pNadSupported, pFwi, pFsdi, pFsci) \
|
||||
phpalI14443p3b_Sw_GetProtocolParams((phpalI14443p3b_Sw_DataParams_t *)pDataParams, pCidEnabled, pCid, pNadSupported, pFwi, pFsdi, pFsci)
|
||||
|
||||
#else
|
||||
|
||||
/**
|
||||
* \brief Set configuration value.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_PROTOCOL_ERROR Invalid response received.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_SetConfig(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint16_t wConfig, /**< [In] Configuration Identifier. */
|
||||
uint16_t wValue /**< [In] Configuration Value. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Get configuration value.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_PROTOCOL_ERROR Invalid response received.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_GetConfig(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint16_t wConfig, /**< [In] Configuration Identifier. */
|
||||
uint16_t* pValue /**< [Out] Configuration Value. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform a ISO14443-3B Request command.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_PROTOCOL_ERROR Invalid response received.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_RequestB(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint8_t bNumSlots, /**< [In] Number of slots. */
|
||||
uint8_t bAfi, /**< [In] AFI; Application Family Indentifier. */
|
||||
uint8_t bExtAtqb, /**< [In] Enable Extended AtqB. */
|
||||
uint8_t * pAtqb, /**< [Out] AtqB; uint8_t[13]. */
|
||||
uint8_t * pAtqbLen /**< [Out] length of ATQB (12/13 bytes). */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform a ISO14443-3B Wakeup command.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_PROTOCOL_ERROR Invalid response received.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_WakeUpB(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint8_t bNumSlots, /**< [In] Number of slots. */
|
||||
uint8_t bAfi, /**< [In] AFI; Application Family Indentifier. */
|
||||
uint8_t bExtAtqb, /**< [In] Enable Extended AtqB. */
|
||||
uint8_t * pAtqb, /**< [Out] AtqB; uint8_t[12/13]. */
|
||||
uint8_t * pAtqbLen /**< [Out] length of ATQB (12/13 bytes). */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform a ISO14443-3B Slot-MARKER command.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_PROTOCOL_ERROR Invalid response received.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_SlotMarker(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint8_t bSlotNumber, /**< [In] Slot Number. */
|
||||
uint8_t * pAtqb, /**< [Out] AtqB; uint8_t[12/13]. */
|
||||
uint8_t * pAtqbLen /**< [Out] length of ATQB (12/13 bytes). */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform a ISO14443-3B Halt command.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_PROTOCOL_ERROR Invalid response received.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_HaltB(
|
||||
void * pDataParams /**< [In] Pointer to this layers parameter structure. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform a ISO14443-3B Attrib command.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_PROTOCOL_ERROR Invalid response received.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_Attrib(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint8_t * pAtqb, /**< [In] Atqb from ReqB/WupB; uint8_t[12/13]. */
|
||||
uint8_t bAtqbLen, /**< [In] Length of Atqb. */
|
||||
uint8_t bFsdi, /**< [In] Frame Size Integer; 0-12. */
|
||||
uint8_t bCid, /**< [In] Card Identifier; 0-14. */
|
||||
uint8_t bDri, /**< [In] Divisor Receive (PCD to PICC) Integer; 0-3. */
|
||||
uint8_t bDsi, /**< [In] Divisor Send (PICC to PCD) Integer; 0-3. */
|
||||
uint8_t * pMbli /**< [Out] MBLI byte; uint8_t. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform ISO14443-3B ReqB or WupB and Anticollision/Select commands for all cascade levels.
|
||||
*
|
||||
* If bLenUidIn is '0' --> CardUid not given, a ReqB is performed.
|
||||
* If CardUid is given, a WupB is performed.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_PROTOCOL_ERROR Invalid response received.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_ActivateCard(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint8_t * pPupi, /**< [In] Pointer to the known PUPI; uint8_t[4]. */
|
||||
uint8_t bPupiLength, /**< [In] Length of given PUPI, only a value of 0 or 4 is allowed. */
|
||||
uint8_t bNumSlots, /**< [In] Number of slots. */
|
||||
uint8_t bAfi, /**< [In] AFI; Application Family Indentifier. */
|
||||
uint8_t bExtAtqb, /**< [In] Enable Extended AtqB. */
|
||||
uint8_t bFsdi, /**< [In] Frame Size Integer; 0-12. */
|
||||
uint8_t bCid, /**< [In] Card Identifier; 0-14. */
|
||||
uint8_t bDri, /**< [In] Divisor Receive (PCD to PICC) Integer; 0-3. */
|
||||
uint8_t bDsi, /**< [In] Divisor Send (PICC to PCD) Integer; 0-3. */
|
||||
uint8_t * pAtqb, /**< [Out] AtqB; uint8_t[13]. */
|
||||
uint8_t * pAtqbLen, /**< [Out] length of ATQB (12/13 bytes). */
|
||||
uint8_t * pMbli, /**< [Out] MBLI byte; uint8_t. */
|
||||
uint8_t * pMoreCardsAvailable /**< [Out] Whether there are more cards in the field or not; uint8_t. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform ISO14443-3B Data Exchange with Picc.
|
||||
*
|
||||
* \c wOption can be one of:\n
|
||||
* \li #PH_EXCHANGE_DEFAULT
|
||||
* \li #PH_EXCHANGE_BUFFER_FIRST
|
||||
* \li #PH_EXCHANGE_BUFFER_CONT
|
||||
* \li #PH_EXCHANGE_BUFFER_LAST
|
||||
*
|
||||
* Alternatively, the following bits can be combined:\n
|
||||
* \li #PH_EXCHANGE_BUFFERED_BIT
|
||||
* \li #PH_EXCHANGE_LEAVE_BUFFER_BIT
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_Exchange(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint16_t wOption, /**< [In] Option parameter. */
|
||||
uint8_t * pTxBuffer, /**< [In] Data to transmit. */
|
||||
uint16_t wTxLength, /**< [In] Length of data to transmit. */
|
||||
uint8_t ** ppRxBuffer, /**< [Out] Pointer to received data. */
|
||||
uint16_t * pRxLength /**< [Out] number of received data bytes. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the serial number.
|
||||
* This function will provide 4 byte PUPI.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_USE_CONDITION No PUPI available.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_GetSerialNo(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint8_t * pPupi /**< [Out] Most recent PUPI. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief This function will update PUPI in this layer's parameter structure.
|
||||
* This function must be called with valid PUPI.
|
||||
* Once set the subsequent type B commands use this PUPI.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_SetSerialNo(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint8_t * pPupi /**< [In] 4 byte PUPI. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Set higher layer information.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_USE_CONDITION Feature not available.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_SetHigherLayerInf(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint8_t * pTxBuffer, /**< [In] Higher layer Information; Can be NULL if /c wTxLength is 0. */
|
||||
uint16_t wTxLength, /**< [In] Length of the Higher layer Information. Can be 0. */
|
||||
uint8_t * pRxBuffer, /**< [In] Higher layer response buffer. */
|
||||
uint16_t wRxBufSize /**< [In] Size of Higher layer response buffer. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Get higher layer response.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_USE_CONDITION Feature not available.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_GetHigherLayerResp(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint8_t ** ppRxBuffer, /**< [Out] Higher layer response. */
|
||||
uint16_t * pRxLength /**< [Out] Length of Higher layer response. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the ISO14443-3B protocol parameters.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
*/
|
||||
phStatus_t phpalI14443p3b_GetProtocolParams(
|
||||
void * pDataParams, /**< [In] Pointer to this layers parameter structure. */
|
||||
uint8_t * pCidEnabled, /**< [Out] Unequal '0' if Card Identifier is enabled. */
|
||||
uint8_t * pCid, /**< [Out] Card Identifier. */
|
||||
uint8_t * pNadSupported, /**< [Out] Node Address Support; Unequal '0' if supported. */
|
||||
uint8_t * pFwi, /**< [Out] Frame Waiting Integer. */
|
||||
uint8_t * pFsdi, /**< [Out] PCD Frame Size Integer; 0-12. */
|
||||
uint8_t * pFsci /**< [Out] PICC Frame Size Integer; 0-12. */
|
||||
);
|
||||
|
||||
/** @} */
|
||||
#endif /* NXPRDLIB_REM_GEN_INTFS */
|
||||
|
||||
#endif /* NXPBUILD__PHPAL_I14443P3B */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* Extern C */
|
||||
#endif
|
||||
|
||||
#endif /* PHPALI14443P3B_H */
|
||||
@ -0,0 +1,50 @@
|
||||
|
||||
|
||||
PROJECT(NfcrdlibEx4_MIFAREClassic)
|
||||
|
||||
|
||||
FILE(GLOB NfcrdlibEx4_MIFAREClassic_Sources
|
||||
*.c
|
||||
src/*.c
|
||||
)
|
||||
|
||||
include_directories(
|
||||
intfs
|
||||
types
|
||||
)
|
||||
|
||||
ADD_EXECUTABLE(NfcrdlibEx4_MIFAREClassic
|
||||
${NfcrdlibEx4_MIFAREClassic_Sources}
|
||||
)
|
||||
|
||||
TARGET_LINK_LIBRARIES(
|
||||
NfcrdlibEx4_MIFAREClassic
|
||||
phOsal
|
||||
DAL
|
||||
NxpRdLib_acDiscLoop
|
||||
NxpRdLib_halHw
|
||||
NxpRdLib_KeyStore
|
||||
NxpRdLib_phTools
|
||||
NxpRdLib_palFelica
|
||||
NxpRdLib_palI18092mPI
|
||||
NxpRdLib_palI14443p4a
|
||||
NxpRdLib_palI14443p4
|
||||
NxpRdLib_palI14443p4
|
||||
NxpRdLib_palMifare
|
||||
NxpRdLib_alFelica
|
||||
NxpRdLib_alMful
|
||||
NxpRdLib_alMfdf
|
||||
NxpRdLib_alT1T
|
||||
NxpRdLib_alTop
|
||||
NxpRdLib_alMfc
|
||||
NxpRdLib_lnLlcp
|
||||
NxpRdLib_phTools
|
||||
NxpRdLib_palI18092mT
|
||||
NxpRdLib_npSnep
|
||||
NxpRdLib_palI14443p4mC
|
||||
NxpRdLib_ceT4T
|
||||
NxpRdLib_palEpcUid
|
||||
NxpRdLib_alMfNtag42XDna
|
||||
NxpRdLib_phNfcLib
|
||||
)
|
||||
|
||||
@ -0,0 +1,245 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3 LTS Patch 2
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
*
|
||||
* The settings in this file configure FreeRTOS correctly for the
|
||||
* given hardware and compiler.
|
||||
*
|
||||
* These settings should not be altered.
|
||||
*-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if ( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
* not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Architecture specifics. */
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Scheduler utilities. */
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
/* Set a PendSV to request a context switch. */ \
|
||||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
|
||||
\
|
||||
/* Barriers are normally not required but do ensure the code is completely \
|
||||
* within the specified behaviour for the architecture. */ \
|
||||
__asm volatile ( "dsb" ::: "memory" ); \
|
||||
__asm volatile ( "isb" ); \
|
||||
}
|
||||
|
||||
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
|
||||
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
|
||||
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
|
||||
#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
|
||||
#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. These are
|
||||
* not necessary for to use this port. They are defined so the common demo files
|
||||
* (which build with all the ports) will build. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Tickless idle/low power functionality. */
|
||||
#ifndef portSUPPRESS_TICKS_AND_SLEEP
|
||||
extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
|
||||
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Architecture specific optimisations. */
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Generic helper function. */
|
||||
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
|
||||
{
|
||||
uint8_t ucReturn;
|
||||
|
||||
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
|
||||
|
||||
return ucReturn;
|
||||
}
|
||||
|
||||
/* Check the configuration. */
|
||||
#if ( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#ifdef configASSERT
|
||||
void vPortValidateInterruptPriority( void );
|
||||
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
|
||||
#endif
|
||||
|
||||
/* portNOP() is not required by this port. */
|
||||
#define portNOP()
|
||||
|
||||
#define portINLINE __inline
|
||||
|
||||
#ifndef portFORCE_INLINE
|
||||
#define portFORCE_INLINE inline __attribute__( ( always_inline ) )
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
|
||||
{
|
||||
uint32_t ulCurrentInterrupt;
|
||||
BaseType_t xReturn;
|
||||
|
||||
/* Obtain the number of the currently executing interrupt. */
|
||||
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
|
||||
|
||||
if( ulCurrentInterrupt == 0 )
|
||||
{
|
||||
xReturn = pdFALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = pdTRUE;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
|
||||
{
|
||||
uint32_t ulNewBASEPRI;
|
||||
|
||||
__asm volatile
|
||||
(
|
||||
" mov %0, %1 \n"\
|
||||
" msr basepri, %0 \n"\
|
||||
" isb \n"\
|
||||
" dsb \n"\
|
||||
: "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
||||
);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
|
||||
{
|
||||
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
|
||||
|
||||
__asm volatile
|
||||
(
|
||||
" mrs %0, basepri \n"\
|
||||
" mov %1, %2 \n"\
|
||||
" msr basepri, %1 \n"\
|
||||
" isb \n"\
|
||||
" dsb \n"\
|
||||
: "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
||||
);
|
||||
|
||||
/* This return will not be reached but is necessary to prevent compiler
|
||||
* warnings. */
|
||||
return ulOriginalBASEPRI;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
" msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
|
||||
);
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
@ -0,0 +1,70 @@
|
||||
/*
|
||||
* @brief LPC17xx/40xx System and Control driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
/* Returns and clears the current sleep mode entry flags */
|
||||
uint32_t Chip_SYSCTL_GetClrSleepFlags(uint32_t flags) {
|
||||
uint32_t savedFlags = LPC_SYSCTL->PCON;
|
||||
|
||||
LPC_SYSCTL->PCON = flags;
|
||||
|
||||
return savedFlags & (SYSCTL_PD_SMFLAG | SYSCTL_PD_DSFLAG |
|
||||
SYSCTL_PD_PDFLAG | SYSCTL_PD_DPDFLAG);
|
||||
}
|
||||
|
||||
#if !defined(CHIP_LPC175X_6X)
|
||||
/* Resets a peripheral */
|
||||
void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_RESET_T periph)
|
||||
{
|
||||
uint32_t bitIndex, regIndex = (uint32_t) periph;
|
||||
|
||||
/* Get register array index and clock index into the register */
|
||||
bitIndex = (regIndex % 32);
|
||||
regIndex = regIndex / 32;
|
||||
|
||||
/* Reset peripheral */
|
||||
LPC_SYSCTL->RSTCON[regIndex] = (1 << bitIndex);
|
||||
LPC_SYSCTL->RSTCON[regIndex] &= ~(1 << bitIndex);
|
||||
}
|
||||
|
||||
#endif /*!defined(CHIP_LPC175X_6X)*/
|
||||
@ -0,0 +1,33 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.5.0
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
|
||||
#warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in a future release.
|
||||
#endif
|
||||
|
||||
#include "stack_macros.h"
|
||||
@ -0,0 +1,123 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2020 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
|
||||
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
|
||||
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
|
||||
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
|
||||
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
|
||||
* The RdLib component initialization requires some user defined data and function pointers.
|
||||
* These are defined in the respective examples and externed here.
|
||||
*
|
||||
* Keystore and Crypto initialization needs to be handled by application.
|
||||
*
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
*/
|
||||
|
||||
/* Status header */
|
||||
#include <ph_Status.h>
|
||||
|
||||
#include "phApp_Init.h"
|
||||
|
||||
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
|
||||
|
||||
#include <phOsal.h>
|
||||
|
||||
#include <phFlashBoot.h>
|
||||
#include <phhalTimer.h>
|
||||
|
||||
/*******************************************************************************
|
||||
** Function Declarations
|
||||
*******************************************************************************/
|
||||
void phApp_CPU_Init(void);
|
||||
|
||||
/*******************************************************************************
|
||||
** Global Variable Declaration
|
||||
*******************************************************************************/
|
||||
phhalHw_PN7462AU_DataParams_t * pHal;
|
||||
|
||||
#ifdef NXPBUILD__PHHAL_HW_TARGET
|
||||
/* Parameters for L3 activation during Autocoll */
|
||||
extern uint8_t sens_res[2] ;
|
||||
extern uint8_t nfc_id1[3] ;
|
||||
extern uint8_t sel_res ;
|
||||
extern uint8_t nfc_id3 ;
|
||||
extern uint8_t poll_res[18] ;
|
||||
#endif /* NXPBUILD__PHHAL_HW_TARGET */
|
||||
|
||||
/*******************************************************************************
|
||||
** Function Definitions
|
||||
*******************************************************************************/
|
||||
/**
|
||||
* This function will initialize NXP NFC Controller.
|
||||
*/
|
||||
void phApp_CPU_Init(void)
|
||||
{
|
||||
phFlashBoot_Main();
|
||||
|
||||
phhalTimer_Init();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initialize Hal Target Config
|
||||
*/
|
||||
phStatus_t phApp_HALConfigAutoColl(void)
|
||||
{
|
||||
#ifdef NXPBUILD__PHHAL_HW_TARGET
|
||||
phStatus_t wStatus;
|
||||
uint8_t bSystemCode[] = {0xFF, 0xFF};
|
||||
|
||||
/* Set Listen Parameters in HAL Buffer used during Autocoll */
|
||||
wStatus = phhalHw_PN7462AU_SetListenParam(
|
||||
pHal,
|
||||
&sens_res[0],
|
||||
&nfc_id1[0],
|
||||
sel_res,
|
||||
(poll_res[0] == 0x02 ? PH_ON : PH_OFF),
|
||||
&poll_res[2],
|
||||
&poll_res[8],
|
||||
bSystemCode);
|
||||
CHECK_SUCCESS(wStatus);
|
||||
#endif /* NXPBUILD__PHHAL_HW_TARGET */
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
/* Configure LPCD (for PN7462AU) */
|
||||
phStatus_t phApp_ConfigureLPCD(void)
|
||||
{
|
||||
phStatus_t status;
|
||||
uint16_t wLpcdValue;
|
||||
|
||||
wLpcdValue = 0;
|
||||
|
||||
status = phhalHw_GetConfig(pHal, PHHAL_HW_CONFIG_PN7462AU_LPCD_NEW_VALUE, &wLpcdValue);
|
||||
CHECK_SUCCESS(status);
|
||||
|
||||
if (wLpcdValue != 0x00)
|
||||
{
|
||||
status = phhalHw_SetConfig(pHal, PHHAL_HW_CONFIG_PN7462AU_LPCD_REF_VALUE, wLpcdValue);
|
||||
CHECK_SUCCESS(status);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@ -0,0 +1,603 @@
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|
||||
<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.738429693.1901050014.1118237901;com.crt.advproject.config.exe.debug.738429693.1901050014.1118237901.;com.crt.advproject.gas.exe.debug.2074064778;com.crt.advproject.assembler.input.306441941">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile" />
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
|
||||
<sdkName>SDK_2.x_FRDM-K82F</sdkName>
|
||||
<sdkVersion>2.6.0</sdkVersion>
|
||||
</storageModule>
|
||||
</cproject>
|
||||
@ -0,0 +1,297 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2009-2023 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Generic ISO14443-4 Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
|
||||
*/
|
||||
|
||||
#ifndef PHPALI14443P4_H
|
||||
#define PHPALI14443P4_H
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <phhalHw.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P4_SW
|
||||
|
||||
/** \defgroup phpalI14443p4_Sw Component : Software
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PHPAL_I14443P4_SW_ID 0x01U /**< ID for Software ISO14443-4 layer */
|
||||
|
||||
/**
|
||||
* \brief ISO14443-4 parameter structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t wId; /**< Layer ID for this component, NEVER MODIFY! */
|
||||
void * pHalDataParams; /**< Pointer to the parameter structure of the underlying layer. */
|
||||
uint8_t bStateNow; /**< Current Exchange-State. */
|
||||
uint8_t bCidEnabled; /**< Card Identifier Enabler; Unequal '0' if enabled. */
|
||||
uint8_t bCid; /**< Card Identifier; Ignored if *pCidSupported is equal '0'. */
|
||||
uint8_t bNadEnabled; /**< Node Address Enabler; Unequal '0' if enabled. */
|
||||
uint8_t bNad; /**< Node Address; Ignored if bNadEnabled is equal '0'. */
|
||||
uint8_t bFwi; /**< Frame Waiting Integer. */
|
||||
uint8_t bFsdi; /**< PCD Frame Size Integer; 0-12; */
|
||||
uint8_t bFsci; /**< PICC Frame Size Integer; 0-12; */
|
||||
uint8_t bPcbBlockNum; /**< Current Block-Number; 0/1; */
|
||||
uint8_t bMaxRetryCount; /**< Maximum Retry count for ISO/IEC 14443-4:2008(E) Rule 4 and 5. */
|
||||
uint8_t bOpeMode; /**< Operation mode. One of NFC, EMVCo, ISO. */
|
||||
} phpalI14443p4_Sw_DataParams_t;
|
||||
|
||||
/**
|
||||
* \brief Initialise this layer.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
*/
|
||||
phStatus_t phpalI14443p4_Sw_Init(
|
||||
phpalI14443p4_Sw_DataParams_t * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wSizeOfDataParams, /**< [In] Specifies the size of the data parameter structure. */
|
||||
void * pHalDataParams /**< [In] Pointer to the parameter structure of the underlying layer. */
|
||||
);
|
||||
|
||||
/** @} */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P4_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P4
|
||||
|
||||
/** \addtogroup ph_Error
|
||||
* phpalI14443p4 Custom Errors
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** \name phpalI14443p4 Error Codes
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I14443P4_ERR_RECOVERY_FAILED ((phStatus_t)PH_ERR_CUSTOM_BEGIN + 0U) /**< ISO14443-4 error recovery failed. */
|
||||
/*@}*/
|
||||
|
||||
/** @} */
|
||||
|
||||
/** \defgroup phpalI14443p4 ISO/IEC 14443-4
|
||||
* \brief These Components implement the ISO/IEC 14443-4:2008(E) contactless protocol.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PHPAL_I14443P4_CID_MAX 14U /**< The last valid CID. */
|
||||
#define PHPAL_I14443P4_FWI_MAX 14U /**< The maximum allowed FWI value. */
|
||||
#define PHPAL_I14443P4_FRAMESIZE_MAX 12U /**< The maximum allowed FSDI/FSCI value. */
|
||||
|
||||
/**
|
||||
* \name ISO14443-4 Parameters
|
||||
*/
|
||||
/*@{*/
|
||||
/**
|
||||
* \brief Set / Get Blocknumber.
|
||||
*/
|
||||
#define PHPAL_I14443P4_CONFIG_BLOCKNO 0x0000U
|
||||
/**
|
||||
* \brief Set / Get Card Identifier.
|
||||
*
|
||||
* \c wValue is parsed as follows:
|
||||
* \verbatim
|
||||
* CidEnabled = (wValue & 0xFF00U) ? 1 : 0;
|
||||
* Cid = (wValue & 0x00FFU);
|
||||
* \endverbatim
|
||||
*/
|
||||
#define PHPAL_I14443P4_CONFIG_CID 0x0001U
|
||||
/**
|
||||
* \brief Set / Get Node Address.
|
||||
*
|
||||
* \c wValue is parsed as follows:
|
||||
* \verbatim
|
||||
* NadEnabled = (wValue & 0xFF00U) ? 1 : 0;
|
||||
* Nad = (wValue & 0x00FFU);
|
||||
* \endverbatim
|
||||
*/
|
||||
#define PHPAL_I14443P4_CONFIG_NAD 0x0002U
|
||||
/**
|
||||
* \brief Set / Get Frame Waiting Integer.
|
||||
*/
|
||||
#define PHPAL_I14443P4_CONFIG_FWI 0x0003U
|
||||
/**
|
||||
* \brief Set / Get PCD & PICC Frame Size Integer.
|
||||
*
|
||||
* \c wValue is parsed as follows:
|
||||
* \verbatim
|
||||
* Fsdi = ((wValue & 0xFF00U) >> 8U);
|
||||
* Fsci = (wValue & 0x00FFU);
|
||||
* \endverbatim
|
||||
*/
|
||||
#define PHPAL_I14443P4_CONFIG_FSI 0x0004U
|
||||
/**
|
||||
* \brief Set / Get Maximum Retry Count.
|
||||
*/
|
||||
#define PHPAL_I14443P4_CONFIG_MAXRETRYCOUNT 0x0005U
|
||||
|
||||
/**
|
||||
* \brief Configure Operation mode.
|
||||
*/
|
||||
|
||||
/**
|
||||
* Configure Operation Mode for this Layer. \n
|
||||
* Possible values are\n
|
||||
* #RD_LIB_MODE_EMVCO, \n
|
||||
* #RD_LIB_MODE_NFC, \n
|
||||
* #RD_LIB_MODE_ISO,\n
|
||||
* Default value is #RD_LIB_MODE_NFC.
|
||||
* */
|
||||
#define PHPAL_I14443P4_CONFIG_OPE_MODE 0x0006U
|
||||
/*@}*/
|
||||
|
||||
#ifdef NXPRDLIB_REM_GEN_INTFS
|
||||
#include "../comps/phpalI14443p4/src/Sw/phpalI14443p4_Sw.h"
|
||||
|
||||
#define phpalI14443p4_SetProtocol( pDataParams, bCidEnable, bCid, bNadEnable, bNad, bFwi, bFsdi, bFsci) \
|
||||
phpalI14443p4_Sw_SetProtocol((phpalI14443p4_Sw_DataParams_t *)pDataParams, bCidEnable, bCid, bNadEnable,bNad, bFwi, bFsdi,bFsci)
|
||||
|
||||
#define phpalI14443p4_ResetProtocol(pDataParams) \
|
||||
phpalI14443p4_Sw_ResetProtocol((phpalI14443p4_Sw_DataParams_t *)pDataParams)
|
||||
|
||||
#define phpalI14443p4_Deselect( pDataParams) \
|
||||
phpalI14443p4_Sw_Deselect((phpalI14443p4_Sw_DataParams_t *)pDataParams)
|
||||
|
||||
#define phpalI14443p4_PresCheck( pDataParams) \
|
||||
phpalI14443p4_Sw_PresCheck((phpalI14443p4_Sw_DataParams_t *)pDataParams)
|
||||
|
||||
#define phpalI14443p4_Exchange( pDataParams, wOption, pTxBuffer, wTxLength, ppRxBuffer, pRxLength) \
|
||||
phpalI14443p4_Sw_Exchange((phpalI14443p4_Sw_DataParams_t *)pDataParams, wOption, pTxBuffer, wTxLength, ppRxBuffer, pRxLength)
|
||||
|
||||
#define phpalI14443p4_SetConfig( pDataParams, wConfig, wValue) \
|
||||
phpalI14443p4_Sw_SetConfig((phpalI14443p4_Sw_DataParams_t *)pDataParams, wConfig, wValue)
|
||||
|
||||
#define phpalI14443p4_GetConfig( pDataParams, wConfig, pValue) \
|
||||
phpalI14443p4_Sw_GetConfig((phpalI14443p4_Sw_DataParams_t *)pDataParams, wConfig, pValue)
|
||||
|
||||
#else
|
||||
|
||||
/**
|
||||
* \brief Set the ISO14443-4 protocol parameters.
|
||||
*
|
||||
* This sets the protocol parameters for this layer.
|
||||
* It is recommended to input this function with the parameters retrieved from either
|
||||
* \ref phpalI14443p4a_GetProtocolParams or \ref phpalI14443p3b_GetProtocolParams respectively after card activation.
|
||||
* \b Note: Refer to the ISO/IEC 14443-4:2008(E) specification for a detailed description of the parameters.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
*/
|
||||
phStatus_t phpalI14443p4_SetProtocol(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bCidEnable, /**< [In] Enable usage of Card Identifier; Unequal '0' if enabled. */
|
||||
uint8_t bCid, /**< [In] Card Identifier; Ignored if \c bCidEnable is equal '0'. */
|
||||
uint8_t bNadEnable, /**< [In] Enabler usage of Node Address; Unequal '0' if enabled. */
|
||||
uint8_t bNad, /**< [In] Node Address; Ignored if bNadEnabled is equal '0'. */
|
||||
uint8_t bFwi, /**< [In] Frame Waiting Integer. */
|
||||
uint8_t bFsdi, /**< [In] PCD Frame Size Integer; 0-12 */
|
||||
uint8_t bFsci /**< [In] PICC Frame Size Integer; 0-12 */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Reset the ISO14443-4 protocol parameters.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
*/
|
||||
phStatus_t phpalI14443p4_ResetProtocol(
|
||||
void * pDataParams /**< [In] Pointer to this layer's parameter structure. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Deselect ISO14443-4 card.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
*/
|
||||
phStatus_t phpalI14443p4_Deselect(
|
||||
void * pDataParams /**< [In] Pointer to this layer's parameter structure. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform presence check for current card. (Perform R(NAK) polling as defined in ISO 14443-4:2008(E)).
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
*/
|
||||
phStatus_t phpalI14443p4_PresCheck(
|
||||
void * pDataParams /**< [In] Pointer to this layer's parameter structure. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform ISO14443-4 Data Exchange with Picc.
|
||||
*
|
||||
* \c wOption can be one of:\n
|
||||
* \li #PH_EXCHANGE_DEFAULT
|
||||
* \li #PH_EXCHANGE_TXCHAINING
|
||||
* \li #PH_EXCHANGE_RXCHAINING
|
||||
* \li #PH_EXCHANGE_RXCHAINING_BUFSIZE
|
||||
*
|
||||
* Additionally, the following options are also available:\n
|
||||
* \li #PH_EXCHANGE_BUFFER_FIRST
|
||||
* \li #PH_EXCHANGE_BUFFER_CONT
|
||||
* \li #PH_EXCHANGE_BUFFER_LAST
|
||||
*
|
||||
* Alternatively to the FIRST/CONT/LAST options, the following bits can be combined:\n
|
||||
* \li #PH_EXCHANGE_BUFFERED_BIT
|
||||
* \li #PH_EXCHANGE_LEAVE_BUFFER_BIT
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p4_Exchange(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wOption, /**< [In] Option parameter. */
|
||||
uint8_t * pTxBuffer, /**< [In] Data to transmit. */
|
||||
uint16_t wTxLength, /**< [In] Length of data to transmit. */
|
||||
uint8_t ** ppRxBuffer, /**< [Out] Pointer to received data. */
|
||||
uint16_t * pRxLength /**< [Out] number of received data bytes. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Set configuration parameter.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p4_SetConfig(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wConfig, /**< [In] Configuration Identifier */
|
||||
uint16_t wValue /**< [In] Configuration Value */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Get configuration parameter.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI14443p4_GetConfig(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wConfig, /**< [In] Configuration Identifier */
|
||||
uint16_t * pValue /**< [Out] Configuration Value */
|
||||
);
|
||||
|
||||
#endif /* NXPRDLIB_REM_GEN_INTFS */
|
||||
/** @} */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P4 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* Extern C */
|
||||
#endif
|
||||
|
||||
#endif /* PHPALI14443P4_H */
|
||||
@ -0,0 +1,254 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2016-2021,2023 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Application specific selection of Reader Library Components
|
||||
*
|
||||
*
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*/
|
||||
|
||||
#ifndef PH_NXPBUILD_APP_H_INC
|
||||
#define PH_NXPBUILD_APP_H_INC
|
||||
|
||||
/** \defgroup ph_NxpBuild NXP Build
|
||||
* \brief Controls the Inclusion of required components, Inclusion SRC/DATA within components and the Build Dependencies between the components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NXPBUILD_DELETE: included code lines should be always removed from code */
|
||||
|
||||
/* NXP BUILD DEFINES */
|
||||
/* use #define to include components */
|
||||
/* comment out #define to exclude components */
|
||||
|
||||
/* DEBUG build mode */
|
||||
/*#define NXPBUILD__PH_DEBUG*/ /**< DEBUG build definition */
|
||||
|
||||
#define NXPRDLIB_REM_GEN_INTFS
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
#if defined(__PN74XXXX__) || defined (__PN73XXXX__)
|
||||
#define NXPBUILD__PHHAL_HW_PN7462AU /**< NFC Controller PN7462AU HAL */
|
||||
#endif
|
||||
|
||||
#ifdef __PN76XX__
|
||||
#ifdef __PN7642__
|
||||
#define NXPBUILD__PHHAL_HW_PN7642 /**< NFC Controller PN7642 HAL */
|
||||
#elif __PN7640__
|
||||
#define NXPBUILD__PHHAL_HW_PN7640 /**< NFC Controller PN7640 HAL */
|
||||
#else
|
||||
#error " PN76 platform definition (__PN7642__ or __PN7640__) missing !!! "
|
||||
#endif
|
||||
|
||||
#if defined(__PN7642__) || defined(__PN7640__)
|
||||
#define NXPBUILD__PHHAL_HW_PN76XX /**< NFC Controller PN76XX HAL */
|
||||
#endif
|
||||
#endif /* __PN76XX__ */
|
||||
|
||||
#if defined(PHDRIVER_LPC1769PN5180_BOARD) \
|
||||
|| defined(PHDRIVER_FRDM_K82FPN5180_BOARD)
|
||||
# define NXPBUILD__PHHAL_HW_PN5180
|
||||
#endif
|
||||
|
||||
#if defined(PHDRIVER_LPC1769PN5190_BOARD) \
|
||||
|| defined(PHDRIVER_K82F_PNEV5190B_BOARD)
|
||||
# define NXPBUILD__PHHAL_HW_PN5190
|
||||
#endif
|
||||
|
||||
#if defined(PHDRIVER_LPC1769RC663_BOARD) \
|
||||
|| defined(PHDRIVER_FRDM_K82FRC663_BOARD)
|
||||
# define NXPBUILD__PHHAL_HW_RC663
|
||||
#endif
|
||||
|
||||
#if defined(NXPBUILD__PHHAL_HW_PN5180) || \
|
||||
defined(NXPBUILD__PHHAL_HW_PN5190) || \
|
||||
defined(NXPBUILD__PHHAL_HW_PN7462AU)
|
||||
// #define NXPBUILD__PHHAL_HW_TARGET /**< Dependency checking if target mode macros should be enabled */
|
||||
#endif
|
||||
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
#define NXPBUILD__PHPAL_I14443P3A_SW /**< PAL ISO 14443-3A SW Component is included. */
|
||||
|
||||
//#define NXPBUILD__PHPAL_I14443P3B_SW /**< PAL ISO 14443-3B SW Component is included. */
|
||||
|
||||
//#define NXPBUILD__PHPAL_I14443P4A_SW /**< PAL ISO 14443-4A SW Component is included. */
|
||||
|
||||
//#define NXPBUILD__PHPAL_I14443P4_SW /**< PAL ISO 14443-4 SW Component is included. */
|
||||
|
||||
//#define NXPBUILD__PHPAL_MIFARE_SW /**< PAL MIFARE SW Component is included */
|
||||
//#define NXPBUILD__PHPAL_MIFARE_STUB /**< PAL MIFARE STUB Component is included */
|
||||
|
||||
//#define NXPBUILD__PHPAL_FELICA_SW /**< PAL Felica SW Component is included. */
|
||||
|
||||
// #define NXPBUILD__PHPAL_SLI15693_SW /**< PAL SLI 15693 Component is included. */
|
||||
// #define NXPBUILD__PHPAL_I18000P3M3_SW /**< PAL ISO 18000p3m3 Component is included. */
|
||||
|
||||
#ifdef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then include EPC UID PAL as required, otherwise exclude. */
|
||||
// #define NXPBUILD__PHPAL_EPCUID_SW /**< PAL EPC UID SW Component is included. */
|
||||
#endif
|
||||
|
||||
//#define NXPBUILD__PHPAL_I18092MPI_SW /**< PAL ISO18092 (P2P) SW Component is included. */
|
||||
|
||||
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then exclude ISO14443 Card Mode PAL & ISO18092 Target Mode PAL, otherwise include as required. */
|
||||
// #define NXPBUILD__PHPAL_I14443P4MC_SW /**< PAL ISO 14443-4 Card Mode SW Component is included. */
|
||||
// #define NXPBUILD__PHPAL_I18092MT_SW /**< PAL ISO 18092 Target Mode SW Component is included. */
|
||||
#endif /* NXPBUILD__PHHAL_HW_RC663 */
|
||||
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
#define NXPBUILD__PHAC_DISCLOOP_SW /**< Discovery Loop Activity SW Component is included. */
|
||||
|
||||
#ifdef NXPBUILD__PHAC_DISCLOOP_SW /**< If DiscLoop SW Component is included, macros( & it's dependencies) to include/exclude SRC/DATA within Discloop is defined. */
|
||||
|
||||
#if defined (NXPBUILD__PHHAL_HW_PN5180) || \
|
||||
defined (NXPBUILD__PHHAL_HW_PN5190) || \
|
||||
defined (NXPBUILD__PHHAL_HW_RC663) || \
|
||||
defined (NXPBUILD__PHHAL_HW_PN7462AU) || \
|
||||
defined (NXPBUILD__PHHAL_HW_PN7642)
|
||||
// #define NXPBUILD__PHAC_DISCLOOP_LPCD /**< SRC to enable LPCD is included. */
|
||||
#endif
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P3_TAGS /**< SRC/DATA to Detect/CollRes/Activate cards such as MFC, MFUL, MFP SL1 etc is included. */
|
||||
// #define NXPBUILD__PHAC_DISCLOOP_TYPEA_JEWEL_TAGS /**< SRC/DATA to Detect cards such as NFC Forum T1T, Topaz/Jewel is included. */
|
||||
|
||||
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) && defined(NXPBUILD__PHPAL_I14443P4_SW)
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS /**< SRC/DATA to Detect cards such as MFDF, MFP, T4AT NFC Forum Tag or Type A EMVCo is included. */
|
||||
#endif
|
||||
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
|
||||
|
||||
#if defined(NXPBUILD__PHPAL_I14443P3A_SW) && defined(NXPBUILD__PHPAL_I18092MPI_SW)
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type A P2P Target mode devices is included. */
|
||||
#endif
|
||||
|
||||
#ifndef NXPBUILD__PHHAL_HW_RC663
|
||||
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE /**< SRC/DATA to Detect Peer Active Type A P2P Target mode devices is included. */
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F212 P2P Target mode devices is included. */
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F424 P2P Target mode devices is included. */
|
||||
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
|
||||
#endif /* NXPBUILD__PHHAL_HW_RC663 */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_FELICA_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_FELICA_TAGS /**< SRC/DATA to Detect FeliCa Cards is included. */
|
||||
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type F P2P Target mode devices is included. */
|
||||
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
|
||||
#endif /* NXPBUILD__PHPAL_FELICA_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P3B_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P3B_TAGS /**< SRC/DATA to Detect Type B Cards that operate at Layer3 level is included */
|
||||
#ifdef NXPBUILD__PHPAL_I14443P4_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P4B_TAGS /**< SRC/DATA to Detect Type B Cards such as NFC Forum Type 4 Tags, EMVCo Type B Cards etc is included */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P4_SW */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P3B_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_SLI15693_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS /**< SRC/DATA to Detect Type V Cards such as ICODE SLI/SLIX/SLI2/Tesa Cards is included*/
|
||||
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS /**< SRC/DATA to Detect ICODE ILT Cards such as SMARTRAC StackIt Cards is included*/
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
|
||||
|
||||
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, target mode is not supported at all, hence exclude those SRC, otherwise include as required */
|
||||
#ifdef NXPBUILD__PHHAL_HW_TARGET
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_PASSIVE /**< SRC to Initialize Type A passive listen config and subsequently call HAL AutoColl is included. */
|
||||
#ifndef NXPBUILD__PHHAL_HW_PN76XX
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_ACTIVE /**< SRC to Initialize Type A active listen config and subsequently call HAL AutoColl is included. */
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_PASSIVE/**< SRC to Initialize Type F212 passive listen config and subsequently call HAL AutoColl is included. */
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_ACTIVE /**< SRC to Initialize Type F212 active listen config and subsequently call HAL AutoColl is included. */
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_PASSIVE/**< SRC to Initialize Type F424 passive listen config and subsequently call HAL AutoColl is included. */
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_ACTIVE /**< SRC to Initialize Type F424 active listen config and subsequently call HAL AutoColl is included. */
|
||||
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
|
||||
#endif /* NXPBUILD__PHHAL_HW_TARGET */
|
||||
#endif
|
||||
|
||||
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
|
||||
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
#define NXPBUILD__PHNFCLIB /**< Simplified API Interface, If enabling this the entry point should be this component in the application */
|
||||
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
//#define NXPBUILD__PH_CIDMANAGER_SW /**< CID Manager SW Component is included. */
|
||||
|
||||
//#define NXPBUILD__PH_KEYSTORE_SW /**< SW KeyStore Component is included. */
|
||||
|
||||
#if defined(NXPBUILD__PHHAL_HW_RC663) && !defined(NXPBUILD__PH_KEYSTORE_SW)
|
||||
// #define NXPBUILD__PH_KEYSTORE_RC663 /**< RC663 KeyStore Component is included. */
|
||||
#endif
|
||||
//#define NXPBUILD__PH_NDA_MFDF /**< MIFARE DESFire contactless IC */
|
||||
//#define NXPBUILD__PH_CRYPTOSYM_SW /**< Crypto Symbols SW Component is included. */
|
||||
//#define NXPBUILD__PH_CRYPTORNG_SW /**< Crypto RNG SW Component is included. */
|
||||
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_FELICA_SW
|
||||
#define NXPBUILD__PHAL_FELICA_SW /**< AL FeliCa SW Component is included */
|
||||
#endif /* NXPBUILD__PHPAL_FELICA_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_MIFARE_SW
|
||||
#if defined(NXPBUILD__PH_KEYSTORE_SW) || defined(NXPBUILD__PH_KEYSTORE_RC663)
|
||||
#define NXPBUILD__PHAL_MFC_SW /**< AL MIFARE Classic contactless IC SW Component is included */
|
||||
#endif
|
||||
#define NXPBUILD__PHAL_MFUL_SW /**< AL Mifare Ultrlight SW Component is included */
|
||||
#define NXPBUILD__PHAL_MFDF_SW /**< AL Mifare DesFire SW Component is included */
|
||||
// #define NXPBUILD__PHAL_MFNTAG42XDNA_SW /**< AL MIFARE Prime Ntag42XDna contactless IC SW Component is included */
|
||||
#endif /* NXPBUILD__PHPAL_MIFARE_SW */
|
||||
|
||||
//#define NXPBUILD__PHAL_T1T_SW /**< AL Type T1 Tag SW Component is included */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_SLI15693_SW
|
||||
#define NXPBUILD__PHAL_ICODE_SW /**< AL ICODE SW COMPONENT is included */
|
||||
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
|
||||
|
||||
//#define NXPBUILD__PHAL_TOP_SW /**< AL for TagOps Mapping SW Component is included.Required for NDEF operations */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
|
||||
#define NXPBUILD__PHAL_I18000P3M3_SW /**< AL ISO18000p3m3 SW Component is included */
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
|
||||
#if !defined(PH_OSAL_NULLOS)
|
||||
#define NXPBUILD__PHCE_T4T_SW /**< AL HCE T2AT SW Component is included */
|
||||
//#define NXPBUILD__PHCE_T4T_PROPRIETARY /**< SRC to handle HCE T4AT Proprietary Commands is included */
|
||||
/*#define NXPBUILD__PHCE_T4T_EXT_NDEF */ /**< SRC to handle Extended NDEF Support as per T4T spec 3.0 is included */
|
||||
#endif
|
||||
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
|
||||
|
||||
/* LLCP Components */
|
||||
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
|
||||
#if !defined(PH_OSAL_NULLOS)
|
||||
#define NXPBUILD__PHLN_LLCP_SW /**< Link LLCP SW Component is included */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* SNEP components */
|
||||
#ifdef NXPBUILD__PHLN_LLCP_SW
|
||||
#define NXPBUILD__PHNP_SNEP_SW /**< Protocol SNEP SW Component is included */
|
||||
#endif /* NXPBUILD__PHLN_LLCP_SW */
|
||||
|
||||
/* Enable/disable Debugging */
|
||||
/*#define NXPBUILD__PH_DEBUG*/ /**< TODO: To be checked if required */
|
||||
|
||||
/** @}
|
||||
* end of ph_NxpBuild
|
||||
*/
|
||||
|
||||
#endif /* PH_NXPBUILD_APP_H_INC */
|
||||
@ -0,0 +1,194 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2009-2020, 2024 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Internal functions of Software implementation of MIFARE (R) Ultralight contactless IC application layer.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* CHu: Generated 05. October 2009
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHALMFUL_INT_H
|
||||
#define PHALMFUL_INT_H
|
||||
|
||||
#include <ph_Status.h>
|
||||
|
||||
/** \addtogroup ph_Private
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** \name MIFARE Ultralight contactless IC error codes. */
|
||||
/** @{ */
|
||||
#define PHAL_MFUL_RESP_ACK 0x0AU /**< MIFARE Ultralight ACK response code */
|
||||
#define PHAL_MFUL_RESP_NAK0 0x00U /**< MIFARE Ultralight NAK0 response code */
|
||||
#define PHAL_MFUL_RESP_NAK1 0x01U /**< MIFARE Ultralight NAK1 response code */
|
||||
#define PHAL_MFUL_RESP_NAK4 0x04U /**< MIFARE Ultralight NAK4 response code */
|
||||
#define PHAL_MFUL_RESP_NAK5 0x05U /**< MIFARE Ultralight NAK5 response code */
|
||||
/** @} */
|
||||
|
||||
/** \name MIFARE Ultralight error codes. */
|
||||
/** @{ */
|
||||
#define PHAL_MFUL_CMD_READ 0x30U /**< MIFARE Ultralight Read command byte */
|
||||
#define PHAL_MFUL_CMD_COMPWRITE 0xA0U /**< MIFARE Ultralight Compatibility Write command byte */
|
||||
#define PHAL_MFUL_CMD_WRITE 0xA2U /**< MIFARE Ultralight Write command byte */
|
||||
#define PHAL_MFUL_CMD_FAST_WRITE 0xA6U /**< MIFARE Ultralight Write command byte */
|
||||
#define PHAL_MFUL_CMD_AUTH 0x1AU /**< MIFARE Ultralight Authenticate command byte */
|
||||
#define PHAL_MFUL_CMD_INCR_CNT 0xA5U /**< MIFARE Ultralight Increment count command byte */
|
||||
#define PHAL_MFUL_CMD_READ_CNT 0x39U /**< MIFARE Ultralight Read counter command byte */
|
||||
#define PHAL_MFUL_CMD_PWD_AUTH 0x1BU /**< MIFARE Ultralight Password Auth command byte */
|
||||
#define PHAL_MFUL_CMD_GET_VER 0x60U /**< MIFARE Ultralight Get version command byte */
|
||||
#define PHAL_MFUL_CMD_FAST_READ 0x3AU /**< MIFARE Ultralight Fast read command byte */
|
||||
#define PHAL_MFUL_CMD_SECTOR_SELECT 0xC2U /**< MIFARE Ultralight SECTOR SELECT command byte */
|
||||
#define PHAL_MFUL_CMD_READ_SIG 0x3CU /**< MIFARE Ultralight Read signature command byte */
|
||||
#define PHAL_MFUL_CMD_CHK_TRG_EVT 0x3EU /**< MIFARE Ultralight Check tearing event command byte */
|
||||
#define PHAL_MFUL_CMD_WRITE_SIGN 0xA9U /**< MIFARE Ultralight Write signature command byte */
|
||||
#define PHAL_MFUL_CMD_LOCK_SIGN 0xACU /**< MIFARE Ultralight Lock signature command byte */
|
||||
#define PHAL_MFUL_CMD_VCSL 0x4BU /**< MIFARE Ultralight Virtual card select command byte */
|
||||
#define PHAL_MFUL_CMD_READ_TT_STATUS 0xA4U /**< MIFARE Ultralight Virtual card select command byte */
|
||||
/** @} */
|
||||
|
||||
#define PHAL_MFUL_NOT_AUTHENTICATED 0xFFU /**< MIFARE Ultralight macro to represent not authenticated state. */
|
||||
#define PHAL_MFUL_PREAMBLE_TX 0xAFU /**< MIFARE Ultralight preamble byte (tx) for authentication. */
|
||||
#define PHAL_MFUL_PREAMBLE_RX 0x00U /**< MIFARE Ultralight preamble byte (rx) for authentication. */
|
||||
|
||||
#define PHAL_MFUL_ORIGINALITY_KEY 0x02U /**< MIFARE Ultralight Originality Check Key. */
|
||||
#define PHAL_MFUL_COMPWRITE_BLOCK_LENGTH 16U /**< Length of a compatibility write MIFARE(R) Ultralight data block. */
|
||||
|
||||
/** @} */
|
||||
|
||||
phStatus_t phalMful_Int_Read(
|
||||
void * pDataParams,
|
||||
uint8_t bAddress,
|
||||
uint8_t * pData
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_Write(
|
||||
void * pDataParams,
|
||||
uint8_t bAddress,
|
||||
uint8_t * pData
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_FastWrite(
|
||||
void * pDataParams,
|
||||
uint8_t * pData
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_CompatibilityWrite(
|
||||
void * pDataParams,
|
||||
uint8_t bAddress,
|
||||
uint8_t * pData
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_IncrCnt(
|
||||
void * pDataParams,
|
||||
uint8_t bCntNum,
|
||||
uint8_t * pCnt
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_ReadCnt(
|
||||
void * pDataParams,
|
||||
uint8_t bCntNum,
|
||||
uint8_t * pCntValue
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_PwdAuth(
|
||||
void * pDataParams,
|
||||
uint8_t * pPwd,
|
||||
uint8_t * pPack
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_GetVersion(
|
||||
void * pDataParams,
|
||||
uint8_t * pVersion
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_FastRead(
|
||||
void * pDataParams,
|
||||
uint8_t bStartAddr,
|
||||
uint8_t bEndAddr,
|
||||
uint8_t ** ppData,
|
||||
uint16_t * pNumBytes
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_SectorSelect(
|
||||
void * pDataParams,
|
||||
uint8_t bSecNo
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_ReadSign(
|
||||
void * pDataParams,
|
||||
uint8_t bAddr,
|
||||
uint8_t ** pSignature,
|
||||
uint16_t* pDataLen
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_ChkTearingEvent(
|
||||
void * pDataParams,
|
||||
uint8_t bCntNum,
|
||||
uint8_t * pValidFlag
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_WriteSign(
|
||||
void * pDataParams,
|
||||
uint8_t bAddress,
|
||||
uint8_t * pSignature
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_LockSign(
|
||||
void * pDataParams,
|
||||
uint8_t bLockMode
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_VirtualCardSelect(
|
||||
void * pDataParams,
|
||||
uint8_t * pVCIID,
|
||||
uint8_t bVCIIDLen,
|
||||
uint8_t * pVCTID
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_ReadTTStatus(
|
||||
void * pDataParams,
|
||||
uint8_t bAddr,
|
||||
uint8_t * pData
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_Exchange (
|
||||
void * pDataParams,
|
||||
uint8_t bCmd,
|
||||
uint8_t * pData,
|
||||
uint8_t bDataLen,
|
||||
uint8_t ** ppResponse,
|
||||
uint16_t * pRespLen );
|
||||
|
||||
phStatus_t phalMful_Int_GetPalMifareDataParams(
|
||||
void * pDataParams,
|
||||
void** pPalMifareDataParams
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_GetCMAC(
|
||||
void * pDataParams,
|
||||
uint8_t* pCMACVal
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_GetAuthMode(
|
||||
void * pDataParams,
|
||||
uint8_t* pAuthMode
|
||||
);
|
||||
|
||||
phStatus_t phalMful_Int_TruncateMac(uint8_t * pMac);
|
||||
|
||||
#endif /* PHALMFUL_INT_H */
|
||||
1470
.svn/pristine/04/0476fe7e0d58be1574974e4fb9a8bc140f4d8ad3.svn-base
Normal file
1470
.svn/pristine/04/0476fe7e0d58be1574974e4fb9a8bc140f4d8ad3.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,597 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _FSL_COMMON_H_
|
||||
#define _FSL_COMMON_H_
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#include <stddef.h>
|
||||
#endif
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup ksdk_common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Construct a status code value from a group and code number. */
|
||||
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
|
||||
|
||||
/*! @brief Construct the version number for drivers. */
|
||||
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief common driver version 2.0.1. */
|
||||
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
|
||||
/*@}*/
|
||||
|
||||
/* Debug console type definition. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
|
||||
|
||||
/*! @brief Status group numbers. */
|
||||
enum _status_groups
|
||||
{
|
||||
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
|
||||
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
|
||||
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
|
||||
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
|
||||
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
|
||||
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
|
||||
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
|
||||
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
|
||||
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
|
||||
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
|
||||
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
|
||||
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
|
||||
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
|
||||
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
|
||||
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
|
||||
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
|
||||
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
|
||||
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
|
||||
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
|
||||
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
|
||||
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
|
||||
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
|
||||
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
|
||||
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
|
||||
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
|
||||
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
|
||||
kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
|
||||
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
|
||||
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
|
||||
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
|
||||
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
|
||||
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
|
||||
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
|
||||
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
|
||||
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
|
||||
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
|
||||
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
|
||||
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
|
||||
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
|
||||
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
|
||||
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
|
||||
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
|
||||
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
|
||||
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
|
||||
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
|
||||
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
|
||||
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
|
||||
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
|
||||
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
|
||||
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
|
||||
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
|
||||
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
|
||||
kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
|
||||
kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
|
||||
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
|
||||
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
|
||||
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
|
||||
kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
|
||||
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
|
||||
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
|
||||
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
|
||||
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
|
||||
kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
|
||||
kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
|
||||
kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */
|
||||
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
|
||||
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
|
||||
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
|
||||
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
|
||||
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
|
||||
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
|
||||
|
||||
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
|
||||
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
|
||||
kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
|
||||
kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
|
||||
kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
|
||||
kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
|
||||
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
|
||||
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
|
||||
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
|
||||
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
|
||||
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
|
||||
kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
|
||||
kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
|
||||
kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
|
||||
kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
|
||||
kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
|
||||
kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
|
||||
kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
|
||||
kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
|
||||
kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */
|
||||
kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
|
||||
kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */
|
||||
};
|
||||
|
||||
/*! @brief Generic status return codes. */
|
||||
enum _generic_status
|
||||
{
|
||||
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
|
||||
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
|
||||
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
|
||||
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
|
||||
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
|
||||
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
|
||||
kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
|
||||
};
|
||||
|
||||
/*! @brief Type used for all status and error return values. */
|
||||
typedef int32_t status_t;
|
||||
|
||||
/*
|
||||
* Macro guard for whether to use default weak IRQ implementation in drivers
|
||||
*/
|
||||
#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
|
||||
#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
|
||||
#endif
|
||||
|
||||
/*! @name Min/max macros */
|
||||
/* @{ */
|
||||
#if !defined(MIN)
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#if !defined(MAX)
|
||||
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @brief Computes the number of elements in an array. */
|
||||
#if !defined(ARRAY_SIZE)
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
#endif
|
||||
|
||||
/*! @name UINT16_MAX/UINT32_MAX value */
|
||||
/* @{ */
|
||||
#if !defined(UINT16_MAX)
|
||||
#define UINT16_MAX ((uint16_t)-1)
|
||||
#endif
|
||||
|
||||
#if !defined(UINT32_MAX)
|
||||
#define UINT32_MAX ((uint32_t)-1)
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @name Timer utilities */
|
||||
/* @{ */
|
||||
/*! Macro to convert a microsecond period to raw count value */
|
||||
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
|
||||
/*! Macro to convert a raw count value to microsecond */
|
||||
#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
|
||||
|
||||
/*! Macro to convert a millisecond period to raw count value */
|
||||
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
|
||||
/*! Macro to convert a raw count value to millisecond */
|
||||
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
|
||||
/* @} */
|
||||
|
||||
/*! @name Alignment variable definition macros */
|
||||
/* @{ */
|
||||
#if (defined(__ICCARM__))
|
||||
/**
|
||||
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
|
||||
* http://supp.iar.com/Support/?note=24725
|
||||
*/
|
||||
_Pragma("diag_suppress=Pm120")
|
||||
#define SDK_PRAGMA(x) _Pragma(#x)
|
||||
_Pragma("diag_error=Pm120")
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
|
||||
#endif
|
||||
#elif defined(__GNUC__)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
|
||||
#endif
|
||||
#else
|
||||
#error Toolchain not supported
|
||||
#define SDK_ALIGN(var, alignbytes) var
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) var
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) var
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! Macro to change a value to a given size aligned value */
|
||||
#define SDK_SIZEALIGN(var, alignbytes) \
|
||||
((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
|
||||
/* @} */
|
||||
|
||||
/*! @name Non-cacheable region definition macros */
|
||||
/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
|
||||
* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
|
||||
* please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
|
||||
* will be initialized to zero in system startup.
|
||||
*/
|
||||
/* @{ */
|
||||
#if (defined(__ICCARM__))
|
||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
||||
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
#endif
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
||||
#endif
|
||||
#elif(defined(__GNUC__))
|
||||
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
|
||||
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
|
||||
*/
|
||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
#endif
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @name Time sensitive region */
|
||||
/* @{ */
|
||||
#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
|
||||
#if (defined(__ICCARM__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
|
||||
#elif(defined(__GNUC__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif /* defined(__ICCARM__) */
|
||||
#else
|
||||
#if (defined(__ICCARM__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
||||
#elif(defined(__GNUC__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif
|
||||
#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
|
||||
/* @} */
|
||||
|
||||
/*! @name Ram Function */
|
||||
#if (defined(__ICCARM__))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
||||
#elif(defined(__GNUC__))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif /* defined(__ICCARM__) */
|
||||
/* @} */
|
||||
|
||||
/*
|
||||
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
|
||||
* defined in previous of this file.
|
||||
*/
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*
|
||||
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
|
||||
*/
|
||||
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
||||
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
||||
#include "fsl_reset.h"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Enable specific interrupt.
|
||||
*
|
||||
* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt enabled successfully
|
||||
* @retval kStatus_Fail Failed to enable the interrupt
|
||||
*/
|
||||
static inline status_t EnableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_EnableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_EnableIRQ(interrupt);
|
||||
#endif
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt.
|
||||
*
|
||||
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt disabled successfully
|
||||
* @retval kStatus_Fail Failed to disable the interrupt
|
||||
*/
|
||||
static inline status_t DisableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_DisableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_DisableIRQ(interrupt);
|
||||
#endif
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the global IRQ
|
||||
*
|
||||
* Disable the global interrupt and return the current primask register. User is required to provided the primask
|
||||
* register for the EnableGlobalIRQ().
|
||||
*
|
||||
* @return Current primask value.
|
||||
*/
|
||||
static inline uint32_t DisableGlobalIRQ(void)
|
||||
{
|
||||
#if defined (__XCC__)
|
||||
return 0;
|
||||
#else
|
||||
#if defined(CPSR_I_Msk)
|
||||
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
|
||||
|
||||
__disable_irq();
|
||||
|
||||
return cpsr;
|
||||
#else
|
||||
uint32_t regPrimask = __get_PRIMASK();
|
||||
|
||||
__disable_irq();
|
||||
|
||||
return regPrimask;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the global IRQ
|
||||
*
|
||||
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
|
||||
* convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
|
||||
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
|
||||
*
|
||||
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
|
||||
* DisableGlobalIRQ().
|
||||
*/
|
||||
static inline void EnableGlobalIRQ(uint32_t primask)
|
||||
{
|
||||
#if defined (__XCC__)
|
||||
#else
|
||||
#if defined(CPSR_I_Msk)
|
||||
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
|
||||
#else
|
||||
__set_PRIMASK(primask);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||
/*!
|
||||
* @brief install IRQ handler
|
||||
*
|
||||
* @param irq IRQ number
|
||||
* @param irqHandler IRQ handler address
|
||||
* @return The old IRQ handler address
|
||||
*/
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
/*!
|
||||
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Enable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Disable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
/*!
|
||||
* @brief Allocate memory with given alignment and aligned size.
|
||||
*
|
||||
* This is provided to support the dynamically allocated memory
|
||||
* used in cache-able region.
|
||||
* @param size The length required to malloc.
|
||||
* @param alignbytes The alignment size.
|
||||
* @retval The allocated memory.
|
||||
*/
|
||||
void *SDK_Malloc(size_t size, size_t alignbytes);
|
||||
|
||||
/*!
|
||||
* @brief Free memory.
|
||||
*
|
||||
* @param ptr The memory to be release.
|
||||
*/
|
||||
void SDK_Free(void *ptr);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_COMMON_H_ */
|
||||
@ -0,0 +1,215 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors Gratkorn / Austria
|
||||
*
|
||||
* (C)NXP Semiconductors
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
*particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Log Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* CHu: Generated 9. October 2009
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHLOG_H
|
||||
#define PHLOG_H
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <ph_TypeDefs.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifdef NXPBUILD__PH_LOG
|
||||
|
||||
/** \defgroup phLog Log
|
||||
*
|
||||
* \brief This layer provides logging and debug functionality.
|
||||
* It is different from the other layers in the way it is initialised.
|
||||
* It stores it's data parameters internally and only once, thus
|
||||
* there can be only one instance.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PH_LOG_DATATYPE_BUFFER 0x00U /**< Data type buffer */
|
||||
#define PH_LOG_DATATYPE_VALUE 0x01U /**< Data type value */
|
||||
|
||||
#define PH_LOG_LOGTYPE_INFO 0x00U /**< Log Type : Info */
|
||||
#define PH_LOG_LOGTYPE_ERROR 0x01U /**< Log Type : Error */
|
||||
#define PH_LOG_LOGTYPE_WARN 0x02U /**< Log Type : Warn */
|
||||
#define PH_LOG_LOGTYPE_DEBUG 0x03U /**< Log Type : Debug */
|
||||
|
||||
#define PH_LOG_OPTION_CATEGORY_ENTER 0x01U /**< Execute Option: Logging takes place at function entry. */
|
||||
#define PH_LOG_OPTION_CATEGORY_GEN 0x02U /**< Execute Option: Logging takes place in the middle of a function. */
|
||||
#define PH_LOG_OPTION_CATEGORY_LEAVE 0x03U /**< Execute Option: Logging takes place before leaving the function. */
|
||||
|
||||
/**
|
||||
* \brief Definition of a singe Log entry
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t bLogType; /**< Type of Entry (one of the \c PH_LOG_LOGTYPE_* values). */
|
||||
uint8_t const * pString; /**< Null-terminated string. */
|
||||
void const * pData; /**< Pointer to the data. */
|
||||
uint16_t wDataLen; /**< Length of the data. */
|
||||
uint8_t bDataType; /**< Indicates the value type (either #PH_LOG_DATATYPE_BUFFER or #PH_LOG_DATATYPE_VALUE). */
|
||||
} phLog_LogEntry_t;
|
||||
|
||||
/**
|
||||
* \brief Definition of a Register Entry
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void * pDataParams; /**< Component for which logging shall be performed. */
|
||||
phLog_LogEntry_t * pLogEntries; /**< An array of \ref phLog_LogEntry_t structures. */
|
||||
uint16_t wNumLogEntries; /**< Number of valid entries within the array. */
|
||||
uint16_t wMaxLogEntries; /**< Number of log entries the \ref phLog_LogEntry_t array can hold. */
|
||||
uint16_t wLogEntriesStart; /**< If a access occures during the log execution this is required */
|
||||
} phLog_RegisterEntry_t;
|
||||
|
||||
/** Function definition for log callback function */
|
||||
typedef void (*pphLog_Callback_t)(void * pDataParams, uint8_t bOption, phLog_LogEntry_t * pLogEntries, uint16_t wEntryCount);
|
||||
|
||||
/**
|
||||
* \brief Log parameter structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
pphLog_Callback_t pLogCallback; /**< Pointer to a log callback function. */
|
||||
phLog_RegisterEntry_t * pRegisterEntries; /**< An array of \ref phLog_RegisterEntry_t structures. */
|
||||
uint16_t wNumRegisterEntries; /**< Number of valid entries within the array. */
|
||||
uint16_t wMaxRegisterEntries; /**< Number of log entries the \ref phLog_RegisterEntry_t array can hold. */
|
||||
} phLog_DataParams_t;
|
||||
|
||||
/**
|
||||
* \brief Allocate space in memory for a \c pString value. \see phLog_LogEnty_t
|
||||
*/
|
||||
#define PH_LOG_ALLOCATE_PARAMNAME(pParam) char const * pParam##_log = #pParam
|
||||
#define PH_LOG_ALLOCATE_TEXT(pIdent, pText) char const * (pIdent) = (pText)
|
||||
|
||||
/**
|
||||
* \brief Initialise Logging.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_INVALID_PARAMETER Input parameter combination is invalid.
|
||||
*/
|
||||
phStatus_t phLog_Init(
|
||||
pphLog_Callback_t pLogCallback, /**< [In] Pointer to a log callback function. */
|
||||
phLog_RegisterEntry_t * pRegisterEntries, /**< [In] An array of \ref phLog_RegisterEntry_t memory. */
|
||||
uint16_t wMaxRegisterEntries /**< [In] Number of log entries the \ref phLog_RegisterEntry_t array can hold. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Register component for logging.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_USE_CONDITION Logging is not properly initialized.
|
||||
* \retval #PH_ERR_INVALID_PARAMETER \c wMaxLogEntries is invalid.
|
||||
* \retval #PH_ERR_BUFFER_OVERFLOW The maximum Register Entry count is reached.
|
||||
*/
|
||||
phStatus_t phLog_Register(
|
||||
void * pDataParams, /**< [In] Component for which logging shall be performed. */
|
||||
phLog_LogEntry_t * pLogEntries, /**< [In] An array of \ref phLog_LogEntry_t structures. */
|
||||
uint16_t wMaxLogEntries /**< [In] Number of log entries the \ref phLog_LogEntry_t array can hold. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Add a new log entry containing just a string. \see phLog_LogEnty_t
|
||||
*/
|
||||
void phLog_AddString(
|
||||
void * pDataParams, /**< [In] The DataParams of the calling function. */
|
||||
uint8_t bLogType, /**< [In] Type of Entry (one of the \c PH_LOG_LOGTYPE_* values). */
|
||||
char const * pString /**< [In] The Null-terminated string to add. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Add a new log entry containing an #uint8_t parameter. \see phLog_LogEnty_t
|
||||
*/
|
||||
void phLog_AddParam_Uint8(
|
||||
void * pDataParams, /**< [In] The DataParams of the calling function. */
|
||||
uint8_t bLogType, /**< [In] Type of Entry (one of the \c PH_LOG_LOGTYPE_* values). */
|
||||
char const * pName, /**< [In] The Null-terminated name of the parameter. */
|
||||
uint8_t * pParam /**< [In] Pointer to the memory where the parameter resides. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Add a new log entry containing an #uint16_t parameter. \see phLog_LogEnty_t
|
||||
*/
|
||||
void phLog_AddParam_Uint16(
|
||||
void * pDataParams, /**< [In] The DataParams of the calling function. */
|
||||
uint8_t bLogType, /**< [In] Type of Entry (one of the \c PH_LOG_LOGTYPE_* values). */
|
||||
char const * pName, /**< [In] The Null-terminated name of the parameter. */
|
||||
uint16_t * pParam /**< [In] Pointer to the memory where the parameter resides. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Add a new log entry containing an #uint32_t parameter. \see phLog_LogEnty_t
|
||||
*/
|
||||
void phLog_AddParam_Uint32(
|
||||
void * pDataParams, /**< [In] The DataParams of the calling function. */
|
||||
uint8_t bLogType, /**< [In] Type of Entry (one of the \c PH_LOG_LOGTYPE_* values). */
|
||||
char const * pName, /**< [In] The Null-terminated name of the parameter. */
|
||||
uint32_t * pParam /**< [In] Pointer to the memory where the parameter resides. */
|
||||
);
|
||||
|
||||
void phLog_AddParam_Uint64(
|
||||
void * pDataParams, /**< [In] The DataParams of the calling function. */
|
||||
uint8_t bLogType, /**< [In] Type of Entry (one of the \c PH_LOG_LOGTYPE_* values). */
|
||||
char const * pName, /**< [In] The Null-terminated name of the parameter. */
|
||||
uint64_t * pParam /**< [In] Pointer to the memory where the parameter resides. */
|
||||
);
|
||||
|
||||
void phLog_AddParam_Int16(
|
||||
void * pDataParams, /**< [In] The DataParams of the calling function. */
|
||||
uint8_t bLogType, /**< [In] Type of Entry (one of the \c PH_LOG_LOGTYPE_* values). */
|
||||
char const * pName, /**< [In] The Null-terminated name of the parameter. */
|
||||
int16_t * pParam /**< [In] Pointer to the memory where the parameter resides. */
|
||||
);
|
||||
|
||||
void phLog_AddParam_Int32(
|
||||
void * pDataParams, /**< [In] The DataParams of the calling function. */
|
||||
uint8_t bLogType, /**< [In] Type of Entry (one of the \c PH_LOG_LOGTYPE_* values). */
|
||||
char const * pName, /**< [In] The Null-terminated name of the parameter. */
|
||||
int32_t * pParam /**< [In] Pointer to the memory where the parameter resides. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Add a new log entry containing a byte-buffer of variable length. \see phLog_LogEnty_t
|
||||
*/
|
||||
void phLog_AddParam_Buffer(
|
||||
void * pDataParams, /**< [In] The DataParams of the calling function. */
|
||||
uint8_t bLogType, /**< [In] Type of Entry (one of the \c PH_LOG_LOGTYPE_* values). */
|
||||
char const * pName, /**< [In] The Null-terminated name of the parameter. */
|
||||
void const * pParam, /**< [In] Pointer to the memory where the parameter resides. */
|
||||
uint16_t wLength /**< [In] The length in bytes to the supplied buffer. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Execute the callback function to process the log buffer.
|
||||
*/
|
||||
void phLog_Execute(
|
||||
void * pDataParams, /**< [In] The DataParams of the calling function. */
|
||||
uint8_t bOption /**< [In] Option byte (one of the PH_LOG_OPTION* defines). */
|
||||
);
|
||||
|
||||
/** @} */
|
||||
#endif /* NXPBUILD__PH_LOG */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* Extern C */
|
||||
#endif
|
||||
|
||||
#endif /* PHLOG_H */
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@ -0,0 +1,344 @@
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<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.738429693.1919901899;com.crt.advproject.config.exe.debug.738429693.1919901899.;com.crt.advproject.gas.exe.debug.1683083229;com.crt.advproject.assembler.input.893302735">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile" />
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.738429693.2136922694;com.crt.advproject.config.exe.debug.738429693.2136922694.;com.crt.advproject.gcc.exe.debug.450971579;com.crt.advproject.compiler.input.924909202">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile" />
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.738429693.1901050014.1118237901;com.crt.advproject.config.exe.debug.738429693.1901050014.1118237901.;com.crt.advproject.gcc.exe.debug.543427012;com.crt.advproject.compiler.input.22295576">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile" />
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.738429693.1901050014.552907120.1244196556;com.crt.advproject.config.exe.debug.738429693.1901050014.552907120.1244196556.;com.crt.advproject.gas.exe.debug.1422642401;com.crt.advproject.assembler.input.247750416">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile" />
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.738429693.2055349940;com.crt.advproject.config.exe.debug.738429693.2055349940.;com.crt.advproject.gcc.exe.debug.1017520906;com.crt.advproject.compiler.input.518769024">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile" />
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.738429693.1901050014.1118237901;com.crt.advproject.config.exe.debug.738429693.1901050014.1118237901.;com.crt.advproject.gas.exe.debug.2074064778;com.crt.advproject.assembler.input.306441941">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile" />
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
|
||||
<sdkName>SDK_2.x_FRDM-K82F</sdkName>
|
||||
<sdkVersion>2.6.0</sdkVersion>
|
||||
</storageModule>
|
||||
</cproject>
|
||||
@ -0,0 +1,98 @@
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_PORT_INTERNAL_H__
|
||||
#define __SERIAL_PORT_INTERNAL_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
|
||||
serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);
|
||||
serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_UartIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
|
||||
serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);
|
||||
serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
|
||||
serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);
|
||||
serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#endif
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_SwoIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
|
||||
serial_manager_status_t Serial_UsbCdcVirtualInit(serial_handle_t serialHandle, void *config);
|
||||
serial_manager_status_t Serial_UsbCdcVirtualDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UsbCdcVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_UsbCdcVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_UsbCdcVirtualCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UsbCdcVirtualInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_UsbCdcVirtualInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_UsbCdcVirtualIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SERIAL_PORT_INTERNAL_H__ */
|
||||
@ -0,0 +1,107 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2016-2022 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** @file
|
||||
* File used to implement Callback/Hooks required for FreeRTOS.
|
||||
* $Author: NXP $
|
||||
* $Revision: $
|
||||
* $Date: $
|
||||
*
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------------
|
||||
* Includes
|
||||
---------------------------------------------------------------------------------------------*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <task.h>
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Stack overflow hook. */
|
||||
void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName)
|
||||
{
|
||||
/* Force an assert. */
|
||||
configASSERT(pcTaskName == 0);
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an
|
||||
* implementation of vApplicationGetIdleTaskMemory() to provide the memory that
|
||||
* is used by the Idle task. */
|
||||
void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
|
||||
StackType_t ** ppxIdleTaskStackBuffer,
|
||||
uint32_t * pulIdleTaskStackSize )
|
||||
{
|
||||
/* If the buffers to be provided to the Idle task are declared inside this
|
||||
* function then they must be declared static - otherwise they will be
|
||||
* allocated on the stack and so not exists after this function exits. */
|
||||
static StaticTask_t xIdleTaskTCB;
|
||||
static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
|
||||
|
||||
/* Pass out a pointer to the StaticTask_t structure in which the Idle
|
||||
* task's state will be stored. */
|
||||
*ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
|
||||
|
||||
/* Pass out the array that will be used as the Idle task's stack. */
|
||||
*ppxIdleTaskStackBuffer = uxIdleTaskStack;
|
||||
|
||||
/* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
|
||||
* Note that, as the array is necessarily of type StackType_t,
|
||||
* configMINIMAL_STACK_SIZE is specified in words, not bytes. */
|
||||
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
|
||||
* application must provide an implementation of vApplicationGetTimerTaskMemory()
|
||||
* to provide the memory that is used by the Timer service task. */
|
||||
void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
|
||||
StackType_t ** ppxTimerTaskStackBuffer,
|
||||
uint32_t * pulTimerTaskStackSize )
|
||||
{
|
||||
/* If the buffers to be provided to the Timer task are declared inside this
|
||||
* function then they must be declared static - otherwise they will be
|
||||
* allocated on the stack and so not exists after this function exits. */
|
||||
static StaticTask_t xTimerTaskTCB;
|
||||
static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__( ( aligned( 32 ) ) );
|
||||
|
||||
/* Pass out a pointer to the StaticTask_t structure in which the Timer
|
||||
* task's state will be stored. */
|
||||
*ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
|
||||
|
||||
/* Pass out the array that will be used as the Timer task's stack. */
|
||||
*ppxTimerTaskStackBuffer = uxTimerTaskStack;
|
||||
|
||||
/* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
|
||||
* Note that, as the array is necessarily of type StackType_t,
|
||||
* configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
|
||||
*pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationMallocFailedHook(void)
|
||||
{
|
||||
/* vApplicationMallocFailedHook() will only be called if
|
||||
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
|
||||
function that will get called if a call to pvPortMalloc() fails.
|
||||
pvPortMalloc() is called internally by the kernel whenever a task, queue,
|
||||
timer or semaphore is created. It is also called by various parts of the
|
||||
demo application. If heap_1.c or heap_2.c are used, then the size of the
|
||||
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
|
||||
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
|
||||
to query the size of free heap space that remains (although it does not
|
||||
provide information on how the remaining heap might be fragmented). */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
@ -0,0 +1,116 @@
|
||||
/*
|
||||
* @brief LPC17xx/40xx 16/32-bit Timer/PWM driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Returns clock for the peripheral block */
|
||||
STATIC CHIP_SYSCTL_CLOCK_T Chip_Timer_GetClockIndex(LPC_TIMER_T *pTMR)
|
||||
{
|
||||
CHIP_SYSCTL_CLOCK_T clkTMR;
|
||||
|
||||
if (pTMR == LPC_TIMER1) {
|
||||
clkTMR = SYSCTL_CLOCK_TIMER1;
|
||||
}
|
||||
else if (pTMR == LPC_TIMER2) {
|
||||
clkTMR = SYSCTL_CLOCK_TIMER2;
|
||||
}
|
||||
else if (pTMR == LPC_TIMER3) {
|
||||
clkTMR = SYSCTL_CLOCK_TIMER3;
|
||||
}
|
||||
else {
|
||||
clkTMR = SYSCTL_CLOCK_TIMER0;
|
||||
}
|
||||
|
||||
return clkTMR;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Initialize a timer */
|
||||
void Chip_TIMER_Init(LPC_TIMER_T *pTMR)
|
||||
{
|
||||
Chip_Clock_EnablePeriphClock(Chip_Timer_GetClockIndex(pTMR));
|
||||
}
|
||||
|
||||
/* Shutdown a timer */
|
||||
void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR)
|
||||
{
|
||||
Chip_Clock_DisablePeriphClock(Chip_Timer_GetClockIndex(pTMR));
|
||||
}
|
||||
|
||||
/* Resets the timer terminal and prescale counts to 0 */
|
||||
void Chip_TIMER_Reset(LPC_TIMER_T *pTMR)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
/* Disable timer, set terminal count to non-0 */
|
||||
reg = pTMR->TCR;
|
||||
pTMR->TCR = 0;
|
||||
pTMR->TC = 1;
|
||||
|
||||
/* Reset timer counter */
|
||||
pTMR->TCR = TIMER_RESET;
|
||||
|
||||
/* Wait for terminal count to clear */
|
||||
while (pTMR->TC != 0) {}
|
||||
|
||||
/* Restore timer state */
|
||||
pTMR->TCR = reg;
|
||||
}
|
||||
|
||||
/* Sets external match control (MATn.matchnum) pin control */
|
||||
void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
|
||||
TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum)
|
||||
{
|
||||
uint32_t mask, reg;
|
||||
|
||||
/* Clear bits corresponding to selected match register */
|
||||
mask = (1 << matchnum) | (0x03 << (4 + (matchnum * 2)));
|
||||
reg = pTMR->EMR &= ~mask;
|
||||
|
||||
/* Set new configuration for selected match register */
|
||||
pTMR->EMR = reg | (((uint32_t) initial_state) << matchnum) |
|
||||
(((uint32_t) matchState) << (4 + (matchnum * 2)));
|
||||
}
|
||||
@ -0,0 +1,314 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors
|
||||
*
|
||||
* (C) NXP Semiconductors 2014
|
||||
*
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
* particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** @file
|
||||
*
|
||||
* phTools_Q.c: <The purpose and scope of this file>
|
||||
*
|
||||
* Project: NxpNfcRdLib
|
||||
*
|
||||
* $Date$
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
*/
|
||||
|
||||
/* *****************************************************************************************************************
|
||||
* Includes
|
||||
* ***************************************************************************************************************** */
|
||||
|
||||
#include "ph_NxpBuild.h"
|
||||
#include <ph_Status.h>
|
||||
#include <phOsal.h>
|
||||
#include <phTools.h>
|
||||
|
||||
/* *****************************************************************************************************************
|
||||
* Global and Static Variables
|
||||
* Total Size: NNNbytes
|
||||
* ***************************************************************************************************************** */
|
||||
static phOsal_MutexObj_t gphTools_Q_Mutex;
|
||||
static phOsal_MutexObj_t gphTools_Q_MsgMutex;
|
||||
static phOsal_SemObj_t gphTools_Q_MsgSema;
|
||||
|
||||
static phTools_Q_t gsphTools_Q_Pool[PH_TOOLS_Q_MAX_ELEMENTS];
|
||||
static phTools_Q_t *gpphTools_Q_PoolHead;
|
||||
static phTools_Q_t *gpphTools_Q_Msgs;
|
||||
static uint8_t bQCount;
|
||||
|
||||
static const uint8_t bToolsxSemaName[] = "ToolsxSema";
|
||||
/* *****************************************************************************************************************
|
||||
* Private Functions
|
||||
* ***************************************************************************************************************** */
|
||||
static phStatus_t phTools_Q_SendInt(phTools_Q_t *psMsgQueue, uint8_t bFront, uint32_t dwBlockTime, uint16_t wFrameOpt);
|
||||
static phTools_Q_t* phTools_Q_PopInt(phTools_Q_t **ppQHead, phOsal_Mutex_t pMutex, uint32_t dwBlockTime, uint8_t bPriority);
|
||||
static void phTools_Q_Push(phTools_Q_t **ppsQHead, phTools_Q_t *psMsgQueue, uint8_t bFront);
|
||||
|
||||
/* *****************************************************************************************************************
|
||||
* Public Functions
|
||||
* ***************************************************************************************************************** */
|
||||
|
||||
phStatus_t phTools_Q_Init(void)
|
||||
{
|
||||
uint8_t count;
|
||||
phTools_Q_t *psQueue = NULL;
|
||||
phStatus_t bRetstatus = PH_ERR_INTERNAL_ERROR;
|
||||
|
||||
bQCount = 0;
|
||||
gpphTools_Q_Msgs = NULL;
|
||||
gpphTools_Q_PoolHead = gsphTools_Q_Pool;
|
||||
psQueue = gsphTools_Q_Pool;
|
||||
gphTools_Q_MsgSema.pSemName = (uint8_t *)bToolsxSemaName;
|
||||
gphTools_Q_MsgSema.semInitialCount = 0;
|
||||
gphTools_Q_MsgSema.semMaxCount = PH_TOOLS_Q_MAX_ELEMENTS;
|
||||
|
||||
PH_CHECK_SUCCESS_FCT(bRetstatus,phOsal_SemCreate(&gphTools_Q_MsgSema.SemHandle, &gphTools_Q_MsgSema, E_OS_SEM_OPT_COUNTING_SEM));
|
||||
if(gphTools_Q_MsgSema.SemHandle == NULL)
|
||||
{
|
||||
return (PH_ERR_RESOURCE_ERROR | PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
PH_CHECK_SUCCESS_FCT(bRetstatus,phOsal_MutexCreate(&gphTools_Q_Mutex.MutexHandle,&gphTools_Q_Mutex));
|
||||
if(gphTools_Q_Mutex.MutexHandle == NULL)
|
||||
{
|
||||
return (PH_ERR_RESOURCE_ERROR | PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
PH_CHECK_SUCCESS_FCT(bRetstatus,phOsal_MutexCreate(&gphTools_Q_MsgMutex.MutexHandle,&gphTools_Q_MsgMutex));
|
||||
if(gphTools_Q_Mutex.MutexHandle == NULL)
|
||||
{
|
||||
return (PH_ERR_RESOURCE_ERROR | PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
for(count = 1; count < PH_TOOLS_Q_MAX_ELEMENTS; count++)
|
||||
{
|
||||
psQueue->pNext = &gsphTools_Q_Pool[count];
|
||||
psQueue = psQueue->pNext;
|
||||
}
|
||||
psQueue->pNext = NULL;
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phTools_Q_t *phTools_Q_Receive(uint32_t dwBlockTime)
|
||||
{
|
||||
phStatus_t bRetstatus;
|
||||
phOsal_TimerPeriodObj_t timePeriodToWait;
|
||||
|
||||
timePeriodToWait.unitPeriod = OS_TIMER_UNIT_MSEC;
|
||||
timePeriodToWait.period = dwBlockTime;
|
||||
|
||||
/* wait for incoming messages */
|
||||
bRetstatus = phOsal_SemPend(&gphTools_Q_MsgSema.SemHandle, timePeriodToWait);
|
||||
if (bRetstatus != PH_ERR_SUCCESS)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return phTools_Q_PopInt(&gpphTools_Q_Msgs, gphTools_Q_MsgMutex.MutexHandle, dwBlockTime, PH_ON);
|
||||
}
|
||||
|
||||
phTools_Q_t *phTools_Q_Get(uint32_t dwBlockTime, uint8_t bPriority)
|
||||
{
|
||||
phTools_Q_t *pEmptyMsg = phTools_Q_PopInt(&gpphTools_Q_PoolHead, gphTools_Q_Mutex.MutexHandle, dwBlockTime, bPriority);
|
||||
|
||||
if(pEmptyMsg == NULL)
|
||||
{
|
||||
return pEmptyMsg;
|
||||
}
|
||||
|
||||
pEmptyMsg->pNext = NULL;
|
||||
|
||||
return pEmptyMsg;
|
||||
}
|
||||
|
||||
static phTools_Q_t *phTools_Q_PopInt(phTools_Q_t **ppQHead, phOsal_Mutex_t pMutex, uint32_t dwBlockTime, uint8_t bPriority)
|
||||
{
|
||||
void *pQueue;
|
||||
phOsal_TimerPeriodObj_t timePeriodToWait;
|
||||
|
||||
phStatus_t bRetstatus;
|
||||
|
||||
timePeriodToWait.unitPeriod = OS_TIMER_UNIT_MSEC;
|
||||
timePeriodToWait.period = dwBlockTime;
|
||||
|
||||
bRetstatus = phOsal_MutexLock(&pMutex, timePeriodToWait);
|
||||
if (bRetstatus != PH_ERR_SUCCESS)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if((bPriority == PH_OFF) && (bQCount >= (PH_TOOLS_Q_MAX_ELEMENTS - PH_TOOLS_Q_RESERVED_ELEMENTS)) && (pMutex == gphTools_Q_Mutex.MutexHandle))
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Get a msg Queue from the pool */
|
||||
if(*ppQHead == NULL)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
pQueue = *ppQHead;
|
||||
*ppQHead = (*ppQHead)->pNext;
|
||||
|
||||
if(pMutex == gphTools_Q_Mutex.MutexHandle)
|
||||
{
|
||||
bQCount++;
|
||||
}
|
||||
|
||||
bRetstatus = phOsal_MutexUnLock(&pMutex);
|
||||
if (bRetstatus != PH_ERR_SUCCESS)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return pQueue;
|
||||
}
|
||||
|
||||
phStatus_t phTools_Q_Release(phTools_Q_t *psMsgQueue, uint32_t dwBlockTime)
|
||||
{
|
||||
phStatus_t wStatus;
|
||||
phStatus_t bRetstatus = PH_ERR_INTERNAL_ERROR;
|
||||
phOsal_TimerPeriodObj_t timePeriodToWait;
|
||||
|
||||
psMsgQueue->pNext = NULL;
|
||||
psMsgQueue->bType = 0U;
|
||||
timePeriodToWait.unitPeriod = OS_TIMER_UNIT_MSEC;
|
||||
timePeriodToWait.period = dwBlockTime;
|
||||
|
||||
PH_CHECK_SUCCESS_FCT(bRetstatus, phOsal_MutexLock(&gphTools_Q_Mutex.MutexHandle, timePeriodToWait));
|
||||
|
||||
if(gpphTools_Q_PoolHead == NULL)
|
||||
{
|
||||
gpphTools_Q_PoolHead = psMsgQueue;
|
||||
gpphTools_Q_PoolHead->pNext = NULL;
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
psMsgQueue->pNext = gpphTools_Q_PoolHead;
|
||||
gpphTools_Q_PoolHead = psMsgQueue;
|
||||
bQCount--;
|
||||
PH_CHECK_SUCCESS_FCT(wStatus, phOsal_MutexUnLock(&gphTools_Q_Mutex.MutexHandle));
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
static phStatus_t phTools_Q_SendInt(phTools_Q_t *psMsgQueue, uint8_t bFront, uint32_t dwBlockTime, uint16_t wFrameOpt)
|
||||
{
|
||||
static uint8_t bNoOfMsgs = 0;
|
||||
uint8_t i;
|
||||
phStatus_t bRetstatus = PH_ERR_INTERNAL_ERROR;
|
||||
phOsal_TimerPeriodObj_t timePeriodToWait;
|
||||
|
||||
timePeriodToWait.unitPeriod = OS_TIMER_UNIT_MSEC;
|
||||
timePeriodToWait.period = dwBlockTime;
|
||||
|
||||
/* Shared memory pool, Mutex protected until all the fragments are queued. */
|
||||
if((wFrameOpt == PH_TRANSMIT_BUFFER_FIRST) || (wFrameOpt == PH_TRANSMIT_DEFAULT))
|
||||
{
|
||||
bNoOfMsgs = 1;
|
||||
PH_CHECK_SUCCESS_FCT(bRetstatus,phOsal_MutexLock(&gphTools_Q_MsgMutex.MutexHandle, timePeriodToWait));
|
||||
}
|
||||
else
|
||||
{
|
||||
bNoOfMsgs++;
|
||||
}
|
||||
|
||||
phTools_Q_Push(&gpphTools_Q_Msgs, psMsgQueue, bFront);
|
||||
|
||||
/* Check for the last fragment to be queued, post the semaphore. */
|
||||
if((wFrameOpt == PH_TRANSMIT_BUFFER_LAST) || (wFrameOpt == PH_TRANSMIT_DEFAULT))
|
||||
{
|
||||
/* TODO: chk for posting single semaphore instead multi No of Semaphore. */
|
||||
for(i=0; i<bNoOfMsgs;i++)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(bRetstatus, phOsal_SemPost(&gphTools_Q_MsgSema.SemHandle, E_OS_SEM_OPT_NONE));
|
||||
}
|
||||
PH_CHECK_SUCCESS_FCT(bRetstatus, phOsal_MutexUnLock(&gphTools_Q_MsgMutex.MutexHandle));
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phTools_Q_Send(
|
||||
phTools_Q_t* psMsgQueue,
|
||||
uint32_t dwBlockTime,
|
||||
uint16_t wFrameOpt
|
||||
)
|
||||
{
|
||||
return phTools_Q_SendInt(psMsgQueue, (uint8_t)PH_OFF, dwBlockTime, wFrameOpt);
|
||||
}
|
||||
|
||||
phStatus_t phTools_Q_SendFront(
|
||||
phTools_Q_t* psMsgQueue,
|
||||
uint32_t dwBlockTime,
|
||||
uint16_t wFrameOpt
|
||||
)
|
||||
{
|
||||
return phTools_Q_SendInt(psMsgQueue, (uint8_t)PH_ON, dwBlockTime, wFrameOpt);
|
||||
}
|
||||
|
||||
static void phTools_Q_Push(phTools_Q_t **ppsQHead, phTools_Q_t *psMsgQueue, uint8_t bFront)
|
||||
{
|
||||
phTools_Q_t *psQList = NULL;
|
||||
|
||||
psMsgQueue->pNext = NULL;
|
||||
|
||||
if(*ppsQHead == NULL)
|
||||
{
|
||||
*ppsQHead = psMsgQueue;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Queue to the head */
|
||||
if(bFront == PH_ON)
|
||||
{
|
||||
psMsgQueue->pNext = *ppsQHead;
|
||||
*ppsQHead = psMsgQueue;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Queue to the tail */
|
||||
psQList = *ppsQHead;
|
||||
while(psQList->pNext != NULL)
|
||||
{
|
||||
psQList = psQList->pNext;
|
||||
}
|
||||
psQList->pNext = psMsgQueue;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void phTools_Q_DeInit(void)
|
||||
{
|
||||
gpphTools_Q_PoolHead = NULL;
|
||||
bQCount = 0;
|
||||
|
||||
/* Release the acquired memory. */
|
||||
if (gphTools_Q_Mutex.MutexHandle != NULL)
|
||||
{
|
||||
(void)phOsal_MutexDelete(&gphTools_Q_Mutex.MutexHandle);
|
||||
gphTools_Q_Mutex.MutexHandle = NULL;
|
||||
}
|
||||
if (gphTools_Q_MsgMutex.MutexHandle != NULL)
|
||||
{
|
||||
(void)phOsal_MutexDelete(&gphTools_Q_MsgMutex.MutexHandle);
|
||||
gphTools_Q_MsgMutex.MutexHandle = NULL;
|
||||
}
|
||||
if (gphTools_Q_MsgSema.SemHandle != NULL)
|
||||
{
|
||||
(void)phOsal_SemDelete(&gphTools_Q_MsgSema.SemHandle);
|
||||
gphTools_Q_MsgSema.SemHandle = NULL;
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,270 @@
|
||||
/*
|
||||
* @brief SMSC 87x0 simple PHY driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2012
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
#include "lpc_phy.h"
|
||||
|
||||
/** @defgroup SMSC87X0_PHY BOARD: PHY status and control driver for the SMSC 87x0
|
||||
* @ingroup BOARD_PHY
|
||||
* Various functions for controlling and monitoring the status of the
|
||||
* SMSC 87x0 PHY.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* LAN8720 PHY register offsets */
|
||||
#define LAN8_BCR_REG 0x0 /*!< Basic Control Register */
|
||||
#define LAN8_BSR_REG 0x1 /*!< Basic Status Reg */
|
||||
#define LAN8_PHYID1_REG 0x2 /*!< PHY ID 1 Reg */
|
||||
#define LAN8_PHYID2_REG 0x3 /*!< PHY ID 2 Reg */
|
||||
#define LAN8_PHYSPLCTL_REG 0x1F/*!< PHY special control/status Reg */
|
||||
|
||||
/* LAN8720 BCR register definitions */
|
||||
#define LAN8_RESET (1 << 15) /*!< 1= S/W Reset */
|
||||
#define LAN8_LOOPBACK (1 << 14) /*!< 1=loopback Enabled */
|
||||
#define LAN8_SPEED_SELECT (1 << 13) /*!< 1=Select 100MBps */
|
||||
#define LAN8_AUTONEG (1 << 12) /*!< 1=Enable auto-negotiation */
|
||||
#define LAN8_POWER_DOWN (1 << 11) /*!< 1=Power down PHY */
|
||||
#define LAN8_ISOLATE (1 << 10) /*!< 1=Isolate PHY */
|
||||
#define LAN8_RESTART_AUTONEG (1 << 9) /*!< 1=Restart auto-negoatiation */
|
||||
#define LAN8_DUPLEX_MODE (1 << 8) /*!< 1=Full duplex mode */
|
||||
|
||||
/* LAN8720 BSR register definitions */
|
||||
#define LAN8_100BASE_T4 (1 << 15) /*!< T4 mode */
|
||||
#define LAN8_100BASE_TX_FD (1 << 14) /*!< 100MBps full duplex */
|
||||
#define LAN8_100BASE_TX_HD (1 << 13) /*!< 100MBps half duplex */
|
||||
#define LAN8_10BASE_T_FD (1 << 12) /*!< 100Bps full duplex */
|
||||
#define LAN8_10BASE_T_HD (1 << 11) /*!< 10MBps half duplex */
|
||||
#define LAN8_AUTONEG_COMP (1 << 5) /*!< Auto-negotation complete */
|
||||
#define LAN8_RMT_FAULT (1 << 4) /*!< Fault */
|
||||
#define LAN8_AUTONEG_ABILITY (1 << 3) /*!< Auto-negotation supported */
|
||||
#define LAN8_LINK_STATUS (1 << 2) /*!< 1=Link active */
|
||||
#define LAN8_JABBER_DETECT (1 << 1) /*!< Jabber detect */
|
||||
#define LAN8_EXTEND_CAPAB (1 << 0) /*!< Supports extended capabilities */
|
||||
|
||||
/* LAN8720 PHYSPLCTL status definitions */
|
||||
#define LAN8_SPEEDMASK (7 << 2) /*!< Speed and duplex mask */
|
||||
#define LAN8_SPEED100F (6 << 2) /*!< 100BT full duplex */
|
||||
#define LAN8_SPEED10F (5 << 2) /*!< 10BT full duplex */
|
||||
#define LAN8_SPEED100H (2 << 2) /*!< 100BT half duplex */
|
||||
#define LAN8_SPEED10H (1 << 2) /*!< 10BT half duplex */
|
||||
|
||||
/* LAN8720 PHY ID 1/2 register definitions */
|
||||
#define LAN8_PHYID1_OUI 0x0007 /*!< Expected PHY ID1 */
|
||||
#define LAN8_PHYID2_OUI 0xC0F0 /*!< Expected PHY ID2, except last 4 bits */
|
||||
|
||||
/* DP83848 PHY update flags */
|
||||
static uint32_t physts, olddphysts;
|
||||
|
||||
/* PHY update counter for state machine */
|
||||
static int32_t phyustate;
|
||||
|
||||
/* Pointer to delay function used for this driver */
|
||||
static p_msDelay_func_t pDelayMs;
|
||||
|
||||
/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns
|
||||
true on success, or false on failure */
|
||||
static Status lpc_mii_write(uint8_t reg, uint16_t data)
|
||||
{
|
||||
Status sts = ERROR;
|
||||
int32_t mst = 250;
|
||||
|
||||
/* Write value for register */
|
||||
Chip_ENET_StartMIIWrite(LPC_ETHERNET, reg, data);
|
||||
|
||||
/* Wait for unbusy status */
|
||||
while (mst > 0) {
|
||||
if (Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
|
||||
mst--;
|
||||
pDelayMs(1);
|
||||
}
|
||||
else {
|
||||
mst = 0;
|
||||
sts = SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
return sts;
|
||||
}
|
||||
|
||||
/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns
|
||||
true on success, or false on failure */
|
||||
static Status lpc_mii_read(uint8_t reg, uint16_t *data)
|
||||
{
|
||||
Status sts = ERROR;
|
||||
int32_t mst = 250;
|
||||
|
||||
/* Start register read */
|
||||
Chip_ENET_StartMIIRead(LPC_ETHERNET, reg);
|
||||
|
||||
/* Wait for unbusy status */
|
||||
while (mst > 0) {
|
||||
if (!Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
|
||||
mst = 0;
|
||||
*data = Chip_ENET_ReadMIIData(LPC_ETHERNET);
|
||||
sts = SUCCESS;
|
||||
}
|
||||
else {
|
||||
mst--;
|
||||
pDelayMs(1);
|
||||
}
|
||||
}
|
||||
|
||||
return sts;
|
||||
}
|
||||
|
||||
/* Update PHY status from passed value */
|
||||
static void smsc_update_phy_sts(uint16_t linksts, uint16_t sdsts)
|
||||
{
|
||||
/* Update link active status */
|
||||
if (linksts & LAN8_LINK_STATUS) {
|
||||
physts |= PHY_LINK_CONNECTED;
|
||||
}
|
||||
else {
|
||||
physts &= ~PHY_LINK_CONNECTED;
|
||||
}
|
||||
|
||||
switch (sdsts & LAN8_SPEEDMASK) {
|
||||
case LAN8_SPEED100F:
|
||||
default:
|
||||
physts |= PHY_LINK_SPEED100;
|
||||
physts |= PHY_LINK_FULLDUPLX;
|
||||
break;
|
||||
|
||||
case LAN8_SPEED10F:
|
||||
physts &= ~PHY_LINK_SPEED100;
|
||||
physts |= PHY_LINK_FULLDUPLX;
|
||||
break;
|
||||
|
||||
case LAN8_SPEED100H:
|
||||
physts |= PHY_LINK_SPEED100;
|
||||
physts &= ~PHY_LINK_FULLDUPLX;
|
||||
break;
|
||||
|
||||
case LAN8_SPEED10H:
|
||||
physts &= ~PHY_LINK_SPEED100;
|
||||
physts &= ~PHY_LINK_FULLDUPLX;
|
||||
break;
|
||||
}
|
||||
|
||||
/* If the status has changed, indicate via change flag */
|
||||
if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) !=
|
||||
(olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) {
|
||||
olddphysts = physts;
|
||||
physts |= PHY_LINK_CHANGED;
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialize the SMSC 87x0 PHY */
|
||||
uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc)
|
||||
{
|
||||
uint16_t tmp;
|
||||
int32_t i;
|
||||
|
||||
pDelayMs = pDelayMsFunc;
|
||||
|
||||
/* Initial states for PHY status and state machine */
|
||||
olddphysts = physts = phyustate = 0;
|
||||
|
||||
/* Only first read and write are checked for failure */
|
||||
/* Put the DP83848C in reset mode and wait for completion */
|
||||
if (lpc_mii_write(LAN8_BCR_REG, LAN8_RESET) != SUCCESS) {
|
||||
return ERROR;
|
||||
}
|
||||
i = 400;
|
||||
while (i > 0) {
|
||||
pDelayMs(1);
|
||||
if (lpc_mii_read(LAN8_BCR_REG, &tmp) != SUCCESS) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
if (!(tmp & (LAN8_RESET | LAN8_POWER_DOWN))) {
|
||||
i = -1;
|
||||
}
|
||||
else {
|
||||
i--;
|
||||
}
|
||||
}
|
||||
/* Timeout? */
|
||||
if (i == 0) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* Setup link */
|
||||
lpc_mii_write(LAN8_BCR_REG, LAN8_AUTONEG);
|
||||
|
||||
/* The link is not set active at this point, but will be detected
|
||||
later */
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/* Phy status update state machine */
|
||||
uint32_t lpcPHYStsPoll(void)
|
||||
{
|
||||
static uint16_t sts;
|
||||
|
||||
switch (phyustate) {
|
||||
default:
|
||||
case 0:
|
||||
/* Read BMSR to clear faults */
|
||||
Chip_ENET_StartMIIRead(LPC_ETHERNET, LAN8_BSR_REG);
|
||||
physts &= ~PHY_LINK_CHANGED;
|
||||
physts = physts | PHY_LINK_BUSY;
|
||||
phyustate = 1;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
/* Wait for read status state */
|
||||
if (!Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
|
||||
/* Get PHY status with link state */
|
||||
sts = Chip_ENET_ReadMIIData(LPC_ETHERNET);
|
||||
Chip_ENET_StartMIIRead(LPC_ETHERNET, LAN8_PHYSPLCTL_REG);
|
||||
phyustate = 2;
|
||||
}
|
||||
break;
|
||||
|
||||
case 2:
|
||||
/* Wait for read status state */
|
||||
if (!Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
|
||||
/* Update PHY status */
|
||||
physts &= ~PHY_LINK_BUSY;
|
||||
smsc_update_phy_sts(sts, Chip_ENET_ReadMIIData(LPC_ETHERNET));
|
||||
phyustate = 0;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return physts;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -0,0 +1,115 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2017-2021 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Generic phDriver Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$
|
||||
* $Date$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef BOARD_FRDM_K82FPN5180_H_
|
||||
#define BOARD_FRDM_K82FPN5180_H_
|
||||
|
||||
#define GPIO_PORT_A 0 /* Same macro for GPIOA/PORTA */
|
||||
#define GPIO_PORT_B 1 /* Same macro for GPIOB/PORTB */
|
||||
#define GPIO_PORT_C 2 /* Same macro for GPIOC/PORTC */
|
||||
#define GPIO_PORT_D 3 /* Same macro for GPIOD/PORTD */
|
||||
#define GPIO_PORT_E 4 /* Same macro for GPIOE/PORTE */
|
||||
|
||||
/******************************************************************
|
||||
* Board Pin/Gpio configurations
|
||||
******************************************************************/
|
||||
/* Pin configuration format : Its a 32 bit format where every byte represents a field as shown below.
|
||||
* | Byte3 | Byte2 | Byte1 | Byte0 |
|
||||
* | -- | -- | GPIO/PORT | PIN |
|
||||
* */
|
||||
#define PHDRIVER_PIN_RESET ((GPIO_PORT_A << 8) | 13) /**< Reset pin, Pin13, GPIOA, PORTA */
|
||||
#define PHDRIVER_PIN_IRQ ((GPIO_PORT_C << 8) | 7) /**< IRQ pin, Pin7, GPIOC, PORTC */
|
||||
#define PHDRIVER_PIN_BUSY ((GPIO_PORT_A << 8) | 5) /**< Busy pin, Pin5, GPIOA, PORTA */
|
||||
#define PHDRIVER_PIN_DWL ((GPIO_PORT_A << 8) | 12) /**< Download pin, Pin12, GPIOA, PORTA */
|
||||
|
||||
/* These pins are used for EMVCo Interoperability test status indication,
|
||||
* not for the generic Reader Library implementation.
|
||||
*/
|
||||
#define PHDRIVER_PIN_GLED ((GPIO_PORT_C << 8) | 9) /**< GREEN LED, Port C, Pin9 */
|
||||
#define PHDRIVER_PIN_RLED ((GPIO_PORT_C << 8) | 8) /**< RED LED, Port C, Pin8 */
|
||||
#define PHDRIVER_PIN_SUCCESS ((GPIO_PORT_C << 8) | 1) /**< GPIO, Port C, Pin1 */
|
||||
#define PHDRIVER_PIN_FAIL ((GPIO_PORT_C << 8) | 2) /**< GPIO, Port C, Pin2 */
|
||||
|
||||
/* GPIO and LED for applications use */
|
||||
#define PHDRIVER_PIN_GPIO ((GPIO_PORT_A << 8) | 1) /**< Port A, Pin1 */
|
||||
#define PHDRIVER_PIN_LED PHDRIVER_PIN_RLED /**< RED LED */
|
||||
|
||||
/******************************************************************
|
||||
* PIN Pull-Up/Pull-Down configurations.
|
||||
******************************************************************/
|
||||
#define PHDRIVER_PIN_RESET_PULL_CFG PH_DRIVER_PULL_UP
|
||||
#define PHDRIVER_PIN_IRQ_PULL_CFG PH_DRIVER_PULL_UP
|
||||
#define PHDRIVER_PIN_BUSY_PULL_CFG PH_DRIVER_PULL_UP
|
||||
#define PHDRIVER_PIN_DWL_PULL_CFG PH_DRIVER_PULL_UP
|
||||
#define PHDRIVER_PIN_NSS_PULL_CFG PH_DRIVER_PULL_UP
|
||||
|
||||
/******************************************************************
|
||||
* IRQ PIN NVIC settings
|
||||
******************************************************************/
|
||||
#define EINT_IRQn PORTC_IRQn
|
||||
#define EINT_PRIORITY 8
|
||||
#define CLIF_IRQHandler PORTC_IRQHandler
|
||||
#define PIN_IRQ_TRIGGER_TYPE PH_DRIVER_INTERRUPT_RISINGEDGE
|
||||
|
||||
/*****************************************************************
|
||||
* Front End Reset logic level settings
|
||||
****************************************************************/
|
||||
#define PH_DRIVER_SET_HIGH 1 /**< Logic High. */
|
||||
#define PH_DRIVER_SET_LOW 0 /**< Logic Low. */
|
||||
#define RESET_POWERDOWN_LEVEL PH_DRIVER_SET_LOW
|
||||
#define RESET_POWERUP_LEVEL PH_DRIVER_SET_HIGH
|
||||
|
||||
/*****************************************************************
|
||||
* SPI Configuration
|
||||
****************************************************************/
|
||||
|
||||
#define PHDRIVER_KSDK_SPI_POLLING /* Enable to perform SPI transfer using polling method. */
|
||||
#define PHDRIVER_KSDK_SPI_MASTER DSPI0
|
||||
#define PHDRIVER_KSDK_SPI_DATA_RATE 5000000U
|
||||
#define PHDRIVER_KSDK_SPI_CLK_SRC DSPI0_CLK_SRC
|
||||
#define PHDRIVER_KSDK_SPI_IRQ SPI0_IRQn
|
||||
|
||||
#define DSPI_IRQ_PRIORITY 7
|
||||
|
||||
#define ENABLE_PORT_SSP_1 kCLOCK_PortA
|
||||
#define PORT_SSP_1 PORTA
|
||||
#define FIRST_PINNUM_SSP 15
|
||||
|
||||
#define ENABLE_PORT_SSP_2 kCLOCK_PortA
|
||||
#define PORT_SSP_2 PORTA
|
||||
#define SECOND_PINNUM_SSP 16
|
||||
|
||||
#define ENABLE_PORT_SSP_3 kCLOCK_PortA
|
||||
#define PORT_SSP_3 PORTA
|
||||
#define THIRD_PINNUM_SSP 17
|
||||
|
||||
#define PHDRIVER_PIN_SSEL ((GPIO_PORT_A << 8) | 14) /**< Reset pin, Pin14, GPIOA, PORTA */
|
||||
|
||||
/*****************************************************************
|
||||
* Timer Configuration
|
||||
****************************************************************/
|
||||
#define PH_DRIVER_KSDK_PIT_TIMER PIT
|
||||
#define PH_DRIVER_KSDK_PIT_CLK kCLOCK_BusClk
|
||||
#define PH_DRIVER_KSDK_TIMER_CHANNEL kPIT_Chnl_0 /**< PIT channel number 0 */
|
||||
#define PH_DRIVER_KSDK_TIMER_NVIC PIT0CH0_IRQn
|
||||
#define PH_DRIVER_KSDK_TIMER_PRIORITY 8
|
||||
|
||||
#endif /* BOARD_FRDM_K82FPN5180_H_ */
|
||||
@ -0,0 +1,121 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.5.0
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PROJDEFS_H
|
||||
#define PROJDEFS_H
|
||||
|
||||
/*
|
||||
* Defines the prototype to which task functions must conform. Defined in this
|
||||
* file to ensure the type is known before portable.h is included.
|
||||
*/
|
||||
typedef void (* TaskFunction_t)( void * );
|
||||
|
||||
/* Converts a time in milliseconds to a time in ticks. This macro can be
|
||||
* overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
|
||||
* definition here is not suitable for your application. */
|
||||
#ifndef pdMS_TO_TICKS
|
||||
#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )
|
||||
#endif
|
||||
|
||||
#define pdFALSE ( ( BaseType_t ) 0 )
|
||||
#define pdTRUE ( ( BaseType_t ) 1 )
|
||||
|
||||
#define pdPASS ( pdTRUE )
|
||||
#define pdFAIL ( pdFALSE )
|
||||
#define errQUEUE_EMPTY ( ( BaseType_t ) 0 )
|
||||
#define errQUEUE_FULL ( ( BaseType_t ) 0 )
|
||||
|
||||
/* FreeRTOS error definitions. */
|
||||
#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )
|
||||
#define errQUEUE_BLOCKED ( -4 )
|
||||
#define errQUEUE_YIELD ( -5 )
|
||||
|
||||
/* Macros used for basic data corruption checks. */
|
||||
#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
|
||||
#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
|
||||
#endif
|
||||
|
||||
#if ( configUSE_16_BIT_TICKS == 1 )
|
||||
#define pdINTEGRITY_CHECK_VALUE 0x5a5a
|
||||
#else
|
||||
#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
|
||||
#endif
|
||||
|
||||
/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
|
||||
* itself. */
|
||||
#define pdFREERTOS_ERRNO_NONE 0 /* No errors */
|
||||
#define pdFREERTOS_ERRNO_ENOENT 2 /* No such file or directory */
|
||||
#define pdFREERTOS_ERRNO_EINTR 4 /* Interrupted system call */
|
||||
#define pdFREERTOS_ERRNO_EIO 5 /* I/O error */
|
||||
#define pdFREERTOS_ERRNO_ENXIO 6 /* No such device or address */
|
||||
#define pdFREERTOS_ERRNO_EBADF 9 /* Bad file number */
|
||||
#define pdFREERTOS_ERRNO_EAGAIN 11 /* No more processes */
|
||||
#define pdFREERTOS_ERRNO_EWOULDBLOCK 11 /* Operation would block */
|
||||
#define pdFREERTOS_ERRNO_ENOMEM 12 /* Not enough memory */
|
||||
#define pdFREERTOS_ERRNO_EACCES 13 /* Permission denied */
|
||||
#define pdFREERTOS_ERRNO_EFAULT 14 /* Bad address */
|
||||
#define pdFREERTOS_ERRNO_EBUSY 16 /* Mount device busy */
|
||||
#define pdFREERTOS_ERRNO_EEXIST 17 /* File exists */
|
||||
#define pdFREERTOS_ERRNO_EXDEV 18 /* Cross-device link */
|
||||
#define pdFREERTOS_ERRNO_ENODEV 19 /* No such device */
|
||||
#define pdFREERTOS_ERRNO_ENOTDIR 20 /* Not a directory */
|
||||
#define pdFREERTOS_ERRNO_EISDIR 21 /* Is a directory */
|
||||
#define pdFREERTOS_ERRNO_EINVAL 22 /* Invalid argument */
|
||||
#define pdFREERTOS_ERRNO_ENOSPC 28 /* No space left on device */
|
||||
#define pdFREERTOS_ERRNO_ESPIPE 29 /* Illegal seek */
|
||||
#define pdFREERTOS_ERRNO_EROFS 30 /* Read only file system */
|
||||
#define pdFREERTOS_ERRNO_EUNATCH 42 /* Protocol driver not attached */
|
||||
#define pdFREERTOS_ERRNO_EBADE 50 /* Invalid exchange */
|
||||
#define pdFREERTOS_ERRNO_EFTYPE 79 /* Inappropriate file type or format */
|
||||
#define pdFREERTOS_ERRNO_ENMFILE 89 /* No more files */
|
||||
#define pdFREERTOS_ERRNO_ENOTEMPTY 90 /* Directory not empty */
|
||||
#define pdFREERTOS_ERRNO_ENAMETOOLONG 91 /* File or path name too long */
|
||||
#define pdFREERTOS_ERRNO_EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
|
||||
#define pdFREERTOS_ERRNO_ENOBUFS 105 /* No buffer space available */
|
||||
#define pdFREERTOS_ERRNO_ENOPROTOOPT 109 /* Protocol not available */
|
||||
#define pdFREERTOS_ERRNO_EADDRINUSE 112 /* Address already in use */
|
||||
#define pdFREERTOS_ERRNO_ETIMEDOUT 116 /* Connection timed out */
|
||||
#define pdFREERTOS_ERRNO_EINPROGRESS 119 /* Connection already in progress */
|
||||
#define pdFREERTOS_ERRNO_EALREADY 120 /* Socket already connected */
|
||||
#define pdFREERTOS_ERRNO_EADDRNOTAVAIL 125 /* Address not available */
|
||||
#define pdFREERTOS_ERRNO_EISCONN 127 /* Socket is already connected */
|
||||
#define pdFREERTOS_ERRNO_ENOTCONN 128 /* Socket is not connected */
|
||||
#define pdFREERTOS_ERRNO_ENOMEDIUM 135 /* No medium inserted */
|
||||
#define pdFREERTOS_ERRNO_EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */
|
||||
#define pdFREERTOS_ERRNO_ECANCELED 140 /* Operation canceled. */
|
||||
|
||||
/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
|
||||
* itself. */
|
||||
#define pdFREERTOS_LITTLE_ENDIAN 0
|
||||
#define pdFREERTOS_BIG_ENDIAN 1
|
||||
|
||||
/* Re-defining endian values for generic naming. */
|
||||
#define pdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIAN
|
||||
#define pdBIG_ENDIAN pdFREERTOS_BIG_ENDIAN
|
||||
|
||||
#endif /* PROJDEFS_H */
|
||||
@ -0,0 +1,252 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2016-2023 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Application specific selection of Reader Library Components
|
||||
*
|
||||
* $Author: NXP $
|
||||
* $Revision: $ (v07.10.00)
|
||||
* $Date: $
|
||||
*/
|
||||
|
||||
#ifndef PH_NXPBUILD_APP_H_INC
|
||||
#define PH_NXPBUILD_APP_H_INC
|
||||
|
||||
/** \defgroup ph_NxpBuild NXP Build
|
||||
* \brief Controls the Inclusion of required components, Inclusion SRC/DATA within components and the Build Dependencies between the components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NXPBUILD_DELETE: included code lines should be always removed from code */
|
||||
|
||||
/* NXP BUILD DEFINES */
|
||||
/* use #define to include components */
|
||||
/* comment out #define to exclude components */
|
||||
|
||||
/* DEBUG build mode */
|
||||
/*#define NXPBUILD__PH_DEBUG*/ /**< DEBUG build definition */
|
||||
|
||||
//#define NXPRDLIB_REM_GEN_INTFS
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
#if defined(__PN74XXXX__) || defined (__PN73XXXX__)
|
||||
#define NXPBUILD__PHHAL_HW_PN7462AU /**< NFC Controller PN7462AU HAL */
|
||||
#endif
|
||||
|
||||
#ifdef __PN76XX__
|
||||
#ifdef __PN7642__
|
||||
#define NXPBUILD__PHHAL_HW_PN7642 /**< NFC Controller PN7642 HAL */
|
||||
#elif __PN7640__
|
||||
#define NXPBUILD__PHHAL_HW_PN7640 /**< NFC Controller PN7640 HAL */
|
||||
#else
|
||||
#error " PN76 platform definition (__PN7642__ or __PN7640__) missing !!! "
|
||||
#endif
|
||||
|
||||
#if defined(__PN7642__) || defined(__PN7640__)
|
||||
#define NXPBUILD__PHHAL_HW_PN76XX /**< NFC Controller PN76XX HAL */
|
||||
#endif
|
||||
#endif /* __PN76XX__ */
|
||||
|
||||
#if defined(PHDRIVER_LPC1769PN5180_BOARD) \
|
||||
|| defined(PHDRIVER_FRDM_K82FPN5180_BOARD)
|
||||
# define NXPBUILD__PHHAL_HW_PN5180
|
||||
#endif
|
||||
|
||||
#if defined(PHDRIVER_LPC1769PN5190_BOARD) \
|
||||
|| defined(PHDRIVER_K82F_PNEV5190B_BOARD)
|
||||
# define NXPBUILD__PHHAL_HW_PN5190
|
||||
#endif
|
||||
|
||||
#if defined(PHDRIVER_LPC1769RC663_BOARD) \
|
||||
|| defined(PHDRIVER_FRDM_K82FRC663_BOARD)
|
||||
/* WARNING: This example is not supported for RC663 */
|
||||
# define NXPBUILD__PHHAL_HW_RC663
|
||||
#endif
|
||||
|
||||
#if defined(NXPBUILD__PHHAL_HW_PN5180) || \
|
||||
defined(NXPBUILD__PHHAL_HW_PN7462AU) || \
|
||||
defined(NXPBUILD__PHHAL_HW_PN76XX) || \
|
||||
defined(NXPBUILD__PHHAL_HW_PN5190)
|
||||
#define NXPBUILD__PHHAL_HW_TARGET /**< Dependency checking if target mode macros should be enabled */
|
||||
#endif
|
||||
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
//#define NXPBUILD__PHPAL_I14443P3A_SW /**< PAL ISO 14443-3A SW Component is included. */
|
||||
|
||||
//#define NXPBUILD__PHPAL_I14443P3B_SW /**< PAL ISO 14443-3B SW Component is included. */
|
||||
|
||||
//#define NXPBUILD__PHPAL_I14443P4A_SW /**< PAL ISO 14443-4A SW Component is included. */
|
||||
|
||||
//#define NXPBUILD__PHPAL_I14443P4_SW /**< PAL ISO 14443-4 SW Component is included. */
|
||||
|
||||
//#define NXPBUILD__PHPAL_MIFARE_SW /**< PAL MIFARE SW Component is included */
|
||||
//#define NXPBUILD__PHPAL_MIFARE_STUB /**< PAL MIFARE STUB Component is included */
|
||||
|
||||
//#define NXPBUILD__PHPAL_FELICA_SW /**< PAL Felica SW Component is included. */
|
||||
|
||||
//#define NXPBUILD__PHPAL_SLI15693_SW /**< PAL SLI 15693 Component is included. */
|
||||
//#define NXPBUILD__PHPAL_I18000P3M3_SW /**< PAL ISO 18000p3m3 Component is included. */
|
||||
|
||||
#ifdef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then include EPC UID PAL as required, otherwise exclude. */
|
||||
// #define NXPBUILD__PHPAL_EPCUID_SW /**< PAL EPC UID SW Component is included. */
|
||||
#endif
|
||||
|
||||
//#define NXPBUILD__PHPAL_I18092MPI_SW /**< PAL ISO18092 (P2P) SW Component is included. */
|
||||
|
||||
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then exclude ISO14443 Card Mode PAL & ISO18092 Target Mode PAL, otherwise include as required. */
|
||||
#define NXPBUILD__PHPAL_I14443P4MC_SW /**< PAL ISO 14443-4 Card Mode SW Component is included. */
|
||||
// #define NXPBUILD__PHPAL_I18092MT_SW /**< PAL ISO 18092 Target Mode SW Component is included. */
|
||||
#endif /* NXPBUILD__PHHAL_HW_RC663 */
|
||||
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
#define NXPBUILD__PHAC_DISCLOOP_SW /**< Discovery Loop Activity SW Component is included. */
|
||||
|
||||
#ifdef NXPBUILD__PHAC_DISCLOOP_SW /**< If DiscLoop SW Component is included, macros( & it's dependencies) to include/exclude SRC/DATA within Discloop is defined. */
|
||||
|
||||
#if defined (NXPBUILD__PHHAL_HW_PN5180) || \
|
||||
defined (NXPBUILD__PHHAL_HW_PN5190) || \
|
||||
defined (NXPBUILD__PHHAL_HW_RC663) || \
|
||||
defined (NXPBUILD__PHHAL_HW_PN7462AU) || \
|
||||
defined (NXPBUILD__PHHAL_HW_PN7642)
|
||||
// #define NXPBUILD__PHAC_DISCLOOP_LPCD /**< SRC to enable LPCD is included. */
|
||||
#endif
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P3_TAGS /**< SRC/DATA to Detect/CollRes/Activate cards such as MFC, MFUL, MFP SL1 etc is included. */
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_JEWEL_TAGS /**< SRC/DATA to Detect cards such as NFC Forum T1T, Topaz/Jewel is included. */
|
||||
|
||||
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) && defined(NXPBUILD__PHPAL_I14443P4_SW)
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS /**< SRC/DATA to Detect cards such as MFDF, MFP, T4AT NFC Forum Tag or Type A EMVCo is included. */
|
||||
#endif
|
||||
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
|
||||
|
||||
#if defined(NXPBUILD__PHPAL_I14443P3A_SW) && defined(NXPBUILD__PHPAL_I18092MPI_SW)
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type A P2P Target mode devices is included. */
|
||||
#endif
|
||||
|
||||
#ifndef NXPBUILD__PHHAL_HW_RC663
|
||||
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE /**< SRC/DATA to Detect Peer Active Type A P2P Target mode devices is included. */
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F212 P2P Target mode devices is included. */
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F424 P2P Target mode devices is included. */
|
||||
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
|
||||
#endif /* NXPBUILD__PHHAL_HW_RC663 */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_FELICA_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_FELICA_TAGS /**< SRC/DATA to Detect FeliCa Cards is included. */
|
||||
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type F P2P Target mode devices is included. */
|
||||
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
|
||||
#endif /* NXPBUILD__PHPAL_FELICA_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P3B_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P3B_TAGS /**< SRC/DATA to Detect Type B Cards that operate at Layer3 level is included */
|
||||
#ifdef NXPBUILD__PHPAL_I14443P4_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P4B_TAGS /**< SRC/DATA to Detect Type B Cards such as NFC Forum Type 4 Tags, EMVCo Type B Cards etc is included */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P4_SW */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P3B_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_SLI15693_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS /**< SRC/DATA to Detect Type V Cards such as ICODE SLI/SLIX/SLI2/Tesa Cards is included*/
|
||||
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
|
||||
#define NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS /**< SRC/DATA to Detect ICODE ILT Cards such as SMARTRAC StackIt Cards is included*/
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
|
||||
|
||||
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, target mode is not supported at all, hence exclude those SRC, otherwise include as required */
|
||||
#ifdef NXPBUILD__PHHAL_HW_TARGET
|
||||
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_PASSIVE /**< SRC to Initialize Type A passive listen config and subsequently call HAL AutoColl is included. */
|
||||
// #define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_ACTIVE /**< SRC to Initialize Type A active listen config and subsequently call HAL AutoColl is included. */
|
||||
// #define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_PASSIVE/**< SRC to Initialize Type F212 passive listen config and subsequently call HAL AutoColl is included. */
|
||||
// #define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_ACTIVE /**< SRC to Initialize Type F212 active listen config and subsequently call HAL AutoColl is included. */
|
||||
// #define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_PASSIVE/**< SRC to Initialize Type F424 passive listen config and subsequently call HAL AutoColl is included. */
|
||||
// #define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_ACTIVE /**< SRC to Initialize Type F424 active listen config and subsequently call HAL AutoColl is included. */
|
||||
#endif /* NXPBUILD__PHHAL_HW_TARGET */
|
||||
#endif
|
||||
|
||||
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
|
||||
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
#define NXPBUILD__PHNFCLIB /**< Simplified API Interface, If enabling this the entry point should be this component in the application */
|
||||
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
//#define NXPBUILD__PH_CIDMANAGER_SW /**< CID Manager SW Component is included. */
|
||||
|
||||
//#define NXPBUILD__PH_KEYSTORE_SW /**< SW KeyStore Component is included. */
|
||||
|
||||
#if defined(NXPBUILD__PHHAL_HW_RC663) && !defined(NXPBUILD__PH_KEYSTORE_SW)
|
||||
#define NXPBUILD__PH_KEYSTORE_RC663 /**< RC663 KeyStore Component is included. */
|
||||
#endif
|
||||
//#define NXPBUILD__PH_NDA_MFDF /**< MIFARE DESFire contactless IC */
|
||||
//#define NXPBUILD__PH_CRYPTOSYM_SW /**< Crypto Symbols SW Component is included. */
|
||||
//#define NXPBUILD__PH_CRYPTORNG_SW /**< Crypto RNG SW Component is included. */
|
||||
|
||||
/*********************************************************************************************************************************************************************************/
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_FELICA_SW
|
||||
#define NXPBUILD__PHAL_FELICA_SW /**< AL FeliCa SW Component is included */
|
||||
#endif /* NXPBUILD__PHPAL_FELICA_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_MIFARE_SW
|
||||
#if defined(NXPBUILD__PH_KEYSTORE_SW) || defined(NXPBUILD__PH_KEYSTORE_RC663)
|
||||
#define NXPBUILD__PHAL_MFC_SW /**< AL MIFARE Classic contactless IC SW Component is included */
|
||||
#endif
|
||||
#define NXPBUILD__PHAL_MFUL_SW /**< AL Mifare Ultrlight SW Component is included */
|
||||
#define NXPBUILD__PHAL_MFDF_SW /**< AL Mifare DesFire SW Component is included */
|
||||
// #define NXPBUILD__PHAL_MFNTAG42XDNA_SW /**< AL MIFARE Prime Ntag42XDna contactless IC SW Component is included */
|
||||
#endif /* NXPBUILD__PHPAL_MIFARE_SW */
|
||||
|
||||
//#define NXPBUILD__PHAL_T1T_SW /**< AL Type T1 Tag SW Component is included */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_SLI15693_SW
|
||||
#define NXPBUILD__PHAL_ICODE_SW /**< AL ICODE SW COMPONENT is included */
|
||||
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
|
||||
|
||||
//#define NXPBUILD__PHAL_TOP_SW /**< AL for TagOps Mapping SW Component is included.Required for NDEF operations */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
|
||||
#define NXPBUILD__PHAL_I18000P3M3_SW /**< AL ISO18000p3m3 SW Component is included */
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
|
||||
#if !defined(PH_OSAL_NULLOS)
|
||||
#define NXPBUILD__PHCE_T4T_SW /**< AL HCE T2AT SW Component is included */
|
||||
//#define NXPBUILD__PHCE_T4T_PROPRIETARY /**< SRC to handle HCE T4AT Proprietary Commands is included */
|
||||
#endif
|
||||
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
|
||||
|
||||
/* LLCP Components */
|
||||
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
|
||||
#if !defined(PH_OSAL_NULLOS)
|
||||
#define NXPBUILD__PHLN_LLCP_SW /**< Link LLCP SW Component is included */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* SNEP components */
|
||||
#ifdef NXPBUILD__PHLN_LLCP_SW
|
||||
#define NXPBUILD__PHNP_SNEP_SW /**< Protocol SNEP SW Component is included */
|
||||
#endif /* NXPBUILD__PHLN_LLCP_SW */
|
||||
|
||||
/* Enable/disable Debugging */
|
||||
/*#define NXPBUILD__PH_DEBUG*/ /**< TODO: To be checked if required */
|
||||
|
||||
/** @}
|
||||
* end of ph_NxpBuild
|
||||
*/
|
||||
|
||||
#endif /* PH_NXPBUILD_APP_H_INC */
|
||||
@ -0,0 +1,431 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3 LTS Patch 2
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Implementation of functions defined in portable.h for the ARM CM0 port.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
/* IAR includes. */
|
||||
#include "intrinsics.h"
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Constants required to manipulate the NVIC. */
|
||||
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
|
||||
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
|
||||
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
|
||||
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
|
||||
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
|
||||
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
|
||||
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
|
||||
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
|
||||
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
|
||||
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
|
||||
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
|
||||
|
||||
/* Constants required to set up the initial stack. */
|
||||
#define portINITIAL_XPSR ( 0x01000000 )
|
||||
|
||||
/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
|
||||
* defined. The value 255 should also ensure backward compatibility.
|
||||
* FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
|
||||
#ifndef configKERNEL_INTERRUPT_PRIORITY
|
||||
#define configKERNEL_INTERRUPT_PRIORITY 0
|
||||
#endif
|
||||
|
||||
/* Each task maintains its own interrupt status in the critical nesting
|
||||
* variable. */
|
||||
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
|
||||
|
||||
/* The systick is a 24-bit counter. */
|
||||
#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
|
||||
|
||||
/* A fiddle factor to estimate the number of SysTick counts that would have
|
||||
* occurred while the SysTick counter is stopped during tickless idle
|
||||
* calculations. */
|
||||
#ifndef portMISSED_COUNTS_FACTOR
|
||||
#define portMISSED_COUNTS_FACTOR ( 45UL )
|
||||
#endif
|
||||
|
||||
/* The number of SysTick increments that make up one tick period. */
|
||||
#if ( configUSE_TICKLESS_IDLE == 1 )
|
||||
static uint32_t ulTimerCountsForOneTick = 0;
|
||||
#endif /* configUSE_TICKLESS_IDLE */
|
||||
|
||||
/* The maximum number of tick periods that can be suppressed is limited by the
|
||||
* 24 bit resolution of the SysTick timer. */
|
||||
#if ( configUSE_TICKLESS_IDLE == 1 )
|
||||
static uint32_t xMaximumPossibleSuppressedTicks = 0;
|
||||
#endif /* configUSE_TICKLESS_IDLE */
|
||||
|
||||
/* Compensate for the CPU cycles that pass while the SysTick is stopped (low
|
||||
* power functionality only. */
|
||||
#if ( configUSE_TICKLESS_IDLE == 1 )
|
||||
static uint32_t ulStoppedTimerCompensation = 0;
|
||||
#endif /* configUSE_TICKLESS_IDLE */
|
||||
|
||||
/*
|
||||
* Setup the timer to generate the tick interrupts. The implementation in this
|
||||
* file is weak to allow application writers to change the timer used to
|
||||
* generate the tick interrupt.
|
||||
*/
|
||||
void vPortSetupTimerInterrupt( void );
|
||||
|
||||
/*
|
||||
* Exception handlers.
|
||||
*/
|
||||
void xPortSysTickHandler( void );
|
||||
|
||||
/*
|
||||
* Start first task is a separate function so it can be tested in isolation.
|
||||
*/
|
||||
extern void vPortStartFirstTask( void );
|
||||
|
||||
/*
|
||||
* Used to catch tasks that attempt to return from their implementing function.
|
||||
*/
|
||||
static void prvTaskExitError( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters )
|
||||
{
|
||||
/* Simulate the stack frame as it would be created by a context switch
|
||||
* interrupt. */
|
||||
pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
|
||||
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) pxCode; /* PC */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
|
||||
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
|
||||
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
|
||||
pxTopOfStack -= 8; /* R11..R4. */
|
||||
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
* its caller as there is nothing to return to. If a task wants to exit it
|
||||
* should instead call vTaskDelete( NULL ).
|
||||
*
|
||||
* Artificially force an assert() to be triggered if configASSERT() is
|
||||
* defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxCriticalNesting == ~0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
for( ; ; )
|
||||
{
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
/* Make PendSV and SysTick the lowest priority interrupts. */
|
||||
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
|
||||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
|
||||
/* Start the timer that generates the tick ISR. Interrupts are disabled
|
||||
* here already. */
|
||||
vPortSetupTimerInterrupt();
|
||||
|
||||
/* Initialise the critical nesting count ready for the first task. */
|
||||
uxCriticalNesting = 0;
|
||||
|
||||
/* Start the first task. */
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should not get here! */
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
* Artificially force an assert. */
|
||||
configASSERT( uxCriticalNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortYield( void )
|
||||
{
|
||||
/* Set a PendSV to request a context switch. */
|
||||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET;
|
||||
|
||||
/* Barriers are normally not required but do ensure the code is completely
|
||||
* within the specified behaviour for the architecture. */
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEnterCritical( void )
|
||||
{
|
||||
portDISABLE_INTERRUPTS();
|
||||
uxCriticalNesting++;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortExitCritical( void )
|
||||
{
|
||||
configASSERT( uxCriticalNesting );
|
||||
uxCriticalNesting--;
|
||||
|
||||
if( uxCriticalNesting == 0 )
|
||||
{
|
||||
portENABLE_INTERRUPTS();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void xPortSysTickHandler( void )
|
||||
{
|
||||
uint32_t ulPreviousMask;
|
||||
|
||||
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
|
||||
{
|
||||
/* Increment the RTOS tick. */
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Pend a context switch. */
|
||||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET;
|
||||
}
|
||||
}
|
||||
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Setup the systick timer to generate the tick interrupts at the required
|
||||
* frequency.
|
||||
*/
|
||||
__weak void vPortSetupTimerInterrupt( void )
|
||||
{
|
||||
/* Calculate the constants required to configure the tick interrupt. */
|
||||
#if ( configUSE_TICKLESS_IDLE == 1 )
|
||||
{
|
||||
ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
|
||||
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
|
||||
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
|
||||
}
|
||||
#endif /* configUSE_TICKLESS_IDLE */
|
||||
|
||||
/* Stop and reset the SysTick. */
|
||||
portNVIC_SYSTICK_CTRL_REG = 0UL;
|
||||
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
||||
|
||||
/* Configure SysTick to interrupt at the requested rate. */
|
||||
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
|
||||
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( configUSE_TICKLESS_IDLE == 1 )
|
||||
|
||||
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
|
||||
{
|
||||
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
|
||||
TickType_t xModifiableIdleTime;
|
||||
|
||||
/* Make sure the SysTick reload value does not overflow the counter. */
|
||||
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
|
||||
{
|
||||
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
|
||||
}
|
||||
|
||||
/* Stop the SysTick momentarily. The time the SysTick is stopped for
|
||||
* is accounted for as best it can be, but using the tickless mode will
|
||||
* inevitably result in some tiny drift of the time maintained by the
|
||||
* kernel with respect to calendar time. */
|
||||
portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
|
||||
|
||||
/* Calculate the reload value required to wait xExpectedIdleTime
|
||||
* tick periods. -1 is used because this code will execute part way
|
||||
* through one of the tick periods. */
|
||||
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
|
||||
|
||||
if( ulReloadValue > ulStoppedTimerCompensation )
|
||||
{
|
||||
ulReloadValue -= ulStoppedTimerCompensation;
|
||||
}
|
||||
|
||||
/* Enter a critical section but don't use the taskENTER_CRITICAL()
|
||||
* method as that will mask interrupts that should exit sleep mode. */
|
||||
__disable_interrupt();
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
/* If a context switch is pending or a task is waiting for the scheduler
|
||||
* to be unsuspended then abandon the low power entry. */
|
||||
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
|
||||
{
|
||||
/* Restart from whatever is left in the count register to complete
|
||||
* this tick period. */
|
||||
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
|
||||
|
||||
/* Restart SysTick. */
|
||||
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
|
||||
|
||||
/* Reset the reload register to the value required for normal tick
|
||||
* periods. */
|
||||
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
|
||||
|
||||
/* Re-enable interrupts - see comments above __disable_interrupt()
|
||||
* call above. */
|
||||
__enable_interrupt();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the new reload value. */
|
||||
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
|
||||
|
||||
/* Clear the SysTick count flag and set the count value back to
|
||||
* zero. */
|
||||
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
||||
|
||||
/* Restart SysTick. */
|
||||
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
|
||||
|
||||
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
|
||||
* set its parameter to 0 to indicate that its implementation contains
|
||||
* its own wait for interrupt or wait for event instruction, and so wfi
|
||||
* should not be executed again. However, the original expected idle
|
||||
* time variable must remain unmodified, so a copy is taken. */
|
||||
xModifiableIdleTime = xExpectedIdleTime;
|
||||
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
|
||||
|
||||
if( xModifiableIdleTime > 0 )
|
||||
{
|
||||
__DSB();
|
||||
__WFI();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
|
||||
|
||||
/* Re-enable interrupts to allow the interrupt that brought the MCU
|
||||
* out of sleep mode to execute immediately. see comments above
|
||||
* __disable_interrupt() call above. */
|
||||
__enable_interrupt();
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
/* Disable interrupts again because the clock is about to be stopped
|
||||
* and interrupts that execute while the clock is stopped will increase
|
||||
* any slippage between the time maintained by the RTOS and calendar
|
||||
* time. */
|
||||
__disable_interrupt();
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
/* Disable the SysTick clock without reading the
|
||||
* portNVIC_SYSTICK_CTRL_REG register to ensure the
|
||||
* portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
|
||||
* the time the SysTick is stopped for is accounted for as best it can
|
||||
* be, but using the tickless mode will inevitably result in some tiny
|
||||
* drift of the time maintained by the kernel with respect to calendar
|
||||
* time*/
|
||||
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
|
||||
|
||||
/* Determine if the SysTick clock has already counted to zero and
|
||||
* been set back to the current reload value (the reload back being
|
||||
* correct for the entire expected idle time) or if the SysTick is yet
|
||||
* to count to zero (in which case an interrupt other than the SysTick
|
||||
* must have brought the system out of sleep mode). */
|
||||
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
|
||||
{
|
||||
uint32_t ulCalculatedLoadValue;
|
||||
|
||||
/* The tick interrupt is already pending, and the SysTick count
|
||||
* reloaded with ulReloadValue. Reset the
|
||||
* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
|
||||
* period. */
|
||||
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
|
||||
|
||||
/* Don't allow a tiny value, or values that have somehow
|
||||
* underflowed because the post sleep hook did something
|
||||
* that took too long. */
|
||||
if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
|
||||
{
|
||||
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
|
||||
}
|
||||
|
||||
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
|
||||
|
||||
/* As the pending tick will be processed as soon as this
|
||||
* function exits, the tick value maintained by the tick is stepped
|
||||
* forward by one less than the time spent waiting. */
|
||||
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Something other than the tick interrupt ended the sleep.
|
||||
* Work out how long the sleep lasted rounded to complete tick
|
||||
* periods (not the ulReload value which accounted for part
|
||||
* ticks). */
|
||||
ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
|
||||
|
||||
/* How many complete tick periods passed while the processor
|
||||
* was waiting? */
|
||||
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
|
||||
|
||||
/* The reload value is set to whatever fraction of a single tick
|
||||
* period remains. */
|
||||
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
|
||||
}
|
||||
|
||||
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
|
||||
* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
|
||||
* value. */
|
||||
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
||||
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
|
||||
vTaskStepTick( ulCompleteTickPeriods );
|
||||
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
|
||||
|
||||
/* Exit with interrpts enabled. */
|
||||
__enable_interrupt();
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* configUSE_TICKLESS_IDLE */
|
||||
@ -0,0 +1,557 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors Gratkorn / Austria
|
||||
*
|
||||
* (C)NXP Semiconductors
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
*particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Generic MIFARE Plus contactless IC Application Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* CHu: Generated 31. July 2009
|
||||
*
|
||||
*/
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <phpalMifare.h>
|
||||
#include <phalMfp.h>
|
||||
#include "phalMfp_Int.h"
|
||||
#include <ph_RefDefs.h>
|
||||
|
||||
#ifdef NXPBUILD__PHAL_MFP
|
||||
|
||||
phStatus_t phalMfp_Int_ComputeErrorResponse(
|
||||
uint16_t wNumBytesReceived,
|
||||
uint8_t bStatus,
|
||||
uint8_t bLayer4Comm
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
/* Invalid error response */
|
||||
if (wNumBytesReceived == 0U)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_AL_MFP);
|
||||
}
|
||||
|
||||
/* validate received response */
|
||||
if (wNumBytesReceived == 1U)
|
||||
{
|
||||
if (0U != (bLayer4Comm))
|
||||
{
|
||||
switch (bStatus)
|
||||
{
|
||||
case PHAL_MFP_RESP_ACK_ISO4:
|
||||
status = PH_ERR_SUCCESS;
|
||||
break;
|
||||
|
||||
case PHAL_MFP_RESP_ERR_AUTH:
|
||||
|
||||
status = PHAL_MFP_ERR_AUTH;
|
||||
break;
|
||||
|
||||
case PHAL_MFP_RESP_ERR_CMD_OVERFLOW:
|
||||
|
||||
status = PHAL_MFP_ERR_CMD_OVERFLOW;
|
||||
break;
|
||||
|
||||
case PHAL_MFP_RESP_ERR_MAC_PCD:
|
||||
|
||||
status = PHAL_MFP_ERR_MAC_PCD;
|
||||
break;
|
||||
|
||||
case PHAL_MFP_RESP_ERR_BNR:
|
||||
|
||||
status = PHAL_MFP_ERR_BNR;
|
||||
break;
|
||||
|
||||
case PHAL_MFP_RESP_ERR_CMD_INVALID:
|
||||
|
||||
status = PHAL_MFP_ERR_CMD_INVALID;
|
||||
break;
|
||||
|
||||
case PHAL_MFP_RESP_ERR_FORMAT:
|
||||
|
||||
status = PHAL_MFP_ERR_FORMAT;
|
||||
break;
|
||||
|
||||
case PHAL_MFP_RESP_ERR_GEN_FAILURE:
|
||||
|
||||
status = PHAL_MFP_ERR_GEN_FAILURE;
|
||||
break;
|
||||
case PHAL_MFP_RESP_ERR_EXT:
|
||||
status = PHAL_MFP_ERR_EXT;
|
||||
break;
|
||||
default:
|
||||
|
||||
status = PH_ERR_PROTOCOL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return PH_ADD_COMPCODE(status, PH_COMP_AL_MFP);
|
||||
}else
|
||||
{
|
||||
switch(bStatus)
|
||||
{
|
||||
case PHAL_MFP_RESP_ACK_ISO3:
|
||||
case PHAL_MFP_RESP_ACK_ISO4:
|
||||
status = PH_ERR_SUCCESS;
|
||||
break;
|
||||
/* Mapping of NAK codes: */
|
||||
case PHAL_MFP_RESP_NACK0:
|
||||
status = PHPAL_MIFARE_ERR_NAK0;
|
||||
break;
|
||||
case PHAL_MFP_RESP_NACK1:
|
||||
status = PHPAL_MIFARE_ERR_NAK1;
|
||||
break;
|
||||
case PHAL_MFP_RESP_NACK4:
|
||||
status = PHPAL_MIFARE_ERR_NAK4;
|
||||
break;
|
||||
case PHAL_MFP_RESP_NACK5:
|
||||
status = PHPAL_MIFARE_ERR_NAK5;
|
||||
break;
|
||||
default:
|
||||
status = PH_ERR_PROTOCOL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return PH_ADD_COMPCODE(status, PH_COMP_PAL_MIFARE); /* For compatibility reasons with SW stack we use here PAL MIFARE product */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* validate received response with wNumBytesReceived > 1 */
|
||||
if (bStatus != PHAL_MFP_RESP_ACK_ISO4)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_AL_MFP);
|
||||
}
|
||||
|
||||
/* proper error response */
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phalMfp_Int_WritePerso(
|
||||
void * pPalMifareDataParams,
|
||||
uint8_t bLayer4Comm,
|
||||
uint16_t wBlockNr,
|
||||
uint8_t * pValue
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM aCmd[3];
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wRxLength = 0;
|
||||
|
||||
/* parameter checking */
|
||||
if (pValue == NULL)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_AL_MFP);
|
||||
}
|
||||
|
||||
/* command frame */
|
||||
aCmd[0] = PHAL_MFP_CMD_WRITEPERSO;
|
||||
aCmd[1] = (uint8_t)(wBlockNr & 0xFFU); /* LSB */
|
||||
aCmd[2] = (uint8_t)(wBlockNr >> 8U); /* MSB */
|
||||
|
||||
/* exchange command/response */
|
||||
if (0U != (bLayer4Comm))
|
||||
{
|
||||
/* command header */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_FIRST,
|
||||
aCmd,
|
||||
3,
|
||||
&pResponse,
|
||||
&wRxLength));
|
||||
|
||||
/* command exchange */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_LAST,
|
||||
pValue,
|
||||
PHAL_MFP_MIFARE_BLOCK_SIZE,
|
||||
&pResponse,
|
||||
&wRxLength));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* command header */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL3(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_FIRST,
|
||||
aCmd,
|
||||
3,
|
||||
&pResponse,
|
||||
&wRxLength));
|
||||
|
||||
/* command exchange */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL3(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_LAST,
|
||||
pValue,
|
||||
PHAL_MFP_MIFARE_BLOCK_SIZE,
|
||||
&pResponse,
|
||||
&wRxLength));
|
||||
}
|
||||
|
||||
/* check response */
|
||||
if (wRxLength == 1U)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phalMfp_Int_ComputeErrorResponse(wRxLength, pResponse[0], bLayer4Comm));
|
||||
}
|
||||
else
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_AL_MFP);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phalMfp_Int_CommitPerso(
|
||||
void * pPalMifareDataParams,
|
||||
uint8_t bLayer4Comm
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM aCmd[1];
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wRxLength = 0;
|
||||
|
||||
/* command code */
|
||||
aCmd[0] = PHAL_MFP_CMD_COMMITPERSO;
|
||||
|
||||
/* exchange command/response */
|
||||
if (0U != (bLayer4Comm))
|
||||
{
|
||||
/* command exchange */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCmd,
|
||||
1,
|
||||
&pResponse,
|
||||
&wRxLength));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* command exchange */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL3(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCmd,
|
||||
1,
|
||||
&pResponse,
|
||||
&wRxLength));
|
||||
}
|
||||
|
||||
/* check response */
|
||||
if (wRxLength == 1U)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phalMfp_Int_ComputeErrorResponse(wRxLength, pResponse[0], bLayer4Comm));
|
||||
}
|
||||
else
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_AL_MFP);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phalMfp_Int_ResetAuth(void * pPalMifareDataParams)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM aCmd[1 /* command code */];
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wRxLength = 0;
|
||||
|
||||
/* command code */
|
||||
aCmd[0] = PHAL_MFP_CMD_RAUTH;
|
||||
|
||||
/* command exchange */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCmd,
|
||||
1,
|
||||
&pResponse,
|
||||
&wRxLength));
|
||||
|
||||
/* check response */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phalMfp_Int_ComputeErrorResponse(wRxLength, pResponse[0], 1));
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phalMfp_Int_PrepareProximityCheck(
|
||||
void * pPalMifareDataParams
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM aCmd[1];
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wRxLength = 0;
|
||||
|
||||
/* command code */
|
||||
aCmd[0] = PHAL_MFP_CMD_PPC;
|
||||
|
||||
/* command exchange */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCmd,
|
||||
1,
|
||||
&pResponse,
|
||||
&wRxLength));
|
||||
|
||||
/* check response */
|
||||
if (wRxLength == 1U)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phalMfp_Int_ComputeErrorResponse(wRxLength, pResponse[0], 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_AL_MFP);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phalMfp_Int_ProximityCheck(
|
||||
void * pPalMifareDataParams,
|
||||
uint8_t bNumSteps,
|
||||
uint8_t * pRndC,
|
||||
uint8_t * pRndRC
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp = 0;
|
||||
uint8_t PH_MEMLOC_REM aCmd[1 /* command code */ + 1 /* length */ + 7 /* max RndC length */];
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wRxLength = 0;
|
||||
uint8_t PH_MEMLOC_REM bPayloadLen;
|
||||
uint8_t PH_MEMLOC_REM bRndCLen = 0;
|
||||
uint8_t PH_MEMLOC_REM bRndRCLen = 0;
|
||||
phStatus_t PH_MEMLOC_REM status = PH_ERR_SUCCESS;
|
||||
|
||||
/* parameter checking */
|
||||
if ((bNumSteps == 0U) || (bNumSteps > PHAL_MFP_PC_RND_LEN) || (pRndC == NULL) || (pRndRC == NULL))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_AL_MFP);
|
||||
}
|
||||
|
||||
/*Enabling Min FDT for PC*/
|
||||
PH_CHECK_SUCCESS_FCT(status, phpalMifare_SetMinFdtPc(pPalMifareDataParams, 1));
|
||||
/* command code */
|
||||
aCmd[0] = PHAL_MFP_CMD_PC;
|
||||
|
||||
/* Proximity Check loop */
|
||||
while (0U != (bNumSteps--))
|
||||
{
|
||||
/* RndC length */
|
||||
if (0U != (bNumSteps))
|
||||
{
|
||||
bPayloadLen = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
bPayloadLen = PHAL_MFP_PC_RND_LEN - bRndCLen;
|
||||
}
|
||||
|
||||
/* Length */
|
||||
aCmd[1] = bPayloadLen;
|
||||
|
||||
/* RndC */
|
||||
(void)memcpy(&aCmd[2], &pRndC[bRndCLen], bPayloadLen);
|
||||
|
||||
/* command exchange */
|
||||
statusTmp = phpalMifare_ExchangePc( pPalMifareDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCmd,
|
||||
2u + bPayloadLen,
|
||||
&pResponse,
|
||||
&wRxLength);
|
||||
|
||||
if (statusTmp == PH_ERR_SUCCESS)
|
||||
{
|
||||
/* check response */
|
||||
if (wRxLength == (uint16_t)bPayloadLen)
|
||||
{
|
||||
/* copy RndR */
|
||||
(void)memcpy(&pRndRC[bRndRCLen], pResponse, wRxLength);
|
||||
bRndRCLen = bRndRCLen + (uint8_t)wRxLength;
|
||||
|
||||
/* copy RndC */
|
||||
(void)memcpy(&pRndRC[bRndRCLen], &pRndC[bRndCLen], wRxLength);
|
||||
bRndRCLen = bRndRCLen + (uint8_t)wRxLength;
|
||||
bRndCLen = bRndCLen + (uint8_t)wRxLength;
|
||||
}
|
||||
else
|
||||
{
|
||||
statusTmp = phalMfp_Int_ComputeErrorResponse(wRxLength,
|
||||
pResponse[0], 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*Disabling Min FDT for PC*/
|
||||
PH_CHECK_SUCCESS_FCT(status, phpalMifare_SetMinFdtPc(pPalMifareDataParams, 0));
|
||||
PH_CHECK_SUCCESS(statusTmp);
|
||||
|
||||
/* We expect to have exactly 7 bytes RndR + 7 bytes RndC */
|
||||
if (bRndRCLen != (PHAL_MFP_PC_RND_LEN * 2U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_AL_MFP);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phalMfp_Int_MultiBlockRead(
|
||||
void * pPalMifareDataParams,
|
||||
uint8_t bBlockNr,
|
||||
uint8_t bNumBlocks,
|
||||
uint8_t * pBlocks
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM aCmd[1 /* command code */ + 1 /* wBlockNr */ + 1 /* bNumBlocks */];
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wRxLength = 0;
|
||||
|
||||
/* parameter checking */
|
||||
if (pBlocks == NULL)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_AL_MFP);
|
||||
}
|
||||
|
||||
/* command frame */
|
||||
aCmd[0] = PHAL_MFP_CMD_MBREAD;
|
||||
aCmd[1] = bBlockNr;
|
||||
aCmd[2] = bNumBlocks;
|
||||
|
||||
/* command exchange */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL3(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCmd,
|
||||
3,
|
||||
&pResponse,
|
||||
&wRxLength));
|
||||
|
||||
/* check response */
|
||||
if (((wRxLength % PHAL_MFP_MIFARE_BLOCK_SIZE) == 0U) && (wRxLength <= (uint16_t)(3u * PHAL_MFP_MIFARE_BLOCK_SIZE)))
|
||||
{
|
||||
/* pass back read bytes */
|
||||
(void)memcpy(pBlocks, pResponse, wRxLength);
|
||||
}
|
||||
else
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phalMfp_Int_ComputeErrorResponse(wRxLength, pResponse[0], 0));
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phalMfp_Int_MultiBlockWrite(
|
||||
void * pPalMifareDataParams,
|
||||
uint8_t bBlockNr,
|
||||
uint8_t bNumBlocks,
|
||||
uint8_t * pBlocks
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM aCmd[1 /* command code */ + 1 /* wBlockNr */ + 1 /* bNumBlocks */];
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wRxLength = 0;
|
||||
|
||||
/* parameter checking */
|
||||
if (pBlocks == NULL)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_AL_MFP);
|
||||
}
|
||||
|
||||
/* command frame */
|
||||
aCmd[0] = PHAL_MFP_CMD_MBWRITE;
|
||||
aCmd[1] = bBlockNr;
|
||||
aCmd[2] = bNumBlocks;
|
||||
|
||||
/* command exchange */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL3(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCmd,
|
||||
3,
|
||||
&pResponse,
|
||||
&wRxLength));
|
||||
|
||||
/* command exchange */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL3(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
pBlocks,
|
||||
(uint16_t)(bNumBlocks * PHAL_MFP_MIFARE_BLOCK_SIZE),
|
||||
&pResponse,
|
||||
&wRxLength));
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phalMfp_Int_CreateValueBlock(
|
||||
uint8_t * pValue,
|
||||
uint8_t bAddrData,
|
||||
uint8_t * pBlock
|
||||
)
|
||||
{
|
||||
pBlock[0] = (uint8_t)(pValue[0]);
|
||||
pBlock[1] = (uint8_t)(pValue[1]);
|
||||
pBlock[2] = (uint8_t)(pValue[2]);
|
||||
pBlock[3] = (uint8_t)(pValue[3]);
|
||||
pBlock[4] = (uint8_t)(~pBlock[0]);
|
||||
pBlock[5] = (uint8_t)(~pBlock[1]);
|
||||
pBlock[6] = (uint8_t)(~pBlock[2]);
|
||||
pBlock[7] = (uint8_t)(~pBlock[3]);
|
||||
pBlock[8] = (uint8_t)(pBlock[0]);
|
||||
pBlock[9] = (uint8_t)(pBlock[1]);
|
||||
pBlock[10] = (uint8_t)(pBlock[2]);
|
||||
pBlock[11] = (uint8_t)(pBlock[3]);
|
||||
pBlock[12] = (uint8_t)bAddrData;
|
||||
pBlock[13] = (uint8_t)~bAddrData;
|
||||
pBlock[14] = (uint8_t)bAddrData;
|
||||
pBlock[15] = (uint8_t)~bAddrData;
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phalMfp_Int_CheckValueBlockFormat(
|
||||
uint8_t * pBlock
|
||||
)
|
||||
{
|
||||
/* check format of value block */
|
||||
if ((pBlock[0] != pBlock[8]) ||
|
||||
(pBlock[1] != pBlock[9]) ||
|
||||
(pBlock[2] != pBlock[10]) ||
|
||||
(pBlock[3] != pBlock[11]) ||
|
||||
(pBlock[4] != (pBlock[0] ^ 0xFFU)) ||
|
||||
(pBlock[5] != (pBlock[1] ^ 0xFFU)) ||
|
||||
(pBlock[6] != (pBlock[2] ^ 0xFFU)) ||
|
||||
(pBlock[7] != (pBlock[3] ^ 0xFFU)) ||
|
||||
(pBlock[12] != pBlock[14]) ||
|
||||
(pBlock[13] != pBlock[15]) ||
|
||||
(pBlock[12] != (pBlock[13]^ 0xFFU)))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_AL_MFP);
|
||||
}
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
#endif /* NXPBUILD__PHAL_MFP */
|
||||
@ -0,0 +1,177 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _FSL_DMAMUX_H_
|
||||
#define _FSL_DMAMUX_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup dmamux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief DMAMUX driver version 2.0.3. */
|
||||
#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*!
|
||||
* @name DMAMUX Initialization and de-initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the DMAMUX peripheral.
|
||||
*
|
||||
* This function ungates the DMAMUX clock.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
*
|
||||
*/
|
||||
void DMAMUX_Init(DMAMUX_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the DMAMUX peripheral.
|
||||
*
|
||||
* This function gates the DMAMUX clock.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
*/
|
||||
void DMAMUX_Deinit(DMAMUX_Type *base);
|
||||
|
||||
/* @} */
|
||||
/*!
|
||||
* @name DMAMUX Channel Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the DMAMUX channel.
|
||||
*
|
||||
* This function enables the DMAMUX channel.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
*/
|
||||
static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the DMAMUX channel.
|
||||
*
|
||||
* This function disables the DMAMUX channel.
|
||||
*
|
||||
* @note The user must disable the DMAMUX channel before configuring it.
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
*/
|
||||
static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_ENBL_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Configures the DMAMUX channel source.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
* @param source Channel source, which is used to trigger the DMA transfer.
|
||||
*/
|
||||
static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source)
|
||||
{
|
||||
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
base->CHCFG[channel] = (uint8_t)((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
|
||||
/*!
|
||||
* @brief Enables the DMAMUX period trigger.
|
||||
*
|
||||
* This function enables the DMAMUX period trigger feature.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
*/
|
||||
static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the DMAMUX period trigger.
|
||||
*
|
||||
* This function disables the DMAMUX period trigger.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
*/
|
||||
static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_TRIG_MASK;
|
||||
}
|
||||
#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */
|
||||
|
||||
#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON)
|
||||
/*!
|
||||
* @brief Enables the DMA channel to be always ON.
|
||||
*
|
||||
* This function enables the DMAMUX channel always ON feature.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
* @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled.
|
||||
*/
|
||||
static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
if (enable)
|
||||
{
|
||||
base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK;
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* @} */
|
||||
|
||||
#endif /* _FSL_DMAMUX_H_ */
|
||||
2751
.svn/pristine/08/0890a9aef4ee68090e882a6f4b2ebdb2863cc71c.svn-base
Normal file
2751
.svn/pristine/08/0890a9aef4ee68090e882a6f4b2ebdb2863cc71c.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,261 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_SDRAMC_H_
|
||||
#define _FSL_SDRAMC_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup sdramc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief SDRAMC driver version 2.1.0. */
|
||||
#define FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief SDRAM controller auto-refresh timing. */
|
||||
typedef enum _sdramc_refresh_time
|
||||
{
|
||||
kSDRAMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
|
||||
kSDRAMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
|
||||
kSDRAMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
|
||||
} sdramc_refresh_time_t;
|
||||
|
||||
/*!
|
||||
* @brief Setting latency for SDRAM controller timing specifications.
|
||||
*
|
||||
* The latency setting affects the following SDRAM timing specifications:
|
||||
* - trcd: SRAS assertion to SCAS assertion \n
|
||||
* - tcasl: SCAS assertion to data out \n
|
||||
* - tras: ACTV command to Precharge command \n
|
||||
* - trp: Precharge command to ACTV command \n
|
||||
* - trwl, trdl: Last data input to Precharge command \n
|
||||
* - tep: Last data out to Precharge command \n
|
||||
* The details of the latency setting and timing specifications are shown in the following table list. \n
|
||||
* latency trcd: tcasl tras trp trwl,trdl tep \n
|
||||
* 0 1 bus clock 1 bus clock 2 bus clocks 1 bus clock 1 bus clock 1 bus clock \n
|
||||
* 1 2 bus clock 2 bus clock 4 bus clocks 2 bus clock 1 bus clock 1 bus clock \n
|
||||
* 2 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n
|
||||
* 3 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n
|
||||
*/
|
||||
typedef enum _sdramc_latency
|
||||
{
|
||||
kSDRAMC_LatencyZero = 0x0U, /*!< Latency 0. */
|
||||
kSDRAMC_LatencyOne, /*!< Latency 1. */
|
||||
kSDRAMC_LatencyTwo, /*!< Latency 2. */
|
||||
kSDRAMC_LatencyThree, /*!< Latency 3. */
|
||||
} sdramc_latency_t;
|
||||
|
||||
/*! @brief SDRAM controller command bit location. */
|
||||
typedef enum _sdramc_command_bit_location
|
||||
{
|
||||
kSDRAMC_Commandbit17 = 0x0U, /*!< Command bit location is bit 17. */
|
||||
kSDRAMC_Commandbit18, /*!< Command bit location is bit 18. */
|
||||
kSDRAMC_Commandbit19, /*!< Command bit location is bit 19. */
|
||||
kSDRAMC_Commandbit20, /*!< Command bit location is bit 20. */
|
||||
kSDRAMC_Commandbit21, /*!< Command bit location is bit 21. */
|
||||
kSDRAMC_Commandbit22, /*!< Command bit location is bit 22. */
|
||||
kSDRAMC_Commandbit23, /*!< Command bit location is bit 23. */
|
||||
kSDRAMC_Commandbit24 /*!< Command bit location is bit 24. */
|
||||
} sdramc_command_bit_location_t;
|
||||
|
||||
/*! @brief SDRAM controller command. */
|
||||
typedef enum _sdramc_command
|
||||
{
|
||||
kSDRAMC_ImrsCommand = 0x0U, /*!< Initiate MRS command. */
|
||||
kSDRAMC_PrechargeCommand, /*!< Initiate precharge command. */
|
||||
kSDRAMC_SelfrefreshEnterCommand, /*!< Enter self-refresh command. */
|
||||
kSDRAMC_SelfrefreshExitCommand, /*!< Exit self-refresh command. */
|
||||
kSDRAMC_AutoRefreshEnableCommand, /*!< Enable Auto refresh command. */
|
||||
kSDRAMC_AutoRefreshDisableCommand, /*!< Disable Auto refresh command. */
|
||||
} sdramc_command_t;
|
||||
|
||||
/*! @brief SDRAM port size. */
|
||||
typedef enum _sdramc_port_size
|
||||
{
|
||||
kSDRAMC_PortSize32Bit = 0x0U, /*!< 32-Bit port size. */
|
||||
kSDRAMC_PortSize8Bit, /*!< 8-Bit port size. */
|
||||
kSDRAMC_PortSize16Bit /*!< 16-Bit port size. */
|
||||
} sdramc_port_size_t;
|
||||
|
||||
/*! @brief SDRAM controller block selection. */
|
||||
typedef enum _sdramc_block_selection
|
||||
{
|
||||
kSDRAMC_Block0 = 0x0U, /*!< Select SDRAM block 0. */
|
||||
kSDRAMC_Block1, /*!< Select SDRAM block 1. */
|
||||
} sdramc_block_selection_t;
|
||||
|
||||
/*! @brief SDRAM controller block control configuration structure. */
|
||||
typedef struct _sdramc_blockctl_config
|
||||
{
|
||||
sdramc_block_selection_t block; /*!< The block number. */
|
||||
sdramc_port_size_t portSize; /*!< The port size of the associated SDRAM block. */
|
||||
sdramc_command_bit_location_t location; /*!< The command bit location. */
|
||||
sdramc_latency_t latency; /*!< The latency for some timing specifications. */
|
||||
uint32_t address; /*!< The base address of the SDRAM block. */
|
||||
uint32_t addressMask; /*!< The base address mask of the SDRAM block. */
|
||||
} sdramc_blockctl_config_t;
|
||||
|
||||
/*! @brief SDRAM controller refresh timing configuration structure. */
|
||||
typedef struct _sdramc_refresh_config
|
||||
{
|
||||
sdramc_refresh_time_t refreshTime; /*!< Trc:The number of bus clocks inserted
|
||||
between a REF and next ACTIVE command. */
|
||||
uint32_t sdramRefreshRow; /*!< The SDRAM refresh time each row: ns/row. */
|
||||
uint32_t busClock_Hz; /*!< The bus clock for SDRAMC. */
|
||||
} sdramc_refresh_config_t;
|
||||
|
||||
/*!
|
||||
* @brief SDRAM controller configuration structure.
|
||||
*
|
||||
* Defines a configure structure and uses the SDRAMC_Configure() function to make necessary
|
||||
* initializations.
|
||||
*/
|
||||
typedef struct _sdramc_config_t
|
||||
{
|
||||
sdramc_refresh_config_t *refreshConfig; /*!< Refresh timing configure structure pointer. */
|
||||
sdramc_blockctl_config_t *blockConfig; /*!< Block configure structure pointer. If both SDRAM
|
||||
blocks are used, use the two continuous blockConfig. */
|
||||
uint8_t numBlockConfig; /*!< SDRAM block numbers for configuration. */
|
||||
} sdramc_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name SDRAM Controller Initialization and De-initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the SDRAM controller.
|
||||
* This function ungates the SDRAM controller clock and initializes the SDRAM controller.
|
||||
* This function must be called before calling any other SDRAM controller driver functions.
|
||||
* Example
|
||||
@code
|
||||
sdramc_refresh_config_t refreshConfig;
|
||||
sdramc_blockctl_config_t blockConfig;
|
||||
sdramc_config_t config;
|
||||
|
||||
refreshConfig.refreshTime = kSDRAM_RefreshThreeClocks;
|
||||
refreshConfig.sdramRefreshRow = 15625;
|
||||
refreshConfig.busClock = 60000000;
|
||||
|
||||
blockConfig.block = kSDRAMC_Block0;
|
||||
blockConfig.portSize = kSDRAMC_PortSize16Bit;
|
||||
blockConfig.location = kSDRAMC_Commandbit19;
|
||||
blockConfig.latency = kSDRAMC_RefreshThreeClocks;
|
||||
blockConfig.address = SDRAM_START_ADDRESS;
|
||||
blockConfig.addressMask = 0x7c0000;
|
||||
|
||||
config.refreshConfig = &refreshConfig,
|
||||
config.blockConfig = &blockConfig,
|
||||
config.totalBlocks = 1;
|
||||
|
||||
SDRAMC_Init(SDRAM, &config);
|
||||
@endcode
|
||||
*
|
||||
* @param base SDRAM controller peripheral base address.
|
||||
* @param configure The SDRAM configuration structure pointer.
|
||||
*/
|
||||
void SDRAMC_Init(SDRAM_Type *base, sdramc_config_t *configure);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the SDRAM controller module and gates the clock.
|
||||
* This function gates the SDRAM controller clock. As a result, the SDRAM
|
||||
* controller module doesn't work after calling this function.
|
||||
*
|
||||
* @param base SDRAM controller peripheral base address.
|
||||
*/
|
||||
void SDRAMC_Deinit(SDRAM_Type *base);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name SDRAM Controller Basic Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Sends the SDRAM command.
|
||||
* This function sends commands to SDRAM. The commands are precharge command, initialization MRS command,
|
||||
* auto-refresh enable/disable command, and self-refresh enter/exit commands.
|
||||
* Note that the self-refresh enter/exit commands are all blocks setting and "block"
|
||||
* is ignored. Ensure to set the correct "block" when send other commands.
|
||||
*
|
||||
* @param base SDRAM controller peripheral base address.
|
||||
* @param block The block selection.
|
||||
* @param command The SDRAM command, see "sdramc_command_t".
|
||||
* kSDRAMC_ImrsCommand - Initialize MRS command \n
|
||||
* kSDRAMC_PrechargeCommand - Initialize precharge command \n
|
||||
* kSDRAMC_SelfrefreshEnterCommand - Enter self-refresh command \n
|
||||
* kSDRAMC_SelfrefreshExitCommand - Exit self-refresh command \n
|
||||
* kSDRAMC_AutoRefreshEnableCommand - Enable auto refresh command \n
|
||||
* kSDRAMC_AutoRefreshDisableCommand - Disable auto refresh command
|
||||
*/
|
||||
void SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command);
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables the write protection.
|
||||
*
|
||||
* @param base SDRAM peripheral base address.
|
||||
* @param block The block which is selected.
|
||||
* @param enable True enable write protection, false disable write protection.
|
||||
*/
|
||||
static inline void SDRAMC_EnableWriteProtect(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->BLOCK[block].CM |= SDRAM_CM_WP_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->BLOCK[block].CM &= ~SDRAM_CM_WP_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables the valid operation.
|
||||
*
|
||||
* @param base SDRAM peripheral base address.
|
||||
* @param block The block which is selected.
|
||||
* @param enable True enable the valid operation; false disable the valid operation.
|
||||
*/
|
||||
static inline void SDRAMC_EnableOperateValid(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->BLOCK[block].CM |= SDRAM_CM_V_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->BLOCK[block].CM &= ~SDRAM_CM_V_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_SDRAMC_H_*/
|
||||
@ -0,0 +1,300 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_dac.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.dac"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Get instance number for DAC module.
|
||||
*
|
||||
* @param base DAC peripheral base address
|
||||
*/
|
||||
static uint32_t DAC_GetInstance(DAC_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to DAC bases for each instance. */
|
||||
static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS;
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to DAC clocks for each instance. */
|
||||
static const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*******************************************************************************
|
||||
* Codes
|
||||
******************************************************************************/
|
||||
static uint32_t DAC_GetInstance(DAC_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++)
|
||||
{
|
||||
if (s_dacBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_dacBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Initializes the DAC module.
|
||||
*
|
||||
* This function initializes the DAC module including the following operations.
|
||||
* - Enabling the clock for DAC module.
|
||||
* - Configuring the DAC converter with a user configuration.
|
||||
* - Enabling the DAC module.
|
||||
*
|
||||
* param base DAC peripheral base address.
|
||||
* param config Pointer to the configuration structure. See "dac_config_t".
|
||||
*/
|
||||
void DAC_Init(DAC_Type *base, const dac_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
uint8_t tmp8;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable the clock. */
|
||||
CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Configure. */
|
||||
/* DACx_C0. */
|
||||
tmp8 = base->C0 & ~(DAC_C0_DACRFS_MASK | DAC_C0_LPEN_MASK);
|
||||
if (kDAC_ReferenceVoltageSourceVref2 == config->referenceVoltageSource)
|
||||
{
|
||||
tmp8 |= DAC_C0_DACRFS_MASK;
|
||||
}
|
||||
if (config->enableLowPowerMode)
|
||||
{
|
||||
tmp8 |= DAC_C0_LPEN_MASK;
|
||||
}
|
||||
base->C0 = tmp8;
|
||||
|
||||
/* DAC_Enable(base, true); */
|
||||
/* Tip: The DAC output can be enabled till then after user sets their own available data in application. */
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief De-initializes the DAC module.
|
||||
*
|
||||
* This function de-initializes the DAC module including the following operations.
|
||||
* - Disabling the DAC module.
|
||||
* - Disabling the clock for the DAC module.
|
||||
*
|
||||
* param base DAC peripheral base address.
|
||||
*/
|
||||
void DAC_Deinit(DAC_Type *base)
|
||||
{
|
||||
DAC_Enable(base, false);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable the clock. */
|
||||
CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Initializes the DAC user configuration structure.
|
||||
*
|
||||
* This function initializes the user configuration structure to a default value. The default values are as follows.
|
||||
* code
|
||||
* config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2;
|
||||
* config->enableLowPowerMode = false;
|
||||
* endcode
|
||||
* param config Pointer to the configuration structure. See "dac_config_t".
|
||||
*/
|
||||
void DAC_GetDefaultConfig(dac_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
/* Initializes the configure structure to zero. */
|
||||
memset(config, 0, sizeof(*config));
|
||||
|
||||
config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2;
|
||||
config->enableLowPowerMode = false;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Configures the CMP buffer.
|
||||
*
|
||||
* param base DAC peripheral base address.
|
||||
* param config Pointer to the configuration structure. See "dac_buffer_config_t".
|
||||
*/
|
||||
void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
uint8_t tmp8;
|
||||
|
||||
/* DACx_C0. */
|
||||
tmp8 = base->C0 & ~(DAC_C0_DACTRGSEL_MASK);
|
||||
if (kDAC_BufferTriggerBySoftwareMode == config->triggerMode)
|
||||
{
|
||||
tmp8 |= DAC_C0_DACTRGSEL_MASK;
|
||||
}
|
||||
base->C0 = tmp8;
|
||||
|
||||
/* DACx_C1. */
|
||||
tmp8 = base->C1 & ~(
|
||||
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
|
||||
DAC_C1_DACBFWM_MASK |
|
||||
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
|
||||
DAC_C1_DACBFMD_MASK);
|
||||
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
|
||||
tmp8 |= DAC_C1_DACBFWM(config->watermark);
|
||||
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
|
||||
tmp8 |= DAC_C1_DACBFMD(config->workMode);
|
||||
base->C1 = tmp8;
|
||||
|
||||
/* DACx_C2. */
|
||||
tmp8 = base->C2 & ~DAC_C2_DACBFUP_MASK;
|
||||
tmp8 |= DAC_C2_DACBFUP(config->upperLimit);
|
||||
base->C2 = tmp8;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Initializes the DAC buffer configuration structure.
|
||||
*
|
||||
* This function initializes the DAC buffer configuration structure to default values. The default values are as
|
||||
* follows.
|
||||
* code
|
||||
* config->triggerMode = kDAC_BufferTriggerBySoftwareMode;
|
||||
* config->watermark = kDAC_BufferWatermark1Word;
|
||||
* config->workMode = kDAC_BufferWorkAsNormalMode;
|
||||
* config->upperLimit = DAC_DATL_COUNT - 1U;
|
||||
* endcode
|
||||
* param config Pointer to the configuration structure. See "dac_buffer_config_t".
|
||||
*/
|
||||
void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
/* Initializes the configure structure to zero. */
|
||||
memset(config, 0, sizeof(*config));
|
||||
|
||||
config->triggerMode = kDAC_BufferTriggerBySoftwareMode;
|
||||
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
|
||||
config->watermark = kDAC_BufferWatermark1Word;
|
||||
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
|
||||
config->workMode = kDAC_BufferWorkAsNormalMode;
|
||||
config->upperLimit = DAC_DATL_COUNT - 1U;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Sets the value for items in the buffer.
|
||||
*
|
||||
* param base DAC peripheral base address.
|
||||
* param index Setting the index for items in the buffer. The available index should not exceed the size of the DAC
|
||||
* buffer.
|
||||
* param value Setting the value for items in the buffer. 12-bits are available.
|
||||
*/
|
||||
void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value)
|
||||
{
|
||||
assert(index < DAC_DATL_COUNT);
|
||||
|
||||
base->DAT[index].DATL = (uint8_t)(0xFFU & value); /* Low 8-bit. */
|
||||
base->DAT[index].DATH = (uint8_t)((0xF00U & value) >> 8); /* High 4-bit. */
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Sets the current read pointer of the DAC buffer.
|
||||
*
|
||||
* This function sets the current read pointer of the DAC buffer.
|
||||
* The current output value depends on the item indexed by the read pointer. It is updated either by a
|
||||
* software trigger or a hardware trigger. After the read pointer changes, the DAC output value also changes.
|
||||
*
|
||||
* param base DAC peripheral base address.
|
||||
* param index Setting an index value for the pointer.
|
||||
*/
|
||||
void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index)
|
||||
{
|
||||
assert(index < DAC_DATL_COUNT);
|
||||
|
||||
uint8_t tmp8 = base->C2 & ~DAC_C2_DACBFRP_MASK;
|
||||
|
||||
tmp8 |= DAC_C2_DACBFRP(index);
|
||||
base->C2 = tmp8;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Enables interrupts for the DAC buffer.
|
||||
*
|
||||
* param base DAC peripheral base address.
|
||||
* param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable".
|
||||
*/
|
||||
void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask)
|
||||
{
|
||||
mask &= (
|
||||
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
|
||||
DAC_C0_DACBWIEN_MASK |
|
||||
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
|
||||
DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK);
|
||||
base->C0 |= ((uint8_t)mask); /* Write 1 to enable. */
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Disables interrupts for the DAC buffer.
|
||||
*
|
||||
* param base DAC peripheral base address.
|
||||
* param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable".
|
||||
*/
|
||||
void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask)
|
||||
{
|
||||
mask &= (
|
||||
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
|
||||
DAC_C0_DACBWIEN_MASK |
|
||||
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
|
||||
DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK);
|
||||
base->C0 &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to disable. */
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Gets the flags of events for the DAC buffer.
|
||||
*
|
||||
* param base DAC peripheral base address.
|
||||
*
|
||||
* return Mask value for the asserted flags. See "_dac_buffer_status_flags".
|
||||
*/
|
||||
uint32_t DAC_GetBufferStatusFlags(DAC_Type *base)
|
||||
{
|
||||
return (uint32_t)(base->SR & (
|
||||
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
|
||||
DAC_SR_DACBFWMF_MASK |
|
||||
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
|
||||
DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK));
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Clears the flags of events for the DAC buffer.
|
||||
*
|
||||
* param base DAC peripheral base address.
|
||||
* param mask Mask value for flags. See "_dac_buffer_status_flags_t".
|
||||
*/
|
||||
void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask)
|
||||
{
|
||||
mask &= (
|
||||
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
|
||||
DAC_SR_DACBFWMF_MASK |
|
||||
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
|
||||
DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK);
|
||||
base->SR &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to clear flags. */
|
||||
}
|
||||
@ -0,0 +1,51 @@
|
||||
/*
|
||||
* Copyright 2019 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Peripherals v6.0
|
||||
processor: MK82FN256xxx15
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.0.18
|
||||
functionalGroups:
|
||||
- name: BOARD_InitPeripherals
|
||||
called_from_default_init: true
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
component:
|
||||
- type: 'system'
|
||||
- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
|
||||
- global_system_definitions: []
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Included files
|
||||
**********************************************************************************************************************/
|
||||
#include "peripherals.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Initialization functions
|
||||
**********************************************************************************************************************/
|
||||
void BOARD_InitPeripherals(void)
|
||||
{
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* BOARD_InitBootPeripherals function
|
||||
**********************************************************************************************************************/
|
||||
void BOARD_InitBootPeripherals(void)
|
||||
{
|
||||
BOARD_InitPeripherals();
|
||||
}
|
||||
@ -0,0 +1,30 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2020 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Example Header for NfcrdlibEx1_DiscoveryLoop to work with EMVCo Profile.
|
||||
*
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*/
|
||||
|
||||
#ifndef NFCRDLIBEX1_EMVCOPROFILE_H
|
||||
#define NFCRDLIBEX1_EMVCOPROFILE_H
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <phacDiscLoop.h>
|
||||
|
||||
void EmvcoProfileProcess (phacDiscLoop_Sw_DataParams_t * pDataParams, phStatus_t eDiscStatus);
|
||||
|
||||
#endif /* NFCRDLIBEX1_EMVCOPROFILE_H */
|
||||
@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright 2017-2020, NXP
|
||||
*
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
*particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Simplified API ISO MFUL.
|
||||
*
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef EX11_SIMPLIFIEDAPI_ISO_MFUL_H
|
||||
#define EX11_SIMPLIFIEDAPI_ISO_MFUL_H
|
||||
|
||||
/* MFUL_READ takes the page no to read */
|
||||
/* bPageNo can be 0x00 - 0xFF depending upon card layout */
|
||||
#define MFUL_READ(bPageNo) { \
|
||||
phNfcLib_TransmitInput.phNfcLib_MifareUltraLight.bPageNumber = bPageNo; \
|
||||
phNfcLib_TransmitInput.phNfcLib_MifareUltraLight.bCommand = MFUL_Read; \
|
||||
}
|
||||
|
||||
/* MFUL_WRITE takes the page no and data to write */
|
||||
/* bPageNo can be 0x00 - 0xFF depending upon card layout, pData is a pointer to 4 byte page data */
|
||||
#define MFUL_WRITE(bPageNo, pData) { \
|
||||
phNfcLib_TransmitInput.phNfcLib_MifareUltraLight.bPageNumber = bPageNo; \
|
||||
phNfcLib_TransmitInput.phNfcLib_MifareUltraLight.pBuffer = pData; \
|
||||
phNfcLib_TransmitInput.phNfcLib_MifareUltraLight.bCommand = MFUL_Write; \
|
||||
}
|
||||
|
||||
/* MFUL_COMPATIBILITY_WRITE takes the page no and data to write */
|
||||
/* bPageNo can be 0x00 - 0xFF depending upon card layout, pData is a pointer to 16 byte page data */
|
||||
#define MFUL_COMPATIBILITY_WRITE(bPageNo, pData) { \
|
||||
phNfcLib_TransmitInput.phNfcLib_MifareUltraLight.bPageNumber = bPageNo; \
|
||||
phNfcLib_TransmitInput.phNfcLib_MifareUltraLight.pBuffer = pData; \
|
||||
phNfcLib_TransmitInput.phNfcLib_MifareUltraLight.bCommand = MFUL_Compatibility_Write; \
|
||||
}
|
||||
|
||||
#endif /* EX11_SIMPLIFIEDAPI_ISO_MFUL_H */
|
||||
@ -0,0 +1,47 @@
|
||||
/***********************************************************************
|
||||
* $Id:: mw_usbd_desc.h 165 2011-04-14 17:41:11Z usb10131 $
|
||||
*
|
||||
* Project: USB device ROM Stack
|
||||
*
|
||||
* Description:
|
||||
* USB Descriptors Definitions.
|
||||
*
|
||||
***********************************************************************
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef __USBDESC_H__
|
||||
#define __USBDESC_H__
|
||||
|
||||
#include "usbd.h"
|
||||
|
||||
#define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF)
|
||||
#define B3VAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF),(((x) >> 16) & 0xFF)
|
||||
|
||||
#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR))
|
||||
#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR))
|
||||
#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR))
|
||||
#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR))
|
||||
#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR))
|
||||
#define USB_OTHER_SPEED_CONF_SIZE (sizeof(USB_OTHER_SPEED_CONFIGURATION))
|
||||
|
||||
//#define HID_DESC_SIZE (sizeof(HID_DESCRIPTOR))
|
||||
//#define HID_REPORT_DESC_SIZE (sizeof(HID_ReportDescriptor))
|
||||
|
||||
extern const uint8_t HID_ReportDescriptor[];
|
||||
extern const uint16_t HID_ReportDescSize;
|
||||
extern const uint16_t HID_DescOffset;
|
||||
|
||||
#endif /* __USBDESC_H__ */
|
||||
@ -0,0 +1,95 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2016, 2017, 2022 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Software Tag Operation Application Layer Component of
|
||||
* Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*/
|
||||
|
||||
#ifndef PHALTOP_SW_H
|
||||
#define PHALTOP_SW_H
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP_SW
|
||||
|
||||
typedef phStatus_t (*pphalTop_Sw_CheckNdef) (phalTop_Sw_DataParams_t * pDataParams, uint8_t * pTagState );
|
||||
typedef phStatus_t (*pphalTop_Sw_FormatNdef) (phalTop_Sw_DataParams_t * pDataParams);
|
||||
typedef phStatus_t (*pphalTop_Sw_EraseNdef) (phalTop_Sw_DataParams_t * pDataParams);
|
||||
typedef phStatus_t (*pphalTop_Sw_ReadNdef) (phalTop_Sw_DataParams_t * pDataParams, uint8_t * pData, uint32_t * pLength);
|
||||
typedef phStatus_t (*pphalTop_Sw_WriteNdef) (phalTop_Sw_DataParams_t * pDataParams, uint8_t * pData, uint32_t dwLength);
|
||||
typedef phStatus_t (*pphalTop_Sw_Int_SetReadOnly) (phalTop_Sw_DataParams_t * pDataParams);
|
||||
typedef phStatus_t (*pphalTop_Sw_LockBlock) (phalTop_Sw_DataParams_t * pDataParams, uint16_t wBlockNum);
|
||||
|
||||
phStatus_t phalTop_Sw_CheckNdef(
|
||||
phalTop_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pTagState
|
||||
);
|
||||
|
||||
phStatus_t phalTop_Sw_FormatNdef(
|
||||
phalTop_Sw_DataParams_t * pDataParams
|
||||
);
|
||||
|
||||
phStatus_t phalTop_Sw_EraseNdef(
|
||||
phalTop_Sw_DataParams_t * pDataParams
|
||||
);
|
||||
|
||||
phStatus_t phalTop_Sw_Reset(
|
||||
phalTop_Sw_DataParams_t * pDataParams
|
||||
);
|
||||
|
||||
phStatus_t phalTop_Sw_SetConfig(
|
||||
phalTop_Sw_DataParams_t * pDataParams,
|
||||
uint16_t wConfig,
|
||||
uint32_t dwValue
|
||||
);
|
||||
|
||||
phStatus_t phalTop_Sw_GetConfig(
|
||||
phalTop_Sw_DataParams_t * pDataParams,
|
||||
uint16_t wConfig,
|
||||
uint32_t * dwValue
|
||||
);
|
||||
|
||||
phStatus_t phalTop_Sw_ReadNdef(
|
||||
phalTop_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pData,
|
||||
uint32_t * pLength
|
||||
);
|
||||
|
||||
phStatus_t phalTop_Sw_WriteNdef(
|
||||
phalTop_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pData,
|
||||
uint32_t dwLength
|
||||
);
|
||||
|
||||
phStatus_t phalTop_Sw_LockBlock(
|
||||
phalTop_Sw_DataParams_t * pDataParams,
|
||||
uint16_t wBlockNum
|
||||
);
|
||||
|
||||
#ifdef __DEBUG
|
||||
phStatus_t phalTop_Sw_SetPtr(
|
||||
phalTop_Sw_DataParams_t * pDataParams,
|
||||
void * pT1T,
|
||||
void * pT2T,
|
||||
void * pT3T,
|
||||
void * pT4T,
|
||||
void * pT5T,
|
||||
void * pMfcTop
|
||||
);
|
||||
#endif /* __DEBUG */
|
||||
|
||||
#endif /* NXPBUILD__PHAL_TOP_SW */
|
||||
|
||||
#endif /* PHALTOP_SW_H */
|
||||
@ -0,0 +1,318 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3 LTS Patch 2
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
*
|
||||
* The settings in this file configure FreeRTOS correctly for the given hardware
|
||||
* and compiler.
|
||||
*
|
||||
* These settings should not be altered.
|
||||
*------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifndef configENABLE_FPU
|
||||
#error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#ifndef configENABLE_MPU
|
||||
#error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
|
||||
#endif /* configENABLE_MPU */
|
||||
|
||||
#ifndef configENABLE_TRUSTZONE
|
||||
#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
|
||||
#endif /* configENABLE_TRUSTZONE */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Type definitions.
|
||||
*/
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if ( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
* not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* Architecture specifics.
|
||||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portNOP()
|
||||
#define portINLINE __inline
|
||||
#ifndef portFORCE_INLINE
|
||||
#define portFORCE_INLINE inline __attribute__( ( always_inline ) )
|
||||
#endif
|
||||
#define portHAS_STACK_OVERFLOW_CHECKING 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Extern declarations.
|
||||
*/
|
||||
extern BaseType_t xPortIsInsideInterrupt( void );
|
||||
|
||||
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
|
||||
|
||||
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
|
||||
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
|
||||
|
||||
extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
|
||||
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
|
||||
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
|
||||
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
|
||||
#endif /* configENABLE_TRUSTZONE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
|
||||
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
|
||||
#endif /* configENABLE_MPU */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief MPU specific constants.
|
||||
*/
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
#define portUSING_MPU_WRAPPERS 1
|
||||
#define portPRIVILEGE_BIT ( 0x80000000UL )
|
||||
#else
|
||||
#define portPRIVILEGE_BIT ( 0x0UL )
|
||||
#endif /* configENABLE_MPU */
|
||||
|
||||
/* MPU regions. */
|
||||
#define portPRIVILEGED_FLASH_REGION ( 0UL )
|
||||
#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
|
||||
#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
|
||||
#define portPRIVILEGED_RAM_REGION ( 3UL )
|
||||
#define portSTACK_REGION ( 4UL )
|
||||
#define portFIRST_CONFIGURABLE_REGION ( 5UL )
|
||||
#define portLAST_CONFIGURABLE_REGION ( 7UL )
|
||||
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
|
||||
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
|
||||
|
||||
/* Device memory attributes used in MPU_MAIR registers.
|
||||
*
|
||||
* 8-bit values encoded as follows:
|
||||
* Bit[7:4] - 0000 - Device Memory
|
||||
* Bit[3:2] - 00 --> Device-nGnRnE
|
||||
* 01 --> Device-nGnRE
|
||||
* 10 --> Device-nGRE
|
||||
* 11 --> Device-GRE
|
||||
* Bit[1:0] - 00, Reserved.
|
||||
*/
|
||||
#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
|
||||
#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
|
||||
#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
|
||||
#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
|
||||
|
||||
/* Normal memory attributes used in MPU_MAIR registers. */
|
||||
#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
|
||||
#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
|
||||
|
||||
/* Attributes used in MPU_RBAR registers. */
|
||||
#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
|
||||
#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
|
||||
#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
|
||||
|
||||
#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
|
||||
#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
|
||||
#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
|
||||
#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
|
||||
|
||||
#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Settings to define an MPU region.
|
||||
*/
|
||||
typedef struct MPURegionSettings
|
||||
{
|
||||
uint32_t ulRBAR; /**< RBAR for the region. */
|
||||
uint32_t ulRLAR; /**< RLAR for the region. */
|
||||
} MPURegionSettings_t;
|
||||
|
||||
/**
|
||||
* @brief MPU settings as stored in the TCB.
|
||||
*/
|
||||
typedef struct MPU_SETTINGS
|
||||
{
|
||||
uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
|
||||
MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
|
||||
} xMPU_SETTINGS;
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief SVC numbers.
|
||||
*/
|
||||
#define portSVC_ALLOCATE_SECURE_CONTEXT 0
|
||||
#define portSVC_FREE_SECURE_CONTEXT 1
|
||||
#define portSVC_START_SCHEDULER 2
|
||||
#define portSVC_RAISE_PRIVILEGE 3
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Scheduler utilities.
|
||||
*/
|
||||
#define portYIELD() vPortYield()
|
||||
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
|
||||
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
|
||||
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Critical section management.
|
||||
*/
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
|
||||
#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
|
||||
#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Tickless idle/low power functionality.
|
||||
*/
|
||||
#ifndef portSUPPRESS_TICKS_AND_SLEEP
|
||||
extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
|
||||
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Task function macros as described on the FreeRTOS.org WEB site.
|
||||
*/
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Allocate a secure context for the task.
|
||||
*
|
||||
* Tasks are not created with a secure context. Any task that is going to call
|
||||
* secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
|
||||
* secure context before it calls any secure function.
|
||||
*
|
||||
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
|
||||
*/
|
||||
#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
|
||||
|
||||
/**
|
||||
* @brief Called when a task is deleted to delete the task's secure context,
|
||||
* if it has one.
|
||||
*
|
||||
* @param[in] pxTCB The TCB of the task being deleted.
|
||||
*/
|
||||
#define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
|
||||
#else
|
||||
#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
|
||||
#define portCLEAN_UP_TCB( pxTCB )
|
||||
#endif /* configENABLE_TRUSTZONE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
|
||||
/**
|
||||
* @brief Checks whether or not the processor is privileged.
|
||||
*
|
||||
* @return 1 if the processor is already privileged, 0 otherwise.
|
||||
*/
|
||||
#define portIS_PRIVILEGED() xIsPrivileged()
|
||||
|
||||
/**
|
||||
* @brief Raise an SVC request to raise privilege.
|
||||
*
|
||||
* The SVC handler checks that the SVC was raised from a system call and only
|
||||
* then it raises the privilege. If this is called from any other place,
|
||||
* the privilege is not raised.
|
||||
*/
|
||||
#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
|
||||
|
||||
/**
|
||||
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
|
||||
* register.
|
||||
*/
|
||||
#define portRESET_PRIVILEGE() vResetPrivilege()
|
||||
#else
|
||||
#define portIS_PRIVILEGED()
|
||||
#define portRAISE_PRIVILEGE()
|
||||
#define portRESET_PRIVILEGE()
|
||||
#endif /* configENABLE_MPU */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Barriers.
|
||||
*/
|
||||
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
|
||||
* the source code because to do so would cause other compilers to generate
|
||||
* warnings. */
|
||||
#pragma diag_suppress=Be006
|
||||
#pragma diag_suppress=Pa082
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
@ -0,0 +1,457 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors Gratkorn / Austria
|
||||
*
|
||||
* (C)NXP Semiconductors
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
* particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Generic ISO18000-3 Mode3 Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* MWt: Generated 27. January 2010
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHPALI18000P3M3_H
|
||||
#define PHPALI18000P3M3_H
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <phhalHw.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
|
||||
|
||||
/** \defgroup phpalI18000p3m3_Sw Component : Software
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PHPAL_I18000P3M3_SW_ID 0x01U /**< ID for Software I18000P3M3 layer. */
|
||||
|
||||
/**
|
||||
* \brief Software PAL-I18000P3M3 parameter structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t wId; /**< Layer ID for this component, NEVER MODIFY! */
|
||||
void * pHalDataParams; /**< Pointer to the parameter structure of the underlying HAL layer. */
|
||||
uint8_t bSession; /**< Active session of inventory round. */
|
||||
uint8_t abStoredCRC[2]; /**< Stored CRC returned by the tag. */
|
||||
uint8_t bStoredCRCValid; /**< Whether StoredCRC is valid or not. */
|
||||
} phpalI18000p3m3_Sw_DataParams_t;
|
||||
|
||||
/**
|
||||
* \brief Initialise this layer.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_Sw_Init(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wSizeOfDataParams, /**< [In] Specifies the size of the data parameter structure. */
|
||||
void * pHalDataParams /**< [In] Pointer to the parameter structure of the underlying HAL layer. */
|
||||
);
|
||||
|
||||
/** @} */
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3
|
||||
|
||||
/** \defgroup phpalI18000p3m3 ISO/IEC 18000-3 Mode3
|
||||
* \brief These Components implement the ISO/IEC 18000-3 Mode3 support.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \name Targets
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I18000P3M3_TARGET_INVENTORIED_S0 0x00U /**< INVENTORIED_S0 Target. */
|
||||
#define PHPAL_I18000P3M3_TARGET_INVENTORIED_S2 0x02U /**< INVENTORIED_S2 Target. */
|
||||
#define PHPAL_I18000P3M3_TARGET_SL 0x04U /**< SL Target. */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Memory Banks
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I18000P3M3_MEMBANK_RESERVED 0x00U /** < Reserved Memory Bank. */
|
||||
#define PHPAL_I18000P3M3_MEMBANK_UII 0x01U /** < UII Memory Bank. */
|
||||
#define PHPAL_I18000P3M3_MEMBANK_TID 0x02U /** < TID Memory Bank. */
|
||||
#define PHPAL_I18000P3M3_MEMBANK_USER 0x03U /** < User Memory Bank. */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Link Frequencies (DR)
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I18000P3M3_LF_423KHZ 0x00U /**< 423kHz (fc/32). Equivalent to #PHHAL_HW_SUBCARRIER_DUAL DR = 0 */
|
||||
#define PHPAL_I18000P3M3_LF_847KHZ 0x01U /**< 847kHz (fc/16). Equivalent to #PHHAL_HW_SUBCARRIER_QUAD DR = 1*/
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name 'M' Values
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I18000P3M3_M_MANCHESTER_2 0x02U /**< 2 sub-carrier pulse Manchester. Equivalent to #PHHAL_HW_RX_I18000P3M3_FL_423_MAN2 or #PHHAL_HW_RX_I18000P3M3_FL_847_MAN2. */
|
||||
#define PHPAL_I18000P3M3_M_MANCHESTER_4 0x03U /**< 4 sub-carrier pulse Manchester. Equivalent to #PHHAL_HW_RX_I18000P3M3_FL_423_MAN4 or #PHHAL_HW_RX_I18000P3M3_FL_847_MAN4. */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name 'Sel' Values
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I18000P3M3_SEL_ALL_00 0x00U /**< All. */
|
||||
#define PHPAL_I18000P3M3_SEL_ALL_01 0x01U /**< All. */
|
||||
#define PHPAL_I18000P3M3_SEL_NOT_SL 0x02U /**< Select only tags not matching SL. */
|
||||
#define PHPAL_I18000P3M3_SEL_SL 0x03U /**< Select only tags matching SL. */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name 'Session' Values
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I18000P3M3_SESSION_S0 0x00U /**< Session S0. */
|
||||
#define PHPAL_I18000P3M3_SESSION_S1 0x01U /**< Session S1 (Optional). */
|
||||
#define PHPAL_I18000P3M3_SESSION_S2 0x02U /**< Session S2. */
|
||||
#define PHPAL_I18000P3M3_SESSION_S3 0x03U /**< Session S3 (Optional). */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name 'UpDn' Values
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I18000P3M3_UPDN_INCREMENT 0x06U /**< Increment Q. */
|
||||
#define PHPAL_I18000P3M3_UPDN_NOCHANGE 0x00U /**< Do not change Q. */
|
||||
#define PHPAL_I18000P3M3_UPDN_DECREMENT 0x03U /**< Decrement Q. */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name ACK Options
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I18000P3M3_ACK_USE_CRC 0x00U /**< Use StoredCrc for ACK command. */
|
||||
#define PHPAL_I18000P3M3_ACK_USE_HANDLE 0x01U /**< Use given Handle for ACK command. */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Communication Configs
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I18000P3M3_CONFIG_TXLASTBITS 0x0003U /**< Set number of valid bits of last Tx-Byte. */
|
||||
#define PHPAL_I18000P3M3_CONFIG_TIMEOUT_VALUE_MS 0x000EU /**< Set RC Timeout (in [ms]). */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Values used for Communication Configs
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHPAL_I18000P3M3_TXLASTBITS_MAX 0x000FU /**< Maximum value used for configuring TXLASTBITS. */
|
||||
#define PHPAL_I18000P3M3_VALID_TXLASTBITS 0x0007U /**< Valid value of TXLASTBITS. */
|
||||
/*@}*/
|
||||
|
||||
#ifdef NXPRDLIB_REM_GEN_INTFS
|
||||
#include "../comps/phpalI18000p3m3/src/Sw/phpalI18000p3m3_Sw.h"
|
||||
|
||||
#define phpalI18000p3m3_Exchange( pDataParams, wOption, pTxBuffer, wTxLength, bTxLastBits, ppRxBuffer, pRxLength, pRxLastBits) \
|
||||
phpalI18000p3m3_Sw_Exchange((phpalI18000p3m3_Sw_DataParams_t *)pDataParams, wOption, pTxBuffer, \
|
||||
wTxLength, bTxLastBits, ppRxBuffer, pRxLength,pRxLastBits)
|
||||
|
||||
#define phpalI18000p3m3_CreateBeginRoundCmd(pDataParams,bDr,bM,bTRext,bSel,bSession,bRfu,bQ,pBeginRnd) \
|
||||
phpalI18000p3m3_Sw_CreateBeginRoundCmd((phpalI18000p3m3_Sw_DataParams_t *)pDataParams,bDr,bM,bTRext,bSel,bSession,bRfu,bQ,pBeginRnd)
|
||||
|
||||
#define phpalI18000p3m3_CreateSelectCmd(pDataParams,bTarget,bAction,bMemBank,pPointer,bPointerLength, \
|
||||
pMask,bMaskBitLength,bTruncate,pSelectCmd,wLen,bValidBits) \
|
||||
phpalI18000p3m3_Sw_CreateSelectCmd((phpalI18000p3m3_Sw_DataParams_t *)pDataParams,bTarget,bAction,bMemBank,pPointer,bPointerLength, \
|
||||
pMask,bMaskBitLength,bTruncate,pSelectCmd,wLen,bValidBits)
|
||||
|
||||
#define phpalI18000p3m3_Ack( pDataParams, bOption, pHandle, ppRxBuffer, pRxBitLength) \
|
||||
phpalI18000p3m3_Sw_Ack( (phpalI18000p3m3_Sw_DataParams_t *)pDataParams, bOption, pHandle,ppRxBuffer, pRxBitLength)
|
||||
|
||||
#define phpalI18000p3m3_Nak( pDataParams) \
|
||||
phpalI18000p3m3_Sw_Nak((phpalI18000p3m3_Sw_DataParams_t *)pDataParams)
|
||||
|
||||
#define phpalI18000p3m3_ActivateCard(pDataParams, pSelCmd, bSelCmdLen, bNumValidBitsinLastByte, pBeginRndCmd, \
|
||||
bTSprocessing, ppRxBuffer, pRxBufferLen, pMoreCardsAvailable) \
|
||||
phpalI18000p3m3_Sw_ActivateCard((phpalI18000p3m3_Sw_DataParams_t *)pDataParams, pSelCmd, bSelCmdLen, bNumValidBitsinLastByte, pBeginRndCmd, \
|
||||
bTSprocessing, ppRxBuffer, pRxBufferLen, pMoreCardsAvailable)
|
||||
|
||||
#define phpalI18000p3m3_SetConfig( pDataParams, wConfig, wValue) \
|
||||
phpalI18000p3m3_Sw_SetConfig((phpalI18000p3m3_Sw_DataParams_t *)pDataParams, wConfig, wValue)
|
||||
|
||||
#define phpalI18000p3m3_Select(pDataParams, bTarget, bAction, bMemBank, pPointer, bPointerLength, pMask, bMaskBitLength, bTruncate) \
|
||||
phpalI18000p3m3_Sw_Select((phpalI18000p3m3_Sw_DataParams_t *)pDataParams, bTarget, bAction, bMemBank, pPointer, bPointerLength, pMask, bMaskBitLength, bTruncate)
|
||||
|
||||
#else
|
||||
|
||||
/**
|
||||
* \brief Perform Data Exchange with Tag.
|
||||
*
|
||||
* \c wOption can be one of:\n
|
||||
* \li #PH_EXCHANGE_DEFAULT
|
||||
* \li #PH_EXCHANGE_BUFFER_FIRST
|
||||
* \li #PH_EXCHANGE_BUFFER_CONT
|
||||
* \li #PH_EXCHANGE_BUFFER_LAST
|
||||
*
|
||||
* Alternatively, the following bits can be combined:\n
|
||||
* \li #PH_EXCHANGE_BUFFERED_BIT
|
||||
* \li #PH_EXCHANGE_LEAVE_BUFFER_BIT
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_Exchange(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wOption, /**< [In] Option parameter. */
|
||||
uint8_t * pTxBuffer, /**< [In] Data to transmit. */
|
||||
uint16_t wTxLength, /**< [In] Length of input data. */
|
||||
uint8_t bTxLastBits, /**< [In] Number of valid bits of last byte (Tx). */
|
||||
uint8_t ** ppRxBuffer, /**< [Out] Pointer to received data. */
|
||||
uint16_t * pRxLength, /**< [Out] Number of received data bytes including incomplete byte. */
|
||||
uint8_t * pRxLastBits /**< [Out] Number of valid bits of last byte (Rx). */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Create the Select command frame.
|
||||
* This is a utility function to create the Select frame in the required format of ISO 18000p3m3.
|
||||
* Parameters are validated to ensure that wrong values or wrong combinations are checked.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_INVALID_PARAMETER if wrong options are provided.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_CreateSelectCmd(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bTarget, /**< [In] Indicates whether the SL flag or the inventoried flags shall be modified. */
|
||||
uint8_t bAction, /**< [In] Indicates the way of changing the SL flag and the inventoried flags. */
|
||||
uint8_t bMemBank, /**< [In] Memory bank where the mask shall be applied. */
|
||||
uint8_t * pPointer, /**< [In] Memory address where the mask shall be applied. */
|
||||
uint8_t bPointerLength, /**< [In] Length of the pointer, 0->8bits,1->16bits,2->24bits or 3->32bits. */
|
||||
uint8_t * pMask, /**< [In] Contains a bit string that a tag compares against the memory location that begins at pPointer. */
|
||||
uint8_t bMaskBitLength, /**< [In] Length of the mask in bits. */
|
||||
uint8_t bTruncate, /**< [In] Specifies whether a tag load modulates its entire UII (#PH_OFF), or only that portion of the UII immediately following Mask (#PH_ON). */
|
||||
uint8_t * pSelectCmd, /**< [Out] Select Command frame. (Max 39 bytes) */
|
||||
uint8_t * bLen, /**< [Out] Length of Select cmd bytes */
|
||||
uint8_t * bValidBits /**< [Out] Number of valid bits in the last byte of pSelectCmd. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Create the BeginRound command frame.
|
||||
* This is a utility function to create the BeginRound frame in the required format of ISO 18000p3m3.
|
||||
* Parameters are validated to ensure that wrong values or wrong combinations are checked.
|
||||
*
|
||||
* bDr can be one of \n
|
||||
* \li #PHPAL_I18000P3M3_LF_423KHZ
|
||||
* \li #PHPAL_I18000P3M3_LF_847KHZ
|
||||
*
|
||||
* bM (Number of subcarrier cycles per symbol) cane be one of \n
|
||||
* \li #PHPAL_I18000P3M3_M_MANCHESTER_2 (M = 10b)
|
||||
* \li #PHPAL_I18000P3M3_M_MANCHESTER_4 (M = 11b)
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_INVALID_PARAMETER if wrong options are provided.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_CreateBeginRoundCmd(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bDr, /**< [In] Divide ratio. */
|
||||
uint8_t bM, /**< [In] Cycles per symbol. */
|
||||
uint8_t bTRext, /**< [In] Indicates whether a pilot tone shall be used in the T=>R pre-amble (#PH_ON) or not (#PH_OFF). */
|
||||
uint8_t bSel, /**< [In] Indicates which tags shall take part of the inventory round. */
|
||||
uint8_t bSession, /**< [In] Indicates the session of the inventory round. */
|
||||
uint8_t bRfu, /**< [In] RFU (1 bit). */
|
||||
uint8_t bQ, /**< [In] Indicates the number of slots in a round (2^Q slots). */
|
||||
uint8_t * pBeginRnd /**< [Out] Begin round command frame (3 bytes) */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform a Ack for ISO18000-3 Mode3 tags.
|
||||
*
|
||||
*
|
||||
* \c bOption can be one of:\n
|
||||
* \li #PHPAL_I18000P3M3_ACK_USE_CRC - This option is deprecated and no longer used.
|
||||
* \li #PHPAL_I18000P3M3_ACK_USE_HANDLE
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_Ack(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bOption, /**< [In] Option parameter. */
|
||||
uint8_t * pHandle, /**< [In] Handle value, mandatory if \c bOption is #PHPAL_I18000P3M3_ACK_USE_HANDLE; uint8_t[2]. */
|
||||
uint8_t ** ppRxBuffer, /**< [Out] Pointer to Tag data and, if required, PacketCRC. */
|
||||
uint16_t * pRxBitLength /**< [Out] Tag response length in bits. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform a Nak for ISO18000-3 Mode3 tags.
|
||||
* All tags will move to arbitrate state after receive this command.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_Nak(
|
||||
void * pDataParams /**< [In] Pointer to this layer's parameter structure. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Bring the first matching tag to OPEN or SECURED state.
|
||||
*
|
||||
* The command performs a selection followed by an inventory round.
|
||||
* The first responding tag is set to the OPEN or SECURED state and
|
||||
* the tag handle is returned.
|
||||
* If more tags are in the field, it shall resolve collision and
|
||||
* activate one tag. The pMoreCardsAvailable value will be set to 1
|
||||
* if more cards are available in the field.
|
||||
*
|
||||
* Issuing the Select command is optional based on the value of bSelCmdLen parameter.
|
||||
* If bSelCmdLen parameter is zero, then ISO 18000p3m3 Select command is
|
||||
* not issued. Only the BeginRound command is issued.
|
||||
*
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_ActivateCard(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t * pSelCmd, /**< [In] ISO 18000p3m3 Select command frame. */
|
||||
uint8_t bSelCmdLen, /**< [In] Select command length in bytes- 1 to 39 bytes. If set to zero, Select command is not sent. */
|
||||
uint8_t bNumValidBitsinLastByte, /**< [In] Number of valid bits in last byte of pSelCmd. */
|
||||
uint8_t * pBeginRndCmd, /**< [In] ISO 18000p3m3 BeginRound command frame. This is 17bits i.e., 3 bytes are expected. CRC5 should not be provided. */
|
||||
uint8_t bTSprocessing, /**< [In] TimeSlot processing behavior. */
|
||||
uint8_t ** ppRxBuffer, /**< [Out] Pointer to HAL Rx Buffer containing handle of the activated tag. */
|
||||
uint16_t * pRxBufferLen, /**< [Out] Length of response in hal Rx Buffer. */
|
||||
uint8_t * pMoreCardsAvailable /**< [Out] Indicates if more tags are present in the field. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Sets the configuration parameter.
|
||||
*
|
||||
* This function sets the values for the provided configuration parameter
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_SetConfig(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wConfig, /**< [In] Configuration Identifier. */
|
||||
uint16_t wValue /**< [In] Configuration Value. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Select a particular tag population.
|
||||
* This API is deprecated. This operation is now done by the phhalHw_I18000p3m3Inventory() function
|
||||
* of the HAL.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_Select(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bTarget, /**< [In] Indicates whether the SL flag or the inventoried flags shall be modified. */
|
||||
uint8_t bAction, /**< [In] Indicates the way of changing the SL flag and the inventoried flags. */
|
||||
uint8_t bMemBank, /**< [In] Memory bank where the mask shall be applied. */
|
||||
uint8_t * pPointer, /**< [In] Memory address where the mask shall be applied. */
|
||||
uint8_t bPointerLength, /**< [In] Length of the pointer in bytes; 0,1,2 or 3. */
|
||||
uint8_t * pMask, /**< [In] Contains a bit string that a tag compares against the memory location that begins at pPointer. */
|
||||
uint8_t bMaskBitLength, /**< [In] Length of the mask in bits. */
|
||||
uint8_t bTruncate /**< [In] Specifies whether a tag load modulates its entire UII (#PH_OFF), or only that portion of the UII immediately following Mask (#PH_ON). */
|
||||
);
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3_DEPRECATED
|
||||
/**
|
||||
* \brief Perform a BeginRound for ISO18000-3 Mode3 tags.
|
||||
* This API is deprecated. This operation is now done by the phhalHw_I18000p3m3Inventory() function
|
||||
* of the HAL.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_BeginRound(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bDr, /**< [In] Divide ratio. */
|
||||
uint8_t bM, /**< [In] Cycles per symbol. */
|
||||
uint8_t bTRext, /**< [In] Indicates whether a pilot tone shall be used in the T=>R pre-amble (#PH_ON) or not (#PH_OFF). */
|
||||
uint8_t bSel, /**< [In] Indicates which tags shall take part of the inventory round. */
|
||||
uint8_t bSession, /**< [In] Indicates the session of the inventory round. */
|
||||
uint8_t bRfu, /**< [In] RFU (1 bit). */
|
||||
uint8_t bQ, /**< [In] Indicates the number of slots in a round (2^Q slots). */
|
||||
uint8_t * pStoredCRC /**< [Out] Stored CRC of a responding tag. This buffer has to be 2 bytes long. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform a ResizeRound for ISO18000-3 Mode3 tags.
|
||||
* This API is deprecated. The equivalent operation is now done within the phhalHw_I18000p3m3Inventory() function
|
||||
* of the HAL.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_ResizeRound(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bUpDn, /**< [In] Indicates whether and how Q shall be adjusted. */
|
||||
uint8_t * pStoredCRC /**< [Out] Stored CRC of a responding tag. This buffer has to be 2 bytes long. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform a NextSlot for ISO18000-3 Mode3 tags.
|
||||
* This API is deprecated. The equivalent operation is now done within the phhalHw_I18000p3m3Inventory() function
|
||||
* of the HAL.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_NextSlot(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t * pStoredCRC /**< [Out] Stored CRC of a responding tag. This buffer has to be 2 bytes long. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Get the tag data.
|
||||
*
|
||||
* The command returns the tag response to the last ActivateCard or ACK.
|
||||
* This API is deprecated. This functionality is available only when the other deprecated functions
|
||||
* are used.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phpalI18000p3m3_GetSerialNo(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t * pRxBuffer, /**< [Out] StoredCRC; uint8_t[2]. */
|
||||
uint8_t * pRxLength /**< [Out] Length of StoredCRC; 2 bytes. */
|
||||
);
|
||||
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3_DEPRECATED */
|
||||
|
||||
/** @} */
|
||||
#endif /* NXPRDLIB_REM_GEN_INTFS */
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* Extern C */
|
||||
#endif
|
||||
|
||||
#endif /* PHPALI18000P3M3_H */
|
||||
@ -0,0 +1,253 @@
|
||||
__________________________________________________
|
||||
|
||||
NXPNFCRDLIB EXAMPLE :
|
||||
NFCRDLIB_EMVCO_ANALOGCOMPLAPP
|
||||
(V07.10.00)
|
||||
__________________________________________________
|
||||
|
||||
|
||||
Table of Contents
|
||||
_________________
|
||||
|
||||
1 Document Purpose
|
||||
2 Description of the Nfcrdlib_EMVCo_AnalogComplApp
|
||||
3 Restrictions on Nfcrdlib_EMVCo_AnalogComplApp
|
||||
4 Configurations of Nfcrdlib_EMVCo_AnalogComplApp
|
||||
5 Package Contents
|
||||
6 Mandatory materials (not included)
|
||||
7 Hardware Configuration
|
||||
8 Software Configuration
|
||||
9 Steps to build Nfcrdlib_EMVCo_AnalogComplApp for LPC1769 with PN5190 using MCUXpresso
|
||||
10 Steps to build Nfcrdlib_EMVCo_AnalogComplApp for LPC1769 with PN5180 using MCUXpresso
|
||||
11 Steps to build Nfcrdlib_EMVCo_AnalogComplApp for LPC1769 with RC663 using MCUXpresso
|
||||
12 Steps to build Nfcrdlib_EMVCo_AnalogComplApp for PN7462AU using MCUXpresso
|
||||
13 Steps to build Nfcrdlib_EMVCo_AnalogComplApp for FRDM-K82F using MCUXpresso
|
||||
14 Selection of Board / OSAL / Frontend (MCUXpresso)
|
||||
15 Running Nfcrdlib_EMVCo_AnalogComplApp
|
||||
16 List of supported NFC Reader Boards/ICs
|
||||
17 Reference Documents
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
1 Document Purpose
|
||||
==================
|
||||
|
||||
This document describes the steps to be followed to execute
|
||||
Nfcrdlib_EMVCo_AnalogComplApp example as well as it's known problems
|
||||
and restrictions.
|
||||
|
||||
|
||||
2 Description of the Nfcrdlib_EMVCo_AnalogComplApp
|
||||
==================================================
|
||||
|
||||
- Nfcrdlib_EMVCo_AnalogComplApp can be run with CLEV663B, PN5180,
|
||||
PN5190 and PN7462AU. (See Section-16 for supported versions)
|
||||
|
||||
This example contains three mode of operations within itself for the
|
||||
user to choose as below.
|
||||
|
||||
1.EMVCo LoopBack Application
|
||||
|
||||
2.Trans send Type A application
|
||||
|
||||
3.Trans send Type B application
|
||||
|
||||
Above Application modes are used to perform EMVCo3.1(L1) Analog
|
||||
compliance validation. The CPU frequency configured for the Host
|
||||
controller platforms should be sufficient enough to meet EMVCo timing
|
||||
requirements.
|
||||
|
||||
|
||||
3 Restrictions on Nfcrdlib_EMVCo_AnalogComplApp
|
||||
===============================================
|
||||
|
||||
- Nfcrdlib_EMVCo_AnalogComplApp is restricted to be run on NFC Reader
|
||||
Boards/ICs mentioned in Section-16.
|
||||
- The APIs are intended for NXP contact-less reader ICs only, as such
|
||||
the APIs are not to be ported to any technology from any other
|
||||
vendor.
|
||||
- NXP will not support porting to any other vendor platform.
|
||||
- This software project requires NxpNfcRdLib v07.10.00 or later.
|
||||
- **IMPORTANT** The default used MCU Type is K82. When executing
|
||||
example on LPC1769 or PN7462AU, the MCU Type has to be changed in
|
||||
the MCUXpresso IDE.
|
||||
- For switching to MCU Type to PN7462AU, see Section-12
|
||||
- For switching to MCU Type to LPC1769, see Section-9, Section-10 and
|
||||
Section-11.
|
||||
|
||||
|
||||
4 Configurations of Nfcrdlib_EMVCo_AnalogComplApp
|
||||
=================================================
|
||||
|
||||
- This example can be used for running EMVCo3.1(L1) analog compliance
|
||||
validation.
|
||||
|
||||
|
||||
5 Package Contents
|
||||
==================
|
||||
|
||||
- Readme.txt
|
||||
+ This readme file
|
||||
- Nfcrdlib_EMVCo_AnalogComplApp.c
|
||||
+ Main example file.
|
||||
- intfs/Nfcrdlib_EMVCo_AnalogComplApp.h
|
||||
+ Interfaces/Defines specific to the example
|
||||
- intfs/ph_NxpBuild_App.h
|
||||
+ Reader library build configuration file
|
||||
- src/phApp_Helper.c
|
||||
- src/phApp_PN5180_Init.c
|
||||
- src/phApp_PN5190_Init.c
|
||||
- src/phApp_PN7462AU_Init.c
|
||||
- src/phApp_RC663_Init.c
|
||||
- src/phApp_Init.c and intfs/phApp_Init.h
|
||||
+ Common utility functions (common across all examples)
|
||||
- mcux/.cproject and mcux/.project
|
||||
+ MCUXpresso project configuration file
|
||||
- cr_startup_lpc175x_6x.c
|
||||
+ Startup required to compile example for LPC1769 Micro Controller.
|
||||
|
||||
|
||||
6 Mandatory materials (not included)
|
||||
====================================
|
||||
|
||||
- MCUXpresso IDE. It can be downloaded from
|
||||
[http://www.nxp.com/products/:MCUXpresso-IDE]
|
||||
- SDK for Freedom K82 Board
|
||||
([http://www.nxp.com/products/:FRDM-K82F]). The pre-build SDK can
|
||||
be downloaded from
|
||||
[https://mcuxpresso.nxp.com/en/license?hash=9897a8c19a6bc569c3fade7141f0f405&hash_download=true&to_vault=true]
|
||||
See MCUXpresso User Manual for steps needed to install an SDK.
|
||||
- Plugin to extend MCUXpresso to support PN7462AU. (Required for
|
||||
MCUXpresso versions before MCUXpressoIDE_10.0.2)
|
||||
|
||||
- LPCXpresso LPC1769 / Freedom K82 development boards For NFC ICs
|
||||
listed in Section-16 (Note: PN7462AU (Section-16 Bullet-3) does not
|
||||
need any other other microcontroller).
|
||||
|
||||
|
||||
7 Hardware Configuration
|
||||
========================
|
||||
|
||||
Before starting this application, HW Changes may be required for the
|
||||
used board. Refer to the following User Manuals / Application notes
|
||||
before starting with this example.
|
||||
|
||||
- AN11211: Quick Start Up Guide RC663 Blueboard
|
||||
- AN11744: PN5180 Evaluation board quick start guide
|
||||
- AN11802: NFC Reader Library for Linux Installation Guidelines
|
||||
- AN12550: PNEV5190B Evaluation board quick start guide
|
||||
|
||||
|
||||
8 Software Configuration
|
||||
========================
|
||||
|
||||
- The Software can be compiled for Cortex M3 LPC1769 micro-controller,
|
||||
Cortex M4 Freedom K82 and Cortex M0 based PN7462AU from NXP.
|
||||
- Since this example can be configured to run on various MCU ICs and
|
||||
various NFC ICs, appropriate changes are required as mentioned in
|
||||
Section-9, Section-10, Section-11, Section-12 and Section-13.
|
||||
|
||||
|
||||
9 Steps to build Nfcrdlib_EMVCo_AnalogComplApp for LPC1769 with PN5190 using MCUXpresso
|
||||
=======================================================================================
|
||||
|
||||
See "PNEV5190B Evaluation board quick start guide" in AN12550 (See
|
||||
Section-17, Bullet-6 below)
|
||||
|
||||
|
||||
10 Steps to build Nfcrdlib_EMVCo_AnalogComplApp for LPC1769 with PN5180 using MCUXpresso
|
||||
========================================================================================
|
||||
|
||||
See "Importing provided SW example projects" in AN11908 (See
|
||||
Section-17, Bullet-2 below)
|
||||
|
||||
|
||||
11 Steps to build Nfcrdlib_EMVCo_AnalogComplApp for LPC1769 with RC663 using MCUXpresso
|
||||
=======================================================================================
|
||||
|
||||
See "Importing provided SW example projects" in AN11022 (See
|
||||
Section-17, Bullet-3 below)
|
||||
|
||||
|
||||
12 Steps to build Nfcrdlib_EMVCo_AnalogComplApp for PN7462AU using MCUXpresso
|
||||
=============================================================================
|
||||
|
||||
- For MCUXpresso versions before MCUXpressoIDE_10.0.2, See "Adding
|
||||
PN7462AU Plugin" in UM10883. (See Section-17, Bullet-4 below)
|
||||
- See "Importing provided SW example projects" in UM10883.
|
||||
|
||||
|
||||
13 Steps to build Nfcrdlib_EMVCo_AnalogComplApp for FRDM-K82F using MCUXpresso
|
||||
==============================================================================
|
||||
|
||||
See "Import projects to the MCUXpresso" in AN11908. (See Section-17,
|
||||
Bullet-2 below)
|
||||
|
||||
|
||||
14 Selection of Board / OSAL / Frontend (MCUXpresso)
|
||||
====================================================
|
||||
|
||||
For MCUXpresso, the selection of Board / OSAL / Frontend has to be
|
||||
done via -D (Preprocessor defines).
|
||||
|
||||
1) To select the board go to "Project Properties" --> "C/C++ Build"
|
||||
--> "Settings" --> "Preprocessor" --> "Defined symbols (-D)", and
|
||||
define the relevant PHDRIVER_<BoardNFCCombination>_BOARD macro.
|
||||
|
||||
e.g. For using LPC1769 with Pn5180 use
|
||||
PHDRIVER_LPC1769PN5180_BOARD. For list of supported boards refer
|
||||
to Platform\DAL\cfg\BoardSelection.h.
|
||||
|
||||
2) To select the osal/os type, go to "Project Properties" --> "C/C++
|
||||
Build" --> "Settings" --> "Preprocessor" --> "Defined symbols
|
||||
(-D)".
|
||||
|
||||
e.g. For using FreeRTOS use PH_OSAL_FREERTOS. For other options
|
||||
refer to RTOS\phOsal\inc\phOsal_Config.h.
|
||||
|
||||
|
||||
15 Running Nfcrdlib_EMVCo_AnalogComplApp
|
||||
========================================
|
||||
|
||||
User needs to select the Mode of Operation by entering the option
|
||||
value in the console/Terminal window and press Enter as mentioned in
|
||||
the section 2. The running application can now be used for EMVCo
|
||||
Analog Test case validation.
|
||||
|
||||
|
||||
16 List of supported NFC Reader Boards/ICs
|
||||
==========================================
|
||||
|
||||
1) CLEV6630B 2.0 Customer Evaluation Board
|
||||
2) PNEV5180B v2.0 Customer Evaluation Board
|
||||
3) PN7462AU v2.1 Customer Evaluation Board
|
||||
4) PNEV5190B v1.0 Customer Evaluation Board
|
||||
|
||||
|
||||
17 Reference Documents
|
||||
======================
|
||||
|
||||
1) UM10954 : PN5180 SW Quick start guide
|
||||
[http://www.nxp.com/docs/en/user-guide/UM10954.pdf]
|
||||
|
||||
2) AN11908 : NFC Reader Library for FRDM-K82F Board Installation
|
||||
guidelines
|
||||
[http://www.nxp.com/docs/en/application-note/AN11908.pdf]
|
||||
|
||||
3) AN11022 : CLRC663 Evaluation board quick start guide
|
||||
[http://www.nxp.com/docs/en/application-note/AN11022.pdf]
|
||||
|
||||
4) UM10883 : PN7462AU Quick Start Guide - Development Kit
|
||||
[http://www.nxp.com/docs/en/user-guide/UM10883.pdf]
|
||||
|
||||
5) AN11802 : NFC Reader Library for Linux Installation Guidelines
|
||||
[http://www.nxp.com/docs/en/application-note/AN11802.pdf]
|
||||
|
||||
6) AN12550 : PNEV5190B Evaluation board quick start guide
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
||||
For updates of this example, see
|
||||
[http://www.nxp.com/pages/:NFC-READER-LIBRARY]
|
||||
1494
.svn/pristine/0b/0ba8983d08b6e285f3aca5370561bb4d763a010e.svn-base
Normal file
1494
.svn/pristine/0b/0ba8983d08b6e285f3aca5370561bb4d763a010e.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,635 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V3.20
|
||||
* @date 05. March 2013
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2013 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __RBIT __rbit
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/* Define macros for porting to both thumb1 and thumb2.
|
||||
* For thumb1, use low register (r0-r7), specified by constrant "l"
|
||||
* Otherwise, use general registers, specified by constrant "r" */
|
||||
#if defined (__thumb__) && !defined (__thumb2__)
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||||
#else
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||||
#endif
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb");
|
||||
}
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb");
|
||||
}
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb");
|
||||
}
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||||
return __builtin_bswap32(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
return (short)__builtin_bswap16(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << (32 - op2));
|
||||
}
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex" ::: "memory");
|
||||
}
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
@ -0,0 +1,831 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2009, 2018-2021, 2023 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Software ISO14443-3A Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
*/
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <phhalHw.h>
|
||||
#include <phpalI14443p3a.h>
|
||||
#include <ph_RefDefs.h>
|
||||
#include <phNxpNfcRdLib_Config.h>
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
|
||||
|
||||
#include "phpalI14443p3a_Sw.h"
|
||||
#include "phpalI14443p3a_Sw_Int.h"
|
||||
|
||||
phStatus_t phpalI14443p3a_Sw_Init(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams,
|
||||
uint16_t wSizeOfDataParams,
|
||||
void * pHalDataParams
|
||||
)
|
||||
{
|
||||
if (sizeof(phpalI14443p3a_Sw_DataParams_t) != wSizeOfDataParams)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
PH_ASSERT_NULL (pDataParams);
|
||||
PH_ASSERT_NULL (pHalDataParams);
|
||||
|
||||
/* init private data */
|
||||
pDataParams->wId = PH_COMP_PAL_ISO14443P3A | PHPAL_I14443P3A_SW_ID;
|
||||
pDataParams->pHalDataParams = pHalDataParams;
|
||||
pDataParams->bUidLength = 0;
|
||||
pDataParams->bUidComplete = 0;
|
||||
pDataParams->bOpeMode = RD_LIB_MODE_NFC;
|
||||
pDataParams->bPollCmd = PHPAL_I14443P3A_USE_REQA;
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
/* Emvco: Added for EMVCO This function is used to config parameter for phpalI14443p3a */
|
||||
phStatus_t phpalI14443p3a_Sw_SetConfig(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams,
|
||||
uint16_t wConfig,
|
||||
uint16_t wValue
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
|
||||
switch (wConfig)
|
||||
{
|
||||
/* Emvco: To Define Running Mode for RdLib: Either Nfc, EMVCO, ISO */
|
||||
case PHPAL_I14443P3A_CONFIG_OPE_MODE:
|
||||
{
|
||||
pDataParams->bOpeMode = (uint8_t)wValue;
|
||||
break;
|
||||
}
|
||||
|
||||
case PHPAL_I14443P3A_CONFIG_POLL_CMD:
|
||||
{
|
||||
pDataParams->bPollCmd = (uint8_t)wValue;
|
||||
break;
|
||||
}
|
||||
|
||||
case PHPAL_I14443P3A_CONFIG_TIMEOUT_VALUE_US:
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
wValue));
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_PARAMETER, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
|
||||
}
|
||||
|
||||
/* Emvco: Added for EMVCO This function is used to config parameter for phpalI14443p3a */
|
||||
phStatus_t phpalI14443p3a_Sw_GetConfig(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams,
|
||||
uint16_t wConfig,
|
||||
uint16_t *pValue
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
|
||||
switch (wConfig)
|
||||
{
|
||||
/* Emvco: To Define Running Mode for RdLib: Either Nfc, EMVCO, ISO */
|
||||
case PHPAL_I14443P3A_CONFIG_OPE_MODE:
|
||||
{
|
||||
*pValue = (uint16_t)pDataParams->bOpeMode;
|
||||
break;
|
||||
}
|
||||
|
||||
case PHPAL_I14443P3A_CONFIG_POLL_CMD:
|
||||
{
|
||||
*pValue = (uint16_t)pDataParams->bPollCmd;
|
||||
break;
|
||||
}
|
||||
|
||||
case PHPAL_I14443P3A_CONFIG_TIMEOUT_VALUE_US:
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_GetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
pValue));
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_PARAMETER, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
|
||||
}
|
||||
|
||||
phStatus_t phpalI14443p3a_Sw_RequestA(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pAtqa
|
||||
)
|
||||
{
|
||||
return phpalI14443p3a_Sw_RequestAEx(pDataParams, PHPAL_I14443P3A_REQUEST_CMD, pAtqa);
|
||||
}
|
||||
|
||||
phStatus_t phpalI14443p3a_Sw_WakeUpA(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pAtqa
|
||||
)
|
||||
{
|
||||
return phpalI14443p3a_Sw_RequestAEx(pDataParams, PHPAL_I14443P3A_WAKEUP_CMD, pAtqa);
|
||||
}
|
||||
|
||||
phStatus_t phpalI14443p3a_Sw_HaltA(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM cmd[2];
|
||||
uint8_t * PH_MEMLOC_REM pResp = NULL;
|
||||
uint16_t PH_MEMLOC_REM wRespLength = 0;
|
||||
|
||||
/* Set halt timeout */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
PHPAL_I14443P3A_HALT_TIME_US + PHPAL_I14443P3A_EXT_TIME_US));
|
||||
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_TXCRC, PH_ON));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_RXCRC, PH_ON));
|
||||
|
||||
/* Send HltA command */
|
||||
cmd[0] = PHPAL_I14443P3A_HALT_CMD;
|
||||
cmd[1] = 0x00;
|
||||
|
||||
status = phhalHw_Exchange(pDataParams->pHalDataParams, PH_EXCHANGE_DEFAULT, cmd, 2, &pResp, &wRespLength);
|
||||
|
||||
switch (status & PH_ERR_MASK)
|
||||
{
|
||||
/* HltA command should timeout -> success */
|
||||
case PH_ERR_IO_TIMEOUT:
|
||||
return PH_ERR_SUCCESS;
|
||||
/* Return protocol error */
|
||||
case PH_ERR_SUCCESS:
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
/* Return other errors */
|
||||
default:
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
phStatus_t phpalI14443p3a_Sw_Anticollision(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bCascadeLevel,
|
||||
uint8_t * pUidIn,
|
||||
uint8_t bNvbUidIn,
|
||||
uint8_t * pUidOut,
|
||||
uint8_t * pNvbUidOut
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM bIsSelect;
|
||||
uint8_t PH_MEMLOC_REM bCmdBuffer[10];
|
||||
uint8_t * PH_MEMLOC_REM pRcvBuffer = NULL;
|
||||
uint16_t PH_MEMLOC_REM wSndBytes;
|
||||
uint16_t PH_MEMLOC_REM wRcvBytes = 0;
|
||||
uint16_t PH_MEMLOC_REM wRcvBits = 0;
|
||||
uint8_t PH_MEMLOC_REM bUidStartIndex;
|
||||
uint8_t PH_MEMLOC_REM bBitCount;
|
||||
|
||||
/* Check for invalid bNvbUidIn parameter */
|
||||
if ((bNvbUidIn > 0x40U) || ((bNvbUidIn & 0x0FU) > 0x07U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
/* Check for invalid bCascadeIndex parameter */
|
||||
switch (bCascadeLevel)
|
||||
{
|
||||
case PHPAL_I14443P3A_CASCADE_LEVEL_1:
|
||||
/* Reset UID length */
|
||||
pDataParams->bUidLength = 0;
|
||||
case PHPAL_I14443P3A_CASCADE_LEVEL_2:
|
||||
case PHPAL_I14443P3A_CASCADE_LEVEL_3:
|
||||
break;
|
||||
default:
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
/* Reset UID complete flag */
|
||||
pDataParams->bUidComplete = 0;
|
||||
|
||||
/* ANTICOLLISION: Disable CRC */
|
||||
if (bNvbUidIn != 0x40U)
|
||||
{
|
||||
bIsSelect = 0;
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_TXCRC, PH_OFF));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_RXCRC, PH_OFF));
|
||||
}
|
||||
/* SELECT: Enable CRC */
|
||||
else
|
||||
{
|
||||
bIsSelect = 1;
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_TXCRC, PH_ON));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_RXCRC, PH_ON));
|
||||
}
|
||||
|
||||
/* Init. command buffer */
|
||||
bCmdBuffer[0] = bCascadeLevel;
|
||||
(void)memset(&bCmdBuffer[2], 0x00, 5);
|
||||
|
||||
/* Copy valid UID bits */
|
||||
wSndBytes = (uint16_t)(((((uint16_t)bNvbUidIn) & 0xF0U) >> 4U) + (((bNvbUidIn & 0x0FU) != 0U) ? 1U : 0U));
|
||||
(void)memcpy(&bCmdBuffer[2], pUidIn, (size_t)wSndBytes);
|
||||
wSndBytes += 2U;
|
||||
|
||||
/* SELECT: Add BCC */
|
||||
if (0U != (bIsSelect))
|
||||
{
|
||||
bNvbUidIn = 0x50;
|
||||
bCmdBuffer[6] = pUidIn[0] ^ pUidIn[1] ^ pUidIn[2] ^ pUidIn[3];
|
||||
++wSndBytes;
|
||||
}
|
||||
|
||||
/* Encode NVB */
|
||||
bCmdBuffer[1] = bNvbUidIn + 0x20U;
|
||||
|
||||
/* Adjust Rx-Align */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_RXALIGN, (((uint16_t)bNvbUidIn) & 0x07U)));
|
||||
|
||||
/* Adjust TxBits */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_TXLASTBITS, (((uint16_t)bNvbUidIn) & 0x07U)));
|
||||
|
||||
/* Send the ANTICOLLISION command */
|
||||
status = phhalHw_Exchange(pDataParams->pHalDataParams, PH_EXCHANGE_DEFAULT, bCmdBuffer, wSndBytes, &pRcvBuffer, &wRcvBytes);
|
||||
|
||||
/* Reset RxAlignment */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_RXALIGN, 0));
|
||||
|
||||
/* Check status, Collision is allowed for anti-collision command. */
|
||||
if ((bIsSelect == 0U) && ((status & PH_ERR_MASK) == PH_ERR_COLLISION_ERROR))
|
||||
{
|
||||
/* Retrieve number of valid bits of last byte */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_GetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_RXLASTBITS, &wRcvBits));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check for protocol error */
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS_INCOMPLETE_BYTE)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
/* Return on other errors */
|
||||
else
|
||||
{
|
||||
PH_CHECK_SUCCESS(status);
|
||||
}
|
||||
|
||||
/* whole byte valid */
|
||||
wRcvBits = 0;
|
||||
}
|
||||
|
||||
/* Add received data to UID */
|
||||
if (bIsSelect == 0U)
|
||||
{
|
||||
/* Retrieve byte-starting-index of received Uid */
|
||||
bUidStartIndex = (uint8_t)((bNvbUidIn & 0xF0U) >> 4U);
|
||||
|
||||
/* Add new bitcount */
|
||||
bBitCount = (uint8_t)(((((uint16_t)bNvbUidIn) >> 4U) << 3U) + (wRcvBytes << 3U) + wRcvBits);
|
||||
|
||||
/* Last incomplete byte is added to wRcvBytes, so remove that again */
|
||||
if (wRcvBits > 0U)
|
||||
{
|
||||
bBitCount -= 8U;
|
||||
}
|
||||
|
||||
/* Convert bitcount to NVB format */
|
||||
*pNvbUidOut = (uint8_t)(((bBitCount >> 3U) << 4U) + (bBitCount & 0x07U));
|
||||
|
||||
/* We do not tolerate more than (5u * 8 =)40 bits because it would lead to buffer overflows */
|
||||
if (*pNvbUidOut > 0x50U)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
/* After successfull reception, the UID must be exact 40 bits */
|
||||
if (((status & PH_ERR_MASK) == PH_ERR_SUCCESS) && (*pNvbUidOut != 0x50U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
/* Copy received bytes to uid */
|
||||
if (wRcvBytes > 0U)
|
||||
{
|
||||
/* Incomplete byte sent: Merge Rx-Aligned first byte */
|
||||
if (0U != (bNvbUidIn & 0x07U))
|
||||
{
|
||||
bCmdBuffer[2U + bUidStartIndex] = (bCmdBuffer[2U + bUidStartIndex] & (uint8_t)((1U << (bNvbUidIn & 0x07U)) - 1U)) |
|
||||
(pRcvBuffer[0] & (uint8_t)(0xFFU << (bNvbUidIn & 0x07U)));
|
||||
}
|
||||
/* Else just copy the first byte */
|
||||
else
|
||||
{
|
||||
bCmdBuffer[2U + bUidStartIndex] = pRcvBuffer[0];
|
||||
}
|
||||
|
||||
/* Add the rest of the uid bytes */
|
||||
(void)memcpy(&bCmdBuffer[2U + bUidStartIndex + 1U], &pRcvBuffer[1], (size_t)(((uint32_t)wRcvBytes) - 1u));
|
||||
}
|
||||
|
||||
/* Anticollision finished */
|
||||
if (*pNvbUidOut > 0x40U)
|
||||
{
|
||||
/* Collision in BCC byte can never happen */
|
||||
if (*pNvbUidOut < 0x50U)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_FRAMING_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
/* Remove BCC from NvbUidOut */
|
||||
*pNvbUidOut = 0x40;
|
||||
--wRcvBytes;
|
||||
|
||||
/* BCC Check */
|
||||
if ((bCmdBuffer[2] ^ bCmdBuffer[3] ^ bCmdBuffer[4] ^ bCmdBuffer[5]) != bCmdBuffer[6])
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_FRAMING_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy UID */
|
||||
(void)memcpy(pUidOut, &bCmdBuffer[2], (size_t)(bUidStartIndex + ((uint32_t)wRcvBytes)));
|
||||
}
|
||||
/* Return SAK instead of the UID */
|
||||
else
|
||||
{
|
||||
/* only one byte allowed */
|
||||
if (wRcvBytes != 1U)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
/* Cascade Bit is set */
|
||||
if (0U != (pRcvBuffer[0] & 0x04U))
|
||||
{
|
||||
/* If additional cascade levels are impossible -> protocol error */
|
||||
if (bCascadeLevel == PHPAL_I14443P3A_CASCADE_LEVEL_3)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
/* Cascade tag does not match -> protocol error */
|
||||
if (pUidIn[0] != PHPAL_I14443P3A_CASCADE_TAG)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
/* Ignore Cascade Tag */
|
||||
(void)memcpy(&pDataParams->abUid[pDataParams->bUidLength], &pUidIn[1], 3);
|
||||
|
||||
/* Increment Uid length */
|
||||
pDataParams->bUidLength += 3U;
|
||||
}
|
||||
/* Cascade Bit is cleared -> no further cascade levels */
|
||||
else
|
||||
{
|
||||
/* Cascade tag does not match -> protocol error */
|
||||
if (pUidIn[0] == PHPAL_I14443P3A_CASCADE_TAG)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
/* Copy all uid bytes except BCC */
|
||||
(void)memcpy(&pDataParams->abUid[pDataParams->bUidLength], &pUidIn[0], 4);
|
||||
|
||||
/* Increment Uid length */
|
||||
pDataParams->bUidLength += 4U;
|
||||
|
||||
/* Set UID complete flag */
|
||||
pDataParams->bUidComplete = 1;
|
||||
|
||||
/* set default card timeout */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_MS,
|
||||
PHPAL_I14443P3A_TIMEOUT_DEFAULT_MS));
|
||||
}
|
||||
|
||||
/* Copy SAK */
|
||||
pUidOut[0] = pRcvBuffer[0];
|
||||
}
|
||||
|
||||
return PH_ADD_COMPCODE(status, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
phStatus_t phpalI14443p3a_Sw_Select(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bCascadeLevel,
|
||||
uint8_t * pUidIn,
|
||||
uint8_t * pSak
|
||||
)
|
||||
{
|
||||
uint8_t PH_MEMLOC_REM bDummy;
|
||||
return phpalI14443p3a_Sw_Anticollision(pDataParams, bCascadeLevel, pUidIn, 0x40, pSak, &bDummy);
|
||||
}
|
||||
|
||||
phStatus_t phpalI14443p3a_Sw_ActivateCard(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pUidIn,
|
||||
uint8_t bLenUidIn,
|
||||
uint8_t * pUidOut,
|
||||
uint8_t * pLenUidOut,
|
||||
uint8_t * pSak,
|
||||
uint8_t * pMoreCardsAvailable
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status = PH_ERR_SUCCESS;
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM bCascadeLevel;
|
||||
uint8_t PH_MEMLOC_COUNT bCascadeIndex;
|
||||
uint8_t PH_MEMLOC_REM bUidIndex;
|
||||
uint8_t PH_MEMLOC_REM bNvbUid;
|
||||
uint8_t PH_MEMLOC_REM bAtqa[2] = {0};
|
||||
uint8_t PH_MEMLOC_REM bUid[4];
|
||||
uint8_t PH_MEMLOC_COUNT bRetryCount;
|
||||
uint8_t PH_MEMLOC_REM bCollDetected = PH_OFF;
|
||||
|
||||
bRetryCount = 0;
|
||||
|
||||
/* Parameter check */
|
||||
if ((bLenUidIn != 0U) &&
|
||||
(bLenUidIn != 4U) &&
|
||||
(bLenUidIn != 7U) &&
|
||||
(bLenUidIn != 10U)&&
|
||||
(pDataParams->bPollCmd != PHPAL_I14443P3A_USE_WUPA))
|
||||
{
|
||||
/* Given UID length is invalid, return error */
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
/* initialise to zero, for VS studio warning */
|
||||
bCascadeLevel = 0;
|
||||
/* Clear Uid */
|
||||
(void)memset(bUid, 0x00, 4);
|
||||
|
||||
/* Clear Uid lengths */
|
||||
bUidIndex = 0;
|
||||
*pLenUidOut = 0;
|
||||
|
||||
/* Clear the more cards available flag */
|
||||
*pMoreCardsAvailable = PH_OFF;
|
||||
|
||||
if(pDataParams->bOpeMode == RD_LIB_MODE_EMVCO)
|
||||
{
|
||||
status = phpalI14443p3a_Sw_WakeUpA(pDataParams, bAtqa);
|
||||
/* As per EMVCo 2.6 req 9.6.1.3, wait for at least Tmin retransmission in case of timeout error. */
|
||||
while (((status & PH_ERR_MASK) == PH_ERR_IO_TIMEOUT) && (bRetryCount < PH_NXPNFCRDLIB_CONFIG_EMVCO_RETRYCOUNT))
|
||||
{
|
||||
bRetryCount++;
|
||||
/* Wait for at least Tmin retransmission delay. */
|
||||
PH_CHECK_SUCCESS_FCT(status, phhalHw_Wait(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_TIME_MICROSECONDS,
|
||||
PH_NXPNFCRDLIB_CONFIG_EMVCO_DEFAULT_RETRANSMISSION));
|
||||
|
||||
status = phpalI14443p3a_Sw_WakeUpA(pDataParams, bAtqa);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if( (pDataParams->bOpeMode == RD_LIB_MODE_ISO) && (pDataParams->bPollCmd == PHPAL_I14443P3A_USE_WUPA))
|
||||
{
|
||||
status = phpalI14443p3a_Sw_WakeUpA(pDataParams, bAtqa);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (bLenUidIn == 0U)
|
||||
{
|
||||
status = phpalI14443p3a_Sw_RequestA(pDataParams, bAtqa);
|
||||
}
|
||||
/* UidIn is given -> WupA */
|
||||
else
|
||||
{
|
||||
status = phpalI14443p3a_Sw_WakeUpA(pDataParams, bAtqa);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Collision error may happen */
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_COLLISION_ERROR)
|
||||
{
|
||||
/* Emvco: case_id TA304_XY */
|
||||
if(pDataParams->bOpeMode == RD_LIB_MODE_EMVCO)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
bCollDetected = PH_ON;
|
||||
|
||||
/* Set the more cards available flag */
|
||||
*pMoreCardsAvailable = PH_ON;
|
||||
}
|
||||
/* Status check */
|
||||
else
|
||||
{
|
||||
PH_CHECK_SUCCESS(status);
|
||||
}
|
||||
|
||||
/* Go through all cascade levels */
|
||||
for (bCascadeIndex = 0; bCascadeIndex < 3U; bCascadeIndex++)
|
||||
{
|
||||
/* Set cascade level tags */
|
||||
switch (bCascadeIndex)
|
||||
{
|
||||
case 0:
|
||||
bCascadeLevel = PHPAL_I14443P3A_CASCADE_LEVEL_1;
|
||||
break;
|
||||
case 1:
|
||||
bCascadeLevel = PHPAL_I14443P3A_CASCADE_LEVEL_2;
|
||||
break;
|
||||
case 2:
|
||||
bCascadeLevel = PHPAL_I14443P3A_CASCADE_LEVEL_3;
|
||||
break;
|
||||
/* Default Case is not required as it will be a Dead Code due to the condition in for() loop statement. */
|
||||
} /* PRQA S 2002 */
|
||||
|
||||
/* Copy know Uid part if neccessary */
|
||||
if (bLenUidIn == (bUidIndex + 4U))
|
||||
{
|
||||
/* Copy whole Uid if this is the only cascade level */
|
||||
(void)memcpy(&bUid[0], &pUidIn[bUidIndex], 4);
|
||||
|
||||
/* [Incrementing Uid index would have no effect] */
|
||||
|
||||
/* All bits except BCC are valid */
|
||||
bNvbUid = 0x40;
|
||||
}
|
||||
else if (bLenUidIn > (bUidIndex + /* */ 4U))
|
||||
{
|
||||
/* Prepend cascade tag if we expect more cascade levels*/
|
||||
bUid[0] = PHPAL_I14443P3A_CASCADE_TAG;
|
||||
|
||||
/* Only three more uid bytes are valid for this level */
|
||||
(void)memcpy(&bUid[1], &pUidIn[bUidIndex], 3);
|
||||
|
||||
/* Increment Uid index */
|
||||
bUidIndex += 3U;
|
||||
|
||||
/* All bits except BCC are valid */
|
||||
bNvbUid = 0x40;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No Uid given */
|
||||
bNvbUid = 0;
|
||||
}
|
||||
|
||||
/* Anticollision Loop */
|
||||
while (bNvbUid != 0x40U)
|
||||
{
|
||||
/* Perform single anticollision command */
|
||||
status = phpalI14443p3a_Sw_Anticollision(pDataParams, bCascadeLevel, bUid, bNvbUid, bUid, &bNvbUid);
|
||||
|
||||
/* As per EMVCo 2.6 req 9.6.1.3, wait for at least Tmin retransmission in case of timeout error. */
|
||||
if (pDataParams->bOpeMode == RD_LIB_MODE_EMVCO)
|
||||
{
|
||||
bRetryCount = 0;
|
||||
while (((status & PH_ERR_MASK) == PH_ERR_IO_TIMEOUT) && (bRetryCount < PH_NXPNFCRDLIB_CONFIG_EMVCO_RETRYCOUNT))
|
||||
{
|
||||
bRetryCount++;
|
||||
/* Wait for at least Tmin retransmission delay. */
|
||||
PH_CHECK_SUCCESS_FCT(status, phhalHw_Wait(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_TIME_MICROSECONDS,
|
||||
PH_NXPNFCRDLIB_CONFIG_EMVCO_DEFAULT_RETRANSMISSION));
|
||||
|
||||
status = phpalI14443p3a_Sw_Anticollision(pDataParams, bCascadeLevel, bUid, bNvbUid, bUid, &bNvbUid);
|
||||
}
|
||||
}
|
||||
/* Collision error occured, add one (zero-)bit to Uid */
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_COLLISION_ERROR)
|
||||
{
|
||||
/* Emvco: case_id TA302_00 */
|
||||
if(pDataParams->bOpeMode == RD_LIB_MODE_EMVCO)
|
||||
{
|
||||
/* Report Error to Application and Application will perform PICC Reset */
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Set the more cards available flag */
|
||||
*pMoreCardsAvailable = PH_ON;
|
||||
|
||||
/* Increment NvbUid by one bit */
|
||||
if ((bNvbUid & 0x07U) < 7U)
|
||||
{
|
||||
bNvbUid++;
|
||||
}
|
||||
/* This is more difficult if we have to increment the bytecount */
|
||||
else
|
||||
{
|
||||
bNvbUid = (uint8_t)((((bNvbUid & 0xF0U) >> 4U) + 1U) << 4U);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check success */
|
||||
PH_CHECK_SUCCESS(status);
|
||||
}
|
||||
|
||||
if(bCollDetected == PH_OFF)
|
||||
{
|
||||
/* Emvco: case_id 302_10 */
|
||||
/*
|
||||
* Digital Proto: Article 4.7.2 and 4.7.2.4
|
||||
* ISO14443-3 Article 6.5.2.1
|
||||
* EMVCo article 5.4.2
|
||||
* So For Single UID Size The NFC Forum Device MUST set nfcid10 of a single-size NFCID1 and nfcid13
|
||||
* of a double-size NFCID1 to a value different from 88h.
|
||||
*/
|
||||
if(
|
||||
( (((bAtqa[0] & 0xC0U) == 0x00U) && (bCascadeLevel == PHPAL_I14443P3A_CASCADE_LEVEL_1))||
|
||||
(((bAtqa[0] & 0xC0U) == 0x40U) && (bCascadeLevel == PHPAL_I14443P3A_CASCADE_LEVEL_2)) ) &&
|
||||
(bUid[0] == PHPAL_I14443P3A_CASCADE_TAG)
|
||||
)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
statusTmp = phpalI14443p3a_Sw_Select(pDataParams, bCascadeLevel, bUid, pSak);
|
||||
|
||||
/* As per EMVCo 2.6 req 9.6.1.3, wait for at least Tmin retransmission in case of timeout error. */
|
||||
if (pDataParams->bOpeMode == RD_LIB_MODE_EMVCO)
|
||||
{
|
||||
bRetryCount = 0;
|
||||
while (((statusTmp & PH_ERR_MASK) == PH_ERR_IO_TIMEOUT) && (bRetryCount < PH_NXPNFCRDLIB_CONFIG_EMVCO_RETRYCOUNT))
|
||||
{
|
||||
bRetryCount++;
|
||||
/* Wait for at least Tmin retransmission delay. */
|
||||
PH_CHECK_SUCCESS_FCT(status, phhalHw_Wait(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_TIME_MICROSECONDS,
|
||||
PH_NXPNFCRDLIB_CONFIG_EMVCO_DEFAULT_RETRANSMISSION));
|
||||
|
||||
statusTmp = phpalI14443p3a_Sw_Select(pDataParams, bCascadeLevel, bUid, pSak);
|
||||
}
|
||||
}
|
||||
|
||||
/* Emvco: Case_id TA305. EMVCo Req. 9.6.1.2 */
|
||||
PH_CHECK_SUCCESS(statusTmp);
|
||||
|
||||
/* Cascade Bit is cleared -> no further cascade levels */
|
||||
if ((pSak[0] & 0x04U) == 0U)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Return UID */
|
||||
(void)memcpy(pUidOut, pDataParams->abUid, pDataParams->bUidLength);
|
||||
*pLenUidOut = pDataParams->bUidLength;
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalI14443p3a_Sw_Exchange(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams,
|
||||
uint16_t wOption,
|
||||
uint8_t * pTxBuffer,
|
||||
uint16_t wTxLength,
|
||||
uint8_t ** ppRxBuffer,
|
||||
uint16_t * pRxLength
|
||||
)
|
||||
{
|
||||
/* direct mapping of HAL exchange function */
|
||||
return phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
wOption,
|
||||
pTxBuffer,
|
||||
wTxLength,
|
||||
ppRxBuffer,
|
||||
pRxLength);
|
||||
}
|
||||
|
||||
phStatus_t phpalI14443p3a_Sw_RequestAEx(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bReqCode,
|
||||
uint8_t * pAtqa
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
phStatus_t PH_MEMLOC_REM Status;
|
||||
uint8_t PH_MEMLOC_REM cmd[1];
|
||||
uint8_t * PH_MEMLOC_REM pResp = NULL;
|
||||
uint16_t PH_MEMLOC_REM wRespLength = 0;
|
||||
uint16_t PH_MEMLOC_REM wRegister;
|
||||
|
||||
/* Disable MIFARE Classic contactless IC Crypto1 */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_DISABLE_MF_CRYPTO1,
|
||||
PH_ON));
|
||||
|
||||
/* Reset default data rates */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TXDATARATE_FRAMING,
|
||||
PHHAL_HW_RF_DATARATE_106));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_RXDATARATE_FRAMING,
|
||||
PHHAL_HW_RF_DATARATE_106));
|
||||
|
||||
/* Set selection timeout */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
PHPAL_I14443P3A_SELECTION_TIME_US + PHPAL_I14443P3A_EXT_TIME_US));
|
||||
|
||||
/* Retrieve RxWaitTime */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_GetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_RXWAIT_US, &wRegister));
|
||||
/* Set RxWaitTime to 76 microseconds equivalent to 8 Bits. */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_RXWAIT_US, 76));
|
||||
|
||||
/* Switch off CRC */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_TXCRC, PH_OFF));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_RXCRC, PH_OFF));
|
||||
|
||||
/* Only 7 bits are valid */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_TXLASTBITS, 7));
|
||||
|
||||
/* Send ReqA command */
|
||||
cmd[0] = bReqCode;
|
||||
statusTmp = phhalHw_Exchange(pDataParams->pHalDataParams, PH_EXCHANGE_DEFAULT, cmd, 1, &pResp, &wRespLength);
|
||||
|
||||
/* Restore previous RxWaitTime */
|
||||
PH_CHECK_SUCCESS_FCT(Status, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_RXWAIT_US, wRegister));
|
||||
|
||||
PH_CHECK_SUCCESS(statusTmp);
|
||||
/* Check and copy ATQA */
|
||||
if (wRespLength == PHPAL_I14443P3A_ATQA_LENGTH)
|
||||
{
|
||||
(void)memcpy(pAtqa, pResp, PHPAL_I14443P3A_ATQA_LENGTH);
|
||||
/* Emvco: case_id: TA304_10, TA304_11, TA304_12 */
|
||||
if(pDataParams->bOpeMode == RD_LIB_MODE_EMVCO)
|
||||
{
|
||||
/*5.3.2*/
|
||||
if(0U != (pAtqa[1] & 0xF0U)) /* Most significant nibble of byte 2 must be 0 */
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* NFCForum-TS-DigitalProtocol-1.0, Requirement 18, Section 4.6.3.3 */
|
||||
if((((pAtqa[0] & 0x1FU) == 0x00U) && ((pAtqa[1] & 0x0FU) != 0x0CU)) || (((pAtqa[1] & 0x0FU) == 0x0CU) && ((pAtqa[0] & 0x1FU) != 0x00U)))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalI14443p3a_Sw_GetSerialNo(
|
||||
phpalI14443p3a_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pUidOut,
|
||||
uint8_t * pLenUidOut
|
||||
)
|
||||
{
|
||||
/* Return an error if UID is not complete */
|
||||
if (0U == (pDataParams->bUidComplete))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_USE_CONDITION, PH_COMP_PAL_ISO14443P3A);
|
||||
}
|
||||
|
||||
/* Copy UID */
|
||||
(void)memcpy(pUidOut, pDataParams->abUid, pDataParams->bUidLength);
|
||||
*pLenUidOut = pDataParams->bUidLength;
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
|
||||
@ -0,0 +1,84 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2016-2023 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
*
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHALMFNTAG42XDNA_SW_INT_H
|
||||
#define PHALMFNTAG42XDNA_SW_INT_H
|
||||
|
||||
/* Macros for LRP usage */
|
||||
#define PHAL_MFNTAG42XDNA_AUTHENTICATE_LRP_FIRST_RESP_LEN 17U /* 16 Bytes of Random number + 1 byte of Auth mode */
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_GetData(phalMfNtag42XDna_Sw_DataParams_t * pDataParams, uint8_t * pSendBuff, uint16_t wCmdLen,
|
||||
uint8_t ** pResponse, uint16_t * pRxlen);
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_ISOGetData(phalMfNtag42XDna_Sw_DataParams_t * pDataParams, uint8_t * pSendBuff, uint16_t wCmdLen,
|
||||
uint8_t ** pResponse, uint16_t * pRxlen);
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_ReadData_Plain(phalMfNtag42XDna_Sw_DataParams_t * pDataParams, uint8_t bOption, uint8_t * bCmdBuff,
|
||||
uint16_t wCmdLen, uint8_t ** ppRxdata, uint16_t * pRxdataLen);
|
||||
|
||||
#ifdef NXPBUILD__PH_CRYPTOSYM
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_ReadData_Enc(phalMfNtag42XDna_Sw_DataParams_t * UNALIGNED pDataParams, uint8_t bPaddingOption,
|
||||
uint8_t * bCmdBuff, uint16_t wCmdLen, uint8_t ** ppRxdata, uint16_t * pRxdataLen);
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_Write_Enc(phalMfNtag42XDna_Sw_DataParams_t * pDataParams, uint8_t bIns, uint8_t * bCmdBuff,
|
||||
uint16_t wCmdLen, uint8_t bPaddingMode, uint8_t bCommOption, uint8_t * pData, uint16_t wDataLen);
|
||||
#endif /* NXPBUILD__PH_CRYPTOSYM */
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_Write_Plain(phalMfNtag42XDna_Sw_DataParams_t * pDataParams, uint8_t bIns, uint8_t * bCmdBuff,
|
||||
uint16_t wCmdLen, uint8_t bCommOption, uint8_t * pData, uint16_t wDataLen);
|
||||
|
||||
void phalMfNtag42XDna_Sw_Int_ResetAuthStatus(phalMfNtag42XDna_Sw_DataParams_t * pDataParams);
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_SendDataToPICC(phalMfNtag42XDna_Sw_DataParams_t * pDataParams, uint8_t bIns, uint8_t bCommOption,
|
||||
uint8_t * pCmd, uint16_t wCmdLen, uint8_t * pData, uint16_t wDataLen, uint8_t * bLastChunk, uint16_t wLastChunkLen, uint8_t * pResp,
|
||||
uint16_t * pRespLen);
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_SendDataAndAddDataToPICC(phalMfNtag42XDna_Sw_DataParams_t * pDataParams, uint8_t bIns, uint8_t * pCmd,
|
||||
uint16_t wCmdLen, uint8_t * pData, uint16_t wDataLen, uint8_t * pAddData, uint16_t wAddDataLen, uint8_t * pResp, uint16_t * pRespLen);
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_IsoRead(phalMfNtag42XDna_Sw_DataParams_t * pDataParams, uint16_t wOption, uint8_t * bCmdBuff,
|
||||
uint16_t wCmdLen, uint8_t ** ppRxBuffer, uint32_t * pBytesRead);
|
||||
|
||||
void phalMfNtag42XDna_Sw_Int_TruncateMac(uint8_t * pMac);
|
||||
|
||||
#ifdef NXPBUILD__PH_CRYPTOSYM
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_ComputeIv(uint8_t bIsResponse, uint8_t * pTi, uint16_t wCmdCtr, uint8_t * pIv);
|
||||
#endif /* NXPBUILD__PH_CRYPTOSYM */
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_GetFrameLength(phalMfNtag42XDna_Sw_DataParams_t * pDataParams, uint16_t * pFSD, uint16_t * pFSC);
|
||||
|
||||
#ifdef NXPBUILD__PH_CRYPTOSYM
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_AuthenticateEv2(phalMfNtag42XDna_Sw_DataParams_t * pDataParams, uint8_t bAuthOption, uint16_t wOption,
|
||||
uint16_t wKeyNo, uint16_t wKeyVer, uint8_t bKeyNoCard, uint8_t * pDivInput, uint8_t bDivLen, uint8_t bLenPcdCapsIn, uint8_t *pPcdCapsIn,
|
||||
uint8_t *pPcdCapsOut, uint8_t *pPdCapsOut);
|
||||
|
||||
#endif /* NXPBUILD__PH_CRYPTOSYM */
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_ComputeSDMIV(phalMfNtag42XDna_Sw_DataParams_t *pDataParams, uint8_t *pSessEncKey, uint8_t *pSDMReadCtr,
|
||||
uint8_t *pIV);
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_DecryptSDMData(phalMfNtag42XDna_Sw_DataParams_t *pDataParams, uint8_t *pSessEncKey, uint8_t *pIv,
|
||||
uint8_t wIvSize, uint8_t *pInputOutputData, uint16_t wInputDataLen);
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Sw_Int_GenerateSDMSessionKeysAES(phalMfNtag42XDna_Sw_DataParams_t *pDataParams, uint8_t bSdmOption, uint16_t wKeyNo,
|
||||
uint16_t wKeyVer, uint8_t *pSDMReadCtr, uint8_t * pVCUID, uint8_t bUidLen, uint8_t *pSessEncKey, uint8_t *pSessMacKey);
|
||||
|
||||
#endif /* PHALMFNTAG42XDNA_SW_INT_H */
|
||||
@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
|
||||
* Copyright 2016-2017 NXP. Not a Contribution.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_I2C_CMSIS_H_
|
||||
#define _FSL_I2C_CMSIS_H_
|
||||
#include "fsl_common.h"
|
||||
#include "Driver_I2C.h"
|
||||
#include "RTE_Device.h"
|
||||
#include "fsl_i2c.h"
|
||||
#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
|
||||
#include "fsl_dmamux.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
|
||||
#include "fsl_i2c_dma.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
|
||||
#include "fsl_i2c_edma.h"
|
||||
#endif
|
||||
|
||||
#if defined(I2C0)
|
||||
extern ARM_DRIVER_I2C Driver_I2C0;
|
||||
#endif
|
||||
|
||||
#if defined(I2C1)
|
||||
extern ARM_DRIVER_I2C Driver_I2C1;
|
||||
#endif
|
||||
|
||||
#if defined(I2C2)
|
||||
extern ARM_DRIVER_I2C Driver_I2C2;
|
||||
#endif
|
||||
|
||||
#if defined(I2C3)
|
||||
extern ARM_DRIVER_I2C Driver_I2C3;
|
||||
#endif
|
||||
|
||||
/* I2C Driver state flags */
|
||||
#define I2C_FLAG_UNINIT (0)
|
||||
#define I2C_FLAG_INIT (1 << 0)
|
||||
#define I2C_FLAG_POWER (1 << 1)
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,20 @@
|
||||
|
||||
ADD_SUBDIRECTORY(NfcrdlibEx1_DiscoveryLoop)
|
||||
IF(NOT FRONTEND_RC663)
|
||||
ADD_SUBDIRECTORY(NfcrdlibEx3_NFCForum)
|
||||
ENDIF()
|
||||
ADD_SUBDIRECTORY(NfcrdlibEx4_MIFAREClassic)
|
||||
ADD_SUBDIRECTORY(NfcrdlibEx5_ISO15693)
|
||||
ADD_SUBDIRECTORY(NfcrdlibEx6_LPCD)
|
||||
IF(NOT FRONTEND_RC663)
|
||||
ADD_SUBDIRECTORY(NfcrdlibEx8_HCE_T4T)
|
||||
ENDIF()
|
||||
ADD_SUBDIRECTORY(NfcrdlibEx9_NTagI2C)
|
||||
IF(WITH_NDA)
|
||||
ADD_SUBDIRECTORY(NfcrdlibEx7_MIFAREPlus)
|
||||
ADD_SUBDIRECTORY(NfcrdlibEx10_MIFAREDESFire_EVx)
|
||||
ENDIF()
|
||||
ADD_SUBDIRECTORY(Nfcrdlib_SimplifiedAPI_ISO)
|
||||
IF(WITH_ECP)
|
||||
ADD_SUBDIRECTORY(NfcrdlibEx2_ECP)
|
||||
ENDIF()
|
||||
@ -0,0 +1,548 @@
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_MANAGER_H__
|
||||
#define __SERIAL_MANAGER_H__
|
||||
|
||||
/*!
|
||||
* @addtogroup serialmanager
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */
|
||||
#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
|
||||
#else
|
||||
#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
|
||||
#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_UART
|
||||
#define SERIAL_PORT_TYPE_UART (1U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_USBCDC
|
||||
#define SERIAL_PORT_TYPE_USBCDC (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_SWO
|
||||
#define SERIAL_PORT_TYPE_SWO (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_USBCDC_VIRTUAL
|
||||
#define SERIAL_PORT_TYPE_USBCDC_VIRTUAL (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Set serial manager write handle size */
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)
|
||||
#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)
|
||||
#else
|
||||
#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)
|
||||
#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
|
||||
#include "serial_port_uart.h"
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
|
||||
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#error The serial manager blocking mode cannot be supported for USB CDC.
|
||||
#endif
|
||||
|
||||
#include "serial_port_usb.h"
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
|
||||
#include "serial_port_swo.h"
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
|
||||
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#error The serial manager blocking mode cannot be supported for USB CDC.
|
||||
#endif
|
||||
|
||||
#include "serial_port_usb_virtual.h"
|
||||
#endif
|
||||
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U
|
||||
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
|
||||
|
||||
#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
|
||||
|
||||
#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
|
||||
|
||||
#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
|
||||
|
||||
#if (SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */
|
||||
#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))
|
||||
#else
|
||||
#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_USBCDC_VIRTUAL should not be cleared at same time.
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U)
|
||||
#else
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
|
||||
#endif
|
||||
|
||||
#define SERIAL_MANAGER_USE_COMMON_TASK (1U)
|
||||
#define SERIAL_MANAGER_TASK_PRIORITY (2U)
|
||||
#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)
|
||||
|
||||
typedef void *serial_handle_t;
|
||||
typedef void *serial_write_handle_t;
|
||||
typedef void *serial_read_handle_t;
|
||||
|
||||
/*! @brief serial port type*/
|
||||
typedef enum _serial_port_type
|
||||
{
|
||||
kSerialPort_Uart = 1U, /*!< Serial port UART */
|
||||
kSerialPort_UsbCdc, /*!< Serial port USB CDC */
|
||||
kSerialPort_Swo, /*!< Serial port SWO */
|
||||
kSerialPort_UsbCdcVirtual, /*!< Serial port USB CDC Virtual */
|
||||
} serial_port_type_t;
|
||||
|
||||
/*! @brief serial manager config structure*/
|
||||
typedef struct _serial_manager_config
|
||||
{
|
||||
uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware.
|
||||
Besides, the memory space cannot be free during the lifetime of the serial
|
||||
manager module. */
|
||||
uint32_t ringBufferSize; /*!< The size of the ring buffer */
|
||||
serial_port_type_t type; /*!< Serial port type */
|
||||
void *portConfig; /*!< Serial port configuration */
|
||||
} serial_manager_config_t;
|
||||
|
||||
/*! @brief serial manager error code*/
|
||||
typedef enum _serial_manager_status
|
||||
{
|
||||
kStatus_SerialManager_Success = kStatus_Success, /*!< Success */
|
||||
kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */
|
||||
kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */
|
||||
kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */
|
||||
kStatus_SerialManager_Canceled =
|
||||
MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */
|
||||
kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */
|
||||
kStatus_SerialManager_RingBufferOverflow =
|
||||
MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */
|
||||
} serial_manager_status_t;
|
||||
|
||||
/*! @brief Callback message structure */
|
||||
typedef struct _serial_manager_callback_message
|
||||
{
|
||||
uint8_t *buffer; /*!< Transferred buffer */
|
||||
uint32_t length; /*!< Transferred data length */
|
||||
} serial_manager_callback_message_t;
|
||||
|
||||
/*! @brief callback function */
|
||||
typedef void (*serial_manager_callback_t)(void *callbackParam,
|
||||
serial_manager_callback_message_t *message,
|
||||
serial_manager_status_t status);
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
/*!
|
||||
* @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.
|
||||
*
|
||||
* This function configures the Serial Manager module with user-defined settings. The user can configure the
|
||||
* configuration
|
||||
* structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE
|
||||
* allocated by the caller.
|
||||
* The Serial Manager module supports two types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc) and USB
|
||||
* CDC.
|
||||
* Please refer to #serial_port_type_t for serial port setting. These two types can be set by using
|
||||
* #serial_manager_config_t.
|
||||
*
|
||||
* Example below shows how to use this API to configure the Serial Manager.
|
||||
* For UART,
|
||||
* @code
|
||||
* #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
|
||||
* static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
|
||||
* static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];
|
||||
* static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
|
||||
*
|
||||
* serial_manager_config_t config;
|
||||
* serial_port_uart_config_t uartConfig;
|
||||
* config.type = kSerialPort_Uart;
|
||||
* config.ringBuffer = &s_ringBuffer[0];
|
||||
* config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
|
||||
* uartConfig.instance = 0;
|
||||
* uartConfig.clockRate = 24000000;
|
||||
* uartConfig.baudRate = 115200;
|
||||
* uartConfig.parityMode = kSerialManager_UartParityDisabled;
|
||||
* uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
|
||||
* uartConfig.enableRx = 1;
|
||||
* uartConfig.enableTx = 1;
|
||||
* config.portConfig = &uartConfig;
|
||||
* SerialManager_Init(s_serialHandle, &config);
|
||||
* @endcode
|
||||
* For USB CDC,
|
||||
* @code
|
||||
* #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
|
||||
* static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
|
||||
* static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];
|
||||
* static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
|
||||
*
|
||||
* serial_manager_config_t config;
|
||||
* serial_port_usb_cdc_config_t usbCdcConfig;
|
||||
* config.type = kSerialPort_UsbCdc;
|
||||
* config.ringBuffer = &s_ringBuffer[0];
|
||||
* config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
|
||||
* usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
|
||||
* config.portConfig = &usbCdcConfig;
|
||||
* SerialManager_Init(s_serialHandle, &config);
|
||||
* @endcode
|
||||
*
|
||||
* @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.
|
||||
* @param config Pointer to user-defined configuration structure.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
* @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief De-initializes the serial manager module instance.
|
||||
*
|
||||
* This function de-initializes the serial manager module instance. If the opened writing or
|
||||
* reading handle is not closed, the function will return kStatus_SerialManager_Busy.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.
|
||||
* @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);
|
||||
|
||||
/*!
|
||||
* @brief Opens a writing handle for the serial manager module.
|
||||
*
|
||||
* This function Opens a writing handle for the serial manager module. If the serial manager needs to
|
||||
* be used in different tasks, the task should open a dedicated write handle for itself by calling
|
||||
* #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing
|
||||
* handle at the same time, multiple writing handles need to be opened when the multiple transmission
|
||||
* is needed for a task.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* @param writeHandle The serial manager module writing handle pointer.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
* @retval kStatus_SerialManager_HandleConflict The writing handle was opened.
|
||||
* @retval kStatus_SerialManager_Success The writing handle is opened.
|
||||
*
|
||||
* Example below shows how to use this API to write data.
|
||||
* For task 1,
|
||||
* @code
|
||||
* static uint8_t s_serialWriteHandleBuffer1[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
|
||||
* static serial_write_handle_t s_serialWriteHandle1 = &s_serialWriteHandleBuffer1[0];
|
||||
* static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n";
|
||||
* SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1);
|
||||
* SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1);
|
||||
* SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1);
|
||||
* @endcode
|
||||
* For task 2,
|
||||
* @code
|
||||
* static uint8_t s_serialWriteHandleBuffer2[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
|
||||
* static serial_write_handle_t s_serialWriteHandle2 = &s_serialWriteHandleBuffer2[0];
|
||||
* static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n";
|
||||
* SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2);
|
||||
* SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2);
|
||||
* SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1);
|
||||
* @endcode
|
||||
*/
|
||||
serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);
|
||||
|
||||
/*!
|
||||
* @brief Closes a writing handle for the serial manager module.
|
||||
*
|
||||
* This function Closes a writing handle for the serial manager module.
|
||||
*
|
||||
* @param writeHandle The serial manager module writing handle pointer.
|
||||
* @retval kStatus_SerialManager_Success The writing handle is closed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);
|
||||
|
||||
/*!
|
||||
* @brief Opens a reading handle for the serial manager module.
|
||||
*
|
||||
* This function Opens a reading handle for the serial manager module. The reading handle can not be
|
||||
* opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when
|
||||
* the previous reading handle is not closed. And There can only be one buffer for receiving for the
|
||||
* reading handle at the same time.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* @param readHandle The serial manager module reading handle pointer.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
* @retval kStatus_SerialManager_Success The reading handle is opened.
|
||||
* @retval kStatus_SerialManager_Busy Previous reading handle is not closed.
|
||||
*
|
||||
* Example below shows how to use this API to read data.
|
||||
* @code
|
||||
* static uint8_t s_serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];
|
||||
* static serial_read_handle_t s_serialReadHandle = &s_serialReadHandleBuffer[0];
|
||||
* SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle);
|
||||
* static uint8_t s_nonBlockingBuffer[64];
|
||||
* SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle);
|
||||
* SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer));
|
||||
* @endcode
|
||||
*/
|
||||
serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);
|
||||
|
||||
/*!
|
||||
* @brief Closes a reading for the serial manager module.
|
||||
*
|
||||
* This function Closes a reading for the serial manager module.
|
||||
*
|
||||
* @param readHandle The serial manager module reading handle pointer.
|
||||
* @retval kStatus_SerialManager_Success The reading handle is closed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);
|
||||
|
||||
/*!
|
||||
* @brief Transmits data with the blocking mode.
|
||||
*
|
||||
* This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.
|
||||
* This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for transmission for the writing handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
|
||||
* cannot be used at the same time.
|
||||
* And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to write.
|
||||
* @param length Length of the data to write.
|
||||
* @retval kStatus_SerialManager_Success Successfully sent all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length);
|
||||
|
||||
/*!
|
||||
* @brief Reads data with the blocking mode.
|
||||
*
|
||||
* This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.
|
||||
* This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for receiving for the reading handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
|
||||
* cannot be used at the same time.
|
||||
* And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to store the received data.
|
||||
* @param length The length of the data to be received.
|
||||
* @retval kStatus_SerialManager_Success Successfully received all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
/*!
|
||||
* @brief Transmits data with the non-blocking mode.
|
||||
*
|
||||
* This is a non-blocking function, which returns directly without waiting for all data to be sent.
|
||||
* When all data is sent, the module notifies the upper layer through a TX callback function and passes
|
||||
* the status parameter @ref kStatus_SerialManager_Success.
|
||||
* This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for transmission for the writing handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
|
||||
* cannot be used at the same time. And, the TX callback is mandatory before the function could be used.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to write.
|
||||
* @param length Length of the data to write.
|
||||
* @retval kStatus_SerialManager_Success Successfully sent all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length);
|
||||
|
||||
/*!
|
||||
* @brief Reads data with the non-blocking mode.
|
||||
*
|
||||
* This is a non-blocking function, which returns directly without waiting for all data to be received.
|
||||
* When all data is received, the module driver notifies the upper layer
|
||||
* through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.
|
||||
* This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for receiving for the reading handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
|
||||
* cannot be used at the same time. And, the RX callback is mandatory before the function could be used.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to store the received data.
|
||||
* @param length The length of the data to be received.
|
||||
* @retval kStatus_SerialManager_Success Successfully received all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length);
|
||||
|
||||
/*!
|
||||
* @brief Tries to read data.
|
||||
*
|
||||
* The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be
|
||||
* copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.
|
||||
* After the data is copied, the actual data length is passed by the parameter length.
|
||||
* And There can only one buffer for receiving for the reading handle at the same time.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to store the received data.
|
||||
* @param length The length of the data to be received.
|
||||
* @param receivedLength Length received from the ring buffer directly.
|
||||
* @retval kStatus_SerialManager_Success Successfully received all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length,
|
||||
uint32_t *receivedLength);
|
||||
|
||||
/*!
|
||||
* @brief Cancels unfinished send transmission.
|
||||
*
|
||||
* The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer
|
||||
* through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
|
||||
*
|
||||
* @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of
|
||||
* the function #SerialManager_WriteBlocking.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Get successfully abort the sending.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);
|
||||
|
||||
/*!
|
||||
* @brief Cancels unfinished receive transmission.
|
||||
*
|
||||
* The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper
|
||||
* layer
|
||||
* through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
|
||||
*
|
||||
* @note The function #SerialManager_CancelReading cannot be used to abort the transmission of
|
||||
* the function #SerialManager_ReadBlocking.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Get successfully abort the receiving.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);
|
||||
|
||||
/*!
|
||||
* @brief Installs a TX callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the TX callback and callback parameter for the serial manager module.
|
||||
* When any status of TX transmission changed, the driver will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_SerialManager_Success Successfully install the callback.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Installs a RX callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the RX callback and callback parameter for the serial manager module.
|
||||
* When any status of RX transmission changed, the driver will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_SerialManager_Success Successfully install the callback.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Prepares to enter low power consumption.
|
||||
*
|
||||
* This function is used to prepare to enter low power consumption.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Successful operation.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);
|
||||
|
||||
/*!
|
||||
* @brief Restores from low power consumption.
|
||||
*
|
||||
* This function is used to restore from low power consumption.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Successful operation.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/*! @} */
|
||||
#endif /* __SERIAL_MANAGER_H__ */
|
||||
@ -0,0 +1,66 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.5.0
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SECURE_HEAP_H__
|
||||
#define __SECURE_HEAP_H__
|
||||
|
||||
/* Standard includes. */
|
||||
#include <stdlib.h>
|
||||
|
||||
/**
|
||||
* @brief Allocates memory from heap.
|
||||
*
|
||||
* @param[in] xWantedSize The size of the memory to be allocated.
|
||||
*
|
||||
* @return Pointer to the memory region if the allocation is successful, NULL
|
||||
* otherwise.
|
||||
*/
|
||||
void * pvPortMalloc( size_t xWantedSize );
|
||||
|
||||
/**
|
||||
* @brief Frees the previously allocated memory.
|
||||
*
|
||||
* @param[in] pv Pointer to the memory to be freed.
|
||||
*/
|
||||
void vPortFree( void * pv );
|
||||
|
||||
/**
|
||||
* @brief Get the free heap size.
|
||||
*
|
||||
* @return Free heap size.
|
||||
*/
|
||||
size_t xPortGetFreeHeapSize( void );
|
||||
|
||||
/**
|
||||
* @brief Get the minimum ever free heap size.
|
||||
*
|
||||
* @return Minimum ever free heap size.
|
||||
*/
|
||||
size_t xPortGetMinimumEverFreeHeapSize( void );
|
||||
|
||||
#endif /* __SECURE_HEAP_H__ */
|
||||
@ -0,0 +1,110 @@
|
||||
/*
|
||||
* @brief LPC17xx/40xx Cyclic Redundancy Check (CRC) Engine driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licenser disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Sets up the CRC engine with defaults based on the polynomial to be used */
|
||||
void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly)
|
||||
{
|
||||
switch (poly) {
|
||||
case CRC_POLY_CRC16:
|
||||
LPC_CRC->MODE = MODE_CFG_CRC16;
|
||||
LPC_CRC->SEED = CRC_SEED_CRC16;
|
||||
break;
|
||||
|
||||
case CRC_POLY_CRC32:
|
||||
LPC_CRC->MODE = MODE_CFG_CRC32;
|
||||
LPC_CRC->SEED = CRC_SEED_CRC32;
|
||||
break;
|
||||
|
||||
case CRC_POLY_CCITT:
|
||||
default:
|
||||
LPC_CRC->MODE = MODE_CFG_CCITT;
|
||||
LPC_CRC->SEED = CRC_SEED_CCITT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* configure CRC engine and compute CCITT checksum from 8-bit data */
|
||||
uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes)
|
||||
{
|
||||
Chip_CRC_UseDefaultConfig(CRC_POLY_CCITT);
|
||||
while (bytes > 0) {
|
||||
Chip_CRC_Write8(*data);
|
||||
data++;
|
||||
bytes--;
|
||||
}
|
||||
return Chip_CRC_Sum();
|
||||
}
|
||||
|
||||
/* Convenience function for computing a standard CRC16 checksum from 16-bit data block */
|
||||
uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords)
|
||||
{
|
||||
Chip_CRC_UseDefaultConfig(CRC_POLY_CRC16);
|
||||
while (hwords > 0) {
|
||||
Chip_CRC_Write16(*data);
|
||||
data++;
|
||||
hwords--;
|
||||
}
|
||||
return Chip_CRC_Sum();
|
||||
}
|
||||
|
||||
/* Convenience function for computing a standard CRC32 checksum from 32-bit data block */
|
||||
uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words)
|
||||
{
|
||||
Chip_CRC_UseDefaultConfig(CRC_POLY_CRC32);
|
||||
while (words > 0) {
|
||||
Chip_CRC_Write32(*data);
|
||||
data++;
|
||||
words--;
|
||||
}
|
||||
return Chip_CRC_Sum();
|
||||
}
|
||||
|
||||
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
|
||||
@ -0,0 +1,266 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2016-2024 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* NFC Library Top Level API of Reader Library Framework.
|
||||
* $Author: NXP $
|
||||
* $Revision: $ (v07.10.00)
|
||||
* $Date: $
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHNFCLIB_INITIALIZATION_H
|
||||
#define PHNFCLIB_INITIALIZATION_H
|
||||
|
||||
#include <ph_Status.h>
|
||||
|
||||
#ifdef NXPBUILD__PHNFCLIB
|
||||
|
||||
#include <phNfcLib.h>
|
||||
|
||||
typedef phStatus_t (*pphNfcLib_Config_Profile)(void);
|
||||
|
||||
#define PH_CHECK_NFCLIB_SUCCESS(status) {if ((status) != PH_ERR_SUCCESS) {return (PH_NFCLIB_STATUS_INVALID_PARAMETER);}}
|
||||
#define PH_CHECK_NFCLIB_SUCCESS_FCT(status,fct) {(status) = (fct); PH_CHECK_NFCLIB_SUCCESS(status);}
|
||||
|
||||
#define PH_NFCLIB_INT_TRANSMIT_OFF 0x00U
|
||||
#define PH_NFCLIB_INT_TRANSMIT_ON 0x01U
|
||||
#define PH_NFCLIB_INT_TRANSMIT_SUCCESS_CHAINING 0x02U
|
||||
|
||||
/* By default invalid authentication status */
|
||||
#define PH_NFCLIB_MFDF_NOT_AUTHENTICATED 0xFFU /**< No authentication. */
|
||||
|
||||
/**
|
||||
* \brief NFCLIB parameter structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t wId; /**< ID of this component, do not modify. */
|
||||
|
||||
void *pBal; /**< Holds BAL context */
|
||||
|
||||
#ifdef NXPBUILD__PHHAL_HW_RC663
|
||||
phhalHw_Rc663_DataParams_t sHal; /**< HAL component holder */
|
||||
#endif /* NXPBUILD__PHHAL_HW_RC663 */
|
||||
|
||||
#ifdef NXPBUILD__PHHAL_HW_PN5180
|
||||
phhalHw_Pn5180_DataParams_t sHal; /**< HAL component holder */
|
||||
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
|
||||
|
||||
#ifdef NXPBUILD__PHHAL_HW_PN5190
|
||||
phhalHw_Pn5190_DataParams_t sHal; /**< HAL component holder */
|
||||
#endif /* NXPBUILD__PHHAL_HW_PN5190 */
|
||||
|
||||
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
|
||||
phhalHw_PN7462AU_DataParams_t sHal; /**< HAL component holder */
|
||||
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
phKeyStore_Sw_DataParams_t sKeyStore; /**< SW Keystore component holder */
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
phKeyStore_Rc663_DataParams_t sKeyStore; /**< Rc663 HW Keystore component holder */
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
pphNfcLib_ErrCallbck pNfcLib_ErrCallbck; /**< Call back in case of error in activation(applicable for activation profile #PH_NFCLIB_ACTIVATION_PROFILE_EMVCO) */
|
||||
|
||||
/* PAL Data Parameter Structures */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
|
||||
phpalI14443p3a_Sw_DataParams_t spalI14443p3a; /* PAL ISO I14443-A component */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P3B_SW
|
||||
phpalI14443p3b_Sw_DataParams_t spalI14443p3b; /* PAL ISO I14443-B component */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P3B_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P4A_SW
|
||||
phpalI14443p4a_Sw_DataParams_t spalI14443p4a; /* PAL ISO I14443-4A component */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P4A_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P4_SW
|
||||
phpalI14443p4_Sw_DataParams_t spalI14443p4; /* PAL ISO I14443-4 component */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P4_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_SLI15693_SW
|
||||
phpalSli15693_Sw_DataParams_t spalSli15693; /* PAL ISO 15693 component */
|
||||
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
|
||||
phpalI18000p3m3_Sw_DataParams_t spalI18000p3m3; /* PAL ISO 18000p3m3 component */
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_FELICA_SW
|
||||
phpalFelica_Sw_DataParams_t spalFelica; /* PAL FeliCa component */
|
||||
#endif /* NXPBUILD__PHPAL_FELICA_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
|
||||
phpalI18092mPI_Sw_DataParams_t spalI18092mPI; /* PAL ISO 18092 Initiator component */
|
||||
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18092MT_SW
|
||||
phpalI18092mT_Sw_DataParams_t spalI18092mT; /* PAL ISO 18092 Target component */
|
||||
|
||||
pRtoxTimerCallback pRtoxCallback; /**< Holds the function pointer of RTOX callback */
|
||||
#endif /* NXPBUILD__PHPAL_I18092MT_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
|
||||
phpalI14443p4mC_Sw_DataParams_t spalI14443p4mC; /* PAL 14443-4mC Target component */
|
||||
|
||||
pWtxTimerCallback pWtxCallback; /**< Holds the function pointer of WTX callback */
|
||||
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_MIFARE_SW
|
||||
phpalMifare_Sw_DataParams_t spalMifare; /* PAL MIFARE product component */
|
||||
#endif /* NXPBUILD__PHPAL_MIFARE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_EPCUID_SW
|
||||
phpalEpcUid_Sw_DataParams_t spalEpcUid; /* Generic ICode EPC/UID Component */
|
||||
#endif /* NXPBUILD__PHPAL_EPCUID_SW */
|
||||
|
||||
/* AL Data Parameter Structures */
|
||||
#ifdef NXPBUILD__PHAL_I18000P3M3_SW
|
||||
phalI18000p3m3_Sw_DataParams_t salI18000p3m3; /* AL ISO 18000p3m3 component */
|
||||
#endif /* NXPBUILD__PHAL_I18000P3M3_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_FELICA_SW
|
||||
phalFelica_Sw_DataParams_t salFelica; /* AL FeliCa component */
|
||||
#endif /* NXPBUILD__PHAL_FELICA_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_ICODE_SW
|
||||
phalICode_Sw_DataParams_t salICode; /* ICode AL component */
|
||||
#endif /* NXPBUILD__PHAL_ICODE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_MFC_SW
|
||||
phalMfc_Sw_DataParams_t salMFC; /* AL MIFARE Classic contactless IC component */
|
||||
#endif /* NXPBUILD__PHAL_MFC_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_MFDF_SW
|
||||
phalMfdf_Sw_DataParams_t salMFDF; /* AL MIFARE DESFire contactless IC component */
|
||||
#endif /* NXPBUILD__PHAL_MFDF_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_MFDFEVX_SW
|
||||
phalMfdfEVx_Sw_DataParams_t salMFDFEVx; /* AL MIFARE DESFire Ev2 contactless IC component */
|
||||
#endif /* NXPBUILD__PHAL_MFDFEVX_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_MFDFLIGHT_SW
|
||||
phalMfdfLight_Sw_DataParams_t salMFDFLight; /* AL MIFARE DESFire Light contactless IC component */
|
||||
#endif /* NXPBUILD__PHAL_MFDFLIGHT_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_MFPEVX_SW
|
||||
phalMfpEVx_Sw_DataParams_t salMFPEVx; /* AL MIFARE Plus EV1 contactless IC product component */
|
||||
#endif /* NXPBUILD__PHAL_MFPEVX_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_MFUL_SW
|
||||
phalMful_Sw_DataParams_t salMFUL; /* AL MIFARE Ultralight contactless IC component */
|
||||
#endif /* NXPBUILD__PHAL_MFUL_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_MFNTAG42XDNA_SW
|
||||
phalMfNtag42XDna_Sw_DataParams_t salMFNtag42XDNA; /* AL NTAG 42x DNA component */
|
||||
#endif /* NXPBUILD__PHAL_MFNTAG42XDNA_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_T1T_SW
|
||||
phalT1T_Sw_DataParams_t salT1T; /* AL T1T component */
|
||||
#endif /* NXPBUILD__PHAL_T1T_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP_SW
|
||||
phalTop_Sw_DataParams_t salTop; /* Tag operations component */
|
||||
#endif /* NXPBUILD__PHAL_TOP_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAC_DISCLOOP_SW
|
||||
phacDiscLoop_Sw_DataParams_t sDiscLoop; /* Discovery loop component */
|
||||
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHCE_T4T_SW
|
||||
phceT4T_Sw_DataParams_t sceT4T; /* HCE component */
|
||||
#endif /* NXPBUILD__PHCE_T4T_SW */
|
||||
|
||||
#if defined(NXPBUILD__PHAL_MFDFEVX_SW) || defined(NXPBUILD__PHAL_MFPEVX_SW) || \
|
||||
defined(NXPBUILD__PHAL_MFNTAG42XDNA_SW) || defined(NXPBUILD__PHAL_MFDFLIGHT_SW)
|
||||
/* Crypto Data Parameter Structures */
|
||||
#ifdef NXPBUILD__PH_CRYPTOSYM_SW
|
||||
phCryptoSym_Sw_DataParams_t sCryptoSymEnc; /* Crypto Sym software component */
|
||||
phCryptoSym_Sw_DataParams_t sCryptoSymMac; /* Crypto Sym software component */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_MFPEVX_SW
|
||||
phCryptoSym_Sw_DataParams_t sCryptoSymDiversify; /* Crypto Sym Diversify software component */
|
||||
#endif /* NXPBUILD__PHAL_MFPEVX_SW */
|
||||
#endif /* NXPBUILD__PH_CRYPTOSYM_SW */
|
||||
|
||||
/* Crypto Data Parameter Structures */
|
||||
#else
|
||||
/* Crypto Data Parameter Structures */
|
||||
#ifdef NXPBUILD__PH_CRYPTOSYM_SW
|
||||
phCryptoSym_Sw_DataParams_t sCryptoSym; /* Crypto Sym software component */
|
||||
#endif /* NXPBUILD__PH_CRYPTOSYM_SW */
|
||||
|
||||
/* Crypto Data Parameter Structures */
|
||||
#endif /* defined(NXPBUILD__PHAL_MFDFEVX_SW) || defined(NXPBUILD__PHAL_MFPEVX_SW) ||
|
||||
defined(NXPBUILD__PHAL_MFNTAG42XDNA_SW) || defined(NXPBUILD__PHAL_MFDFLIGHT_SW) */
|
||||
|
||||
#ifdef NXPBUILD__PH_CRYPTORNG_SW
|
||||
phCryptoRng_Sw_DataParams_t sCryptoRng; /* Crypto Rng component */
|
||||
#endif /* NXPBUILD__PH_CRYPTORNG_SW */
|
||||
|
||||
} phNfcLib_DataParams_t;
|
||||
|
||||
/**
|
||||
* \brief NFC LIB StateMachine
|
||||
* \anchor NfcLib_StateMachine
|
||||
* Refer state machine for each mode defined above.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
eNfcLib_ResetState = 0,
|
||||
eNfcLib_InitializedState = 1,
|
||||
eNfcLib_ActivatedState = 2,
|
||||
eNfcLib_DeactOngoingState = 3,
|
||||
eNfcLib_LAST = 0x7F /* Where facilitated by compiler, promote to 8 bit number */
|
||||
} phNfcLib_StateMachine_t;
|
||||
|
||||
/**
|
||||
* \brief NFC LIB State
|
||||
* \anchor NfcLib_State
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
phNfcLib_StateMachine_t bNfcLibState; /* State of the NfcLib takes value from enum phNfcLib_StateMachine_t */
|
||||
uint8_t bProfileSelected; /* Tells about the selected profile takes value ISO, NFC, EMVCO */
|
||||
uint8_t bActivateBlocking; /* Tells the blocking #PH_ON or #PH_OFF feature of Activation */
|
||||
uint8_t bDeactBlocking; /* Tells the blocking #PH_ON or #PH_OFF feature of DeActivation */
|
||||
uint8_t bMergedSakPrio; /* Tells the priority to perform activation of the card in case Merged Sak is received */
|
||||
uint8_t bLPCDState; /* Tells the LPCD #PH_ON or #PH_OFF performance */
|
||||
uint8_t bTxState; /* Tells the TX state of nfclib, if 1 then only receive can be performed */
|
||||
uint16_t wConfiguredRFTech; /* Tells the configured RF Tech that was used for current activation cycle */
|
||||
#ifdef NXPBUILD__PHNFCLIB_PROFILES
|
||||
phNfcLib_PeerInfo_t * pPeerInfo;
|
||||
#endif /* NXPBUILD__PHNFCLIB_PROFILES */
|
||||
uint8_t *pRxBuffer; /* Pointer to the RX */
|
||||
uint16_t wRxLength; /* Stores the length of the received Data */
|
||||
uint16_t wRxDataPoin; /* Points to the starting address of the rx buffer to perform Chaining */
|
||||
uint8_t bHalBufferTx[PH_NXPNFCRDLIB_CONFIG_HAL_TX_BUFFSIZE]; /* HAL TX buffer. */
|
||||
uint8_t bHalBufferRx[PH_NXPNFCRDLIB_CONFIG_HAL_RX_BUFFSIZE]; /* HAL RX buffer. */
|
||||
uint8_t bWrappedMode; /* Tells about the MIFARE DESFire Wrapped Mode Status */
|
||||
uint8_t bAuthMode; /* Tells about the MIFARE DESFire Auth Mode */
|
||||
uint16_t wActivatedUIDLength; /* Length of the activated UID */
|
||||
uint8_t* pActivatedUid; /* Contains the pointer of the activated Uid */
|
||||
uint8_t bFsdi; /* Frame Size Device Integer value. Note: This Parameter is used only in EMVCo profile. */
|
||||
} phNfcLib_InternalState_t;
|
||||
|
||||
extern phNfcLib_DataParams_t gphNfcLib_Params;
|
||||
extern phNfcLib_InternalState_t gphNfcLib_State;
|
||||
|
||||
#endif /* NXPBUILD__PHNFCLIB */
|
||||
|
||||
#endif /* PHNFCLIB_INITIALIZATION_H */
|
||||
@ -0,0 +1,209 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
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|
||||
<externalSettings>
|
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<externalSetting>
|
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||||
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|
||||
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|
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|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
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|
||||
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|
||||
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|
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@ -0,0 +1,80 @@
|
||||
/*
|
||||
* @brief LPC17xx/40xx Motor Control PWM driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __MCPWM_17XX_40XX_H_
|
||||
#define __MCPWM_17XX_40XX_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup MCPWM_17XX_40XX CHIP: LPC17xx/40xx Motor Control PWM driver
|
||||
* @ingroup CHIP_17XX_40XX_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Motor Control PWM register block structure
|
||||
*/
|
||||
typedef struct { /*!< MCPWM Structure */
|
||||
__I uint32_t CON; /*!< PWM Control read address */
|
||||
__O uint32_t CON_SET; /*!< PWM Control set address */
|
||||
__O uint32_t CON_CLR; /*!< PWM Control clear address */
|
||||
__I uint32_t CAPCON; /*!< Capture Control read address */
|
||||
__O uint32_t CAPCON_SET; /*!< Capture Control set address */
|
||||
__O uint32_t CAPCON_CLR; /*!< Event Control clear address */
|
||||
__IO uint32_t TC[3]; /*!< Timer Counter register */
|
||||
__IO uint32_t LIM[3]; /*!< Limit register */
|
||||
__IO uint32_t MAT[3]; /*!< Match register */
|
||||
__IO uint32_t DT; /*!< Dead time register */
|
||||
__IO uint32_t CCP; /*!< Communication Pattern register */
|
||||
__I uint32_t CAP[3]; /*!< Capture register */
|
||||
__I uint32_t INTEN; /*!< Interrupt Enable read address */
|
||||
__O uint32_t INTEN_SET; /*!< Interrupt Enable set address */
|
||||
__O uint32_t INTEN_CLR; /*!< Interrupt Enable clear address */
|
||||
__I uint32_t CNTCON; /*!< Count Control read address */
|
||||
__O uint32_t CNTCON_SET; /*!< Count Control set address */
|
||||
__O uint32_t CNTCON_CLR; /*!< Count Control clear address */
|
||||
__I uint32_t INTF; /*!< Interrupt flags read address */
|
||||
__O uint32_t INTF_SET; /*!< Interrupt flags set address */
|
||||
__O uint32_t INTF_CLR; /*!< Interrupt flags clear address */
|
||||
__O uint32_t CAP_CLR; /*!< Capture clear address */
|
||||
} LPC_MCPWM_T;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MCPWM_17XX_40XX_H_ */
|
||||
@ -0,0 +1 @@
|
||||
***** IMPORTANT : Please unzip API Guide compressed folder and double click on index.html to view API Guide documentation. *****
|
||||
@ -0,0 +1,262 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_SAI_EDMA_H_
|
||||
#define _FSL_SAI_EDMA_H_
|
||||
|
||||
#include "fsl_edma.h"
|
||||
#include "fsl_sai.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup sai_edma
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*!< Version 2.2.0 */
|
||||
/*@}*/
|
||||
|
||||
typedef struct _sai_edma_handle sai_edma_handle_t;
|
||||
|
||||
/*! @brief SAI eDMA transfer callback function for finish and error */
|
||||
typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData);
|
||||
|
||||
/*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/
|
||||
struct _sai_edma_handle
|
||||
{
|
||||
edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */
|
||||
uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
|
||||
uint8_t bytesPerFrame; /*!< Bytes in a frame */
|
||||
uint8_t channel; /*!< Which data channel */
|
||||
uint8_t count; /*!< The transfer data count in a DMA request */
|
||||
uint32_t state; /*!< Internal state for SAI eDMA transfer */
|
||||
sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */
|
||||
void *userData; /*!< User callback parameter */
|
||||
uint8_t tcd[(SAI_XFER_QUEUE_SIZE + 1U) * sizeof(edma_tcd_t)]; /*!< TCD pool for eDMA transfer. */
|
||||
sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */
|
||||
size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */
|
||||
volatile uint8_t queueUser; /*!< Index for user to queue transfer. */
|
||||
volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* APIs
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name eDMA Transactional
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the SAI eDMA handle.
|
||||
*
|
||||
* This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs.
|
||||
* Usually, for a specified SAI instance, call this API once to get the initialized handle.
|
||||
*
|
||||
* @param base SAI base pointer.
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
* @param base SAI peripheral base address.
|
||||
* @param callback Pointer to user callback function.
|
||||
* @param userData User parameter passed to the callback function.
|
||||
* @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users.
|
||||
*/
|
||||
void SAI_TransferTxCreateHandleEDMA(
|
||||
I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle);
|
||||
|
||||
/*!
|
||||
* @brief Initializes the SAI Rx eDMA handle.
|
||||
*
|
||||
* This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs.
|
||||
* Usually, for a specified SAI instance, call this API once to get the initialized handle.
|
||||
*
|
||||
* @param base SAI base pointer.
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
* @param base SAI peripheral base address.
|
||||
* @param callback Pointer to user callback function.
|
||||
* @param userData User parameter passed to the callback function.
|
||||
* @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users.
|
||||
*/
|
||||
void SAI_TransferRxCreateHandleEDMA(
|
||||
I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle);
|
||||
|
||||
/*!
|
||||
* @brief Configures the SAI Tx audio format.
|
||||
*
|
||||
* The audio format can be changed at run-time. This function configures the sample rate and audio data
|
||||
* format to be transferred. This function also sets the eDMA parameter according to formatting requirements.
|
||||
*
|
||||
* @param base SAI base pointer.
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
* @param format Pointer to SAI audio data format structure.
|
||||
* @param mclkSourceClockHz SAI master clock source frequency in Hz.
|
||||
* @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master
|
||||
* clock, this value should equals to masterClockHz in format.
|
||||
* @retval kStatus_Success Audio format set successfully.
|
||||
* @retval kStatus_InvalidArgument The input argument is invalid.
|
||||
*/
|
||||
void SAI_TransferTxSetFormatEDMA(I2S_Type *base,
|
||||
sai_edma_handle_t *handle,
|
||||
sai_transfer_format_t *format,
|
||||
uint32_t mclkSourceClockHz,
|
||||
uint32_t bclkSourceClockHz);
|
||||
|
||||
/*!
|
||||
* @brief Configures the SAI Rx audio format.
|
||||
*
|
||||
* The audio format can be changed at run-time. This function configures the sample rate and audio data
|
||||
* format to be transferred. This function also sets the eDMA parameter according to formatting requirements.
|
||||
*
|
||||
* @param base SAI base pointer.
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
* @param format Pointer to SAI audio data format structure.
|
||||
* @param mclkSourceClockHz SAI master clock source frequency in Hz.
|
||||
* @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master
|
||||
* clock, this value should equal to masterClockHz in format.
|
||||
* @retval kStatus_Success Audio format set successfully.
|
||||
* @retval kStatus_InvalidArgument The input argument is invalid.
|
||||
*/
|
||||
void SAI_TransferRxSetFormatEDMA(I2S_Type *base,
|
||||
sai_edma_handle_t *handle,
|
||||
sai_transfer_format_t *format,
|
||||
uint32_t mclkSourceClockHz,
|
||||
uint32_t bclkSourceClockHz);
|
||||
|
||||
/*!
|
||||
* @brief Configures the SAI Tx.
|
||||
*
|
||||
*
|
||||
* @param base SAI base pointer.
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
* @param saiConfig sai configurations.
|
||||
*/
|
||||
void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig);
|
||||
|
||||
/*!
|
||||
* @brief Configures the SAI Rx.
|
||||
*
|
||||
*
|
||||
* @param base SAI base pointer.
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
* @param saiConfig sai configurations.
|
||||
*/
|
||||
void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig);
|
||||
|
||||
/*!
|
||||
* @brief Performs a non-blocking SAI transfer using DMA.
|
||||
*
|
||||
* @note This interface returns immediately after the transfer initiates. Call
|
||||
* SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished.
|
||||
*
|
||||
* @param base SAI base pointer.
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
* @param xfer Pointer to the DMA transfer structure.
|
||||
* @retval kStatus_Success Start a SAI eDMA send successfully.
|
||||
* @retval kStatus_InvalidArgument The input argument is invalid.
|
||||
* @retval kStatus_TxBusy SAI is busy sending data.
|
||||
*/
|
||||
status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Performs a non-blocking SAI receive using eDMA.
|
||||
*
|
||||
* @note This interface returns immediately after the transfer initiates. Call
|
||||
* the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished.
|
||||
*
|
||||
* @param base SAI base pointer
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
* @param xfer Pointer to DMA transfer structure.
|
||||
* @retval kStatus_Success Start a SAI eDMA receive successfully.
|
||||
* @retval kStatus_InvalidArgument The input argument is invalid.
|
||||
* @retval kStatus_RxBusy SAI is busy receiving data.
|
||||
*/
|
||||
status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Terminate all SAI send.
|
||||
*
|
||||
* This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
|
||||
* current transfer slot, please call SAI_TransferAbortSendEDMA.
|
||||
*
|
||||
* @param base SAI base pointer.
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
*/
|
||||
void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Terminate all SAI receive.
|
||||
*
|
||||
* This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
|
||||
* current transfer slot, please call SAI_TransferAbortReceiveEDMA.
|
||||
*
|
||||
* @param base SAI base pointer.
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
*/
|
||||
void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts a SAI transfer using eDMA.
|
||||
*
|
||||
* This function only aborts the current transfer slots, the other transfer slots' information still kept
|
||||
* in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA.
|
||||
*
|
||||
* @param base SAI base pointer.
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
*/
|
||||
void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts a SAI receive using eDMA.
|
||||
*
|
||||
* This function only aborts the current transfer slots, the other transfer slots' information still kept
|
||||
* in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA.
|
||||
*
|
||||
* @param base SAI base pointer
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
*/
|
||||
void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Gets byte count sent by SAI.
|
||||
*
|
||||
* @param base SAI base pointer.
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
* @param count Bytes count sent by SAI.
|
||||
* @retval kStatus_Success Succeed get the transfer count.
|
||||
* @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress.
|
||||
*/
|
||||
status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count);
|
||||
|
||||
/*!
|
||||
* @brief Gets byte count received by SAI.
|
||||
*
|
||||
* @param base SAI base pointer
|
||||
* @param handle SAI eDMA handle pointer.
|
||||
* @param count Bytes count received by SAI.
|
||||
* @retval kStatus_Success Succeed get the transfer count.
|
||||
* @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress.
|
||||
*/
|
||||
status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count);
|
||||
|
||||
/*! @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_dmamux.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.dmamux"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief Get instance number for DMAMUX.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
*/
|
||||
static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Array to map DMAMUX instance number to base pointer. */
|
||||
static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Array to map DMAMUX instance number to clock name. */
|
||||
static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++)
|
||||
{
|
||||
if (s_dmamuxBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_dmamuxBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Initializes the DMAMUX peripheral.
|
||||
*
|
||||
* This function ungates the DMAMUX clock.
|
||||
*
|
||||
* param base DMAMUX peripheral base address.
|
||||
*
|
||||
*/
|
||||
void DMAMUX_Init(DMAMUX_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Deinitializes the DMAMUX peripheral.
|
||||
*
|
||||
* This function gates the DMAMUX clock.
|
||||
*
|
||||
* param base DMAMUX peripheral base address.
|
||||
*/
|
||||
void DMAMUX_Deinit(DMAMUX_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
@ -0,0 +1,288 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors Gratkorn / Austria
|
||||
*
|
||||
* (C)NXP Semiconductors
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
*particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Generic ICode EPC/UID Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* CHu: Generated 8. September 2009
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHPALEPCUID_H
|
||||
#define PHPALEPCUID_H
|
||||
|
||||
#include <ph_Status.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_EPCUID
|
||||
|
||||
/** \defgroup phpalEpcUid ICODE EPC, ICODE UID
|
||||
* \brief These Components implement the ICode EPC and ICode UID products.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PHPAL_EPCUID_LABEL_EPC 0x00U /**< EPC label identifier */
|
||||
#define PHPAL_EPCUID_LABEL_UID 0x01U /**< UID label identifier */
|
||||
|
||||
#define PHPAL_EPCUID_EPC_MAXBLOCKNUMBER 16U /**< Last EPC block number. */
|
||||
#define PHPAL_EPCUID_UID_MAXBLOCKNUMBER 23U /**< Last UID block number. */
|
||||
|
||||
#define PHPAL_EPCUID_EPC_LENGTH 12U /**< EPC length in bytes without CRC. */
|
||||
#define PHPAL_EPCUID_IDD_LENGTH 19U /**< IDD length in bytes without UID-CRC. */
|
||||
|
||||
#define PHPAL_EPCUID_DESTROYCODE_LENGTH 3U /**< Length of the destroy code. */
|
||||
|
||||
#define PHPAL_EPCUID_CLOSESLOT_NONLAST 0x00U /**< Send a non last close slot and wait for tag replies afterwards. */
|
||||
#define PHPAL_EPCUID_CLOSESLOT_LAST 0x01U /**< Send the last close slot of a reply round, no data is received afterwards. */
|
||||
|
||||
#define PHPAL_EPCUID_NUMSLOTS_1 0x00U /**< Value for \c bNumSlots = 1. */
|
||||
#define PHPAL_EPCUID_NUMSLOTS_4 0x01U /**< Value for \c bNumSlots = 4. */
|
||||
#define PHPAL_EPCUID_NUMSLOTS_8 0x03U /**< Value for \c bNumSlots = 8. */
|
||||
#define PHPAL_EPCUID_NUMSLOTS_16 0x07U /**< Value for \c bNumSlots = 16. */
|
||||
#define PHPAL_EPCUID_NUMSLOTS_32 0x0FU /**< Value for \c bNumSlots = 32. */
|
||||
#define PHPAL_EPCUID_NUMSLOTS_64 0x1FU /**< Value for \c bNumSlots = 64. */
|
||||
#define PHPAL_EPCUID_NUMSLOTS_128 0x3FU /**< Value for \c bNumSlots = 128. */
|
||||
#define PHPAL_EPCUID_NUMSLOTS_256 0x7FU /**< Value for \c bNumSlots = 256. */
|
||||
#define PHPAL_EPCUID_NUMSLOTS_512 0xFFU /**< Value for \c bNumSlots = 512. */
|
||||
|
||||
/** @} */
|
||||
#endif /* NXPBUILD__PHPAL_EPCUID */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_EPCUID_SW
|
||||
|
||||
/** \defgroup phpalEpcUid_Sw Component : Software
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PHPAL_EPCUID_SW_ID 0x01U /**< ID for Software EPCUID layer */
|
||||
|
||||
/**
|
||||
* \brief Software PAL-EPCUID parameter structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t wId; /**< Layer ID for this component, NEVER MODIFY! */
|
||||
void * pHalDataParams; /**< Pointer to the parameter structure of the underlying HAL layer. */
|
||||
uint8_t bUidValid; /**< Whether current UID is valid or not. */
|
||||
uint8_t bLabelType; /**< Type of selected label. */
|
||||
uint8_t bMaskBitLength; /**< Number of masked bits already written into \c bEpc/bIdd. */
|
||||
union
|
||||
{
|
||||
uint8_t bEpc[PHPAL_EPCUID_EPC_LENGTH]; /**< 12 bytes EPC. */
|
||||
uint8_t bIdd[PHPAL_EPCUID_IDD_LENGTH]; /**< 12 bytes user data (UD) + 2 bytes UD-CRC + 5 bytes UID. */
|
||||
} LabelInfo;
|
||||
} phpalEpcUid_Sw_DataParams_t;
|
||||
|
||||
/**
|
||||
* \brief Initialise this layer.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
*/
|
||||
phStatus_t phpalEpcUid_Sw_Init(
|
||||
phpalEpcUid_Sw_DataParams_t * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wSizeOfDataParams, /**< [In] Specifies the size of the data parameter structure. */
|
||||
void * pHalDataParams /**< [In] Pointer to the parameter structure of the underlying HAL layer. */
|
||||
);
|
||||
|
||||
/** @} */
|
||||
#endif /* NXPBUILD__PHPAL_EPCUID_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_EPCUID
|
||||
|
||||
#ifdef NXPRDLIB_REM_GEN_INTFS
|
||||
#include "../comps/phpalEpcUid/src/Sw/phpalEpcUid_Sw.h"
|
||||
|
||||
#define phpalEpcUid_ActivateCard( pDataParams, bTagType, bNumSlots, pMask, bMaskLength, bHash, pRxBuffer, pRxLength, pMoreCardsAvailable) \
|
||||
phpalEpcUid_Sw_ActivateCard((phpalEpcUid_Sw_DataParams_t *)pDataParams, bTagType, bNumSlots, pMask, bMaskLength, bHash, pRxBuffer, pRxLength, pMoreCardsAvailable)
|
||||
|
||||
#define phpalEpcUid_BeginRound( pDataParams, bTagType, bNumSlots, pMask,bMaskLength, bHash, pRxBuffer, pRxLength) \
|
||||
phpalEpcUid_Sw_BeginRound((phpalEpcUid_Sw_DataParams_t *)pDataParams, bTagType, bNumSlots, pMask,bMaskLength, bHash, pRxBuffer, pRxLength) \
|
||||
|
||||
#define phpalEpcUid_CloseSlot( pDataParams, bOption, pRxBuffer, pRxLength) \
|
||||
phpalEpcUid_Sw_CloseSlot((phpalEpcUid_Sw_DataParams_t *)pDataParams, bOption, pRxBuffer, pRxLength)
|
||||
|
||||
#define phpalEpcUid_FixSlot( pDataParams, bTagType, pMask, bMaskLength) \
|
||||
phpalEpcUid_Sw_FixSlot((phpalEpcUid_Sw_DataParams_t *) pDataParams, bTagType, pMask, bMaskLength)
|
||||
|
||||
#define phpalEpcUid_Write( pDataParams, bTagType, bBlockNo, bData) \
|
||||
phpalEpcUid_Sw_Write( (phpalEpcUid_Sw_DataParams_t *)pDataParams, bTagType, bBlockNo, bData)
|
||||
|
||||
#define phpalEpcUid_Destroy( pDataParams, bTagType,pData, bDataLength, pDestroyCode) \
|
||||
phpalEpcUid_Sw_Destroy((phpalEpcUid_Sw_DataParams_t *) pDataParams, bTagType,pData, bDataLength, pDestroyCode)
|
||||
|
||||
#define phpalEpcUid_GetSerialNo( pDataParams, pRxBuffer, pRxLength) \
|
||||
phpalEpcUid_Sw_GetSerialNo((phpalEpcUid_Sw_DataParams_t *) pDataParams, pRxBuffer, pRxLength)
|
||||
|
||||
#else
|
||||
|
||||
/** \addtogroup phpalEpcUid
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Perform BeginRound command and bring first label to FIXED SLOT state.
|
||||
*
|
||||
* This command performs a \ref phpalEpcUid_BeginRound command and
|
||||
* iterates through the given number of slots using the \ref phpalEpcUid_CloseSlot
|
||||
* command until it receives the first correct response.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlaying component.
|
||||
*/
|
||||
phStatus_t phpalEpcUid_ActivateCard(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bTagType, /**< [In] Tag type; Either #PHPAL_EPCUID_LABEL_EPC or #PHPAL_EPCUID_LABEL_UID. */
|
||||
uint8_t bNumSlots, /**< [In] Number of slots. */
|
||||
uint8_t * pMask, /**< [In] Fractional or complete EPC/IDD for selecting certain labels. */
|
||||
uint8_t bMaskBitLength, /**< [In] Length of the mask in bits. */
|
||||
uint8_t bHash, /**< [In] Used by EPC labels to generate random slot position. */
|
||||
uint8_t * pRxBuffer, /**< [Out] Data returned by the tag which was detected first. */
|
||||
uint8_t * pRxLength, /**< [Out] Received data length. */
|
||||
uint8_t * pMoreCardsAvailable /**< [Out] Indicates if more than one tag was detected */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform BeginRound command.
|
||||
*
|
||||
* This command sends a BeginRound command to all labels and
|
||||
* stores the response of each label into a seperate
|
||||
* pLabelInfo Array.
|
||||
* Since the round starts with SlotF and not Slot0, the caller has to ensure
|
||||
* that the number of entries within \c pLabelInfo is \c 1+bNumSlots.
|
||||
* For each slot, a "Close Slot" Sequence is performed.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlaying component.
|
||||
*/
|
||||
phStatus_t phpalEpcUid_BeginRound(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bTagType, /**< [In] Tag type; Either #PHPAL_EPCUID_LABEL_EPC or #PHPAL_EPCUID_LABEL_UID. */
|
||||
uint8_t bNumSlots, /**< [In] Number of slots. */
|
||||
uint8_t * pMask, /**< [In] Fractional or complete EPC/IDD for selecting certain labels. */
|
||||
uint8_t bMaskBitLength, /**< [In] Length of the mask in bits. */
|
||||
uint8_t bHash, /**< [In] Used by EPC labels to generate random slot position. */
|
||||
uint8_t * pRxBuffer, /**< [Out] Data returned by the tag which was detected first. */
|
||||
uint8_t * pRxLength /**< [Out] Received data length. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform CloseSlot command.
|
||||
*
|
||||
* This command closes the actual slot and returnes the answer of all labels
|
||||
* replying in the next slot. If \c bOption is set to #PHPAL_EPCUID_CLOSESLOT_LAST
|
||||
* the reply round is closed and no more data is received.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlaying component.
|
||||
*/
|
||||
phStatus_t phpalEpcUid_CloseSlot(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bOption, /**< [In] Option; Either #PHPAL_EPCUID_CLOSESLOT_NONLAST or #PHPAL_EPCUID_CLOSESLOT_LAST. */
|
||||
uint8_t * pRxBuffer, /**< [Out] Data returned by the tag which answers during the next slot. */
|
||||
uint8_t * pRxLength /**< [Out] Received data length. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Perform FixSlot command.
|
||||
*
|
||||
* This command sets a lables matching to the given mask into the FIXED state.
|
||||
* A begin round with a single slot is started and the responding label is fixed by a
|
||||
* following FixSlot command.
|
||||
* <em><strong>Remark:</strong> This command is coupled with \ref phpalEpcUid_BeginRound to ensure the
|
||||
* exact timing 302,04us (using TxWait) between the two commands.</em>
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlaying component.
|
||||
*/
|
||||
phStatus_t phpalEpcUid_FixSlot(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bTagType, /**< [In] Tag type; Either #PHPAL_EPCUID_LABEL_EPC or #PHPAL_EPCUID_LABEL_UID. */
|
||||
uint8_t * pMask, /**< [In] Complete EPC/IDD for target label. */
|
||||
uint8_t bMaskBitLength /**< [In] Length of the mask in bits. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Write a block.
|
||||
*
|
||||
* There is no response from the label after sending this command.
|
||||
* In order to verify the written data, a
|
||||
* \ref phpalEpcUid_BeginRound command should be performed.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlaying component.
|
||||
*/
|
||||
phStatus_t phpalEpcUid_Write(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bTagType, /**< [In] Tag type; Either #PHPAL_EPCUID_LABEL_EPC or #PHPAL_EPCUID_LABEL_UID. */
|
||||
uint8_t bBlockNo, /**< [In] Destination block number. */
|
||||
uint8_t bData /**< [In] Data to write */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Destroy Label.
|
||||
*
|
||||
* There is no response from the label after sending this command.
|
||||
* In order to verify that the label is destroyed,
|
||||
* a \ref phpalEpcUid_BeginRound command should be performed.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlaying component.
|
||||
*/
|
||||
phStatus_t phpalEpcUid_Destroy(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t bTagType, /**< [In] Tag type; Either #PHPAL_EPCUID_LABEL_EPC or #PHPAL_EPCUID_LABEL_UID. */
|
||||
uint8_t * pData, /**< [In] Complete EPC/IDD data of the tag to be destroyed. */
|
||||
uint8_t bDataLength, /**< [In] Length of EPC/IDD data. */
|
||||
uint8_t * pDestroyCode /**< [In] 3 bytes destroy code. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Get the tag data.
|
||||
*
|
||||
* The command returnes the tag response to the last \ref phpalEpcUid_ActivateCard.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on implementation and underlaying component.
|
||||
*/
|
||||
phStatus_t phpalEpcUid_GetSerialNo(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t * pUidOut, /**< [Out] Tag response to the last \ref phpalEpcUid_ActivateCard. */
|
||||
uint8_t * pLenUidOut /**< [Out] Tag response length. */
|
||||
);
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* NXPRDLIB_REM_GEN_INTFS */
|
||||
|
||||
#endif /* NXPBUILD__PHPAL_EPCUID */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* Extern C */
|
||||
#endif
|
||||
|
||||
#endif /* PHPALEPCUID_H */
|
||||
@ -0,0 +1,179 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2020-2021,2023 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Example Source for NfcrdlibEx6_LPCD.
|
||||
* This application will configure Reader Library to provide demo on LPCD functionality of NXP Reader IC's.
|
||||
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
|
||||
* execute the project which is present in the same project directory.
|
||||
*
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*/
|
||||
|
||||
/**
|
||||
* Reader Library Headers
|
||||
*/
|
||||
#include <phApp_Init.h>
|
||||
#ifdef NXPBUILD__PHHAL_HW_PN5190
|
||||
#include <phhalHw_Pn5190_Instr.h>
|
||||
#endif /* NXPBUILD__PHHAL_HW_PN5190 */
|
||||
|
||||
/* Local headers */
|
||||
#include "NfcrdlibEx6_LPCD.h"
|
||||
|
||||
/*******************************************************************************
|
||||
** Definitions
|
||||
*******************************************************************************/
|
||||
|
||||
#ifdef NXPBUILD__PHHAL_HW_PN7640
|
||||
# warning "This example is not supported for PN7640"
|
||||
int main() {
|
||||
DEBUG_PRINTF("This example is not supported for PN7640.");
|
||||
while (1){
|
||||
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
/* Actual main defined below has no purpose in this example and hence over-riding it. */
|
||||
# define main dummy_main
|
||||
#endif /* NXPBUILD__PHHAL_HW_RC663 */
|
||||
|
||||
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
|
||||
uint32_t aLPCDTaskBuffer[LPCD_TASK_STACK];
|
||||
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
|
||||
#define aLPCDTaskBuffer NULL
|
||||
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
|
||||
|
||||
#ifdef PH_OSAL_FREERTOS
|
||||
const uint8_t bTaskName[configMAX_TASK_NAME_LEN] = {"LPCDTask"};
|
||||
#else
|
||||
const uint8_t bTaskName[] = {"LPCDTask"};
|
||||
#endif /* PH_OSAL_FREERTOS */
|
||||
|
||||
/*******************************************************************************
|
||||
** Static Defines
|
||||
*******************************************************************************/
|
||||
static volatile uint8_t bInfLoop = 1U;
|
||||
|
||||
/*******************************************************************************
|
||||
** Prototypes
|
||||
*******************************************************************************/
|
||||
|
||||
void LPCD_Demo(void * pHalParams);
|
||||
|
||||
/*******************************************************************************
|
||||
** Code
|
||||
*******************************************************************************/
|
||||
|
||||
int main (void)
|
||||
{
|
||||
do
|
||||
{
|
||||
phStatus_t wStatus = PH_ERR_INTERNAL_ERROR;
|
||||
phNfcLib_Status_t dwStatus;
|
||||
#ifdef PH_PLATFORM_HAS_ICFRONTEND
|
||||
phNfcLib_AppContext_t AppContext = {0};
|
||||
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
|
||||
|
||||
#ifndef PH_OSAL_NULLOS
|
||||
phOsal_ThreadObj_t LPCDTask;
|
||||
#endif /* PH_OSAL_NULLOS */
|
||||
|
||||
/* Perform Controller specific initialization. */
|
||||
phApp_CPU_Init();
|
||||
|
||||
/* Perform OSAL Initialization. */
|
||||
(void)phOsal_Init();
|
||||
|
||||
DEBUG_PRINTF("\n LPCD Example: ");
|
||||
|
||||
#ifdef PH_PLATFORM_HAS_ICFRONTEND
|
||||
wStatus = phbalReg_Init(&sBalParams, sizeof(phbalReg_Type_t));
|
||||
CHECK_STATUS(wStatus);
|
||||
|
||||
AppContext.pBalDataparams = &sBalParams;
|
||||
dwStatus = phNfcLib_SetContext(&AppContext);
|
||||
CHECK_NFCLIB_STATUS(dwStatus);
|
||||
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
|
||||
/* Initialize library */
|
||||
dwStatus = phNfcLib_Init();
|
||||
CHECK_NFCLIB_STATUS(dwStatus);
|
||||
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS) break;
|
||||
|
||||
/* Set the generic pointer */
|
||||
pHal = phNfcLib_GetDataParams(PH_COMP_HAL);
|
||||
|
||||
/* Perform Platform Init */
|
||||
wStatus = phApp_Configure_IRQ();
|
||||
CHECK_STATUS(wStatus);
|
||||
if(wStatus != PH_ERR_SUCCESS) break;
|
||||
|
||||
#ifndef PH_OSAL_NULLOS
|
||||
|
||||
LPCDTask.pTaskName = (uint8_t *)bTaskName;
|
||||
LPCDTask.pStackBuffer = aLPCDTaskBuffer;
|
||||
LPCDTask.priority = LPCD_TASK_PRIO;
|
||||
LPCDTask.stackSizeInNum = LPCD_TASK_STACK;
|
||||
phOsal_ThreadCreate(&LPCDTask.ThreadHandle, &LPCDTask, &LPCD_Demo, pHal);
|
||||
|
||||
phOsal_StartScheduler();
|
||||
|
||||
DEBUG_PRINTF("RTOS Error : Scheduler exited. \n");
|
||||
|
||||
#else
|
||||
LPCD_Demo(pHal);
|
||||
#endif /* PH_OSAL_NULLOS */
|
||||
} while(0);
|
||||
|
||||
while(bInfLoop); /* Comes here if initialization failure or scheduler exit due to error */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void LPCD_Demo(void * pHalParams)
|
||||
{
|
||||
phStatus_t wStatus;
|
||||
uint32_t dwLPCDCalibrateOption;
|
||||
uint32_t dwLPCDDemoOption;
|
||||
uint32_t dwLPCDRefValue;
|
||||
uint16_t wLPCDWakeUpTime = LPCD_POWERDOWN_TIME;
|
||||
|
||||
/* This call shall allocate secure context before calling any secure function,
|
||||
* when FreeRtos trust zone is enabled.
|
||||
* */
|
||||
phOsal_ThreadSecureStack( 512 );
|
||||
|
||||
/* Perform LPCD Calibration */
|
||||
wStatus = Configure_LPCD(&dwLPCDCalibrateOption, &dwLPCDDemoOption);
|
||||
CHECK_STATUS(wStatus);
|
||||
|
||||
/* Perform LPCD Calibration */
|
||||
wStatus = Calibrate_LPCD(dwLPCDDemoOption, &dwLPCDRefValue);
|
||||
CHECK_STATUS(wStatus);
|
||||
|
||||
do
|
||||
{
|
||||
/* Perform LPCD Call */
|
||||
wStatus = DemoLPCD(dwLPCDDemoOption, dwLPCDRefValue, wLPCDWakeUpTime);
|
||||
CHECK_STATUS(wStatus);
|
||||
|
||||
if (dwLPCDCalibrateOption == 1U)
|
||||
{
|
||||
/* Perform LPCD Calibration */
|
||||
wStatus = Calibrate_LPCD(dwLPCDDemoOption, &dwLPCDRefValue);
|
||||
CHECK_STATUS(wStatus);
|
||||
}
|
||||
}while(bInfLoop);
|
||||
}
|
||||
@ -0,0 +1,225 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.5.0
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
|
||||
* all the API functions to use the MPU wrappers. That should only be done when
|
||||
* task.h is included from an application file. */
|
||||
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
#include "list.h"
|
||||
|
||||
/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
|
||||
* because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
|
||||
* defined for the header files above, but not in this file, in order to
|
||||
* generate the correct privileged Vs unprivileged linkage and placement. */
|
||||
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* PUBLIC LIST API documented in list.h
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
void vListInitialise( List_t * const pxList )
|
||||
{
|
||||
/* The list structure contains a list item which is used to mark the
|
||||
* end of the list. To initialise the list the list end is inserted
|
||||
* as the only list entry. */
|
||||
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
||||
|
||||
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
|
||||
|
||||
/* The list end value is the highest possible value in the list to
|
||||
* ensure it remains at the end of the list. */
|
||||
pxList->xListEnd.xItemValue = portMAX_DELAY;
|
||||
|
||||
/* The list end next and previous pointers point to itself so we know
|
||||
* when the list is empty. */
|
||||
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
||||
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
||||
|
||||
/* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */
|
||||
#if ( configUSE_MINI_LIST_ITEM == 0 )
|
||||
{
|
||||
pxList->xListEnd.pvOwner = NULL;
|
||||
pxList->xListEnd.pxContainer = NULL;
|
||||
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
|
||||
}
|
||||
#endif
|
||||
|
||||
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
|
||||
|
||||
/* Write known values into the list if
|
||||
* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
|
||||
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vListInitialiseItem( ListItem_t * const pxItem )
|
||||
{
|
||||
/* Make sure the list item is not recorded as being on a list. */
|
||||
pxItem->pxContainer = NULL;
|
||||
|
||||
/* Write known values into the list item if
|
||||
* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
||||
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vListInsertEnd( List_t * const pxList,
|
||||
ListItem_t * const pxNewListItem )
|
||||
{
|
||||
ListItem_t * const pxIndex = pxList->pxIndex;
|
||||
|
||||
/* Only effective when configASSERT() is also defined, these tests may catch
|
||||
* the list data structures being overwritten in memory. They will not catch
|
||||
* data errors caused by incorrect configuration or use of FreeRTOS. */
|
||||
listTEST_LIST_INTEGRITY( pxList );
|
||||
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
|
||||
|
||||
/* Insert a new list item into pxList, but rather than sort the list,
|
||||
* makes the new list item the last item to be removed by a call to
|
||||
* listGET_OWNER_OF_NEXT_ENTRY(). */
|
||||
pxNewListItem->pxNext = pxIndex;
|
||||
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
|
||||
|
||||
/* Only used during decision coverage testing. */
|
||||
mtCOVERAGE_TEST_DELAY();
|
||||
|
||||
pxIndex->pxPrevious->pxNext = pxNewListItem;
|
||||
pxIndex->pxPrevious = pxNewListItem;
|
||||
|
||||
/* Remember which list the item is in. */
|
||||
pxNewListItem->pxContainer = pxList;
|
||||
|
||||
( pxList->uxNumberOfItems )++;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vListInsert( List_t * const pxList,
|
||||
ListItem_t * const pxNewListItem )
|
||||
{
|
||||
ListItem_t * pxIterator;
|
||||
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
|
||||
|
||||
/* Only effective when configASSERT() is also defined, these tests may catch
|
||||
* the list data structures being overwritten in memory. They will not catch
|
||||
* data errors caused by incorrect configuration or use of FreeRTOS. */
|
||||
listTEST_LIST_INTEGRITY( pxList );
|
||||
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
|
||||
|
||||
/* Insert the new list item into the list, sorted in xItemValue order.
|
||||
*
|
||||
* If the list already contains a list item with the same item value then the
|
||||
* new list item should be placed after it. This ensures that TCBs which are
|
||||
* stored in ready lists (all of which have the same xItemValue value) get a
|
||||
* share of the CPU. However, if the xItemValue is the same as the back marker
|
||||
* the iteration loop below will not end. Therefore the value is checked
|
||||
* first, and the algorithm slightly modified if necessary. */
|
||||
if( xValueOfInsertion == portMAX_DELAY )
|
||||
{
|
||||
pxIterator = pxList->xListEnd.pxPrevious;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* *** NOTE ***********************************************************
|
||||
* If you find your application is crashing here then likely causes are
|
||||
* listed below. In addition see https://www.FreeRTOS.org/FAQHelp.html for
|
||||
* more tips, and ensure configASSERT() is defined!
|
||||
* https://www.FreeRTOS.org/a00110.html#configASSERT
|
||||
*
|
||||
* 1) Stack overflow -
|
||||
* see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html
|
||||
* 2) Incorrect interrupt priority assignment, especially on Cortex-M
|
||||
* parts where numerically high priority values denote low actual
|
||||
* interrupt priorities, which can seem counter intuitive. See
|
||||
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition
|
||||
* of configMAX_SYSCALL_INTERRUPT_PRIORITY on
|
||||
* https://www.FreeRTOS.org/a00110.html
|
||||
* 3) Calling an API function from within a critical section or when
|
||||
* the scheduler is suspended, or calling an API function that does
|
||||
* not end in "FromISR" from an interrupt.
|
||||
* 4) Using a queue or semaphore before it has been initialised or
|
||||
* before the scheduler has been started (are interrupts firing
|
||||
* before vTaskStartScheduler() has been called?).
|
||||
* 5) If the FreeRTOS port supports interrupt nesting then ensure that
|
||||
* the priority of the tick interrupt is at or below
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
||||
**********************************************************************/
|
||||
|
||||
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
|
||||
{
|
||||
/* There is nothing to do here, just iterating to the wanted
|
||||
* insertion position. */
|
||||
}
|
||||
}
|
||||
|
||||
pxNewListItem->pxNext = pxIterator->pxNext;
|
||||
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
|
||||
pxNewListItem->pxPrevious = pxIterator;
|
||||
pxIterator->pxNext = pxNewListItem;
|
||||
|
||||
/* Remember which list the item is in. This allows fast removal of the
|
||||
* item later. */
|
||||
pxNewListItem->pxContainer = pxList;
|
||||
|
||||
( pxList->uxNumberOfItems )++;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
|
||||
{
|
||||
/* The list item knows which list it is in. Obtain the list from the list
|
||||
* item. */
|
||||
List_t * const pxList = pxItemToRemove->pxContainer;
|
||||
|
||||
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
|
||||
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
|
||||
|
||||
/* Only used during decision coverage testing. */
|
||||
mtCOVERAGE_TEST_DELAY();
|
||||
|
||||
/* Make sure the index is left pointing to a valid item. */
|
||||
if( pxList->pxIndex == pxItemToRemove )
|
||||
{
|
||||
pxList->pxIndex = pxItemToRemove->pxPrevious;
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
|
||||
pxItemToRemove->pxContainer = NULL;
|
||||
( pxList->uxNumberOfItems )--;
|
||||
|
||||
return pxList->uxNumberOfItems;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
@ -0,0 +1,472 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2016-2023 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Example Source for NfcrdlibEx9_NTagI2c that uses the NTag I2C implementation.
|
||||
* This example will load/configure Discovery loop for NTag I2C, uses POLL mode to detect the NTag I2C card.
|
||||
* Displays detected NTag I2C card information like UID, ATQA, SAK, Product, Version Info, Page Read and Write status.
|
||||
* Example will activate the device at index zero whenever multiple NTag I2C cards are detected.
|
||||
|
||||
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
|
||||
* execute the project which is present in the same project directory.
|
||||
* $Author: $
|
||||
* $Revision: $ (v07.10.00)
|
||||
* $Date: $
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* Reader Library Headers
|
||||
*/
|
||||
#include <phApp_Init.h>
|
||||
|
||||
/* Local headers */
|
||||
#include "NfcrdlibEx9_NTagI2C.h"
|
||||
|
||||
/*******************************************************************************
|
||||
** Definitions
|
||||
*******************************************************************************/
|
||||
|
||||
phacDiscLoop_Sw_DataParams_t * pDiscLoop; /* Pointer to Discovery loop data-params */
|
||||
phalMful_Sw_DataParams_t * palMful; /* Pointer to AL MFUL data-params */
|
||||
|
||||
uint8_t bDataBuffer[DATA_BUFFER_LEN]; /* universal data buffer */
|
||||
|
||||
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
|
||||
uint32_t aNTagI2CTaskBuffer[NTAGI2C_TASK_STACK];
|
||||
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
|
||||
#define aNTagI2CTaskBuffer NULL
|
||||
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
|
||||
|
||||
#ifdef PH_OSAL_FREERTOS
|
||||
const uint8_t bTaskName[configMAX_TASK_NAME_LEN] = {"NTagI2C"};
|
||||
#else
|
||||
const uint8_t bTaskName[] = {"NTagI2C"};
|
||||
#endif /* PH_OSAL_FREERTOS */
|
||||
|
||||
static volatile uint8_t bInfLoop = 1U;
|
||||
|
||||
/*******************************************************************************
|
||||
** Prototypes
|
||||
*******************************************************************************/
|
||||
|
||||
void NfcrdlibEx9_NTagI2C(void *pParams);
|
||||
phStatus_t phExample_Init(void);
|
||||
|
||||
/*******************************************************************************
|
||||
** Code
|
||||
*******************************************************************************/
|
||||
|
||||
int main(void)
|
||||
{
|
||||
do
|
||||
{
|
||||
phStatus_t status = PH_ERR_INTERNAL_ERROR;
|
||||
phNfcLib_Status_t dwStatus;
|
||||
#ifdef PH_PLATFORM_HAS_ICFRONTEND
|
||||
phNfcLib_AppContext_t AppContext = {0};
|
||||
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
|
||||
|
||||
#ifndef PH_OSAL_NULLOS
|
||||
phOsal_ThreadObj_t NTagI2C;
|
||||
#endif /* PH_OSAL_NULLOS */
|
||||
|
||||
/* Perform Controller specific initialization. */
|
||||
phApp_CPU_Init();
|
||||
|
||||
/* Perform OSAL Initialization. */
|
||||
(void)phOsal_Init();
|
||||
|
||||
/* Print Example application name */
|
||||
DEBUG_PRINTF("\n *** NTag I2C Example *** \n");
|
||||
|
||||
#ifdef PH_PLATFORM_HAS_ICFRONTEND
|
||||
status = phbalReg_Init(&sBalParams, sizeof(phbalReg_Type_t));
|
||||
CHECK_STATUS(status);
|
||||
|
||||
AppContext.pBalDataparams = &sBalParams;
|
||||
dwStatus = phNfcLib_SetContext(&AppContext);
|
||||
CHECK_NFCLIB_STATUS(dwStatus);
|
||||
#endif
|
||||
|
||||
/* Initialize library */
|
||||
dwStatus = phNfcLib_Init();
|
||||
CHECK_NFCLIB_STATUS(dwStatus);
|
||||
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS) break;
|
||||
|
||||
/* Set the generic pointer */
|
||||
pHal = phNfcLib_GetDataParams(PH_COMP_HAL);
|
||||
pDiscLoop = (phacDiscLoop_Sw_DataParams_t *) phNfcLib_GetDataParams(PH_COMP_AC_DISCLOOP);
|
||||
palMful = (phalMful_Sw_DataParams_t *) phNfcLib_GetDataParams(PH_COMP_AL_MFUL);
|
||||
|
||||
/* Configure the IRQ */
|
||||
status = phApp_Configure_IRQ();
|
||||
CHECK_STATUS(status);
|
||||
if(status != PH_ERR_SUCCESS) break;
|
||||
|
||||
#ifndef PH_OSAL_NULLOS
|
||||
|
||||
NTagI2C.pTaskName = (uint8_t *)bTaskName;
|
||||
NTagI2C.pStackBuffer = aNTagI2CTaskBuffer;
|
||||
NTagI2C.priority = NTAGI2C_TASK_PRIO;
|
||||
NTagI2C.stackSizeInNum = NTAGI2C_TASK_STACK;
|
||||
|
||||
phOsal_ThreadCreate(&NTagI2C.ThreadHandle, &NTagI2C, &NfcrdlibEx9_NTagI2C, pDiscLoop);
|
||||
|
||||
phOsal_StartScheduler();
|
||||
|
||||
/* Print Error info */
|
||||
DEBUG_PRINTF("RTOS Error : Scheduler exited. \n");
|
||||
|
||||
#else
|
||||
(void)NfcrdlibEx9_NTagI2C(pDiscLoop);
|
||||
#endif /* PH_OSAL_NULLOS */
|
||||
} while(0);
|
||||
|
||||
while(bInfLoop); /* Comes here if initialization failure or scheduler exit due to error */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***********************************************************************************************
|
||||
* \brief This function demonstrates the NTag I2C application as mentioned
|
||||
* Performs Type A Card detection and Activation and displays Tag UID, ATQA and SAK info.
|
||||
* Performs Read Tag Version info to confirm that the detected Tag is NTag I2C.
|
||||
* Performs Read Session Registers to check the Tag Mode. We can perform Sector/Page Read Write only in non pass-through mode.
|
||||
* Performs Read operation and Displays content of Sector 0 Pages 5 to 8 Data.
|
||||
* Performs Write operation i.e. writes back the sector 0 Pages 5 to 8 Data.
|
||||
* \param *pParams
|
||||
* \return This function will never return
|
||||
**********************************************************************************************/
|
||||
void NfcrdlibEx9_NTagI2C(void *pParams)
|
||||
{
|
||||
phStatus_t status = 0;
|
||||
uint16_t wTagsDetected = 0;
|
||||
uint8_t bTagType;
|
||||
uint8_t *pBuff;
|
||||
uint16_t numOfBytes;
|
||||
uint8_t bSectorNum;
|
||||
uint8_t bMoreCardsAvailable;
|
||||
|
||||
/* This call shall allocate secure context before calling any secure function,
|
||||
* when FreeRtos trust zone is enabled.
|
||||
* */
|
||||
phOsal_ThreadSecureStack( 512 );
|
||||
|
||||
/* Initialize library */
|
||||
status = phExample_Init();
|
||||
CHECK_STATUS(status);
|
||||
|
||||
while(bInfLoop) /* Continuous loop */
|
||||
{
|
||||
DEBUG_PRINTF("\nReady to detect");
|
||||
DEBUG_PRINTF("\n");
|
||||
|
||||
do
|
||||
{
|
||||
/* Field OFF */
|
||||
status = phhalHw_FieldOff(pHal);
|
||||
CHECK_STATUS(status);
|
||||
|
||||
status = phhalHw_Wait(pHal, PHHAL_HW_TIME_MICROSECONDS, 5100);
|
||||
CHECK_STATUS(status);
|
||||
|
||||
/* Configure Discovery loop for Poll Mode */
|
||||
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_NEXT_POLL_STATE, PHAC_DISCLOOP_POLL_STATE_DETECTION);
|
||||
CHECK_STATUS(status);
|
||||
|
||||
/* Run Discovery loop */
|
||||
status = phacDiscLoop_Run(pDiscLoop, PHAC_DISCLOOP_ENTRY_POINT_POLL);
|
||||
|
||||
}while((status & PH_ERR_MASK) != PHAC_DISCLOOP_DEVICE_ACTIVATED); /* Exit on Card detection */
|
||||
|
||||
/* Card detected */
|
||||
/* Get the tag types detected info */
|
||||
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TECH_DETECTED, &wTagsDetected);
|
||||
|
||||
/* Check for Status */
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
/* Check for Type A tag detection */
|
||||
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_A))
|
||||
{
|
||||
/* Bit b3 is set to zero, [Digital] 4.8.2 */
|
||||
/* Mask out all other bits except for b7 and b6 */
|
||||
bTagType = (pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aSak & 0x60);
|
||||
bTagType = bTagType >> 5;
|
||||
|
||||
/* Check for Type 2 Tag */
|
||||
if (bTagType == PHAC_DISCLOOP_TYPEA_TYPE2_TAG_CONFIG_MASK)
|
||||
{
|
||||
/* Check for NTAG I2C */
|
||||
if ((pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aAtqa[0] == 0x44)&&
|
||||
(pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aAtqa[1] == 0x00)&&
|
||||
(pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aSak == 0x00))
|
||||
{
|
||||
do
|
||||
{
|
||||
/* Print UID */
|
||||
DEBUG_PRINTF ("\nUID: ");
|
||||
phApp_Print_Buff(pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
|
||||
pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize);
|
||||
|
||||
/* Print ATQA and SAK */
|
||||
DEBUG_PRINTF("\nATQA:");
|
||||
phApp_Print_Buff(pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aAtqa, 2);
|
||||
DEBUG_PRINTF ("\nSAK: 0x%x",pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aSak);
|
||||
|
||||
/* Print Tag info */
|
||||
DEBUG_PRINTF ("\n\nType A T2-tag detected ");
|
||||
|
||||
/* Read Tag Version
|
||||
* Byte 0: Fixed Header(0x00)
|
||||
* Byte 1: Vendor ID(NXP Semiconductor: 0x04)
|
||||
* Byte 2: Product Type(NTag: 0x04)
|
||||
* Byte 6: Storage size(1k: 0x13 and 2k: 0x15)
|
||||
*/
|
||||
status = phalMful_GetVersion(palMful, &bDataBuffer[0]);
|
||||
|
||||
/* Check for Error */
|
||||
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
|
||||
{
|
||||
DEBUG_PRINTF ("\nUnable to Read Tag Version information");
|
||||
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* Check for Tag Info */
|
||||
if((bDataBuffer[0] == 0x00) && (bDataBuffer[1] == 0x04) && (bDataBuffer[2] == 0x04))
|
||||
{
|
||||
DEBUG_PRINTF ("\nProduct: NTag I2C ");
|
||||
if(bDataBuffer[6] == NTAG_I2C_1K_VERSION)
|
||||
{
|
||||
DEBUG_PRINTF ("1k Version ");
|
||||
}
|
||||
else if(bDataBuffer[6] == NTAG_I2C_2K_VERSION)
|
||||
{
|
||||
DEBUG_PRINTF ("2k Version ");
|
||||
}
|
||||
else
|
||||
{
|
||||
DEBUG_PRINTF ("\nInvalid Tag Version");
|
||||
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Read Tag Mode */
|
||||
/* Select Sector 3 to Read Session Registers */
|
||||
status = phalMful_SectorSelect(palMful, 3);
|
||||
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
|
||||
{
|
||||
DEBUG_PRINTF ("\nSector 3 selection Failed");
|
||||
DEBUG_PRINTF ("\nUnable to Read Tag Mode");
|
||||
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* Read Session registers */
|
||||
status = phalMful_Read(palMful, 0xF8, bDataBuffer);
|
||||
|
||||
/* check for Error */
|
||||
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
|
||||
{
|
||||
DEBUG_PRINTF ("\nSession Registers Read Failed");
|
||||
DEBUG_PRINTF ("\nUnable to Read Tag Mode");
|
||||
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* check for Pass-through mode */
|
||||
if ((bDataBuffer[0] & PTHRU_ON_OFF))
|
||||
{
|
||||
DEBUG_PRINTF ("\nTag is Configured in Pass-through Mode");
|
||||
DEBUG_PRINTF ("\nCan not perform Sector/Page Read Write Operation");
|
||||
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* --- Read Operation --- */
|
||||
/* Select Sector 0 */
|
||||
status = phalMful_SectorSelect(palMful, 0);
|
||||
|
||||
/* check for Success */
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
/* Read Sector 0 Page 5 to 8 Data */
|
||||
status = phalMful_FastRead(palMful, 5, 8, &pBuff, &numOfBytes);
|
||||
|
||||
/* check for Success */
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
DEBUG_PRINTF ("\n\nRead Success");
|
||||
|
||||
/* Copy Sector0 Page 5 to 6 Data */
|
||||
memcpy(bDataBuffer, pBuff, numOfBytes);
|
||||
|
||||
/* Display contents of Sector 0 Pages 5 to 6 Data */
|
||||
for (bSectorNum = 5; bSectorNum <= 8; bSectorNum++)
|
||||
{
|
||||
DEBUG_PRINTF ("\nSector 0 Page %d Data: ", bSectorNum);
|
||||
phApp_Print_Buff(&bDataBuffer[0 + ((bSectorNum - 5) * 4)], 4);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for Error */
|
||||
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
|
||||
{
|
||||
DEBUG_PRINTF ("\nRead Operation Failed!!!");
|
||||
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* End of Read Operation */
|
||||
DEBUG_PRINTF("\n\n --- End of Read Operation --- \n");
|
||||
|
||||
/* --- Write Operation --- */
|
||||
DEBUG_PRINTF("\nInitiation of Write operation to write back the Sector 0 Pages 5 to 8 Data \n");
|
||||
|
||||
/* Select Sector 0 */
|
||||
status = phalMful_SectorSelect(palMful, 0);
|
||||
|
||||
/* check for Success */
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
/* Write data to Sector 0 Page 5 to 8 */
|
||||
for (bSectorNum = 5; bSectorNum <= 8; bSectorNum++)
|
||||
{
|
||||
/* Page Write */
|
||||
status = phalMful_Write(palMful, bSectorNum, &bDataBuffer[0 + ((bSectorNum - 5) * 4)]);
|
||||
|
||||
/* Check for Success */
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
DEBUG_PRINTF("\nWrite Success: Sector 0 Page %d", bSectorNum);
|
||||
}
|
||||
else
|
||||
{
|
||||
DEBUG_PRINTF ("\nWrite Failed: Sector 0 Page %d ", bSectorNum);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for Error */
|
||||
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
|
||||
{
|
||||
DEBUG_PRINTF ("\nWrite Operation Failed!!! ");
|
||||
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* End of Write Operation */
|
||||
DEBUG_PRINTF("\n\n --- End of Write Operation --- \n");
|
||||
|
||||
/* End of example */
|
||||
DEBUG_PRINTF("\n\n --- End of Example --- \n\n");
|
||||
|
||||
DEBUG_PRINTF("\nPlease Remove the Card\n\n");
|
||||
|
||||
}while(0);
|
||||
|
||||
/* Field RESET */
|
||||
status = phhalHw_FieldReset(pHal);
|
||||
CHECK_STATUS(status);
|
||||
|
||||
/* Make sure that example application is not detecting the same card continuously */
|
||||
do
|
||||
{
|
||||
/* Activate Card */
|
||||
status = phpalI14443p3a_ActivateCard(
|
||||
pDiscLoop->pPal1443p3aDataParams,
|
||||
pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
|
||||
pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize,
|
||||
pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
|
||||
&pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize,
|
||||
&pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aSak,
|
||||
&bMoreCardsAvailable);
|
||||
|
||||
/* Check for Status */
|
||||
if (status != PH_ERR_SUCCESS)
|
||||
{
|
||||
break; /* Card Removed, break from the loop */
|
||||
}
|
||||
|
||||
/* Send HaltA */
|
||||
phpalI14443p3a_HaltA(pDiscLoop->pPal1443p3aDataParams);
|
||||
|
||||
/* Delay - 5 milli seconds*/
|
||||
status = phhalHw_Wait(pHal, PHHAL_HW_TIME_MILLISECONDS, 5);
|
||||
CHECK_STATUS(status);
|
||||
|
||||
}while(bInfLoop);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/***********************************************************************************************
|
||||
* \brief Application initialization
|
||||
* \param none
|
||||
* \return status Returns the function status
|
||||
**********************************************************************************************/
|
||||
phStatus_t phExample_Init(void)
|
||||
{
|
||||
phStatus_t status = 0;
|
||||
|
||||
/* Bailout on Type A detect */
|
||||
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_BAIL_OUT, PHAC_DISCLOOP_POS_BIT_MASK_A);
|
||||
CHECK_STATUS(status);
|
||||
|
||||
/* Read the version of the reader IC */
|
||||
#if defined NXPBUILD__PHHAL_HW_RC663
|
||||
status = phhalHw_Rc663_ReadRegister(pHal, PHHAL_HW_RC663_REG_VERSION, &bDataBuffer[0]);
|
||||
CHECK_STATUS(status);
|
||||
DEBUG_PRINTF("\nReader chip RC663 Version: 0x%02x\n", bDataBuffer[0]);
|
||||
#endif /* NXPBUILD__PHHAL_HW_RC663 */
|
||||
|
||||
/* Return Success */
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
/* Stubs, in case the phApp_Init.c expects these implementations */
|
||||
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
|
||||
/*
|
||||
* WTX Callback called from WTX timer of 14443p3mC PAL.
|
||||
*/
|
||||
void pWtoxCallBck()
|
||||
{
|
||||
/* Dummy */
|
||||
}
|
||||
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18092MT_SW
|
||||
void pRtoxCallBck()
|
||||
{
|
||||
/* Dummy */
|
||||
}
|
||||
#endif /* NXPBUILD__PHPAL_I18092MT_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHHAL_HW_TARGET
|
||||
/* Stubbed definitions in case TARGET is enabled */
|
||||
uint8_t sens_res[2] = {0x04, 0x00};
|
||||
uint8_t nfc_id1[3] = {0xA1, 0xA2, 0xA3};
|
||||
uint8_t sel_res = 0x40;
|
||||
uint8_t nfc_id3 = 0xFA;
|
||||
uint8_t poll_res[18] = {0x01, 0xFE, 0xB2, 0xB3, 0xB4, 0xB5,
|
||||
0xB6, 0xB7, 0xC0, 0xC1, 0xC2, 0xC3,
|
||||
0xC4, 0xC5, 0xC6, 0xC7, 0x23, 0x45 };
|
||||
#endif /* NXPBUILD__PHHAL_HW_TARGET */
|
||||
@ -0,0 +1,384 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors Gratkorn / Austria
|
||||
*
|
||||
* (C)NXP Semiconductors
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
*particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Internal functions for SW functionality of the Symmetric Cryptography component.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* SLe: Generated 01.12.2009
|
||||
* SLe: Alpha Release 10.01.2010
|
||||
*
|
||||
*/
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <ph_RefDefs.h>
|
||||
#include <phCryptoSym.h>
|
||||
|
||||
#ifdef NXPBUILD__PH_CRYPTOSYM_SW
|
||||
|
||||
#include "phCryptoSym_Sw.h"
|
||||
#ifdef PH_CRYPTOSYM_SW_AES
|
||||
#include "phCryptoSym_Sw_Aes.h"
|
||||
#endif
|
||||
#ifdef PH_CRYPTOSYM_SW_DES
|
||||
#include "phCryptoSym_Sw_Des.h"
|
||||
#endif
|
||||
#include "phCryptoSym_Sw_Int.h"
|
||||
|
||||
phStatus_t phCryptoSym_Sw_CMAC_GenerateK1K2(
|
||||
phCryptoSym_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pSubKey1,
|
||||
uint8_t * pSubKey2
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_CRYTOSYM_SW_FAST_RAM aBuffer[PH_CRYPTOSYM_SW_MAX_BLOCK_SIZE];
|
||||
uint16_t PH_MEMLOC_REM wBlockSize;
|
||||
uint8_t PH_MEMLOC_REM bR_b;
|
||||
|
||||
(void)memset(aBuffer, 0x00, (size_t)sizeof(aBuffer));
|
||||
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_GetConfig(pDataParams, PH_CRYPTOSYM_CONFIG_BLOCK_SIZE, &wBlockSize));
|
||||
|
||||
/* Calculate xor value according to Seq. 5.3 of SP_800-38B */
|
||||
/* R128 = 0exp(120) || 10000111, and R64 = 0exp(59) || 11011. */
|
||||
switch (wBlockSize)
|
||||
{
|
||||
case PH_CRYPTOSYM_AES_BLOCK_SIZE:
|
||||
bR_b = 0x87U;
|
||||
break;
|
||||
case PH_CRYPTOSYM_DES_BLOCK_SIZE:
|
||||
bR_b = 0x1BU;
|
||||
break;
|
||||
default:
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INTERNAL_ERROR, PH_COMP_CRYPTOSYM);
|
||||
}
|
||||
|
||||
/* Encrypt zero block*/
|
||||
/* 1. Let L = CIPHK(0 exp b). */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_EncryptBlock(pDataParams, aBuffer));
|
||||
|
||||
/* Shift the pSubKey array according to NIST SP_800-38B */
|
||||
/* 2. If MSB1(L) = 0, then K1 = L << 1U; */
|
||||
/* Else K1 = (L << 1U) xor Rb; see Sec. 5.3 for the definition of Rb. */
|
||||
phCryptoSym_Sw_CMAC_LeftShift(aBuffer, (uint8_t)wBlockSize, pSubKey1);
|
||||
if (0U != (aBuffer[0] & 0x80U))
|
||||
{
|
||||
/* We need to perform the XOR operation with the R_b array */
|
||||
pSubKey1[wBlockSize - 1U ] ^= bR_b;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* We are done with key1 generation */
|
||||
}
|
||||
|
||||
/* Now let's continue with Key 2 */
|
||||
/* Shift the pSubKey array according to NIST SP_800-38B*/
|
||||
/* 3. If MSB1(K1) = 0, then K2 = K1 << 1U; */
|
||||
/* Else K2 = (K1 << 1U) xor Rb. */
|
||||
phCryptoSym_Sw_CMAC_LeftShift(pSubKey1, (uint8_t)wBlockSize, pSubKey2);
|
||||
|
||||
if (0U != (pSubKey1[0] & 0x80U))
|
||||
{
|
||||
/* We need to perform the XOR operation with the R_b array */
|
||||
pSubKey2[wBlockSize - 1U ] ^= bR_b;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* We are done with key2 generation */
|
||||
}
|
||||
|
||||
#ifndef PH_CRYPTOSYM_SW_ONLINE_CMAC_SUBKEY_CALCULATION
|
||||
pDataParams->bCMACSubKeysInitialized = PH_ON;
|
||||
#endif /* PH_CRYPTOSYM_SW_ONLINE_CMAC_SUBKEY_CALCULATION */
|
||||
|
||||
/* Clear buffer for security reasons */
|
||||
(void)memset(aBuffer, 0x00, (size_t)sizeof(aBuffer));
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
void phCryptoSym_Sw_CMAC_LeftShift(
|
||||
const uint8_t * pInBuffer,
|
||||
uint8_t bInputLen,
|
||||
uint8_t * pOutBuffer
|
||||
)
|
||||
{
|
||||
uint8_t PH_MEMLOC_REM bOverflow = 0;
|
||||
|
||||
do
|
||||
{
|
||||
bInputLen--;
|
||||
pOutBuffer[bInputLen] = pInBuffer[bInputLen] << 1U;
|
||||
pOutBuffer[bInputLen] |= bOverflow;
|
||||
bOverflow = (uint8_t) (((pInBuffer[bInputLen] & 0x80U) != 0U) ? 0x01U : 0x00U);
|
||||
}
|
||||
while(0U != bInputLen);
|
||||
}
|
||||
|
||||
phStatus_t phCryptoSym_Sw_EncryptBlock(
|
||||
phCryptoSym_Sw_DataParams_t * pDataParams,
|
||||
uint8_t PH_CRYTOSYM_SW_FAST_RAM * pBlock
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
|
||||
switch (pDataParams->wKeyType)
|
||||
{
|
||||
#ifdef PH_CRYPTOSYM_SW_AES
|
||||
case PH_CRYPTOSYM_KEY_TYPE_AES128:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Aes_EncryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
PH_CRYPTOSYM_SW_NUM_AES_ROUNDS_128));
|
||||
break;
|
||||
case PH_CRYPTOSYM_KEY_TYPE_AES192:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Aes_EncryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
PH_CRYPTOSYM_SW_NUM_AES_ROUNDS_192));
|
||||
break;
|
||||
case PH_CRYPTOSYM_KEY_TYPE_AES256:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Aes_EncryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
PH_CRYPTOSYM_SW_NUM_AES_ROUNDS_256));
|
||||
break;
|
||||
#endif /* PH_CRYPTOSYM_SW_AES */
|
||||
#ifdef PH_CRYPTOSYM_SW_DES
|
||||
case PH_CRYPTOSYM_KEY_TYPE_DES:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_EncryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
0));
|
||||
break;
|
||||
case PH_CRYPTOSYM_KEY_TYPE_2K3DES:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_EncryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
0));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_DecryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
1));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_EncryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
0));
|
||||
break;
|
||||
case PH_CRYPTOSYM_KEY_TYPE_3K3DES:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_EncryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
0));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_DecryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
1));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_EncryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
2));
|
||||
break;
|
||||
#endif /* PH_CRYPTOSYM_SW_DES */
|
||||
default:
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_CRYPTOSYM);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phCryptoSym_Sw_DecryptBlock(
|
||||
phCryptoSym_Sw_DataParams_t * pDataParams,
|
||||
uint8_t PH_CRYTOSYM_SW_FAST_RAM * pBlock
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
|
||||
switch (pDataParams->wKeyType)
|
||||
{
|
||||
#ifdef PH_CRYPTOSYM_SW_AES
|
||||
case PH_CRYPTOSYM_KEY_TYPE_AES128:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Aes_DecryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
PH_CRYPTOSYM_SW_NUM_AES_ROUNDS_128));
|
||||
break;
|
||||
case PH_CRYPTOSYM_KEY_TYPE_AES192:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Aes_DecryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
PH_CRYPTOSYM_SW_NUM_AES_ROUNDS_192));
|
||||
break;
|
||||
case PH_CRYPTOSYM_KEY_TYPE_AES256:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Aes_DecryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
PH_CRYPTOSYM_SW_NUM_AES_ROUNDS_256));
|
||||
break;
|
||||
#endif /* PH_CRYPTOSYM_SW_AES */
|
||||
#ifdef PH_CRYPTOSYM_SW_DES
|
||||
case PH_CRYPTOSYM_KEY_TYPE_DES:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_DecryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
0));
|
||||
break;
|
||||
case PH_CRYPTOSYM_KEY_TYPE_2K3DES:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_DecryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
0));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_EncryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
1));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_DecryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
0));
|
||||
break;
|
||||
case PH_CRYPTOSYM_KEY_TYPE_3K3DES:
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_DecryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
2));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_EncryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
1));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Des_DecryptBlock(
|
||||
pDataParams,
|
||||
pBlock,
|
||||
0));
|
||||
break;
|
||||
#endif /* PH_CRYPTOSYM_SW_DES */
|
||||
default:
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_CRYPTOSYM);
|
||||
}
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phCryptoSym_Sw_Diversify_CMAC(
|
||||
phCryptoSym_Sw_DataParams_t * pDataParams,
|
||||
const uint8_t * pData,
|
||||
uint16_t wDataLength,
|
||||
uint8_t * pMac,
|
||||
uint8_t * pMacLength
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint16_t PH_MEMLOC_REM wBlockSize;
|
||||
uint16_t PH_MEMLOC_REM wIndex;
|
||||
uint8_t PH_MEMLOC_REM aTmpData[PH_CRYPTOSYM_AES_BLOCK_SIZE * 2U];
|
||||
#ifndef PH_CRYPTOSYM_SW_ONLINE_CMAC_SUBKEY_CALCULATION
|
||||
uint8_t * pSubKey1 = pDataParams->pCMACSubKey1;
|
||||
uint8_t * pSubKey2 = pDataParams->pCMACSubKey2;
|
||||
#else
|
||||
uint8_t pSubKey1[PH_CRYPTOSYM_SW_MAX_BLOCK_SIZE];
|
||||
uint8_t pSubKey2[PH_CRYPTOSYM_SW_MAX_BLOCK_SIZE];
|
||||
|
||||
(void)memset(pSubKey1, 0x00, (size_t)sizeof(pSubKey1));
|
||||
(void)memset(pSubKey2, 0x00, (size_t)sizeof(pSubKey2));
|
||||
#endif /* PH_CRYPTOSYM_SW_ONLINE_CMAC_SUBKEY_CALCULATION */
|
||||
|
||||
/* Clear MAC length */
|
||||
*pMacLength = 0;
|
||||
|
||||
/* Get the block size of the currently loaded key */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_GetConfig(pDataParams, PH_CRYPTOSYM_CONFIG_BLOCK_SIZE, &wBlockSize));
|
||||
|
||||
/* Check input length */
|
||||
if (wDataLength > (wBlockSize << 1U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_LENGTH_ERROR, PH_COMP_CRYPTOSYM);
|
||||
}
|
||||
|
||||
/* Clear IV */
|
||||
(void)memset(pDataParams->pIV, 0x00, wBlockSize);
|
||||
|
||||
/* Now we may start with MAC calculation */
|
||||
|
||||
#ifndef PH_CRYPTOSYM_SW_ONLINE_CMAC_SUBKEY_CALCULATION
|
||||
/* Do we need to compute the sub keys? */
|
||||
if (pDataParams->bCMACSubKeysInitialized == 0x00U)
|
||||
{
|
||||
/* start with sub key generation */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_CMAC_GenerateK1K2(pDataParams, pSubKey1, pSubKey2));
|
||||
}
|
||||
#else
|
||||
/* Always perform with sub key generation */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_CMAC_GenerateK1K2(pDataParams, pSubKey1, pSubKey2));
|
||||
#endif /* PH_CRYPTOSYM_SW_ONLINE_CMAC_SUBKEY_CALCULATION */
|
||||
|
||||
/* Copy data to temporary buffer */
|
||||
(void)memcpy(aTmpData, pData, wDataLength);
|
||||
|
||||
/* Two full blocks -> NO PADDING, K1 */
|
||||
if (wDataLength == (wBlockSize << 1U))
|
||||
{
|
||||
/* XOR with K1 */
|
||||
for (wIndex = 0; wIndex < wBlockSize; ++wIndex)
|
||||
{
|
||||
aTmpData[wBlockSize + wIndex] ^= pSubKey1[wIndex];
|
||||
}
|
||||
}
|
||||
/* Otherwise APPLY PADDING, K2 */
|
||||
else
|
||||
{
|
||||
/* Apply padding */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_ApplyPadding(
|
||||
PH_CRYPTOSYM_PADDING_MODE_2,
|
||||
aTmpData,
|
||||
wDataLength,
|
||||
(uint8_t)(wBlockSize << 1U),
|
||||
(uint16_t)(sizeof(aTmpData)),
|
||||
aTmpData,
|
||||
&wDataLength));
|
||||
|
||||
/* XOR with K2 */
|
||||
for (wIndex = 0; wIndex < wBlockSize; ++wIndex)
|
||||
{
|
||||
aTmpData[wBlockSize + wIndex] ^= pSubKey2[wIndex];
|
||||
}
|
||||
}
|
||||
|
||||
/* Perform encryption */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phCryptoSym_Sw_Encrypt(
|
||||
pDataParams,
|
||||
PH_CRYPTOSYM_CIPHER_MODE_CBC,
|
||||
aTmpData,
|
||||
(PH_CRYPTOSYM_AES_BLOCK_SIZE * 2U),
|
||||
aTmpData));
|
||||
|
||||
/* Return MAC */
|
||||
(void)memcpy(pMac, &aTmpData[wBlockSize], wBlockSize);
|
||||
*pMacLength = (uint8_t)wBlockSize;
|
||||
|
||||
/* Clear the IV for security reasons */
|
||||
(void)memset(pDataParams->pIV, 0, wBlockSize);
|
||||
|
||||
#ifdef PH_CRYPTOSYM_SW_ONLINE_CMAC_SUBKEY_CALCULATION
|
||||
/* Clear key arrays */
|
||||
(void)memset(pSubKey1, 0x00, (size_t)sizeof(pSubKey1));
|
||||
(void)memset(pSubKey2, 0x00, (size_t)sizeof(pSubKey2));
|
||||
#endif
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
#endif /* NXPBUILD__PH_CRYPTOSYM_SW */
|
||||
@ -0,0 +1,476 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_PORT_H_
|
||||
#define _FSL_PORT_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup port
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.port"
|
||||
#endif
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! Version 2.1.0. */
|
||||
#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
|
||||
/*@}*/
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
|
||||
/*! @brief Internal resistor pull feature selection */
|
||||
enum _port_pull
|
||||
{
|
||||
kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
|
||||
kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */
|
||||
kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
|
||||
/*! @brief Slew rate selection */
|
||||
enum _port_slew_rate
|
||||
{
|
||||
kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
|
||||
kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
|
||||
/*! @brief Open Drain feature enable/disable */
|
||||
enum _port_open_drain_enable
|
||||
{
|
||||
kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
|
||||
kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
|
||||
/*! @brief Passive filter feature enable/disable */
|
||||
enum _port_passive_filter_enable
|
||||
{
|
||||
kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
|
||||
kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
|
||||
/*! @brief Configures the drive strength. */
|
||||
enum _port_drive_strength
|
||||
{
|
||||
kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */
|
||||
kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
|
||||
/*! @brief Unlock/lock the pin control register field[15:0] */
|
||||
enum _port_lock_register
|
||||
{
|
||||
kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
|
||||
kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
|
||||
/*! @brief Pin mux selection */
|
||||
typedef enum _port_mux
|
||||
{
|
||||
kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
|
||||
kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */
|
||||
kPORT_MuxAlt2 = 2U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt3 = 3U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt4 = 4U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt5 = 5U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt6 = 6U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt7 = 7U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt8 = 8U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt9 = 9U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt10 = 10U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt11 = 11U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt12 = 12U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt13 = 13U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt14 = 14U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt15 = 15U, /*!< Chip-specific */
|
||||
} port_mux_t;
|
||||
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
|
||||
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
|
||||
/*! @brief Configures the interrupt generation condition. */
|
||||
typedef enum _port_interrupt
|
||||
{
|
||||
kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
|
||||
kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
|
||||
kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
|
||||
kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
|
||||
kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
|
||||
kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
|
||||
kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
|
||||
#endif
|
||||
kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
|
||||
kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
|
||||
kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
|
||||
kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
|
||||
kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
|
||||
#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
|
||||
kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
|
||||
kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */
|
||||
#endif
|
||||
} port_interrupt_t;
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
|
||||
/*! @brief Digital filter clock source selection */
|
||||
typedef enum _port_digital_filter_clock_source
|
||||
{
|
||||
kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
|
||||
kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
|
||||
} port_digital_filter_clock_source_t;
|
||||
|
||||
/*! @brief PORT digital filter feature configuration definition */
|
||||
typedef struct _port_digital_filter_config
|
||||
{
|
||||
uint32_t digitalFilterWidth; /*!< Set digital filter width */
|
||||
port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
|
||||
} port_digital_filter_config_t;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
|
||||
/*! @brief PORT pin configuration structure */
|
||||
typedef struct _port_pin_config
|
||||
{
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
|
||||
uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
|
||||
#else
|
||||
uint16_t : 2;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
|
||||
uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
|
||||
|
||||
uint16_t : 1;
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
|
||||
uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
|
||||
uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
|
||||
uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif
|
||||
|
||||
uint16_t : 1;
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3)
|
||||
uint16_t mux : 3; /*!< Pin mux Configure */
|
||||
uint16_t : 4;
|
||||
#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4)
|
||||
uint16_t mux : 4; /*!< Pin mux Configure */
|
||||
uint16_t : 3;
|
||||
#else
|
||||
uint16_t : 7,
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
|
||||
uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
|
||||
} port_pin_config_t;
|
||||
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
|
||||
/*! @name Configuration */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Sets the port PCR register.
|
||||
*
|
||||
* This is an example to define an input pin or output pin PCR configuration.
|
||||
* @code
|
||||
* // Define a digital input pin PCR configuration
|
||||
* port_pin_config_t config = {
|
||||
* kPORT_PullUp,
|
||||
* kPORT_FastSlewRate,
|
||||
* kPORT_PassiveFilterDisable,
|
||||
* kPORT_OpenDrainDisable,
|
||||
* kPORT_LowDriveStrength,
|
||||
* kPORT_MuxAsGpio,
|
||||
* kPORT_UnLockRegister,
|
||||
* };
|
||||
* @endcode
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param config PORT PCR register configuration structure.
|
||||
*/
|
||||
static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
uint32_t addr = (uint32_t)&base->PCR[pin];
|
||||
*(volatile uint16_t *)(addr) = *((const uint16_t *)config);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the port PCR register for multiple pins.
|
||||
*
|
||||
* This is an example to define input pins or output pins PCR configuration.
|
||||
* @code
|
||||
* // Define a digital input pin PCR configuration
|
||||
* port_pin_config_t config = {
|
||||
* kPORT_PullUp ,
|
||||
* kPORT_PullEnable,
|
||||
* kPORT_FastSlewRate,
|
||||
* kPORT_PassiveFilterDisable,
|
||||
* kPORT_OpenDrainDisable,
|
||||
* kPORT_LowDriveStrength,
|
||||
* kPORT_MuxAsGpio,
|
||||
* kPORT_UnlockRegister,
|
||||
* };
|
||||
* @endcode
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
* @param config PORT PCR register configuration structure.
|
||||
*/
|
||||
static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
uint16_t pcrl = *((const uint16_t *)config);
|
||||
|
||||
if (mask & 0xffffU)
|
||||
{
|
||||
base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
|
||||
}
|
||||
if (mask >> 16)
|
||||
{
|
||||
base->GPCHR = (mask & 0xffff0000U) | pcrl;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG
|
||||
/*!
|
||||
* @brief Sets the port interrupt configuration in PCR register for multiple pins.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
* @param config PORT pin interrupt configuration.
|
||||
* - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
|
||||
* - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
|
||||
* - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
|
||||
* - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
|
||||
* - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
|
||||
* - #kPORT_InterruptLogicZero : Interrupt when logic zero.
|
||||
* - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
|
||||
* - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
|
||||
* - #kPORT_InterruptEitherEdge : Interrupt on either edge.
|
||||
* - #kPORT_InterruptLogicOne : Interrupt when logic one.
|
||||
* - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
|
||||
* - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..
|
||||
*/
|
||||
static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
if (mask & 0xffffU)
|
||||
{
|
||||
base->GICLR = (config << 16) | (mask & 0xffffU);
|
||||
}
|
||||
mask = mask >> 16;
|
||||
if (mask)
|
||||
{
|
||||
base->GICHR = (config << 16) | (mask & 0xffffU);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Configures the pin muxing.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param mux pin muxing slot selection.
|
||||
* - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
|
||||
* - #kPORT_MuxAsGpio : Set as GPIO.
|
||||
* - #kPORT_MuxAlt2 : chip-specific.
|
||||
* - #kPORT_MuxAlt3 : chip-specific.
|
||||
* - #kPORT_MuxAlt4 : chip-specific.
|
||||
* - #kPORT_MuxAlt5 : chip-specific.
|
||||
* - #kPORT_MuxAlt6 : chip-specific.
|
||||
* - #kPORT_MuxAlt7 : chip-specific.
|
||||
* @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
|
||||
* the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
|
||||
* reset to zero : kPORT_PinDisabledOrAnalog).
|
||||
* This function is recommended to use to reset the pin mux
|
||||
*
|
||||
*/
|
||||
static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
|
||||
{
|
||||
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
|
||||
}
|
||||
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
|
||||
|
||||
/*!
|
||||
* @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
*/
|
||||
static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable == true)
|
||||
{
|
||||
base->DFER |= mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->DFER &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param config PORT digital filter configuration structure.
|
||||
*/
|
||||
static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
base->DFCR = PORT_DFCR_CS(config->clockSource);
|
||||
base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
|
||||
}
|
||||
|
||||
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*! @name Interrupt */
|
||||
/*@{*/
|
||||
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
|
||||
/*!
|
||||
* @brief Configures the port pin interrupt/DMA request.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param config PORT pin interrupt configuration.
|
||||
* - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
|
||||
* - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
|
||||
* - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
|
||||
* - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
|
||||
* - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
|
||||
* - #kPORT_InterruptLogicZero : Interrupt when logic zero.
|
||||
* - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
|
||||
* - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
|
||||
* - #kPORT_InterruptEitherEdge : Interrupt on either edge.
|
||||
* - #kPORT_InterruptLogicOne : Interrupt when logic one.
|
||||
* - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
|
||||
* - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).
|
||||
*/
|
||||
static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
|
||||
{
|
||||
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
|
||||
/*!
|
||||
* @brief Configures the port pin drive strength.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param config PORT pin drive strength
|
||||
* - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
|
||||
* - #kPORT_HighDriveStrength = 1U - High-drive strength is configured.
|
||||
*/
|
||||
static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength)
|
||||
{
|
||||
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
|
||||
/*!
|
||||
* @brief Reads the whole port status flag.
|
||||
*
|
||||
* If a pin is configured to generate the DMA request, the corresponding flag
|
||||
* is cleared automatically at the completion of the requested DMA transfer.
|
||||
* Otherwise, the flag remains set until a logic one is written to that flag.
|
||||
* If configured for a level sensitive interrupt that remains asserted, the flag
|
||||
* is set again immediately.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @return Current port interrupt status flags, for example, 0x00010001 means the
|
||||
* pin 0 and 16 have the interrupt.
|
||||
*/
|
||||
static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
|
||||
{
|
||||
return base->ISFR;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the multiple pin interrupt status flag.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
*/
|
||||
static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
|
||||
{
|
||||
base->ISFR = mask;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_PORT_H_ */
|
||||
@ -0,0 +1,880 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2006 - 2017, 2021, 2022, 2024 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Generic KeyStore Component of Reader Library Framework.
|
||||
* $Author:
|
||||
* $Revision:
|
||||
* $Date:
|
||||
*
|
||||
*/
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <phKeyStore.h>
|
||||
#include <ph_RefDefs.h>
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
#include "Sw/phKeyStore_Sw.h"
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
#include "Rc663/phKeyStore_Rc663.h"
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE
|
||||
|
||||
#ifndef NXPRDLIB_REM_GEN_INTFS
|
||||
|
||||
/* Common Interfaces ------------------------------------------------------------------------------------------------------------------- */
|
||||
phStatus_t phKeyStore_FormatKeyEntry(void * pDataParams, uint16_t wKeyNo, uint16_t wNewKeyType)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_FormatKeyEntry");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyNo);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wNewKeyType);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyNo), &wKeyNo);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wNewKeyType), &wNewKeyType);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_FormatKeyEntry((phKeyStore_Sw_DataParams_t *) pDataParams, wKeyNo, wNewKeyType);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_FormatKeyEntry((phKeyStore_Rc663_DataParams_t *) pDataParams, wKeyNo, wNewKeyType);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_SetKUC(void * pDataParams, uint16_t wKeyNo, uint16_t wRefNoKUC)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_SetKUC");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyNo);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wRefNoKUC);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyNo), &wKeyNo);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wRefNoKUC), &wRefNoKUC);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_SetKUC((phKeyStore_Sw_DataParams_t *) pDataParams, wKeyNo, wRefNoKUC);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_SetKUC((phKeyStore_Rc663_DataParams_t *) pDataParams, wKeyNo, wRefNoKUC);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_GetKUC(void * pDataParams, uint16_t wRefNoKUC, uint32_t * pdwLimit, uint32_t * pdwCurVal)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_GetKUC");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wRefNoKUC);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pdwLimit);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pdwCurVal);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pdwLimit, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pdwCurVal, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wRefNoKUC), &wRefNoKUC);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_GetKUC((phKeyStore_Sw_DataParams_t *) pDataParams, wRefNoKUC, pdwLimit, pdwCurVal);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_GetKUC((phKeyStore_Rc663_DataParams_t *) pDataParams, wRefNoKUC, pdwLimit, pdwCurVal);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
#ifdef NXPBUILD__PH_LOG
|
||||
if((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
PH_LOG_HELPER_ADDPARAM_UINT32(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pdwLimit), pdwLimit);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT32(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pdwCurVal), pdwCurVal);
|
||||
}
|
||||
#endif
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_ChangeKUC(void * pDataParams, uint16_t wRefNoKUC, uint32_t dwLimit)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_ChangeKUC");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wRefNoKUC);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(dwLimit);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wRefNoKUC), &wRefNoKUC);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT32(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(dwLimit), &dwLimit);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_ChangeKUC((phKeyStore_Sw_DataParams_t *) pDataParams, wRefNoKUC, dwLimit);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_ChangeKUC((phKeyStore_Rc663_DataParams_t *) pDataParams, wRefNoKUC, dwLimit);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_SetConfig(void * pDataParams, uint16_t wConfig, uint16_t wValue)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_SetConfig");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wConfig);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wValue);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wConfig), &wConfig);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wValue), &wValue);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_SetConfig((phKeyStore_Sw_DataParams_t *) pDataParams, wConfig, wValue);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_SetConfig((phKeyStore_Rc663_DataParams_t *) pDataParams, wConfig, wValue);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_SetConfigStr(void * pDataParams, uint16_t wConfig, uint8_t *pBuffer, uint16_t wBufferLength)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_SetConfigStr");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wConfig);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pBuffer);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wBufferLength);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pBuffer, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wConfig), &wConfig);
|
||||
PH_LOG_HELPER_ADDPARAM_BUFFER(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pBuffer), pBuffer, wBufferLength);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wBufferLength), &wBufferLength);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_SetConfigStr((phKeyStore_Sw_DataParams_t *) pDataParams, wConfig, pBuffer, wBufferLength);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_SetConfigStr((phKeyStore_Rc663_DataParams_t *) pDataParams, wConfig, pBuffer, wBufferLength);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_GetConfig(void * pDataParams, uint16_t wConfig, uint16_t * pValue)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_GetConfig");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wConfig);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pValue);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pValue, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wConfig), &wConfig);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_GetConfig((phKeyStore_Sw_DataParams_t *) pDataParams, wConfig, pValue);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_GetConfig((phKeyStore_Rc663_DataParams_t *) pDataParams, wConfig, pValue);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
#ifdef NXPBUILD__PH_LOG
|
||||
if((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pValue), pValue);
|
||||
}
|
||||
#endif
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_GetConfigStr(void * pDataParams, uint16_t wConfig, uint8_t ** ppBuffer, uint16_t * pBufferLength)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_GetConfigStr");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wConfig);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(ppBuffer);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pBufferLength);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(ppBuffer, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pBufferLength, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wConfig), &wConfig);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_GetConfigStr((phKeyStore_Sw_DataParams_t *) pDataParams, wConfig, ppBuffer, pBufferLength);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_GetConfigStr((phKeyStore_Rc663_DataParams_t *) pDataParams, wConfig, ppBuffer, pBufferLength);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
#ifdef NXPBUILD__PH_LOG
|
||||
if((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
PH_LOG_HELPER_ADDPARAM_BUFFER(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(ppBuffer), *ppBuffer, *pBufferLength);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pBufferLength), pBufferLength);
|
||||
}
|
||||
#endif
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Interfaces for Symmetric Keys ------------------------------------------------------------------------------------------------------- */
|
||||
phStatus_t phKeyStore_SetKey(void * pDataParams, uint16_t wKeyNo, uint16_t wKeyVersion, uint16_t wKeyType, uint8_t * pNewKey,
|
||||
uint16_t wNewKeyVersion)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_SetKey");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyNo);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyVersion);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyType);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pNewKey);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wNewKeyVersion);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pNewKey, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyNo), &wKeyNo);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyVersion), &wKeyVersion);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyType), &wKeyType);
|
||||
PH_LOG_HELPER_ADDPARAM_BUFFER(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pNewKey), pNewKey, phKeyStore_GetKeySize(wKeyType));
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wNewKeyVersion), &wNewKeyVersion);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_SetKey((phKeyStore_Sw_DataParams_t *) pDataParams, wKeyNo, wKeyVersion, wKeyType, pNewKey, wNewKeyVersion);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_SetKey((phKeyStore_Rc663_DataParams_t *) pDataParams, wKeyNo, wKeyVersion, wKeyType, pNewKey, wNewKeyVersion);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_SetKeyAtPos(void * pDataParams, uint16_t wKeyNo, uint16_t wPos, uint16_t wKeyType, uint8_t * pNewKey,
|
||||
uint16_t wNewKeyVersion)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_SetKeyAtPos");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyNo);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wPos);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyType);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pNewKey);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wNewKeyVersion);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pNewKey, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyNo), &wKeyNo);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wPos), &wPos);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyType), &wKeyType);
|
||||
PH_LOG_HELPER_ADDPARAM_BUFFER(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pNewKey), pNewKey, phKeyStore_GetKeySize(wKeyType));
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wNewKeyVersion), &wNewKeyVersion);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_SetKeyAtPos((phKeyStore_Sw_DataParams_t *) pDataParams, wKeyNo, wPos, wKeyType, pNewKey, wNewKeyVersion);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_SetKeyAtPos((phKeyStore_Rc663_DataParams_t *) pDataParams, wKeyNo, wPos, wKeyType, pNewKey, wNewKeyVersion);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_SetFullKeyEntry(void * pDataParams, uint16_t wNoOfKeys, uint16_t wKeyNo, uint16_t wNewRefNoKUC,
|
||||
uint16_t wNewKeyType, uint8_t * pNewKeys, uint16_t * pNewKeyVersionList)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_SetFullKeyEntry");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wNoOfKeys);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyNo);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wNewRefNoKUC);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wNewKeyType);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pNewKeys);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pNewKeyVersionList);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pNewKeys, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pNewKeyVersionList, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wNoOfKeys), &wNoOfKeys);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyNo), &wKeyNo);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wNewRefNoKUC), &wNewRefNoKUC);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wNewKeyType), &wNewKeyType);
|
||||
PH_LOG_HELPER_ADDPARAM_BUFFER(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pNewKeys), pNewKeys, phKeyStore_GetKeySize(wNewKeyType)*wNoOfKeys);
|
||||
PH_LOG_HELPER_ADDPARAM_BUFFER(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pNewKeyVersionList), pNewKeyVersionList, wNoOfKeys);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_SetFullKeyEntry((phKeyStore_Sw_DataParams_t *) pDataParams, wNoOfKeys, wKeyNo, wNewRefNoKUC, wNewKeyType, pNewKeys, pNewKeyVersionList);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_SetFullKeyEntry((phKeyStore_Rc663_DataParams_t *) pDataParams, wNoOfKeys, wKeyNo, wNewRefNoKUC, wNewKeyType, pNewKeys, pNewKeyVersionList);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_GetKeyEntry(void * pDataParams, uint16_t wKeyNo, uint16_t wKeyVersionBufSize, uint16_t * wKeyVersion,
|
||||
uint16_t * wKeyVersionLength, uint16_t * pKeyType)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_GetKeyEntry");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyNo);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyVersionBufSize);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyVersion);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pKeyType);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(wKeyVersion, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(wKeyVersionLength, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pKeyType, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyNo), &wKeyNo);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyVersionBufSize), &wKeyVersionBufSize);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_GetKeyEntry((phKeyStore_Sw_DataParams_t *) pDataParams, wKeyNo, wKeyVersionBufSize, wKeyVersion, wKeyVersionLength, pKeyType);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_GetKeyEntry((phKeyStore_Rc663_DataParams_t *) pDataParams, wKeyNo, wKeyVersionBufSize, wKeyVersion, wKeyVersionLength, pKeyType);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
#ifdef NXPBUILD__PH_LOG
|
||||
if((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
PH_LOG_HELPER_ADDPARAM_BUFFER(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyVersion), wKeyVersion, *wKeyVersionLength);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pKeyType), pKeyType);
|
||||
}
|
||||
#endif
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_GetKey(void * pDataParams, uint16_t wKeyNo, uint16_t wKeyVersion, uint8_t bKeyBufSize, uint8_t * pKey,
|
||||
uint16_t * pKeyType)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
|
||||
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phKeyStore_GetKey");
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyNo);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(wKeyVersion);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(bKeyBufSize);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pKey);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pKeyType);
|
||||
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
|
||||
|
||||
/* Validate the parameters. */
|
||||
PH_ASSERT_NULL_DATA_PARAM(pDataParams, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pKey, PH_COMP_KEYSTORE);
|
||||
PH_ASSERT_NULL_PARAM(pKeyType, PH_COMP_KEYSTORE);
|
||||
|
||||
/* Log the information. */
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyNo), &wKeyNo);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(wKeyVersion), &wKeyVersion);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT8(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(bKeyBufSize), &bKeyBufSize);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
|
||||
|
||||
/* Component Code Validation */
|
||||
if(PH_GET_COMPCODE(pDataParams) != PH_COMP_KEYSTORE)
|
||||
{
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Perform operation on active layer. */
|
||||
switch(PH_GET_COMPID(pDataParams))
|
||||
{
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_SW
|
||||
case PH_KEYSTORE_SW_ID:
|
||||
status = phKeyStore_Sw_GetKey((phKeyStore_Sw_DataParams_t *) pDataParams, wKeyNo, wKeyVersion, bKeyBufSize, pKey, pKeyType);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_SW */
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
case PH_KEYSTORE_RC663_ID:
|
||||
status = phKeyStore_Rc663_GetKey((phKeyStore_Rc663_DataParams_t *) pDataParams, wKeyNo, wKeyVersion, bKeyBufSize, pKey, pKeyType);
|
||||
break;
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
break;
|
||||
}
|
||||
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
|
||||
#ifdef NXPBUILD__PH_LOG
|
||||
if((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
PH_LOG_HELPER_ADDPARAM_BUFFER(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pKey), pKey, phKeyStore_GetKeySize(*pKeyType));
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_DEBUG, PH_LOG_VAR(pKeyType), pKeyType);
|
||||
}
|
||||
#endif
|
||||
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, PH_LOG_VAR(status), &status);
|
||||
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /* NXPRDLIB_REM_GEN_INTFS */
|
||||
|
||||
/* Utility Interfaces ------------------------------------------------------------------------------------------------------------------ */
|
||||
uint8_t phKeyStore_GetKeySize(uint16_t wKeyType)
|
||||
{
|
||||
switch(wKeyType)
|
||||
{
|
||||
case PH_KEYSTORE_KEY_TYPE_MIFARE:
|
||||
/* 6 bytes for key A + 6 bytes for key B */
|
||||
return 12;
|
||||
|
||||
case PH_KEYSTORE_KEY_TYPE_DES:
|
||||
return 8;
|
||||
|
||||
case PH_KEYSTORE_KEY_TYPE_2K3DES:
|
||||
case PH_KEYSTORE_KEY_TYPE_AES128:
|
||||
return 16;
|
||||
|
||||
case PH_KEYSTORE_KEY_TYPE_3K3DES:
|
||||
case PH_KEYSTORE_KEY_TYPE_AES192:
|
||||
return 24;
|
||||
|
||||
case PH_KEYSTORE_KEY_TYPE_AES256:
|
||||
return 32;
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
#endif /* NXPBUILD__PH_KEYSTORE */
|
||||
@ -0,0 +1,438 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2016-2022 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
|
||||
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
|
||||
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
|
||||
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
|
||||
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
|
||||
* The RdLib component initialization requires some user defined data and function pointers.
|
||||
* These are defined in the respective examples and externed here.
|
||||
*
|
||||
* Keystore and Crypto initialization needs to be handled by application.
|
||||
*
|
||||
* $Author: NXP$
|
||||
* $Revision: $ (v07.10.00)
|
||||
* $Date: $
|
||||
*
|
||||
*/
|
||||
|
||||
/* Status header */
|
||||
#include <ph_Status.h>
|
||||
|
||||
#include "phApp_Init.h"
|
||||
|
||||
/* LLCP header */
|
||||
#include <phlnLlcp.h>
|
||||
|
||||
#include <phOsal.h>
|
||||
|
||||
#ifdef PH_PLATFORM_HAS_ICFRONTEND
|
||||
#include "BoardSelection.h"
|
||||
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
|
||||
|
||||
#ifdef PHDRIVER_KINETIS_K82
|
||||
#include <fsl_port.h>
|
||||
#include <fsl_pit.h>
|
||||
#ifdef DEBUG
|
||||
#include <fsl_clock.h>
|
||||
#endif /* DEBUG */
|
||||
#endif /* PHDRIVER_KINETIS_K82 */
|
||||
|
||||
#ifdef PHDRIVER_KINETIS_K82
|
||||
#ifdef DEBUG
|
||||
|
||||
#define KINETIS_K82_DEBUG_UART_CLK_FREQ CLOCK_GetOsc0ErClkFreq()
|
||||
#define KINETIS_K82_DEBUG_UART_BASEADDR (uint32_t)(LPUART4)
|
||||
#define KINETIS_K82_DEBUG_UART_INSTANCE 4U
|
||||
#define KINETIS_K82_DEBUG_UART_BAUDRATE 115200
|
||||
#define KINETIS_K82_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
|
||||
|
||||
#endif /* DEBUG */
|
||||
|
||||
/*! @brief Clock configuration structure. */
|
||||
typedef struct _clock_config
|
||||
{
|
||||
mcg_config_t mcgConfig; /*!< MCG configuration. */
|
||||
sim_clock_config_t simConfig; /*!< SIM configuration. */
|
||||
osc_config_t oscConfig; /*!< OSC configuration. */
|
||||
uint32_t coreClock; /*!< core clock frequency. */
|
||||
} clock_config_t;
|
||||
#endif /* PHDRIVER_KINETIS_K82 */
|
||||
|
||||
#ifdef PH_OSAL_LINUX
|
||||
# define PI_IRQ_POLLING_TASK_PRIO 0
|
||||
# define PI_IRQ_POLLING_TASK_STACK 0x20000
|
||||
phOsal_ThreadObj_t gphPiThreadObj;
|
||||
#endif /* PH_OSAL_LINUX */
|
||||
|
||||
#if defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
|
||||
uint32_t SystemCoreClock;
|
||||
#endif
|
||||
/*******************************************************************************
|
||||
** Function Declarations
|
||||
*******************************************************************************/
|
||||
#ifdef PHDRIVER_KINETIS_K82
|
||||
static void phApp_K82_Init(void);
|
||||
#endif /* PHDRIVER_KINETIS_K82 */
|
||||
|
||||
#ifdef PH_OSAL_LINUX
|
||||
static void phExample_IrqPolling(void* param);
|
||||
#endif /* PH_OSAL_LINUX */
|
||||
|
||||
phStatus_t phApp_Configure_IRQ();
|
||||
|
||||
/*******************************************************************************
|
||||
** Clock configuration of K82 Platform
|
||||
*******************************************************************************/
|
||||
|
||||
#ifdef PHDRIVER_KINETIS_K82
|
||||
/* Configuration for enter RUN mode. Core clock = 50MHz. */
|
||||
const clock_config_t g_defaultClockConfigRun = {
|
||||
.mcgConfig =
|
||||
{
|
||||
.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
|
||||
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
|
||||
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
|
||||
.fcrdiv = 0U, /* FCRDIV is 0. */
|
||||
|
||||
.frdiv = 4U,
|
||||
.drs = kMCG_DrsLow, /* Low frequency range. */
|
||||
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
|
||||
.oscsel = kMCG_OscselOsc, /* Select OSC. */
|
||||
|
||||
.pll0Config =
|
||||
{
|
||||
.enableMode = 0U, .prdiv = 0x01U, .vdiv = 0x01U,
|
||||
},
|
||||
},
|
||||
.simConfig =
|
||||
{
|
||||
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
|
||||
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
|
||||
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
|
||||
.er32kSrc = 5U, /* ERCLK32K selection, use RTC. */
|
||||
.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
|
||||
},
|
||||
.oscConfig = {.freq = CPU_XTAL_CLK_HZ,
|
||||
.capLoad = 0,
|
||||
.workMode = kOSC_ModeOscLowPower,
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = kOSC_ErClkEnable,
|
||||
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
|
||||
.erclkDiv = 0U,
|
||||
#endif
|
||||
}},
|
||||
|
||||
};
|
||||
#endif /* PHDRIVER_KINETIS_K82 */
|
||||
|
||||
/*******************************************************************************
|
||||
** Global Variable Declaration
|
||||
*******************************************************************************/
|
||||
|
||||
#ifdef NXPBUILD__PHLN_LLCP_SW
|
||||
phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
|
||||
#endif /* NXPBUILD__PHLN_LLCP_SW */
|
||||
|
||||
/* General information bytes to be sent with ATR Request */
|
||||
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
|
||||
uint8_t aLLCPGeneralBytes[36] = { 0x46,0x66,0x6D,
|
||||
0x01,0x01,0x10, /*VERSION*/
|
||||
0x03,0x02,0x00,0x01, /*WKS*/
|
||||
0x04,0x01,0xF1 /*LTO*/
|
||||
};
|
||||
uint8_t bLLCPGBLength = 13;
|
||||
#endif
|
||||
|
||||
/* ATR Response or ATS Response holder */
|
||||
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) || \
|
||||
defined(NXPBUILD__PHPAL_I18092MPI_SW)
|
||||
uint8_t aResponseHolder[64];
|
||||
#endif
|
||||
|
||||
/* prints if error is detected */
|
||||
#define CHECK_SUCCESS(x) \
|
||||
if ((x) != PH_ERR_SUCCESS) \
|
||||
{ \
|
||||
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
|
||||
return (x); \
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function Definitions
|
||||
*******************************************************************************/
|
||||
#ifdef PHDRIVER_KINETIS_K82
|
||||
static void phApp_K82_Init(void)
|
||||
{
|
||||
#ifdef DEBUG
|
||||
uint32_t uartClkSrcFreq;
|
||||
#endif /* DEBUG */
|
||||
|
||||
pit_config_t pitConfig; /* Structure of initialize PIT */
|
||||
|
||||
CLOCK_SetSimSafeDivs();
|
||||
|
||||
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
|
||||
CLOCK_SetXtal0Freq(CPU_XTAL_CLK_HZ);
|
||||
|
||||
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
|
||||
&g_defaultClockConfigRun.mcgConfig.pll0Config);
|
||||
|
||||
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
|
||||
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
|
||||
|
||||
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
/*
|
||||
* pitConfig.enableRunInDebug = false;
|
||||
*/
|
||||
PIT_GetDefaultConfig(&pitConfig);
|
||||
|
||||
/* Init pit module */
|
||||
PIT_Init(PIT, &pitConfig);
|
||||
|
||||
#ifdef DEBUG
|
||||
|
||||
/* Initialize LPUART4 pins below used to Print */
|
||||
/* Ungate the port clock */
|
||||
CLOCK_EnableClock(kCLOCK_PortC);
|
||||
/* Affects PORTC_PCR14 register */
|
||||
PORT_SetPinMux(PORTC, 14U, kPORT_MuxAlt3);
|
||||
/* Affects PORTC_PCR15 register */
|
||||
PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt3);
|
||||
|
||||
/* SIM_SOPT2[27:26]:
|
||||
* 00: Clock Disabled
|
||||
* 01: MCGFLLCLK, or MCGPLLCLK, or IRC48M
|
||||
* 10: OSCERCLK
|
||||
* 11: MCGIRCCLK
|
||||
*/
|
||||
CLOCK_SetLpuartClock(2);
|
||||
|
||||
uartClkSrcFreq = KINETIS_K82_DEBUG_UART_CLK_FREQ;
|
||||
|
||||
DbgConsole_Init(KINETIS_K82_DEBUG_UART_INSTANCE, KINETIS_K82_DEBUG_UART_BAUDRATE, KINETIS_K82_DEBUG_UART_TYPE, uartClkSrcFreq);
|
||||
#endif /* DEBUG */
|
||||
}
|
||||
#endif /* PHDRIVER_KINETIS_K82 */
|
||||
|
||||
#ifdef PH_PLATFORM_HAS_ICFRONTEND
|
||||
/**
|
||||
* This function will initialize Host Controller interfaced with NXP Reader IC's.
|
||||
* Any initialization which is not generic across Platforms, should be done here.
|
||||
* Note: For NXP NFC Controllers HOST initialization is not required.
|
||||
*/
|
||||
void phApp_CPU_Init(void)
|
||||
{
|
||||
#if defined PHDRIVER_KINETIS_K82
|
||||
phApp_K82_Init();
|
||||
#elif defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
|
||||
SystemCoreClock = (( unsigned long ) 96000000);
|
||||
#elif defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190)
|
||||
phStatus_t status;
|
||||
status = PiGpio_OpenIrq();
|
||||
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
|
||||
{
|
||||
DEBUG_PRINTF("\n PiGpio_OpenIrq failed \n");
|
||||
DEBUG_PRINTF("\n Couldn't open PN5190 Kernel IRQ Driver.\n Halting here!!FIX IT!!\n");
|
||||
while(1);
|
||||
}
|
||||
#else
|
||||
/* In case of LPC series, startup file takes care of initializing clock and ports.
|
||||
* No initialization is required in Linux environment. */
|
||||
#endif /* PHDRIVER_KINETIS_K82 */
|
||||
}
|
||||
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
|
||||
|
||||
/**
|
||||
* This function will initialize Reader LIbrary Component
|
||||
*/
|
||||
phStatus_t phApp_Comp_Init(void * pDiscLoopParams)
|
||||
{
|
||||
phStatus_t wStatus = PH_ERR_SUCCESS;
|
||||
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW) || \
|
||||
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
|
||||
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || \
|
||||
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
|
||||
|
||||
phacDiscLoop_Sw_DataParams_t * pDiscLoop = (phacDiscLoop_Sw_DataParams_t *)pDiscLoopParams;
|
||||
#endif
|
||||
|
||||
/* Initialize the LLCP component */
|
||||
#ifdef NXPBUILD__PHLN_LLCP_SW
|
||||
slnLlcp.sLocalLMParams.wMiu = 0x00; /* 128 bytes only */
|
||||
slnLlcp.sLocalLMParams.wWks = 0x11; /* SNEP & LLCP */
|
||||
slnLlcp.sLocalLMParams.bLto = 100; /* Maximum LTO */
|
||||
slnLlcp.sLocalLMParams.bOpt = 0x02;
|
||||
slnLlcp.sLocalLMParams.bAvailableTlv = PHLN_LLCP_TLV_MIUX_MASK | PHLN_LLCP_TLV_WKS_MASK |
|
||||
PHLN_LLCP_TLV_LTO_MASK | PHLN_LLCP_TLV_OPT_MASK;
|
||||
|
||||
wStatus = phlnLlcp_Sw_Init(
|
||||
&slnLlcp,
|
||||
sizeof(phlnLlcp_Sw_DataParams_t),
|
||||
aLLCPGeneralBytes,
|
||||
&bLLCPGBLength);
|
||||
#endif /* NXPBUILD__PHLN_LLCP_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAC_DISCLOOP_SW
|
||||
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
|
||||
/* Assign the GI for Type A */
|
||||
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
|
||||
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.bGiLength = bLLCPGBLength;
|
||||
/* Assign the GI for Type F */
|
||||
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
|
||||
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.bGiLength = bLLCPGBLength;
|
||||
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
|
||||
|
||||
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
|
||||
/* Assign ATR response for Type A */
|
||||
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pAtrRes = aResponseHolder;
|
||||
#endif
|
||||
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || \
|
||||
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
|
||||
/* Assign ATR response for Type F */
|
||||
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pAtrRes = aResponseHolder;
|
||||
#endif
|
||||
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS
|
||||
/* Assign ATS buffer for Type A */
|
||||
pDiscLoop->sTypeATargetInfo.sTypeA_I3P4.pAts = aResponseHolder;
|
||||
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS */
|
||||
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
|
||||
return wStatus;
|
||||
}
|
||||
|
||||
phStatus_t phApp_Configure_IRQ()
|
||||
{
|
||||
#ifdef PH_OSAL_LINUX
|
||||
phStatus_t wStatus;
|
||||
#endif /* PH_OSAL_LINUX */
|
||||
|
||||
#ifdef PH_PLATFORM_HAS_ICFRONTEND
|
||||
#if !(defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190))
|
||||
phDriver_Pin_Config_t pinCfg;
|
||||
|
||||
pinCfg.bOutputLogic = PH_DRIVER_SET_LOW;
|
||||
pinCfg.bPullSelect = PHDRIVER_PIN_IRQ_PULL_CFG;
|
||||
|
||||
pinCfg.eInterruptConfig = PIN_IRQ_TRIGGER_TYPE;
|
||||
phDriver_PinConfig(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT, &pinCfg);
|
||||
#endif
|
||||
|
||||
#ifdef PHDRIVER_LPC1769
|
||||
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
|
||||
/* Enable interrupt in the NVIC */
|
||||
NVIC_ClearPendingIRQ(EINT_IRQn);
|
||||
NVIC_EnableIRQ(EINT_IRQn);
|
||||
#endif /* PHDRIVER_LPC1769 */
|
||||
|
||||
#ifdef PH_OSAL_LINUX
|
||||
|
||||
gphPiThreadObj.pTaskName = (uint8_t *) "IrqPolling";
|
||||
gphPiThreadObj.pStackBuffer = NULL;
|
||||
gphPiThreadObj.priority = PI_IRQ_POLLING_TASK_PRIO;
|
||||
gphPiThreadObj.stackSizeInNum = PI_IRQ_POLLING_TASK_STACK;
|
||||
PH_CHECK_SUCCESS_FCT(wStatus, phOsal_ThreadCreate(&gphPiThreadObj.ThreadHandle, &gphPiThreadObj,
|
||||
&phExample_IrqPolling, NULL));
|
||||
|
||||
#endif /* PH_OSAL_LINUX */
|
||||
|
||||
#ifdef PHDRIVER_KINETIS_K82
|
||||
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
|
||||
NVIC_ClearPendingIRQ(EINT_IRQn);
|
||||
EnableIRQ(EINT_IRQn);
|
||||
#endif /* PHDRIVER_KINETIS_K82 */
|
||||
|
||||
#endif /* #ifdef PH_PLATFORM_HAS_ICFRONTEND */
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
#ifdef PH_OSAL_LINUX
|
||||
/*
|
||||
* \brief: The purpose of this Thread is to detect RF signal from an External Peer .
|
||||
*/
|
||||
static void phExample_IrqPolling(void* param)
|
||||
{
|
||||
uint8_t bgpioVal = 0;
|
||||
uint8_t bhighOrLow = 0;
|
||||
|
||||
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
|
||||
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
|
||||
{
|
||||
bhighOrLow = 1;
|
||||
}
|
||||
|
||||
while(PiGpio_read(PHDRIVER_PIN_IRQ, &bgpioVal) != PH_ERR_SUCCESS)
|
||||
{
|
||||
PiGpio_unexport(PHDRIVER_PIN_IRQ);
|
||||
PiGpio_export(PHDRIVER_PIN_IRQ);
|
||||
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
|
||||
|
||||
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
|
||||
{
|
||||
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
|
||||
}
|
||||
else
|
||||
{
|
||||
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
|
||||
}
|
||||
}
|
||||
|
||||
/* Initial status: If pin is already Active, post an event. */
|
||||
if(bgpioVal == bhighOrLow)
|
||||
{
|
||||
CLIF_IRQHandler();
|
||||
}
|
||||
#endif
|
||||
|
||||
while(1)
|
||||
{
|
||||
/* Block forever for Raising Edge in PHDRIVER_PIN_IRQ. */
|
||||
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
|
||||
if(PiGpio_poll(PHDRIVER_PIN_IRQ, bhighOrLow, -1) == PH_ERR_SUCCESS)
|
||||
#elif defined(NXPBUILD__PHHAL_HW_PN5190)
|
||||
if(PiGpio_Irq() == PH_ERR_SUCCESS)
|
||||
#endif
|
||||
{
|
||||
CLIF_IRQHandler();
|
||||
}
|
||||
else
|
||||
{
|
||||
PiGpio_unexport(PHDRIVER_PIN_IRQ);
|
||||
|
||||
PiGpio_export(PHDRIVER_PIN_IRQ);
|
||||
|
||||
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
|
||||
|
||||
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
|
||||
{
|
||||
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
|
||||
}
|
||||
else
|
||||
{
|
||||
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
#endif /* PH_OSAL_LINUX */
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright 2019 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PERIPHERALS_H_
|
||||
#define _PERIPHERALS_H_
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Initialization functions
|
||||
**********************************************************************************************************************/
|
||||
void BOARD_InitPeripherals(void);
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* BOARD_InitBootPeripherals function
|
||||
**********************************************************************************************************************/
|
||||
void BOARD_InitBootPeripherals(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _PERIPHERALS_H_ */
|
||||
@ -0,0 +1,669 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2014-2020, 2022, 2023 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Generic Tag Operation Application Layer Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*/
|
||||
|
||||
#ifndef PHALTOP_H
|
||||
#define PHALTOP_H
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <phacDiscLoop.h>
|
||||
#include <phalT1T.h>
|
||||
#include <phalMful.h>
|
||||
/* #define __DEBUG */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP_SW
|
||||
|
||||
/** \defgroup phalTop_Sw Component : Software
|
||||
* @{
|
||||
*/
|
||||
#define PHAL_TOP_SW_ID 0x01U /**< ID for Software Tag Operation layer */
|
||||
|
||||
#define PHAL_TOP_MAX_TAGTYPE_SUPPORTED 0x06U /**< Maximum number of Tag Types Supported */
|
||||
|
||||
#define PHAL_TOP_T1T_MAX_MEM_CTRL_TLV 0x01U /**< Max Memory control TLV count for T1T */
|
||||
#define PHAL_TOP_T1T_MAX_LOCK_CTRL_TLV 0x01U /**< Max Lock control TLV count for T1T */
|
||||
|
||||
#define PHAL_TOP_T2T_MAX_MEM_CTRL_TLV 0x03U /**< Max Memory control TLV count for T2T */
|
||||
#define PHAL_TOP_T2T_MAX_LOCK_CTRL_TLV 0x03U /**< Max Lock control TLV count for T2T */
|
||||
|
||||
#define PHAL_TOP_T3T_READ_MAX_BLOCKS 0x0FU /**< Max number of blocks supported in one read command. */
|
||||
#define PHAL_TOP_T3T_WRITE_MAX_BLOCKS 0x0FU /**< Max number of blocks supported in one write command. */
|
||||
|
||||
#define PHAL_TOP_T1T_NDEF_SUPPORTED_VNO 0x10U /**< Version Number for T1T */
|
||||
#define PHAL_TOP_T2T_NDEF_SUPPORTED_VNO 0x10U /**< Version Number for T2T */
|
||||
#define PHAL_TOP_T3T_NDEF_SUPPORTED_VNO 0x11U /**< Version Number for T3T */
|
||||
#define PHAL_TOP_T4T_NDEF_SUPPORTED_VNO 0x30U /**< Version Number for T4T - Default Mapping version 3.0 */
|
||||
#define PHAL_TOP_T4T_NDEF_SUPPORTED_VNO_20 0x20U /**< Version Number for T4T - Mapping version 2.0 */
|
||||
#define PHAL_TOP_T5T_NDEF_SUPPORTED_VNO 0x10U /**< Version Number for T5T */
|
||||
|
||||
/** \name phalTop Custom Error Codes
|
||||
*/
|
||||
/** @{ */
|
||||
#define PHAL_TOP_ERR_READONLY_TAG ((phStatus_t)PH_ERR_CUSTOM_BEGIN + 0x01U) /**< Tag is Read Only */
|
||||
#define PHAL_TOP_ERR_INVALID_STATE ((phStatus_t)PH_ERR_CUSTOM_BEGIN + 0x02U) /**< Tag state is invalid */
|
||||
#define PHAL_TOP_ERR_FORMATTED_TAG ((phStatus_t)PH_ERR_CUSTOM_BEGIN + 0x03U) /**< Tag already in NDEF formatted state. */
|
||||
#define PHAL_TOP_ERR_UNSUPPORTED_VERSION ((phStatus_t)PH_ERR_CUSTOM_BEGIN + 0x04U) /**< Unsupported NDEF version. */
|
||||
#define PHAL_TOP_ERR_MISCONFIGURED_TAG ((phStatus_t)PH_ERR_CUSTOM_BEGIN + 0x05U) /**< Tag not configured as per NDEF specification. */
|
||||
#define PHAL_TOP_ERR_UNSUPPORTED_TAG ((phStatus_t)PH_ERR_CUSTOM_BEGIN + 0x06U) /**< Tag with unsupported structure/format. */
|
||||
#define PHAL_TOP_ERR_EMPTY_NDEF ((phStatus_t)PH_ERR_CUSTOM_BEGIN + 0x07U) /**< NDEF message length is zero (i.e. Tag in initialized state). */
|
||||
#define PHAL_TOP_ERR_NON_NDEF_TAG ((phStatus_t)PH_ERR_CUSTOM_BEGIN + 0x08U) /**< Tag is not NDEF formatted. */
|
||||
/** @} */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP_T1T_SW
|
||||
/**
|
||||
* \brief T1T Lock Control TLV parameter structure
|
||||
*/
|
||||
typedef struct /*phalTop_T1T_LockCtrlTlv*/
|
||||
{
|
||||
uint16_t wOffset; /**< TLV offset */
|
||||
uint16_t wByteAddr; /**< Lock bytes start address/offset */
|
||||
uint8_t bSizeInBits; /**< Lock bytes size in bits */
|
||||
uint8_t bBytesPerPage; /**< Number of Bytes per page */
|
||||
uint8_t bBytesLockedPerBit; /**< Number of bytes locked per lock bit */
|
||||
}phalTop_T1T_LockCtrlTlv_t;
|
||||
|
||||
/**
|
||||
* \brief T1T Memory Control TLV parameter structure
|
||||
*/
|
||||
typedef struct /*phalTop_T1T_MemCtrlTlv*/
|
||||
{
|
||||
uint16_t wOffset; /**< TLV offset */
|
||||
uint16_t wByteAddr; /**< Reserved memory start address/offset */
|
||||
uint8_t bSizeInBytes; /**< Reserved memory size in bytes */
|
||||
uint8_t bBytesPerPage; /**< Number of Bytes per page */
|
||||
}phalTop_T1T_MemCtrlTlv_t;
|
||||
|
||||
/**
|
||||
* \brief T1T Proprietary TLV parameter structure
|
||||
*/
|
||||
typedef struct /*phalTop_T1T_ProprietaryTlv*/
|
||||
{
|
||||
uint16_t wOffset; /**< TLV address/offset */
|
||||
uint16_t wLength; /**< TLV Length */
|
||||
}phalTop_T1T_ProprietaryTlv_t;
|
||||
|
||||
/**
|
||||
* \brief T1T Segment parameters
|
||||
*/
|
||||
typedef struct /*phalTop_TIT_Segment*/
|
||||
{
|
||||
uint8_t bAddress; /**< Current active segment address */
|
||||
uint8_t * pData; /**< Segment data (points to HAL RX buffer) */
|
||||
uint8_t bLockReservedOtp[16]; /**< Lock/reserved/OTP bytes in current segment */
|
||||
}phalTop_TIT_Segment_t;
|
||||
#endif /* NXPBUILD__PHAL_TOP_T1T_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP_T2T_SW
|
||||
/**
|
||||
* \brief T2T Lock Control TLV parameter structure
|
||||
*/
|
||||
typedef struct /* phalTop_T2T_LockCtrlTlv */
|
||||
{
|
||||
uint16_t wOffset; /**< TLV offset */
|
||||
uint16_t wByteAddr; /**< Lock bytes start address/offset */
|
||||
uint8_t bSizeInBits; /**< Lock bytes size in bits */
|
||||
uint8_t bBytesPerPage; /**< Number of Bytes per page */
|
||||
uint8_t bBytesLockedPerBit; /**< Number of bytes locked per lock bit */
|
||||
}phalTop_T2T_LockCtrlTlv_t;
|
||||
|
||||
/**
|
||||
* \brief T2T Memory Control TLV parameter structure
|
||||
*/
|
||||
typedef struct /*phalTop_T2T_MemCtrlTlv*/
|
||||
{
|
||||
uint16_t wOffset; /**< TLV offset */
|
||||
uint16_t wByteAddr; /**< Reserved memory start address/offset */
|
||||
uint8_t bSizeInBytes; /**< Reserved memory size in bytes */
|
||||
uint8_t bBytesPerPage; /**< Number of Bytes per page */
|
||||
}phalTop_T2T_MemCtrlTlv_t;
|
||||
|
||||
/**
|
||||
* \brief T2T Sector parameters
|
||||
*/
|
||||
typedef struct /*phalTop_T2T_Sector*/
|
||||
{
|
||||
uint8_t bAddress; /**< Current active Sector address */
|
||||
uint8_t bBlockAddress; /**< Current active block address */
|
||||
uint8_t bLockReservedOtp[32]; /**< Lock/reserved/OTP bytes in current Sector */
|
||||
uint8_t bValidity; /**< Read data validity */
|
||||
}phalTop_T2T_Sector_t;
|
||||
#endif /* NXPBUILD__PHAL_TOP_T2T_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP_T1T_SW
|
||||
/**
|
||||
* \brief T1T parameter structure
|
||||
*/
|
||||
typedef struct /*phalTop_T1T*/
|
||||
{
|
||||
void * pAlT1TDataParams; /**< Pointer to T1T data parameters */
|
||||
uint8_t bRwa; /**< Tag read/write size */
|
||||
uint8_t bTms; /**< Tag Memory size */
|
||||
uint8_t bTagMemoryType; /**< Tag memory type (static or dynamic) */
|
||||
uint8_t bTerminatorTlvPresence; /**< Terminator TLV presence; 1 -present, 0 - not present */
|
||||
uint8_t bLockTlvCount; /**< Number of lock TLV present in tag */
|
||||
uint8_t bMemoryTlvCount; /**< Number of memory TLV present in tag */
|
||||
uint16_t wNdefHeaderAddr; /**< Header offset of first NDEF message */
|
||||
uint16_t wNdefMsgAddr; /**< NDEF message start address */
|
||||
uint8_t bUid[4]; /**< T1T UID */
|
||||
phalTop_T1T_MemCtrlTlv_t asMemCtrlTlv[PHAL_TOP_T1T_MAX_MEM_CTRL_TLV]; /**< Memory TLV details for each TLV present */
|
||||
phalTop_T1T_LockCtrlTlv_t asLockCtrlTlv[PHAL_TOP_T1T_MAX_LOCK_CTRL_TLV]; /**< Lock TLV details for each TLV present */
|
||||
phalTop_TIT_Segment_t sSegment; /**< Current segment details */
|
||||
}phalTop_T1T_t;
|
||||
#endif /* NXPBUILD__PHAL_TOP_T1T_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP_T2T_SW
|
||||
/**
|
||||
* \brief T2T parameter structure
|
||||
*/
|
||||
typedef struct /*phalTop_T2T*/
|
||||
{
|
||||
void * pAlT2TDataParams; /**< Pointer to T2T data parameters */
|
||||
phalTop_T2T_MemCtrlTlv_t * pMemCtrlTlv; /**< Memory TLV details for each TLV present */
|
||||
phalTop_T2T_LockCtrlTlv_t * pLockCtrlTlv; /**< Lock TLV details for each TLV present */
|
||||
uint8_t bRwa; /**< Tag read/write size */
|
||||
uint8_t bTms; /**< Tag Memory size */
|
||||
uint8_t bTagMemoryType; /**< Tag memory type (static or dynamic) */
|
||||
uint8_t bLockTlvCount; /**< Number of lock TLV present in tag */
|
||||
uint8_t bMemoryTlvCount; /**< Number of memory TLV present in tag */
|
||||
uint16_t wNdefHeaderAddr; /**< Header offset of first NDEF message */
|
||||
uint16_t wNdefMsgAddr; /**< NDEF message start address */
|
||||
phalTop_T2T_Sector_t sSector; /**< Current segment details */
|
||||
uint8_t bData[16]; /**< Contains NDEF data(V) bytes along with NDEF T and L bytes, when reading 16 bytes data */
|
||||
uint16_t wStartBlockNum; /**< Parameter to obtain the block num to start reading during ReadNdef */
|
||||
uint8_t bDataIndex; /**< Num of NDEF data(V) bytes read along with NDEF T and L bytes, when reading 16 bytes data */
|
||||
uint8_t bNdefHeaderBlock[8]; /**< NDEF TLV Header block */
|
||||
|
||||
}phalTop_T2T_t;
|
||||
#endif /* NXPBUILD__PHAL_TOP_T2T_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP_T3T_SW
|
||||
/**
|
||||
* \brief T3T parameter structure
|
||||
*/
|
||||
typedef struct /*phalTop_T3T*/
|
||||
{
|
||||
void * pAlT3TDataParams; /**< Pointer to FeliCa data parameters */
|
||||
uint8_t bRwa; /**< Tag read/write access; 1 - Read/Write, 0 - Read Only */
|
||||
uint8_t bNbr; /**< Number of Blocks that can be read at one time*/
|
||||
uint8_t bNbw; /**< Number of Blocks that can be written at one time*/
|
||||
uint16_t bNmaxb; /**< Maximum number of 'Blocks * 16' available for NDEF data */
|
||||
uint8_t bUid[16]; /**< UID to address T3T */
|
||||
uint8_t bAttributeBlock[16]; /**< Contains the attribute block of the Ndef Type 3 tag */
|
||||
}phalTop_T3T_t;
|
||||
#endif /* NXPBUILD__PHAL_TOP_T3T_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP_T4T_SW
|
||||
/**
|
||||
* \brief T4T parameter structure
|
||||
*/
|
||||
typedef struct /*phalTop_T4T*/
|
||||
{
|
||||
void * pAlT4TDataParams; /**< Pointer to T4T data parameters */
|
||||
uint8_t aNdefFileID[2]; /**< NDEF File ID to Create */
|
||||
uint8_t bRa; /**< NDEF file read access condition size */
|
||||
uint8_t bWa; /**< NDEF file write access condition size */
|
||||
uint8_t bCurrentSelectedFile; /**< Current selected file */
|
||||
uint16_t wMLe; /**< MLe supported by card (obtained from CC) */
|
||||
uint16_t wMLc; /**< MLc supported by card (obtained from CC) */
|
||||
uint16_t wCCLEN; /**< Size of CCr,Valid CCLEN range 000Fh-FFFEh.*/
|
||||
uint32_t dwMaxFileSize; /**< Maximum NDEF file size in bytes */
|
||||
uint16_t wAdditionalInfo; /**< Error codes for ISO7816-4 generic errors.*/
|
||||
uint8_t bWrappedMode; /**< Wrapped APDU mode. All native commands need to be sent wrapped in ISO 7816 APDUs. */
|
||||
uint8_t aAid[3]; /**< Aid of the currently selected application */
|
||||
uint8_t * pCmdBuf; /**< Pointer to global buffer for processing the command. */
|
||||
uint8_t bCmdCode; /**< Command code. This will be used for differentiating the comman error codes between different commands. */
|
||||
uint8_t bShortLenApdu; /**< Parameter for force set Short Length APDU in case of BIG ISO read. */
|
||||
}phalTop_T4T_t;
|
||||
#endif /* NXPBUILD__PHAL_TOP_T4T_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP_T5T_SW
|
||||
/**
|
||||
* \brief T5T parameter structure
|
||||
*/
|
||||
typedef struct /*phalTop_T5T*/
|
||||
{
|
||||
void * pAlI15693DataParams; /**< Pointer to T5T data parameters */
|
||||
uint8_t bRwa; /**< Tag read/write size */
|
||||
uint8_t bTerminatorTlvPresence; /**< Terminator TLV presence; 1 -present, 0 - not present */
|
||||
uint8_t bMbRead; /**< Flag Bit for Multiple Read support */
|
||||
uint8_t bLockBlock; /**< Flag Bit for Lock Command support */
|
||||
uint8_t bSplFrm; /**< Flag Bit for special frame support */
|
||||
uint8_t bExtCmdSupt; /**< Flag Bit for Extended Command Support support */
|
||||
uint8_t bOptionFlag; /**< Option Flag PH_ON = Enable, PH_OFF = Disable */
|
||||
uint16_t wMlen; /**< Tag Memory size */
|
||||
uint16_t wNdefHeaderAddr; /**< Header offset of first NDEF message */
|
||||
uint16_t wNdefMsgAddr; /**< NDEF message start address */
|
||||
uint16_t bBlockSize; /**< T5T Block Size supported by card */
|
||||
uint16_t bMaxBlockNum; /**< Maximum Block number supported by Card */
|
||||
uint8_t bCcLength; /**< Num of blocks CC bytes spread across */
|
||||
uint8_t bCcBlockData[32]; /**< Contains CC block data if the block size is either 4 or 8 bytes and also TLV bytes if the block size is more than 8 bytes */
|
||||
uint16_t wStartBlockNum; /**< Parameter to obtain the block num to start reading during CheckNdef */
|
||||
uint16_t wCcBlockDataLen; /**< Parameter to obtain the num of CC and TLV bytes read */
|
||||
uint16_t wMaxReadLength; /**< Parameter to obtain max num of bytes that can be read in one chunk */
|
||||
}phalTop_T5T_t;
|
||||
#endif /* NXPBUILD__PHAL_TOP_T5T_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP_MFC_SW
|
||||
|
||||
/**
|
||||
* \name MIFARE Classic contactless IC Card Types
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHAL_TOP_NO_MFC 0x00U /**< No Card is selected */
|
||||
#define PHAL_TOP_MFC_1K 0x01U /**< MFC 1K is selected*/
|
||||
#define PHAL_TOP_MFC_4K 0x02U /**< MFC 4K is selected*/
|
||||
#define PHAL_TOP_MFP_2K 0x03U /**< MFP 2K is selected*/
|
||||
#define PHAL_TOP_MFP_4K 0x04U /**< MFP 4K is selected*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \brief Tag Operations parameter structure
|
||||
*/
|
||||
typedef struct /*phalTop_MfcTop*/
|
||||
{
|
||||
void * pPalI14443paDataParams; /**< Pointer to the parameter structure of the type A layer 3. */
|
||||
uint8_t bCardType; /**< Selected Card Type can be MFC1K, MFC4K, MFP2K, MFP4K */
|
||||
uint8_t bFirstNdefSector; /**< First Sector with NDEF TLV */
|
||||
uint8_t bPreFormatted; /**< Card is non default and is formatted incorrect */
|
||||
uint8_t bNdefSectorCount; /**< Count of sectors with Ndef AID present */
|
||||
uint8_t bOffset; /**< Offset Used while writing the Ndef */
|
||||
uint8_t bNdefMessageStart; /**< In a Ndef Sector the Ndef Message Starts from this byte */
|
||||
}phalTop_MfcTop_t;
|
||||
|
||||
#endif /* NXPBUILD__PHAL_TOP_MFC_SW */
|
||||
|
||||
/**
|
||||
* \brief Tag Operations parameter structure
|
||||
*/
|
||||
typedef struct /*phalTop_Sw_DataParams*/
|
||||
{
|
||||
uint16_t wId; /**< Layer ID for this component, NEVER MODIFY! */
|
||||
uint8_t bTagType; /**< Tag type */
|
||||
uint8_t bVno; /**< NDEF version number */
|
||||
uint8_t bTagState; /**< Tag state */
|
||||
uint32_t dwNdefLength; /**< NDEF message length */
|
||||
uint32_t dwMaxNdefLength; /**< Maximum supported NDEF length */
|
||||
void * pTopTagsDataParams[PHAL_TOP_MAX_TAGTYPE_SUPPORTED]; /**< Array of void pointer for Tag Types structure */
|
||||
union
|
||||
{
|
||||
#ifdef NXPBUILD__PHAL_TOP_T1T_SW
|
||||
phalTop_T1T_t salTop_T1T; /**< T1T Parameter Structure */
|
||||
#endif /* NXPBUILD__PHAL_TOP_T1T_SW*/
|
||||
#ifdef NXPBUILD__PHAL_TOP_T2T_SW
|
||||
phalTop_T2T_t salTop_T2T; /**< T2T Parameter Structure */
|
||||
#endif /* NXPBUILD__PHAL_TOP_T2T_SW*/
|
||||
#ifdef NXPBUILD__PHAL_TOP_T3T_SW
|
||||
phalTop_T3T_t salTop_T3T; /**< T3T Parameter Structure */
|
||||
#endif /* NXPBUILD__PHAL_TOP_T3T_SW */
|
||||
#ifdef NXPBUILD__PHAL_TOP_T4T_SW
|
||||
phalTop_T4T_t salTop_T4T; /**< T4T Parameter Structure */
|
||||
#endif /* NXPBUILD__PHAL_TOP_T4T_SW */
|
||||
#ifdef NXPBUILD__PHAL_TOP_T5T_SW
|
||||
phalTop_T5T_t salTop_T5T; /**< T5T Parameter Structure */
|
||||
#endif /* NXPBUILD__PHAL_TOP_T5T_SW*/
|
||||
#ifdef NXPBUILD__PHAL_TOP_MFC_SW
|
||||
phalTop_MfcTop_t salTop_MfcTop; /**< MFC as Tag Type Parameter structure */
|
||||
#endif /* NXPBUILD__PHAL_TOP_MFC_SW*/
|
||||
} ualTop;
|
||||
|
||||
}phalTop_Sw_DataParams_t;
|
||||
|
||||
/**
|
||||
* \brief Initialize this layer.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval Other Depending on error type
|
||||
*/
|
||||
phStatus_t phalTop_Sw_Init(
|
||||
phalTop_Sw_DataParams_t * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wSizeOfDataParams, /**< [In] Specifies the size of the data parameter structure. */
|
||||
void * pAlT1T, /**< Pointer to T1T data parameters */
|
||||
void * pAlMful, /**< Pointer to T2T data parameters */
|
||||
void * pAlFelica, /**< Pointer to T3T data parameters */
|
||||
void * pPalMifareDataParams, /**< Pointer to T4T data parameters */
|
||||
void * pAl15693, /**< Pointer to T5T data parameters */
|
||||
void * pPalI14443paDataParams /**< Pointer to Layer 3a data parameters */
|
||||
);
|
||||
/** @} */
|
||||
#endif /* NXPBUILD__PHAL_TOP_SW */
|
||||
|
||||
#ifdef NXPBUILD__PHAL_TOP
|
||||
|
||||
/** \defgroup phalTop Tag Operation Layer
|
||||
* \brief This Component implements tag operations for different NFC Tag types T1T, T2T, T3T,T4T and T5T.
|
||||
* To perform any operation like Read, Write, Lock, format and erase operation on the tag. The Tag should be
|
||||
* activated first as shown in the below block diagram. Any Read/Write operation is possible on the Tag only
|
||||
* if the tag is NDEF format. Refer NFC Forum Tag operation Specifications.
|
||||
*
|
||||
* \image html TOP_BlockDiagram.png
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* \name Tag types
|
||||
* \brief Tag types are used to set Tag used using \ref phalTop_SetConfig with \ref PHAL_TOP_CONFIG_TAG_TYPE Type
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHAL_TOP_TAG_TYPE_T1T_TAG 0x01U /**< Type 1 Tag. */
|
||||
#define PHAL_TOP_TAG_TYPE_T2T_TAG 0x02U /**< Type 2 Tag. */
|
||||
#define PHAL_TOP_TAG_TYPE_T3T_TAG 0x03U /**< Type 3 Tag. */
|
||||
#define PHAL_TOP_TAG_TYPE_T4T_TAG 0x04U /**< Type 4 Tag. */
|
||||
#define PHAL_TOP_TAG_TYPE_T5T_TAG 0x05U /**< Type 5 Tag. */
|
||||
#define PHAL_TOP_TAG_TYPE_MFC_TOP 0x06U /**< MFC as Tag Type */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Configuration types
|
||||
* \brief Use these Macro in \ref phalTop_SetConfig to configure Tags.
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHAL_TOP_CONFIG_TAG_TYPE 0x51U /**< Set/Get Tag type. Should be configured before calling CheckNdef. */
|
||||
#define PHAL_TOP_CONFIG_TAG_STATE 0x52U /**< Get tag state. This shall be also used to set tag to read-only state. */
|
||||
#define PHAL_TOP_CONFIG_NDEF_LENGTH 0x53U /**< Get current NDEF message Length. */
|
||||
#define PHAL_TOP_CONFIG_MAX_NDEF_LENGTH 0x54U /**< Get Max support NDEF Length by tag. */
|
||||
#define PHAL_TOP_CONFIG_NDEF_VERSION 0x55U /**< Get NDEF Version Number. This shall be also used to set NDEF Version Number. */
|
||||
|
||||
#define PHAL_TOP_CONFIG_T1T_TMS 0x03U /**< Set tag memory size. Set before format operation. */
|
||||
#define PHAL_TOP_CONFIG_T1T_TERMINATOR_TLV 0x05U /**< Set Terminator TLV presence. Set before format/write operation to enable writing terminator TLV at end of NDEF TLV. */
|
||||
|
||||
#define PHAL_TOP_CONFIG_T2T_TMS 0x09U /**< Set tag memory size. Set before format operation. */
|
||||
|
||||
#define PHAL_TOP_CONFIG_T4T_NDEF_FILE_ID 0x15U /**< Set NDEF file ID. Set before format operation. */
|
||||
#define PHAL_TOP_CONFIG_T4T_NDEF_FILE_SIZE 0x18U /**< Set Max NDEF length. Set before format operation. */
|
||||
#define PHAL_TOP_CONFIG_T4T_MLE 0x19U /**< Set/Get MLe. Set before format operation. */
|
||||
#define PHAL_TOP_CONFIG_T4T_MLC 0x1AU /**< Set/Get MLc. Set before format operation. */
|
||||
#define PHAL_TOP_CONFIG_T4T_SHORT_APDU 0x1BU /**< Set Short APDU format. Set before Read/Write NDEF operation. */
|
||||
|
||||
#define PHAL_TOP_CONFIG_T5T_MLEN 0x1DU /**< Set T5T NDEF data area. Set before format operation. */
|
||||
#define PHAL_TOP_CONFIG_T5T_MBREAD 0x20U /**< Set T5T multiple block read support. Set before format operation. */
|
||||
#define PHAL_TOP_CONFIG_T5T_LOCKBLOCK 0x21U /**< Set T5T Lock block command support. Set before format operation. */
|
||||
#define PHAL_TOP_CONFIG_T5T_SPL_FRM 0x22U /**< Set T5T special frame support. Set before format operation. */
|
||||
#define PHAL_TOP_CONFIG_T5T_OPTION_FLAG 0x26U /**< Set T5T option Flag. Set before format operation. */
|
||||
#define PHAL_TOP_CONFIG_T5T_TERMINATOR_TLV 0x1FU /**< Set Terminator TLV presence. Set before format/write operation to enable writing terminator TLV at end of NDEF TLV. */
|
||||
#define PHAL_TOP_CONFIG_T5T_MAX_READ_LENGTH 0x70U /**< Set max num of bytes that can be read in one chunk. Max value that can be set is 1024 bytes as none of the Reader IC's supports beyond 1k. */
|
||||
|
||||
#define PHAL_TOP_CONFIG_MFCTOP_CARD_TYPE 0x60U /**< Set the Card Type */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Tag States
|
||||
*/
|
||||
/*@{*/
|
||||
#define PHAL_TOP_STATE_NONE 0x00U /**< Default initial state. */
|
||||
#define PHAL_TOP_STATE_INITIALIZED 0x01U /**< Initialized state. */
|
||||
#define PHAL_TOP_STATE_READONLY 0x02U /**< Read Only state. */
|
||||
#define PHAL_TOP_STATE_READWRITE 0x04U /**< Read/Write state. */
|
||||
/*@}*/
|
||||
|
||||
#define PHAL_TOP_T1T_TAG_MEMORY_TYPE_STATIC 0x00U /**< Static memory type */
|
||||
#define PHAL_TOP_T1T_TAG_MEMORY_TYPE_DYNAMIC 0x01U /**< Dynamic memory type */
|
||||
|
||||
#define PHAL_TOP_T2T_TAG_MEMORY_TYPE_STATIC 0x00U /**< Static memory type */
|
||||
#define PHAL_TOP_T2T_TAG_MEMORY_TYPE_DYNAMIC 0x01U /**< Dynamic memory type */
|
||||
|
||||
#ifdef NXPRDLIB_REM_GEN_INTFS
|
||||
#include "../comps/phalTop/src/Sw/phalTop_Sw.h"
|
||||
|
||||
#define phalTop_ReadNdef(pDataParams, pData, pLength) \
|
||||
phalTop_Sw_ReadNdef( (phalTop_Sw_DataParams_t *)pDataParams, pData, pLength)
|
||||
|
||||
#define phalTop_WriteNdef(pDataParams, pData, pLength) \
|
||||
phalTop_Sw_WriteNdef( (phalTop_Sw_DataParams_t *)pDataParams, pData, pLength)
|
||||
|
||||
#define phalTop_CheckNdef(pDataParams, pNdefPresence) \
|
||||
phalTop_Sw_CheckNdef( (phalTop_Sw_DataParams_t *)pDataParams, pNdefPresence)
|
||||
|
||||
#define phalTop_Reset(pDataParams) \
|
||||
phalTop_Sw_Reset( (phalTop_Sw_DataParams_t *)pDataParams)
|
||||
|
||||
#define phalTop_SetConfig(pDataParams, wConfig, dwValue) \
|
||||
phalTop_Sw_SetConfig( (phalTop_Sw_DataParams_t *)pDataParams, wConfig, dwValue)
|
||||
|
||||
#define phalTop_GetConfig(pDataParams, wConfig, pValue) \
|
||||
phalTop_Sw_GetConfig( (phalTop_Sw_DataParams_t *)pDataParams, wConfig, pValue)
|
||||
|
||||
#define phalTop_EraseNdef(pDataParams) \
|
||||
phalTop_Sw_EraseNdef( (phalTop_Sw_DataParams_t *)pDataParams)
|
||||
|
||||
#define phalTop_FormatNdef(pDataParams) \
|
||||
phalTop_Sw_FormatNdef( (phalTop_Sw_DataParams_t *)pDataParams)
|
||||
|
||||
#define phalTop_LockBlock(pDataParams, wBlockNum) \
|
||||
phalTop_Sw_LockBlock( (phalTop_Sw_DataParams_t *)pDataParams, wBlockNum)
|
||||
|
||||
#else
|
||||
|
||||
/**
|
||||
* \brief Format a new non-NDEF tag as NDEF tag.
|
||||
*
|
||||
* FormatNdef shall be used for formatting a non-NDEF tag as NDEF tag if needed
|
||||
* when CheckNdef returns error. Before formatting, tag parameters like max. NDEF
|
||||
* size etc., shall be specified by the application. If not specified tag will be
|
||||
* formatted with default values. FormatNdef shall be called only once for a tag.
|
||||
* Once formatted, tag will become a NDEF tag. To remove NDEF format if needed,
|
||||
* application needs to over write / delete NDEF format using tag specific
|
||||
* read/write commands.
|
||||
*
|
||||
* This is only a utility function not specified by NFC Forum.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PHAL_TOP_ERR_UNSUPPORTED_TAG Tag does not support NDEF formatting.
|
||||
* \retval #PHAL_TOP_ERR_FORMATTED_TAG Tag is already NDEF formatted.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phalTop_FormatNdef(
|
||||
void * pDataParams /**< [In] Pointer to this layer's parameter structure. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Read NDEF message from Tag.
|
||||
*
|
||||
* ReadNdef shall only be called after CheckNdef returned success.
|
||||
* If it is an empty NDEF message(i.e. initialized state) then this will return
|
||||
* empty NDEF error.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PHAL_TOP_ERR_INVALID_STATE Tag is not is any valid state (i.e. when check NDEF failed or has not been called before.)
|
||||
* \retval #PHAL_TOP_ERR_EMPTY_NDEF Tag is in initialized state (i.e. no NDEF / empty NDEF)
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*
|
||||
* Note: In case of T4T Tag, if read MLe value is greater than HAL Receive buffer size of frame size supported by Reader IC,
|
||||
* then MLe value need to be configured using \ref phalTop_SetConfig with \ref PHAL_TOP_CONFIG_T4T_MLE Type.
|
||||
* If not, ReadNDEF throws #PH_ERR_BUFFER_OVERFLOW error if MLe value is greater than HAL Receive buffer allocation or
|
||||
* frame supported by Reader IC.
|
||||
*/
|
||||
phStatus_t phalTop_ReadNdef(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t * pData, /**< [Out] NDEF data from the Tag. User has to allocate memory accordingly */
|
||||
uint32_t * pLength /**< [Out] NDEF data length. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Write NDEF message into Tag.
|
||||
*
|
||||
* WriteNdef shall be used to write a new NDEF message to tag if check NDEF
|
||||
* returned success. If tag is in read only state, write NDEF will return error.
|
||||
* The tag is expected to be a formatted NDEF tag for this to succeed.
|
||||
*
|
||||
* WriteNDEF will update the NDEF message TLV or the capability container with
|
||||
* the length of the data written to the tag.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_INVALID_PARAMETER dwLength is 0 or dwLength is more than supported max length.
|
||||
* \retval #PHAL_TOP_ERR_INVALID_STATE Tag is not is any valid state (i.e. when check NDEF failed).
|
||||
* \retval #PHAL_TOP_ERR_READONLY_TAG Tag is in read only state.
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*
|
||||
* Note: In case of T4T Tag, if read MLc value is greater than HAL Transmit buffer size of frame size supported by Reader IC,
|
||||
* then MLc value need to be configured using \ref phalTop_SetConfig with \ref PHAL_TOP_CONFIG_T4T_MLC Type.
|
||||
* If not, WriteNDEF throws #PH_ERR_BUFFER_OVERFLOW error if MLc value is greater than HAL Transmit buffer allocation or
|
||||
* frame supported by Reader IC.
|
||||
*/
|
||||
phStatus_t phalTop_WriteNdef(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t * pData, /**< [In] NDEF data to be written to tag. User has to allocate memory accordingly */
|
||||
uint32_t dwLength /**< [In] Length of NDEF data to be written. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Does the NDEF detection procedure as per NFC Tag Operation
|
||||
* specifications for each tag type.
|
||||
*
|
||||
* The caller has to ensure that Tag activation is done before calling this API.
|
||||
* Also \ref phalTop_SetConfig should be called before to configure the Tag type
|
||||
* #PHAL_TOP_CONFIG_TAG_TYPE. For MIFARE Classic as tag type \ref phalTop_SetConfig needs to be called
|
||||
* to configure the MIFARE Classic IC-based contactless card type #PHAL_TOP_CONFIG_MFCTOP_CARD_TYPE e.g. #PHAL_TOP_MFC_1K.
|
||||
* Only after phalTop_CheckNdef is called any other
|
||||
* NDEF operation on Tag can be performed.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PHAL_TOP_ERR_NON_NDEF_TAG Tag don't indicate NDEF presence
|
||||
* \retval #PHAL_TOP_ERR_UNSUPPORTED_VERSION Tag indicates NDEF presence but NDEF version mentioned in tag is not supported by reader library.
|
||||
* \retval #PHAL_TOP_ERR_MISCONFIGURED_TAG Tag indicates NDEF presence but the NDEF CC or NDEF attribute information is wrongly configured
|
||||
* \retval #PHAL_TOP_ERR_UNSUPPORTED_TAG Tag uses some proprietary or RFU or unsupported configuration
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phalTop_CheckNdef(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t * pTagState /**< [Out] State of tag */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Reset Tag Operation parameters
|
||||
*
|
||||
* User has to call phalTop_Reset to reset all the Software parameters. This shall
|
||||
* be called after performing all NDEF operations if needed.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
*/
|
||||
phStatus_t phalTop_Reset(
|
||||
void * pDataParams /**< [In] Pointer to this layer's parameter structure. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Erase a valid NDEF message with an empty NDEF.
|
||||
*
|
||||
* EraseNdef shall be used to erase a valid NDEF message by writing an empty NDEF
|
||||
* (i.e. NDEF length as 0) to tag. This will change the tag from read/write state to
|
||||
* initialized state. If tag is already in initialized state this API will return error.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PHAL_TOP_ERR_INVALID_STATE Tag is not is any valid state (i.e. when check NDEF failed)
|
||||
* \retval #PHAL_TOP_ERR_READONLY_TAG Tag is in read only state.
|
||||
* \retval #PHAL_TOP_ERR_EMPTY_NDEF Tag is in initialized state (i.e. no NDEF / empty NDEF)
|
||||
* \retval Other Depending on implementation and underlying component.
|
||||
*/
|
||||
phStatus_t phalTop_EraseNdef(
|
||||
void * pDataParams /**< [In] Pointer to this layer's parameter structure. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Set configuration parameter.
|
||||
* Refer to #PHAL_TOP_CONFIG_TAG_TYPE from where the configurable parameters are listed.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_INVALID_PARAMETER Parameter value is invalid.
|
||||
*/
|
||||
phStatus_t phalTop_SetConfig(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wConfig, /**< [In] Configuration Identifier. */
|
||||
uint32_t dwValue /**< [In] Configuration Value. */
|
||||
);
|
||||
|
||||
/**
|
||||
* \brief Get configuration parameter.
|
||||
*
|
||||
* After calling \ref phalTop_CheckNdef, \ref phalTop_WriteNdef, \ref phalTop_ReadNdef
|
||||
* or \ref phalTop_EraseNdef, user can call phalTop_GetConfig to get different
|
||||
* parameters.
|
||||
*
|
||||
* Refer to #PHAL_TOP_CONFIG_TAG_TYPE from where the configurable parameters are listed.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_INVALID_PARAMETER Parameter value is invalid.
|
||||
*/
|
||||
phStatus_t phalTop_GetConfig(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wConfig, /**< [In] Configuration Identifier. */
|
||||
uint32_t * pValue /**< [Out] Configuration Value. */
|
||||
);
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \brief Lock the specified block of T5T tag memory.
|
||||
*
|
||||
* After calling \ref phalTop_CheckNdef, user can call phalTop_LockBlock to Lock the specified block of T5T tag memory.
|
||||
*
|
||||
* NOTE: This functionality is only applicable to T5T Tag Operations.
|
||||
*
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
* \retval #PH_ERR_INVALID_PARAMETER Parameter value is invalid.
|
||||
* \retval #PH_ERR_UNSUPPORTED_COMMAND Tag type is not T5T.
|
||||
*/
|
||||
phStatus_t phalTop_LockBlock(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint16_t wBlockNum /**< [In] Block number to be locked. */
|
||||
);
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* NXPRDLIB_REM_GEN_INTFS */
|
||||
|
||||
#endif /* NXPBUILD__PHAL_TOP */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* Extern C */
|
||||
#endif
|
||||
|
||||
#ifdef __DEBUG
|
||||
/* This API would be available only for debugging purpose and test bench */
|
||||
/**
|
||||
* \brief Assigns the component data parameter to one of the filed in
|
||||
* T1T parameter based on the option
|
||||
*
|
||||
* \return Error code
|
||||
* \retval #PH_ERR_INVALID_PARAMTER If invalid option was passed
|
||||
* \retval #PH_ERR_SUCCESS on success
|
||||
*
|
||||
*/
|
||||
phStatus_t phalTop_SetPtr(
|
||||
void * pDataParams, /**< [In] Pointer to this layer's parameter structure */
|
||||
void * pT1T, /**< [In] Pointer to Tag Type 1 parameter structure */
|
||||
void * pT2T, /**< [In] Pointer to Tag Type 2 parameter structure */
|
||||
void * pT3T, /**< [In] Pointer to Tag Type 3 parameter structure */
|
||||
void * pT4T, /**< [In] Pointer to Tag Type 4 parameter structure */
|
||||
void * pT5T, /**< [In] Pointer to Tag Type 5 parameter structure */
|
||||
void * pMfcTop /**< [In] Pointer to Tag Type MFC parameter structure */
|
||||
);
|
||||
#endif /* __DEBUG */
|
||||
|
||||
#endif /* PHALTOP_H */
|
||||
@ -0,0 +1,167 @@
|
||||
/*
|
||||
* @brief Common ring buffer support functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2012
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include "ring_buffer.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
#define RB_INDH(rb) ((rb)->head & ((rb)->count - 1))
|
||||
#define RB_INDT(rb) ((rb)->tail & ((rb)->count - 1))
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Initialize ring buffer */
|
||||
int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count)
|
||||
{
|
||||
RingBuff->data = buffer;
|
||||
RingBuff->count = count;
|
||||
RingBuff->itemSz = itemSize;
|
||||
RingBuff->head = RingBuff->tail = 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Insert a single item into Ring Buffer */
|
||||
int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data)
|
||||
{
|
||||
uint8_t *ptr = RingBuff->data;
|
||||
|
||||
/* We cannot insert when queue is full */
|
||||
if (RingBuffer_IsFull(RingBuff))
|
||||
return 0;
|
||||
|
||||
ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
|
||||
memcpy(ptr, data, RingBuff->itemSz);
|
||||
RingBuff->head++;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Insert multiple items into Ring Buffer */
|
||||
int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num)
|
||||
{
|
||||
uint8_t *ptr = RingBuff->data;
|
||||
int cnt1, cnt2;
|
||||
|
||||
/* We cannot insert when queue is full */
|
||||
if (RingBuffer_IsFull(RingBuff))
|
||||
return 0;
|
||||
|
||||
/* Calculate the segment lengths */
|
||||
cnt1 = cnt2 = RingBuffer_GetFree(RingBuff);
|
||||
if (RB_INDH(RingBuff) + cnt1 >= RingBuff->count)
|
||||
cnt1 = RingBuff->count - RB_INDH(RingBuff);
|
||||
cnt2 -= cnt1;
|
||||
|
||||
cnt1 = MIN(cnt1, num);
|
||||
num -= cnt1;
|
||||
|
||||
cnt2 = MIN(cnt2, num);
|
||||
num -= cnt2;
|
||||
|
||||
/* Write segment 1 */
|
||||
ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
|
||||
memcpy(ptr, data, cnt1 * RingBuff->itemSz);
|
||||
RingBuff->head += cnt1;
|
||||
|
||||
/* Write segment 2 */
|
||||
ptr = (uint8_t *) RingBuff->data + RB_INDH(RingBuff) * RingBuff->itemSz;
|
||||
data = (const uint8_t *) data + cnt1 * RingBuff->itemSz;
|
||||
memcpy(ptr, data, cnt2 * RingBuff->itemSz);
|
||||
RingBuff->head += cnt2;
|
||||
|
||||
return cnt1 + cnt2;
|
||||
}
|
||||
|
||||
/* Pop single item from Ring Buffer */
|
||||
int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data)
|
||||
{
|
||||
uint8_t *ptr = RingBuff->data;
|
||||
|
||||
/* We cannot pop when queue is empty */
|
||||
if (RingBuffer_IsEmpty(RingBuff))
|
||||
return 0;
|
||||
|
||||
ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
|
||||
memcpy(data, ptr, RingBuff->itemSz);
|
||||
RingBuff->tail++;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Pop multiple items from Ring buffer */
|
||||
int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num)
|
||||
{
|
||||
uint8_t *ptr = RingBuff->data;
|
||||
int cnt1, cnt2;
|
||||
|
||||
/* We cannot insert when queue is empty */
|
||||
if (RingBuffer_IsEmpty(RingBuff))
|
||||
return 0;
|
||||
|
||||
/* Calculate the segment lengths */
|
||||
cnt1 = cnt2 = RingBuffer_GetCount(RingBuff);
|
||||
if (RB_INDT(RingBuff) + cnt1 >= RingBuff->count)
|
||||
cnt1 = RingBuff->count - RB_INDT(RingBuff);
|
||||
cnt2 -= cnt1;
|
||||
|
||||
cnt1 = MIN(cnt1, num);
|
||||
num -= cnt1;
|
||||
|
||||
cnt2 = MIN(cnt2, num);
|
||||
num -= cnt2;
|
||||
|
||||
/* Write segment 1 */
|
||||
ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
|
||||
memcpy(data, ptr, cnt1 * RingBuff->itemSz);
|
||||
RingBuff->tail += cnt1;
|
||||
|
||||
/* Write segment 2 */
|
||||
ptr = (uint8_t *) RingBuff->data + RB_INDT(RingBuff) * RingBuff->itemSz;
|
||||
data = (uint8_t *) data + cnt1 * RingBuff->itemSz;
|
||||
memcpy(data, ptr, cnt2 * RingBuff->itemSz);
|
||||
RingBuff->tail += cnt2;
|
||||
|
||||
return cnt1 + cnt2;
|
||||
}
|
||||
@ -0,0 +1,137 @@
|
||||
/*
|
||||
* @brief Common stopwatch support
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2013
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __STOPWATCH_H_
|
||||
#define __STOPWATCH_H_
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
/** @defgroup Stop_Watch CHIP: Stopwatch primitives.
|
||||
* @ingroup CHIP_Common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize stopwatch
|
||||
* @return Nothing
|
||||
*/
|
||||
void StopWatch_Init(void);
|
||||
|
||||
/**
|
||||
* @brief Start a stopwatch
|
||||
* @return Current cycle count
|
||||
*/
|
||||
uint32_t StopWatch_Start(void);
|
||||
|
||||
/**
|
||||
* @brief Returns number of ticks elapsed since stopwatch was started
|
||||
* @param startTime : Time returned by StopWatch_Start().
|
||||
* @return Number of ticks elapsed since stopwatch was started
|
||||
*/
|
||||
STATIC INLINE uint32_t StopWatch_Elapsed(uint32_t startTime)
|
||||
{
|
||||
return StopWatch_Start() - startTime;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns number of ticks per second of the stopwatch timer
|
||||
* @return Number of ticks per second of the stopwatch timer
|
||||
*/
|
||||
uint32_t StopWatch_TicksPerSecond(void);
|
||||
|
||||
/**
|
||||
* @brief Converts from stopwatch ticks to mS.
|
||||
* @param ticks : Duration in ticks to convert to mS.
|
||||
* @return Number of mS in given number of ticks
|
||||
*/
|
||||
uint32_t StopWatch_TicksToMs(uint32_t ticks);
|
||||
|
||||
/**
|
||||
* @brief Converts from stopwatch ticks to uS.
|
||||
* @param ticks : Duration in ticks to convert to uS.
|
||||
* @return Number of uS in given number of ticks
|
||||
*/
|
||||
uint32_t StopWatch_TicksToUs(uint32_t ticks);
|
||||
|
||||
/**
|
||||
* @brief Converts from mS to stopwatch ticks.
|
||||
* @param mS : Duration in mS to convert to ticks.
|
||||
* @return Number of ticks in given number of mS
|
||||
*/
|
||||
uint32_t StopWatch_MsToTicks(uint32_t mS);
|
||||
|
||||
/**
|
||||
* @brief Converts from uS to stopwatch ticks.
|
||||
* @param uS : Duration in uS to convert to ticks.
|
||||
* @return Number of ticks in given number of uS
|
||||
*/
|
||||
uint32_t StopWatch_UsToTicks(uint32_t uS);
|
||||
|
||||
/**
|
||||
* @brief Delays the given number of ticks using stopwatch primitives
|
||||
* @param ticks : Number of ticks to delay
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void StopWatch_DelayTicks(uint32_t ticks)
|
||||
{
|
||||
uint32_t startTime = StopWatch_Start();
|
||||
while (StopWatch_Elapsed(startTime) < ticks) {}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Delays the given number of mS using stopwatch primitives
|
||||
* @param mS : Number of mS to delay
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void StopWatch_DelayMs(uint32_t mS)
|
||||
{
|
||||
uint32_t ticks = StopWatch_MsToTicks(mS);
|
||||
uint32_t startTime = StopWatch_Start();
|
||||
while (StopWatch_Elapsed(startTime) < ticks) {}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Delays the given number of uS using stopwatch primitives
|
||||
* @param uS : Number of uS to delay
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void StopWatch_DelayUs(uint32_t uS)
|
||||
{
|
||||
uint32_t ticks = StopWatch_UsToTicks(uS);
|
||||
uint32_t startTime = StopWatch_Start();
|
||||
while (StopWatch_Elapsed(startTime) < ticks) {}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __STOPWATCH_H_ */
|
||||
@ -0,0 +1,362 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.5.0
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "croutine.h"
|
||||
|
||||
/* Remove the whole file is co-routines are not being used. */
|
||||
#if ( configUSE_CO_ROUTINES != 0 )
|
||||
|
||||
/*
|
||||
* Some kernel aware debuggers require data to be viewed to be global, rather
|
||||
* than file scope.
|
||||
*/
|
||||
#ifdef portREMOVE_STATIC_QUALIFIER
|
||||
#define static
|
||||
#endif
|
||||
|
||||
/* Lists for ready and blocked co-routines. --------------------*/
|
||||
static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */
|
||||
static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */
|
||||
static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
|
||||
static List_t * pxDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used. */
|
||||
static List_t * pxOverflowDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
|
||||
static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
|
||||
|
||||
/* Other file private variables. --------------------------------*/
|
||||
CRCB_t * pxCurrentCoRoutine = NULL;
|
||||
static UBaseType_t uxTopCoRoutineReadyPriority = 0;
|
||||
static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
|
||||
|
||||
/* The initial state of the co-routine when it is created. */
|
||||
#define corINITIAL_STATE ( 0 )
|
||||
|
||||
/*
|
||||
* Place the co-routine represented by pxCRCB into the appropriate ready queue
|
||||
* for the priority. It is inserted at the end of the list.
|
||||
*
|
||||
* This macro accesses the co-routine ready lists and therefore must not be
|
||||
* used from within an ISR.
|
||||
*/
|
||||
#define prvAddCoRoutineToReadyQueue( pxCRCB ) \
|
||||
{ \
|
||||
if( ( pxCRCB )->uxPriority > uxTopCoRoutineReadyPriority ) \
|
||||
{ \
|
||||
uxTopCoRoutineReadyPriority = ( pxCRCB )->uxPriority; \
|
||||
} \
|
||||
vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ ( pxCRCB )->uxPriority ] ), &( ( pxCRCB )->xGenericListItem ) ); \
|
||||
}
|
||||
|
||||
/*
|
||||
* Utility to ready all the lists used by the scheduler. This is called
|
||||
* automatically upon the creation of the first co-routine.
|
||||
*/
|
||||
static void prvInitialiseCoRoutineLists( void );
|
||||
|
||||
/*
|
||||
* Co-routines that are readied by an interrupt cannot be placed directly into
|
||||
* the ready lists (there is no mutual exclusion). Instead they are placed in
|
||||
* in the pending ready list in order that they can later be moved to the ready
|
||||
* list by the co-routine scheduler.
|
||||
*/
|
||||
static void prvCheckPendingReadyList( void );
|
||||
|
||||
/*
|
||||
* Macro that looks at the list of co-routines that are currently delayed to
|
||||
* see if any require waking.
|
||||
*
|
||||
* Co-routines are stored in the queue in the order of their wake time -
|
||||
* meaning once one co-routine has been found whose timer has not expired
|
||||
* we need not look any further down the list.
|
||||
*/
|
||||
static void prvCheckDelayedList( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
|
||||
UBaseType_t uxPriority,
|
||||
UBaseType_t uxIndex )
|
||||
{
|
||||
BaseType_t xReturn;
|
||||
CRCB_t * pxCoRoutine;
|
||||
|
||||
/* Allocate the memory that will store the co-routine control block. */
|
||||
pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
|
||||
|
||||
if( pxCoRoutine )
|
||||
{
|
||||
/* If pxCurrentCoRoutine is NULL then this is the first co-routine to
|
||||
* be created and the co-routine data structures need initialising. */
|
||||
if( pxCurrentCoRoutine == NULL )
|
||||
{
|
||||
pxCurrentCoRoutine = pxCoRoutine;
|
||||
prvInitialiseCoRoutineLists();
|
||||
}
|
||||
|
||||
/* Check the priority is within limits. */
|
||||
if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
|
||||
{
|
||||
uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
|
||||
}
|
||||
|
||||
/* Fill out the co-routine control block from the function parameters. */
|
||||
pxCoRoutine->uxState = corINITIAL_STATE;
|
||||
pxCoRoutine->uxPriority = uxPriority;
|
||||
pxCoRoutine->uxIndex = uxIndex;
|
||||
pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
|
||||
|
||||
/* Initialise all the other co-routine control block parameters. */
|
||||
vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
|
||||
vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
|
||||
|
||||
/* Set the co-routine control block as a link back from the ListItem_t.
|
||||
* This is so we can get back to the containing CRCB from a generic item
|
||||
* in a list. */
|
||||
listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
|
||||
listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
|
||||
|
||||
/* Event lists are always in priority order. */
|
||||
listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
|
||||
|
||||
/* Now the co-routine has been initialised it can be added to the ready
|
||||
* list at the correct priority. */
|
||||
prvAddCoRoutineToReadyQueue( pxCoRoutine );
|
||||
|
||||
xReturn = pdPASS;
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
|
||||
List_t * pxEventList )
|
||||
{
|
||||
TickType_t xTimeToWake;
|
||||
|
||||
/* Calculate the time to wake - this may overflow but this is
|
||||
* not a problem. */
|
||||
xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
|
||||
|
||||
/* We must remove ourselves from the ready list before adding
|
||||
* ourselves to the blocked list as the same list item is used for
|
||||
* both lists. */
|
||||
( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
|
||||
|
||||
/* The list item will be inserted in wake time order. */
|
||||
listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
|
||||
|
||||
if( xTimeToWake < xCoRoutineTickCount )
|
||||
{
|
||||
/* Wake time has overflowed. Place this item in the
|
||||
* overflow list. */
|
||||
vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The wake time has not overflowed, so we can use the
|
||||
* current block list. */
|
||||
vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
|
||||
}
|
||||
|
||||
if( pxEventList )
|
||||
{
|
||||
/* Also add the co-routine to an event list. If this is done then the
|
||||
* function must be called with interrupts disabled. */
|
||||
vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvCheckPendingReadyList( void )
|
||||
{
|
||||
/* Are there any co-routines waiting to get moved to the ready list? These
|
||||
* are co-routines that have been readied by an ISR. The ISR cannot access
|
||||
* the ready lists itself. */
|
||||
while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
|
||||
{
|
||||
CRCB_t * pxUnblockedCRCB;
|
||||
|
||||
/* The pending ready list can be accessed by an ISR. */
|
||||
portDISABLE_INTERRUPTS();
|
||||
{
|
||||
pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) );
|
||||
( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
|
||||
}
|
||||
portENABLE_INTERRUPTS();
|
||||
|
||||
( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
|
||||
prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvCheckDelayedList( void )
|
||||
{
|
||||
CRCB_t * pxCRCB;
|
||||
|
||||
xPassedTicks = xTaskGetTickCount() - xLastTickCount;
|
||||
|
||||
while( xPassedTicks )
|
||||
{
|
||||
xCoRoutineTickCount++;
|
||||
xPassedTicks--;
|
||||
|
||||
/* If the tick count has overflowed we need to swap the ready lists. */
|
||||
if( xCoRoutineTickCount == 0 )
|
||||
{
|
||||
List_t * pxTemp;
|
||||
|
||||
/* Tick count has overflowed so we need to swap the delay lists. If there are
|
||||
* any items in pxDelayedCoRoutineList here then there is an error! */
|
||||
pxTemp = pxDelayedCoRoutineList;
|
||||
pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
|
||||
pxOverflowDelayedCoRoutineList = pxTemp;
|
||||
}
|
||||
|
||||
/* See if this tick has made a timeout expire. */
|
||||
while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
|
||||
{
|
||||
pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
|
||||
|
||||
if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
|
||||
{
|
||||
/* Timeout not yet expired. */
|
||||
break;
|
||||
}
|
||||
|
||||
portDISABLE_INTERRUPTS();
|
||||
{
|
||||
/* The event could have occurred just before this critical
|
||||
* section. If this is the case then the generic list item will
|
||||
* have been moved to the pending ready list and the following
|
||||
* line is still valid. Also the pvContainer parameter will have
|
||||
* been set to NULL so the following lines are also valid. */
|
||||
( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
|
||||
|
||||
/* Is the co-routine waiting on an event also? */
|
||||
if( pxCRCB->xEventListItem.pxContainer )
|
||||
{
|
||||
( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
|
||||
}
|
||||
}
|
||||
portENABLE_INTERRUPTS();
|
||||
|
||||
prvAddCoRoutineToReadyQueue( pxCRCB );
|
||||
}
|
||||
}
|
||||
|
||||
xLastTickCount = xCoRoutineTickCount;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vCoRoutineSchedule( void )
|
||||
{
|
||||
/* Only run a co-routine after prvInitialiseCoRoutineLists() has been
|
||||
* called. prvInitialiseCoRoutineLists() is called automatically when a
|
||||
* co-routine is created. */
|
||||
if( pxDelayedCoRoutineList != NULL )
|
||||
{
|
||||
/* See if any co-routines readied by events need moving to the ready lists. */
|
||||
prvCheckPendingReadyList();
|
||||
|
||||
/* See if any delayed co-routines have timed out. */
|
||||
prvCheckDelayedList();
|
||||
|
||||
/* Find the highest priority queue that contains ready co-routines. */
|
||||
while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
|
||||
{
|
||||
if( uxTopCoRoutineReadyPriority == 0 )
|
||||
{
|
||||
/* No more co-routines to check. */
|
||||
return;
|
||||
}
|
||||
|
||||
--uxTopCoRoutineReadyPriority;
|
||||
}
|
||||
|
||||
/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
|
||||
* of the same priority get an equal share of the processor time. */
|
||||
listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
|
||||
|
||||
/* Call the co-routine. */
|
||||
( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvInitialiseCoRoutineLists( void )
|
||||
{
|
||||
UBaseType_t uxPriority;
|
||||
|
||||
for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
|
||||
{
|
||||
vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
|
||||
}
|
||||
|
||||
vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
|
||||
vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
|
||||
vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
|
||||
|
||||
/* Start with pxDelayedCoRoutineList using list1 and the
|
||||
* pxOverflowDelayedCoRoutineList using list2. */
|
||||
pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
|
||||
pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList )
|
||||
{
|
||||
CRCB_t * pxUnblockedCRCB;
|
||||
BaseType_t xReturn;
|
||||
|
||||
/* This function is called from within an interrupt. It can only access
|
||||
* event lists and the pending ready list. This function assumes that a
|
||||
* check has already been made to ensure pxEventList is not empty. */
|
||||
pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
|
||||
( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
|
||||
vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
|
||||
|
||||
if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
|
||||
{
|
||||
xReturn = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = pdFALSE;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
#endif /* configUSE_CO_ROUTINES == 0 */
|
||||
@ -0,0 +1,114 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.5.0
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PORT_ASM_H__
|
||||
#define __PORT_ASM_H__
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
|
||||
/* MPU wrappers includes. */
|
||||
#include "mpu_wrappers.h"
|
||||
|
||||
/**
|
||||
* @brief Restore the context of the first task so that the first task starts
|
||||
* executing.
|
||||
*/
|
||||
void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/**
|
||||
* @brief Checks whether or not the processor is privileged.
|
||||
*
|
||||
* @return 1 if the processor is already privileged, 0 otherwise.
|
||||
*/
|
||||
BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
|
||||
|
||||
/**
|
||||
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
|
||||
* register.
|
||||
*
|
||||
* @note This is a privileged function and should only be called from the kenrel
|
||||
* code.
|
||||
*
|
||||
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
|
||||
* Bit[0] = 0 --> The processor is running privileged
|
||||
* Bit[0] = 1 --> The processor is running unprivileged.
|
||||
*/
|
||||
void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/**
|
||||
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
|
||||
* register.
|
||||
*
|
||||
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
|
||||
* Bit[0] = 0 --> The processor is running privileged
|
||||
* Bit[0] = 1 --> The processor is running unprivileged.
|
||||
*/
|
||||
void vResetPrivilege( void ) __attribute__( ( naked ) );
|
||||
|
||||
/**
|
||||
* @brief Starts the first task.
|
||||
*/
|
||||
void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/**
|
||||
* @brief Disables interrupts.
|
||||
*/
|
||||
uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/**
|
||||
* @brief Enables interrupts.
|
||||
*/
|
||||
void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/**
|
||||
* @brief PendSV Exception handler.
|
||||
*/
|
||||
void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/**
|
||||
* @brief SVC Handler.
|
||||
*/
|
||||
void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/**
|
||||
* @brief Allocate a Secure context for the calling task.
|
||||
*
|
||||
* @param[in] ulSecureStackSize The size of the stack to be allocated on the
|
||||
* secure side for the calling task.
|
||||
*/
|
||||
void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
|
||||
|
||||
/**
|
||||
* @brief Free the task's secure context.
|
||||
*
|
||||
* @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
|
||||
*/
|
||||
void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
|
||||
|
||||
#endif /* __PORT_ASM_H__ */
|
||||
@ -0,0 +1,744 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2009,2020,2022 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Generic Tools Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* CHu: Generated 19. May 2009
|
||||
*
|
||||
*/
|
||||
|
||||
#include <phTools.h>
|
||||
#include <ph_RefDefs.h>
|
||||
#include <NxpNfcRdLib_Ver.h>
|
||||
|
||||
#ifdef _WIN32
|
||||
#pragma warning(push) /* PRQA S 3116 */
|
||||
#pragma warning(disable:4001) /* PRQA S 3116 */
|
||||
#include <stdlib.h>
|
||||
#include <string.h> /* memcpy */
|
||||
#pragma warning(pop) /* PRQA S 3116 */
|
||||
#else
|
||||
#include <string.h> /* memcpy */
|
||||
#endif
|
||||
|
||||
static uint8_t phTools_CalcParity(uint8_t bDataByte, uint8_t bOption);
|
||||
|
||||
phStatus_t phTools_EncodeParity(
|
||||
uint8_t bOption,
|
||||
uint8_t * pInBuffer,
|
||||
uint16_t wInBufferLength,
|
||||
uint8_t bInBufferBits,
|
||||
uint16_t wOutBufferSize,
|
||||
uint8_t * pOutBuffer,
|
||||
uint16_t * pOutBufferLength,
|
||||
uint8_t * pOutBufferBits
|
||||
)
|
||||
{
|
||||
uint16_t PH_MEMLOC_REM wByteIndexIn;
|
||||
uint16_t PH_MEMLOC_REM wByteIndexOut;
|
||||
uint8_t PH_MEMLOC_REM bBitPosition;
|
||||
uint16_t PH_MEMLOC_REM wInByteCount;
|
||||
|
||||
/* Parameter check */
|
||||
if (((bOption != PH_TOOLS_PARITY_OPTION_EVEN) && (bOption != PH_TOOLS_PARITY_OPTION_ODD)) || (bInBufferBits > 7U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
/* Retrieve full input byte count */
|
||||
if (bInBufferBits == 0U)
|
||||
{
|
||||
wInByteCount = wInBufferLength;
|
||||
}
|
||||
else
|
||||
{
|
||||
wInByteCount = wInBufferLength - 1u;
|
||||
}
|
||||
|
||||
/* Retrieve number of (additional) full bytes */
|
||||
(*pOutBufferLength) = (uint16_t)((uint16_t)(wInByteCount + bInBufferBits) >> 3U);
|
||||
|
||||
/* Retrieve output bits */
|
||||
*pOutBufferBits = (uint8_t)((uint16_t)(wInByteCount + bInBufferBits) % 8U);
|
||||
|
||||
/* Increment output length in case of incomplete byte */
|
||||
if (*pOutBufferBits > 0U)
|
||||
{
|
||||
++(*pOutBufferLength);
|
||||
}
|
||||
|
||||
/* Overflow check */
|
||||
if ((*pOutBufferLength) > (0xFFFFU - wInByteCount))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
/* Calculate number of output bytes */
|
||||
(*pOutBufferLength) = wInByteCount + (*pOutBufferLength);
|
||||
|
||||
/* Buffer overflow check*/
|
||||
if (wOutBufferSize < (*pOutBufferLength))
|
||||
{
|
||||
(*pOutBufferLength) = 0;
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_BUFFER_OVERFLOW, PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
/* Prepare output buffer */
|
||||
pOutBuffer[0] = 0x00;
|
||||
|
||||
/* Prepare loop vars */
|
||||
wByteIndexIn = 0;
|
||||
wByteIndexOut = 0;
|
||||
bBitPosition = 7;
|
||||
|
||||
/* Do for each byte */
|
||||
for (; wByteIndexIn < wInBufferLength; ++wByteIndexIn )
|
||||
{
|
||||
/* Append source bits to output */
|
||||
pOutBuffer[wByteIndexOut] |= (uint8_t)(pInBuffer[wByteIndexIn] << (7U - bBitPosition));
|
||||
|
||||
/* If there is more data bits in the sourcebyte append it to next data byte */
|
||||
if ((wByteIndexOut + 1U) < (*pOutBufferLength))
|
||||
{
|
||||
if(bBitPosition == 7U)
|
||||
{
|
||||
pOutBuffer[wByteIndexOut + 1U] = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
pOutBuffer[wByteIndexOut + 1U] = (uint8_t)(pInBuffer[wByteIndexIn] >> (1u + bBitPosition));
|
||||
}
|
||||
|
||||
/* Perform parity appending if this isn't an incomplete byte */
|
||||
if ((bInBufferBits == 0U) || ((wByteIndexIn + 1U) < wInBufferLength))
|
||||
{
|
||||
pOutBuffer[wByteIndexOut + 1U] |= (uint8_t)(phTools_CalcParity(pInBuffer[wByteIndexIn], bOption) << (7U - bBitPosition));
|
||||
}
|
||||
}
|
||||
|
||||
/* We have reached the 8th parity bit, the output buffer index is now one ahead */
|
||||
if (bBitPosition == 0U)
|
||||
{
|
||||
if ((wByteIndexOut + 2U) < (*pOutBufferLength))
|
||||
{
|
||||
bBitPosition = 8;
|
||||
pOutBuffer[++wByteIndexOut + 1U] = 0x00;
|
||||
}
|
||||
}
|
||||
|
||||
++wByteIndexOut;
|
||||
--bBitPosition;
|
||||
}
|
||||
|
||||
/* Mask out invalid bits of last byte */
|
||||
if (*pOutBufferBits > 0U)
|
||||
{
|
||||
pOutBuffer[(*pOutBufferLength) - 1U] &= (uint8_t)(0xFFU >> (8U - *pOutBufferBits));
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phTools_DecodeParity(
|
||||
uint8_t bOption,
|
||||
uint8_t * pInBuffer,
|
||||
uint16_t wInBufferLength,
|
||||
uint8_t bInBufferBits,
|
||||
uint16_t wOutBufferSize,
|
||||
uint8_t * pOutBuffer,
|
||||
uint16_t * pOutBufferLength,
|
||||
uint8_t * pOutBufferBits
|
||||
)
|
||||
{
|
||||
uint16_t PH_MEMLOC_REM wByteIndexIn;
|
||||
uint16_t PH_MEMLOC_REM wByteIndexOut;
|
||||
uint8_t PH_MEMLOC_REM bBitPosition;
|
||||
uint16_t PH_MEMLOC_REM wDiv;
|
||||
uint8_t PH_MEMLOC_REM bMod;
|
||||
uint8_t PH_MEMLOC_REM bParity;
|
||||
|
||||
/* Parameter check */
|
||||
if (((bOption != PH_TOOLS_PARITY_OPTION_EVEN) && (bOption != PH_TOOLS_PARITY_OPTION_ODD)) || (bInBufferBits > 7U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
/* Parameter check */
|
||||
if (wInBufferLength == 0U)
|
||||
{
|
||||
/* Zero input length is simply passed through */
|
||||
if (bInBufferBits == 0U)
|
||||
{
|
||||
(*pOutBufferLength) = 0;
|
||||
*pOutBufferBits = 0;
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
/* Invalid parameter */
|
||||
else
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_TOOLS);
|
||||
}
|
||||
}
|
||||
|
||||
/* Retrieve DIV and MOD */
|
||||
if (bInBufferBits == 0U)
|
||||
{
|
||||
wDiv = (uint16_t)(wInBufferLength / 9U);
|
||||
bMod = (uint8_t)(wInBufferLength % 9U);
|
||||
}
|
||||
else
|
||||
{
|
||||
wDiv = (uint16_t)((wInBufferLength - 1U) / 9U);
|
||||
bMod = (uint8_t)((wInBufferLength - 1U) % 9U);
|
||||
}
|
||||
|
||||
/* Calculate number of output bytes */
|
||||
(*pOutBufferLength) = (uint16_t)((wDiv << 3U) + bMod);
|
||||
if (bMod > bInBufferBits)
|
||||
{
|
||||
--(*pOutBufferLength);
|
||||
}
|
||||
|
||||
/* Calculate number of rest-bits of output */
|
||||
*pOutBufferBits = (uint8_t)((8U - (((8U + ((*pOutBufferLength) % 8U)) - bInBufferBits) % 8U)) % 8U);
|
||||
|
||||
/* Increment output length in case of incomplete byte */
|
||||
if (*pOutBufferBits > 0U)
|
||||
{
|
||||
++(*pOutBufferLength);
|
||||
}
|
||||
|
||||
/* Buffer overflow check*/
|
||||
if (wOutBufferSize < (*pOutBufferLength))
|
||||
{
|
||||
(*pOutBufferLength) = 0;
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_BUFFER_OVERFLOW, PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
/* Prepare loop vars */
|
||||
wByteIndexIn = 0U;
|
||||
wByteIndexOut = 0U;
|
||||
bBitPosition = 7U;
|
||||
|
||||
/* Do for each byte */
|
||||
for (; wByteIndexOut < (*pOutBufferLength); ++wByteIndexOut, ++wByteIndexIn, --bBitPosition)
|
||||
{
|
||||
/* Append source bits to output */
|
||||
pOutBuffer[wByteIndexOut] = (uint8_t)(pInBuffer[wByteIndexIn] >> (7U - bBitPosition));
|
||||
|
||||
/* If there is more data bits in the sourcebyte append it to next data byte */
|
||||
if ((wByteIndexIn + /* */ 1U) < wInBufferLength)
|
||||
{
|
||||
/* Append remaining bits to output */
|
||||
pOutBuffer[wByteIndexOut] |= (uint8_t)(pInBuffer[wByteIndexIn + 1U] << (1U + bBitPosition));
|
||||
|
||||
/* Perform parity checking if this isn't an incomplete byte */
|
||||
if ((*pOutBufferBits == 0U)
|
||||
|| ((wByteIndexOut + /* */ 1U) < (*pOutBufferLength)))
|
||||
{
|
||||
bParity = phTools_CalcParity(pOutBuffer[wByteIndexOut], bOption);
|
||||
if ((pInBuffer[wByteIndexIn + 1U] & (uint8_t)(1U << (7U - bBitPosition))) != (bParity << (7U - bBitPosition)))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INTEGRITY_ERROR, PH_COMP_TOOLS);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* We have reached the 8th parity bit, the input buffer index is now one ahead */
|
||||
if (bBitPosition == 0U)
|
||||
{
|
||||
bBitPosition = 8;
|
||||
++wByteIndexIn;
|
||||
}
|
||||
}
|
||||
|
||||
/* Mask out invalid bits of last byte */
|
||||
if (*pOutBufferBits > 0U)
|
||||
{
|
||||
pOutBuffer[(*pOutBufferLength) - 1U] &= (uint8_t)(0xFFU >> (8U - *pOutBufferBits));
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phTools_CalculateCrc5(
|
||||
uint8_t bOption,
|
||||
uint8_t bPreset,
|
||||
uint8_t bPolynom,
|
||||
uint8_t * pData,
|
||||
uint16_t wDataLength,
|
||||
uint8_t * pCrc
|
||||
)
|
||||
{
|
||||
uint16_t PH_MEMLOC_REM wDataIndex = 0;
|
||||
uint8_t PH_MEMLOC_REM bBitIndex;
|
||||
uint8_t PH_MEMLOC_REM bBitMax;
|
||||
|
||||
if (0u != (bOption & (uint8_t)~(uint8_t)PH_TOOLS_CRC_OPTION_MASK))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
*pCrc = bPreset;
|
||||
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_MSB_FIRST))
|
||||
{
|
||||
/* Shift 5bit preset to 8bit (data) alignment */
|
||||
*pCrc <<= 3U;
|
||||
|
||||
/* Shift 5bit polinom to 8bit (data) alignment */
|
||||
bPolynom <<= 3U;
|
||||
}
|
||||
|
||||
/* Loop through all data bytes */
|
||||
while (0U != wDataLength)
|
||||
{
|
||||
/* XOR input data */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_BITWISE))
|
||||
{
|
||||
if (wDataLength < 8U)
|
||||
{
|
||||
bBitMax = (uint8_t)wDataLength;
|
||||
wDataLength = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
bBitMax = 8;
|
||||
wDataLength -= 8u;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
bBitMax = 8;
|
||||
/* Decrement DataLen */
|
||||
--wDataLength;
|
||||
}
|
||||
|
||||
/* CRC polynom (MSB first) */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_MSB_FIRST))
|
||||
{
|
||||
*pCrc ^= pData[wDataIndex++] & (0xFFU << (8U - bBitMax));
|
||||
|
||||
for (bBitIndex = 0; bBitIndex < bBitMax; ++bBitIndex)
|
||||
{
|
||||
if (0u != ((*pCrc) & 0x80U))
|
||||
{
|
||||
*pCrc = (uint8_t)(((*pCrc) << 1U) ^ bPolynom);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pCrc = (*pCrc) << 1U;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* CRC polynom (LSB first) */
|
||||
else
|
||||
{
|
||||
*pCrc ^= pData[wDataIndex++] & (0xFFU >> (8U - bBitMax));
|
||||
|
||||
for (bBitIndex = 0; bBitIndex < bBitMax; ++bBitIndex)
|
||||
{
|
||||
if (0u != ((*pCrc) & 0x01U))
|
||||
{
|
||||
*pCrc = (uint8_t)(((*pCrc) >> 1U) ^ bPolynom);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pCrc = ((*pCrc) >> 1U);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_MSB_FIRST))
|
||||
{
|
||||
/* Shift back for 5bit alignment */
|
||||
*pCrc >>= 3U;
|
||||
}
|
||||
|
||||
/* Invert CRC if requested */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_OUPUT_INVERTED))
|
||||
{
|
||||
*pCrc ^= 0x1FU;
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phTools_CalculateCrc8(
|
||||
uint8_t bOption,
|
||||
uint8_t bPreset,
|
||||
uint8_t bPolynom,
|
||||
uint8_t * pData,
|
||||
uint16_t wDataLength,
|
||||
uint8_t * pCrc
|
||||
)
|
||||
{
|
||||
uint16_t PH_MEMLOC_REM wDataIndex = 0;
|
||||
uint8_t PH_MEMLOC_REM bBitIndex;
|
||||
uint8_t PH_MEMLOC_REM bBitMax;
|
||||
|
||||
if (0u != (bOption & (uint8_t)~(uint8_t)PH_TOOLS_CRC_OPTION_MASK))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
*pCrc = bPreset;
|
||||
|
||||
/* Loop through all data bytes */
|
||||
while (0U != wDataLength)
|
||||
{
|
||||
/* XOR input data */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_BITWISE))
|
||||
{
|
||||
if (wDataLength < 8U)
|
||||
{
|
||||
bBitMax = (uint8_t)wDataLength;
|
||||
wDataLength = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
bBitMax = 8;
|
||||
wDataLength -= 8u;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
bBitMax = 8;
|
||||
/* Decrement DataLen */
|
||||
--wDataLength;
|
||||
}
|
||||
|
||||
/* CRC polynom (MSB first) */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_MSB_FIRST))
|
||||
{
|
||||
*pCrc ^= pData[wDataIndex++] & (0xFFU << (8U - bBitMax));
|
||||
|
||||
for (bBitIndex = 0; bBitIndex < bBitMax; ++bBitIndex)
|
||||
{
|
||||
if (0U != ((*pCrc) & 0x80U))
|
||||
{
|
||||
*pCrc = (uint8_t)(((*pCrc) << 1U) ^ bPolynom);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pCrc = ((*pCrc) << 1U);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* CRC polynom (LSB first) */
|
||||
else
|
||||
{
|
||||
*pCrc ^= pData[wDataIndex++] & (0xFFU >> (8U - bBitMax));
|
||||
|
||||
for (bBitIndex = 0; bBitIndex < bBitMax; ++bBitIndex)
|
||||
{
|
||||
if (0u != ((*pCrc) & 0x01U))
|
||||
{
|
||||
*pCrc = (uint8_t)(((*pCrc) >> 1U) ^ bPolynom);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pCrc = ((*pCrc) >> 1U);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Invert CRC if requested */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_OUPUT_INVERTED))
|
||||
{
|
||||
*pCrc ^= 0xFFU;
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phTools_CalculateCrc16(
|
||||
uint8_t bOption,
|
||||
uint16_t wPreset,
|
||||
uint16_t wPolynom,
|
||||
uint8_t * pData,
|
||||
uint16_t wDataLength,
|
||||
uint16_t * pCrc
|
||||
)
|
||||
{
|
||||
uint16_t PH_MEMLOC_REM wDataIndex = 0;
|
||||
uint8_t PH_MEMLOC_REM bBitIndex;
|
||||
uint8_t PH_MEMLOC_REM bBitMax;
|
||||
|
||||
if (0u != (bOption & (uint8_t)~(uint8_t)PH_TOOLS_CRC_OPTION_MASK))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
*pCrc = wPreset;
|
||||
|
||||
/* Loop through all data bytes */
|
||||
while (0U != wDataLength)
|
||||
{
|
||||
/* XOR input data */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_BITWISE))
|
||||
{
|
||||
if (wDataLength < 8U)
|
||||
{
|
||||
bBitMax = (uint8_t)wDataLength;
|
||||
wDataLength = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
bBitMax = 8;
|
||||
wDataLength -= 8u;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
bBitMax = 8;
|
||||
/* Decrement DataLen */
|
||||
--wDataLength;
|
||||
}
|
||||
|
||||
/* CRC polynom (MSB first) */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_MSB_FIRST))
|
||||
{
|
||||
*pCrc ^= (uint16_t)pData[wDataIndex++] << 8U;
|
||||
|
||||
for (bBitIndex = 0; bBitIndex < bBitMax; ++bBitIndex)
|
||||
{
|
||||
if (0u != ((*pCrc) & 0x8000U))
|
||||
{
|
||||
*pCrc = (uint16_t)(((*pCrc) << 1U) ^ wPolynom);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pCrc = ((*pCrc) << 1U);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* CRC polynom (LSB first) */
|
||||
else
|
||||
{
|
||||
*pCrc ^= pData[wDataIndex++];
|
||||
|
||||
for (bBitIndex = 0; bBitIndex < bBitMax; ++bBitIndex)
|
||||
{
|
||||
if (0U != ((*pCrc) & 0x0001U))
|
||||
{
|
||||
*pCrc = (uint16_t)(((*pCrc) >> 1U) ^ wPolynom);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pCrc = ((*pCrc) >> 1U);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Invert CRC if requested */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_OUPUT_INVERTED))
|
||||
{
|
||||
*pCrc ^= 0xFFFFU;
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phTools_CalculateCrc32(
|
||||
uint8_t bOption,
|
||||
uint32_t dwPreset,
|
||||
uint32_t dwPolynom,
|
||||
uint8_t * pData,
|
||||
uint32_t dwDataLength,
|
||||
uint32_t * pCrc
|
||||
)
|
||||
{
|
||||
uint32_t PH_MEMLOC_REM dwDataIndex = 0;
|
||||
uint8_t PH_MEMLOC_REM bBitIndex;
|
||||
uint8_t PH_MEMLOC_REM bBitMax;
|
||||
|
||||
if (0u != (bOption & (uint8_t)~(uint8_t)PH_TOOLS_CRC_OPTION_MASK))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_TOOLS);
|
||||
}
|
||||
|
||||
*pCrc = dwPreset;
|
||||
|
||||
/* Loop through all data bytes */
|
||||
while (0U != dwDataLength)
|
||||
{
|
||||
/* XOR input data */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_BITWISE))
|
||||
{
|
||||
if (dwDataLength < 8U)
|
||||
{
|
||||
bBitMax = (uint8_t)dwDataLength;
|
||||
dwDataLength = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
bBitMax = 8;
|
||||
dwDataLength -= 8u;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
bBitMax = 8;
|
||||
/* Decrement DataLen */
|
||||
--dwDataLength;
|
||||
}
|
||||
|
||||
/* CRC polynom (MSB first) */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_MSB_FIRST))
|
||||
{
|
||||
*pCrc ^= (uint32_t)pData[dwDataIndex++] << 24U;
|
||||
|
||||
for (bBitIndex = 0; bBitIndex < bBitMax; ++bBitIndex)
|
||||
{
|
||||
if (0u != ((*pCrc) & 0x80000000U))
|
||||
{
|
||||
*pCrc = (uint32_t)(((*pCrc) << 1U) ^ dwPolynom);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pCrc = ((*pCrc) << 1U);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* CRC polynom (LSB first) */
|
||||
else
|
||||
{
|
||||
*pCrc ^= pData[dwDataIndex++];
|
||||
|
||||
for (bBitIndex = 0; bBitIndex < bBitMax; ++bBitIndex)
|
||||
{
|
||||
if (0u != ((*pCrc) & 0x00000001U))
|
||||
{
|
||||
*pCrc = (uint32_t)(((*pCrc) >> 1U) ^ dwPolynom);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pCrc = ((*pCrc) >> 1U);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Invert CRC if requested */
|
||||
if (0U != (bOption & PH_TOOLS_CRC_OPTION_OUPUT_INVERTED))
|
||||
{
|
||||
*pCrc ^= 0xFFFFFFFFU;
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
static uint8_t phTools_CalcParity(
|
||||
uint8_t bDataByte,
|
||||
uint8_t bOption
|
||||
)
|
||||
{
|
||||
uint8_t PH_MEMLOC_REM bBit;
|
||||
uint8_t PH_MEMLOC_REM bParity;
|
||||
|
||||
if (bOption == PH_TOOLS_PARITY_OPTION_EVEN)
|
||||
{
|
||||
bParity = 0x00;
|
||||
}
|
||||
else
|
||||
{
|
||||
bParity = 0x01;
|
||||
}
|
||||
|
||||
for (bBit = 0; bBit < 8U; ++bBit)
|
||||
{
|
||||
if (0U != (bDataByte & (uint8_t)(1U << bBit)))
|
||||
{
|
||||
++bParity;
|
||||
}
|
||||
}
|
||||
return bParity & 0x01U;
|
||||
}
|
||||
|
||||
static void phTools_UpdateCrc_B(uint8_t bCh, uint16_t *pLpwCrc)
|
||||
{
|
||||
bCh = (bCh^(uint8_t)((*pLpwCrc)&0x00FFU));
|
||||
bCh = (bCh ^ (bCh<<4U));
|
||||
*pLpwCrc = (*pLpwCrc >> 8U) ^ ((uint16_t)bCh << 8U) ^ ((uint16_t)bCh << 3U) ^ ((uint16_t)bCh>>4U);
|
||||
}
|
||||
|
||||
phStatus_t phTools_ComputeCrc_B(
|
||||
uint8_t *pData,
|
||||
uint32_t dwLength,
|
||||
uint8_t *pCrc)
|
||||
{
|
||||
uint8_t PH_MEMLOC_REM bChBlock = 0;
|
||||
uint16_t PH_MEMLOC_REM wCrc = 0xFFFF;
|
||||
|
||||
do
|
||||
{
|
||||
bChBlock = *pData++;
|
||||
phTools_UpdateCrc_B(bChBlock, &wCrc);
|
||||
} while (0u != (--dwLength));
|
||||
|
||||
wCrc = ~wCrc;
|
||||
|
||||
pCrc[0] = (uint8_t) (wCrc & 0xFFU);
|
||||
pCrc[1] = (uint8_t) ( (wCrc>>8U) & 0xFFU);
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
#ifndef __min
|
||||
# define __min(X,Y) (((X) < (Y)) ? (X) : (Y))
|
||||
#endif
|
||||
|
||||
phStatus_t phTools_GetVersion(
|
||||
uint8_t * pProductVer,
|
||||
uint16_t * pMajor,
|
||||
uint8_t * pMinor,
|
||||
uint16_t * pPatch_Dev,
|
||||
uint8_t * pVersionString,
|
||||
uint16_t * pVersionStringLen)
|
||||
{
|
||||
uint16_t PH_MEMLOC_REM wCopyLen = 0;
|
||||
const char szNxpNfcRdLib_VER_FILEDESCRIPTION[] = NxpNfcRdLib_VER_FILEDESCRIPTION;
|
||||
|
||||
PH_UNUSED_VARIABLE(pProductVer);
|
||||
|
||||
/* *pProductVer = ; ankur update it when there ir product version */
|
||||
*pMajor = NxpNfcRdLib_VER_MAJOR;
|
||||
*pMinor = NxpNfcRdLib_VER_MINOR;
|
||||
*pPatch_Dev = NxpNfcRdLib_VER_DEV;
|
||||
|
||||
wCopyLen = (uint16_t)(sizeof(szNxpNfcRdLib_VER_FILEDESCRIPTION)/sizeof(szNxpNfcRdLib_VER_FILEDESCRIPTION[0]));
|
||||
|
||||
if(*pVersionStringLen < (wCopyLen - 1u))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_LENGTH_ERROR, PH_COMP_TOOLS);
|
||||
}
|
||||
else
|
||||
{
|
||||
wCopyLen = __min(wCopyLen,(*pVersionStringLen));
|
||||
|
||||
(void)memcpy(pVersionString, szNxpNfcRdLib_VER_FILEDESCRIPTION, wCopyLen);
|
||||
|
||||
*pVersionStringLen = wCopyLen - 1u;
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
@ -0,0 +1,456 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2016-2023 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
*
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
*/
|
||||
|
||||
#include <ph_Status.h>
|
||||
|
||||
#ifdef NXPBUILD__PHAL_MFNTAG42XDNA
|
||||
|
||||
#include <string.h>
|
||||
#include <phpalMifare.h>
|
||||
#include <phalMfNtag42XDna.h>
|
||||
#include "phalMfNtag42XDna_Int.h"
|
||||
#include <ph_RefDefs.h>
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Int_ComputeErrorResponse(void * pDataParams, uint16_t wStatus)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status = PH_ERR_SUCCESS;
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
|
||||
switch (wStatus)
|
||||
{
|
||||
case PHAL_MFNTAG42XDNA_RESP_OPERATION_OK:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_SUCCESS:
|
||||
case PHAL_MFNTAG42XDNA_RESP_OK:
|
||||
status = PH_ERR_SUCCESS;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_CMD_INVALID:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_CMD_INVALID;
|
||||
break;
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_FORMAT:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_FORMAT;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_OUT_OF_EEPROM_ERROR:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_OUT_OF_EEPROM_ERROR;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_INTEGRITY_ERROR:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_PICC_CRYPTO;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_PARAMETER_ERROR:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_PARAMETER_ERROR;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_NO_SUCH_KEY:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_NO_SUCH_KEY;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_LENGTH_ERROR:
|
||||
status = PH_ERR_LENGTH_ERROR;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_PERMISSION_DENIED:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_PERMISSION_DENIED;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_APPLICATION_NOT_FOUND:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_APPLICATION_NOT_FOUND;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_AUTHENTICATION_ERROR:
|
||||
status = PH_ERR_AUTH_ERROR;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_AUTHENTICATION_DELAY:
|
||||
status = PH_ERR_AUTH_DELAY;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ADDITIONAL_FRAME:
|
||||
status = PH_ERR_SUCCESS_CHAINING;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_BOUNDARY_ERROR:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_BOUNDARY_ERROR;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_COMMAND_ABORTED:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_COMMAND_ABORTED;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_COUNT:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_COUNT;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_DUPLICATE:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_DUPLICATE;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_FILE_NOT_FOUND:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_FILE_NOT_FOUND;
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_APPL_INTEGRITY_ERROR:
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_PICC_INTEGRITY:
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_EEPROM:
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_FILE_INTEGRITY:
|
||||
case PHAL_MFNTAG42XDNA_RESP_ERR_PIC_DISABLED:
|
||||
case PHAL_MFNTAG42XDNA_RESP_ILLEGAL_COMMAND_CODE:
|
||||
status = PHAL_MFNTAG42XDNA_ERR_DF_GEN_ERROR;
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phalMfNtag42XDna_SetConfig(
|
||||
pDataParams,
|
||||
PHAL_MFNTAG42XDNA_ADDITIONAL_INFO,
|
||||
wStatus));
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_WRONG_LENGTH:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_WRONG_LE:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_FILE_NOT_FOUND:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_WRONG_PARAMS:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_WRONG_LC:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_NO_PRECISE_DIAGNOSTICS:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_EOF_REACHED:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_LIMITED_FUNCTIONALITY_INS:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_FILE_ACCESS:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_FILE_EMPTY:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_MEMORY_FAILURE:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_INCORRECT_PARAMS:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_WRONG_CLA:
|
||||
case PHAL_MFNTAG42XDNA_ISO7816_ERR_UNSUPPORTED_INS:
|
||||
|
||||
status = PHAL_MFNTAG42XDNA_ERR_DF_7816_GEN_ERROR;
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phalMfNtag42XDna_SetConfig(
|
||||
pDataParams,
|
||||
PHAL_MFNTAG42XDNA_ADDITIONAL_INFO,
|
||||
wStatus));
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_RESP_CHAINING:
|
||||
status = PH_ERR_SUCCESS_CHAINING;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = PH_ERR_PROTOCOL_ERROR;
|
||||
}
|
||||
return PH_ADD_COMPCODE(status, PH_COMP_AL_MFNTAG42XDNA);
|
||||
}
|
||||
|
||||
/*
|
||||
*
|
||||
* Should take care of wrapping and unwrapping if ISO 7816 Wrapped mode
|
||||
* Does not handle any chaining or CMAC generation/verification or encryption/decryption
|
||||
*/
|
||||
phStatus_t phalMfNtag42XDna_ExchangeCmd(void * pDataParams, void * pPalMifareDataParams, uint8_t bWrappedMode,
|
||||
uint8_t * pSendBuff, uint16_t wCmdLen, uint8_t ** ppResponse, uint16_t * pRxlen)
|
||||
{
|
||||
uint16_t PH_MEMLOC_REM wFrameLen;
|
||||
uint8_t PH_MEMLOC_REM * pRecv;
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM bStatusByte = 0xFF;
|
||||
uint8_t PH_MEMLOC_REM pApdu[5] = { PHAL_MFNTAG42XDNA_WRAPPEDAPDU_CLA, 0x00, PHAL_MFNTAG42XDNA_WRAPPEDAPDU_P1, PHAL_MFNTAG42XDNA_WRAPPEDAPDU_P2, 0x00 };
|
||||
|
||||
if (bWrappedMode)
|
||||
{
|
||||
wFrameLen = PHAL_MFNTAG42XDNA_MAXWRAPPEDAPDU_SIZE;
|
||||
}
|
||||
else
|
||||
{
|
||||
wFrameLen = PHAL_MFNTAG42XDNA_MAXDFAPDU_SIZE;
|
||||
}
|
||||
|
||||
if (wCmdLen > wFrameLen)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_BUFFER_OVERFLOW, PH_COMP_AL_MFNTAG42XDNA);
|
||||
}
|
||||
|
||||
/* Send the data to PICC */
|
||||
if (bWrappedMode)
|
||||
{
|
||||
pApdu[1] = pSendBuff[0]; /* Desfire cmd code in INS */
|
||||
pApdu[4] = (uint8_t)(wCmdLen) - 0x01u;
|
||||
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
pApdu[4] == 0x00 ? PH_EXCHANGE_DEFAULT : PH_EXCHANGE_BUFFER_FIRST,
|
||||
pApdu,
|
||||
PHAL_MFNTAG42XDNA_WRAP_HDR_LEN,
|
||||
&pRecv,
|
||||
pRxlen));
|
||||
|
||||
if (pApdu[4] != 0x00)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_CONT,
|
||||
&pSendBuff[1],
|
||||
wCmdLen - 1,
|
||||
&pRecv,
|
||||
pRxlen));
|
||||
|
||||
/* Le byte */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_LAST,
|
||||
&pApdu[2], /* Le is always zero in wrapped mode. */
|
||||
0x01,
|
||||
&pRecv,
|
||||
pRxlen));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
pSendBuff,
|
||||
wCmdLen,
|
||||
&pRecv,
|
||||
pRxlen));
|
||||
}
|
||||
if (bWrappedMode)
|
||||
{
|
||||
/* memcpy(pResponse, pRecv, (*pRxlen) - 2); PRQA S 3200 */
|
||||
*ppResponse = pRecv;
|
||||
bStatusByte = pRecv[(*pRxlen) - 1];
|
||||
(*pRxlen) -= 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* memcpy(pResponse, &pRecv[1], (*pRxlen) - 1); PRQA S 3200 */
|
||||
*ppResponse = pRecv + 1;
|
||||
bStatusByte = pRecv[0];
|
||||
(*pRxlen) -= 1;
|
||||
}
|
||||
return phalMfNtag42XDna_Int_ComputeErrorResponse(pDataParams, bStatusByte);
|
||||
}
|
||||
|
||||
/*
|
||||
* Should return SW1+SW2
|
||||
*/
|
||||
phStatus_t phalMfNtag42XDna_Int_Send7816Apdu(void * pDataParams, void * pPalMifareDataParams, uint8_t bOption, uint8_t bIns,
|
||||
uint8_t bP1, uint8_t bP2, uint32_t bLc, uint8_t bExtendedLenApdu, uint8_t * pDataIn, uint32_t bLe, uint8_t ** ppDataOut,
|
||||
uint16_t *pDataLen)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp = PH_ERR_SUCCESS;
|
||||
uint8_t PH_MEMLOC_REM bCmdBuff[20];
|
||||
uint16_t PH_MEMLOC_REM wCmdLen = 0;
|
||||
|
||||
bCmdBuff[wCmdLen++] = 0x00; /* Class is always 0x00 */
|
||||
bCmdBuff[wCmdLen++] = bIns;
|
||||
bCmdBuff[wCmdLen++] = bP1;
|
||||
bCmdBuff[wCmdLen++] = bP2;
|
||||
|
||||
switch(bIns)
|
||||
{
|
||||
case PHAL_MFNTAG42XDNA_CMD_ISO7816_SELECT_FILE:
|
||||
/* Both Lc and Le are required */
|
||||
statusTmp = phalMfNtag42XDna_Int_ISOSelectFile(pDataParams, pPalMifareDataParams, bOption, bCmdBuff, wCmdLen,
|
||||
(uint8_t)bLc, bExtendedLenApdu, pDataIn, (uint8_t)bLe, ppDataOut, pDataLen);
|
||||
break;
|
||||
|
||||
case PHAL_MFNTAG42XDNA_CMD_ISO7816_UPDATE_BINARY:
|
||||
statusTmp = phalMfNtag42XDna_Int_ISOUpdateBinary(pDataParams, pPalMifareDataParams, bOption, bCmdBuff, wCmdLen,
|
||||
bLc, bExtendedLenApdu, pDataIn, ppDataOut, pDataLen);
|
||||
break;
|
||||
|
||||
default:
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_COMMAND, PH_COMP_AL_MFNTAG42XDNA);
|
||||
break;
|
||||
}
|
||||
return statusTmp;
|
||||
}
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Int_ISOSelectFile(void * pDataParams, void * pPalMifareDataParams, uint8_t bOption, uint8_t * bCmdBuff,
|
||||
uint16_t wCmdLen, uint8_t bLc, uint8_t bExtendedLenApdu, uint8_t * pDataIn, uint8_t bLe, uint8_t ** ppDataOut, uint16_t *pDataLen)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint16_t PH_MEMLOC_REM wRxlen;
|
||||
uint8_t PH_MEMLOC_REM *pRecv;
|
||||
bOption = 0x01; /* To avoid warnings */
|
||||
|
||||
/* Do not frame LC for Selector zero. */
|
||||
if(bCmdBuff[2] != 0x03)
|
||||
{
|
||||
/* Check whether Length Lc is represented in short APDU or extended APDU */
|
||||
if(bExtendedLenApdu == 0x01)
|
||||
{
|
||||
/* Extended APDU */
|
||||
bCmdBuff[wCmdLen++] = 0x00; /* first byte will be 0x00 if Ext apdu present. Next 2 byte contains actual data */
|
||||
bCmdBuff[wCmdLen++] = 0x00; /* As of now this field will be set to 0x00 since maximum data that can be sent is 16 bytes. In case if data to be sent exceeds 255 bytes, this byte shall be used */
|
||||
bCmdBuff[wCmdLen++] = bLc; /* Actual data to be sent */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Short APDU */
|
||||
bCmdBuff[wCmdLen++] = bLc;
|
||||
}
|
||||
}
|
||||
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_FIRST,
|
||||
bCmdBuff,
|
||||
wCmdLen,
|
||||
&pRecv,
|
||||
&wRxlen
|
||||
));
|
||||
if ((bLc > 0))
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_CONT,
|
||||
pDataIn,
|
||||
bLc,
|
||||
&pRecv,
|
||||
&wRxlen
|
||||
));
|
||||
}
|
||||
wCmdLen = 0;
|
||||
|
||||
/* As per ISO/IEC:7816-4(2005), Section 5, An extended Le field consists of either three bytes
|
||||
* (one byte set to '00' followed by two bytes with any
|
||||
* value) if the Lc field is absent, or two bytes (with any value) if an extended Lc field is present.
|
||||
*/
|
||||
|
||||
/* Check whether Length is represented in extended APDU format and Lc is present.
|
||||
* If true, then Le should represented in 2 bytes else Le should be represented in 3 bytes
|
||||
*/
|
||||
if(bCmdBuff[2] != 0x03)
|
||||
{
|
||||
if(bExtendedLenApdu == 0x01)
|
||||
{
|
||||
/* Extended APDU */
|
||||
bCmdBuff[wCmdLen++] = 0x00;
|
||||
bCmdBuff[wCmdLen++] = bLe;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Short APDU */
|
||||
bCmdBuff[wCmdLen++] = bLe;
|
||||
}
|
||||
}
|
||||
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_LAST,
|
||||
bCmdBuff,
|
||||
wCmdLen,
|
||||
&pRecv,
|
||||
&wRxlen
|
||||
));
|
||||
statusTmp = pRecv[wRxlen - 2];
|
||||
statusTmp <<= 8;
|
||||
statusTmp |= pRecv[wRxlen - 1];
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phalMfNtag42XDna_Int_ComputeErrorResponse(pDataParams, statusTmp));
|
||||
if (pDataLen != NULL)
|
||||
{
|
||||
*pDataLen = wRxlen -2;
|
||||
}
|
||||
if (ppDataOut != NULL)
|
||||
{
|
||||
*ppDataOut = pRecv;
|
||||
}
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phalMfNtag42XDna_Int_ISOUpdateBinary(void * pDataParams, void * pPalMifareDataParams, uint8_t bOption, uint8_t * bCmdBuff,
|
||||
uint16_t wCmdLen, uint32_t dwLc, uint8_t bExtendedLenApdu, uint8_t * pDataIn, uint8_t ** ppDataOut, uint16_t *pDataLen)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint16_t PH_MEMLOC_REM wRxlen;
|
||||
uint8_t PH_MEMLOC_REM *pRecv;
|
||||
uint8_t PH_MEMLOC_REM *bDataLenPtr;
|
||||
/* Initialise LcPtr */
|
||||
bDataLenPtr = (uint8_t *)&dwLc;
|
||||
/* Check whether Lc has to be passed */
|
||||
if (bOption & 0x01)
|
||||
{
|
||||
/* Check whether Length Lc is represented in short APDU or extended APDU */
|
||||
if(bExtendedLenApdu == 0x01)
|
||||
{
|
||||
/*
|
||||
* As per ISO-7816 Standard(2005), section 5.1,
|
||||
* A short Lc field consists of one byte not set to '00'.
|
||||
* From '01' to 'FF', the byte encodes Nc from one to 255.
|
||||
*
|
||||
* An extended Lc field consists of three bytes: one byte
|
||||
* set to '00' followed by two bytes not set to '0000'.From
|
||||
* '0001' to 'FFFF', the two bytes encode Nc from one to
|
||||
* 65535.
|
||||
*/
|
||||
bCmdBuff[wCmdLen++] = 0x00;
|
||||
bCmdBuff[wCmdLen++] = *(bDataLenPtr + 1);
|
||||
bCmdBuff[wCmdLen++] = *(bDataLenPtr);
|
||||
/* Note: Need to handle the case where data to write is more than 0xFFFF(i.e 65535 bytes).
|
||||
*/
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Short APDU */
|
||||
bCmdBuff[wCmdLen++] = *bDataLenPtr;
|
||||
}
|
||||
}
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_FIRST,
|
||||
bCmdBuff,
|
||||
wCmdLen,
|
||||
&pRecv,
|
||||
&wRxlen
|
||||
));
|
||||
if ((bOption & 0x01) && (dwLc > 0))
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_CONT,
|
||||
pDataIn,
|
||||
(uint16_t)dwLc,
|
||||
&pRecv,
|
||||
&wRxlen
|
||||
));
|
||||
}
|
||||
wCmdLen = 0;
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalMifare_ExchangeL4(
|
||||
pPalMifareDataParams,
|
||||
PH_EXCHANGE_BUFFER_LAST,
|
||||
bCmdBuff,
|
||||
wCmdLen,
|
||||
&pRecv,
|
||||
&wRxlen
|
||||
));
|
||||
|
||||
statusTmp = pRecv[wRxlen - 2];
|
||||
statusTmp <<= 8;
|
||||
statusTmp |= pRecv[wRxlen - 1];
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phalMfNtag42XDna_Int_ComputeErrorResponse(pDataParams, statusTmp));
|
||||
if (pDataLen != NULL)
|
||||
{
|
||||
*pDataLen = wRxlen -2;
|
||||
}
|
||||
if (ppDataOut != NULL)
|
||||
{
|
||||
*ppDataOut = pRecv;
|
||||
}
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
#endif /* NXPBUILD__PHAL_MFNTAG42XDNA */
|
||||
@ -0,0 +1,247 @@
|
||||
/*
|
||||
* @brief SD Card Interface registers and control functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
static void writeDelay(void)
|
||||
{
|
||||
volatile uint8_t i;
|
||||
for ( i = 0; i < 0x10; i++ ) { /* delay 3MCLK + 2PCLK */
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Set power state of SDC peripheral */
|
||||
void Chip_SDC_PowerControl(LPC_SDC_T *pSDC, SDC_PWR_CTRL_T pwrMode, uint32_t flag)
|
||||
{
|
||||
pSDC->POWER = SDC_PWR_CTRL(pwrMode) | flag;
|
||||
writeDelay();
|
||||
}
|
||||
|
||||
/* Set clock divider for SDC peripheral */
|
||||
void Chip_SDC_SetClockDiv(LPC_SDC_T *pSDC, uint8_t div)
|
||||
{
|
||||
uint32_t temp;
|
||||
temp = (pSDC->CLOCK & (~SDC_CLOCK_CLKDIV_BITMASK));
|
||||
pSDC->CLOCK = temp | (SDC_CLOCK_CLKDIV(div));
|
||||
writeDelay();
|
||||
}
|
||||
|
||||
/* Clock control for SDC peripheral*/
|
||||
void Chip_SDC_ClockControl(LPC_SDC_T *pSDC, SDC_CLOCK_CTRL_T ctrlType,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
if (NewState) {
|
||||
pSDC->CLOCK |= (1 << ctrlType);
|
||||
}
|
||||
else {
|
||||
pSDC->CLOCK &= (~(1 << ctrlType));
|
||||
}
|
||||
writeDelay();
|
||||
}
|
||||
|
||||
/* Initialize SDC peripheral */
|
||||
static void SDC_Init(LPC_SDC_T *pSDC)
|
||||
{
|
||||
/* Disable SD_CLK */
|
||||
Chip_SDC_ClockControl(pSDC, SDC_CLOCK_ENABLE, DISABLE);
|
||||
|
||||
/* Power-off */
|
||||
Chip_SDC_PowerControl(pSDC, SDC_POWER_OFF, 0);
|
||||
writeDelay();
|
||||
|
||||
/* Disable all interrupts */
|
||||
pSDC->MASK0 = 0;
|
||||
|
||||
/*Setting for timeout problem */
|
||||
pSDC->DATATIMER = 0x1FFFFFFF;
|
||||
|
||||
pSDC->COMMAND = 0;
|
||||
writeDelay();
|
||||
|
||||
pSDC->DATACTRL = 0;
|
||||
writeDelay();
|
||||
|
||||
/* clear all pending interrupts */
|
||||
pSDC->CLEAR = SDC_CLEAR_ALL;
|
||||
}
|
||||
|
||||
/* Initializes the SDC card controller */
|
||||
void Chip_SDC_Init(LPC_SDC_T *pSDC)
|
||||
{
|
||||
uint32_t i = 0;
|
||||
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SDC);
|
||||
Chip_SYSCTL_PeriphReset(SYSCTL_RESET_PCSDC);
|
||||
|
||||
/* Initialize GPDMA controller */
|
||||
Chip_GPDMA_Init(LPC_GPDMA);
|
||||
|
||||
/* Initialize SDC peripheral */
|
||||
SDC_Init(pSDC);
|
||||
|
||||
/* Power-up SDC Peripheral */
|
||||
Chip_SDC_PowerControl(pSDC, SDC_POWER_UP, 0);
|
||||
|
||||
/* delays for the supply output is stable*/
|
||||
for ( i = 0; i < 0x80000; i++ ) {}
|
||||
|
||||
Chip_SDC_SetClock(pSDC, SDC_IDENT_CLOCK_RATE);
|
||||
Chip_SDC_ClockControl(pSDC, SDC_CLOCK_ENABLE, ENABLE);
|
||||
|
||||
/* Power-on SDC Interface */
|
||||
Chip_SDC_PowerControl(pSDC, SDC_POWER_ON, 0);
|
||||
|
||||
}
|
||||
|
||||
/* Set Command Info */
|
||||
void Chip_SDC_SetCommand(LPC_SDC_T *pSDC, uint32_t Cmd, uint32_t Arg)
|
||||
{
|
||||
/* Clear status register */
|
||||
pSDC->CLEAR = SDC_CLEAR_ALL;
|
||||
|
||||
/* Set the argument first, finally command */
|
||||
pSDC->ARGUMENT = Arg;
|
||||
|
||||
/* Write command value, enable the command */
|
||||
pSDC->COMMAND = Cmd | SDC_COMMAND_ENABLE;
|
||||
|
||||
writeDelay();
|
||||
}
|
||||
|
||||
/* Reset Command Info */
|
||||
void Chip_SDC_ResetCommand(LPC_SDC_T *pSDC)
|
||||
{
|
||||
pSDC->CLEAR = SDC_CLEAR_ALL;
|
||||
|
||||
pSDC->ARGUMENT = 0xFFFFFFFF;
|
||||
|
||||
pSDC->COMMAND = 0;
|
||||
|
||||
writeDelay();
|
||||
}
|
||||
|
||||
/* Get Command response */
|
||||
void Chip_SDC_GetResp(LPC_SDC_T *pSDC, SDC_RESP_T *pResp)
|
||||
{
|
||||
uint8_t i;
|
||||
pResp->CmdIndex = SDC_RESPCOMMAND_VAL(pSDC->RESPCMD);
|
||||
for (i = 0; i < SDC_CARDSTATUS_BYTENUM; i++) {
|
||||
pResp->Data[i] = pSDC->RESPONSE[i];
|
||||
}
|
||||
}
|
||||
|
||||
/* Setup Data Transfer Information */
|
||||
void Chip_SDC_SetDataTransfer(LPC_SDC_T *pSDC, SDC_DATA_TRANSFER_T *pTransfer)
|
||||
{
|
||||
uint32_t DataCtrl = 0;
|
||||
pSDC->DATATIMER = pTransfer->Timeout;
|
||||
pSDC->DATALENGTH = pTransfer->BlockNum * SDC_DATACTRL_BLOCKSIZE_VAL(pTransfer->BlockSize);
|
||||
DataCtrl = SDC_DATACTRL_ENABLE;
|
||||
DataCtrl |= ((uint32_t) pTransfer->Dir) | ((uint32_t) pTransfer->Mode) | SDC_DATACTRL_BLOCKSIZE(
|
||||
pTransfer->BlockSize);
|
||||
if (pTransfer->DMAUsed) {
|
||||
DataCtrl |= SDC_DATACTRL_DMA_ENABLE;
|
||||
}
|
||||
pSDC->DATACTRL = DataCtrl;
|
||||
writeDelay();
|
||||
}
|
||||
|
||||
/* Write data to FIFO */
|
||||
void Chip_SDC_WriteFIFO(LPC_SDC_T *pSDC, uint32_t *pSrc, bool bFirstHalf)
|
||||
{
|
||||
uint8_t start = 0, end = 7;
|
||||
if (!bFirstHalf) {
|
||||
start += 8;
|
||||
end += 8;
|
||||
}
|
||||
for (; start <= end; start++) {
|
||||
pSDC->FIFO[start] = *pSrc;
|
||||
pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Read data from FIFO */
|
||||
void Chip_SDC_ReadFIFO(LPC_SDC_T *pSDC, uint32_t *pDst, bool bFirstHalf)
|
||||
{
|
||||
uint8_t start = 0, end = 7;
|
||||
|
||||
if (!bFirstHalf) {
|
||||
start += 8;
|
||||
end += 8;
|
||||
}
|
||||
for (; start <= end; start++) {
|
||||
*pDst = pSDC->FIFO[start];
|
||||
pDst++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set SD_CLK Clock */
|
||||
void Chip_SDC_SetClock(LPC_SDC_T *pSDC, uint32_t freq)
|
||||
{
|
||||
uint32_t PClk;
|
||||
uint32_t ClkValue = 0;
|
||||
|
||||
PClk = Chip_Clock_GetPeripheralClockRate();
|
||||
|
||||
ClkValue = (PClk + 2 * freq - 1) / (2 * freq);
|
||||
if (ClkValue > 0) {
|
||||
ClkValue -= 1;
|
||||
}
|
||||
Chip_SDC_SetClockDiv(pSDC, ClkValue);
|
||||
}
|
||||
|
||||
/* Shutdown the SDC card controller */
|
||||
void Chip_SDC_DeInit(LPC_SDC_T *pSDC)
|
||||
{
|
||||
/* Power-off */
|
||||
Chip_SDC_PowerControl(pSDC, SDC_POWER_OFF, 0);
|
||||
|
||||
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SDC);
|
||||
}
|
||||
|
||||
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC4XX) */
|
||||
1829
.svn/pristine/15/1519ff1d8c705f38045bfe4f3caa6b0d4453129e.svn-base
Normal file
1829
.svn/pristine/15/1519ff1d8c705f38045bfe4f3caa6b0d4453129e.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,363 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors Gratkorn / Austria
|
||||
*
|
||||
* (C)NXP Semiconductors
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
*particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Rc663 Keystore Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* RSn: Generated 5. May 2010
|
||||
*
|
||||
*/
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <ph_RefDefs.h>
|
||||
#include <phhalHw.h>
|
||||
#include <phKeyStore.h>
|
||||
|
||||
#ifdef NXPBUILD__PH_KEYSTORE_RC663
|
||||
|
||||
#include "phKeyStore_Rc663.h"
|
||||
#include "phKeyStore_Rc663_Int.h"
|
||||
#include <phhalHw_Rc663_Reg.h>
|
||||
|
||||
phStatus_t phKeyStore_Rc663_Init(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wSizeOfDataParams,
|
||||
void * pHalDataParams
|
||||
)
|
||||
{
|
||||
/* Dataparam structure check */
|
||||
if (sizeof(phKeyStore_Rc663_DataParams_t) != wSizeOfDataParams)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_KEYSTORE);
|
||||
}
|
||||
PH_ASSERT_NULL (pDataParams);
|
||||
PH_ASSERT_NULL (pHalDataParams);
|
||||
|
||||
/* Init private data */
|
||||
pDataParams->wId = PH_COMP_KEYSTORE| PH_KEYSTORE_RC663_ID;
|
||||
pDataParams->pHalDataParams = pHalDataParams;
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_FormatKeyEntry(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wKeyNo,
|
||||
uint16_t wNewKeyType
|
||||
)
|
||||
{
|
||||
uint8_t PH_MEMLOC_BUF bKey[PH_KEYSTORE_KEY_TYPE_MIFARE_SIZE];
|
||||
|
||||
/* clear key buffer */
|
||||
(void)memset(bKey, 0x00, PH_KEYSTORE_KEY_TYPE_MIFARE_SIZE);
|
||||
|
||||
return phKeyStore_Rc663_SetKeyAtPos(pDataParams, wKeyNo, 0, wNewKeyType, bKey, 0);
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_SetKey(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wKeyNo,
|
||||
uint16_t wKeyVersion,
|
||||
uint16_t wKeyType,
|
||||
uint8_t * pNewKey,
|
||||
uint16_t wNewKeyVersion
|
||||
)
|
||||
{
|
||||
/* satisfy compiler */
|
||||
if (0U != (wKeyVersion));
|
||||
return (phKeyStore_Rc663_SetKeyAtPos(pDataParams, wKeyNo, 0, wKeyType, pNewKey, wNewKeyVersion));
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_SetKeyAtPos(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wKeyNo,
|
||||
uint16_t wPos,
|
||||
uint16_t wKeyType,
|
||||
uint8_t * pNewKey,
|
||||
uint16_t wNewKeyVersion
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_BUF bKeyNoInt;
|
||||
|
||||
/* satisfy compiler */
|
||||
if (wPos || wNewKeyVersion);
|
||||
|
||||
/* Check if wKeyNo is out of range */
|
||||
if (wKeyNo >= PH_KEYSTORE_RC663_NUM_KEYS)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
/* Retrieve Key type */
|
||||
switch(wKeyType)
|
||||
{
|
||||
/* MIFARE keys are the only supported keys */
|
||||
case PH_KEYSTORE_KEY_TYPE_MIFARE:
|
||||
|
||||
/* prepare the command to be sent */
|
||||
bKeyNoInt = (uint8_t)(wKeyNo << 1U);
|
||||
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phKeyStore_Rc663_StoreKeyE2_Int(
|
||||
pDataParams,
|
||||
bKeyNoInt,
|
||||
pNewKey,
|
||||
2));
|
||||
|
||||
break;
|
||||
|
||||
case PH_KEYSTORE_KEY_TYPE_AES128:
|
||||
case PH_KEYSTORE_KEY_TYPE_AES192:
|
||||
case PH_KEYSTORE_KEY_TYPE_AES256:
|
||||
case PH_KEYSTORE_KEY_TYPE_DES:
|
||||
case PH_KEYSTORE_KEY_TYPE_2K3DES:
|
||||
case PH_KEYSTORE_KEY_TYPE_3K3DES:
|
||||
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_PARAMETER, PH_COMP_KEYSTORE);
|
||||
|
||||
default:
|
||||
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_SetKUC(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wKeyNo,
|
||||
uint16_t wRefNoKUC
|
||||
)
|
||||
{
|
||||
/* satisfy compiler */
|
||||
if (pDataParams || wKeyNo || wRefNoKUC);
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_COMMAND, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_SetFullKeyEntry(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wNoOfKeys,
|
||||
uint16_t wKeyNo,
|
||||
uint16_t wNewRefNoKUC,
|
||||
uint16_t wNewKeyType,
|
||||
uint8_t * pNewKeys,
|
||||
uint16_t * pNewKeyVersionList
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint16_t PH_MEMLOC_REM wKeyVersion = 0;
|
||||
uint16_t PH_MEMLOC_COUNT i;
|
||||
|
||||
/* satisfy compiler */
|
||||
if (wNewRefNoKUC || pNewKeyVersionList);
|
||||
|
||||
/* check wNoOfKeys */
|
||||
if (wNoOfKeys > PH_KEYSTORE_RC663_NUM_VERSIONS)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
/* set keys */
|
||||
for (i = 0; i < wNoOfKeys; ++i)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phKeyStore_Rc663_SetKeyAtPos(pDataParams, wKeyNo, i, wNewKeyType, &pNewKeys[i*PH_KEYSTORE_KEY_TYPE_MIFARE_SIZE], wKeyVersion));
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_GetKeyEntry(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wKeyNo,
|
||||
uint16_t wKeyVersionBufSize,
|
||||
uint16_t * wKeyVersion,
|
||||
uint16_t * wKeyVersionLength,
|
||||
uint16_t * pKeyType
|
||||
)
|
||||
{
|
||||
/* satisfy compiler */
|
||||
if (pDataParams || wKeyNo || wKeyVersionBufSize || wKeyVersion || wKeyVersionLength || pKeyType);
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_COMMAND, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_GetKey(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wKeyNo,
|
||||
uint16_t wKeyVersion,
|
||||
uint8_t bKeyBufSize,
|
||||
uint8_t * pKey,
|
||||
uint16_t * pKeyType
|
||||
)
|
||||
{
|
||||
/* satisfy compiler */
|
||||
if (pDataParams || wKeyNo || wKeyVersion || bKeyBufSize || pKey || pKeyType);
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_COMMAND, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_SetConfig(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wConfig,
|
||||
uint16_t wValue
|
||||
)
|
||||
{
|
||||
/* satisfy compiler */
|
||||
if (pDataParams || wConfig || wValue);
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_PARAMETER, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_SetConfigStr(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wConfig,
|
||||
uint8_t *pBuffer,
|
||||
uint16_t wBufferLength
|
||||
)
|
||||
{
|
||||
/* satisfy compiler */
|
||||
if (pDataParams || wConfig || pBuffer || wBufferLength);
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_PARAMETER, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_GetConfig(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wConfig,
|
||||
uint16_t * pValue
|
||||
)
|
||||
{
|
||||
/* satisfy compiler */
|
||||
if (pDataParams || wConfig || pValue);
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_PARAMETER, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_GetConfigStr(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wConfig,
|
||||
uint8_t ** ppBuffer,
|
||||
uint16_t * pBufferLength
|
||||
)
|
||||
{
|
||||
/* satisfy compiler */
|
||||
if (pDataParams || wConfig || ppBuffer || pBufferLength);
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_PARAMETER, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_ChangeKUC(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wRefNoKUC,
|
||||
uint32_t dwLimit
|
||||
)
|
||||
{
|
||||
/* satisfy compiler */
|
||||
if (pDataParams || wRefNoKUC || dwLimit);
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_COMMAND, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_GetKUC(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint16_t wRefNoKUC,
|
||||
uint32_t * pdwLimit,
|
||||
uint32_t * pdwCurVal
|
||||
)
|
||||
{
|
||||
|
||||
/* satisfy compiler */
|
||||
if (pDataParams || wRefNoKUC || pdwLimit || pdwCurVal);
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_COMMAND, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
phStatus_t phKeyStore_Rc663_StoreKeyE2_Int(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint8_t bKeyNumber,
|
||||
uint8_t * pKey,
|
||||
uint8_t bNumKeys
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM bRegValue;
|
||||
uint16_t PH_MEMLOC_COUNT wIndex;
|
||||
|
||||
/* clear all IRQ0 flags */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rc663_WriteRegister(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_KEYSTORE_RC663_REG_IRQ0,
|
||||
(uint8_t)~(uint8_t)PH_KEYSTORE_RC663_BIT_IRQ_SET));
|
||||
|
||||
/* clear all IRQ1 flags */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rc663_WriteRegister(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_KEYSTORE_RC663_REG_IRQ1,
|
||||
(uint8_t)~(uint8_t)PH_KEYSTORE_RC663_BIT_IRQ_SET));
|
||||
|
||||
/* Stop an eventual previous Command (enter Idle state) */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rc663_WriteRegister(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_KEYSTORE_RC663_REG_COMMAND,
|
||||
PH_KEYSTORE_RC663_CMD_IDLE
|
||||
));
|
||||
|
||||
/* Flush Rc663 fifo */
|
||||
/* Read FIFO Control register*/
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rc663_ReadRegister(pDataParams->pHalDataParams, PH_KEYSTORE_RC663_REG_FIFOCONTROL, &bRegValue));
|
||||
|
||||
/* Set FlushFifo bit */
|
||||
bRegValue |= PH_KEYSTORE_RC663_BIT_FLUSHFIFO;
|
||||
|
||||
/* Write to FIFO Control register */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rc663_WriteRegister(pDataParams->pHalDataParams, PH_KEYSTORE_RC663_REG_FIFOCONTROL, bRegValue));
|
||||
|
||||
/* Write the Key number */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rc663_WriteRegister(pDataParams->pHalDataParams, PH_KEYSTORE_RC663_REG_FIFODATA, bKeyNumber));
|
||||
|
||||
/* Write each single key byte */
|
||||
for (wIndex = 0; wIndex < (bNumKeys * PH_KEYSTORE_KEY_TYPE_MIFARE_SIZE); ++wIndex)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rc663_WriteRegister(pDataParams->pHalDataParams, PH_KEYSTORE_RC663_REG_FIFODATA, pKey[wIndex]));
|
||||
}
|
||||
|
||||
/* start the command */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rc663_WriteRegister(pDataParams->pHalDataParams, PH_KEYSTORE_RC663_REG_COMMAND, PH_KEYSTORE_RC663_CMD_STOREKEYE2));
|
||||
|
||||
/* wait for the EE programming to be finished */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Wait(pDataParams->pHalDataParams, PHHAL_HW_TIME_MILLISECONDS, PH_KEYSTORE_RC663_EEP_WR_TO_MS * bNumKeys));
|
||||
|
||||
/* take a look at the IDLE IRQ */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rc663_ReadRegister(pDataParams->pHalDataParams, PH_KEYSTORE_RC663_REG_IRQ0, &bRegValue));
|
||||
|
||||
if ( (0U == ((PHHAL_HW_RC663_BIT_IDLEIRQ & bRegValue))))
|
||||
{
|
||||
/* stop the command */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rc663_WriteRegister(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_KEYSTORE_RC663_REG_COMMAND,
|
||||
PH_KEYSTORE_RC663_CMD_IDLE));
|
||||
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_READ_WRITE_ERROR, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
/* read the error register */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rc663_ReadRegister(pDataParams->pHalDataParams, PHHAL_HW_RC663_REG_ERROR, &bRegValue));
|
||||
|
||||
/* check for EEPROM error */
|
||||
if (0U != (bRegValue & PHHAL_HW_RC663_BIT_EE_ERR))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_READ_WRITE_ERROR, PH_COMP_KEYSTORE);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
#endif /* NXPBUILD__PH_KEYSTORE_RC663 */
|
||||
1081
.svn/pristine/15/159aa61ef26eee1a0b60cd66af118ecca2582115.svn-base
Normal file
1081
.svn/pristine/15/159aa61ef26eee1a0b60cd66af118ecca2582115.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
1128
.svn/pristine/15/15d7a9740db8b08a1e7dd5d7ad7a667bb2ebde1f.svn-base
Normal file
1128
.svn/pristine/15/15d7a9740db8b08a1e7dd5d7ad7a667bb2ebde1f.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,44 @@
|
||||
/*
|
||||
* @brief LPC17xx/40xx GPIO driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
180734
.svn/pristine/16/16deaf8ded2179bd607f42d0165a97d0540cc630.svn-base
Normal file
180734
.svn/pristine/16/16deaf8ded2179bd607f42d0165a97d0540cc630.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,784 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2010-2023 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Software FeliCa Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
*/
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <phhalHw.h>
|
||||
#include <phpalFelica.h>
|
||||
#include <ph_RefDefs.h>
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_FELICA_SW
|
||||
|
||||
#include "phpalFelica_Sw.h"
|
||||
#include "phpalFelica_Sw_Int.h"
|
||||
|
||||
/* Table for 4^E evaluation (E is only 2 bits, so more values are not possible). */
|
||||
static const uint8_t PH_MEMLOC_CONST_ROM aFelica_E_Table[] = {1, 4, 16, 64};
|
||||
|
||||
#define FDTF_LISTEN_SENSF_REQ(x, y) ((PHPAL_FELICA_SW_T_DELAY_US + ((x) * PHPAL_FELICA_SW_T_TIMESLOT_US)) + y) /**< NFC Forum Digital Protocol Technical Specification v1.1 : 8.7.1 : FDTF,LISTEN,SENSF_REQ */
|
||||
|
||||
static const uint16_t PH_MEMLOC_CONST_ROM aFelica_TR1_Value_Us[][2] = {
|
||||
{PHPAL_FELICA_SW_TR1_48BITS_AT212_US, PHPAL_FELICA_SW_TR1_48BITS_AT424_US},
|
||||
{PHPAL_FELICA_SW_TR1_56BITS_AT212_US, PHPAL_FELICA_SW_TR1_56BITS_AT424_US},
|
||||
{PHPAL_FELICA_SW_TR1_64BITS_AT212_US, PHPAL_FELICA_SW_TR1_64BITS_AT424_US},
|
||||
{PHPAL_FELICA_SW_TR1_72BITS_AT212_US, PHPAL_FELICA_SW_TR1_72BITS_AT424_US},
|
||||
};
|
||||
|
||||
phStatus_t phpalFelica_Sw_Init(
|
||||
phpalFelica_Sw_DataParams_t * pDataParams,
|
||||
uint16_t wSizeOfDataParams,
|
||||
void * pHalDataParams
|
||||
)
|
||||
{
|
||||
/* parameter structure length check */
|
||||
if (sizeof(phpalFelica_Sw_DataParams_t) != wSizeOfDataParams)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
PH_ASSERT_NULL (pDataParams);
|
||||
PH_ASSERT_NULL (pHalDataParams);
|
||||
|
||||
/* init private data */
|
||||
pDataParams->wId = PH_COMP_PAL_FELICA | PHPAL_FELICA_SW_ID;
|
||||
pDataParams->pHalDataParams = pHalDataParams;
|
||||
pDataParams->bIDmPMmValid = PHPAL_FELICA_SW_IDMPMM_INVALID;
|
||||
pDataParams->bLength = 0x00;
|
||||
pDataParams->bRequestCode = 0x00;
|
||||
pDataParams->bPreambleLen = PHPAL_FELICA_PREAMBLE_LEN_48BITS;
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalFelica_Sw_ReqC(
|
||||
phpalFelica_Sw_DataParams_t* pDataParams,
|
||||
uint8_t * pSystemCode,
|
||||
uint8_t bNumTimeSlots,
|
||||
uint8_t ** ppRxBuffer,
|
||||
uint16_t * pRxLength
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM aCmd[6];
|
||||
uint8_t * PH_MEMLOC_REM pRxBufferTmp = NULL;
|
||||
uint16_t PH_MEMLOC_REM wRxLengthTmp = 0;
|
||||
uint16_t PH_MEMLOC_REM wTimeOutUs;
|
||||
uint16_t PH_MEMLOC_REM wCardType = 0;
|
||||
uint16_t PH_MEMLOC_REM wTR1ValueUs;
|
||||
|
||||
/* reset validity of stored card IDs */
|
||||
pDataParams->bIDmPMmValid = PHPAL_FELICA_SW_IDMPMM_INVALID;
|
||||
|
||||
/* Reset received frame count */
|
||||
pDataParams->bTotalFrames = 0;
|
||||
|
||||
/* parameter check and timeout setting */
|
||||
if(!((bNumTimeSlots == PHPAL_FELICA_NUMSLOTS_1) ||
|
||||
(bNumTimeSlots == PHPAL_FELICA_NUMSLOTS_2) ||
|
||||
(bNumTimeSlots == PHPAL_FELICA_NUMSLOTS_4) ||
|
||||
(bNumTimeSlots == PHPAL_FELICA_NUMSLOTS_8) ||
|
||||
(bNumTimeSlots == PHPAL_FELICA_NUMSLOTS_16))
|
||||
)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
else
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_GetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_CARD_TYPE,
|
||||
&wCardType));
|
||||
/* NFC Forum Digital Protocol Technical Specification v2.3
|
||||
* 8.7.1.3 : wTimeOutUs = FDTF,LISTEN,SENSF_REQ(TSN+1U) - TR1 + (delta)TF,POLL
|
||||
* Using TR1 value @212kbps */
|
||||
if ((wCardType != PHHAL_HW_CARDTYPE_FELICA_212) && (wCardType != PHHAL_HW_CARDTYPE_FELICA_424))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_USE_CONDITION, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
if (wCardType == PHHAL_HW_CARDTYPE_FELICA_212)
|
||||
{
|
||||
wTR1ValueUs = aFelica_TR1_Value_Us[pDataParams->bPreambleLen][0];
|
||||
}
|
||||
else
|
||||
{
|
||||
wTR1ValueUs = aFelica_TR1_Value_Us[pDataParams->bPreambleLen][1];
|
||||
}
|
||||
|
||||
wTimeOutUs = FDTF_LISTEN_SENSF_REQ((((uint16_t)bNumTimeSlots) + 1U), wTR1ValueUs) - wTR1ValueUs + PHPAL_FELICA_SW_T_DELTA_F_POLL_US;
|
||||
}
|
||||
|
||||
/* build the command frame */
|
||||
aCmd[0] = 6;
|
||||
aCmd[1] = PHPAL_FELICA_SW_CMD_REQC;
|
||||
aCmd[2] = pSystemCode[0];
|
||||
aCmd[3] = pSystemCode[1];
|
||||
aCmd[4] = pDataParams->bRequestCode;
|
||||
aCmd[5] = bNumTimeSlots;
|
||||
|
||||
/* Set ReqC timeout according to the number of slots */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
wTimeOutUs));
|
||||
|
||||
if(bNumTimeSlots > PHPAL_FELICA_NUMSLOTS_1)
|
||||
{
|
||||
/* Set RX Multiple feature of HW */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_RXMULTIPLE,
|
||||
PH_ON));
|
||||
}
|
||||
|
||||
/* Exchange command */
|
||||
status = phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCmd,
|
||||
6,
|
||||
&pRxBufferTmp,
|
||||
&wRxLengthTmp);
|
||||
|
||||
if(bNumTimeSlots > PHPAL_FELICA_NUMSLOTS_1)
|
||||
{
|
||||
/* Re-Set RX Multiple feature of HW */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_RXMULTIPLE,
|
||||
PH_OFF));
|
||||
}
|
||||
|
||||
/* Error check */
|
||||
PH_CHECK_SUCCESS(status);
|
||||
|
||||
/* Check length and update info*/
|
||||
if(bNumTimeSlots > PHPAL_FELICA_NUMSLOTS_1)
|
||||
{
|
||||
/* Rx Length should be multiple of response frame size */
|
||||
if(0U != (wRxLengthTmp % PHPAL_FELICA_SW_RESP_FRAME_SIZE))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
/* assign and update IDm and PMm and length */
|
||||
*ppRxBuffer = pRxBufferTmp;
|
||||
*pRxLength = wRxLengthTmp;
|
||||
|
||||
pDataParams->bTotalFrames = (uint8_t)(wRxLengthTmp / PHPAL_FELICA_SW_RESP_FRAME_SIZE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (((wRxLengthTmp != (PHPAL_FELICA_ATQC_LENGTH + 1U)) &&
|
||||
(wRxLengthTmp != (PHPAL_FELICA_ATQC_LENGTH + PHPAL_FELICA_RD_LENGTH + 1U))) ||
|
||||
(pRxBufferTmp[0] != wRxLengthTmp) ||
|
||||
(pRxBufferTmp[1] != PHPAL_FELICA_SW_RSP_REQC))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* RC = 0 and card response with RD information */
|
||||
if((wRxLengthTmp == (PHPAL_FELICA_ATQC_LENGTH + PHPAL_FELICA_RD_LENGTH + 1U)) && (pDataParams->bRequestCode == 0U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
/* Store IDm and PMm */
|
||||
(void)memcpy(pDataParams->aIDmPMm, &pRxBufferTmp[2], (((uint32_t)(pRxBufferTmp[0])) - 2U));
|
||||
pDataParams->bIDmPMmValid = PHPAL_FELICA_SW_IDMPMM_VALID;
|
||||
|
||||
/* Remove LEN Byte and Response Byte from response and assign start position of ID */
|
||||
*ppRxBuffer = &pRxBufferTmp[PHPAL_FELICA_SW_LEN_BYTE_SIZE + PHPAL_FELICA_SW_RESP_REQC_SIZE];
|
||||
*pRxLength = (uint16_t)(((uint16_t)pRxBufferTmp[0]) - (PHPAL_FELICA_SW_LEN_BYTE_SIZE + PHPAL_FELICA_SW_RESP_REQC_SIZE));
|
||||
|
||||
pDataParams->bTotalFrames = 1;
|
||||
}
|
||||
|
||||
pDataParams->bIDmPMmValid = PHPAL_FELICA_SW_IDMPMM_VALID;
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
phStatus_t phpalFelica_Sw_GetFrameInfo(
|
||||
phpalFelica_Sw_DataParams_t* pDataParams,
|
||||
uint8_t bFrameNum,
|
||||
uint8_t * pResponseBuffer,
|
||||
uint16_t *pwStatus,
|
||||
uint8_t** ppID,
|
||||
uint8_t * pLen
|
||||
)
|
||||
{
|
||||
uint8_t PH_MEMLOC_REM bError;
|
||||
uint8_t PH_MEMLOC_REM bStartPos;
|
||||
|
||||
/* check frame number */
|
||||
if((bFrameNum > pDataParams->bTotalFrames) || (bFrameNum == 0U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
*pwStatus = PH_ERR_SUCCESS;
|
||||
|
||||
/* get start position of frame */
|
||||
bStartPos = (uint8_t)(PHPAL_FELICA_SW_RESP_FRAME_SIZE * (bFrameNum - 1U));
|
||||
|
||||
/* Check length */
|
||||
if( ((pResponseBuffer[bStartPos + PHHAL_HW_STATUS_FRAME_LEN_BYTE_POS] != (PHPAL_FELICA_ATQC_LENGTH + PHPAL_FELICA_SW_LEN_BYTE_SIZE)) &&
|
||||
(pResponseBuffer[bStartPos + PHHAL_HW_STATUS_FRAME_LEN_BYTE_POS] != (PHPAL_FELICA_ATQC_LENGTH + PHPAL_FELICA_RD_LENGTH + PHPAL_FELICA_SW_LEN_BYTE_SIZE))) ||
|
||||
(pResponseBuffer[bStartPos + 1U] != PHPAL_FELICA_SW_RSP_REQC))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* RC = 0 and card response with RD information */
|
||||
if((pResponseBuffer[bStartPos + PHHAL_HW_STATUS_FRAME_LEN_BYTE_POS] == (PHPAL_FELICA_ATQC_LENGTH + PHPAL_FELICA_RD_LENGTH + PHPAL_FELICA_SW_LEN_BYTE_SIZE)) && (pDataParams->bRequestCode == 0U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* Extract error from Status byte */
|
||||
bError = pResponseBuffer[(bStartPos) + PHHAL_HW_STATUS_FRAME_ERR_BYTE_POS ] & PHHAL_HW_STATUS_FRAME_ERR_MASK;
|
||||
|
||||
if(bError != 0x00U)
|
||||
{
|
||||
/* check for contact less error */
|
||||
if(0U != (bError & PHHAL_HW_STATUS_FRAME_CL_ERR_POS))
|
||||
{
|
||||
/* check for protocol error */
|
||||
if(0U != (bError & PHHAL_HW_STATUS_FRAME_PROT_ERR_POS))
|
||||
{
|
||||
*pwStatus = PH_ERR_PROTOCOL_ERROR;
|
||||
}
|
||||
/* check for collision error */
|
||||
else if(0U != (bError & PHHAL_HW_STATUS_FRAME_COLL_ERR_POS))
|
||||
{
|
||||
*pwStatus = PH_ERR_COLLISION_ERROR;
|
||||
}
|
||||
/* check for Integrity error */
|
||||
else if(0U != (bError & PHHAL_HW_STATUS_FRAME_DATA_ERR_POS))
|
||||
{
|
||||
*pwStatus = PH_ERR_INTEGRITY_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If CL Error is set and no Protocol, Collision, Integrity flag is set */
|
||||
return (PH_ERR_PROTOCOL_ERROR | PH_COMP_PAL_FELICA);
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* Length error */
|
||||
*pwStatus = PH_ERR_LENGTH_ERROR;
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Remove LEN Byte and Response Byte (0x01) from response and assign start position of ID */
|
||||
*ppID = &pResponseBuffer[bStartPos + (PHPAL_FELICA_SW_LEN_BYTE_SIZE + PHPAL_FELICA_SW_RESP_REQC_SIZE)];
|
||||
*pLen = pResponseBuffer[bStartPos + PHHAL_HW_STATUS_FRAME_LEN_BYTE_POS] - (PHPAL_FELICA_SW_LEN_BYTE_SIZE + PHPAL_FELICA_SW_RESP_REQC_SIZE);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalFelica_Sw_SetSerialNo(
|
||||
phpalFelica_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pIDmPMm
|
||||
)
|
||||
{
|
||||
|
||||
pDataParams->bIDmPMmValid = PHPAL_FELICA_SW_IDMPMM_VALID;
|
||||
/* copy IDm and PMm */
|
||||
(void)memcpy(pDataParams->aIDmPMm, pIDmPMm, (PHPAL_FELICA_IDM_LENGTH + PHPAL_FELICA_PMM_LENGTH));
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
|
||||
}
|
||||
|
||||
phStatus_t phpalFelica_Sw_ActivateCard(
|
||||
phpalFelica_Sw_DataParams_t* pDataParams,
|
||||
uint8_t* pIDmPMm,
|
||||
uint8_t bIDmPMmLength,
|
||||
uint8_t * pSystemCode,
|
||||
uint8_t bNumTimeSlots,
|
||||
uint8_t * pRxBuffer,
|
||||
uint8_t * pRxLength,
|
||||
uint8_t * pMoreCardsAvailable
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
uint8_t * PH_MEMLOC_REM pId = NULL;
|
||||
uint8_t * PH_MEMLOC_REM pRxBuff = NULL;
|
||||
uint16_t PH_MEMLOC_REM wRxLen = 0;
|
||||
uint8_t PH_MEMLOC_REM bTemp;
|
||||
uint16_t PH_MEMLOC_REM wFrameStatus;
|
||||
|
||||
*pRxLength = 0;
|
||||
*pMoreCardsAvailable = 0;
|
||||
|
||||
/* if serial number is given only store it */
|
||||
if (0U != (bIDmPMmLength))
|
||||
{
|
||||
/* check if IDm length is valid. */
|
||||
if (bIDmPMmLength != (PHPAL_FELICA_IDM_LENGTH + PHPAL_FELICA_PMM_LENGTH))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* Store IDm/PMm */
|
||||
(void)memcpy(pDataParams->aIDmPMm, pIDmPMm, bIDmPMmLength);
|
||||
pDataParams->bIDmPMmValid = PHPAL_FELICA_SW_IDMPMM_VALID;
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
do{
|
||||
/* RequestC == ReqC command (not requesting the system code) */
|
||||
status = phpalFelica_Sw_ReqC(
|
||||
pDataParams,
|
||||
pSystemCode,
|
||||
bNumTimeSlots,
|
||||
&pRxBuff,
|
||||
&wRxLen);
|
||||
|
||||
if(bNumTimeSlots > PHPAL_FELICA_NUMSLOTS_1)
|
||||
{
|
||||
if(pDataParams->bTotalFrames > 1U)
|
||||
{
|
||||
*pMoreCardsAvailable = 1;
|
||||
}
|
||||
|
||||
/* get total number of response frame */
|
||||
bTemp = pDataParams->bTotalFrames;
|
||||
|
||||
while(0U != bTemp)
|
||||
{
|
||||
*pRxLength = 0x00;
|
||||
wFrameStatus = 0x00;
|
||||
/* retrieve IDmPMm one by one for all frames */
|
||||
PH_CHECK_SUCCESS_FCT(status, phpalFelica_Sw_GetFrameInfo(
|
||||
pDataParams,
|
||||
bTemp,
|
||||
pRxBuff,
|
||||
&wFrameStatus,
|
||||
&pId,
|
||||
pRxLength));
|
||||
|
||||
status = wFrameStatus;
|
||||
/* store only one valid response and return */
|
||||
if(wFrameStatus == PH_ERR_SUCCESS)
|
||||
{
|
||||
*pRxLength = PHPAL_FELICA_IDM_LENGTH + PHPAL_FELICA_PMM_LENGTH;
|
||||
(void)memcpy(pRxBuffer, pId, (PHPAL_FELICA_IDM_LENGTH + PHPAL_FELICA_PMM_LENGTH));
|
||||
(void)memcpy(pDataParams->aIDmPMm, pId, (PHPAL_FELICA_IDM_LENGTH + PHPAL_FELICA_PMM_LENGTH));
|
||||
pDataParams->bIDmPMmValid = PHPAL_FELICA_SW_IDMPMM_VALID;
|
||||
return status;
|
||||
}
|
||||
bTemp--;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
*pRxLength = PHPAL_FELICA_IDM_LENGTH + PHPAL_FELICA_PMM_LENGTH;
|
||||
(void)memcpy(pRxBuffer, pRxBuff, (PHPAL_FELICA_IDM_LENGTH + PHPAL_FELICA_PMM_LENGTH));
|
||||
(void)memcpy(pDataParams->aIDmPMm, pRxBuff, (PHPAL_FELICA_IDM_LENGTH + PHPAL_FELICA_PMM_LENGTH));
|
||||
pDataParams->bIDmPMmValid = PHPAL_FELICA_SW_IDMPMM_VALID;
|
||||
|
||||
return status;
|
||||
}
|
||||
}
|
||||
/* check for availability of more card */
|
||||
if((status & PH_ERR_MASK) == PH_ERR_COLLISION_ERROR)
|
||||
{
|
||||
*pMoreCardsAvailable = 1;
|
||||
bNumTimeSlots = (bNumTimeSlots << 1U) + 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
return status;
|
||||
}
|
||||
}while (bNumTimeSlots <= PHPAL_FELICA_NUMSLOTS_16);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
phStatus_t phpalFelica_Sw_Exchange(
|
||||
phpalFelica_Sw_DataParams_t* pDataParams,
|
||||
uint16_t wOption,
|
||||
uint16_t wN,
|
||||
uint8_t* pTxBuffer,
|
||||
uint16_t wTxLength,
|
||||
uint8_t ** ppRxBuffer,
|
||||
uint16_t * pRxLength
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM aHeader[2];
|
||||
uint16_t PH_MEMLOC_REM wCmd;
|
||||
uint32_t PH_MEMLOC_REM dwTimeoutUs;
|
||||
uint8_t PH_MEMLOC_REM bTparam;
|
||||
uint8_t PH_MEMLOC_REM bA;
|
||||
uint8_t PH_MEMLOC_REM bB;
|
||||
uint8_t PH_MEMLOC_REM bE;
|
||||
uint8_t * PH_MEMLOC_REM pPMm = NULL;
|
||||
uint32_t PH_MEMLOC_REM dwTOut;
|
||||
|
||||
/* [len][cmd] [IDm ... 8 bytes] [cmd parameters ...] */
|
||||
|
||||
/* Check if we do have an IDm */
|
||||
if (pDataParams->bIDmPMmValid == PHPAL_FELICA_SW_IDMPMM_INVALID)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* Parameter check */
|
||||
if ((wTxLength + /* */ 2U) > PHPAL_FELICA_TXLENGTH_MAX)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* If the PH_EXCHANGE_LEAVE_BUFFER_BIT is NOT set, wOption is:
|
||||
~ PH_EXCHANGE_DEFAULT: we have the command byte and eventually parameter bytes (data),
|
||||
how ever, we already have all data to exchange the complete frame.
|
||||
~ PH_EXCHANGE_BUFFER_FIRST: we have the command byte and eventually parameter bytes (data),
|
||||
but the callee wants to transmit some more.
|
||||
pDataParams->bLength < 2 -> the cmd byte was not transmitted yet
|
||||
*/
|
||||
if ((0U == ((wOption & PH_EXCHANGE_LEAVE_BUFFER_BIT))) || (pDataParams->bLength < 2U))
|
||||
{
|
||||
/* If there is nothing to transmit, we are done. */
|
||||
if (wTxLength == 0U)
|
||||
{
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
/* Prepare header */
|
||||
aHeader[0] = 0x00; /* This is just a dummy which is updated with the correct value later on,
|
||||
when the last chunk is ready to transmit. */
|
||||
aHeader[1] = pTxBuffer[0];
|
||||
|
||||
/* Buffer the header */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_BUFFER_FIRST,
|
||||
aHeader,
|
||||
2,
|
||||
ppRxBuffer,
|
||||
pRxLength));
|
||||
|
||||
/* until now, we have transmitted 2 bytes: */
|
||||
pDataParams->bLength = 2;
|
||||
|
||||
/* following Hw_Echange calls shall not overwrite already buffered data */
|
||||
wOption |= PH_EXCHANGE_LEAVE_BUFFER_BIT;
|
||||
|
||||
/* Check if IDm has to be send */
|
||||
wCmd = (uint16_t)pTxBuffer[0];
|
||||
switch (wCmd)
|
||||
{
|
||||
case PHPAL_FELICA_SW_CMD_REQ_RESP:
|
||||
case PHPAL_FELICA_SW_CMD_REQ_SERVICE:
|
||||
case PHPAL_FELICA_SW_CMD_READ:
|
||||
case PHPAL_FELICA_SW_CMD_WRITE:
|
||||
case PHPAL_FELICA_SW_CMD_AUTH1:
|
||||
case PHPAL_FELICA_SW_CMD_AUTH2:
|
||||
|
||||
/* If there is no more parameter bytes (data) to send, we adjust pointer and length
|
||||
for the LAST Exchange, the IDm */
|
||||
if (wTxLength == 1U)
|
||||
{
|
||||
pTxBuffer = pDataParams->aIDmPMm;
|
||||
wTxLength = PHPAL_FELICA_IDM_LENGTH;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set pointer and length for the LAST exchange. */
|
||||
pTxBuffer++;
|
||||
wTxLength = wTxLength - 1u;
|
||||
|
||||
/* Transmit the IDm */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_BUFFER_CONT,
|
||||
pDataParams->aIDmPMm,
|
||||
PHPAL_FELICA_IDM_LENGTH,
|
||||
ppRxBuffer,
|
||||
pRxLength));
|
||||
|
||||
pDataParams->bLength = pDataParams->bLength + PHPAL_FELICA_IDM_LENGTH;
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
|
||||
/* Set pointer and length for the LAST exchange. */
|
||||
pTxBuffer++;
|
||||
wTxLength = wTxLength - 1u;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* command byte already buffered */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_TXBUFFER_OFFSET, 0x01));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_GetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_TXBUFFER, &wCmd));
|
||||
}
|
||||
|
||||
/* Length check */
|
||||
if ((pDataParams->bLength + wTxLength) > PHPAL_FELICA_TXLENGTH_MAX)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_LENGTH_ERROR, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* If the PH_EXCHANGE_BUFFERED_BIT IS set, wOption is:
|
||||
~ PH_EXCHANGE_BUFFER_FIRST, or
|
||||
~ PH_EXCHANGE_BUFFER_CONT: This means that there is data which shall be put into the
|
||||
buffer but not to be sent yet since more data will follow. */
|
||||
if (0U != (wOption & PH_EXCHANGE_BUFFERED_BIT))
|
||||
{
|
||||
if (wTxLength > 0U)
|
||||
{
|
||||
/* Exchange command */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
wOption,
|
||||
pTxBuffer,
|
||||
wTxLength,
|
||||
ppRxBuffer,
|
||||
pRxLength));
|
||||
|
||||
pDataParams->bLength = pDataParams->bLength + (uint8_t)wTxLength;
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
/* If the PH_EXCHANGE_BUFFERED_BIT is NOT set, wOption is:
|
||||
~ PH_EXCHANGE_DEFAULT, or
|
||||
~ PH_EXCHANGE_BUFFER_LAST: This means that either this is the last (or only) chunk
|
||||
of command parameters (data), which also could be of zero bytes.
|
||||
|
||||
So this is the last chunk and we should received a response,
|
||||
which we extrakt the IDm bytes from and also check them. */
|
||||
pDataParams->bLength = pDataParams->bLength + (uint8_t)(wTxLength);
|
||||
|
||||
/* Update the length byte which had been sent before */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_TXBUFFER_OFFSET, 0x00));
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(pDataParams->pHalDataParams, PHHAL_HW_CONFIG_TXBUFFER, (uint16_t)pDataParams->bLength));
|
||||
|
||||
/* Reset precached length */
|
||||
pDataParams->bLength = 0x00;
|
||||
|
||||
/* Get stored PMm */
|
||||
pPMm = &pDataParams->aIDmPMm[PHPAL_FELICA_IDM_LENGTH];
|
||||
|
||||
/* Command and PMm evaluation */
|
||||
switch(wCmd)
|
||||
{
|
||||
case PHPAL_FELICA_SW_CMD_REQ_SERVICE:
|
||||
bTparam = pPMm[2];
|
||||
break;
|
||||
case PHPAL_FELICA_SW_CMD_REQ_RESP:
|
||||
bTparam = pPMm[3];
|
||||
break;
|
||||
case PHPAL_FELICA_SW_CMD_AUTH1:
|
||||
case PHPAL_FELICA_SW_CMD_AUTH2:
|
||||
bTparam = pPMm[4];
|
||||
break;
|
||||
case PHPAL_FELICA_SW_CMD_READ:
|
||||
case PHPAL_FELICA_SW_CMD_READ_SECF:
|
||||
bTparam = pPMm[5];
|
||||
break;
|
||||
case PHPAL_FELICA_SW_CMD_WRITE:
|
||||
case PHPAL_FELICA_SW_CMD_WRITE_SECF:
|
||||
bTparam = pPMm[6];
|
||||
break;
|
||||
default:
|
||||
bTparam = pPMm[7];
|
||||
break;
|
||||
}
|
||||
|
||||
/* Get timing parameters */
|
||||
bA = bTparam & 0x07U;
|
||||
bB = (bTparam >> 3U) & 0x07U;
|
||||
bE = (bTparam >> 6U) & 0x03U;
|
||||
|
||||
/* Timeout calculation */
|
||||
/* Response time = T x [(B + 1U) x n + (A + 1U)] x 4^E */
|
||||
dwTOut = ((((uint32_t)bB + 1U) * (uint32_t)wN) + ((uint32_t)bA + 1U));
|
||||
dwTimeoutUs = (uint32_t)(PHPAL_FELICA_SW_TIME_T_US * dwTOut * aFelica_E_Table[bE]);
|
||||
dwTimeoutUs = dwTimeoutUs + PHPAL_FELICA_SW_DELTA_TIME_T_US;
|
||||
|
||||
/* Timeout setting in Milliseconds */
|
||||
if (dwTimeoutUs > 0xFFFFU)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_MS,
|
||||
(uint16_t)(dwTimeoutUs / 1000U)));
|
||||
}
|
||||
/* Timeout setting in Microseconds */
|
||||
else
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
(uint16_t)dwTimeoutUs));
|
||||
}
|
||||
|
||||
/* Exchange command */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_BUFFER_LAST,
|
||||
pTxBuffer,
|
||||
wTxLength,
|
||||
ppRxBuffer,
|
||||
pRxLength));
|
||||
|
||||
/* Check length */
|
||||
if ((*pRxLength < 1U) || ((*ppRxBuffer)[0] != *pRxLength))
|
||||
{
|
||||
*pRxLength = 0;
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* Skip length */
|
||||
--(*pRxLength);
|
||||
++(*ppRxBuffer);
|
||||
|
||||
/* Check response code */
|
||||
if ((*pRxLength < 1U) || ((*ppRxBuffer)[0] != (wCmd + 1U)))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* Skip response code */
|
||||
--(*pRxLength);
|
||||
++(*ppRxBuffer);
|
||||
|
||||
/* Check and skip IDm if received */
|
||||
switch (wCmd)
|
||||
{
|
||||
case PHPAL_FELICA_SW_CMD_REQ_RESP:
|
||||
case PHPAL_FELICA_SW_CMD_REQ_SERVICE:
|
||||
case PHPAL_FELICA_SW_CMD_READ:
|
||||
case PHPAL_FELICA_SW_CMD_WRITE:
|
||||
case PHPAL_FELICA_SW_CMD_AUTH1:
|
||||
|
||||
/* Protocol error check */
|
||||
if (*pRxLength < PHPAL_FELICA_IDM_LENGTH)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* We can only check the IDm if we have a valid one stored */
|
||||
if (memcmp(*ppRxBuffer, pDataParams->aIDmPMm, PHPAL_FELICA_IDM_LENGTH) != 0)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* Skip IDm */
|
||||
*pRxLength = *pRxLength - PHPAL_FELICA_IDM_LENGTH;
|
||||
*ppRxBuffer = *ppRxBuffer + PHPAL_FELICA_IDM_LENGTH;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalFelica_Sw_SetConfig(
|
||||
phpalFelica_Sw_DataParams_t* pDataParams,
|
||||
uint16_t wConfig,
|
||||
uint16_t wValue
|
||||
)
|
||||
{
|
||||
switch(wConfig)
|
||||
{
|
||||
case PHPAL_FELICA_CONFIG_RC:
|
||||
if(((uint8_t)wValue != 0x00U) && ((uint8_t)wValue != 0x01U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
pDataParams->bRequestCode = (uint8_t)(wValue);
|
||||
break;
|
||||
|
||||
case PHPAL_FELICA_PREAMBLE_LENGTH:
|
||||
if(!((wValue == PHPAL_FELICA_PREAMBLE_LEN_48BITS) ||
|
||||
(wValue == PHPAL_FELICA_PREAMBLE_LEN_56BITS) ||
|
||||
(wValue == PHPAL_FELICA_PREAMBLE_LEN_64BITS) ||
|
||||
(wValue == PHPAL_FELICA_PREAMBLE_LEN_72BITS))
|
||||
)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
pDataParams->bPreambleLen = (uint8_t)(wValue);
|
||||
break;
|
||||
|
||||
default:
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_PARAMETER, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalFelica_Sw_GetConfig(
|
||||
phpalFelica_Sw_DataParams_t* pDataParams,
|
||||
uint16_t wConfig,
|
||||
uint16_t * pValue
|
||||
)
|
||||
{
|
||||
switch(wConfig)
|
||||
{
|
||||
case PHPAL_FELICA_CONFIG_RC:
|
||||
*pValue = (uint16_t)pDataParams->bRequestCode;
|
||||
break;
|
||||
|
||||
case PH_PALFELICA_CONFIG_NUM_RESPONSE_FRAMES:
|
||||
*pValue = (uint16_t)pDataParams->bTotalFrames;
|
||||
break;
|
||||
default:
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_UNSUPPORTED_PARAMETER, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalFelica_Sw_GetSerialNo(
|
||||
phpalFelica_Sw_DataParams_t* pDataParams,
|
||||
uint8_t * pIDmPMmOut,
|
||||
uint8_t * pLenIDmPMmOut
|
||||
)
|
||||
{
|
||||
/* Return an error if IDm and PMm are not valid */
|
||||
if (pDataParams->bIDmPMmValid == PHPAL_FELICA_SW_IDMPMM_INVALID)
|
||||
{
|
||||
*pLenIDmPMmOut = 0;
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_USE_CONDITION, PH_COMP_PAL_FELICA);
|
||||
}
|
||||
|
||||
/* copy the IDm and PMm */
|
||||
(void)memcpy(pIDmPMmOut, pDataParams->aIDmPMm, PHPAL_FELICA_IDM_LENGTH + PHPAL_FELICA_PMM_LENGTH);
|
||||
*pLenIDmPMmOut = PHPAL_FELICA_IDM_LENGTH + PHPAL_FELICA_PMM_LENGTH;
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
#endif /* NXPBUILD__PHPAL_FELICA_SW */
|
||||
@ -0,0 +1,26 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>lpc_chip_175x_6x</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
@ -0,0 +1,687 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_TSI_V4_H_
|
||||
#define _FSL_TSI_V4_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup tsi_v4_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief TSI driver version */
|
||||
#define FSL_TSI_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief TSI status flags macro collection */
|
||||
#define ALL_FLAGS_MASK (TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK)
|
||||
|
||||
/*! @brief resistor bit shift in EXTCHRG bit-field */
|
||||
#define TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT TSI_GENCS_EXTCHRG_SHIFT
|
||||
|
||||
/*! @brief filter bits shift in EXTCHRG bit-field */
|
||||
#define TSI_V4_EXTCHRG_FILTER_BITS_SHIFT (1U + TSI_GENCS_EXTCHRG_SHIFT)
|
||||
|
||||
/*! @brief macro of clearing the resistor bit in EXTCHRG bit-field */
|
||||
#define TSI_V4_EXTCHRG_RESISTOR_BIT_CLEAR \
|
||||
((uint32_t)((~(ALL_FLAGS_MASK | TSI_GENCS_EXTCHRG_MASK)) | (3U << TSI_V4_EXTCHRG_FILTER_BITS_SHIFT)))
|
||||
|
||||
/*! @brief macro of clearing the filter bits in EXTCHRG bit-field */
|
||||
#define TSI_V4_EXTCHRG_FILTER_BITS_CLEAR \
|
||||
((uint32_t)((~(ALL_FLAGS_MASK | TSI_GENCS_EXTCHRG_MASK)) | (1U << TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT)))
|
||||
|
||||
/*!
|
||||
* @brief TSI number of scan intervals for each electrode.
|
||||
*
|
||||
* These constants define the tsi number of consecutive scans in a TSI instance for each electrode.
|
||||
*/
|
||||
typedef enum _tsi_n_consecutive_scans
|
||||
{
|
||||
kTSI_ConsecutiveScansNumber_1time = 0U, /*!< Once per electrode */
|
||||
kTSI_ConsecutiveScansNumber_2time = 1U, /*!< Twice per electrode */
|
||||
kTSI_ConsecutiveScansNumber_3time = 2U, /*!< 3 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_4time = 3U, /*!< 4 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_5time = 4U, /*!< 5 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_6time = 5U, /*!< 6 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_7time = 6U, /*!< 7 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_8time = 7U, /*!< 8 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_9time = 8U, /*!< 9 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_10time = 9U, /*!< 10 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_11time = 10U, /*!< 11 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_12time = 11U, /*!< 12 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_13time = 12U, /*!< 13 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_14time = 13U, /*!< 14 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_15time = 14U, /*!< 15 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_16time = 15U, /*!< 16 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_17time = 16U, /*!< 17 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_18time = 17U, /*!< 18 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_19time = 18U, /*!< 19 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_20time = 19U, /*!< 20 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_21time = 20U, /*!< 21 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_22time = 21U, /*!< 22 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_23time = 22U, /*!< 23 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_24time = 23U, /*!< 24 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_25time = 24U, /*!< 25 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_26time = 25U, /*!< 26 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_27time = 26U, /*!< 27 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_28time = 27U, /*!< 28 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_29time = 28U, /*!< 29 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_30time = 29U, /*!< 30 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_31time = 30U, /*!< 31 times consecutive scan */
|
||||
kTSI_ConsecutiveScansNumber_32time = 31U /*!< 32 times consecutive scan */
|
||||
} tsi_n_consecutive_scans_t;
|
||||
|
||||
/*!
|
||||
* @brief TSI electrode oscillator prescaler.
|
||||
*
|
||||
* These constants define the TSI electrode oscillator prescaler in a TSI instance.
|
||||
*/
|
||||
typedef enum _tsi_electrode_osc_prescaler
|
||||
{
|
||||
kTSI_ElecOscPrescaler_1div = 0U, /*!< Electrode oscillator frequency divided by 1 */
|
||||
kTSI_ElecOscPrescaler_2div = 1U, /*!< Electrode oscillator frequency divided by 2 */
|
||||
kTSI_ElecOscPrescaler_4div = 2U, /*!< Electrode oscillator frequency divided by 4 */
|
||||
kTSI_ElecOscPrescaler_8div = 3U, /*!< Electrode oscillator frequency divided by 8 */
|
||||
kTSI_ElecOscPrescaler_16div = 4U, /*!< Electrode oscillator frequency divided by 16 */
|
||||
kTSI_ElecOscPrescaler_32div = 5U, /*!< Electrode oscillator frequency divided by 32 */
|
||||
kTSI_ElecOscPrescaler_64div = 6U, /*!< Electrode oscillator frequency divided by 64 */
|
||||
kTSI_ElecOscPrescaler_128div = 7U /*!< Electrode oscillator frequency divided by 128 */
|
||||
} tsi_electrode_osc_prescaler_t;
|
||||
|
||||
/*!
|
||||
* @brief TSI analog mode select.
|
||||
*
|
||||
* Set up TSI analog modes in a TSI instance.
|
||||
*/
|
||||
typedef enum _tsi_analog_mode
|
||||
{
|
||||
kTSI_AnalogModeSel_Capacitive = 0U, /*!< Active TSI capacitive sensing mode */
|
||||
kTSI_AnalogModeSel_NoiseNoFreqLim = 4U, /*!< Single threshold noise detection mode with no freq. limitation. */
|
||||
kTSI_AnalogModeSel_NoiseFreqLim = 8U, /*!< Single threshold noise detection mode with freq. limitation. */
|
||||
kTSI_AnalogModeSel_AutoNoise = 12U /*!< Active TSI analog in automatic noise detection mode */
|
||||
} tsi_analog_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief TSI Reference oscillator charge and discharge current select.
|
||||
*
|
||||
* These constants define the TSI Reference oscillator charge current select in a TSI (REFCHRG) instance.
|
||||
*/
|
||||
typedef enum _tsi_reference_osc_charge_current
|
||||
{
|
||||
kTSI_RefOscChargeCurrent_500nA = 0U, /*!< Reference oscillator charge current is 500 µA */
|
||||
kTSI_RefOscChargeCurrent_1uA = 1U, /*!< Reference oscillator charge current is 1 µA */
|
||||
kTSI_RefOscChargeCurrent_2uA = 2U, /*!< Reference oscillator charge current is 2 µA */
|
||||
kTSI_RefOscChargeCurrent_4uA = 3U, /*!< Reference oscillator charge current is 4 µA */
|
||||
kTSI_RefOscChargeCurrent_8uA = 4U, /*!< Reference oscillator charge current is 8 µA */
|
||||
kTSI_RefOscChargeCurrent_16uA = 5U, /*!< Reference oscillator charge current is 16 µA */
|
||||
kTSI_RefOscChargeCurrent_32uA = 6U, /*!< Reference oscillator charge current is 32 µA */
|
||||
kTSI_RefOscChargeCurrent_64uA = 7U /*!< Reference oscillator charge current is 64 µA */
|
||||
} tsi_reference_osc_charge_current_t;
|
||||
|
||||
/*!
|
||||
* @brief TSI oscilator's voltage rails.
|
||||
*
|
||||
* These bits indicate the oscillator's voltage rails.
|
||||
*/
|
||||
typedef enum _tsi_osc_voltage_rails
|
||||
{
|
||||
kTSI_OscVolRailsOption_0 = 0U, /*!< DVOLT value option 0, the value may differ on different platforms */
|
||||
kTSI_OscVolRailsOption_1 = 1U, /*!< DVOLT value option 1, the value may differ on different platforms */
|
||||
kTSI_OscVolRailsOption_2 = 2U, /*!< DVOLT value option 2, the value may differ on different platforms */
|
||||
kTSI_OscVolRailsOption_3 = 3U /*!< DVOLT value option 3, the value may differ on different platforms */
|
||||
} tsi_osc_voltage_rails_t;
|
||||
|
||||
/*!
|
||||
* @brief TSI External oscillator charge and discharge current select.
|
||||
*
|
||||
* These bits indicate the electrode oscillator charge and discharge current value
|
||||
* in TSI (EXTCHRG) instance.
|
||||
*/
|
||||
typedef enum _tsi_external_osc_charge_current
|
||||
{
|
||||
kTSI_ExtOscChargeCurrent_500nA = 0U, /*!< External oscillator charge current is 500 µA */
|
||||
kTSI_ExtOscChargeCurrent_1uA = 1U, /*!< External oscillator charge current is 1 µA */
|
||||
kTSI_ExtOscChargeCurrent_2uA = 2U, /*!< External oscillator charge current is 2 µA */
|
||||
kTSI_ExtOscChargeCurrent_4uA = 3U, /*!< External oscillator charge current is 4 µA */
|
||||
kTSI_ExtOscChargeCurrent_8uA = 4U, /*!< External oscillator charge current is 8 µA */
|
||||
kTSI_ExtOscChargeCurrent_16uA = 5U, /*!< External oscillator charge current is 16 µA */
|
||||
kTSI_ExtOscChargeCurrent_32uA = 6U, /*!< External oscillator charge current is 32 µA */
|
||||
kTSI_ExtOscChargeCurrent_64uA = 7U /*!< External oscillator charge current is 64 µA */
|
||||
} tsi_external_osc_charge_current_t;
|
||||
|
||||
/*!
|
||||
* @brief TSI series resistance RS value select.
|
||||
*
|
||||
* These bits indicate the electrode RS series resistance for the noise mode
|
||||
* in TSI (EXTCHRG) instance.
|
||||
*/
|
||||
typedef enum _tsi_series_resistance
|
||||
{
|
||||
kTSI_SeriesResistance_32k = 0U, /*!< Series Resistance is 32 kilo ohms */
|
||||
kTSI_SeriesResistance_187k = 1U /*!< Series Resistance is 18 7 kilo ohms */
|
||||
} tsi_series_resistor_t;
|
||||
|
||||
/*!
|
||||
* @brief TSI series filter bits select.
|
||||
*
|
||||
* These bits indicate the count of the filter bits
|
||||
* in TSI noise mode EXTCHRG[2:1] bits
|
||||
*/
|
||||
typedef enum _tsi_filter_bits
|
||||
{
|
||||
kTSI_FilterBits_3 = 0U, /*!< 3 filter bits, 8 peaks increments the cnt+1 */
|
||||
kTSI_FilterBits_2 = 1U, /*!< 2 filter bits, 4 peaks increments the cnt+1 */
|
||||
kTSI_FilterBits_1 = 2U, /*!< 1 filter bits, 2 peaks increments the cnt+1 */
|
||||
kTSI_FilterBits_0 = 3U /*!< no filter bits,1 peak increments the cnt+1 */
|
||||
} tsi_filter_bits_t;
|
||||
|
||||
/*! @brief TSI status flags. */
|
||||
typedef enum _tsi_status_flags
|
||||
{
|
||||
kTSI_EndOfScanFlag = TSI_GENCS_EOSF_MASK, /*!< End-Of-Scan flag */
|
||||
kTSI_OutOfRangeFlag = (int)TSI_GENCS_OUTRGF_MASK /*!< Out-Of-Range flag */
|
||||
} tsi_status_flags_t;
|
||||
|
||||
/*! @brief TSI feature interrupt source.*/
|
||||
typedef enum _tsi_interrupt_enable
|
||||
{
|
||||
kTSI_GlobalInterruptEnable = 1U, /*!< TSI module global interrupt */
|
||||
kTSI_OutOfRangeInterruptEnable = 2U, /*!< Out-Of-Range interrupt */
|
||||
kTSI_EndOfScanInterruptEnable = 4U /*!< End-Of-Scan interrupt */
|
||||
} tsi_interrupt_enable_t;
|
||||
|
||||
/*! @brief TSI calibration data storage. */
|
||||
typedef struct _tsi_calibration_data
|
||||
{
|
||||
uint16_t calibratedData[FSL_FEATURE_TSI_CHANNEL_COUNT]; /*!< TSI calibration data storage buffer */
|
||||
} tsi_calibration_data_t;
|
||||
|
||||
/*!
|
||||
* @brief TSI configuration structure.
|
||||
*
|
||||
* This structure contains the settings for the most common TSI configurations including
|
||||
* the TSI module charge currents, number of scans, thresholds, and so on.
|
||||
*/
|
||||
typedef struct _tsi_config
|
||||
{
|
||||
uint16_t thresh; /*!< High threshold. */
|
||||
uint16_t thresl; /*!< Low threshold. */
|
||||
tsi_electrode_osc_prescaler_t prescaler; /*!< Prescaler */
|
||||
tsi_external_osc_charge_current_t extchrg; /*!< Electrode charge current */
|
||||
tsi_reference_osc_charge_current_t refchrg; /*!< Reference charge current */
|
||||
tsi_n_consecutive_scans_t nscn; /*!< Number of scans. */
|
||||
tsi_analog_mode_t mode; /*!< TSI mode of operation. */
|
||||
tsi_osc_voltage_rails_t dvolt; /*!< Oscillator's voltage rails. */
|
||||
tsi_series_resistor_t resistor; /*!< Series resistance value */
|
||||
tsi_filter_bits_t filter; /*!< Noise mode filter bits */
|
||||
} tsi_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Initializes hardware.
|
||||
*
|
||||
* @details Initializes the peripheral to the targeted state specified by parameter configuration,
|
||||
* such as sets prescalers, number of scans, clocks, delta voltage
|
||||
* series resistor, filter bits, reference, and electrode charge current and threshold.
|
||||
* @param base TSI peripheral base address.
|
||||
* @param config Pointer to TSI module configuration structure.
|
||||
* @return none
|
||||
*/
|
||||
void TSI_Init(TSI_Type *base, const tsi_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief De-initializes hardware.
|
||||
*
|
||||
* @details De-initializes the peripheral to default state.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @return none
|
||||
*/
|
||||
void TSI_Deinit(TSI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Gets the TSI normal mode user configuration structure.
|
||||
* This interface sets userConfig structure to a default value. The configuration structure only
|
||||
* includes the settings for the whole TSI.
|
||||
* The user configure is set to these values:
|
||||
* @code
|
||||
userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
|
||||
userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA;
|
||||
userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
|
||||
userConfig->nscn = kTSI_ConsecutiveScansNumber_10time;
|
||||
userConfig->mode = kTSI_AnalogModeSel_Capacitive;
|
||||
userConfig->dvolt = kTSI_OscVolRailsOption_0;
|
||||
userConfig->thresh = 0U;
|
||||
userConfig->thresl = 0U;
|
||||
@endcode
|
||||
*
|
||||
* @param userConfig Pointer to the TSI user configuration structure.
|
||||
*/
|
||||
void TSI_GetNormalModeDefaultConfig(tsi_config_t *userConfig);
|
||||
|
||||
/*!
|
||||
* @brief Gets the TSI low power mode default user configuration structure.
|
||||
* This interface sets userConfig structure to a default value. The configuration structure only
|
||||
* includes the settings for the whole TSI.
|
||||
* The user configure is set to these values:
|
||||
* @code
|
||||
userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
|
||||
userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA;
|
||||
userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
|
||||
userConfig->nscn = kTSI_ConsecutiveScansNumber_10time;
|
||||
userConfig->mode = kTSI_AnalogModeSel_Capacitive;
|
||||
userConfig->dvolt = kTSI_OscVolRailsOption_0;
|
||||
userConfig->thresh = 400U;
|
||||
userConfig->thresl = 0U;
|
||||
@endcode
|
||||
*
|
||||
* @param userConfig Pointer to the TSI user configuration structure.
|
||||
*/
|
||||
void TSI_GetLowPowerModeDefaultConfig(tsi_config_t *userConfig);
|
||||
|
||||
/*!
|
||||
* @brief Hardware calibration.
|
||||
*
|
||||
* @details Calibrates the peripheral to fetch the initial counter value of
|
||||
* the enabled electrodes.
|
||||
* This API is mostly used at initial application setup. Call
|
||||
* this function after the \ref TSI_Init API and use the calibrated
|
||||
* counter values to set up applications (such as to determine
|
||||
* under which counter value we can confirm a touch event occurs).
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param calBuff Data buffer that store the calibrated counter value.
|
||||
* @return none
|
||||
*
|
||||
*/
|
||||
void TSI_Calibrate(TSI_Type *base, tsi_calibration_data_t *calBuff);
|
||||
|
||||
/*!
|
||||
* @brief Enables the TSI interrupt requests.
|
||||
* @param base TSI peripheral base address.
|
||||
* @param mask interrupt source
|
||||
* The parameter can be combination of the following source if defined:
|
||||
* @arg kTSI_GlobalInterruptEnable
|
||||
* @arg kTSI_EndOfScanInterruptEnable
|
||||
* @arg kTSI_OutOfRangeInterruptEnable
|
||||
*/
|
||||
void TSI_EnableInterrupts(TSI_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Disables the TSI interrupt requests.
|
||||
* @param base TSI peripheral base address.
|
||||
* @param mask interrupt source
|
||||
* The parameter can be combination of the following source if defined:
|
||||
* @arg kTSI_GlobalInterruptEnable
|
||||
* @arg kTSI_EndOfScanInterruptEnable
|
||||
* @arg kTSI_OutOfRangeInterruptEnable
|
||||
*/
|
||||
void TSI_DisableInterrupts(TSI_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Gets an interrupt flag.
|
||||
* This function gets the TSI interrupt flags.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @return The mask of these status flags combination.
|
||||
*/
|
||||
static inline uint32_t TSI_GetStatusFlags(TSI_Type *base)
|
||||
{
|
||||
return (base->GENCS & (kTSI_EndOfScanFlag | kTSI_OutOfRangeFlag));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the interrupt flag.
|
||||
*
|
||||
* This function clears the TSI interrupt flag,
|
||||
* automatically cleared flags can't be cleared by this function.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param mask The status flags to clear.
|
||||
*/
|
||||
void TSI_ClearStatusFlags(TSI_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Gets the TSI scan trigger mode.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @return Scan trigger mode.
|
||||
*/
|
||||
static inline uint32_t TSI_GetScanTriggerMode(TSI_Type *base)
|
||||
{
|
||||
return (base->GENCS & TSI_GENCS_STM_MASK);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the scan in progress flag.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @return True - scan is in progress.
|
||||
* False - scan is not in progress.
|
||||
*/
|
||||
static inline bool TSI_IsScanInProgress(TSI_Type *base)
|
||||
{
|
||||
return (base->GENCS & TSI_GENCS_SCNIP_MASK);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the prescaler.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param prescaler Prescaler value.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_SetElectrodeOSCPrescaler(TSI_Type *base, tsi_electrode_osc_prescaler_t prescaler)
|
||||
{
|
||||
base->GENCS = (base->GENCS & ~(TSI_GENCS_PS_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_PS(prescaler));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the number of scans (NSCN).
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param number Number of scans.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_SetNumberOfScans(TSI_Type *base, tsi_n_consecutive_scans_t number)
|
||||
{
|
||||
base->GENCS = (base->GENCS & ~(TSI_GENCS_NSCN_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_NSCN(number));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables the TSI module.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param enable Choose whether to enable or disable module;
|
||||
* - true Enable TSI module;
|
||||
* - false Disable TSI module;
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_EnableModule(TSI_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_TSIEN_MASK; /* Enable module */
|
||||
}
|
||||
else
|
||||
{
|
||||
base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_TSIEN_MASK); /* Disable module */
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the TSI low power STOP mode as enabled or disabled.
|
||||
* This enables the TSI module function in low power modes.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param enable Choose to enable or disable STOP mode.
|
||||
* - true Enable module in STOP mode;
|
||||
* - false Disable module in STOP mode;
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_EnableLowPower(TSI_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->GENCS =
|
||||
(base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_STPE_MASK; /* Module enabled in low power stop modes */
|
||||
}
|
||||
else
|
||||
{
|
||||
base->GENCS =
|
||||
(base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_STPE_MASK); /* Module disabled in low power stop modes */
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables the hardware trigger scan.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param enable Choose to enable hardware trigger or software trigger scan.
|
||||
* - true Enable hardware trigger scan;
|
||||
* - false Enable software trigger scan;
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_EnableHardwareTriggerScan(TSI_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_STM_MASK; /* Enable hardware trigger scan */
|
||||
}
|
||||
else
|
||||
{
|
||||
base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_STM_MASK); /* Enable software trigger scan */
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Starts a software trigger measurement (triggers a new measurement).
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_StartSoftwareTrigger(TSI_Type *base)
|
||||
{
|
||||
base->DATA |= TSI_DATA_SWTS_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the measured channel number.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param channel Channel number 0 ... 15.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_SetMeasuredChannelNumber(TSI_Type *base, uint8_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT);
|
||||
|
||||
base->DATA = ((base->DATA) & ~TSI_DATA_TSICH_MASK) | (TSI_DATA_TSICH(channel));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the current measured channel number.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @return uint8_t Channel number 0 ... 15.
|
||||
*/
|
||||
static inline uint8_t TSI_GetMeasuredChannelNumber(TSI_Type *base)
|
||||
{
|
||||
return (uint8_t)((base->DATA & TSI_DATA_TSICH_MASK) >> TSI_DATA_TSICH_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables the DMA transfer.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param enable Choose to enable DMA transfer or not.
|
||||
* - true Enable DMA transfer;
|
||||
* - false Disable DMA transfer;
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_EnableDmaTransfer(TSI_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->DATA |= TSI_DATA_DMAEN_MASK; /* Enable DMA transfer */
|
||||
}
|
||||
else
|
||||
{
|
||||
base->DATA &= ~TSI_DATA_DMAEN_MASK; /* Disable DMA transfer */
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE) && (FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE == 1)
|
||||
/*!
|
||||
* @brief Decides whether to enable end of scan DMA transfer request only.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param enable Choose whether to enable End of Scan DMA transfer request only.
|
||||
* - true Enable End of Scan DMA transfer request only;
|
||||
* - false Both End-of-Scan and Out-of-Range can generate DMA transfer request.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_EnableEndOfScanDmaTransferOnly(TSI_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) |
|
||||
TSI_GENCS_EOSDMEO_MASK; /* Enable End of Scan DMA transfer request only; */
|
||||
}
|
||||
else
|
||||
{
|
||||
base->GENCS =
|
||||
(base->GENCS & ~ALL_FLAGS_MASK) &
|
||||
(~TSI_GENCS_EOSDMEO_MASK); /* Both End-of-Scan and Out-of-Range can generate DMA transfer request. */
|
||||
}
|
||||
}
|
||||
#endif /* End of (FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE == 1)*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the conversion counter value.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @return Accumulated scan counter value ticked by the reference clock.
|
||||
*/
|
||||
static inline uint16_t TSI_GetCounter(TSI_Type *base)
|
||||
{
|
||||
return (uint16_t)(base->DATA & TSI_DATA_TSICNT_MASK);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the TSI wake-up channel low threshold.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param low_threshold Low counter threshold.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_SetLowThreshold(TSI_Type *base, uint16_t low_threshold)
|
||||
{
|
||||
assert(low_threshold < 0xFFFFU);
|
||||
|
||||
base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESL_MASK) | (TSI_TSHD_THRESL(low_threshold));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the TSI wake-up channel high threshold.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param high_threshold High counter threshold.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_SetHighThreshold(TSI_Type *base, uint16_t high_threshold)
|
||||
{
|
||||
assert(high_threshold < 0xFFFFU);
|
||||
|
||||
base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESH_MASK) | (TSI_TSHD_THRESH(high_threshold));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the analog mode of the TSI module.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param mode Mode value.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_SetAnalogMode(TSI_Type *base, tsi_analog_mode_t mode)
|
||||
{
|
||||
base->GENCS = (base->GENCS & ~(TSI_GENCS_MODE_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_MODE(mode));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the noise mode result of the TSI module.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @return Value of the GENCS[MODE] bit-fields.
|
||||
*/
|
||||
static inline uint8_t TSI_GetNoiseModeResult(TSI_Type *base)
|
||||
{
|
||||
return (base->GENCS & TSI_GENCS_MODE_MASK) >> TSI_GENCS_MODE_SHIFT;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the reference oscillator charge current.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param current The reference oscillator charge current.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_SetReferenceChargeCurrent(TSI_Type *base, tsi_reference_osc_charge_current_t current)
|
||||
{
|
||||
base->GENCS = (base->GENCS & ~(TSI_GENCS_REFCHRG_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_REFCHRG(current));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the external electrode charge current.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param current External electrode charge current.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_SetElectrodeChargeCurrent(TSI_Type *base, tsi_external_osc_charge_current_t current)
|
||||
{
|
||||
base->GENCS = (base->GENCS & ~(TSI_GENCS_EXTCHRG_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_EXTCHRG(current));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the oscillator's voltage rails.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param dvolt The voltage rails.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_SetOscVoltageRails(TSI_Type *base, tsi_osc_voltage_rails_t dvolt)
|
||||
{
|
||||
base->GENCS = (base->GENCS & ~(TSI_GENCS_DVOLT_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_DVOLT(dvolt));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the electrode series resistance value in EXTCHRG[0] bit.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param resistor Series resistance.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_SetElectrodeSeriesResistor(TSI_Type *base, tsi_series_resistor_t resistor)
|
||||
{
|
||||
base->GENCS = (base->GENCS & TSI_V4_EXTCHRG_RESISTOR_BIT_CLEAR) | TSI_GENCS_EXTCHRG(resistor);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the electrode filter bits value in EXTCHRG[2:1] bits.
|
||||
*
|
||||
* @param base TSI peripheral base address.
|
||||
* @param filter Series resistance.
|
||||
* @return none.
|
||||
*/
|
||||
static inline void TSI_SetFilterBits(TSI_Type *base, tsi_filter_bits_t filter)
|
||||
{
|
||||
base->GENCS = (base->GENCS & TSI_V4_EXTCHRG_FILTER_BITS_CLEAR) | (filter << TSI_V4_EXTCHRG_FILTER_BITS_SHIFT);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_TSI_V4_H_ */
|
||||
@ -0,0 +1,270 @@
|
||||
__________________________________________________
|
||||
|
||||
NXPNFCRDLIB EXAMPLE : NFCRDLIBEX1_DISCOVERYLOOP
|
||||
(V07.10.00)
|
||||
__________________________________________________
|
||||
|
||||
|
||||
Table of Contents
|
||||
_________________
|
||||
|
||||
1 Document Purpose
|
||||
2 Description of the NfcrdlibEx1_DiscoveryLoop
|
||||
3 Restrictions on NfcrdlibEx1_DiscoveryLoop
|
||||
4 Configurations of NfcrdlibEx1_DiscoveryLoop
|
||||
5 Package Contents
|
||||
6 Mandatory materials (not included)
|
||||
7 Hardware Configuration
|
||||
8 Software Configuration
|
||||
9 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with PN5190 using MCUXpresso
|
||||
10 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with PN5180 using MCUXpresso
|
||||
11 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with RC663 using MCUXpresso
|
||||
12 Steps to build NfcrdlibEx1_DiscoveryLoop for PN7462AU using MCUXpresso
|
||||
13 Steps to build NfcrdlibEx1_DiscoveryLoop for FRDM-K82F using MCUXpresso
|
||||
14 Selection of Board / OSAL / Frontend (MCUXpresso)
|
||||
15 Steps to follow for PI / Linux / CMake
|
||||
16 Running NfcrdlibEx1_DiscoveryLoop
|
||||
17 List of supported NFC Reader Boards/ICs
|
||||
18 Reference Documents
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
1 Document Purpose
|
||||
==================
|
||||
|
||||
This document describes the steps to be followed to execute
|
||||
NfcrdlibEx1_DiscoveryLoop example as well as it's known problems and
|
||||
restrictions.
|
||||
|
||||
|
||||
2 Description of the NfcrdlibEx1_DiscoveryLoop
|
||||
==============================================
|
||||
|
||||
- NfcrdlibEx1_DiscoveryLoop can be run with CLEV663B, PN5180, PN5190
|
||||
and PN7462AU. (See Section-17 for supported versions)
|
||||
- This example will use both POLL and LISTEN modes of discovery loop.
|
||||
- It displays/prints detected tag information (like UID, SAK, Product
|
||||
Type for MIfare Cards) and prints information when it gets activated
|
||||
as a target by an external Initiator/reader.
|
||||
- This example will load/configure Discovery loop with default values
|
||||
based on the interested profile (Nfc, Emvco) via SetConfig.
|
||||
- Whenever multiple technologies are detected, example will select
|
||||
first detected technology to resolve.
|
||||
- This example will activate device at index zero whenever multiple
|
||||
devices are detected.
|
||||
- For EMVCo profile, this example provide full EMVCo digital
|
||||
demonstration.
|
||||
|
||||
|
||||
3 Restrictions on NfcrdlibEx1_DiscoveryLoop
|
||||
===========================================
|
||||
|
||||
- NfcrdlibEx1_DiscoveryLoop is restricted to be run on NFC Reader
|
||||
Boards/ICs mentioned in Section-17.
|
||||
- The APIs are intended for NXP contact-less reader ICs only, as such
|
||||
the APIs are not to be ported to any technology from any other
|
||||
vendor.
|
||||
- NXP will not support porting to any other vendor platform.
|
||||
- This software project requires NxpNfcRdLib v07.10.00 or later.
|
||||
- **IMPORTANT** The default used MCU Type is K82. When executing
|
||||
example on LPC1769 or PN7462AU, the MCU Type has to be changed in
|
||||
the MCUXpresso IDE.
|
||||
- For switching to MCU Type to PN7462AU, see Section-12
|
||||
- For switching to MCU Type to LPC1769, see Section-9, Section-10 and
|
||||
Section-11.
|
||||
|
||||
|
||||
4 Configurations of NfcrdlibEx1_DiscoveryLoop
|
||||
=============================================
|
||||
|
||||
- The example application can be run with default configuratin Or can
|
||||
be configured by enabling ENABLE_DISC_CONFIG to different settings
|
||||
Or can be configure to work as EMVCo digital loopback application,
|
||||
by enabling both ENABLE_DISC_CONFIG and ENABLE_EMVCO_PROF
|
||||
- The Default configuration example application is written to detect
|
||||
and activate one tag of supported technologies.
|
||||
- Listen mode is supported only for PN5180 and PN7462AU and this
|
||||
example application receives ATR_REQ or RATS from a NFC Peer/Reader.
|
||||
Additional functionality is not supported in this example.
|
||||
- With CLRC663, owing to the hardware limitations of CLRC663, it only
|
||||
supports poll without Active mode.
|
||||
|
||||
|
||||
5 Package Contents
|
||||
==================
|
||||
|
||||
- Readme.txt
|
||||
+ This readme file
|
||||
- NfcrdlibEx1_DiscoveryLoop.c
|
||||
+ Main example file.
|
||||
- intfs/NfcrdlibEx1_DiscoveryLoop.h
|
||||
+ Interfaces/Defines specific to the example
|
||||
- intfs/ph_NxpBuild_App.h
|
||||
+ Reader library build configuration file
|
||||
- src/phApp_Helper.c
|
||||
- src/phApp_PN5180_Init.c
|
||||
- src/phApp_PN5190_Init.c
|
||||
- src/phApp_PN7462AU_Init.c
|
||||
- src/phApp_RC663_Init.c
|
||||
- src/phApp_Init.c and intfs/phApp_Init.h
|
||||
+ Common utility functions (common across all examples)
|
||||
- src/NfcrdlibEx1_EmvcoProfile.c
|
||||
+ Emvco profile funtions specific to the example
|
||||
- mcux/.cproject and mcux/.project
|
||||
+ MCUXpresso project configuration file
|
||||
- cr_startup_lpc175x_6x.c
|
||||
+ Startup required to compile example for LPC1769 Micro Controller.
|
||||
|
||||
|
||||
6 Mandatory materials (not included)
|
||||
====================================
|
||||
|
||||
- MCUXpresso IDE. It can be downloaded from
|
||||
[http://www.nxp.com/products/:MCUXpresso-IDE]
|
||||
- SDK for Freedom K82 Board
|
||||
([http://www.nxp.com/products/:FRDM-K82F]). The pre-build SDK can
|
||||
be downloaded from
|
||||
[https://mcuxpresso.nxp.com/en/license?hash=9897a8c19a6bc569c3fade7141f0f405&hash_download=true&to_vault=true]
|
||||
See MCUXpresso User Manual for steps needed to install an SDK.
|
||||
- Plugin to extend MCUXpresso to support PN7462AU. (Required for
|
||||
MCUXpresso versions before MCUXpressoIDE_10.0.2)
|
||||
|
||||
- LPCXpresso LPC1769 / Freedom K82 development boards For NFC ICs
|
||||
listed in Section-17 (Note: PN7462AU (Section-17 Bullet-3) does not
|
||||
need any other other microcontroller).
|
||||
|
||||
|
||||
7 Hardware Configuration
|
||||
========================
|
||||
|
||||
Before starting this application, HW Changes may be required for the
|
||||
used board. Refer to the following User Manuals / Application notes
|
||||
before starting with this example.
|
||||
|
||||
- AN11211: Quick Start Up Guide RC663 Blueboard
|
||||
- AN11744: PN5180 Evaluation board quick start guide
|
||||
- AN11802: NFC Reader Library for Linux Installation Guidelines
|
||||
- AN12550: PNEV5190B Evaluation board quick start guide
|
||||
|
||||
|
||||
8 Software Configuration
|
||||
========================
|
||||
|
||||
- The Software can be compiled for Cortex M3 LPC1769 micro-controller,
|
||||
Cortex M4 Freedom K82 and Cortex M0 based PN7462AU from NXP.
|
||||
- Since this example can be configured to run on various MCU ICs and
|
||||
various NFC ICs, appropriate changes are required as mentioned in
|
||||
Section-9, Section-10, Section-11, Section-12 and Section-13.
|
||||
|
||||
|
||||
9 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with PN5190 using MCUXpresso
|
||||
===================================================================================
|
||||
|
||||
See "PNEV5190B Evaluation board quick start guide" in AN12550 (See
|
||||
Section-18, Bullet-6 below)
|
||||
|
||||
|
||||
10 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with PN5180 using MCUXpresso
|
||||
====================================================================================
|
||||
|
||||
See "Importing provided SW example projects" in AN11908 (See
|
||||
Section-18, Bullet-2 below)
|
||||
|
||||
|
||||
11 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with RC663 using MCUXpresso
|
||||
===================================================================================
|
||||
|
||||
See "Importing provided SW example projects" in AN11022 (See
|
||||
Section-18, Bullet-3 below)
|
||||
|
||||
|
||||
12 Steps to build NfcrdlibEx1_DiscoveryLoop for PN7462AU using MCUXpresso
|
||||
=========================================================================
|
||||
|
||||
- For MCUXpresso versions before MCUXpressoIDE_10.0.2, See "Adding
|
||||
PN7462AU Plugin" in UM10883. (See Section-18, Bullet-4 below)
|
||||
- See "Importing provided SW example projects" in UM10883.
|
||||
|
||||
|
||||
13 Steps to build NfcrdlibEx1_DiscoveryLoop for FRDM-K82F using MCUXpresso
|
||||
==========================================================================
|
||||
|
||||
See "Import projects to the MCUXpresso" in AN11908. (See Section-18,
|
||||
Bullet-2 below)
|
||||
|
||||
|
||||
14 Selection of Board / OSAL / Frontend (MCUXpresso)
|
||||
====================================================
|
||||
|
||||
For MCUXpresso, the selection of Board / OSAL / Frontend has to be
|
||||
done via -D (Preprocessor defines).
|
||||
|
||||
1) To select the board go to "Project Properties" --> "C/C++ Build"
|
||||
--> "Settings" --> "Preprocessor" --> "Defined symbols (-D)", and
|
||||
define the relevant PHDRIVER_<BoardNFCCombination>_BOARD macro.
|
||||
|
||||
e.g. For using K82 with Pn5190 use PHDRIVER_K82F_PNEV5190B_BOARD
|
||||
and for LPC1769 with PN5190 use PHDRIVER_LPC1769PN5190_BOARD. For
|
||||
list of supported boards refer to
|
||||
Platform\DAL\cfg\BoardSelection.h.
|
||||
|
||||
2) To select the osal/os type, go to "Project Properties" --> "C/C++
|
||||
Build" --> "Settings" --> "Preprocessor" --> "Defined symbols
|
||||
(-D)".
|
||||
|
||||
e.g. For using FreeRTOS use PH_OSAL_FREERTOS. For other options
|
||||
refer to RTOS\phOsal\inc\phOsal_Config.h.
|
||||
|
||||
|
||||
15 Steps to follow for PI / Linux / CMake
|
||||
=========================================
|
||||
|
||||
The steps are described in AN11802. (See Section-18, Bullet-5 below)
|
||||
|
||||
|
||||
16 Running NfcrdlibEx1_DiscoveryLoop
|
||||
====================================
|
||||
|
||||
When this application is running in default configuration on the
|
||||
target MCU setup and when you bring the NFC cards or phone in
|
||||
proximity, the example application will detect and reports the NFC
|
||||
technology types detected. Upon using MACRO ENABLE_EMVCO_PROF, this
|
||||
application will work as EMVCo Digital Loopback Application
|
||||
|
||||
|
||||
17 List of supported NFC Reader Boards/ICs
|
||||
==========================================
|
||||
|
||||
1) CLEV6630B v2.0 Customer Evaluation Board
|
||||
2) PNEV5180B v2.0 Customer Evaluation Board
|
||||
3) PN7462AU v2.1 Customer Evaluation Board
|
||||
4) PNEV5190B v1.0 Customer Evaluation Board
|
||||
|
||||
|
||||
18 Reference Documents
|
||||
======================
|
||||
|
||||
1) UM10954 : PN5180 SW Quick start guide
|
||||
[http://www.nxp.com/docs/en/user-guide/UM10954.pdf]
|
||||
|
||||
2) AN11908 : NFC Reader Library for FRDM-K82F Board Installation
|
||||
guidelines
|
||||
[http://www.nxp.com/docs/en/application-note/AN11908.pdf]
|
||||
|
||||
3) AN11022 : CLRC663 Evaluation board quick start guide
|
||||
[http://www.nxp.com/docs/en/application-note/AN11022.pdf]
|
||||
|
||||
4) UM10883 : PN7462AU Quick Start Guide - Development Kit
|
||||
[http://www.nxp.com/docs/en/user-guide/UM10883.pdf]
|
||||
|
||||
5) AN11802 : NFC Reader Library for Linux Installation Guidelines
|
||||
[http://www.nxp.com/docs/en/application-note/AN11802.pdf]
|
||||
|
||||
6) AN12550 : PNEV5190B Evaluation board quick start guide
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
||||
For updates of this example, see
|
||||
[http://www.nxp.com/products/:NFC-READER-LIBRARY]
|
||||
1628
.svn/pristine/19/192e58d7c0ece4962f4b0dde868959bd1c0bdc5d.svn-base
Normal file
1628
.svn/pristine/19/192e58d7c0ece4962f4b0dde868959bd1c0bdc5d.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
1571
.svn/pristine/19/1941bcb89ffe4080f04937e51b17f6edc281db0b.svn-base
Normal file
1571
.svn/pristine/19/1941bcb89ffe4080f04937e51b17f6edc281db0b.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,150 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors Gratkorn / Austria
|
||||
*
|
||||
* (C)NXP Semiconductors
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
*particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Software ISO18000-3 Mode3 Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* MWt: Generated 1. February 2010
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHPALI18000P3M3_SW_H
|
||||
#define PHPALI18000P3M3_SW_H
|
||||
|
||||
#include <ph_Status.h>
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
|
||||
|
||||
phStatus_t phpalI18000p3m3_Sw_Exchange(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams,
|
||||
uint16_t wOption,
|
||||
uint8_t * pTxBuffer,
|
||||
uint16_t wTxLength,
|
||||
uint8_t bTxLastBits,
|
||||
uint8_t ** ppRxBuffer,
|
||||
uint16_t * pRxLength,
|
||||
uint8_t * pRxLastBits
|
||||
);
|
||||
|
||||
phStatus_t phpalI18000p3m3_Sw_Select(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bTarget,
|
||||
uint8_t bAction,
|
||||
uint8_t bMemBank,
|
||||
uint8_t * pPointer,
|
||||
uint8_t bPointerLength,
|
||||
uint8_t * pMask,
|
||||
uint8_t bMaskBitLength,
|
||||
uint8_t bTruncate
|
||||
);
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3_DEPRECATED
|
||||
phStatus_t phpalI18000p3m3_Sw_BeginRound(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bDr,
|
||||
uint8_t bM,
|
||||
uint8_t bTRext,
|
||||
uint8_t bSel,
|
||||
uint8_t bSession,
|
||||
uint8_t bRfu,
|
||||
uint8_t bQ,
|
||||
uint8_t * pStoredCRC
|
||||
);
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3_DEPRECATED */
|
||||
|
||||
phStatus_t phpalI18000p3m3_Sw_CreateBeginRoundCmd(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bDr,
|
||||
uint8_t bM,
|
||||
uint8_t bTRext,
|
||||
uint8_t bSel,
|
||||
uint8_t bSession,
|
||||
uint8_t bRfu,
|
||||
uint8_t bQ,
|
||||
uint8_t * pBeginRnd
|
||||
);
|
||||
|
||||
phStatus_t phpalI18000p3m3_Sw_CreateSelectCmd(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bTarget,
|
||||
uint8_t bAction,
|
||||
uint8_t bMemBank,
|
||||
uint8_t * pPointer,
|
||||
uint8_t bPointerLength,
|
||||
uint8_t * pMask,
|
||||
uint8_t bMaskBitLength,
|
||||
uint8_t bTruncate,
|
||||
uint8_t * pSelectCmd,
|
||||
uint8_t * bLen,
|
||||
uint8_t * bValidBits
|
||||
);
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3_DEPRECATED
|
||||
phStatus_t phpalI18000p3m3_Sw_ResizeRound(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bUpDn,
|
||||
uint8_t * pStoredCRC
|
||||
);
|
||||
|
||||
phStatus_t phpalI18000p3m3_Sw_NextSlot(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pStoredCRC
|
||||
);
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3_DEPRECATED*/
|
||||
|
||||
phStatus_t phpalI18000p3m3_Sw_Ack(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bOption,
|
||||
uint8_t * pHandle,
|
||||
uint8_t ** ppRxBuffer,
|
||||
uint16_t * pRxBitLength
|
||||
);
|
||||
|
||||
phStatus_t phpalI18000p3m3_Sw_Nak(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams
|
||||
);
|
||||
|
||||
phStatus_t phpalI18000p3m3_Sw_ActivateCard(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams, /**< [In] Pointer to this layer's parameter structure. */
|
||||
uint8_t * pSelCmd, /**< [In] ISO 18000p3m3 Select command frame. */
|
||||
uint8_t bSelCmdLen, /**< [In] Select command length in bytes- 1 to 39 bytes. */
|
||||
uint8_t bNumValidBitsinLastByte, /**< [In] Number of valid bits in last byte of pSelCmd. */
|
||||
uint8_t * pBeginRndCmd, /**< [In] ISO 18000p3m3 BeginRound command frame. This is 17bits i.e., 3 bytes are expected. CRC5 should not be provided. */
|
||||
uint8_t bTSprocessing, /**< [In] TimeSlot processing behavior. */
|
||||
uint8_t ** ppRxBuffer, /**< [In] Pointer to HAL Rx Buffer containing handle of the activated tag. */
|
||||
uint16_t * pRxBufferLen, /**< [In] Length of response in hal Rx Buffer. */
|
||||
uint8_t * pMoreCardsAvailable /**< [Out] Indicates if more tags are present in the field. */
|
||||
);
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_I18000P3M3_DEPRECATED
|
||||
phStatus_t phpalI18000p3m3_Sw_GetSerialNo(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pRxBuffer,
|
||||
uint8_t * pRxLength
|
||||
);
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3_DEPRECATED */
|
||||
|
||||
phStatus_t phpalI18000p3m3_Sw_SetConfig(
|
||||
phpalI18000p3m3_Sw_DataParams_t * pDataParams,
|
||||
uint16_t wConfig,
|
||||
uint16_t wValue
|
||||
);
|
||||
|
||||
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
|
||||
|
||||
#endif /* PHPALI18000P3M3_SW_H */
|
||||
Binary file not shown.
2168
.svn/pristine/19/19fd2a242a371907f12b14dc6830ba8070abf634.svn-base
Normal file
2168
.svn/pristine/19/19fd2a242a371907f12b14dc6830ba8070abf634.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors Gratkorn / Austria
|
||||
*
|
||||
* (C)NXP Semiconductors
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
*particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Software ISO18000-3 Mode3 Application Layer (Internals).
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* CHu: Generated 20. July 2010
|
||||
*
|
||||
*/
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <ph_RefDefs.h>
|
||||
|
||||
#ifdef NXPBUILD__PHAL_I18000P3M3_SW
|
||||
|
||||
#include <phalI18000p3m3.h>
|
||||
#include "phalI18000p3m3_Sw_Int.h"
|
||||
|
||||
phStatus_t phalI18000p3m3_Sw_ParseError(
|
||||
phalI18000p3m3_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pRxData,
|
||||
uint16_t wRxDataLength,
|
||||
uint8_t bRxLastBits
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
uint8_t PH_MEMLOC_REM bError;
|
||||
uint8_t PH_MEMLOC_REM bHandle[2];
|
||||
|
||||
/* Parameter check */
|
||||
if (pRxData == NULL)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INTERNAL_ERROR, PH_COMP_AL_I18000P3M3);
|
||||
}
|
||||
|
||||
/* Check received length */
|
||||
if ((wRxDataLength != 4U) || (bRxLastBits != 1U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_AL_I18000P3M3);
|
||||
}
|
||||
|
||||
/* Check for Error-Bit */
|
||||
if (0U == (pRxData[0] & 0x80U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_AL_I18000P3M3);
|
||||
}
|
||||
|
||||
/* Check Handle */
|
||||
bHandle[0] = (uint8_t)((pRxData[1] << 1U) | (pRxData[2] >> 7U));
|
||||
bHandle[1] = (uint8_t)((pRxData[2] << 1U) | (pRxData[3] >> 7U));
|
||||
if ((bHandle[0] != pDataParams->abHandle[0]) ||
|
||||
(bHandle[1] != pDataParams->abHandle[1]))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_AL_I18000P3M3);
|
||||
}
|
||||
|
||||
/* Retrieve and map error code */
|
||||
bError = (uint8_t)((pRxData[0] << 1U) | (pRxData[1] >> 7U));
|
||||
switch (bError)
|
||||
{
|
||||
case PHAL_I18000P3M3_ERRCODE_OTHER:
|
||||
status = PH_ADD_COMPCODE_FIXED(PHAL_I18000P3M3_ERR_OTHER, PH_COMP_AL_I18000P3M3);
|
||||
break;
|
||||
case PHAL_I18000P3M3_ERRCODE_MEMORY_OVERRUN:
|
||||
status = PH_ADD_COMPCODE_FIXED(PHAL_I18000P3M3_ERR_MEMORY_OVERRUN, PH_COMP_AL_I18000P3M3);
|
||||
break;
|
||||
case PHAL_I18000P3M3_ERRCODE_MEMORY_LOCKED:
|
||||
status = PH_ADD_COMPCODE_FIXED(PHAL_I18000P3M3_ERR_MEMORY_LOCKED, PH_COMP_AL_I18000P3M3);
|
||||
break;
|
||||
case PHAL_I18000P3M3_ERRCODE_INSUFFICIENT_POWER:
|
||||
status = PH_ADD_COMPCODE_FIXED(PHAL_I18000P3M3_ERR_INSUFFICIENT_POWER, PH_COMP_AL_I18000P3M3);
|
||||
break;
|
||||
case PHAL_I18000P3M3_ERRCODE_NON_SPECIFIC:
|
||||
status = PH_ADD_COMPCODE_FIXED(PHAL_I18000P3M3_ERR_NON_SPECIFIC, PH_COMP_AL_I18000P3M3);
|
||||
break;
|
||||
default:
|
||||
status = PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_AL_I18000P3M3);
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /* NXPBUILD__PHAL_I18000P3M3_SW */
|
||||
@ -0,0 +1,981 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors Gratkorn / Austria
|
||||
*
|
||||
* (C)NXP Semiconductors
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
*particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Software ICode EPC/UID Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* CHu: Generated 8. September 2009
|
||||
*
|
||||
*/
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <phTools.h>
|
||||
#include <phhalHw.h>
|
||||
#include <phpalEpcUid.h>
|
||||
#include <ph_RefDefs.h>
|
||||
|
||||
#ifdef NXPBUILD__PHPAL_EPCUID_SW
|
||||
|
||||
#include "phpalEpcUid_Sw.h"
|
||||
#include "phpalEpcUid_Sw_Int.h"
|
||||
|
||||
phStatus_t phpalEpcUid_Sw_Init(
|
||||
phpalEpcUid_Sw_DataParams_t * pDataParams,
|
||||
uint16_t wSizeOfDataParams,
|
||||
void * pHalDataParams
|
||||
)
|
||||
{
|
||||
/* Dataparam check */
|
||||
if (sizeof(phpalEpcUid_Sw_DataParams_t) != wSizeOfDataParams)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
|
||||
/* Pointer check */
|
||||
PH_ASSERT_NULL (pDataParams);
|
||||
PH_ASSERT_NULL (pHalDataParams);
|
||||
|
||||
/* init private data */
|
||||
pDataParams->wId = PH_COMP_PAL_EPCUID | PHPAL_EPCUID_SW_ID;
|
||||
pDataParams->pHalDataParams = pHalDataParams;
|
||||
pDataParams->bUidValid = PH_OFF;
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalEpcUid_Sw_ActivateCard(
|
||||
phpalEpcUid_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bTagType,
|
||||
uint8_t bNumSlots,
|
||||
uint8_t * pMask,
|
||||
uint8_t bMaskBitLength,
|
||||
uint8_t bHash,
|
||||
uint8_t * pRxBuffer,
|
||||
uint8_t * pRxLength,
|
||||
uint8_t * pMoreCardsAvailable
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
phStatus_t PH_MEMLOC_REM statusReturned;
|
||||
uint8_t PH_MEMLOC_REM bNumSlotsTmp;
|
||||
uint16_t PH_MEMLOC_REM wNumSlotsDec;
|
||||
uint8_t PH_MEMLOC_REM bCardsPresent;
|
||||
|
||||
/* reset pMoreCardsAvailable flag */
|
||||
*pMoreCardsAvailable = PH_OFF;
|
||||
|
||||
/* init. return status */
|
||||
statusReturned = PH_ERR_SUCCESS;
|
||||
|
||||
do
|
||||
{
|
||||
/* Reset card present state */
|
||||
bCardsPresent = PH_OFF;
|
||||
|
||||
/* Start a new Response Round and scan slot 0 */
|
||||
status = phpalEpcUid_Sw_BeginRound(
|
||||
pDataParams,
|
||||
bTagType,
|
||||
bNumSlots,
|
||||
pMask,
|
||||
bMaskBitLength,
|
||||
bHash,
|
||||
pRxBuffer,
|
||||
pRxLength);
|
||||
|
||||
/* Return on parameter error */
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_INVALID_PARAMETER)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Calculate number of slots in decimal */
|
||||
wNumSlotsDec = 0x01;
|
||||
if (bNumSlots > PHPAL_EPCUID_NUMSLOTS_1)
|
||||
{
|
||||
bNumSlotsTmp = bNumSlots;
|
||||
do
|
||||
{
|
||||
bNumSlotsTmp >>= 1U;
|
||||
wNumSlotsDec <<= 1U;
|
||||
} while (0U != bNumSlotsTmp);
|
||||
|
||||
wNumSlotsDec <<= 1U;
|
||||
}
|
||||
bNumSlotsTmp = bNumSlots;
|
||||
|
||||
/* Do for all further requested slots */
|
||||
while (0U != (wNumSlotsDec--))
|
||||
{
|
||||
/* Multiple labels found in current slot */
|
||||
if (((status & PH_ERR_MASK) == PH_ERR_COLLISION_ERROR) ||
|
||||
((status & PH_ERR_MASK) == PH_ERR_INTEGRITY_ERROR))
|
||||
{
|
||||
bCardsPresent = PH_ON;
|
||||
*pMoreCardsAvailable = PH_ON;
|
||||
|
||||
/* Store collision error in case it can't be resolved */
|
||||
if ((statusReturned & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
statusReturned = status;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Store timeout error if integrity / collision error has not happened */
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_IO_TIMEOUT)
|
||||
{
|
||||
if ((statusReturned & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
statusReturned = status;
|
||||
}
|
||||
}
|
||||
/* Return on success or other errors */
|
||||
else
|
||||
{
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* Last slot -> send CloseSlotLast */
|
||||
if (wNumSlotsDec == 0U)
|
||||
{
|
||||
/* Send CloseSlot command */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalEpcUid_Sw_CloseSlot(
|
||||
pDataParams,
|
||||
PHPAL_EPCUID_CLOSESLOT_LAST,
|
||||
pRxBuffer,
|
||||
pRxLength));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Send CloseSlot command */
|
||||
status = phpalEpcUid_Sw_CloseSlot(
|
||||
pDataParams,
|
||||
PHPAL_EPCUID_CLOSESLOT_NONLAST,
|
||||
pRxBuffer,
|
||||
pRxLength);
|
||||
}
|
||||
}
|
||||
|
||||
/* Increment number of slots */
|
||||
bNumSlots = (bNumSlots << 1U) | 0x01U;
|
||||
}
|
||||
while ((bCardsPresent != PH_OFF) && (bNumSlotsTmp < PHPAL_EPCUID_NUMSLOTS_512));
|
||||
|
||||
/* return error */
|
||||
return statusReturned;
|
||||
}
|
||||
|
||||
phStatus_t phpalEpcUid_Sw_BeginRound(
|
||||
phpalEpcUid_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bTagType,
|
||||
uint8_t bNumSlots,
|
||||
uint8_t * pMask,
|
||||
uint8_t bMaskBitLength,
|
||||
uint8_t bHash,
|
||||
uint8_t * pRxBuffer,
|
||||
uint8_t * pRxLength
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM bCrc8;
|
||||
uint8_t PH_MEMLOC_REM bBitCount;
|
||||
uint8_t PH_MEMLOC_REM aCommand[PHPAL_EPCUID_IDD_LENGTH + 4U];
|
||||
uint16_t PH_MEMLOC_REM wCommandLen = 0;
|
||||
uint16_t PH_MEMLOC_REM wCommandBitLen = 0;
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wResponseLen = 0;
|
||||
|
||||
/* Parameter check */
|
||||
switch (bNumSlots)
|
||||
{
|
||||
case PHPAL_EPCUID_NUMSLOTS_1:
|
||||
case PHPAL_EPCUID_NUMSLOTS_4:
|
||||
case PHPAL_EPCUID_NUMSLOTS_8:
|
||||
case PHPAL_EPCUID_NUMSLOTS_16:
|
||||
case PHPAL_EPCUID_NUMSLOTS_32:
|
||||
case PHPAL_EPCUID_NUMSLOTS_64:
|
||||
case PHPAL_EPCUID_NUMSLOTS_128:
|
||||
case PHPAL_EPCUID_NUMSLOTS_256:
|
||||
case PHPAL_EPCUID_NUMSLOTS_512:
|
||||
break;
|
||||
default:
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
|
||||
/* checks for EPC */
|
||||
if (bTagType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
if (bMaskBitLength > (PHPAL_EPCUID_EPC_LENGTH << 3U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
|
||||
/* Copy EPC mask */
|
||||
(void)memcpy(pDataParams->LabelInfo.bEpc, pMask, (size_t)(((uint32_t)bMaskBitLength) >> 3U));
|
||||
}
|
||||
/* checks for UID */
|
||||
else if (bTagType == PHPAL_EPCUID_LABEL_UID)
|
||||
{
|
||||
if (bMaskBitLength > (PHPAL_EPCUID_IDD_LENGTH << 3U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
|
||||
/* Copy IDD mask */
|
||||
(void)memcpy(pDataParams->LabelInfo.bIdd, pMask, (((uint32_t)bMaskBitLength) >> 3U));
|
||||
}
|
||||
else
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
|
||||
/* reset label data */
|
||||
pDataParams->bLabelType = bTagType;
|
||||
pDataParams->bMaskBitLength = bMaskBitLength;
|
||||
pDataParams->bUidValid = PH_OFF;
|
||||
|
||||
/* Build first part of frame */
|
||||
aCommand[0] = PHPAL_EPCUID_SW_CMD_BEGINROUND;
|
||||
aCommand[1] = bMaskBitLength;
|
||||
|
||||
/* Evaluate command length and copy mask */
|
||||
bBitCount = bMaskBitLength & 0x07U;
|
||||
wCommandLen = (bBitCount == 0U) ? (((uint16_t)bMaskBitLength) >> 3U) : ((((uint16_t)bMaskBitLength) >> 3U) + 1U);
|
||||
(void)memcpy(&aCommand[2], pMask, wCommandLen);
|
||||
wCommandLen = wCommandLen + 2U;
|
||||
|
||||
/* append number of slots */
|
||||
if (0U != (bBitCount))
|
||||
{
|
||||
/* clear the last invalid bits of the mask */
|
||||
aCommand[wCommandLen - 1u] &= (uint8_t) (0xFFU << (8U - bBitCount));
|
||||
|
||||
/* append number of slots */
|
||||
aCommand[wCommandLen - 1u] |= (uint8_t) (bNumSlots >> bBitCount);
|
||||
aCommand[wCommandLen++] = (uint8_t) (bNumSlots << (8U - bBitCount));
|
||||
}
|
||||
else
|
||||
{
|
||||
aCommand[wCommandLen++] = bNumSlots;
|
||||
}
|
||||
|
||||
/* Calculate full bit-length */
|
||||
wCommandBitLen = (bBitCount == 0U) ? (wCommandLen << 3U) : (((uint16_t)(wCommandLen - 1u) << 3U) + bBitCount);
|
||||
|
||||
/* Calculate CRC for Epc */
|
||||
if (bTagType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phTools_CalculateCrc8(
|
||||
PH_TOOLS_CRC_OPTION_MSB_FIRST | PH_TOOLS_CRC_OPTION_BITWISE,
|
||||
PH_TOOLS_CRC8_PRESET_EPC,
|
||||
PH_TOOLS_CRC8_POLY_EPCUID,
|
||||
aCommand,
|
||||
wCommandBitLen,
|
||||
&bCrc8));
|
||||
}
|
||||
/* calculate CRC for Uid */
|
||||
else
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phTools_CalculateCrc8(
|
||||
PH_TOOLS_CRC_OPTION_MSB_FIRST | PH_TOOLS_CRC_OPTION_BITWISE,
|
||||
PH_TOOLS_CRC8_PRESET_UID,
|
||||
PH_TOOLS_CRC8_POLY_EPCUID,
|
||||
aCommand,
|
||||
wCommandBitLen,
|
||||
&bCrc8));
|
||||
}
|
||||
|
||||
/* Insert CRC & Hashvalue if applicable */
|
||||
if (0U != (bBitCount))
|
||||
{
|
||||
/* Insert the crc */
|
||||
aCommand[wCommandLen - 1u] |= bCrc8 >> bBitCount;
|
||||
aCommand[wCommandLen++] = bCrc8 << (8U - bBitCount);
|
||||
|
||||
if (bTagType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
/* Insert the hash value */
|
||||
aCommand[wCommandLen - 1u] |= bHash >> bBitCount;
|
||||
aCommand[wCommandLen++] = bHash << (8U - bBitCount);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Insert the crc */
|
||||
aCommand[wCommandLen++] = bCrc8;
|
||||
|
||||
if (bTagType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
/* Insert the hash value */
|
||||
aCommand[wCommandLen++] = bHash;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set TxLastBits to bBitCount */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TXLASTBITS,
|
||||
bBitCount));
|
||||
|
||||
/* set SSOF as start symbol */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_SYMBOL_START,
|
||||
PHHAL_HW_SYMBOL_ICODEEPCUID_SSOF)
|
||||
);
|
||||
|
||||
/* set CEOF as end symbol */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_SYMBOL_END,
|
||||
PHHAL_HW_SYMBOL_ICODEEPCUID_CEOF)
|
||||
);
|
||||
|
||||
/* Set RxWait */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_RXWAIT_US,
|
||||
PHPAL_EPCUID_SW_BEGINROUND_DEAFTIME));
|
||||
|
||||
/* Set the RxTimeout */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
PHPAL_EPCUID_SW_TIMEOUT_ANTICOLL_US));
|
||||
|
||||
/* Exchange command */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCommand,
|
||||
wCommandLen,
|
||||
&pResponse,
|
||||
&wResponseLen));
|
||||
|
||||
/* Parse response */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalEpcUid_Sw_ParseResponse(pDataParams, pResponse, wResponseLen));
|
||||
|
||||
/* Return response */
|
||||
if (pDataParams->bLabelType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
*pRxLength = PHPAL_EPCUID_EPC_LENGTH;
|
||||
(void)memcpy(pRxBuffer, pDataParams->LabelInfo.bEpc, *pRxLength);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pRxLength = PHPAL_EPCUID_IDD_LENGTH;
|
||||
(void)memcpy(pRxBuffer, pDataParams->LabelInfo.bIdd, *pRxLength);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalEpcUid_Sw_CloseSlot(
|
||||
phpalEpcUid_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bOption,
|
||||
uint8_t * pRxBuffer,
|
||||
uint8_t * pRxLength
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM aCommand[1];
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wResponseLen = 0;
|
||||
|
||||
/* Set closeslot timeout*/
|
||||
if (bOption == PHPAL_EPCUID_CLOSESLOT_NONLAST)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
PHPAL_EPCUID_SW_TIMEOUT_ANTICOLL_US));
|
||||
}
|
||||
/* Set minimum timeout */
|
||||
else if (bOption == PHPAL_EPCUID_CLOSESLOT_LAST)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
1));
|
||||
}
|
||||
else
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
|
||||
/* set CS as start symbol */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_SYMBOL_START,
|
||||
PHHAL_HW_SYMBOL_ICODEEPCUID_CS));
|
||||
|
||||
/* no stop symbol */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_SYMBOL_END,
|
||||
PHHAL_HW_SYMBOL_ICODEEPCUID_CEOF));
|
||||
|
||||
/* Set RxWait */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_RXWAIT_US,
|
||||
PHPAL_EPCUID_SW_DEAFTIME_DEFAULT));
|
||||
|
||||
/* Exchange command */
|
||||
status = phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCommand,
|
||||
0,
|
||||
&pResponse,
|
||||
&wResponseLen);
|
||||
|
||||
if (bOption == PHPAL_EPCUID_CLOSESLOT_NONLAST)
|
||||
{
|
||||
/* Return on error */
|
||||
PH_CHECK_SUCCESS(status);
|
||||
|
||||
/* Parse response */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalEpcUid_Sw_ParseResponse(pDataParams, pResponse, wResponseLen));
|
||||
|
||||
/* Return response */
|
||||
if (pDataParams->bLabelType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
*pRxLength = PHPAL_EPCUID_EPC_LENGTH;
|
||||
(void)memcpy(pRxBuffer, pDataParams->LabelInfo.bEpc, *pRxLength);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pRxLength = PHPAL_EPCUID_IDD_LENGTH;
|
||||
(void)memcpy(pRxBuffer, pDataParams->LabelInfo.bIdd, *pRxLength);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset received length */
|
||||
if (NULL != (pRxLength))
|
||||
{
|
||||
*pRxLength = 0;
|
||||
}
|
||||
|
||||
/* Timeout is the correct behaviour */
|
||||
if ((status & PH_ERR_MASK) != PH_ERR_IO_TIMEOUT)
|
||||
{
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
/* if data was received return an error */
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Return the received error */
|
||||
return status;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalEpcUid_Sw_FixSlot(
|
||||
phpalEpcUid_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bTagType,
|
||||
uint8_t * pMask,
|
||||
uint8_t bMaskBitLength
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM aCommand[2];
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wResponseLen = 0;
|
||||
uint8_t PH_MEMLOC_REM bResponseLen;
|
||||
uint16_t PH_MEMLOC_REM wCrc16;
|
||||
|
||||
/* checks for EPC */
|
||||
if (bTagType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
if (bMaskBitLength != (PHPAL_EPCUID_EPC_LENGTH << 3U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
}
|
||||
/* checks for UID */
|
||||
else if (bTagType == PHPAL_EPCUID_LABEL_UID)
|
||||
{
|
||||
if (bMaskBitLength != (PHPAL_EPCUID_IDD_LENGTH << 3U))
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
|
||||
/* Set TxWait */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TXWAIT_US,
|
||||
PHPAL_EPCUID_SW_T1_MIN_US));
|
||||
|
||||
/* Execute Begin-Round with only 1 slot */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phpalEpcUid_Sw_BeginRound(
|
||||
pDataParams,
|
||||
bTagType,
|
||||
PHPAL_EPCUID_NUMSLOTS_1,
|
||||
pMask,
|
||||
bMaskBitLength,
|
||||
0x00,
|
||||
pDataParams->LabelInfo.bIdd,
|
||||
&bResponseLen));
|
||||
|
||||
/* Calculate CRC */
|
||||
if (pDataParams->bLabelType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phTools_CalculateCrc16(
|
||||
PH_TOOLS_CRC_OPTION_MSB_FIRST | PH_TOOLS_CRC_OPTION_OUPUT_INVERTED,
|
||||
PH_TOOLS_CRC16_PRESET_EPCUID,
|
||||
PH_TOOLS_CRC16_POLY_EPCUID,
|
||||
pDataParams->LabelInfo.bEpc,
|
||||
PHPAL_EPCUID_EPC_LENGTH,
|
||||
&wCrc16));
|
||||
}
|
||||
else
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phTools_CalculateCrc16(
|
||||
PH_TOOLS_CRC_OPTION_MSB_FIRST | PH_TOOLS_CRC_OPTION_OUPUT_INVERTED,
|
||||
PH_TOOLS_CRC16_PRESET_EPCUID,
|
||||
PH_TOOLS_CRC16_POLY_EPCUID,
|
||||
&pDataParams->LabelInfo.bIdd[PHPAL_EPCUID_EPC_LENGTH + 2U],
|
||||
PHPAL_EPCUID_IDD_LENGTH - (PHPAL_EPCUID_EPC_LENGTH + 2U),
|
||||
&wCrc16));
|
||||
}
|
||||
|
||||
/* Build fix-slot command (2 crc bytes) */
|
||||
aCommand[0] = (uint8_t)(wCrc16 >> 8U);
|
||||
aCommand[1] = (uint8_t)wCrc16;
|
||||
|
||||
/* set LSOF as start symbol */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_SYMBOL_START,
|
||||
PHHAL_HW_SYMBOL_ICODEEPCUID_LSOF));
|
||||
|
||||
/* set CEOF as end symbol */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_SYMBOL_END,
|
||||
PHHAL_HW_SYMBOL_ICODEEPCUID_CEOF));
|
||||
|
||||
/* Set RxWait */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_RXWAIT_US,
|
||||
PHPAL_EPCUID_SW_DEAFTIME_DEFAULT));
|
||||
|
||||
/* Set fix-slot timeout */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
1));
|
||||
|
||||
/* Send the command */
|
||||
status = phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCommand,
|
||||
2,
|
||||
&pResponse,
|
||||
&wResponseLen);
|
||||
|
||||
/* Timeout is the correct behaviour */
|
||||
if ((status & PH_ERR_MASK) != PH_ERR_IO_TIMEOUT)
|
||||
{
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
/* if data was received return an error */
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Return the received error */
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalEpcUid_Sw_Write(
|
||||
phpalEpcUid_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bTagType,
|
||||
uint8_t bBlockNo,
|
||||
uint8_t bData
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM aCommand[4];
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wResponseLen = 0;
|
||||
|
||||
/* checks for EPC */
|
||||
if (bTagType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
if (bBlockNo > PHPAL_EPCUID_EPC_MAXBLOCKNUMBER)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
}
|
||||
/* checks for UID */
|
||||
else if (bTagType == PHPAL_EPCUID_LABEL_UID)
|
||||
{
|
||||
if (bBlockNo > PHPAL_EPCUID_UID_MAXBLOCKNUMBER)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
|
||||
/* set SSOF as start symbol */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_SYMBOL_START,
|
||||
PHHAL_HW_SYMBOL_ICODEEPCUID_SSOF)
|
||||
);
|
||||
|
||||
/* set CEOF as end symbol */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_SYMBOL_END,
|
||||
PHHAL_HW_SYMBOL_ICODEEPCUID_CEOF)
|
||||
);
|
||||
|
||||
/* Set timeout to 6.4ms */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
PHPAL_EPCUID_SW_TIMEOUT_DEFAULT_US));
|
||||
|
||||
/* Build command frame */
|
||||
aCommand[0] = PHPAL_EPCUID_SW_CMD_WRITE;
|
||||
aCommand[1] = bBlockNo;
|
||||
aCommand[2] = bData;
|
||||
|
||||
/* Calculate CRC */
|
||||
if (bTagType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phTools_CalculateCrc8(
|
||||
PH_TOOLS_CRC_OPTION_MSB_FIRST,
|
||||
PH_TOOLS_CRC8_PRESET_EPC,
|
||||
PH_TOOLS_CRC8_POLY_EPCUID,
|
||||
aCommand,
|
||||
3,
|
||||
&aCommand[3]));
|
||||
}
|
||||
else
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phTools_CalculateCrc8(
|
||||
PH_TOOLS_CRC_OPTION_MSB_FIRST,
|
||||
PH_TOOLS_CRC8_PRESET_UID,
|
||||
PH_TOOLS_CRC8_POLY_EPCUID,
|
||||
aCommand,
|
||||
3,
|
||||
&aCommand[3]));
|
||||
}
|
||||
|
||||
/* Send the command */
|
||||
status = phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_DEFAULT,
|
||||
aCommand,
|
||||
4,
|
||||
&pResponse,
|
||||
&wResponseLen);
|
||||
|
||||
/* Timeout is the correct behaviour */
|
||||
if ((status & PH_ERR_MASK) != PH_ERR_IO_TIMEOUT)
|
||||
{
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
/* if data was received return an error */
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Return the received error */
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalEpcUid_Sw_Destroy(
|
||||
phpalEpcUid_Sw_DataParams_t * pDataParams,
|
||||
uint8_t bTagType,
|
||||
uint8_t * pData,
|
||||
uint8_t bDataLength,
|
||||
uint8_t * pDestroyCode
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM status;
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t PH_MEMLOC_REM bCrc8;
|
||||
uint8_t PH_MEMLOC_REM aCommand[1];
|
||||
uint8_t * PH_MEMLOC_REM pResponse = NULL;
|
||||
uint16_t PH_MEMLOC_REM wResponseLen = 0;
|
||||
|
||||
/* checks for EPC */
|
||||
if (bTagType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
if (bDataLength != PHPAL_EPCUID_EPC_LENGTH)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
}
|
||||
/* checks for UID */
|
||||
else if (bTagType == PHPAL_EPCUID_LABEL_UID)
|
||||
{
|
||||
if (bDataLength != PHPAL_EPCUID_IDD_LENGTH)
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INVALID_PARAMETER, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
|
||||
/* set SSOF as start symbol */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_SYMBOL_START,
|
||||
PHHAL_HW_SYMBOL_ICODEEPCUID_SSOF)
|
||||
);
|
||||
|
||||
/* set CEOF as end symbol */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_SYMBOL_END,
|
||||
PHHAL_HW_SYMBOL_ICODEEPCUID_CEOF)
|
||||
);
|
||||
|
||||
/* Set timeout to 6.4ms */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_SetConfig(
|
||||
pDataParams->pHalDataParams,
|
||||
PHHAL_HW_CONFIG_TIMEOUT_VALUE_US,
|
||||
PHPAL_EPCUID_SW_TIMEOUT_DEFAULT_US));
|
||||
|
||||
/* Set command code */
|
||||
aCommand[0] = PHPAL_EPCUID_SW_CMD_DESTROY;
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_BUFFER_FIRST,
|
||||
aCommand,
|
||||
1,
|
||||
NULL,
|
||||
NULL));
|
||||
|
||||
/* Append EPC/IDD */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_BUFFER_CONT,
|
||||
pData,
|
||||
(uint16_t)bDataLength,
|
||||
NULL,
|
||||
NULL));
|
||||
|
||||
/* Append Destroy Code */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_BUFFER_CONT,
|
||||
pDestroyCode,
|
||||
PHPAL_EPCUID_DESTROYCODE_LENGTH,
|
||||
NULL,
|
||||
NULL));
|
||||
|
||||
/* Calculate CRC over command */
|
||||
if (bTagType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phTools_CalculateCrc8(
|
||||
PH_TOOLS_CRC_OPTION_MSB_FIRST,
|
||||
PH_TOOLS_CRC8_PRESET_EPC,
|
||||
PH_TOOLS_CRC8_POLY_EPCUID,
|
||||
aCommand,
|
||||
1,
|
||||
&bCrc8));
|
||||
}
|
||||
else
|
||||
{
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phTools_CalculateCrc8(
|
||||
PH_TOOLS_CRC_OPTION_MSB_FIRST,
|
||||
PH_TOOLS_CRC8_PRESET_UID,
|
||||
PH_TOOLS_CRC8_POLY_EPCUID,
|
||||
aCommand,
|
||||
1,
|
||||
&bCrc8));
|
||||
}
|
||||
|
||||
/* Calculate CRC over data */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phTools_CalculateCrc8(
|
||||
PH_TOOLS_CRC_OPTION_MSB_FIRST,
|
||||
bCrc8,
|
||||
PH_TOOLS_CRC8_POLY_EPCUID,
|
||||
pData,
|
||||
(uint16_t)bDataLength,
|
||||
&bCrc8));
|
||||
|
||||
/* Calculate CRC over destroy-code */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phTools_CalculateCrc8(
|
||||
PH_TOOLS_CRC_OPTION_MSB_FIRST,
|
||||
bCrc8,
|
||||
PH_TOOLS_CRC8_POLY_EPCUID,
|
||||
pDestroyCode,
|
||||
PHPAL_EPCUID_DESTROYCODE_LENGTH,
|
||||
&bCrc8));
|
||||
|
||||
/* Append CRC and perform exchange */
|
||||
aCommand[0] = bCrc8;
|
||||
status = phhalHw_Exchange(
|
||||
pDataParams->pHalDataParams,
|
||||
PH_EXCHANGE_BUFFER_LAST,
|
||||
aCommand,
|
||||
1,
|
||||
&pResponse,
|
||||
&wResponseLen);
|
||||
|
||||
/* Timeout is the correct behaviour */
|
||||
if ((status & PH_ERR_MASK) != PH_ERR_IO_TIMEOUT)
|
||||
{
|
||||
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
|
||||
{
|
||||
/* if data was received return an error */
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Return the received error */
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
phStatus_t phpalEpcUid_Sw_GetSerialNo(
|
||||
phpalEpcUid_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pUidOut,
|
||||
uint8_t * pLenUidOut
|
||||
)
|
||||
{
|
||||
if (pDataParams->bUidValid != PH_OFF)
|
||||
{
|
||||
if (pDataParams->bLabelType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
*pLenUidOut = PHPAL_EPCUID_EPC_LENGTH;
|
||||
(void)memcpy(pUidOut, pDataParams->LabelInfo.bEpc, *pLenUidOut);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pLenUidOut = PHPAL_EPCUID_IDD_LENGTH;
|
||||
(void)memcpy(pUidOut, pDataParams->LabelInfo.bIdd, *pLenUidOut);
|
||||
}
|
||||
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
else
|
||||
{
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_USE_CONDITION, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
}
|
||||
|
||||
phStatus_t phpalEpcUid_Sw_ParseResponse(
|
||||
phpalEpcUid_Sw_DataParams_t * pDataParams,
|
||||
uint8_t * pRxBuffer,
|
||||
uint16_t wRxLength
|
||||
)
|
||||
{
|
||||
phStatus_t PH_MEMLOC_REM statusTmp;
|
||||
uint8_t * PH_MEMLOC_REM pEpcIddStorage = NULL;
|
||||
uint16_t PH_MEMLOC_REM wCrc16;
|
||||
uint16_t PH_MEMLOC_REM wLabelLenght;
|
||||
|
||||
/* Response check */
|
||||
if ((
|
||||
(pDataParams->bLabelType == PHPAL_EPCUID_LABEL_EPC) &&
|
||||
(wRxLength != (PHPAL_EPCUID_EPC_LENGTH + 2U - (((uint16_t)pDataParams->bMaskBitLength) >> 3U)))
|
||||
) ||
|
||||
(
|
||||
(pDataParams->bLabelType == PHPAL_EPCUID_LABEL_UID) &&
|
||||
(wRxLength != (PHPAL_EPCUID_IDD_LENGTH + 2U - (((uint16_t)pDataParams->bMaskBitLength) >> 3U)))
|
||||
))
|
||||
{
|
||||
pDataParams->bUidValid = PH_OFF;
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_PROTOCOL_ERROR, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
|
||||
/* Check where to store EPC/IDD */
|
||||
if (pDataParams->bLabelType == PHPAL_EPCUID_LABEL_EPC)
|
||||
{
|
||||
/* Copy EPC */
|
||||
(void)memcpy(&pDataParams->LabelInfo.bEpc[pDataParams->bMaskBitLength >> 3U], pRxBuffer, (((uint32_t)(wRxLength)) - 2u));
|
||||
|
||||
/* Set data paramters for CRC calculation */
|
||||
pEpcIddStorage = pDataParams->LabelInfo.bEpc;
|
||||
wLabelLenght = PHPAL_EPCUID_EPC_LENGTH;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Copy IDD */
|
||||
(void)memcpy(&pDataParams->LabelInfo.bIdd[pDataParams->bMaskBitLength >> 3U], pRxBuffer, (((uint32_t)(wRxLength)) - 2u));
|
||||
|
||||
/* Set data paramters for CRC calculation */
|
||||
pEpcIddStorage = &pDataParams->LabelInfo.bIdd[PHPAL_EPCUID_EPC_LENGTH + 2U];
|
||||
wLabelLenght = PHPAL_EPCUID_IDD_LENGTH - (PHPAL_EPCUID_EPC_LENGTH + 2U);
|
||||
}
|
||||
|
||||
/* Calculate CRC */
|
||||
PH_CHECK_SUCCESS_FCT(statusTmp, phTools_CalculateCrc16(
|
||||
PH_TOOLS_CRC_OPTION_MSB_FIRST | PH_TOOLS_CRC_OPTION_OUPUT_INVERTED,
|
||||
PH_TOOLS_CRC16_PRESET_EPCUID,
|
||||
PH_TOOLS_CRC16_POLY_EPCUID,
|
||||
pEpcIddStorage,
|
||||
wLabelLenght,
|
||||
&wCrc16));
|
||||
|
||||
/* Check CRC */
|
||||
if (((uint8_t)(wCrc16 >> 8U) != pRxBuffer[wRxLength-2u]) || ((uint8_t)(wCrc16) != pRxBuffer[wRxLength-1u]))
|
||||
{
|
||||
pDataParams->bUidValid = PH_OFF;
|
||||
return PH_ADD_COMPCODE_FIXED(PH_ERR_INTEGRITY_ERROR, PH_COMP_PAL_EPCUID);
|
||||
}
|
||||
|
||||
pDataParams->bUidValid = PH_ON;
|
||||
return PH_ERR_SUCCESS;
|
||||
}
|
||||
|
||||
#endif /* NXPBUILD__PHPAL_EPCUID_SW */
|
||||
@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors Gratkorn / Austria
|
||||
*
|
||||
* (C)NXP Semiconductors
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
*particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Rc663 functions of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* RSn: Generated 5. March 2010
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHKEYSTORE_RC663_INT_H
|
||||
#define PHKEYSTORE_RC663_INT_H
|
||||
|
||||
#include <ph_Status.h>
|
||||
|
||||
#define PH_KEYSTORE_RC663_EEP_WR_TO_MS 06U /**< Time out to perform EEPROM write in milliseconds. */
|
||||
|
||||
/**
|
||||
* \name Rc663 register definitions
|
||||
*/
|
||||
/*@{*/
|
||||
#define PH_KEYSTORE_RC663_REG_COMMAND 0x00U /**< Command register. */
|
||||
#define PH_KEYSTORE_RC663_REG_FIFOCONTROL 0x02U /**< FIFO Control register. */
|
||||
#define PH_KEYSTORE_RC663_REG_FIFODATA 0x05U /**< FIFO Data register. */
|
||||
#define PH_KEYSTORE_RC663_REG_IRQ0 0x06U /**< Interrupt 0 register. */
|
||||
#define PH_KEYSTORE_RC663_REG_IRQ1 0x07U /**< Interrupt 1 register. */
|
||||
|
||||
/* Bit definitions */
|
||||
#define PH_KEYSTORE_RC663_BIT_IRQ_SET 0x80U /**< Bit SET of the Irq registers. */
|
||||
|
||||
/* Control register */
|
||||
#define PH_KEYSTORE_RC663_BIT_FLUSHFIFO 0x10U /**< Clears internal FIFO buffer when set. */
|
||||
|
||||
/* Command set */
|
||||
#define PH_KEYSTORE_RC663_CMD_IDLE 0x00U /**< Command Idle. */
|
||||
#define PH_KEYSTORE_RC663_CMD_STOREKEYE2 0x0FU /**< Command to store keys in EE. */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \brief Write Store Keys in Eeprom command implementation.
|
||||
* \return Status code
|
||||
* \retval #PH_ERR_SUCCESS Operation successful.
|
||||
*/
|
||||
phStatus_t phKeyStore_Rc663_StoreKeyE2_Int(
|
||||
phKeyStore_Rc663_DataParams_t * pDataParams,
|
||||
uint8_t bKeyNumber,
|
||||
uint8_t * pKey,
|
||||
uint8_t bNumKeys
|
||||
);
|
||||
/** @}
|
||||
* end of phKeyStore_Rc663
|
||||
*/
|
||||
|
||||
#endif /* PHKEYSTORE_RC663_INT_H */
|
||||
3314
.svn/pristine/1b/1b3a7179964752eaa16c31cd81b5302b7ba82a2f.svn-base
Normal file
3314
.svn/pristine/1b/1b3a7179964752eaa16c31cd81b5302b7ba82a2f.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
2646
.svn/pristine/1b/1bca59eb2f8076864aec860dc1af4f9aaf74dd7d.svn-base
Normal file
2646
.svn/pristine/1b/1bca59eb2f8076864aec860dc1af4f9aaf74dd7d.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (c), NXP Semiconductors Bangalore / India
|
||||
*
|
||||
* (C)NXP Semiconductors
|
||||
* All rights are reserved. Reproduction in whole or in part is
|
||||
* prohibited without the written consent of the copyright owner.
|
||||
* NXP reserves the right to make changes without notice at any time.
|
||||
* NXP makes no warranty, expressed, implied or statutory, including but
|
||||
* not limited to any implied warranty of merchantability or fitness for any
|
||||
* particular purpose, or that the use will not infringe any third party patent,
|
||||
* copyright or trademark. NXP must not be liable for any loss or damage
|
||||
* arising from its use.
|
||||
*/
|
||||
|
||||
/** \file
|
||||
* Reference application file for Type B interface of Simplified API
|
||||
* $Author: Ashish Pal (nxp79566) $
|
||||
* $Revision: 5458 $ (v07.10.00)
|
||||
* $Date: 2016-09-01 19:11:09 +0530 (Thu, 01 Sept 2016) $
|
||||
*
|
||||
* History:
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#include <Nfcrdlib_SimplifiedApi_ISO.h>
|
||||
|
||||
extern phNfcLib_Transmit_t phNfcLib_TransmitInput;
|
||||
extern phNfcLib_PeerInfo_t PeerInfo;
|
||||
|
||||
extern uint8_t bMoreDataAvailable;
|
||||
extern uint16_t wNumberofBytes;
|
||||
extern uint8_t bDataBuffer[256];
|
||||
|
||||
/*
|
||||
* This application is to demonstrate the usage of simplified API related to Type B
|
||||
* The application reaches to this point only after the activation of a card of Type B technology with
|
||||
* or without ISO 14443-4 compatibilty is done. Transmit api is used to perform any command exchange with the card and
|
||||
* receive api is used to get back the out data.
|
||||
*/
|
||||
uint32_t NfcLib_TypeB_Reference_app()
|
||||
{
|
||||
uint32_t dwStatus;
|
||||
uint8_t bData[6] = {0};
|
||||
do
|
||||
{
|
||||
|
||||
/*************************************************************************************************************************
|
||||
****************************************ISO 14443-4 EXCHANGE ************************************************************
|
||||
*************************************************************************************************************************/
|
||||
|
||||
/*
|
||||
* To perform ISO14443-4 layer exchange first form the command in bData
|
||||
* this is get challenge command of ISO7816-4
|
||||
*/
|
||||
bData[0] = 0x00; /* INF1 */
|
||||
bData[1] = 0x84; /* INF2 */
|
||||
bData[2] = 0x00; /* INF3 */
|
||||
bData[3] = 0x00; /* INF4 */
|
||||
bData[4] = 0x08; /* INF4 */
|
||||
|
||||
phNfcLib_TransmitInput.phNfcLib_RawTransmit.pBuffer = &bData[0];
|
||||
|
||||
/* Finally the command has to be sent, the command for Type B with layer 4 compatibility will be send with ISO 7816 - 4*/
|
||||
dwStatus = phNfcLib_Transmit(&phNfcLib_TransmitInput,
|
||||
0x05 /* Length of this exchange is 5 bytes*/
|
||||
);
|
||||
|
||||
/* The status should be success, if not break from the application */
|
||||
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS)
|
||||
{
|
||||
DEBUG_PRINTF("\nGet Challenge failed");
|
||||
break;
|
||||
}
|
||||
|
||||
/* This parameter has to be reset before every receive */
|
||||
wNumberofBytes = 256;
|
||||
|
||||
/*The data received over the above command can be retrieved by calling the receive */
|
||||
/* wNumberofBytes first as input tells the max supported recieve size and then as out tells the actual number of data bytes received */
|
||||
/* wNumberofBytes will vary depending upon the card layout*/
|
||||
dwStatus = phNfcLib_Receive(&bDataBuffer[0],
|
||||
&wNumberofBytes,
|
||||
&bMoreDataAvailable
|
||||
);
|
||||
|
||||
DEBUG_PRINTF("\nReply to get challenge is\n");
|
||||
phApp_Print_Buff(&bDataBuffer[0], wNumberofBytes);
|
||||
/*************************************************************************************************************************/
|
||||
|
||||
}while(0);
|
||||
|
||||
return dwStatus;
|
||||
|
||||
}
|
||||
1674
.svn/pristine/1c/1c4d899edf1b972147f76e8595a5f7ec84907701.svn-base
Normal file
1674
.svn/pristine/1c/1c4d899edf1b972147f76e8595a5f7ec84907701.svn-base
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,744 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _FSL_QSPI_H_
|
||||
#define _FSL_QSPI_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup qspi_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief QSPI driver version 2.2.0. */
|
||||
#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief Macro functions for LUT table */
|
||||
#define QSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(QuadSPI_LUT_INSTR0(cmd0) | QuadSPI_LUT_PAD0(pad0) | QuadSPI_LUT_OPRND0(op0) | QuadSPI_LUT_INSTR1(cmd1) | \
|
||||
QuadSPI_LUT_PAD1(pad1) | QuadSPI_LUT_OPRND1(op1))
|
||||
|
||||
/*! @brief Macro for QSPI LUT command */
|
||||
#define QSPI_CMD (0x1U)
|
||||
#define QSPI_ADDR (0x2U)
|
||||
#define QSPI_DUMMY (0x3U)
|
||||
#define QSPI_MODE (0x4U)
|
||||
#define QSPI_MODE2 (0x5U)
|
||||
#define QSPI_MODE4 (0x6U)
|
||||
#define QSPI_READ (0x7U)
|
||||
#define QSPI_WRITE (0x8U)
|
||||
#define QSPI_JMP_ON_CS (0x9U)
|
||||
#define QSPI_ADDR_DDR (0xAU)
|
||||
#define QSPI_MODE_DDR (0xBU)
|
||||
#define QSPI_MODE2_DDR (0xCU)
|
||||
#define QSPI_MODE4_DDR (0xDU)
|
||||
#define QSPI_READ_DDR (0xEU)
|
||||
#define QSPI_WRITE_DDR (0xFU)
|
||||
#define QSPI_DATA_LEARN (0x10U)
|
||||
#define QSPI_CMD_DDR (0x11U)
|
||||
#define QSPI_CADDR (0x12U)
|
||||
#define QSPI_CADDR_DDR (0x13U)
|
||||
#define QSPI_STOP (0x0U)
|
||||
|
||||
/*! @brief Macro for QSPI PAD */
|
||||
#define QSPI_PAD_1 (0x0U)
|
||||
#define QSPI_PAD_2 (0x1U)
|
||||
#define QSPI_PAD_4 (0x2U)
|
||||
#define QSPI_PAD_8 (0x3U)
|
||||
|
||||
/*! @brief Status structure of QSPI.*/
|
||||
enum _status_t
|
||||
{
|
||||
kStatus_QSPI_Idle = MAKE_STATUS(kStatusGroup_QSPI, 0), /*!< QSPI is in idle state */
|
||||
kStatus_QSPI_Busy = MAKE_STATUS(kStatusGroup_QSPI, 1), /*!< QSPI is busy */
|
||||
kStatus_QSPI_Error = MAKE_STATUS(kStatusGroup_QSPI, 2), /*!< Error occurred during QSPI transfer */
|
||||
};
|
||||
|
||||
/*! @brief QSPI read data area, from IP FIFO or AHB buffer.*/
|
||||
typedef enum _qspi_read_area
|
||||
{
|
||||
kQSPI_ReadAHB = 0x0U, /*!< QSPI read from AHB buffer. */
|
||||
kQSPI_ReadIP /*!< QSPI read from IP FIFO. */
|
||||
} qspi_read_area_t;
|
||||
|
||||
/*! @brief QSPI command sequence type */
|
||||
typedef enum _qspi_command_seq
|
||||
{
|
||||
kQSPI_IPSeq = QuadSPI_SPTRCLR_IPPTRC_MASK, /*!< IP command sequence */
|
||||
kQSPI_BufferSeq = QuadSPI_SPTRCLR_BFPTRC_MASK, /*!< Buffer command sequence */
|
||||
kQSPI_AllSeq = QuadSPI_SPTRCLR_IPPTRC_MASK | QuadSPI_SPTRCLR_BFPTRC_MASK /* All command sequence */
|
||||
} qspi_command_seq_t;
|
||||
|
||||
/*! @brief QSPI buffer type */
|
||||
typedef enum _qspi_fifo
|
||||
{
|
||||
kQSPI_TxFifo = QuadSPI_MCR_CLR_TXF_MASK, /*!< QSPI Tx FIFO */
|
||||
kQSPI_RxFifo = QuadSPI_MCR_CLR_RXF_MASK, /*!< QSPI Rx FIFO */
|
||||
kQSPI_AllFifo = QuadSPI_MCR_CLR_TXF_MASK | QuadSPI_MCR_CLR_RXF_MASK /*!< QSPI all FIFO, including Tx and Rx */
|
||||
} qspi_fifo_t;
|
||||
|
||||
/*! @brief QSPI transfer endianess*/
|
||||
typedef enum _qspi_endianness
|
||||
{
|
||||
kQSPI_64BigEndian = 0x0U, /*!< 64 bits big endian */
|
||||
kQSPI_32LittleEndian, /*!< 32 bit little endian */
|
||||
kQSPI_32BigEndian, /*!< 32 bit big endian */
|
||||
kQSPI_64LittleEndian /*!< 64 bit little endian */
|
||||
} qspi_endianness_t;
|
||||
|
||||
/*! @brief QSPI error flags */
|
||||
enum _qspi_error_flags
|
||||
{
|
||||
kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
|
||||
kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */
|
||||
kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */
|
||||
kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */
|
||||
kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */
|
||||
kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */
|
||||
kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */
|
||||
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
|
||||
kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */
|
||||
#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
|
||||
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
|
||||
kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */
|
||||
#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
|
||||
kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */
|
||||
#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
|
||||
kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK, /*!< IP command usage error flag */
|
||||
#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
|
||||
kQSPI_IPCommandTriggerDuringAHBAccess = QuadSPI_FR_IPAEF_MASK, /*!< IP command trigger during AHB access error */
|
||||
kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK, /*!< IP command trigger cannot be executed */
|
||||
kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, /*!< IP command trigger during AHB grant error */
|
||||
kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, /*!< IP command transaction finished flag */
|
||||
kQSPI_FlagAll = (int)0x8C83F8D1U /*!< All error flag */
|
||||
};
|
||||
|
||||
/*! @brief QSPI state bit */
|
||||
enum _qspi_flags
|
||||
{
|
||||
kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
|
||||
kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */
|
||||
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
|
||||
kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK, /*!< Tx DMA is requested or running */
|
||||
kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK, /*!< Tx buffer watermark available */
|
||||
#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
|
||||
kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, /*!< Tx buffer enough data available */
|
||||
kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, /*!< Rx DMA is requesting or running */
|
||||
kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */
|
||||
kQSPI_RxWatermark = QuadSPI_SR_RXWE_MASK, /*!< Rx buffer watermark exceeded */
|
||||
kQSPI_AHB3BufferFull = QuadSPI_SR_AHB3FUL_MASK, /*!< AHB buffer 3 full*/
|
||||
kQSPI_AHB2BufferFull = QuadSPI_SR_AHB2FUL_MASK, /*!< AHB buffer 2 full */
|
||||
kQSPI_AHB1BufferFull = QuadSPI_SR_AHB1FUL_MASK, /*!< AHB buffer 1 full */
|
||||
kQSPI_AHB0BufferFull = QuadSPI_SR_AHB0FUL_MASK, /*!< AHB buffer 0 full */
|
||||
kQSPI_AHB3BufferNotEmpty = QuadSPI_SR_AHB3NE_MASK, /*!< AHB buffer 3 not empty */
|
||||
kQSPI_AHB2BufferNotEmpty = QuadSPI_SR_AHB2NE_MASK, /*!< AHB buffer 2 not empty */
|
||||
kQSPI_AHB1BufferNotEmpty = QuadSPI_SR_AHB1NE_MASK, /*!< AHB buffer 1 not empty */
|
||||
kQSPI_AHB0BufferNotEmpty = QuadSPI_SR_AHB0NE_MASK, /*!< AHB buffer 0 not empty */
|
||||
kQSPI_AHBTransactionPending = QuadSPI_SR_AHBTRN_MASK, /*!< AHB access transaction pending */
|
||||
kQSPI_AHBCommandPriorityGranted = QuadSPI_SR_AHBGNT_MASK, /*!< AHB command priority granted */
|
||||
kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, /*!< AHB access */
|
||||
kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, /*!< IP access */
|
||||
kQSPI_Busy = QuadSPI_SR_BUSY_MASK, /*!< Module busy */
|
||||
kQSPI_StateAll = (int)0xEF897FE7U /*!< All flags */
|
||||
};
|
||||
|
||||
/*! @brief QSPI interrupt enable */
|
||||
enum _qspi_interrupt_enable
|
||||
{
|
||||
kQSPI_DataLearningFailInterruptEnable =
|
||||
(int)QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
|
||||
kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */
|
||||
kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */
|
||||
kQSPI_IllegalInstructionInterruptEnable =
|
||||
QuadSPI_RSER_ILLINIE_MASK, /*!< Illegal instruction error interrupt enable */
|
||||
kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK, /*!< Rx buffer overflow interrupt enable */
|
||||
kQSPI_RxBufferDrainInterruptEnable = QuadSPI_RSER_RBDIE_MASK, /*!< Rx buffer drain interrupt enable */
|
||||
kQSPI_AHBSequenceErrorInterruptEnable = QuadSPI_RSER_ABSEIE_MASK, /*!< AHB sequence error interrupt enable */
|
||||
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
|
||||
kQSPI_AHBIllegalTransactionInterruptEnable =
|
||||
QuadSPI_RSER_AITIE_MASK, /*!< AHB illegal transaction error interrupt enable */
|
||||
#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
|
||||
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
|
||||
kQSPI_AHBIllegalBurstSizeInterruptEnable =
|
||||
QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */
|
||||
#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
|
||||
kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */
|
||||
#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
|
||||
kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, /*!< IP command usage error interrupt enable */
|
||||
#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
|
||||
kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable =
|
||||
QuadSPI_RSER_IPAEIE_MASK, /*!< IP command trigger during AHB access error */
|
||||
kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable =
|
||||
QuadSPI_RSER_IPIEIE_MASK, /*!< IP command trigger cannot be executed */
|
||||
kQSPI_IPCommandTriggerDuringAHBGrantInterruptEnable =
|
||||
QuadSPI_RSER_IPGEIE_MASK, /*!< IP command trigger during AHB grant error */
|
||||
kQSPI_IPCommandTransactionFinishedInterruptEnable =
|
||||
QuadSPI_RSER_TFIE_MASK, /*!< IP command transaction finished interrupt enable */
|
||||
kQSPI_AllInterruptEnable = (int)0x8C83F8D1U /*!< All error interrupt enable */
|
||||
};
|
||||
|
||||
/*! @brief QSPI DMA request flag */
|
||||
enum _qspi_dma_enable
|
||||
{
|
||||
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
|
||||
kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK, /*!< Tx buffer fill DMA */
|
||||
#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
|
||||
kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK, /*!< Rx buffer drain DMA */
|
||||
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
|
||||
kQSPI_AllDDMAEnable = QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK /*!< All DMA source */
|
||||
#else
|
||||
kQSPI_AllDDMAEnable = QuadSPI_RSER_RBDDE_MASK /* All DMA source */
|
||||
#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
|
||||
};
|
||||
|
||||
/*! @brief Phrase shift number for DQS mode. */
|
||||
typedef enum _qspi_dqs_phrase_shift
|
||||
{
|
||||
kQSPI_DQSNoPhraseShift = 0x0U, /*!< No phase shift */
|
||||
kQSPI_DQSPhraseShift45Degree, /*!< Select 45 degree phase shift*/
|
||||
kQSPI_DQSPhraseShift90Degree, /*!< Select 90 degree phase shift */
|
||||
kQSPI_DQSPhraseShift135Degree /*!< Select 135 degree phase shift */
|
||||
} qspi_dqs_phrase_shift_t;
|
||||
|
||||
/*! @brief Qspi read sampling option. */
|
||||
typedef enum _qspi_dqs_read_sample_clock
|
||||
{
|
||||
kQSPI_ReadSampleClkInternalLoopback = 0x0U, /*!< Read sample clock adopts internal loopback mode. */
|
||||
kQSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by QSPI Controller
|
||||
and loopback from DQS pad. */
|
||||
kQSPI_ReadSampleClkExternalInputFromDqsPad = 0x2U, /*!< Flash provided Read strobe and input from DQS pad. */
|
||||
} qspi_dqs_read_sample_clock_t;
|
||||
|
||||
/*! @brief DQS configure features*/
|
||||
typedef struct QspiDQSConfig
|
||||
{
|
||||
uint32_t portADelayTapNum; /*!< Delay chain tap number selection for QSPI port A DQS */
|
||||
#if defined(QuadSPI_SOCCR_DQS_IFB_DELAY_CHAIN_SEL_MASK)
|
||||
uint32_t portBDelayTapNum; /*!< Delay chain tap number selection for QSPI port B DQS*/
|
||||
#endif
|
||||
qspi_dqs_phrase_shift_t shift; /*!< Phase shift for internal DQS generation */
|
||||
qspi_dqs_read_sample_clock_t rxSampleClock; /*!< Read sample clock for Dqs. */
|
||||
bool enableDQSClkInverse; /*!< Enable inverse clock for internal DQS generation */
|
||||
} qspi_dqs_config_t;
|
||||
|
||||
/*! @brief Flash timing configuration. */
|
||||
typedef struct QspiFlashTiming
|
||||
{
|
||||
uint32_t dataHoldTime; /*!< Serial flash data in hold time */
|
||||
uint32_t CSHoldTime; /*!< Serial flash CS hold time in terms of serial flash clock cycles */
|
||||
uint32_t CSSetupTime; /*!< Serial flash CS setup time in terms of serial flash clock cycles */
|
||||
} qspi_flash_timing_t;
|
||||
|
||||
/*! @brief QSPI configuration structure*/
|
||||
typedef struct QspiConfig
|
||||
{
|
||||
uint32_t clockSource; /*!< Clock source for QSPI module */
|
||||
uint32_t baudRate; /*!< Serial flash clock baud rate */
|
||||
uint8_t txWatermark; /*!< QSPI transmit watermark value */
|
||||
uint8_t rxWatermark; /*!< QSPI receive watermark value. */
|
||||
uint32_t AHBbufferSize[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */
|
||||
uint8_t AHBbufferMaster[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer master. */
|
||||
bool enableAHBbuffer3AllMaster; /*!< Is AHB buffer3 for all master.*/
|
||||
qspi_read_area_t area; /*!< Which area Rx data readout */
|
||||
bool enableQspi; /*!< Enable QSPI after initialization */
|
||||
} qspi_config_t;
|
||||
|
||||
/*! @brief External flash configuration items*/
|
||||
typedef struct _qspi_flash_config
|
||||
{
|
||||
uint32_t flashA1Size; /*!< Flash A1 size */
|
||||
uint32_t flashA2Size; /*!< Flash A2 size */
|
||||
#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
|
||||
uint32_t flashB1Size; /*!< Flash B1 size */
|
||||
uint32_t flashB2Size; /*!< Flash B2 size */
|
||||
#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
|
||||
uint32_t lookuptable[FSL_FEATURE_QSPI_LUT_DEPTH]; /*!< Flash command in LUT */
|
||||
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
|
||||
uint32_t dataHoldTime; /*!< Data line hold time. */
|
||||
#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
|
||||
uint32_t CSHoldTime; /*!< CS line hold time */
|
||||
uint32_t CSSetupTime; /*!< CS line setup time*/
|
||||
uint32_t cloumnspace; /*!< Column space size */
|
||||
uint32_t dataLearnValue; /*!< Data Learn value if enable data learn */
|
||||
qspi_endianness_t endian; /*!< Flash data endianess. */
|
||||
bool enableWordAddress; /*!< If enable word address.*/
|
||||
} qspi_flash_config_t;
|
||||
|
||||
/*! @brief Transfer structure for QSPI */
|
||||
typedef struct _qspi_transfer
|
||||
{
|
||||
uint32_t *data; /*!< Pointer to data to transmit */
|
||||
size_t dataSize; /*!< Bytes to be transmit */
|
||||
} qspi_transfer_t;
|
||||
|
||||
/*! @brief 16-bit access reg for IPCR register */
|
||||
typedef struct _ip_command_config
|
||||
{
|
||||
union
|
||||
{
|
||||
__IO uint32_t IPCR; /*!< IP Configuration Register */
|
||||
struct
|
||||
{
|
||||
__IO uint16_t IDATZ; /*!< 16-bit access for IDATZ field in IPCR register */
|
||||
__IO uint8_t RESERVED_0; /*!< 8-bit access for RESERVED_0 field in IPCR register */
|
||||
__IO uint8_t SEQID; /*!< 8-bit access for SEQID field in IPCR register */
|
||||
} BITFIELD;
|
||||
} IPCR_REG;
|
||||
} ip_command_config_t;
|
||||
|
||||
/******************************************************************************
|
||||
* API
|
||||
*****************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Get the instance number for QSPI.
|
||||
*
|
||||
* @param base QSPI base pointer.
|
||||
*/
|
||||
uint32_t QSPI_GetInstance(QuadSPI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Initializes the QSPI module and internal state.
|
||||
*
|
||||
* This function enables the clock for QSPI and also configures the QSPI with the
|
||||
* input configure parameters. Users should call this function before any QSPI operations.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param config QSPI configure structure.
|
||||
* @param srcClock_Hz QSPI source clock frequency in Hz.
|
||||
*/
|
||||
void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Gets default settings for QSPI.
|
||||
*
|
||||
* @param config QSPI configuration structure.
|
||||
*/
|
||||
void QSPI_GetDefaultQspiConfig(qspi_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the QSPI module.
|
||||
*
|
||||
* Clears the QSPI state and QSPI module registers.
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
*/
|
||||
void QSPI_Deinit(QuadSPI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Configures the serial flash parameter.
|
||||
*
|
||||
* This function configures the serial flash relevant parameters, such as the size, command, and so on.
|
||||
* The flash configuration value cannot have a default value. The user needs to configure it according to the
|
||||
* QSPI features.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param config Flash configuration parameters.
|
||||
*/
|
||||
void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config);
|
||||
|
||||
#if (!defined(FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG)) || !FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG
|
||||
/*!
|
||||
* @brief Configures the serial flash DQS parameter.
|
||||
*
|
||||
* This function configures the serial flash DQS relevant parameters, such as the delay chain tap number, .
|
||||
* DQS shift phase, whether need to inverse and the rxc sample clock selection.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param config Dqs configuration parameters.
|
||||
*/
|
||||
void QSPI_SetDqsConfig(QuadSPI_Type *base, qspi_dqs_config_t *config);
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Software reset for the QSPI logic.
|
||||
*
|
||||
* This function sets the software reset flags for both AHB and buffer domain and
|
||||
* resets both AHB buffer and also IP FIFOs.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
*/
|
||||
void QSPI_SoftwareReset(QuadSPI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables the QSPI module.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param enable True means enable QSPI, false means disable.
|
||||
*/
|
||||
static inline void QSPI_Enable(QuadSPI_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->MCR &= ~QuadSPI_MCR_MDIS_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->MCR |= QuadSPI_MCR_MDIS_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* @name Status
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the state value of QSPI.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @return status flag, use status flag to AND #_qspi_flags could get the related status.
|
||||
*/
|
||||
static inline uint32_t QSPI_GetStatusFlags(QuadSPI_Type *base)
|
||||
{
|
||||
return base->SR;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets QSPI error status flags.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @return status flag, use status flag to AND #_qspi_error_flags could get the related status.
|
||||
*/
|
||||
static inline uint32_t QSPI_GetErrorStatusFlags(QuadSPI_Type *base)
|
||||
{
|
||||
return base->FR;
|
||||
}
|
||||
|
||||
/*! @brief Clears the QSPI error flags.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param mask Which kind of QSPI flags to be cleared, a combination of _qspi_error_flags.
|
||||
*/
|
||||
static inline void QSPI_ClearErrorFlag(QuadSPI_Type *base, uint32_t mask)
|
||||
{
|
||||
base->FR = mask;
|
||||
}
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* @name Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the QSPI interrupts.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param mask QSPI interrupt source.
|
||||
*/
|
||||
static inline void QSPI_EnableInterrupts(QuadSPI_Type *base, uint32_t mask)
|
||||
{
|
||||
base->RSER |= mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the QSPI interrupts.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param mask QSPI interrupt source.
|
||||
*/
|
||||
static inline void QSPI_DisableInterrupts(QuadSPI_Type *base, uint32_t mask)
|
||||
{
|
||||
base->RSER &= ~mask;
|
||||
}
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* @name DMA Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the QSPI DMA source.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param mask QSPI DMA source.
|
||||
* @param enable True means enable DMA, false means disable.
|
||||
*/
|
||||
static inline void QSPI_EnableDMA(QuadSPI_Type *base, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->RSER |= mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->RSER &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the Tx data register address. It is used for DMA operation.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @return QSPI Tx data register address.
|
||||
*/
|
||||
static inline uint32_t QSPI_GetTxDataRegisterAddress(QuadSPI_Type *base)
|
||||
{
|
||||
return (uint32_t)(&base->TBDR);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the Rx data register address used for DMA operation.
|
||||
*
|
||||
* This function returns the Rx data register address or Rx buffer address
|
||||
* according to the Rx read area settings.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @return QSPI Rx data register address.
|
||||
*/
|
||||
uint32_t QSPI_GetRxDataRegisterAddress(QuadSPI_Type *base);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Bus Operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief Sets the IP command address.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param addr IP command address.
|
||||
*/
|
||||
static inline void QSPI_SetIPCommandAddress(QuadSPI_Type *base, uint32_t addr)
|
||||
{
|
||||
base->SFAR = addr;
|
||||
}
|
||||
|
||||
/*! @brief Sets the IP command size.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param size IP command size.
|
||||
*/
|
||||
static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint32_t size)
|
||||
{
|
||||
ip_command_config_t *ipCommand = (ip_command_config_t *)(&(base->IPCR));
|
||||
ipCommand->IPCR_REG.BITFIELD.IDATZ = QuadSPI_IPCR_IDATSZ(size);
|
||||
}
|
||||
|
||||
/*! @brief Executes IP commands located in LUT table.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param index IP command located in which LUT table index.
|
||||
*/
|
||||
void QSPI_ExecuteIPCommand(QuadSPI_Type *base, uint32_t index);
|
||||
|
||||
/*! @brief Executes AHB commands located in LUT table.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param index AHB command located in which LUT table index.
|
||||
*/
|
||||
void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index);
|
||||
|
||||
#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
|
||||
/*! @brief Enables/disables the QSPI IP command parallel mode.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param enable True means enable parallel mode, false means disable parallel mode.
|
||||
*/
|
||||
static inline void QSPI_EnableIPParallelMode(QuadSPI_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->IPCR |= QuadSPI_IPCR_PAR_EN_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->IPCR &= ~QuadSPI_IPCR_PAR_EN_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*! @brief Enables/disables the QSPI AHB command parallel mode.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param enable True means enable parallel mode, false means disable parallel mode.
|
||||
*/
|
||||
static inline void QSPI_EnableAHBParallelMode(QuadSPI_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->BFGENCR |= QuadSPI_BFGENCR_PAR_EN_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->BFGENCR &= ~QuadSPI_BFGENCR_PAR_EN_MASK;
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
|
||||
|
||||
/*! @brief Updates the LUT table.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param index Which LUT index needs to be located. It should be an integer divided by 4.
|
||||
* @param cmd Command sequence array.
|
||||
*/
|
||||
void QSPI_UpdateLUT(QuadSPI_Type *base, uint32_t index, uint32_t *cmd);
|
||||
|
||||
/*! @brief Clears the QSPI FIFO logic.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param mask Which kind of QSPI FIFO to be cleared.
|
||||
*/
|
||||
static inline void QSPI_ClearFifo(QuadSPI_Type *base, uint32_t mask)
|
||||
{
|
||||
base->MCR |= mask;
|
||||
}
|
||||
|
||||
/*!@ brief Clears the command sequence for the IP/buffer command.
|
||||
*
|
||||
* This function can reset the command sequence.
|
||||
* @param base QSPI base address.
|
||||
* @param seq Which command sequence need to reset, IP command, buffer command or both.
|
||||
*/
|
||||
static inline void QSPI_ClearCommandSequence(QuadSPI_Type *base, qspi_command_seq_t seq)
|
||||
{
|
||||
base->SPTRCLR = seq;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable or disable DDR mode.
|
||||
*
|
||||
* @param base QSPI base pointer
|
||||
* @param eanble True means enable DDR mode, false means disable DDR mode.
|
||||
*/
|
||||
static inline void QSPI_EnableDDRMode(QuadSPI_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->MCR |= QuadSPI_MCR_DDR_EN_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->MCR &= ~QuadSPI_MCR_DDR_EN_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
|
||||
|
||||
/*! @brief Clears the QSPI cache.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
*/
|
||||
void QSPI_ClearCache(QuadSPI_Type *base);
|
||||
#endif
|
||||
|
||||
/*!@ brief Set the RX buffer readout area.
|
||||
*
|
||||
* This function can set the RX buffer readout, from AHB bus or IP Bus.
|
||||
* @param base QSPI base address.
|
||||
* @param area QSPI Rx buffer readout area. AHB bus buffer or IP bus buffer.
|
||||
*/
|
||||
void QSPI_SetReadDataArea(QuadSPI_Type *base, qspi_read_area_t area);
|
||||
|
||||
/*!
|
||||
* @brief Sends a buffer of data bytes using a blocking method.
|
||||
* @note This function blocks via polling until all bytes have been sent.
|
||||
* @param base QSPI base pointer
|
||||
* @param buffer The data bytes to send
|
||||
* @param size The number of data bytes to send
|
||||
*/
|
||||
void QSPI_WriteBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size);
|
||||
|
||||
/*!
|
||||
* @brief Writes data into FIFO.
|
||||
*
|
||||
* @param base QSPI base pointer
|
||||
* @param data The data bytes to send
|
||||
*/
|
||||
static inline void QSPI_WriteData(QuadSPI_Type *base, uint32_t data)
|
||||
{
|
||||
base->TBDR = data;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Receives a buffer of data bytes using a blocking method.
|
||||
* @note This function blocks via polling until all bytes have been sent. Users shall notice that
|
||||
* this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
|
||||
* For flash contents read, please use AHB bus read, this is much more efficiency.
|
||||
*
|
||||
* @param base QSPI base pointer
|
||||
* @param buffer The data bytes to send
|
||||
* @param size The number of data bytes to receive
|
||||
*/
|
||||
void QSPI_ReadBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size);
|
||||
|
||||
/*!
|
||||
* @brief Receives data from data FIFO.
|
||||
*
|
||||
* @param base QSPI base pointer
|
||||
* @return The data in the FIFO.
|
||||
*/
|
||||
uint32_t QSPI_ReadData(QuadSPI_Type *base);
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* @name Transactional
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Writes data to the QSPI transmit buffer.
|
||||
*
|
||||
* This function writes a continuous data to the QSPI transmit FIFO. This function is a block function
|
||||
* and can return only when finished. This function uses polling methods.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param xfer QSPI transfer structure.
|
||||
*/
|
||||
static inline void QSPI_TransferSendBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)
|
||||
{
|
||||
QSPI_WriteBlocking(base, xfer->data, xfer->dataSize);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads data from the QSPI receive buffer in polling way.
|
||||
*
|
||||
* This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking
|
||||
* function and can return only when finished. This function uses polling methods. Users shall notice that
|
||||
* this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
|
||||
* For flash contents read, please use AHB bus read, this is much more efficiency.
|
||||
*
|
||||
* @param base Pointer to QuadSPI Type.
|
||||
* @param xfer QSPI transfer structure.
|
||||
*/
|
||||
static inline void QSPI_TransferReceiveBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)
|
||||
{
|
||||
QSPI_ReadBlocking(base, xfer->data, xfer->dataSize);
|
||||
}
|
||||
|
||||
/*! @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* @}*/
|
||||
|
||||
#endif /* _FSL_QSPI_H_*/
|
||||
@ -0,0 +1,85 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3 LTS Patch 2
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
SECTION .text:CODE:NOROOT(2)
|
||||
THUMB
|
||||
|
||||
/* Including FreeRTOSConfig.h here will cause build errors if the header file
|
||||
contains code not understood by the assembler - for example the 'extern' keyword.
|
||||
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
|
||||
the code is included in C files but excluded by the preprocessor in assembly
|
||||
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
|
||||
#include "FreeRTOSConfig.h"
|
||||
|
||||
PUBLIC SecureContext_LoadContextAsm
|
||||
PUBLIC SecureContext_SaveContextAsm
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
SecureContext_LoadContextAsm:
|
||||
/* pxSecureContext value is in r0. */
|
||||
mrs r1, ipsr /* r1 = IPSR. */
|
||||
cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
|
||||
ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
|
||||
msr control, r3 /* CONTROL = r3. */
|
||||
#endif /* configENABLE_MPU */
|
||||
|
||||
msr psplim, r2 /* PSPLIM = r2. */
|
||||
msr psp, r1 /* PSP = r1. */
|
||||
|
||||
load_ctx_therad_mode:
|
||||
bx lr
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
SecureContext_SaveContextAsm:
|
||||
/* pxSecureContext value is in r0. */
|
||||
mrs r1, ipsr /* r1 = IPSR. */
|
||||
cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
|
||||
mrs r1, psp /* r1 = PSP. */
|
||||
|
||||
#if ( configENABLE_FPU == 1 )
|
||||
vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */
|
||||
vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
mrs r2, control /* r2 = CONTROL. */
|
||||
stmdb r1!, {r2} /* Store CONTROL value on the stack. */
|
||||
#endif /* configENABLE_MPU */
|
||||
|
||||
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
|
||||
movs r1, #0 /* r1 = securecontextNO_STACK. */
|
||||
msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
|
||||
msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
|
||||
|
||||
save_ctx_therad_mode:
|
||||
bx lr
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
END
|
||||
@ -0,0 +1,217 @@
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Copyright 2015, 2022 NXP */
|
||||
/* */
|
||||
/* NXP Confidential. This software is owned or controlled by NXP and may only */
|
||||
/* be used strictly in accordance with the applicable license terms. */
|
||||
/* By expressly accepting such terms or by downloading, installing, */
|
||||
/* activating and/or otherwise using the software, you are agreeing that you */
|
||||
/* have read, and that you agree to comply with and are bound by, such */
|
||||
/* license terms. If you do not agree to be bound by the applicable license */
|
||||
/* terms, then you may not retain, install, activate or otherwise use the */
|
||||
/* software. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/** \file
|
||||
* Software LLCP Link layer Component of Reader Library Framework.
|
||||
* $Author$
|
||||
* $Revision$ (v07.10.00)
|
||||
* $Date$
|
||||
*
|
||||
* History:
|
||||
* KK: Generated 14. April 2015
|
||||
*
|
||||
*/
|
||||
|
||||
#include <ph_Status.h>
|
||||
#include <ph_RefDefs.h>
|
||||
#include <phlnLlcp.h>
|
||||
|
||||
#ifdef NXPBUILD__PHLN_LLCP_SW
|
||||
|
||||
#include "phlnLlcp_Sw.h"
|
||||
#include "phlnLlcp_Sw_Int.h"
|
||||
#include "phlnLlcp_Sw_Mac.h"
|
||||
|
||||
phStatus_t phlnLlcp_Sw_Int_Socket_SendInt(phlnLlcp_Transport_Socket_t* psSocket,
|
||||
uint8_t* pTxBuffer,
|
||||
uint32_t dwLength,
|
||||
uint16_t wFrameOpt,
|
||||
uint8_t bState)
|
||||
{
|
||||
phTools_Q_t * PH_MEMLOC_REM psMsgQueue = NULL;
|
||||
uint32_t PH_MEMLOC_REM dwBlockTime = 0xFFFFFFFFU;
|
||||
phStatus_t PH_MEMLOC_REM wStatus = PH_ERR_SUCCESS;
|
||||
phOsal_TimerPeriodObj_t timePeriodToWait;
|
||||
phStatus_t bRetstatus;
|
||||
|
||||
timePeriodToWait.unitPeriod = OS_TIMER_UNIT_MSEC;
|
||||
timePeriodToWait.period = PHOSAL_MAX_DELAY;
|
||||
|
||||
/* Just forward the buffer data to LLCP context using LLCP Queue mechanism.
|
||||
* Get the Queue */
|
||||
psMsgQueue = phTools_Q_Get(dwBlockTime, PH_OFF);
|
||||
|
||||
if (psMsgQueue == NULL)
|
||||
{
|
||||
return (PH_ERR_RESOURCE_ERROR | PH_COMP_LN_LLCP);
|
||||
}
|
||||
psMsgQueue->pbData = pTxBuffer;
|
||||
psMsgQueue->dwLength = dwLength;
|
||||
|
||||
/* Send the Queue */
|
||||
psMsgQueue->wFrameOpt = wFrameOpt;
|
||||
psMsgQueue->pSender = (void *)psSocket;
|
||||
psMsgQueue->bType = PH_TOOLS_Q_DATA_TO_BE_SENT;
|
||||
psSocket->bState = bState;
|
||||
PH_CHECK_SUCCESS_FCT(wStatus, phTools_Q_Send(psMsgQueue, dwBlockTime, wFrameOpt));
|
||||
|
||||
/* Check for PHLN_LLCP_NO_MORE_FRAG and block on Queue(Semaphore) to be sent */
|
||||
if((wFrameOpt == PH_TRANSMIT_DEFAULT) || (wFrameOpt == PH_TRANSMIT_BUFFER_LAST))
|
||||
{
|
||||
/* Block on Semaphore until it gets a new remote connection. */
|
||||
PH_CHECK_SUCCESS_FCT(bRetstatus, phOsal_SemPend(&psSocket->xSema.SemHandle, timePeriodToWait));
|
||||
|
||||
wStatus = psSocket->wStatus;
|
||||
}
|
||||
return PH_ADD_COMPCODE(wStatus, PH_COMP_LN_LLCP);
|
||||
}
|
||||
|
||||
phStatus_t phlnLlcp_Sw_Int_Pdu_CcOrC(phlnLlcp_Transport_Socket_t *psSocket,
|
||||
uint8_t bPtype,
|
||||
uint8_t *pServiceName,
|
||||
uint8_t bSnLength
|
||||
)
|
||||
{
|
||||
uint16_t PH_MEMLOC_REM wLength = 0;
|
||||
uint8_t PH_MEMLOC_REM baPdu[12];
|
||||
phStatus_t PH_MEMLOC_REM wStatus;
|
||||
uint16_t PH_MEMLOC_REM wLMiu;
|
||||
|
||||
/* Frame the connect Or CC PDU */
|
||||
wLength = phlnLlcp_Sw_Int_Pdu_FrameHeader(bPtype, psSocket->bRsap, psSocket->bLsap, 0, 0, baPdu);
|
||||
|
||||
baPdu[wLength++] = PHLN_LLCP_TLV_TYPE_MIUX;
|
||||
baPdu[wLength++] = PHLN_LLCP_TLV_LENGTH_MIUX;
|
||||
|
||||
wLMiu = (uint16_t)((psSocket->dwBufLen > PHLN_LLCP_MIU) ? PHLN_LLCP_MIU: psSocket->dwBufLen);
|
||||
wLMiu -= 128u;
|
||||
|
||||
baPdu[wLength++] = (uint8_t)((wLMiu & 0xFF00U) >> 8U);
|
||||
baPdu[wLength++] = (uint8_t)(wLMiu & 0xFFU);
|
||||
|
||||
if((psSocket->bRsap == 0x01U) && (bPtype == PHLN_LLCP_PTYPE_CONNECT))
|
||||
{
|
||||
baPdu[wLength++] = PHLN_LLCP_TLV_TYPE_RW;
|
||||
baPdu[wLength++] = PHLN_LLCP_TLV_LENGTH_RW;
|
||||
baPdu[wLength++] = PHLN_LLCP_TLV_RW_VALUE;
|
||||
|
||||
/* Add SN to TLV bytes sent during Connect PDU. */
|
||||
baPdu[wLength++] = PHLN_LLCP_TLV_TYPE_SN;
|
||||
baPdu[wLength++] = bSnLength;
|
||||
|
||||
wStatus = phlnLlcp_MacTransmit(PH_TRANSMIT_BUFFER_FIRST, baPdu, wLength);
|
||||
if(wStatus != PH_ERR_SUCCESS)
|
||||
{
|
||||
return wStatus;
|
||||
}
|
||||
|
||||
wStatus = phlnLlcp_MacTransmit(PH_TRANSMIT_BUFFER_LAST, pServiceName, bSnLength);
|
||||
}
|
||||
else if (bPtype == PHLN_LLCP_PTYPE_CONNECT)
|
||||
{
|
||||
baPdu[wLength++] = PHLN_LLCP_TLV_TYPE_RW;
|
||||
baPdu[wLength++] = PHLN_LLCP_TLV_LENGTH_RW;
|
||||
baPdu[wLength++] = PHLN_LLCP_TLV_RW_VALUE;
|
||||
|
||||
wStatus = phlnLlcp_MacTransmit(PH_TRANSMIT_DEFAULT, baPdu, wLength);
|
||||
}
|
||||
else
|
||||
{
|
||||
wStatus = phlnLlcp_Sw_Int_HandleMsgQueue(baPdu, wLength, (uint8_t)PH_TOOLS_Q_DATA_TO_BE_SENT);
|
||||
|
||||
/* Change the socket state from Connect pending to Info Exchange */
|
||||
psSocket->bState = PHLN_LLCP_SOCKET_INFO_EX;
|
||||
}
|
||||
return wStatus;
|
||||
}
|
||||
|
||||
phStatus_t phlnLlcp_Sw_Int_Pdu_Frmr(phlnLlcp_Transport_Socket_t *psSocket,
|
||||
uint8_t bPtype,
|
||||
uint8_t bLsap,
|
||||
uint8_t bRsap,
|
||||
uint8_t bSeq,
|
||||
uint8_t bReason,
|
||||
uint8_t bSend)
|
||||
{
|
||||
uint8_t PH_MEMLOC_REM baFrmr[6];
|
||||
uint16_t PH_MEMLOC_REM wLength;
|
||||
|
||||
wLength = phlnLlcp_Sw_Int_Pdu_FrameHeader(PHLN_LLCP_PTYPE_FRMR, bRsap, bLsap, 0, 0, baFrmr);
|
||||
|
||||
baFrmr[wLength++] = ((uint8_t)(bReason << 4U) | (uint8_t)bPtype);
|
||||
baFrmr[wLength++] = bSeq;
|
||||
baFrmr[wLength++] = (psSocket->sSeq.bSendState_Vs << 4U) | psSocket->sSeq.bRxState_Vr;
|
||||
baFrmr[wLength++] = (psSocket->sSeq.bSendAck_Vsa << 4U) | psSocket->sSeq.bRxAck_Vra;
|
||||
|
||||
if (bSend == PH_OFF)
|
||||
{
|
||||
return phlnLlcp_Sw_Int_HandleMsgQueue(baFrmr, wLength, (uint8_t)PH_TOOLS_Q_DATA_TO_BE_SENT);
|
||||
}
|
||||
else
|
||||
{
|
||||
return phlnLlcp_MacTransmit(PH_TRANSMIT_DEFAULT, baFrmr, wLength);
|
||||
}
|
||||
}
|
||||
|
||||
phStatus_t phlnLlcp_Sw_Int_Pdu_DiscOrDm(phlnLlcp_Transport_Socket_t *psSocket,
|
||||
uint8_t bPtype,
|
||||
uint8_t bReason)
|
||||
{
|
||||
uint16_t PH_MEMLOC_REM wLength;
|
||||
uint8_t PH_MEMLOC_REM pDiscPdu[4];
|
||||
|
||||
/* Frame the Disconnect pdu */
|
||||
wLength = phlnLlcp_Sw_Int_Pdu_FrameHeader(bPtype, psSocket->bRsap, psSocket->bLsap, 0, 0, (uint8_t *)pDiscPdu);
|
||||
|
||||
if(bPtype == PHLN_LLCP_PTYPE_DISC)
|
||||
{
|
||||
return phlnLlcp_MacTransmit(PH_TRANSMIT_DEFAULT, pDiscPdu, wLength);
|
||||
}
|
||||
else
|
||||
{
|
||||
pDiscPdu[wLength++] = bReason;
|
||||
}
|
||||
return phlnLlcp_Sw_Int_HandleMsgQueue(pDiscPdu, wLength, (uint8_t)PH_TOOLS_Q_DATA_TO_BE_SENT);
|
||||
}
|
||||
|
||||
phStatus_t phlnLlcp_Sw_Int_Pdu_Snl(uint8_t bTid, uint8_t bSap)
|
||||
{
|
||||
uint16_t PH_MEMLOC_REM wLength;
|
||||
uint8_t PH_MEMLOC_REM pSnlPdu[6];
|
||||
|
||||
/* Frame the Disconnect pdu */
|
||||
wLength = phlnLlcp_Sw_Int_Pdu_FrameHeader(PHLN_LLCP_PTYPE_SNL, 0x01, 0x01, 0, 0, (uint8_t *)pSnlPdu);
|
||||
|
||||
pSnlPdu[wLength++] = PHLN_LLCP_TLV_TYPE_SDRES;
|
||||
pSnlPdu[wLength++] = PHLN_LLCP_TLV_LENGTH_SDRES;
|
||||
pSnlPdu[wLength++] = bTid;
|
||||
pSnlPdu[wLength++] = bSap;
|
||||
|
||||
return phlnLlcp_Sw_Int_HandleMsgQueue(pSnlPdu, wLength, (uint8_t)PH_TOOLS_Q_DATA_TO_BE_SENT);
|
||||
}
|
||||
|
||||
phStatus_t phlnLlcp_Sw_Int_Pdu_RrOrRnr(phlnLlcp_Transport_Socket_t *psSocket,
|
||||
uint8_t bPtype)
|
||||
{
|
||||
uint16_t PH_MEMLOC_REM wLength;
|
||||
uint8_t PH_MEMLOC_REM pResPdu[3];
|
||||
|
||||
wLength = phlnLlcp_Sw_Int_Pdu_FrameHeader(bPtype, psSocket->bRsap, psSocket->bLsap, psSocket->sSeq.bRxState_Vr,
|
||||
0, pResPdu);
|
||||
|
||||
psSocket->sSeq.bRxAck_Vra = psSocket->sSeq.bRxState_Vr;
|
||||
|
||||
return phlnLlcp_Sw_Int_HandleMsgQueue(pResPdu, wLength, (uint8_t)PH_TOOLS_Q_DATA_TO_BE_SENT);
|
||||
}
|
||||
|
||||
#endif /* NXPBUILD__PHLN_LLCP_SW */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user